skristiansson/wb_sdram_ctrl — pull request #6 by fjullien (2014-05-17 21:03:26+00:00)
Title: wb_port_arbiter: fix cache coherency during wb block write

Multiples write can occur during a single write block cycle.

Old code triggers a buffer write on the rising edge of wb_cyc.
This only works with single write cycles.

This patch signals that a write have happend to all ports
on every wb_ack during the write block cycle.

Signed-off-by: Franck Jullien