ucb-bar/chisel — pull request #193 by donggyukim (2014-04-19 23:06:11+00:00)
Title: Vtests

New Verilog genHarness implementation supporting multi clock domains.

Basic usage: compile verilog with the following options.
--genHarness: generate the harness. By default, it does not contain the API interpreter.
--compile: compile the test harness using VCS.
--test: generate the harness containing the API interpreter and run the manual tester.
--vcd: generate the VCD dump of selected signals.
--debug: generate the VPD dump of all signals. It overrides the --vcd option.