ucb-bar/chisel — pull request #185 by palmer-dabbelt (2014-04-10 02:55:30+00:00)
Title: Fix VCD dumps

WIRE__prev was not getting set during the first cycle's VCD dump,
which can result in inconsistent VCD dumps. Essentially the idea is
that if your circuit has a wire that starts as non-zero and becomes
zero after the first cycle, the VCD dump will never reflect this
change.