susematz/qemu — pull request #7 by twocode (2014-03-27 05:42:41+00:00)
Title: The checkin adds support for msr instruction operating nzcv register and fixes the wrong behavior of tst instruction.

##### 1. decoding msr instruction for *nzcv* operations.
According to P.248 to P.249, when *msr* instruction is used for **accessing special-purpose registers**, `Op0 == 0b11, CRn == 0b0100`. As *fpcr* is also accessible at EL0 when such conditions are met. So `CRm == 4` should be excluded where *fpcr* will be the target register.
The values supposed to set the *nzcv* values are [31:28] of the source register.
##### 2. wrong behavior of *tst* instruction
*tst* instruction is correctly decoded but incorrectly handled when working in 32-bit regsize mode. Only low 32 bits should be anded and referred to the n value in pstate.

*Tested and verified with instruction tests and syscall tests.*