Xilinx/XilinxTclStore — pull request #216 by ronagyl (2014-03-24 15:49:22+00:00)
Title: Added filtering capability for the check_cdc_paths proc 

The change makes available the option to skip from the analysis the asynchronous reset paths.
The reset signals are not always synchronized to the destination clock, usually a false path is applied on them.
The proc should not encourage this design practice, just sometimes we want to put aside these paths and concentrate on the real crossings.