buserror-uk/simavr — pull request #68 by bsekisser (2014-03-22 12:41:26+00:00)
Title: sim_core: fix rcall instruction cycles...

Based on the instrtiming.elf code and checking the Avr Instruction
Manual, RCALL was found to be producing incorrect cycle counts.

Atmega; 3, 16-bit pc; 4, 22-bit pc.

Fixed accordingly.

modified: sim/sim_core.c