buserror-uk/simavr — pull request #59 by bsekisser (2014-03-05 15:23:36+00:00)
Title: sim_core: Fix for issue #46, correction to ld {rXYZ}

User supplied test seems to indicate that the avr writes data to
the destination register AFTER updating the index register.
whereas the core originally read the index register and
immediately stored the result into the register and then wrote
back the index register.

If the code used: LD XH, X test indicated XH would return the
value loaded from the indirect load operation versus the updated
XH:XL value as the core originally assumed.

modified: sim/sim_core.c