openrisc/orpsoc-cores — pull request #33 by jjts (2014-01-22 17:38:31+00:00)
Title: A Verilator testbench

This are the files of a basic verilator testbench.

It should be easy to merge as it consists of a single new system folder: de0_nano_sim. I think it is has value to merge this system now and make it prettier later.

This system is similar to the de0_nano board system where the SDRAM controller was replaced with a memory model.

NOTE: both ram_wb_b3.v ram_and ram_wb.v components are needed. Using only ram_wb_b3.v as in or1200-generic results in erratic behavior, especially bad with gdb.

Quite a few files have been copied and patched from Orpsoc V2. The JtagServer class is new but inspired in jtag_vpi.

This was tested stand alone:

```
vlt:
orpsoc sim --force --sim verilator de0_nano_sim -f /home/jts/sandbox/bld-orpsoc/sw/hello -d
```

And tested with or1k-eld-gdb via openocd.

Compile openocd:
```
./configure --enable-jtag_vpi --enable-adv_debug_sys --enable-maintainer-mode --no-create --no-recursion && make
```

Makefile snippet:

```
vlt:
orpsoc sim --force --sim verilator de0_nano_sim -f /home/jts/sandbox/bld-orpsoc/sw/hello -j

openocd-sim:
sed 's/VJTAG/MOHOR/' ../openocd/tcl/board/or1k_generic.cfg > or1k_generic.cfg
../openocd/src/openocd -f ../openocd/tcl/interface/jtag_vpi.cfg -f ./or1k_generic.cfg
```

Verilator model output:

```
Starting ORPSoc Verilator cycle accurate simulation...
Preparing to launch JTAG server...
Launching JTAG Server...Connecting the JTAG server module...
Connecting the UART testbench module...
* Loading program from /home/jts/sandbox/bld-orpsoc/sw/hello
* Section: .vectors,* vaddr: 0x00000000,* paddr: 0x0* offset: 0x00002000,* size: 0x00002000
* Section: .init,* vaddr: 0x00002000,* paddr: 0x2000* offset: 0x00004000,* size: 0x00000028
* Section: .text,* vaddr: 0x00002028,* paddr: 0x2028* offset: 0x00004028,* size: 0x0000eb68
* Section: .fini,* vaddr: 0x00010b90,* paddr: 0x10b90* offset: 0x00012b90,* size: 0x0000001c
* Section: .rodata,* vaddr: 0x00010bac,* paddr: 0x10bac* offset: 0x00012bac,* size: 0x00000688
* Section: .eh_frame,* vaddr: 0x00013234,* paddr: 0x13234* offset: 0x00013234,* size: 0x00000050
* Section: .ctors,* vaddr: 0x00013284,* paddr: 0x13284* offset: 0x00013284,* size: 0x00000008
* Section: .dtors,* vaddr: 0x0001328c,* paddr: 0x1328c* offset: 0x0001328c,* size: 0x00000008
* Section: .jcr,* vaddr: 0x00013294,* paddr: 0x13294* offset: 0x00013294,* size: 0x00000004
* Section: .data,* vaddr: 0x00013298,* paddr: 0x13298* offset: 0x00013298,* size: 0x00000a38
Running Jtag Server...
Listening on port 5555
Waiting for client connection...ok
hello, world 100 10 100
```

OpenOCD output:
```
Open On-Chip Debugger 0.8.0-dev-00294-gbc256b1-dirty (2014-01-22-10:19)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : Set server port to 5555
Info : Set server address to 127.0.0.1
Info : mohor tap selected
Info : adv debug unit selected
Info : Option 1 is passed to adv debug unit
adapter speed: 3000 kHz
Info : Connection to 127.0.0.1 : 5555 succeed
Info : This adapter doesn't support configurable speed
Info : JTAG tap: or1200.cpu tap/device found: 0x149511c3 (mfg: 0x0e1, part: 0x4951, ver: 0x1)
Warn : JTAG tap: or1200.cpu UNEXPECTED: 0x149511c3 (mfg: 0x0e1, part: 0x4951, ver: 0x1)
Error: JTAG tap: or1200.cpu expected 1 of 1: 0x14951185 (mfg: 0x0c2, part: 0x4951, ver: 0x1)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
Info : adv debug unit is configured with option ADBG_USE_HISPEED
Halting processor
target state: halted
Chip is or1200.cpu, Endian: big, type: or1k
Target ready...
Info : accepting 'gdb' connection from 3333
Warn : acknowledgment received, but no packet pending
```

GDB output:
```
GNU gdb (GDB) 7.6.50.20130930-cvs
Copyright (C) 2013 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=or1k-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
.
Find the GDB manual and other documentation resources online at:
.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from hello...done.
(gdb) target remote :3333
Remote debugging using :3333
0x0000276c in or1k_cache_init ()
(gdb) set remotetimeout unlimited
(gdb) load
Loading section .vectors, size 0x2000 lma 0x0
Loading section .init, size 0x28 lma 0x2000
Loading section .text, size 0xeb68 lma 0x2028
Loading section .fini, size 0x1c lma 0x10b90
Loading section .rodata, size 0x688 lma 0x10bac
Loading section .eh_frame, size 0x50 lma 0x13234
Loading section .ctors, size 0x8 lma 0x13284
Loading section .dtors, size 0x8 lma 0x1328c
Loading section .jcr, size 0x4 lma 0x13294
Loading section .data, size 0xa38 lma 0x13298
Start address 0x100, load size 72912
Transfer rate: 2 KB/sec, 5608 bytes/write.
(gdb) l 1
1	#include
2
3	int foo(int a, int b){
4	int c;
5	c = a*100/b;
6	return c;
7	}
8
9
10	int
(gdb)
11	main(void)
12	{
13
14	int a = 2;
15	int b = 3;
16
17	int c, d, e;
18
19	c = a + b;
20
21	d = c * a;
22
23	e = foo(a, b);
24
25	//scanf("%d", &b);
26
27	printf("hello, world %d %d %d\n", c, d);
28	return 0;
29	}
(gdb) b 23
Breakpoint 1 at 0x23dc: file hello.c, line 23.
(gdb) b 27
Breakpoint 2 at 0x23f0: file hello.c, line 27.
(gdb) c
Continuing.

[Remote target] #1 stopped.
0x000023e0 in main () at hello.c:23
23	e = foo(a, b);
(gdb) s

[Remote target] #1 stopped.
0x00002354 in foo (a=10, b=3) at hello.c:5
5	c = a*100/b;
(gdb) c
Continuing.

[Remote target] #1 stopped.
0x000023f4 in main () at hello.c:27
27	printf("hello, world %d %d %d\n", c, d);
(gdb) n

[Remote target] #1 stopped.
main () at hello.c:28
28	return 0;

```

NOTE: I also ran Icarus with this system and notice a few verilog core files need patches, which I will send soon for your comments. Do you have the same experience?

NOTE: I don't like the system of patches associated with orpsoc-cores. It would be better if the cores were individually available from github, and we could submit pull requests directly to their repos.

NOTE: If the move to github happens it would be nice of the cores are re-released with the OHDL licenses as my experience in the semiconductor IP market really tells me that using GPL licenses for hardware is a drag. Any thoughts?