hrydgard/ppsspp — pull request #4484 by unknownbrackets (2013-11-09 16:49:11+00:00)
Title: Implement some more ops in armjit (divu, lwl, lwr, msub, msubu)

The ugliest part is lwl/lwr. It's still better than flushing all regs, but it's not entirely pretty... couldn't find a good way to do it without temporaries so I kinda forced the issue. It's not so bad.

The unsigned division code might not be ideal, but it works fine, and it doesn't have to flush out all regs to mem.

These ops were showing up in profiles so this gets rid of them. Still have div...

-[Unknown]