openrisc/orpsoc-cores — pull request #6 by skristiansson (2013-09-19 06:42:04+00:00)
Title: wb_intercon_gen instantiation template

The following changes since commit 2d7ab8e54bec5656735e04054c03669833defaf4:

wb_intercon: Add wb_intercon generator (2013-09-18 11:38:52 +0200)

are available in the git repository at:

https://github.com/skristiansson/orpsoc-cores.git for-openrisc

for you to fetch changes up to bbf235ac205e456be15c37407b676d464de32724:

or1200-generic: use wb_intercon_gen template header file (2013-09-19 09:33:37 +0300)

----------------------------------------------------------------
Stefan Kristiansson (2):
wb_intercon: add generation of instantiation template
or1200-generic: use wb_intercon_gen template header file

cores/wb_intercon/sw/verilogwriter.py | 9 ++--
cores/wb_intercon/sw/wb_intercon_gen | 33 ++++++++++++--
systems/or1200-generic/bench/verilog/orpsoc_top.v | 121 ++++----------------------------------------------
systems/or1200-generic/bench/verilog/wb_intercon.vh | 101 +++++++++++++++++++++++++++++++++++++++++
systems/or1200-generic/data/wb_intercon.conf | 11 +++++
systems/or1200-generic/or1200-generic.core | 1 +
6 files changed, 155 insertions(+), 121 deletions(-)
create mode 100644 systems/or1200-generic/bench/verilog/wb_intercon.vh
create mode 100644 systems/or1200-generic/data/wb_intercon.conf