openrisc/orpsoc-cores — pull request #5 by skristiansson (2013-09-17 02:45:46+00:00)
Title: cores: updates and additions

The following changes since commit 03277939d200cd49aa1eb6dd598dd2bcb1fa7123:

cores: add simple 8-bit gpio core (2013-09-14 23:29:08 +0300)

are available in the git repository at:

https://github.com/skristiansson/orpsoc-cores.git for-openrisc

for you to fetch changes up to 7ed67cfd8260cfd3c55523cdca670c5c1d220662:

cores: add wishbone to avalon bridge core (2013-09-17 05:34:12 +0300)

----------------------------------------------------------------
Stefan Kristiansson (3):
cores/mor1kx: use 'version' instead of deprecated 'branch' option
cores: add diila - Device Independent Integrated Logic Analyzer core
cores: add wishbone to avalon bridge core

cores/diila/diila.core | 13 +++++++++++
cores/mor1kx/mor1kx.core | 2 +-
cores/wb_avalon_bridge/verilog/wb_to_avalon_bridge.v | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
cores/wb_avalon_bridge/wb_avalon_bridge.core | 7 ++++++
4 files changed, 104 insertions(+), 1 deletion(-)
create mode 100644 cores/diila/diila.core
create mode 100644 cores/wb_avalon_bridge/verilog/wb_to_avalon_bridge.v
create mode 100644 cores/wb_avalon_bridge/wb_avalon_bridge.core