sulir/edigen — pull request #14 by vbmacher (2012-09-09 17:51:45+00:00)
Title: Allow to force definition of subrule pattern manually

Following our last email discussion from 7.9. I was still facing to several problems with rules ambiguity, good definition of disassembler formats and it looked horrible unclear when reading the specification file - due various "workarounds" needed for edigen satisfaction.

Therefore, I got an idea how it can be improved, at least temporarily - you can possibly change it later. If some rules are going to be ambiguous, you can explicitly define so called "pre-pattern" - manual forward definition of subrule pattern, such as this:

```
instr =
"rlc": 000111 | "rrc": 001111 | "ral": 010111 | "rar": 011111 | "nop": 000000 |
"ldax": 0 ldax_bc_de[01](2) 010 | "ldax" : 0 ldax_bc_de[11](2) 010 ;

ldax_bc_de =
"BC": 01 | "DE": 11;
```

The `[]` denotes pattern definition for a subrule. Edigen will "trust" to the pattern ultimately and this is a threat, because the "pre-pattern" does not have to correspond to real pattern of the subrule. Therefore, it is not very good solution and it should be solved later.

It is up to you either to accept it, or not. Or, better we can discuss this and I can potentionally fix this according to some consensus...