scj7t4/FREEDM — pull request #87 by scj7t4 (2012-09-08 03:51:26+00:00)
Title: Clock synchronizer improvement

With respect to Issue 84 and Issue 85, could you test these changes and what behavior they have with respect to forming groups with PSCAD simulations?

This has an experimental change to use an entirely new scheme for getting the phases in lock step and I am not entirely sure what behaviors we will observe.

I suggest using `git merge --squash` to bring this in btw