mxcl/homebrew — pull request #12785 by saperant (2012-06-12 16:05:41+00:00)
Title: Added formula for Verilator

Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not
test-bench code!), plus some PSL, SystemVerilog and Synthesis
assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is
especially well suited to generate executable models of CPUs for
embedded software design teams.