krasin/llvm-dcpu16 — pull request #82 by drak3 (2012-04-09 17:00:54+00:00)
Title: Changed output of [0+Reg] to [Reg]

Currently in the readme example assembler output there is the following line:
SET [0+C], 0 ; The Notch order
The [0+C] is somewhat problematic as the "official" assembler noted in the readme does not understand this expression, and even if assemblers understand [0+C] it is very likely that they translate it to [Reg+Nextword] which is one one cycle slower and one word longer (kind of micro-optimization though, but it looks cleaner anyway)
I've fixed this in the InstrPrinter but I'm not sure if this is the right place to do so.