petersry/EECE4730-5730-Class-Project — pull request #7 by pspillane (2011-11-08 09:06:04+00:00)
Title: Memory and I/O files

I have added my group's VHDL files and documentation to my fork. The README file was just for learning how to add a file to my fork.

I did not include any Xilinx projects, since I figured that a lot of the space in this repository would be wasted with files that could easily be generated by Xilinx. Each component (RAM, ROM, and the register file) were given separate projects, and each test file was in the same directory/project as the component being tested.