ska-sa/mlib_devel — Issue #1: 10GbE v2 synchronous resets
Author: jmanley
Created: 2012-02-09 07:34:08+00:00
State: open

The 10GbE v2 core uses asynchronous resets of the fifos (Xilinx default, I believe). For this to work reliably, we must ensure that no data is being clocked into the interface at the time of the reset. This makes it a bit awkward to use; we'd like to be able to issue a reset at any time. I think if we changed it to be a synchronous reset, this problem might go away.