ispc/ispc — Issue #132: Improve gather/scatter code by using x86 scale by 2/4/8s
Author: mmp
Created: 2011-12-06 22:38:39+00:00
State: open
Labels: performance

When we do gather/scatter in the base ptr+ offsets case, the addressing calculation is basically:

```
vector multiply of offset by element size
foreach lane
compute pointer as base + offset
load/store
```

For the case where the element size is 2, 4, or 8, we'd like take advantage of the free scale by 2/4/8 in the x86 address calculation ops. It should be pretty straightforward to update one of the gather/scatter optimizations to do this; the trick is to emit a pattern that LLVM identifies. Early experiments suggest that for the i32 offset case, the key is to sext to i64 first, then do a scalar multiply by 2/4/8, then gep with base address and the offset before the load/store.