cospan/Sycamore_FPGA — Issue #3: Add the capability to add parameters to the configuration file
Author: cospan
Created: 2011-12-01 05:04:45+00:00
State: open

'parameters' within Verilog allow a for a large degree of flexibility within an already written core. 'Parameters' are core specific so as apposed to a 'define' which will be a global define for every core.

I believe that a good place in the configuration file will be within the slave braces.

What needs to be modified is the gen_top.py file, the parameters would be added when the core is instantiated. It would be good if the parameter values could verify that they are indeed within in a core instead of blindly declaring them