ku-fpg/kansas-lava — Issue #1: Invalid VHDL generated
Author: uschoepp
Created: 2011-11-12 20:07:55+00:00
State: open

When I try the following simple example, then I get VHDL-code that does not compile with XilinX ISE 13.1:

{-# LANGUAGE TypeFamilies, ScopedTypeVariables #-}

module Main where
import Language.KansasLava
import Hardware.KansasLava.Boards.Spartan3e
import Data.Sized.Ix
import Data.Sized.Matrix

type U4 = Matrix X4 Bool
type U8 = Matrix X8 Bool

example :: (sig ~ Signal c) => sig U4 -> sig U8
example =
funMap (\s ->
let b i = if s!i then 1 else 0
n = b 0 + 2 * (b 1) + 4 * (b 2) + 8 * (b 3)
in Just $ matrix [n == x | x<-[1..8]])

test_leds :: Fabric ()
test_leds = do sw <- switches
leds (unpackMatrix $ example (packMatrix sw))

main = do
kleg <- reifyFabric test_leds
writeVhdlCircuit "main" "main.vhd" kleg
writeUCF "main.ucf" kleg
writeVhdlPrelude "Lava.vhd"

The offending line in the generated VHDL-code is:

sig_6_o0 <= sig_7_o0(to_integer(unsigned(lava_to_std_logic(sig_8_o0(3)) & lava_to_std_logic(sig_8_o0(2)) & lava_to_std_logic(sig_8_o0(1)) & lava_to_std_logic(sig_8_o0(0)))));

The error message is:

Expression in type conversion to unsigned has 4 possible definitions in this scope, for example, SIGNED and UNSIGNED.

If I replace unsigned(...) by unsigned'(...), then the VHDL-code works as expected.