casper-astro/hdl_devel — Issue #4: Mux primitive needs a MyHDL model/converter
Author: ruriktherus
Created: 2011-11-10 03:29:43+00:00
State: open
Labels: primitives

This should work similar to the [counter model](http://github.com/casper-astro/hdl_devel/blob/master/libraries/primitives/counter/counter.py) and insert an instantiation of the mux primitive when converted to Verilog.