petdance/scratch — Issue #24: ptr_alignment 8 not honored, sparc 64bit broken
Author: petdance
Created: 2011-11-01 05:26:47+00:00
State: open
Labels: bug, core, Pri-minor, Sev-low

Sparc 64bit with strict ptr_alignment=8 breaks when reading frozen pmc's because of misalignment.

Any 64bit big-endian cpu with strict alignment is broken without '''-xmemalign=4s''' (the immediate workaround)
The default for all v9 architectures is '''-xmemalign=8s'''.

However, our goal should be to allow fast aligned code and not to skip this with a compiler relaxement.

{{{
t@1 (l@1) stopped in PF_fetch_integer at line 1076 in file "pf_items.c"
1076 ASSERT_ARGS(PF_fetch_integer)
(dbx) step
t@1 (l@1) stopped in PF_fetch_integer at line 1078 in file "pf_items.c"
1078 if (!pf || pf->fetch_iv == NULL)
(dbx) print *(*stream)
**stream = 4
(dbx) step
t@1 (l@1) stopped in PF_fetch_integer at line 1079 in file "pf_items.c"
1079 return *(*stream)++;
(dbx) print *(*stream)
**stream = 4
(dbx) step
t@1 (l@1) signal BUS (invalid address alignment) in PF_fetch_integer at line 1079 in file "pf_items.c"
1079 return *(*stream)++;
(dbx) print *(*stream)
**stream = 35
(dbx) print *stream
*stream = 0x100000dec
}}}

'''0x100000dec''' is not properly aligned. It must be '''0x100000df0'''.

Sparc cc manpage:[[BR]]
-xmemalign[=] Controls memory alignment, ={1|2|4|8|16}, b={f|i|s}.[[BR]]
Accepted values for b are:[[BR]]
i Interpret access and continue execution.[[BR]]
s Raise signal SIGBUS. [[BR]]
f For variants of -xarch=v9 only. [reduced i] [[BR]]

Thanks to Rolf Grossmann for coming up with all this info and debugging, and to Andy Dougherty for correcting my wrong first analysis.

The fix for 1.0 will be a hints file update to add -xmemalign=4s to cc_flags, the goal for 2.6 will be a --64bitcompat argument to parrot to create 8-byte aligned values on 32-bit, not 4-byte as now.