chemeris/UHD-Fairwaves — comment on commit 18f19a044f61ee2491ccd3b4a756538d24228160
File:  line 0
By chemeris:

Changes looks much cleaner now, thanks!

So, what is the current way with those coregen files? Does original files give correct timing? I'm sorry for asking stupid questions, as I have little knowledge about FPGA programming.