chemeris/UHD-Fairwaves — comment on commit 18f19a044f61ee2491ccd3b4a756538d24228160
File: fpga/usrp2/control_lib/s3a_icap_wb.v line 76
By smunaut:

That's a bit strong ...

I agree that having a DCM buried several level down the design is a bad practice.

However having them in a sub module that encapsulate all the clocking generation and buffering nastiness is perfectly OK IMHO ... I've always done it that way and served me many times when dealing with slighly different board variants that all had the same clocking scheme.