chemeris/UHD-Fairwaves — comment on commit 18f19a044f61ee2491ccd3b4a756538d24228160
File: fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise line 15
By closehaulcom:

The Xilinx tools auto generate these files. I used ISE Version 13.3, which is more current than 12.1. The tool will create a new .xise project file when it detects a new version of the Xilinx tools. In some cases when much older versions are used, the design may not be backwards compatible (i.e., the Spartan-6 FPGA isn't supported because it's a relatively new device).