paul99/v8m-rb — comment on commit 6ad313afb9f6d158ce2a0b6628d87b05917b6d0b
File: src/mips/constants-mips.h line 50
By nemanja-lukic:

One more comment.

If we are making this changes to truly support old MIPS cores (like MIPS III) and not just make this a fix for Loongson architecture, than we should think about other possible ISA problems that may occur on real MIPS III cores. I have no board where I could verify this, but MIPS ISA clearly states on numerous places that MIPS I, II and III architectures have some limitation on how some instructions can be used. These include (among other):

CFC1 instruction:
- For the MIPS I, II and III architectures, the contents of GPR rt are UNPREDICTABLE for the instruction immediately following CFC1.
- But in some places in our codegen we use it like this (stub-cache-mips.cc):
__ cfc1(t5, FCSR);
__ srl(t5, t5, kFCSRFlagShift);

MFC1 instruction:
- For MIPS I, MIPS II, and MIPS III the contents of GPR rt are UNPREDICTABLE for the instruction immediately following MFC1.
- We use it like this (stub-cache-mips.cc):
__ mfc1(v0, f0);
// Check if the result fits into a smi.
__ Addu(a1, v0, Operand(0x40000000));

BC1T instruction:
- In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
- Here is how it is used in our codegen:
__ c(EQ, D, f12, f14);
__ bc1t(&equal);