omniomni/omni-engineering huggingface dataset:
WDC 65C134. The Western Design Center (WDC) W65C134S is an 8-bit CMOS microcontroller based on a W65C02S processor core, which is a superset of the MOS Technology 6502 processor.

The W65C134S consists of a fully static 8-bit W65C02S CPU core, 4 KB of ROM containing a machine language monitor, 192 bytes of SRAM, two 16 bit timers, one 16-bit Watch-Dog Timer (WDT) with "restart" interrupt, one UART with baud rate timer, a low power Serial Interface Bus (SIB) configured as a token passing local area network, twenty-two priority encoded interrupts, two crystal inputs (slow 32.768KHz and fast up to 8-MHz), Bus Control Register (BCR) for external memory bus control, interface circuitry for peripheral devices, and many low power features.  The W65C134S has been developed for high-reliability applications, as well as where minimum power is required.

Features
CMOS low power process 
Operating ambient temperature range of -40 °C to +85 °C
Single 2.8V to 5.5V power supply 
Static to 8 MHz clock operation, as well as 32.768KHz capability
W65C02S compatible CPU
8-bit parallel processing 
Variable length stack 
True indexing capability 
Fifteen addressing modes 
Decimal or binary arithmetic 
Pipeline architecture 
Fully static CPU 
Single chip microcomputer 
Many power saving features 
56 CMOS compatible I/O lines 
4096 x 8 ROM on chip 
192 x 8 RAM on chip 
Low power modes 
WAIt for interrupt 
SToP the clock 
Fast oscillator start and stop feature 
Twenty-two priority encoded interrupts 
BRK software interrupt 
RESET "RESTART" interrupt 
NMIB Non-Maskable Interrupt input 
SIB Interrupt 
IRQ1B level interrupt input 
IRQ2B level interrupt input 
2 timer edge interrupts 
7 positive edge interrupt inputs 
5 negative edge interrupt inputs 
Asynchronous Receiver Interrupt 
Asynchronous Transmitter Interrupt 
UART 7/8-bit w/wo odd or even parity 
16M byte segmented address space 
64K byte linear address space 
4 x 16 bit timer/counter 
Bus control register for external memory 
Internal or external ROM 
8 Decoded Chip Select outputs 
Surface mount 68 and 80 lead packages 
Real time clock features 
Time of Day (ToD) clock features

See also
 WDC 65C265 - a 16-bit microcontroller based around a WDC 65C816 processor core

References

Further reading

External links
 W65C134S webpage - Western Design Center (WDC)
 W65C134S datasheet - WDC
 W65C134S monitor ROM manual - WDC

65xx microprocessors
8-bit microprocessors
WDC 65C51. The CMOS W65C51 Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between microprocessor based systems and serial communication data sets and modems. It is produced by Western Design Center (WDC) and is a drop-in replacement for the MOS Technology 6551.

The ACIA has an internal baud rate generator, eliminating the need for multiple component support circuits. The transmitter rate can be selected under program control to be 1 of 15 different rates from 50 to 19,200 bits per second, or at 1/16 times an external clock rate. The receiver rate may be selected under program control to be either the Transmitter rate or at 1/16 times the external clock rate. The ACIA has programmable word lengths of 5, 6, 7 or 8 bits; even, odd or no parity 1, 1½ or 2 stop bits.

The ACIA is designed for maximum programmed control from the microprocessor (MPU) to simplify hardware implementation. Three separate registers permit an MPU to easily select the W65C51 operating modes, data checking parameters and determine operational status.

The command register controls parity, receiver echo mode, transmitter interrupt control, the state of the RTS line, receiver interrupt control and the state of the DTR line.

The control register controls the number of stop bits, the word length, receiver clock source and transmit/receive rate.

The status register indicates the status of the IRQ, DSR and DCD lines, transmitter and receiver data Registers, and overrun, framing and parity error conditions.

Transmitter and receiver data Registers are used for temporary data storage by the transmit and receiver circuits, each able to hold one byte.

Known bugs

The N version datasheet has a note regarding the Transmitter Data Register Empty flag:

"The W65C51N loads the Transmitter Data Register (TDR) and Transmitter Shift Register (TSR) at the same time. A delay should be used to insure that the shift register is empty before the TDR/TSR is reloaded. This feature of the W65C51N works different from earlier 6551 designs."

This means the TDRE flag cannot be relied on for flow control.

It has been reported that some W65C51 chips have the TDRE flag stuck high

References

External links
W65C51S Datasheet
W65C51N Datasheet

Input/output integrated circuits
Trampe bicycle lift. The Trampe bicycle lift () is a bicycle lift in Trondheim, Norway, invented and installed in 1993 by Jarle Wanwik.

In 2013 it was upgraded and rebranded under the name CycloCable by Skirail, part of the Poma group.

Usage 
Use of the Trampe bicycle lift is free. When using the lift, the right foot is placed on the starting point (the left foot stays on the bicycle pedal). After pushing the start button, the user is pushed forward and a footplate emerges. A common mistake among tourists and other first-time users is that they don't keep their right leg outstretched and their body tilted forward. This makes it hard to maintain balance on the footplate, and can result in falling off.

In the summer months, Trampe is used extensively by both commuting inhabitants of Trondheim as well as tourists.

References

Gallery

External links 

 Video of the lift in operation on YouTube

Norwegian inventions
Cycling in Norway
Transport in Trondheim
Elevators
Individual elevators
1993 establishments in Norway
WDC 65C265. The Western Design Center (WDC) W65C265S is a 16-bit CMOS microcontroller based on a W65C816S processor core, which is a superset of the MOS Technology 6502 processor.

The W65C265S consists of a fully static W65C816S CPU core, 8 KB of ROM containing a machine language monitor, 576 bytes of SRAM, a processor cache under software control, eight 16-bit timers with maskable interrupts, an interrupt-driven parallel bus (PIB), four universal asynchronous receiver-transmitters (UARTs), a watchdog timer that fires a restart interrupt, twenty-nine priority encoded interrupts, a time-of-day clock, two sound generators, a bus control register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power features.

Features
 Hi-Rel low power CMOS process 
 Operating ambient temperature range is 0 °C to +70 °C 
 Single 2.8 V to 5.5 V power supply 
 Static to 8 MHz clock operation, as well as 32.768KHz capability 
 W65C816S compatible CPU
 16 MB linear address space 
 Twenty-nine priority encoded interrupts 
 Four UARTS's 
 Time of Day (ToD) clock features 
 8 x 16 bit timer/counters 
 Bus Control Register 
 Many bus operating features and modes 
 8 Programmable chip select outputs 
 Low cost surface mount 84 and 100 lead packages 
 Automatically shifts speed for slow memory or peripherals

See also
 WDC 65C134 - an 8-bit microcontroller based around a WDC 65C02 processor core

References

Further reading

External links 
 W65C265S website - Western Design Center (WDC)
 W65C265S datasheet - WDC
 W65C265S monitor ROM manual - WDC

65xx microprocessors
16-bit microprocessors
David L. Tennenhouse. David Lawrence Tennenhouse (born c. 1957) is a Canadian–American computer researcher and technology executive.

Life
Tennenhouse was born about 1957 in Ottawa, Canada.
He received a bachelor's and master's degree in electrical engineering from the University of Toronto. In 1989 he completed a PhD at the University of Cambridge under advisor Roger Needham.
His dissertation was Site interconnection and the exchange architecture.
He then joined the faculty of Massachusetts Institute of Technology (MIT). 
He was chairman of the Technology and Policy Working Group of the US National Information Infrastructure Task Force at some time point.
In 1996 he became director of the Information Technology Office of the Defense Advanced Research Projects Agency (DARPA), overseeing US government research.

In 1999, he joined Intel as a director of research. 
In 2001, he founded what were sometimes called the Intel Research Lablets. One of the projects sponsored was TinyOS.
In February 2006 he became the chief executive officer of A9.com, the search subsidiary of Amazon.com, replacing Udi Manber. 
He left Amazon in September 2006. In 2007 he became a partner at the venture capital firm New Venture Partners.

In 2004, he was granted IEEE fellowship for leadership in the development of active networks.

In September 2012 he became vice president for technology policy at Microsoft.
In May 2014 he joined VMware to direct its research.

References 

Living people
Year of birth missing (living people)
Businesspeople in information technology
MIT Sloan School of Management faculty
American technology chief executives
University of Toronto alumni
Alumni of the University of Cambridge
Kegg Pipe Organ Builders. Kegg Pipe Organ Builders is a manufacturer of pipe organs based out of Hartville, Ohio, U.S.A.

The company was founded by Charles E. Kegg in 1985.  Kegg had previously worked with a number of organ building firms, including Casavant Frères.  He worked on organs of a wide variety of sizes, from four stops up to over 100 stops.

Kegg founded his own company out of a desire to provide electric action instruments that are mechanically innovative and tonally well designed.  His company's philosophy when it comes to instruments is to build organs that are "American" in character instead of copying other older styles.

Since the founding of the company, Kegg has produced over forty instruments.  His company also has been involved in restoring instruments — for example by making replacement consoles and restoring historic organs, especially Moller and Aeolian player organs and Welte Philharmonic organs.

References

External links
 Kegg Pipe Organ Builders

Pipe organ building companies
Manufacturing companies based in Ohio
Stark County, Ohio
Manufacturing companies established in 1985
Musical instrument manufacturing companies of the United States
1985 establishments in Ohio
Di-tert-butyl peroxide. Di-tert-butyl peroxide or DTBP is an organic compound consisting of a peroxide group bonded to two tert-butyl groups. It is one of the most stable organic peroxides, due to the tert-butyl groups being bulky. It is a colorless liquid.

Reactions
The peroxide bond undergoes homolysis at temperatures above 100 °C.  For this reason di-tert-butyl peroxide is commonly used as a radical initiator in organic synthesis and polymer chemistry. The decomposition reaction proceeds via the generation of methyl radicals.
(CH3)3COOC(CH3)3 → 2 (CH3)3CO•
(CH3)3CO• → (CH3)2CO + 
2  → C2H6

DTBP can in principle be used in engines where oxygen is limited, since the molecule supplies both the oxidizer and the fuel.

Safety 
DTBP is an irritant to the nose, eyes, and skin. It is also flammable, and can explode unpredictably at high (≈150 °C) temperatures.

See also
tert-Butyl hydroperoxide
Bis(trimethylsilyl) peroxide

References

External links

Organic peroxides
Fuels
Propellants
Radical initiators
Tert-butyl compounds
Uranopilite. Uranopilite is a minor ore of uranium with the chemistry (UO2)6SO4(OH)6O2·14H2O or, hydrated uranyl sulfate hydroxide.

As with many uranyl minerals, it is fluorescent and radioactive. It is straw yellow in normal light. Uranopilite fluoresces a bright green under ultraviolet light. Uranopilite contains clusters of six uranyl pentagonal bipyramids that share equatorial edges and vertices, with the clusters cross-linked to form chains by sharing vertices with sulfate tetrahedra. In uranopilite, the chains are linked directly by hydrogen bonds, as well as to interstitial H2O groups.

Uranopilite is associated with other uranyl minerals such as zippeite and johannite and, like them, is usually found as an efflorescent crust in uranium mines.

Notable occurrences include:

 Wheal Owles, Cornwall, England
 San Juan County, Utah, US
 Northwest Territories, Canada
 Bohemian region of Europe

See also 
 Uranyl sulfate
 List of minerals

References 

 Progress in Solid State Chemistry
 ATHENA MINERAL: Mineral Data

Uranium(VI) minerals
Sulfate minerals
Triclinic minerals
Minerals in space group 2
William H. Avery (engineer). William Hinckley Avery (July 25, 1912 – June 26, 2004) was an influential aeronautical engineer.  He designed the propulsion mechanism known as the ramjet, and was known for heading the Ocean Thermal Energy Conversion program which generates electricity from the temperature differential between shallow and deep ocean water.

Early years
Avery was born on July 25, 1912. After studying chemistry and physics at Harvard and working as a private research chemist, Avery turned to rocket science during World War II. He directed a division of the Allegany Ballistics Laboratory in Cumberland, Maryland, that developed solid fuels for rockets later used to launch guided missiles and spacecraft.

Ramjets
Avery moved to Johns Hopkins University in 1947 and soon became head of propulsion research at the Applied Physics Laboratory. Over the next several decades, his research laid the foundation for understanding combustion in rocket and jet engines. His group invented the propulsion system for Talos, the first surface-to-air missile to use a ramjet engine.

While at the Applied Physics Laboratory, Avery mentored Frederick S. Billig, the scramjet pioneer.

Ocean Thermal Energy Conversion
In 1973, Avery began leading the Applied Physics Laboratory's work on emerging technologies. Searching for alternative sources of energy, he helped develop the Ocean Thermal Energy Conversion program, which used the temperature difference between shallow and deep tropical seawater to generate electricity. Avery retired from the Applied Physics Laboratory in 1989.

Death
Avery died on June 26, 2004, of congestive heart failure.

References

1912 births
2004 deaths
American aerospace engineers
Harvard College alumni
20th-century American engineers
General Aviation XFA. The General Aviation XFA was an American biplane fighter aircraft built by the General Aviation Company for the United States Navy.

Development
The PW-4 was built for U.S. Navy Specification No. 96, calling for a carrier-based light fighter. This specification was eventually revealed as a cover for the Navy's actual desire for an airship fighter, the Curtiss XF9C. The XFA was a single-bay biplane with an all-metal fuselage and metal laminate skin. The construction of its fuselage was innovative in that instead of using lap jointing, the edges of each panel were bent inwards, with the rivets fastening them on the inside, instead of being visible on the surface. It had a gull-type upper wing which was fabric covered. The prototype was ordered in 1930, but the company was engaged in another reorganization, which delayed its work. Delivered for evaluations in 1932, it showed poor flying characteristics, including longitudinal instability and over-sensitive controls. General Aircraft increased the area of the tail surfaces and made other changes, then returned the prototype for more testing; but now the stability problems were worse. The plane would nose up with more throttle, but then drop its nose when the throttle was reduced. After another round of modifications, and some close calls, the plane was finally classed as unsafe and testing was abandoned.

Specifications

References

Citations

Bibliography

Lloyd S. Jones, U.S. Naval Fighters (Fallbrook CA: Aero Publishers, 1977, ), pp. 89–91

Gull-wing aircraft
General Aviation FA
Aircraft first flown in 1932
Sesquiplanes
IXL. IXL may refer to: 

 IXL, Oklahoma, a town in the USA
 IXL Historical Museum, a historic building in Hermansville, Michigan, and IXL, a brand of flooring
 Henry Jones IXL, an Australian manufacturer of jams and other foods, and IXL, a brand name
 Kushok Bakula Rimpochee Airport (IATA: IXL), in Leh, Ladakh, India
 A railway interlocking
 A gramogram for the phrase, "I excel"; see
Berliner-Joyce XFJ. The Berliner-Joyce XFJ was a United States prototype biplane fighter aircraft that first flew in May 1930. Designed by Berliner-Joyce Aircraft for the United States Navy, its lower wing, placed below the fuselage and just two feet above the ground, apparently gave it a tendency to ground loop when landing, and it was never ordered for production.

Development and design
Berliner-Joyce had been formed in 1929, and had won a contract with the United States Army for the Berliner-Joyce P-16 aircraft.  At the same time, they submitted a similar design to the Navy, modified to meet the differing requirements, which included a metal-skinned semi-monocoque fuselage, shoulder-mounted upper wings and a lower wing underslung on cabane-type struts.

The prototype, XFJ-1, was sent to Anacostia for testing after its initial flights, where the ground-looping habit was noted, and eventually resulted in a landing accident, necessitating return and repair. The company took the opportunity to add a Townend ring engine cowling, and upgraded the engine from a 450-hp Pratt & Whitney R-1340C to a 500-hp R-1340-92 Wasp. This and other improvements boosted speed from 177 to 193 mph, and the Navy gave the reconstructed aircraft the designation XFJ-2.  However, improved performance came at the expense of stability, and the ground loop problem persisted, and there was no interest in continuing with this design. Nevertheless, the prototype continued to be used for other tests for several years.

Specifications (XFJ-1)

References

Further reading

External links

 Berliner-Joyce XFJ-1 — AeroWeb: The Aviation Enthusiast Corner (includes an image)

F1J
Berliner-Joyce F1J
Single-engined tractor aircraft
Carrier-based aircraft
Zharchikhite. Zharchikhite is a halide mineral, a hydroxyl fluoride of aluminium; formula AlF(OH)2. It forms colourless, transparent crystals.  Discovered in 1968, it is named after its original locality, the Zharchinskoya Deposit, which is in Buryatia, Russia.

References

Webmineral - Zharchikhite

Aluminium minerals
Fluorine minerals
Monoclinic minerals
PurVIEW. PurVIEW is an integrated image display and viewing plug-in software package that incorporates stereoscopic viewing technology for ESRI ArcGIS 9 (or later version). Essentially, PurVIEW is a photogrammetry-based data capture workstation that extend the ArcGIS environment. It converts Arc- desktops into precise stereo-viewing windows for geo-referenced aerial or space-borne imagery. Digitizing features directly yields positional accuracy comparable with photogrammetric mapping.

Using ArcMap, geodatabase contents can be directly accessed and reviewed superimposed on standard geo-referenced 3-dimensional image models, revealing errors and omissions, or natural changes. 

PurVIEW's creators, International Systemap, are working with ESRI to develop seamless software integration for the 2010 release of ArcGIS 9.4. 

PurVIEW is suitable for a number of professional fields, such as mapping, geomatics, geology, forestry and mining.

External links
http://www.purview.com/
http://www.mypurview.com/
https://web.archive.org/web/20091016095055/http://www.esricanada.com/EN_products/7098.asp

Image processing software
GIS software
Perrone Robotics. Perrone Robotics is a robotics software company based out of Charlottesville, Virginia and formed in 2001. The company formed Team Jefferson as a low budget side project in 2004 to build an autonomous robotic dune buggy for participation in the 2005 DARPA Grand Challenge. The company was at the 2006 JavaOne conference with their robotic dune buggy 'Tommy' and received a Duke Award in the emerging technology category for Tommy & MAX. 

The company has reformed Team Jefferson to participate in the 2007 DARPA Urban Challenge with partners such as Fair-Isaac Corporation, Sun Microsystems, and the University of Virginia.

The CEO spoke at the Consumer Electronics Show (CES) 2007 in Las Vegas describing the emerging consumer robotics market and how to 'roboticize' consumer products .

References

External links
www.perronerobotics.com

Robotics companies of the United States
Diphenyl oxalate. Diphenyl oxalate (trademark name Cyalume) is a solid whose oxidation products are responsible for the chemiluminescence in a glowstick. This chemical is the double ester of phenol with oxalic acid. Upon reaction with hydrogen peroxide, 1,2-dioxetanedione is formed, along with release of the two phenols. The dioxetanedione then reacts with a dye molecule, decomposing to form carbon dioxide and leaving the dye in an excited state. As the dye relaxes back to its unexcited state, it releases a photon of visible light.

The reaction rate is pH dependent, and slightly alkaline conditions, achieved by adding a weak base, such as sodium salicylate, give a faster reaction and therefore produce brighter light.
The 2,4,6-trichlorophenol ester is a solid and thus easier to handle. Furthermore, since trichlorophenolate is the better leaving group, the reaction will proceed faster, again producing brighter light, as compared to the phenol ester.

The following colors can be produced by using different dyes:

References

Oxalate esters
Chemiluminescence
Phenol esters
Power-on reset. A power-on reset (PoR, POR) generator is a microcontroller or microprocessor peripheral that generates a reset signal when power is applied to the device. It ensures that the device starts operating in a known state.

PoR generator 
In VLSI devices, the power-on reset (PoR) is an electronic device incorporated into the integrated circuit that detects the power applied to the chip and generates a reset impulse that goes to the entire circuit placing it into a known state.

A simple PoR uses the charging of a capacitor, in series with a resistor, to measure a time period during which the rest of the circuit is held in a reset state.  A Schmitt trigger may be used to deassert the reset signal cleanly, once the rising voltage of the RC network passes the threshold voltage of the Schmitt trigger.  The resistor and capacitor values should be determined so that the charging of the RC network takes long enough that the supply voltage will have stabilised by the time the threshold is reached.

One of the issues with using an RC network to generate a PoR pulse is the sensitivity of the R and C values to the power-supply ramp characteristics. When the power supply ramp is rapid, the R and C values can be calculated so that the time to reach the switching threshold of the Schmitt trigger is enough to apply a long enough reset pulse. When the power-supply ramp itself is slow, the RC network tends to get charged up along with the power-supply ramp up. So when the input Schmitt stage is all powered up and ready, the input voltage from the RC network would already have crossed the Schmitt trigger point. This means that there might not be a reset pulse supplied to the core of the VLSI.

Power-on reset on IBM mainframes 
On an IBM mainframe, a power-on reset (POR) is a sequence of actions that the processor performs either due to a POR request from the operator or as part of turning on power. The operator requests a POR for configuration changes that cannot be recognized by a simple System Reset.

See also
 Low-voltage detect
 Oscillator start-up timer
 Power-up timer (PWRT), similar to a watchdog timer

References

Embedded systems