A companion publication to an opamp based Nv neuron architecture paper, this publication explores the use of inexpensive mouse optical sensors for shape recognition as polygons from line recognition networks, in sensor and two motor fusion in a TOMU/WOMU circuit using the SPI bus and a master -slave architecture. Lie Computability, is defined on discrete Tensor architectures, similar to computation on fields, in future work, field computing is proven to have the same complexity as integer lattices, though Lie Lattices embeddings in integer and complex lattices, proving MFA I and II architectures are equivalent in complexity, in both analog and digital worlds. Keywords: Tensor Flow, Tensor Architectures, Unsupervised Learning, Emergent A.I , procedural A.I, MFA I and II architectures, neuromodulation, MCU, SoC , TOMU/WOMU, SPI bus. What: We consider inexpensive 18 by 18 matrix 64 gray levels SPI interface, based photodetector components of optical mice. In this paper we consider the use of the SPI interface for the use of a master slave system of interface of an MCU to the optic processor for creating of BEAM circuitry using inexpensive MCU circuitry, such as the TOMU/WOMU. How: MFA I and MFA II architectures are fulfilled in both digital and analog circuitry, with a network architecture defined by a tensor notation, as described in a companion paper. Why: A digital fulfilment of a tensor architecture is defined and compared to Lego Mindstorm based deep learning and procedural algorithms for semantic segmentation and classification algorithms. ​ Octagon ​ : Exclusively used for Stop. ​ Equilateral Triangle ​ (One point down): Exclusively used for Yield. ​ (Mark n.d.) Introduction. In a previous paper on opamp based Nv neuron topologies, ​ (Kumar 2020) ​ we have presented semantic segmentation networks, in continuation of this series, is this paper on the use of digital MCU based architectures for tensor nets of Nv neurons. Problem Definition. Given a Line L in a Background B, there exists a circuit of Nv Neurons [Nv], for semantic segmentation to objects defined by the shape. [Hexagon, Triangle]. We define a Nv neuron for line segmentation and a set of neurons [Nv] for shape segmentation, one for hexagons, He=[Nv] and T = [Nv] for triangle segmentation. The circuit graph of a Nv Neuron as denoted in CaC is an opamp(in+,in-, out), impedence_mux_i, i = 1 to 4 , impedence_mux_opamp+(in, out), impedence_mux_opamp-(in,out), imepdence_feedback+(in,out) and impedence_feedback-(in,out). The circuit graph is straightforward from these elements with the impedance being a complex value with a multiplexed hard wired control bus, [in+,in-,fb+,fb-], with various values for various circuit topologies. Amplification differential amplification uses negative feedback with gain and bandwidth tradeoffs, while positive feedback leads to a whole universe of noise based computing and signal theory (S/N ratio) in two port analysis, of dynamical systems, with stable orbits called oscillations ,leading to stability theorems definable as the basis of a BEAM operating system. ​ (Bheemaiah, n.d.) Small signal analysis of two port networks is incomplete in its role in BEAM circuit design, needing large signal analysis, and dynamical systems theory, of stochastic partial differential equations in computable field theory or embeddings in lattices of integers or complex numbers. Hence there is persistence, memory and computability in circuits, analogous to asymptotics and polynomial time definitions of field and lattice based computing. This generalization is in Lie Algebraic definitions of the lattices, in D4 in E8 species called Lie Computability. Background. Much of line detection circuitry stems from neurobiology research, which supports formal art element theory of the atomicity of line as form and structure in the neurophysiology of cognition, with support for the existence of circuits for line segmentation and for shape by yet not understood mechanisms. While modern circuit theory is very distant from phenomenology in biological circuitry, a similar architecture is created as a non invasive animal model. Thus robotics serves as viable animal models for much of non-invasive 3R’s research. Speculation on cognition as more of preceptory mechanisms, rather than anatomical hard-wiring, is from hypothetical plastic reconfigurable circuitry in perception from lines. This circuitry is Tensor based and either discrete or continuous and represented in a tensor calculus on [NvH] and [NvT]. Topology. A tensor definition of the circuit follows from many layers , [S] sensors, [NvL] the line detection layer, [NvH] the hexagon detection layer and [NvT] the triangle detection layer. (S ∘ ) ↔(NvL)↔ 1.0 (NvL ⊕ )↔(NvH)↔ 1.1 (NvL ⊕ )↔(NvT)↔ 1.2 1.0 represents multi sensor fusion, with line detection by a neuro-modulation system as a binary or a soliton/cw based coding as an event indicator. The bus is represented by similar integrative nonlinear functions, between sets of line detectors of various configurations and Nv neurons for the emergent computation of semantic detection of polyhedra. The emergence is of concavity of the detection of spatial coherence in six lines and three lines respectively. Binary or CW/soliton neuro-modulation of the output, indicates categories of ‘perception’ as emergent A.I in the circuitry. Nv Neurons and SPI bus. “A Synchronous Solution SPI works in a slightly different manner. It's a "synchronous" data bus, which means that it uses separate lines for data and a "clock" that keeps both sides in perfect sync. The clock is an oscillating signal that tells the receiver exactly when to sample the bits on the data line. This could be the rising (low to high) or falling (high to low) edge of the clock signal; the datasheet will specify which one to use. When the receiver detects that edge, it will immediately look at the data line to read the next bit (see the arrows in the below diagram). Because the clock is sent along with the data, specifying the speed isn't important, although devices will have a top speed at which they can operate (We'll discuss choosing the proper clock edge and speed in a bit). One reason that SPI is so popular is that the receiving hardware can be a simple ​ shift register ​ . This is a much simpler (and cheaper!) piece of hardware than the full-up UART (Universal Asynchronous Receiver / Transmitter) that asynchronous serial requires. ​ (“Serial Peripheral Interface (SPI) - Learn.sparkfun.com” n.d., “Serial Peripheral Interface (SPI) - Learn.sparkfun.com” n.d.) Receiving Data You might be thinking to yourself, self, that sounds great for one-way communications, but how do you send data back in the opposite direction? Here's where things get slightly more complicated. In SPI, only one side generates the clock signal (usually called CLK or SCK for Serial ClocK). The side that generates the clock is called the "master", and the other side is called the "slave". There is always only one master (which is almost always your microcontroller), but there can be multiple slaves (more on this in a bit). When data is sent from the master to a slave, it's sent on a data line called MOSI, for "Master Out / Slave In". If the slave needs to send a response back to the master, the master will continue to generate a prearranged number of clock cycles, and the slave will put the data onto a third data line called MISO, for "Master In / Slave Out". Notice we said "prearranged" in the above description. Because the master always generates the clock signal, it must know in advance when a slave needs to return data and how much data will be returned. This is very different than asynchronous serial, where random amounts of data can be sent in either direction at any time. In practice this isn't a problem, as SPI is generally used to talk to sensors that have a very specific command structure. For example, if you send the command for "read data" to a device, you know that the device will always send you, for example, two bytes in return. (In cases where you might want to return a variable amount of data, you could always return one or two bytes specifying the length of the data and then have the master retrieve the full amount.) Note that SPI is "full duplex" (has separate send and receive lines), and, thus, in certain situations, you can transmit and receive data at the same time ​ (for example, requesting a new sensor reading while retrieving the data from the previous one). Your device's datasheet will tell you if this is possible. Slave Select (SS) There's one last line you should be aware of, called SS for Slave Select. This tells the slave that it should wake up and receive / send data and is also used when multiple slaves are present to select the one you'd like to talk to. The SS line is normally held high, which disconnects the slave from the SPI bus. (This type of logic is known as “active low,” and you’ll often see used it for enable and reset lines.) Just before data is sent to the slave, the line is brought low, which activates the slave. When you're done using the slave, the line is made high again. In a ​ shift register ​ , this corresponds to the "latch" input, which transfers the received data to the output lines. Multiple slaves There are two ways of connecting multiple slaves to an SPI bus: 1. In general, each slave will need a separate SS line. To talk to a particular slave, you'll make that slave's SS line low and keep the rest of them high (you don't want two slaves activated at the same time, or they may both try to talk on the same MISO line resulting in garbled data). Lots of slaves will require lots of SS lines; if you're running low on outputs, there are ​ binary decoder chips ​ that can multiply your SS outputs. 2. On the other hand, some parts prefer to be daisy-chained together, with the MISO (output) of one going to the MOSI (input) of the next. In this case, a single SS line goes to ​ all ​ the slaves. Once all the data is sent, the SS line is raised, which causes all the chips to be activated simultaneously. This is often used for daisy-chained shift registers and ​ addressable LED drivers ​ . Note that, for this layout, data overflows from one slave to the next, so to send data to any one ​ slave, you'll need to transmit enough data to reach ​ all ​ of them. Also, keep in mind that the ​ first ​ piece of data you transmit will end up in the ​ last ​ slave. This type of layout is typically used in output-only situations, such as driving LEDs where you don't need to receive any data back. In these cases you can leave the master's MISO line disconnected. However, if data does need to be returned to the master, you can do this by closing the daisy-chain loop (blue wire in the above diagram). Note that if you do this, the return data from slave 1 will need to pass through ​ all ​ the slaves before getting back to the master, so be sure to send enough receive commands to get the data you need. Programming for SPI Many microcontrollers have built-in SPI peripherals that handle all the details of sending and receiving data, and can do so at very high speeds. The SPI protocol is also simple enough that you (yes, you!) can write your own routines to manipulate the I/O lines in the proper sequence to transfer data. (A good example is on the ​ Wikipedia SPI page ​ .) If you're using an Arduino, there are two ways you can communicate with SPI devices: 1. You can use the ​ shiftIn() ​ and shiftOut() ​ commands. These are software-based commands that will work on any group of pins, but will be somewhat slow. 2. Or you can use the ​ SPI Library ​ , which takes advantage of the SPI hardware built into the microcontroller. This is vastly faster than the above commands, but it will only work on certain pins. You will need to select some options when setting up your interface. These options must match those of the device you're talking to; check the device's datasheet to see what it requires. ● The interface can send data with the most-significant bit (MSB) first, or least-significant bit (LSB) first. In the Arduino SPI library, this is controlled by the ​ setBitOrder() ​ function. ● The slave will read the data on either the rising edge or the falling edge of the clock pulse. Additionally, the clock can be considered "idle" when it is high or low. In the Arduino SPI library, both of these options are controlled by the ​ setDataMode() ​ function. ● SPI can operate at extremely high speeds (millions of bytes per second), which may be too fast for some devices. To accommodate such devices, you can adjust the data rate. In the Arduino SPI library, the speed is set by the ​ setClockDivider() ​ function, which divides the master clock (16MHz on most Arduinos) down to a frequency between 8MHz (/2) and 125kHz (/128). ● If you're using the SPI Library, you must use the provided SCK, MOSI and MISO pins, as the hardware is hardwired to those pins. There is also a dedicated SS pin that you can use (which must, at least, be set to an output in order for the SPI hardware to function), but note that you can use any other available output pin(s) for SS to your slave device(s) as well. ● On older Arduinos, you'll need to control the SS pin(s) yourself, making one of them low before your data transfer and high afterward. Newer Arduinos such as the Due can control each SS pin automatically as part of the data transfer; see the ​ Due SPI documentation page ​ for more information.” ​ (“Website” n.d.) Sensory Motor Integration. In an MFA I architecture, behaviors define the network topology, we have two behaviors for a two motor model [M] and a 18 by 18 sensor [S] on the SPI bus. The behaviors are: isOctohedron->stop() isTriangle->keepLane() Given a sensor and motor as multiple slaves, the neuro modulation is binary and could be extended to PCM for motor control. But soliton or other dynamical systems based controls are not possible with a digital bus. Lego mindstorms identify color and identify shapes. (LEGO Education n.d.) ​ describes a Lego based curriculum for the use of color and line sensing using simple edge detection and thresholds of light and color intensities. TensorFlow, a software to execute tensor architectures is available on the EV3, and can execute the tensor topology defined above, in equations 1.0., 1.1 and 1.2. A deep learning topology also can be defined in an BEAM architecture of Nv neurons as Tensor elements. An example is a simple semantic segmentation deep network using a rnn or cnn architecture. Given a training set of traffic signs, it can be trained to create the behaviours needed, namely stop() and LaneKeeping() for an octahedral and triangular detection. SImple procedural transformation functions for polygon segmentation from line detection, ​ (“[No Title]” n.d.) ​ Ferreira et.al define, a minimum cyclic graph detection from lines, instead of emergence in an ROI. DETECT-POLYGONS(Ψ) 1 G ← COMPUTE-INDUCED-GRAPH(Ψ) 2 Γ ← MINIMUM-CYCLE-BASIS(G) 3 Θ ← POLYGONS-FROM-CYCLES(Γ) 4 return Θ (“UOR_7.2.4” n.d.) ​ defines the intersection algorithm for a set on n lines. (Contributors to Wikimedia projects 2008) Bentley–Ottmann algorithm ​ is a ​ sweep line algorithm ​ for listing all ​ crossings ​ in a set of line segments ​ . Discussion. A digital computing based MFA I architecture is described for simple behaviors, with a tensor based topology for polygon shape detection from line detection, algorithms using edge detection or line segmentation tensor architectures. A number of autopilot systems have dedicated cameras for traffic sign, recognition, though a legal framework for autopilot system architecture is yet to be developed. Tesla’s autopilot system, and most other HAV systems have dedicated cameras for traffic sign interpretation using deep learning, and Mapillary is a semantic segmentation with geotag service for the smooth transition to a HAV world of automation. We have thus developed , two different approaches to Nv Neuron based MFA I architectures, one using analog and discrete components and the second based on operating systems and the use of data buses and MCUs. The meta nature of control theory, emergent A.I , and Tensor based representations in E8, with Lie computability is thus proven independent of the fulfilment mechanisms of tensor formulations and complexity definitions. Lambda circuits and oscillators are as inherent in MCU and SoC integrations as are in purely analog formulations. Future Work. Future work involves the definition of Lie Computability for much of Tensor based topologies, including Nv Neuron based topologies, for either a hard wired or a plastic topology of circuitry for behaviour driven architectures. GIven the plasticity of a digital implementation, or analog neuromorphic circuits, ​ (Chang, Yang, and Lu 2013; Azghadi, Moradi, and Indiveri 2013) (neuromem n.d.) ​ (“Intel Neuromorphic Research Community” n.d.) ​ the reconfiguration as a hyper operating system for MFA I or BEAM architectures is to be explored. The use of these topologies in 3R’s and art therapy is also explored.