V850. V850 is a 32-bit RISC CPU architecture produced by Renesas Electronics for embedded microcontrollers. It was designed by NEC as a replacement for their earlier NEC V60 family, and was introduced shortly before NEC sold their designs to Renesas in the early 1990s. It has continued to be developed by Renesas .

The V850 architecture is a load/store architecture with 32 32-bit general-purpose registers. It features a compressed instruction set with the most frequently used instructions mapped onto 16-bit half-words.

Intended for use in ultra-low power consumption systems, such as those using 0.5 mW/MIPS, the V850 has been widely used in a variety of applications, including optical disk drives, hard disk drives, mobile phones, car audio, and inverter compressors for air conditioners. Today, microarchitectures primarily focus on high performance and high reliability, such as the dual-lockstep redundant mechanism for the automotive industry; and the V850 and RH850 families are comprehensively used in cars.

The V850/RH850 microcontrollers are also used prominently on non-Japanese automobile marques such as Chevrolet, Chrysler, Dodge, Ford, Hyundai, Jeep, Kia, Opel, Range Rover, Renault and Volkswagen Group brands.

Overview

The V850 is the trademark name for a 32-bit RISC CPU architecture for embedded microcontrollers of Renesas Electronics Corporation. It was originally developed and manufactured by NEC Corporation in the early 1990s
(the copyright mark for the microcode on the package shows 1991) as a branch of the V800 Series
and is still being evolved today.

Its base-architecture has been succeeded by the V850 family variants, named V850E, V850E1, V850ES,
V850E1F, V850E2, V850E2M, V850E2S, and the RH850 family (V850E2M, V850E2S, and V850E3) CPU cores.

Many compilers and debuggers are available from various development tool vendors.

Real-time operating systems are provided by compiler vendors.

In-circuit emulators (ICE) are provided by many vendors. Legacy proven pod-based types—the JTAG-based N-Wire interface with the N-trace type, and the Nexus interface with the Aurora Trace type—are available.

Application systems

The first V850 CPU core was used in many DVD drives manufactured by NEC's and Sony's Optiarc (later wholly owned by Sony).
NEC Electronics (currently Renesas Electronics) itself intensively developed application-specific standard products (ASSPs) for SCOMBO Series optical disk drives.
This first generation of processor core was also used for hard disk drives manufactured by Quantum Corporation (see photo).

In 1997, the V850/xxn product line started with the V850/SA1
and the V850/SV1
and expanded its application to ultra-lo-power products such as "handy camcorders."
It has a main and sub internal oscillator amplifier working from 1.8 V to 3.6 V with external crystal or ceramic resonator.
Software STOP mode, whose internal watch timer operates with a 32.768 kHz sub-oscillator, typically consumes only 8μA of electrical current.
In 1998, NEC launched the V850/SB1,
with IEBus controller, for car audio, an ultra-low-power (3.6 mW@5 V/MIPS) and ultra-low-noise (EMI/EMS) 5 V product.
The V850/SC1
was also for car audio.
These strategic product line expansions succeeded in increasing the number of devices sold.

This first generation of the V850 core is also used for some NEC mobile phones.
It is also used for the programmable-host CPUs of some small form factor GSM/GPRS mobile devices with GPS embedded modem modules.

In the next phase, NEC targeted the automotive industry with a CAN bus controller based on the V850,
as the V850/SF1.
Later on, the automotive industry became the main target of the V850 and RH850.

The V850E core was targeted at system-on-a-chip (SoC) applications as well as standard products,
and was used for some Japanese domestic mobile phones, including Sony Mobile's and NEC's.
V850E and V850ES are also used in air conditioning inverter compressors.
At this stage, another mass market was its use in car audio.
The V850ES core succeeded in the low-power embedded-product line,
and is ISA-compatible with the V850E.
NEC Electronics (currently, Renesas Electronics) adopted the V850 CPU core for its USB 3.0 controllers.

Around 2005, several companies started a feasibility study for the FlexRay controller on the V850E platform. Yokogawa Digital Computer (currently DTS INSIGHT) developed an evaluation board named GT200 with a V850E/IA1 and a field-programmable gate array (FPGA), which employs the FlexRay controller developed by Bosch.

The V850E2 core primarily targeted automotive areas,
but was also used for NEC's mobile phones.

The V850 family line up (based on V850E, V850ES, and V850E2 cores) and the Renesas RH850 family (based on the V850E3 core, as of 2018) are mainly employed in automotive applications as well as inter-equipment connectivity and motor-control specific microcontroller units (MCUs).

Trademark strategy

The V850 is a unregistered trademark but not a registered one.
NEC once applied for a trademark to be registered with the Japan Patent Office, but it was rejected,
as it was a natural extension of the series number.
However, this action has been enough to prevent other people or organizations from registering it as a trademark. In addition, Renesas has been using the V850X/xxn type trademark, such as V850E/MA1, for more than 20 years, because the combination of one alphabetical with two numerical characters cannot be granted as a registered trademark. It is thus free to use without registration.

One exception is V850E/PHO3 (PHOENIX 3, or PHOENIX-FS).
Another usage of PHOENIX 3 by Renesas Electronics is the COOL PHOENIX 3, which employs the ARM Cortex-M0 core.
PHOENIX 3 is a registered trademark of the 3DO Company as USPTO Reg. 2,009,119.

According to current Renesas Electronics documentation, at least the following strings are regarded as its trademark: "V800 Series", "V850 family", "V850/SA1", "V850/SB1", "V850/SB2", "V850/SF1", "V850/SV1", "V850E/MA1", "V850E/MA2", "V850E/IA1", "V850E/IA2", "V850E/MS1", "V850E/MS2", "V851", "V852", "V853", "V854", "V850", "V850E", and "V850ES".

Because the V850 trademark has been used for more than 20 years, most people do not know that the RH850 family is based on an extension of the V850 instruction set architecture, and has backward compatibility with V850, V850E, V850ES, and V850E2. The RH850 is consequently thought of as being without the legacy software compatibility of the V850.

Development methodology

Because the V850 family
was developed as a branch of the V800 series,
the basic CPU architecture is inherited from the V810.
The instruction set architecture of the first V850 is drastically modified from that of the V810, but the difference is within a patch level from the GNU Compiler Collection point of view. The main purpose of this change is to implement saturation arithmetic at customers' request.

The detailed design methodology of the V810 is described in this journal.
The V850 utilizes these design assets; but the datapath logic was changed from dynamic logic to static logic, to enable 32.768 kHz real-time clock frequency operation mode.

The register-transfer level "CPU architecture design" of the V810 is developed with the Functional Description Language (FDL)
on the Falcon Simulator software, which are NEC's in-house CAD tools.
This methodology is the same as that used for the NEC V60.
In the late 1980s, the Verilog HDL had not yet been acquired by Cadence Design Systems.
FDL had been used until the middle of the 2000s, and was also used for the development of NEC's super-computer named Earth Simulator.

The difference from V60 is that the circuit diagram was written with a schematic editor, not of Calma but of Mentor Graphics, called NETED,
a part of the Design Architect product
on Apollo Computer's workstation, which was the major schematic editor at that moment.
It enabled designers to generate netlists, such as EDIF and SPICE, for LVS programs like cadence's Dracula products, and NEC's in-house Zycad netlist for logic simulation. Later on, this circuit diagram of NETED was able to generate a gate-level Verilog HDL netlist for V850.

Most of the register-transfer-level FDL netlist was translated to the gate-level schematic by hand, because the logic synthesis had not yet to be practical.
The FDL was precisely divided into datapath and random logic. For the datapath part,
the gate-level circuit diagram enabled manually repeated artwork. On the other hand, for the random logic part, logic synthesis was tried for generating gate-level schematic, but it was only about 10% of the total circuit.

In addition, formal verification was also not yet practical, which meant that full regression test by dynamic logic simulation was required for the gate-level netlist to compare with the RTL one. For gate-level logic simulation, NEC's in-house CAD tool V-SIM was usually used.
But sometimes a hardware emulator, such as Zycad LE simulation accelerator,
was used for this purpose.
(Refer to:.
In this material, the performance of Zycad LE is compared with NEC's HAL, but initial design decade differs.)

Architecture

Basic architecture

The basis of the V810 and V850 has a typical general-purpose registers-based load/store architecture.
There are 32 32-bit general-purpose registers. Register 0 (R0) is fixed as the Zero Register which always contains zero.
In the V850, R30 is implicitly used by the sld and sst instructions. 16-bit short-format load/store instructions use element pointer (ep), where the addressing mode comprises the base address register ep and immediate-operand offsets.
In V850E or later microarchitectures, R3 is implicitly used by PREPARE/DISPOSE; call stack frame creation; and unwinding instructions, as a stack pointer. Compilers' calling conventions also use R3 as the stack pointer.

The original V850 has a simple 5-stage 1-clock pitch pipeline architecture.<ref name="V810-seminar"/
This is a significant feature of reduced instruction set computers (RISCs). But the object-code size is about half that of the MIPS R3000, because the V810 and V850 adopted 16-bit and 32-bit 2-way form-length instruction formats, respectively,
and most of the frequently used instructions are mapped onto a 16-bit half-word. In other words, a 16-bit external bus width is enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipment. This concept is similar to Renesas (formerly, Hitachi) SH, ARM Thumb, and MIPS16 instruction set architectures.

In addition, the instruction set is carefully implemented. For example, to execute a function call with a Jump and (Register) Link instruction, which saves the next program counter (PC) on a register (fixed to R31 in V810), is also one of the RISC techniques to reduce the number of instructions. Return from the function can be accoomplished by jmp [Rn] (jmp [R31] in V810) instruction. Typical CISC processors use call and return instructions and push the next PC on their stack memory area.

But V810 and V850 have some microarchitecture differences. The V810 adopts a microprogram operation method for some instructions, such as floating-point arithmetic and bit string operations, while the V850 uses a one-hundred-percent hardwired control method. As a result, for example, the first V850 does not have floating-point arithmetic and bit manipulation instruction sets, including the "find first one/zero" (search 1/0; SCH1x/SCH0x), except for "set/clr/negate a bit" (SET1/CLR1/NOT1). Those extended instruction sets are revived in V850E2x extensions.

Though the V800 series adopts a RISC instruction set architecture, their assembly language is hand-coding friendly. They adopt a straightforward load/store architecture. In addition, the "interlock" mechanism, both for the data hazards and for the branch hazards, are implemented: in other words, an assembly language programmer does not need to consider any delay slots. 32 general-purpose registers provide flexibility for assembly language users. A mixture of hand-assembled codes and C language compiled codes is facilitated by using compiler options, such as "-mno-app-regs" in the Gnu Compiler Collection.

The IN instruction of the V810, which enables unsigned-load from memory-mapped I/O, was removed from the first V850s.

Detailed discussions are available in some old journals.

Instruction set extensions

The V850 series added many instruction set extensions, but all the extensions have backward compatibility.
Therefore, old binary software assets work on the new cores.

The first generation of the V850 does not have unsigned load instructions, which had been removed from the V810 (where it was implemented with IN.H and IN.B). Then, in the second generation V850E (V850E1) Series, such unsigned functionality was again added (with LD.HU and LD.BU). In addition, the V850E has some other user-friendly "CISCy" extensions, such as call table, switch,  and prepare/dispose.

In 1996, the V853 was announced as the first 32-bit RISC microcontroller with integrated flash memory.
But its maximum number of "erase and write" cycles was 16.

In 1998, NEC strategically started to expand the V850 product line, to standard, application-specific_standard_product (ASSP), application-specific integrated circuit (ASIC), and system on a chip (SoC) businesses.

In 2001, NEC launched V850ES core, which is an ultra-low-power series, but is ISA-compatible with the V850E.

Around 2001, Java Acceleration IP core for the V850 seemed to be provided to some customers as SoC,
but detailed information is only found in some patents.

In 2005, NEC Electronics introduced V850E2 core as the V850E2/ME3 product line with super-scalar architecture.

In 2009, NEC Electronics introduced V850E2M as dual-core with 2.56MIPS/MHz and 1.5 mW/MIPS.

In 2011, Renesas disclosed the SIMD extension for the V850 as V850E2H.
As for the SIMD extension, some academic studies were done.
But architectural documentation for this latest product line is disclosed to automotive customers only; it cannot be found on Renesas' website.
Its name seems to have been changed to V850E3 or G3H. The only way to know about its instruction set is to reverse engineer it with the GNU Compiler Collection.

Power consumption

The original V810 and V850 CPU architecture is designed for ultra-low power applications.

The V810 is described in detail in some journals.

According to Renesas's documentation, the power consumption of the V850ES/Jx3-L implementation is about 70% of ARM Cortex-M3.

The V810 was one of the most low-power 32-bit microcontroller products of the early 1990s. It operates at from 2.2 V to 5.5 V  with a 5 V 0.8 μm (CZ4) fabrication process.
Measured with Dhrystone MIPS, power dissipation is 500 mW at 15MIPS and 40 mW at 6 MIPS, at 5 V and 2.2 V, respectively.  This specification can be achieved both by well considered instruction-set architecture and by precisely tuned 5-stage 1-clock pitch pipeline microarchitecture, both of which are the benefit of a simplified RISC architecture.

This ultra-low-power architecture was succeeded by V850/Sxn product line, which are still being mass-produced after 20 years. Most of the improved chips are produced using a 3.3 V, 0.35μm (UC1) fabrication process, where the CPU core is precisely tuned to operate from 1.8 V to 3.6 V, working at 32.768 kHz (sub-oscillator) to 16.78 MHz (main-oscillator) with internal oscillator amplifier plus external resonator (crystal or ceramic).
Its power dissipation is 2.7 mW/MIPS at 3.3 V when made with a 0.35 μm (UC1) fabrication process, and 3.6 mW/MIPS at 5 V with a 0.35 μm (CZ6) fabrication process. "Software STOP" stand-by mode for the mask ROM version of V850/SA1, whose internal watch timer operates at 3.3 V with 32.768 kHz sub-oscillator (IDD6), consumes typically only 8 μA electrical current. Subclock normal operation mode at 3.3 V with 32.768 kHz consumes 40 μA typically, 140 μA at the maximum. (IDD5)
Its 1.8 V typical CPU operating current at 32.768 kHz might be 22 μA (40 μA ÷ 3.3 V × 1.8 V), where power dissipation should be 40 μW. It corresponds to 1.0 mW/MIPS (40 μW ÷ 0.032768 MHz ÷ 1.15 DMIPS/MHz ÷ 1000).

The V850/Sxn product line is also tuned for low noise, with both EMI and with EMS. The V850/SB1 and SB2 are especially tuned for low EMI noise with a 5 V internal voltage regulator, which facilitates high sensitivity in receiving RF for car radios.

In 2011, NEC launched the 3rd generation microarchitecture V850ES ultra-low-power series, which achieves 1.43 mW/MIPS at an operating voltage range of from 2.2 V to 2.7 V,
but this first implementation of V850ES microarchitecture seems to be incomplete compared with later generations of the same architecture.
Its "Sub-IDLE" stand-by mode for the mask ROM version of V850ES/SA2 and V850ES/SA3, whose internal RTC operate at 2.5 V with 32.768 kHz sub-oscillator (IDD6), consume typically only 5 μA electrical current. But, Subclock normal operation mode at 2.5 V with 32.768 kHz consumes typically 40 μA, 100 μA at the maximum.
Its 2.2 V typical CPU operation current at 32.768 kHz might be 31 μA (40 μA ÷ 2.5 V × 2.2 V), where power dissipation should be 68 μW. This is about 1.7 times that of V850/SA1. It corresponds to 1.6 mW/MIPS (68 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000).

The V850ES/JG3-L product line has ultra-low-power variants, the μPD70F3792, 793, and the μPD70F3841, 842. They can operate from 2.0 V to 3.6 V with typical electrical current of 18 μA at 32.768 kHz, which should be 22 μW at 2.0 V (18 μA × 2.0 V ÷ 3.3 V × 2.0 V). This corresponds to 0.52 mW/MIPS (22 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000). In addition, their sub-clock idle mode power consumption, with watch timer, should be typically 3.4 μW at 1.8 V (3.5 μA ÷ 3.3 V × 1.8 V × 1.8 V).

The power consumption of the NA85E2 (V850E2) core is much larger compared with the NU85E (V850E1) core using the same CB-12L (UX4L)
fabrication process. 
The reason is that the V850E2x core has a 128-bit instruction prefetch bus and more than one instruction prefetch queue,
while the average instruction length of the V800 series is 16 bits.
It means 16 instructions can be fetched from the memory at once, and the memory and prefetch circuits sleep fors 3 to 7 cycles for dual-pipeline superscalar architecture. 
This gap enlarges electrical current amplitude differences.
In addition, the peak electric current exceeds allowances for the voltage stabilizers of mobile gadgets.
As for V850E2M CPU core, it is publicly introduced as 1.5 mW/MIPS, 3 times that of former generations, although it should be able to take advantage of new fabrication process technologies.
Some mobile equipment avoids using dual-instruction execution (dual-pipeline superscalar), adopting the single-instruction (single-pipeline) execution setting to reduce electrical current amplitude differences.

Instruction opcode table
Each opcode (operation code) table is from User's Manual: Architecture (refer to external links.).

V810 (obsoleted) 

1st map opcodes

 All opcodes (operation codes) of the hardwired control operation are contained within the first 16-bit half-word of an instruction, from the most significant bit (MSB). A 64-word depth ROM structure with branch condition code table is enough for decoding hardware. If a 16-bit literal operand is required, it is located in the second half-word. Microprogram control operations, bit strings, and floating-point arithmetic instructions are also located in the second 16-bit half-word. As a result, all the instructions have 16-bit and 32-bit 2-way form length. Unsigned load form memory mapped I/O is implemented as the In instruction. Arithmetic and logical instructions are not fully, but relatively, orthogonal.
 The V810 does not have saturation arithmetic instructions, but 1 additional instruction in format II, such as SAT which checks flags (Overflow, Sign, Zero, and Half-word) and rewrites the specified register, might be enough both for signed and unsigned, and for word and half-word, arithmetic operations.

{| class="wikitable" style="text-align:center;font-size: 80%"
|-
! style="width:100px" | Bit [12:10][15:13, 9]
! style="width:100px" | 000
! style="width:100px" | 001
! style="width:100px" | 010
! style="width:100px" | 011
! style="width:100px" | 100
! style="width:100px" | 101
! style="width:100px" | 110
! style="width:100px" | 111
! style="width:150px" | Format
|-
! 000 X
| MOV  || ADD  || SUB  || CMP  || SHL  || SHR  || JMP  || SAR  || rowspan="2" | I(R,r)
|-
! 001 X
| MUL  || DIV  || MULU || DIVU || OR   || AND  || XOR  || NOT
|-
! 010 X
| MOV  || ADD  || SETF || CMP  || SHL  || SHR  ||      || SAR  || rowspan="2" | II(imm5,r)
|-
! 011 X
| TRAP || RETI || HALT ||      || LDSR || STSR ||      || Bit str.
|-
! rowspan="3" | 100 0100 1
| colspan="8" | Bcond || rowspan="3" |III(disp9)
|-
| BV    || BZ/BE  || BN(BS) || BLT || BNV     || BNZ/BNE || BP(BNS)  || BGE
|-
| BC/BL || BNH    || BR || BLE || BNC/BNL || BH      || NOP || BGT
|-
! 101 X
| MOVEA|| ADDI || JR   || JAL  || ORI  || ANDI || XORI || MOVHI|| IV/V
|-
! 110 X
| LD.B || LD.H ||      || LD.W || ST.B || ST.H ||      || ST.W || VI(disp16[R],r)
|-
! 111 X
| IN.B || IN.H || CAXI || IN.W || OUT.B|| OUT.H|| Float || OUT.W|| VI/VII
|-
|}
 NOP is an alias of Non-BR.

V850 (1st Gen.) 

 1st map opcodes

{| class="wikitable" style="text-align:center;font-size: 80%"
|-
! style="width:100px" | Bit [7:5][10:8]
! style="width:100px" | 000
! style="width:100px" | 001
! style="width:100px" | 010
! style="width:100px" | 011
! style="width:100px" | 100
! style="width:100px" | 101
! style="width:100px" | 110
! style="width:100px" | 111
! style="width:150px" | Format
|-
! 000
| MOV  || NOT  || DIVH  || JMP  || style="background: yellow;" | SATSUBR
| style="background: yellow;" | SATSUB || style="background: yellow;" | SATADD || MULH || rowspan="2" | I(R,r)
|-
! 001
| OR   || XOR  || AND  || TST  || SUBR || SUB  || ADD || CMP
|-
! 010
| MOV || style="background: yellow;" | SATADD  || ADD || CMP || SHR  || SAR  || SHL || MULH  ||  II(imm5,r)
|-
! 011
| colspan="4" | SLD.B || colspan="4" | SST.B || IV(disp7[ep],r)
|-
! 100
| colspan="4" | SLD.H || colspan="4" | SST.H || IV(disp8[ep],r)
|-
! 101
| colspan="4" | Bit[0] SLD.W / SST.W || colspan="4" | Bit[3:0] Bcond || IV/III
|-
! 110
| ADDI || MOVEA || MOVHI|| style="background: yellow;" | SATSUBI|| ORI  || XORI || ANDI || MULHI|| VI(disp16[R],r)
|-
! 111
| LD.B || 2nd Map || ST.B || 2nd Map || colspan="2" | JARL
| Bit[15:14]SET1/NOT1/CLR1/TST1 || 2nd MapExtension || V/VII/VIII
|-
|}
 NOP is an alias of MOV R0,R0.

 2nd map opcodes

{| class="wikitable" style="text-align:center;font-size: 80%"
|-
! style="width:100px" | Bit [23:21]
! style="width:100px" | 000
! style="width:100px" | 001
! style="width:100px" | 010
! style="width:100px" | 011
! style="width:100px" | 100
! style="width:100px" | 101
! style="width:100px" | 110
! style="width:100px" | 111
! style="width:150px" | Format
|-
! [16] !! colspan="8" | 1st Map  Bit[10:5]=111001 !!
|-
! 0
| colspan="8" | LD.H || VII
|-
! 1
| colspan="8" | ST.H || VII
|-
! [16] !! colspan="8" | 1st Map  Bit[10:5]=111011 !!
|-
! 0
| colspan="8" | LD.W || VII
|-
! 1
| colspan="8" | ST.W || VII
|-
! [26:24] !! colspan="8" | 1st Map  Bit[10:5]=111111 !!
|-
! 000
| SETF || LDSR || STSR || undef || SHR  || SAR  || SHL  || undef || IX(R,r)
|-
! 001
| TRAP  || HALT || RETI || 1st Map Bit[15:13]EI/DIundef
| colspan="4" | Illegal instruction || X
|-
! 01X
| colspan="8" rowspan="1" | Illegal instruction || rowspan="1" | —
|-
! 1XX
| colspan="8" rowspan="1" | Illegal instruction || rowspan="1" | —
|-
|}

V850E/E1/ES 
 1st map opcodes

{| class="wikitable" style="text-align:center;font-size: 80%"
|-
! style="width:100px" | Bit [7:5][10:8]
! style="width:100px" | 000
! style="width:100px" | 001
! style="width:100px" | 010
! style="width:100px" | 011
! style="width:100px" | 100
! style="width:100px" | 101
! style="width:100px" | 110
! style="width:100px" | 111
! style="width:150px" | Format
|-
! rowspan="4" | 000
| rowspan="1" |  —† || rowspan="4" | NOT  || SWITCH || JMP
| ZXB || SXB || ZXH || SXH || I(R,r0)
|-
| rowspan="3" | MOV    || DBTRAP
| rowspan="3" | Bit[4]SLD.BU/SLD.HU || rowspan="3" | SATSUBR
| rowspan="3" | SATSUB || rowspan="3" | SATADD || rowspan="3" | MULH
| I(R0,r31) / IV
|-
| undef || I(R0,r) / IV
|-
| DIVH || I(R,r) / IV
|-
! 001
| OR   || XOR  || AND  || TST  || SUBR || SUB  || ADD || CMP || I(R,r)
|-
! rowspan="2" | 010
| colspan="2" | CALLT || rowspan="2" | ADD || rowspan="2" | CMP
| rowspan="2" | SHR   || rowspan="2" | SAR || rowspan="2" | SHL || undef  || II(imm5,r0)
|-
| MOV || SATADD || MULH || II(imm5,r)
|-
! 011
| colspan="4" | SLD.B || colspan="4" | SST.B || IV(disp7[ep],r)
|-
! 100
| colspan="4" | SLD.H || colspan="4" | SST.H || IV(disp8[ep],r)
|-
! 101
| colspan="4" | Bit[0] SLD.W / SST.W || colspan="4" | Bit[3:0] Bcond
| IV/III(disp9)
|-
! rowspan="2" | 110
| rowspan="2" | ADDI || Bit[15:11]MOV(r=0)
| colspan="2" | Bit[15:11]DISPOSE(r=0)
| rowspan="2" | ORI  || rowspan="2" | XORI || rowspan="2" | ANDI || Bit[15:11]undef
| rowspan="2" | VI(imm16,R,r)/VI(imm32,R)/XIII
|-
| MOVEA || MOVHI || STASUBI || MULHI
|-
! 111
| LD.B || 2nd Map || ST.B || colspan="3" | 2nd Map
| Bit[15:14]SET1/NOT1/CLR1/TST1 || 2nd Map
| VII(disp16[R],r)/VIII(imm3,disp16[R])
|-
|}
 † NOP is an alias of MOV R0,R0.

 2nd map opcodes

{| class="wikitable" style="text-align:center;font-size: 80%"
|-
! style="width:100px" | Bit [23:21][16, 26:24]
! style="width:100px" | 000
! style="width:100px" | 001
! style="width:100px" | 010
! style="width:100px" | 011
! style="width:100px" | 100
! style="width:100px" | 101
! style="width:100px" | 110
! style="width:100px" | 111
! style="width:150px" | Format
|-
|-
!   !! colspan="8" | 1st Map  Bit[10:5]=111001 !!
|-
! 0 XXX
| colspan="8" | LD.H || rowspan="2" | VII(disp16[R],r)
|-
! 1 XXX
| colspan="8" | ST.H
|-
!   !! colspan="8" | 1st Map  Bit[10:5]=111011 !!
|-
! 0 XXX
| colspan="8" | LD.W || rowspan="2" | VII(disp16[R],r)
|-
! 1 XXX
| colspan="8" | ST.W
|-
!   !! colspan="8" | 1st Map  Bit[10:5]=11110X !!
|-
! 0 XXX
| colspan="8" | 1st Map  Bit[15:11]  JR(r=0) / JARL (r≠0)
| V(disp22)
|-
! 1 XXX
| colspan="8" | 1st Map  Bit[15:11]  PREPARE(r=0) / LD.BU
| XIII/VII(disp16[R],r)
|-
!   !! colspan="8" | 1st Map  Bit[10:5]=111111 !!
|-
! 0 000
| SETF || LDSR || STSR || undef || SHR  || SAR  || SHL
| Bit[18:17]SET1/NOT1CLR1/TST1  || IX(R,r)IX(R,[r])
|-
! 0 001
| TRAP  || HALT || Bit[18:17]RETI/CTRET/DBRET/undef
| 1st MapBit[15:11]EI/DIundef || colspan="4" | undef || X
|-
! 0 010
| SASF || Bit[17]MUL(R,r,w)/MULU(R,r,w) || colspan="2" | Bit[17]MUL(imm9,r,w)/MULU(imm9,r,w)
| colspan="2" | Bit[17]DIVH(R,r,w)/DIVHU(R,r,W)
| colspan="2" | Bit[17]DIV(R,r,w)/DIVU(R,r,w) || IX(R,r)/XI(R,r,w)/XII(imm9,r,w)
|-
! 0 011
| CMOV(imm5,r,w) || CMOV(R,r,w) || Bit[18:17]BSW/BSHHSW/undef || undef
| colspan="4" | Illegal instruction || XI(c,R,r,w)/XII(c,imm5,r,w)
|-
! 0 10X
| colspan="8" rowspan="1" | Illegal instruction || rowspan="1" |
|-
! 1 XXX 
| colspan="8" | LD.HU || VII(disp16[R],r)
|}

List of the V800 Series CPU cores

SoC solutions

SoC IP cores

In 1998, NEC started to provide the V850 family as an ASIC core, to expand its ASIC business.
In addition, both the V850E1 CPU core named Nx85E
and the V850E2 CPU core named Nx85E2,
are also used for expanding its ASIC products business.

Various SoCs utilize this core. In 2003, for example, Dotcast, Inc. used the NU85E core for a set top box receiver of digital datacasting based on the dNTSC (data in NTSC video method). This core is fabricated with CB-10 0.25μm 5-layered-metal process technology.

The NA85E2C core, which is developed using a 1.5 V 150 nm CB-12L (UX4L) fabrication process,
has many errata (4 pages appendix in preliminary architecture manual,
plus a further, 7-page restrictions document),
but which doesn't seem to matter, because this is a product with a long lifespan.

NEC also expanded production of a core using a 130 nm CB-130 (UX5) fabrication process,
cell-base IC.

Synopsys DesignWare IP core for V850E was once announced, but support has been discontinued.

FPGA prototyping systems for SoC

FPGA prototyping systems for V850E1, V850E2, and V850E2M core-based SoCs were intensively developed to expand the SoC business. They comprised a V850 CPU core LSI (TEG, or Test Element Group) board and FPGA add-ons. Most SoC products were for mobile equipments, because the power dissipation of original V800-Series RISC architecture was much lower compared with CISC. 
It is similar to the ARM architecture that is widely used for mobile gadgets.

Renesas (NEC): COREBEST (2001)

Renesas (NEC): Microssp (2006)

Renesas (NEC): Hybrid Emulator (2007)

Renesas (NEC): PFESiP EP1 Evaluation Board (2008)

Renesas (NEC): PFESiP EP1 Evaluation Board Lite (2008)

Renesas (NEC): PFESiP EP3 Evaluation Board (2010): V850E2M CPU core, max. 266 MHz operation

Xylon: logicBRICS

Strategic confusion

Around 2011–2014, Renesas Electronics extensively expanded the V850E2 product line,
but this high-paced expansion brought much confusion. For example, as of 2018, some have requested that V850E2/xxn products be replaced with RH850/xnx ones.

In addition, in 2012 Renesas started to intensively promote the migration from ten-year-old V850ES/Jx3 product lines to the newly produced V850E2/Jx4, such as for Ethernet and USB applications,
but the newer products are not listed on their website, as of 2018.

Currently, Renesas Electronics is designing a "dual" "lockstep" system, but its predecessor NEC V60-V80 had "multiple modular" lockstep mechanism called FRM,
either with roll-back by "retry" or with roll-forward by "exception" for each fault detected instruction.

In addition, the NEC V60-V80 has several implementations of UNIX System V port product releases, one of which is "real-time UNIX RX/UX-832"
(here, 832 stands for the μPD70832 (V80), not V832). Its multiprocessor implementation is called MUSTARD (Multiprocessor Unix for Embedded Real-Time Systems), which can operate a maximum of 8 processors simultaneously, and its lockstep mechanism was dynamically configurable.

In 2001, both NEC Corporation and Synopsys, Inc., announced they had agreed to promote the V850E as DesignWare IP core.
But as of 2018, the V850E is not listed on DesignWare libraries.

Lucent Technologies and Texas Instruments once licensed the V850 and V850E SoC cores, respectively,
but those devices cannot be found.

In 2006,Metrowerks developed the CodeWarrior compiler for the V850, which was one of the main compilers for the V850,
but around 2010, they discontinued support.

Also in 2006, NEC did not give any roadmap for the V850 family as SoC cores. The V850E2 core, developed in 2004, was described as the last, best core for SoC applications. However, NEC introduced ARM9 (arm v5) and ARM11 (arm v6), especially for mobile equipment.
This decision suddenly decreased the net profit of LSI devices, because of the royalty for using ARM, and thus price competition with other ARM SoC providers. The sales revenue of "V850 total solutions", such as development tools, real-time OS, middle-ware packages, and in-circuit emulators, also decreased. The number of V850 devices sold also suddenly decreased, because mobile equipment manufacturer were the major customers of V850E1 and V850E2 cores at that moment.

In 2008, KMC (Kyoto Mictocomputer), which is one of the major and of the first providers of in-circuit emulators for the V850 family, announced "exeGCC" being updated from Rel. 3 to Rel. 4,
but it excluded the V850 from this updating list, which added PowerPC and ARM v7. KMC chose SH-4A and ARM v7, instead of V850 and RH850,
though it had been working closely with NEC and Renesas Electronics.

The V850 CPU cores run uClinux,
but on October 9, 2008, Linux kernel support for the V850 was removed in revision 2.6.27., because NEC stopped its maintenance.
The person in charge of V850 Linux kernel maintenance was moved from NEC to Renesas by its merger, but his new job was compiler design and never returned to Linux kernel maintenance.
This corporate decision prevented the possibility of porting to Android.
As of 2018, Renesas Electronics mainly focuses Linux kernel support on SH3/SH4 and M32R processors.

Target software solutions

Libraries

 Red Hat, Inc.: The Newlib for C runtime library (libc.a) and mathematical library (libm.a)
C runtime startup routine (crt0.S) for the latest v850e3v5 microarchitecture is available.

 Micro Digital Inc.: GoFast for NEC V85x Fast Software Floating Point Library
 The GNU Compiler Collection: Software floating point
 The GNU Compiler Collection: Decimal floating point (libdecnumber.a)

Operating systems

V850 Operating systems are mostly real-time.

Some operating systems require a memory protection unit (MPU) to divide tasks (or threads) strictly for reliability and safety reasons. In such cases, the v850e2v3 (Gen. 3) microarchitecture, or above, is required.

ITRON based real-time OS

ITRON is an open standard specification of real-time OS (RTOS), which is major in Japan.
Its specification is defined under the leadership of Ken Sakamura, as a part of TRON project, the initialr I standing for "Industrial". Because the ITRON specification defines interface and skeleton only, each vendor has its own implementation.

Renesas:
RI850MP Real-time OS for V850E2M Dual Core
RI850V4 V2 Real-time OS for RH850 family
RI850V4 V1 Real-time OS for V850 family

Toppers Project: Open source TOPPERS/JSP
→ In 2003, on Rel. 1.3, V850 dedicated part bug was fixed.
→ Kernel update history
A.I. Corporation: Toppers-Pro/xxx
T-Engine Project: Open source T-Kernel by TRON Forum
eSOL: eT-Kernel; Extended T-Kernel — RTOS for embedded systems
eT-Kernel/Compact, eT-Kernel/Embedded, eT-Kernel/POSIX
eT-Kernel Multi-Core Edition
eCos: Open source real-time operating system

AUTOSAR, OSEK/VDX compliant real-time OS

AUTOSAR is an open systems architecture of operating system for the automotive industry. Its purpose is to standardize electronic control units (ECU) for automotive engines. AUTOSAR is an upward compatible specification of OSEK/VDX, which is also a German consortium established in 1993.

In Japan, this research was started in 2006, as a joint project by JAIST and DENSO. Renesas Electronics joined this project in 2009.
Because the current RH850 and V850 processors are principally targeted at the automotive industry, it is a strategical product of Renesas Electronics. However, its documentation is only available in Japanese, as its main customer is Toyota Motor Corporation.

Renesas: RV850 (documents are in Japanese only)
ETAS GmbH: RTA-OS RH850/GHS, RTA-OSEK V850E/GHS
Mentor Graphics (formerly Accelerated Technology, Inc.): Nucleus OSEK
HighTec EDV-Systeme GmbH: EB tresos Safety OS
Toppers Project: Open source TOPPERS/AUTOSAR
eSOL:  AUTOSAR profile

Other real-time OS

SYSGO AG:
PikeOS; Embedded Virtualization Hypervisor

eSOL:
; Scalable RTOS, Distributed Microkernel Architecture, non-hypervisor type OS

MiSPO:
NORTi Professional; Real-time OS + TCP/IP stack + Simulator

SEGGER
embOS V850 NEC, embOS V850 Green Hills, embOS V850 IAR

Wind River Systems:
VxWorks: Ported in the early 1990s.The Tornado IDE is stated that MP licenses has been sold via NEC in 2000, currently Renesas.

Mentor Graphics (formerly ATI, currently A Siemens Business):
Nucleus PLUS

Linux

uCLinux
Linux kernel
On October 9th 2008, Linux kernel support for V850 was removed in revision 2.6.27, preventing the possibility of porting Android.

Middleware packages

Various middleware application softwares are provided from various vendors.

Renesas: SD Memory Card Control

Software development tools

Compilers and assemblers

Most of the compilers, for both for the V850 family and the RH850 family, are exactly the same product, and extended ISA targets are controlled by command line options.

Compilers for the V850 family and the RH850 family include:
 The GNU Compiler Collection (the name is still v850 for RH850) developed both:
 by "Red Hat, Inc." (formerly "Cygnus Solutions") as a part of the GNUPro Developers Kit
 by "KMC (Kyoto Micro Computer)" as a part of the exeGCC
 by "CyberTHOR Studios, Ltd.": Free pre-built binaries can be downloaded by registration.

 Renesas:
C Compiler Package for V850 family
 CA850 C compiler for V850E1 and V850ES (v850e1 and/or v850es, a.k.a. Gen. 1)
 CX C compiler for V850E2M and V850E2S (v850e2v3, a.k.a. Gen. 3)
Software Package for V850 [SP850] for V850E2 (v850e2(v2), a.k.a. Gen. 2)
CC-RH C compiler package for G3, G3K(H), G3M(H)

 GHS (Green Hills Software): The Green Hills Optimizing Compilers

 Wind River Systems: Diab Compiler

 IAR Systems: Embedded Workbench

Altium Limited: Tasking; RENESAS RH850 SOFTWARE DEVELOPMENT TOOLS

 HighTec EDV Systeme GmbH: HighTec Development Platform

 GAIO Technology: XASS-V Series cross development tools

 Metrowerks: CodeWarrior (obsoleted)

Disassemblers
Usually, dis-assemblers are provided as a part of C compiler or assembler packages.

The GNU Binutils: objdump (v850-elf-objdump or v850-elf32-objdump)
Radare2: Radare2 is a set of command-line tools for reverse engineering. Open-source code is available from GitHub repository.

IDA Pro: IDA Pro is a freeware disassembler for hobby use. A plugin for V850 is available. Download site is gray for securities.

GUI based debuggers

GUI based program debuggers are mainly provided for debugging of compiled source codes. Usually, it is used with instruction set simulators or in-circuit emulators.

Renesas:
ID850: For the combination of CA850 compiler and SM850 instruction set simulator.
ID850NW: For the combination of N-Wire based in-circuit emulators.
ID850QB: For the combination of probing-pod based emulator IEQUBE2
NDK (Naito Densei Kogyo Co. Ltd, Group): Operation started in 1950 as subsidiary of NEC.
NW-V850-32
GHS (Green Hills Software): Multi: General-purpose debugger.
Red Hat, Inc.: Insight (GDB-Tk): GUI front-end tightly combined with GNU Debugger.
Mentor Graphics (formerly Accelerated Technology, Inc.): code|lab Developer Suite
By N-Wire based in-circuit emulator vendors:
KMC (Kyoto Microcomputer) and Midias Lab.: PARTNER
Sohwa & Sophia Technologies:WATCHPOINT
DTS INSIGHT (formerly YDC, Yokogawa Digital Computer): microVIEW-PLUS
Computex: CSIDE

Instruction set simulators

Instruction set simulator, in other words, Virtual Platform is provided to perform debugging without equipment's hardware before testing on a real machine.
Renesas: SM850
Open Virtual Platform: Instruction set simulator
Synopsys: VDK for Renesas RH850 MCU

Automated code reviewers

Automated code reviewer, in other words, source code analyzer qualify the level of completeness of written software source code. This method is classified as dynamic code analysis and static code analysis.

Dynamic code analyzers with simulators

Renesas: TW850
TW850 Performance Analysis Tuning Tool is a general utility to improve effectiveness of software.

Renesas: AZ850
AZ850 System Performance Analyzer is a utility for RX850 real-time operating system to evaluate effectiveness of application programs.

Gaio Technology: Coverage Master winAMS
Coverage Master winAMS is a source code coverage measurement tool.

Static code analyzers

GHS (Green Hills Software): DoubleCheck ISA (Integrated Static Analysis) tool

Rogue Wave Software, Inc: Klocwork

IDE (Integrated Development Environments)

IDE, Integrated Development Environment, is a framework to provide software development functions.

Renesas: CS+ (formerly CubeSuite+)
GHS (Green Hills Software): Multi
Eclipse Plugins
GNU Compiler Collection (GCC) and GNU Debugger (GDB)
Wind River Workbench (formerly Tornado)

Hardware development tools

ICE (In-circuit emulators)

Most in-circuit emulators, such as Renesas's IE850 (formerly IECUBE2),
can be used for both the V850 family and the RH850 family, but may require firmware updating.
The latest "trace function" of the JTAG (N-Wire) based in-circuit emulator is upgraded from the N-Trace (single-ended signaling)
to the Aurora Trace (differential signaling).

Full probing pod type

Full probing pod type in-circuit emulator is sometimes called full ICE or legacy ICE.

Renesas IE850 (formerly IECUBE2)
Naito Densei Machida Mfg. Co., Ltd. (Operation started as NEC's subsidiary.)
Asmis brand for custom LSIs.

ROM emulator type

Lauterbach: ROM Monitor for V850
KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-ET II (obsoleted)

JTAG N-Wire and N-Trace type

N-Wire and N-Trace
is a JTAG-based debugging interface specification, which circuit implementation is called TAP Controller (Test Access Port controller),
primarily compiled by Philips N.V. (currently NXP Semiconductors). But it is perhaps not disclosed publicly in its earlier stage. As the result, each semiconductor and in-circuit emulator vendor implemented similar interfaces independently. Nowadays, it is standardized by IEEE 1149.1 Working Group.

Renesas
E1 Emulator: USB 2.0 based affordable compact housing equipment.
PCMCIA N-Wire Card IE-V850E1-CD-NW

Naito Densei Machida Mfg. Co., Ltd. (Operation started as NEC's subsidiary.): Asmis brand.
Midas Lab.: RTE-2000H with PARTNER debugger
Lauterbach: Trace32
: BlueBox iC5000 and iC5700
IAR Systems
DTS INSIGHT (formerly YDC; Yokogawa Digital Computer): adviceLUNA II

Computex: PALMiCE3 V850
Sohwa & Sophia Technologies: Universal Probe Blue with WATCHPOINT debugger
KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-Jet (obsoleted)

Nexus and Aurora trace type

Nexus or IEEE-ISTO 5001-2003 is a standard debugging interface for embedded systems.

Aurora is a high speed signal transfer specification. Its data link layer communications protocol is a point-to-point serial links, and physical layer is a high speed differential signaling.

Lauterbach: Trace32: PowerTrace for NEXUS
: BlueBox iC5000 and iC5700 (Nexus), iC6000 (Aurora)

Flash ROM programmers

Because the V850 family is developed as a single chip microcontroller, every product integrates non-volatile memory. In its first stage, it was one-time programmable or UV EPROM type, but in V853, V850/xxn Series, and later, it becomes flash memory type.

Gang writers (gang programmers)

A gang writer, or a gang programmer, is an old terminology for programmable ROM writers, or programmers. Its name comes from that it steals the binary code from one device, and write it to several others simultaneously. This read device is sometimes called a master device. For mass production use, a dedicated attachment board with "a set of sockets", i.e. "a gang", is needed. As usual, instead of a programmed master device, an object code file can be copied from a PC via download cable, or from a USB stick. Most gang writers accept ASCII-format files such as Intel HEX and Motorola SREC, or binary format files such as ELF.

This method is suitable for mass production.

TESSERA Technology Inc.: Stick GANG Writer

Programming service providers

Flash ROM programming service providers exist in most countries.

Minato Holdings, Inc.

Minato Holdings, Inc. (in Japanese) is a Japanese company that started as an automated test equipment vendor for memory LSIs. Nowadays, it provides flash ROM programming services for various devices, including V850 and RH850, with its own gang writers and full automatic device handler machines.

On board programming with ICE

Most JTAG-based in-circuit emulators have an on board flash ROM programming function via a debug port,

which may be according to IEEE standard 1532-2002, a standard for in-system configuration of programmable components.

Direct connection via RS-232C

If the target board has a RS-232C connector and a transceiver (driver/receiver) IC, such as ICL32xx,
for the UARTx peripheral function of V850 device, flash ROM programming with a directly connected PC might be available (depends on devices
).
The Renesas Flash Programmer software V2
or V3
is required.

Dedicated on board programmer

On-board programming is also available via UARTx or CSIx+HS peripherals on V850 devices by using dedicated programmer hardware (depends on devices).

Renesas: PG-FP6

Ancient PROM writers

To program V851
and V852, an ancient PROM programmer with dedicated adapter is required.

Renesas PG-1500 (obsoleted)
Renesas PG-1500 is a programmable ROM writer compatible with 27C1001A devices, UV EPROM, or one-time PROM (OTP). This writer reads a silicon signature from each device before programming, by asserting 12.5 V to the A9 (address #9) terminal. It must NOT be used for modern flash ROM burning.

Gray zone tools

Some gray zone hacking tools exist for V850 on car dashboards.

VVDI PROG.:
OBDexpress

Evaluation boards

Renesas: TK-850: The name is influenced by nostalgia for the TK-80 8080-based training kit.

See also

NEC V60
NEC V20
RL78
78K
IEBus

References and notes

External links
Die photo of V850 (V851 maybe) introduced 1994 by Nikkei BP (in Japanese, registration required)
Die photo of V853 by NEC's press release (in Japanese)
Present Status of the Embedded CPU in SoC Design, NEC Tech. Journal 1-5 pp.38-45 (Dec. 2006)
Renesas: V850 Architecture Overview, High performance and Energy Efficient
User’s Manual, V850 Family 32-bit Single-Chip Microcontroller Architecture

V850|V850E|V850E2|RH850
Renesas microcontrollers
Computer-related introductions in 1994