— This paper presents an empirical approach backed by LTspice simulation to optimize switching performan ce in half- bridge configuration. For a given layout effective value of RC network in gate drive loop, ways to avoid dV/dt ind uced false turn- on of MOSFET and remedial circuit for minimizing para sitic oscillation at switching nodes have been presented. Entire study has been validated using LTspice simulation as it’s n ot possible to build a hardware board which can cover all the desi gn aspects authors wanted to cover. Idea is to present a syste matic approach which a practicing engineer can adopt for optimizi ng switching of MOSFET in a given PCB layout. Keywords– MOSFET, false turn-on, 3-phase inverter, parasitic oscillations, automotive electronics, low voltage e lectronics. I. INTRODUCTION esigning a power electronic converter is a dauntin g task. For a given voltage and current rating, several MOS FET may be available in market from different manufactu rer. Each manufacture define their datasheet parameters at di fferent test condition. If a universal test condition is adopted by all manufacturer for their datasheet, then, one can jus t pick MOSFET by comparing parameters in datasheets availa ble from manufacturer, but this is not the case in real ity. Therefore, for selection of MOSFETs relying just on datasheet is not a good idea. Best way for selecting MOSFET for a give n application is to test the shortlisted MOSFET in th e given layout to check their switching behavior. Almost ev ery power electronics converter employs inductive switching, therefore, double pulse test (DPT) is commonly used for access ing switching performance. By performing a DPT, informa tion such as rise time/fall time of voltage and current, dV/dt information, dI/dt information, overshoot of curren t and voltage, switching losses and presence of gate osci llation, amplitude of miller pulse on the off device due to dV/dt induced gate voltage can be accessed [1]-[2]. Having this i nformation on hand can be useful for determining parasitic ele ments of circuit layout and apply corrective actions to opti mize the circuit the best one could. Fig. 1 shows a typical DPT circuit and switching wa veform obtained using the test setup. First pulse is a wid e pulse which is used to build the current to the magnitude which is of interest. This is usually equal to maximum RMS value of load current in the converter topology. Second pulse is a short pul se for measurement purposes and is kept as short as possib le [3]-[4]. The DPT are supplied at a very low frequency to all ow measurement at constant device temperature and to a llow the load to discharge completely between two DPT. By ad justing time T1, T2 and T3, the run-on and turn-off wavefor ms of the device under test (DUT) can be controlled and measu red over the full range of operating conditions. T2 and T3 u sually corresponds to minimum duty cycle used in the actua l converter. V DC is the DC link voltage. (a) (b) Fig. 1. (a) Double pulse test (DPT) circuit (b) Sw itching waveform in DPT It is worth noting that complementary MOSFET T 2 can also be switched with dead time for synchronous ope ration for observing the effect of dead-time interval on switc hing performance. Beauty of this circuit is that it eff ectively represents switching in any converter topology emp loying D similar switching pole structure, e.g. buck convert er, boost converter, half-bridge inverter, full-bridge invert er, 3-phase inverter, multilevel inverter etc. This test allows to optimize the switching behavior of the power frame of the conver ter without using the actual controller and load. For example, to optimize the power frame of 3-phase inverter for motor drive application, one may not have to use the actual controller and m otor load to test and finalize the power frame layout. This in t urn allows the hardware engineer working on PCB layout and power f rame design to work independently with the firmware engi neer working on controller design and vice versa. Fig. 2. Half bridge circuit with parasitic element s of PCB layout Fig. 3. Ringing on phase voltage (PhA) and gate pi n of MOSFET in circuit shown in Fig. 2 Fig. 2 shows the half-bridge circuit which will be used to present the optimization process. Resistance and in ductance in dotted box represents the parasitic of the PCB trac es. In addition, LD and LS represent the lead inductance o f the MOSFET T1 and T2. T1 and T2 is STL64DN4F7AG dual channel automotive grade 40V MOSFET from STMicroelectronics [5]. Targeted application is ele ctronic purge pumps (BLDC motor pumps) used in gasoline veh icles with 12V battery pack. Circuit inside solid green b ox represents gate driver unit with current limit and different t urn-on (R GDON )and turn-off (R GDOFF ) resistance. Load inductor is fixed to achieve load current of 10A in 25µs assuming swi tching frequency of 20kHz. Due to parasitic elements of PC B layout and MOSFET package (lead inductances, input/output capacitance) oscillation could be observed on switc hing nodes (gate, source and drain) of MOSFET as shown in Fig. 3. Optimization process involves appropriate sizing of gate resistor R G to meet desired dV/dt rate, selection of external capacitance C GS,Ext connected between gate a-source pin of MOSFET to avoid false turn-on of the MOSFET and snu bbers to damp ringing on drain of MOSFET. However, gate r esistor not only affect dV/dt rate and overall switching ti me, but it also influence false turn-on in MOSFET, similarly extern al capacitance, if not sized properly, will make the s witching time longer than desired and will therefore generate los s. Therefore, a systematic approach is needed as switching variab les are interlinked to each other and has been discussed in coming sections. II. SIZING GATE RESISTOR , RG Selection of gate resistor R G depends on three factors: (a) Gate driver current limit : Gate resistor should be high enough that sourcing a nd sinking current doesn’t hit the limit set in GDU. To meet t his rule, value of gate resistor is given as: , ≥( )  (1) In eq.(1) VDD(max) is the maximum supply voltage of gate driver unit (GDU). I limit is the peak sourcing and sinking current capability of GDU. R G,tot is the sum of resistance offered by internal circuitry of GDU, internal gate resistance of MOSFET and external gate resistor R G. In this paper author wants to limit the current drawn from GDU to 250mA to avoid stressing GDU. Using eq. (1), R G,tot is calculated to be 48 Ω for VDD(max) of 12V. (b) Rate of change of voltage across MOSFET Rate of change of voltage across MOSFET, i.e., dV/d t rate is inversely proportional to R G,tot and is given by:   =  ,  = (  ) ,  (2) In eq. (2) V DS is voltage across FET, V GP is miller plateau voltage of the FET, Q GD is total gate-drain charge moved during voltage changing across the FET. V GP and Q GD are obtained from the datasheet of STL64DN4F7AG and are equal to 5.5V and 2.48nC respectively. In automotive application operating voltage range of electronics product is usually 9V to 16V. Switching frequency of purge pump which is essentia lly a 3- phase inverter driving a BLDC motor is 20kHz. Facto rs behind selection of dV/dt rate depends upon desired switch ing speed, EMI performance and factors such as device capabil ity. Detail discussion over choice of dV/dt rate is out of scop e of current paper. In this paper, assuming minimum rise time of 50ns for 16V, i.e. dV/dt rate of 0.32V/ns is used for presen ting the optimization process. Using eq. (2) value of R G,tot is calculated to be 131 Ω. Fig. (4) shows the effect of gate resi stance on dV/dt rate of FET T2. For R G,tot of 131 Ω, rise of approximately 50ns is obtained as can be seen from the time base. Fig. 4. Simulation result showing slope of drain- source voltage of T2 for different value of R G (c) Oscillation in gate drive loop Oscillation on gate signal is due to two reasons: ( i) parasitic components in the gate drive loop (ii) any voltage transients on drain is coupled to the gate due to the presence of miller capacitor C GD between drain and gate of FET. To illustrate this point, a circuit was created as shown in Fig. 5. Simulation results obtained from the circuit, pr esented in Fig. 6, shows the oscillation on gate pin of FET. Low fr equency oscillation is due to parasitic components in gate drive loop High frequency oscillation is due to oscillation on drain pin which is induced on the gate pin by miller cap C GD. Frequency of induced oscillation is same as frequency of ring ing on drain node of MOSFET. Low frequency oscillation on gate p in is given by:  =! "#$%&'( &'( (3) In eq. (3) L par is total inductance in gate drive loop. This includes inductance due to PCB traces, MOSFET packa ging and GDU inductance in Gate drive loop. C par is total capacitance in gate drive loop. This includes stray capacitance s due to PCB layout as well as MOSFET gate source capacitance. Fig. 5. Simulation circuit used to show oscillatio ns on gate of FET Fig. 6. Simulation result showing oscillation on g ate pin of MOSFET M2 Neglecting effect of stray capacitance due to PCB t races, C par is essentially equal to C GS of the FET and can be obtained from the datasheet of the device By measuring the freque ncy of oscillation f osc using CRO, value of L par can then be easily be calculated using eq. (3). However, for more accurac y C par and Lpar should be determined experimentally and procedure for determining the parasitic elements has been discuss ed in later section of this paper. Once f osc and L par is known, value of gate resistance to damp the oscillation is given by: , = 4*+  ,- . (4) Fig. 7. Effect of gate resistor on oscillation on gate voltage In Fig. 5, Lpar is 110.6nH and f osc is measured to be 19MHz in Fig. 6. For damping factor ζ equal to 1, R G,tot is calculated to be 27.38 Ω using eq. (4). Fig.7 shows the effect of R G,tot of 27 Ω on gate oscillation. One can observe that low frequency oscillation is completely damped however high frequ ency induced oscillation remains. A common mistake is to try to damp high frequency oscillation by increasing gate resistor value. Technically high frequency oscillation can a lso be eliminated by using corresponding value of gate res istor but for damping of 146MHz one would need a resistor of 202Ω . Using such a high value of gate resistor will make the ri se time of voltage very slow. One should also realize that for a given layout it’s possible that induced oscillation is si milar to gate oscillation, in that case a single value of gate re sistor can solve the problem of oscillation on gate as well as drain node. If that’s not the case, one should always identify the type o f oscillation first and then apply appropriate corrective action as described above. Final value of gate resistor should satisfy all thr ee cases discussed above, therefore, R G,tot should be 131 Ω. Finally, value of R G is calculated to be: (131-1.3-17.4) Ω = 112.3 Ω. Here 1.3 Ω is internal gate resistor of STL64DN4F7A G and 17.4 Ω is the resistance of the GDU. Nearest standa rd value of 110 Ω will be used as R G in this paper. III. AVOID FALSE TURN -ON OF COMPLEMENTARY MOSFET Using Fig. 8 one can understand, if T1 turn-on sudd enly, then rate of change of voltage at node U will cause disp lacement current through Miller capacitor C GD of T2. This current causes voltage drop V GS,off across turn-off resistor of T2. If V GS,off is greater than threshold voltage V GS(th) of T2 it will turn on and will cause direct short circuit across the DC suppl y. Fig. 8. Circuit showing self-turn-on phenomenon Using Fig. 8, one can write: / = / 0 + / ,22 = 3 0    +,44 5(6 ,44 (5) 70 = 7  + 7 0 (6) In eq. (5), V drv is initial voltage on gate of T2 during start of dV/dt. Using (1) and (2), one can derive the V GS,off as in eq. (7). 70,22 =  ,22 3   [1 − ; ,44 (  <  ) =] (7) From (7), V GS,off is rising exponentially with time-constant of τ=R G,off (C GS +C GD ) and its peak value is equal to ,22 3   . To avoid false turn-on one can either reduce the peak value of V GS,off below V GS(th) of T2 or can increase the time constant τ of V GS,off . To reduce the peak value, only option is to reduce R G,off , i.e. to use a separate gate resistor for turn-on and tur n-off interval. Usually, its common practice to bypass the turn-on resistor R G using a Schottky diode to limit the voltage generat ed on gate pin of FET due to dV/dt. However, this method is no t very effective in synchronous rectification operation as it also increase the dV/dt rate and resulting current will cause voltage drop across R GDON which is still present. Therefore, overall peak value of V GS,off remains almost the same. Most effective way to avoid false turn-on is to inc rease the time constant τ of V GS,off so that it doesn’t reach its peak value during dV/dt time period, t. This is achieved effec tively by adding an external capacitor C GS,Ext between gate-source pin of FET. If τ>>t then, using Maclaurin expansion e x=1+x, eq. (7) can be re-written as: 70,22 =   <  70 (8) This essentially means that C GD and C GS behaves like a capacitive divider. If induced voltage becomes gre ater than V th of the FET, it will turn-on. Therefore, in order to have a low sensitivity to parasitic turn-on, selecting MOSFETs with a high VGS(th) and a large C GS /C GD ratio is of prime importance. Adding external C GS,Ext further increases the C GS /C GD ratio. Note, however, that the gate-source capacitor affects the switching speed of the MOSFET as well as size of bootstrap ca pacitor will also increase, therefore an optimum value must be s elected for a circuit. To verify eq. (7), an approximate small signal mode l of MOSFET was simulated as shown in Fig. 9. In the cir cuit, RG,OFF is 10Ω C GS is 611pF and C GD is 26pF, therefore τ is 6.37ns. Supply of 16V is being turned-on and off in 50ns to have dV/dt of 0.32V/ns. Fig. 9. Circuit for verifying dV/dt induced voltag e Since, in Fig. 9, τ<dV/dt period, V GS,off reaches its peak value of : 70,22 =  ,22 3   =10*26pF*0.32V/ns=0.0832V If R G,off is increased to 120Ω, τ increases to 76ns which is greater than dV/dt period. In such a circuit, V GS,off is given by eq. (8) and is calculated to be 0.653V. Fig.10 and Fig. 11 shows the simulation result for both cases, i.e. for τ<dV /dt period and τ>dV/dt period respectively. I GD can also be calculated as: / = 3     = 26AB ∗ .327/GH = 8.32JK Fig. 10. Simulation Result for τ<dV/dt period Fig. 11. Simulation Result for τ>dV/dt period In Fig. 10, one can see that the V GS,off reaches its peak value of 83mV during dV/dt period. In Fig. 11 since τ>dV/dt VGS,off couldn’t reach its peak value and start dropping on ce dV/dt period is over. I GD in each case is independent of R G,off and is equal to 8.32mA.This essentially verifies the conce pt of dV/dt induced gate voltage on MOSFET. For the original circuit shown in Fig. 2, C GS,ext is calculated for dV/dt of 0.32V/ns. Considering inductive spike to be 100% of V DC , maximum voltage across the MOSFET will be 32V. Fo r STL64DN4F7AG, minimum value of V GS(th) is 2V, C GD is 26pF and C GS is 611pF. Minimum value of C GS,Ext needed to keep induced voltage at maximum 0.5V is calculated as: 3,L  = 3   (44)− 3 0 − 3  =1027 pF To provide some design margin, a value of 2.2nF is selected considering non-linear nature of C GD capacitor. Fig. 12 shows the effect of adding C GS,Ext on gate voltage and V GS,off in Fig. 2. Fig. 12. Simulation result showing effect of addin g C GS,Ext in DPT circuit IV. MINIMIZING RINGING ON SWITCHING NODE Fig. 13 shows the ringing on voltage across MOSFET T1 and T2, of the circuit shown in Fig. 2, during their tu rn-off instant. For Fig. 13, simulation was done with C GS,Ext of 2.2nF. Reason of ringing has been explained in several literature s [7]. Essentially, during turn-off process, the body-diod e of FET draws a peak reverse recovery current and then abru ptly snaps off. Since there is a small but finite parasitic in ductance in the circuit, the reverse recovery current will circulat e through the circuit until it dies down. This will result in vol tage overshoot and oscillation at the drain node of FET as observe d in Fig. 13. Fig. 14 shows the leakage current path in the DPT c ircuit during turn-off of T1 and T2. Frequency of ringing at drain of T1 during its turn-off instant is given as:  =! "#$%M N (9) Here, L lkg is total leakage inductance in leakage current pat h, i.e., L lkg =L lkg1 + L lkg2 + L lkg3 + L lkg4 + L lkg5 + L lkg6 and C DS1 is equivalent output capacitance of T1. This includes MOSFET drain-source cap C DS , any external capacitance connected across FET, freewheeling diode capacitance as well as any stray capacitance due to PCB layout. Fig. 13. Ringing at switching node of T1 and T2 MO SFET. Fig. 14. Circuit showing leakage current path duri ng turn-on and turn-off instant of switches in DPT fosc doesn't depend upon location of L lkg but only on its total net value which makes it very easy to determine experim entally. Note, however, location of L lkg will affect the magnitude and phase of the ringing though as is evident from the Fig. 13. To determine the f osc experimentally steps described as below could be used: a) Measure the frequency of oscillation (f osc ) on Phase voltage during it fall from V DC to GND level as shown in Fig. 15. b) Connect a capacitor (C DS,Ext ) of known value across High Side FET T1 and measure the new frequency of oscill ation (fosc1) on phase voltage during its fall from V DC to GND potential as shown in Fig. 16. c) Calculate the ratio of two frequency: x= (f osc )/(f osc1 )=2.5 d) Calculate circuit parasitic capacitance: C DS = C DS,ext /(x 2-1)= 419pF e) Calculate parasitic inductance of circuit: L lkg = 1/(4π2CDS f2osc )=44.2nH Total L lkg in simulation circuit is 43.72nH. Therefore, this method gives a very accurate estimate of total para sitic inductance in leakage current path Fig. 15. Phase voltage without any external capaci tor across T1 Fig. 16. Phase voltage with external capacitor of 2.2nF across T1 Once L lkg and C DS is determined, a snubber circuit could be designed to minizine the ringing on switching node. There are various snubber topology used for this purpose, suc h as [7]- [10]: RCD snubber, regenerative snubber, bus side R CD snubber, over-voltage snubber etc. Each have its ow n merit and demerits, discussion over which is out of scope of this paper. For a low power and low voltage circuit, a simple R C snubber is a good compromise between complexity, cost and a vailable real estate on PCB and therefore will be used in th is paper. Fig. 17 shows the equivalent circuit used for RC snubber design. (a) (b) Fig. 17. Equivalent circuit during turn-off of FET in switching pole (a) Without snubber (b) with RC snubber Neglecting Cs, transfer function of Fig. 17(b) is g iven as: P(Q)=RST U 0U<0"VR ST <RST U (10) Here, W =! $%XMY  and 2+W Z=!   Value of Resistance, R S which snubs the circuit is given as: 0=! "VR [  =! "V\%MY  (11) In half-bridge circuit, one cannot just have a resi stor mounted directly across FET as it will permanently short th at FET. Therefore, a capacitor Cs is put in series with R S to RC snubber. Reasonable damping occur at ζ=0.5, therefore, 0=\%MY  =\]]."Z^ ]!_-` = 10.27 Ω Snubber capacitor is selected so that ringing frequ ency is easily passed but all lower frequency and DC are b locked. For convenience it is nice to choose a frequency that 2 π times lower the RC cut-off frequency [11]. Therefore, 30=c 2ST =1/(10.27Ω*37MHz)=7.89nF Using a higher value of capacitor will provide over damping but will also increase loss in R S [11]. Time constant of RC snubber should be small compared to the shortest ex pected on- time of the FET. Fig. 18 shows the simulation of Fi g.17 with and without RC snubber. Fig. 18. Effect of using RC snubber on voltage at node ‘n’ Once RC snubber is calculated, optimisation process is complete. In final circuit a practical value of Rs= 10Ω and Cs=10nF was used. Fig. 27 shows the final circuit w ith calculated R G, C GS,Ext and RC snubber. Fig. 19. Final optimised circuit. Fig. 20. Simulation result showing switching node voltage for optimised circuit. In Fig. 20 one can see that ringing on gate, drain and source pin of MOSFET is damped. A dV/dt rate of 0.18V/ns is achieved. Due to addition of snubber rise time of p hase voltage increases from 50ns to 87ns which is within the des ign requirement of achieving minimum rise time of 50ns. V. CONCLUSIONS This paper presents an analytical design methodolog y backed by LTspice simulation for optimising switching perf ormance in half-bridge MOSFET circuit. In such a half-bridge c ircuit, design variables are depended on each other. For ex ample, gate resistor value not only affect the oscillation in the gate drive loop but also affect the switching rate of the MOSF ET. It is shown in this paper that oscillations on the gate p in of MOSFET is due to parasitic elements in gate-drive loop as well as due to the induced oscillation which is coupled to the gat e from drain through Miller cap. This paper showed the differenc e between both type of oscillations and corrective action nee ded to minimize both type of oscillation. Gate resistor va lue is calculated to damp the oscillation due to parasitic elements in gate-source loop. Since gate resistor also affect t he dV/dt rate, its important to not oversize it. Paper also showed the rational behind selecting proper value of external gate-sour ce capacitance used in circuit for avoiding false turn -on of the MOSFET. Finally, dV/dt induced oscillation as well as oscillation on drain of MOSFET is damped using snub ber circuit. Following the design methodology presented in this paper any half-bridge circuit can be optimised to m eet the design goal.