This article presents the detailed design and implementation of a Static Random-Access Memory (SRAM) in CMOS technology. The data access (read/write) is done through Serial Peripheral Interface (SPI), an industry-standard serial protocol. This SRAM is speci/uniFB01cally suitable for Internet-of-Things (IoT) applications with slow access rates and low power consumption. For the purpose of demonstration, a /three.pnum/two.pnum-byte SRAM was designed and fabricated in /zero.pnum./six.pnum m CMOS technology and successfully tested for its full functionality after fabrication. /one.pnum Introduction A typical IoT sensor contains four main devices as shown in Figure /one.pnum: sensor, microcontroller (MCU), a wireless device (Bluetooth, WiFi, LoRa) and SRAM. Since sensor nodes work on low data rates and low power, the devices communicate among themselves over a serial bus such as the Serial Peripheral Interface (SPI) or Inter IC Communication (I/two.pnumC) protocol. The MCU serves as the master controller for the IoT node to negotiate all transactions between devices. The wireless device is responsible for sending sensor data to the nearest gateway and receiving control instructions from the gateway as well. The sensor measures environmental parameters (temperature/humidity/etc) and the data is digitized is transmitted over the SPI/ I/two.pnumC serial communication bus. The SRAM is used to store local data when a gateway is not available for communication. This article describes the design and implementation of a low-power SPI accessible SRAM implemented in a /zero.pnum./six.pnum /uni00B5m CMOS technology. The innovation of this project lies in creating and controlling all the signals required for the SRAM without use of internal clocks, deriving all control signals from the SPI signals themselves instead, thereby making it a simple and scalable circuit that can be made to consume very little power with slower access time. Figure /one.pnum: Block diagram of a typical IoT sensor node. 1 Figure /two.pnum: SRAM Architecture. Figure /three.pnum: .Timing diagram for the write operation. /two.pnum SRAM Architecture The architecture of the SRAM with the serial interface is shown in Figure /two.pnum. The SRAM consists of the array of the core SRAM cells along with the row decoders, column decoders, and the sense ampli/uniFB01ers. The SPI interface converts the incoming serial signals to their appropriate control signals to read and write the data from the SRAM using the serial bus. The SRAM core consists of /three.pnum/two.pnum-bytes of /eight.pnum-bit words laid out as a /one.pnum/six.pnumx/one.pnum/six.pnum array of six-transistor (/six.pnumT) CMOS memory cells (Leblebici et al., /two.pnum/zero.pnum/one.pnum/four.pnum; Weste and Harris, /two.pnum/zero.pnum/one.pnum/one.pnum). Each cell is individually accessed by selecting the corresponding row and column using their respective decoders. The word lines are selected using the /four.pnum-bit LSB of the SRAM address A3:0and two columns are selected using the MSB of the address A4. After selecting the individual cells, the corresponding bit lines are used to read from the cell or write to it. During the read operation the bit lines are /uniFB01rst pre-charged to a pre- determined value (VDDVTN), then the pre-charge circuit is disabled, and the SRAM cell is selected after that. The di/uniFB00erence in the voltage between the bit lines represents the data in the SRAM cell and typically this di/uniFB00erential voltage is a fraction of the supply voltage, not enough to drive a digital gate directly. A di/uniFB00erential sense ampli/uniFB01er is used to amplify this small di/uniFB00erential voltage to the supply rails ( VDDor0) and then the output of the sense ampli/uniFB01er can drive digital gates directly. The output is fed back to the SPI controller which then converts the parallel /eight.pnum-bit data to a serial output complying with the SPI protocol. During the write operation, the SPI controller converts the serial input data to /eight.pnum-bit parallel data and the corresponding SRAM cells area selected, as in the read operation, but the column decoders now connect the bit lines to the /eight.pnum-bit drivers to write the data instead of sensing it. Once the data is written, all the cells are de-selected and the data remain stored until the power is applied to the IC or overwritten by another write operation. The next two sections detail the architecture of the timing to keep everything synchronous to the master clock ( SLCK ). The SPI protocol has /four.pnum modes of operation (/zero.pnum-/three.pnum) (Leens, /two.pnum/zero.pnum/zero.pnum/nine.pnum) and this SPI controller is designed for Mode-/two.pnum where the idle clock is high and the masters sends data at the negative-edge of the clock and samples at the positive edge of the clock. To keep the design simple and avoid setup/hold time issues, the SRAM sends and samples data opposite to the master ie. negative-edge and positive-edge respectively. /two.pnum./one.pnum Write Operation Figure /three.pnum shows the timing diagram of the SPI write operation. After the master (eg. MCU) selects the SRAM chip by pulling Chip-Select ( CS) low, /two.pnum bytes are transferred serially on the Master-Out-Slave-In /two.pnum Figure /four.pnum: .Timing diagram for the read operation. Figure /five.pnum: /six.pnumT SRAM Cell. (MOSI ) port with data changing synchronously every negative edge of the clock input ( SCLK ). The /uniFB01rst bit denotes if the operation is read (/one.pnum) or write (/zero.pnum). The next /five.pnum bits are assigned for the address of the SRAM and the last two bits are unused. The second byte contains the /eight.pnum-bit data that needs to be written to the corresponding address. The controller latches the read/write bit after the /uniFB01rst clock cycle and latches the address to the decoders at the end of the 6thclock cycle. Then the controller generates a pre-charge signal (pc) at the positive edge of the 14thcycle for one clock period. The data is latched for write at the positive edge of the last clock cycle ( 16th) and write control signals ( wl;wr;col ) are also asserted at the same edge and pulled low when the chip is de-selected ( CSis high). /two.pnum./two.pnum Read Operation Figure /four.pnum shows the timing diagram for the read operation. First byte of the read operation is the same as the write operation except, the pre-charge signal ( pc) is asserted at the positive edge of the 7thclock cycle and the read control signals ( wl;col;muxen;sae ) are asserted from one clock cycle at the positive edge of the 8thclock cycle during which the data from the SRAM ( Dsns[7:0]) is latched by a shift-register at the negative edge of the 9thclock cycle. Once the data is latched, the shift register shifts each bit into the Master-Input-Slave-Output ( MISO ) port at the negative edge of the clock for the next does clock cycles. /two.pnum./three.pnum Six-Transistor (/six.pnumT) SRAM Cell The core of the design is the SRAM cell itself which stores one bit of information. The area and the power of each cell is very critical since it decides the area and power of the entire chip. In this design, a standard /six.pnumT SRAM Cell is used as shown in Figure /five.pnum (Leblebici et al., /two.pnum/zero.pnum/one.pnum/four.pnum; Weste and Harris, /two.pnum/zero.pnum/one.pnum/one.pnum). In principle, it is a back-to-back inverter ( M1;M2;M5;M6) to store data inde/uniFB01nitely if power is provided to the cell. The ac- cess transistors ( M3;M4) are used to read and write data into the cell. The sizing of the devices is decided by three main factors: (/one.pnum) smallest size (/two.pnum) does not destroy the data when reading and (/three.pnum) able to over- write the stored data. On analyzing with the given constraints and the appropriate large-signal equations /three.pnum Figure /six.pnum: Block diagram of the SRAM Controller. Figure /seven.pnum: Measurement setup. (saturation/linear) (Leblebici et al., /two.pnum/zero.pnum/one.pnum/four.pnum), it can be shown that M3needs to stronger M5andM1needs to be stronger than M3. Since the structure is symmetric, the same constraints for M6;M4;M2. /two.pnum./four.pnum SRAM Controller The core contribution of this work is to create all the control signals for SRAM from the master clock (SCLK ). Figure /six.pnum shows the block diagram of the overall architecture of the controller. A /five.pnum-bit syn- chronous counter is used to keep track of the number of cycles after CSgoes low to create the appropriate synchronous timing signals as shown in Fig. /three.pnum and Fig. /four.pnum. Two /eight.pnum-bit shift-registers are used to convert serial data to parallel and vice-versa. The SRAM controller uses a combination of comparators and /uniFB02ip-/uniFB02ops to generate the required control signals for the SRAM. /three.pnum Measurement Setup and Results A picture-schematic of the measurement setup is shown in Figure /seven.pnum. An Arduino development was used as the master to communicate with the SRAM using the SPI protocol. An Open Workbench Logic Sni/uniFB00er was used to probe the SPI signals and plot them to verify the functionality of the fabricated SRAM IC. Figure /eight.pnum shows the Logic Sni/uniFB00er output for a SPI transaction writing location 0x19 with 0xDC and reading the same location. As seen from the annotation, the /uniFB01rst bit on MOSI is0denoting a write, the next /uniFB01ve is the address 0x19 and the second word is 0xDC . The last two byte is a read operation of the same location and seen from the MISO output of the SRAM it is 0xDC . /four.pnum Figure /eight.pnum: Measurement result. /four.pnum Conclusion A SRAM design in 0:6mCMOS technology is demonstrated to be a viable candidate for IoT-based sensor nodes where power consumption is the top priority and the access rates are slow which can be done over a serial bus such as the SPI protocol. /five.pnum Acknowledgement We acknowledge the support of Deepika Kumari, Gautam Kumar, Pragya Tiwari, Sameer Namdeo, Shiva Prasad Das, Suruchi Kumari, Unnati Kumari Gupta, Anshuman Mishra and Vishal Sao for their help in sim- ulation and layout.