Super Harvard Architecture Single-Chip Computer. The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is used in a variety of signal processing applications ranging from  audio processing, to single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers. The original design dates to about January 1994.

SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to SMP.

Architecture
The SHARC is a Harvard architecture word-addressed VLIW processor; it knows nothing of 8-bit or 16-bit values since each address is used to point to a whole 32-bit word, not just an octet. It is thus neither little-endian nor big-endian, though a compiler may use either convention if it implements 64-bit data and/or some way to pack multiple 8-bit or 16-bit values into a single 32-bit word. In C, the characters are 32-bit as they are the smallest addressable words by standard.

The word size is 48-bit for instructions, 32-bit for integers and normal floating-point, and 40-bit for extended floating-point. Code and data are normally fetched from on-chip memory, which the user must split into regions of different word sizes as desired. Small data types may be stored in wider memory, simply wasting the extra space. A system that does not use 40-bit extended floating-point might divide the on-chip memory into two sections, a 48-bit one for code and a 32-bit one for everything else. Most memory-related CPU instructions can not access all the bits of 48-bit memory, but a special 48-bit register is provided for this purpose. The special 48-bit register may be accessed as a pair of smaller registers, allowing movement to and from the normal registers.

Off-chip memory can be used with the SHARC. This memory can only be configured for one single size. If the off-chip memory is configured as 32-bit words to avoid waste, then only the on-chip memory may be used for code execution and extended floating-point. Operating systems may use overlays to work around this problem, transferring 48-bit data to on-chip memory as needed for execution. A DMA engine is provided for this. True paging is impossible without an external MMU.

The SHARC has a 32-bit word-addressed address space. Depending on word size this is 16 GB, 20 GB, or 24 GB (using the common definition of an 8-bit "byte").

SHARC instructions may contain a 32-bit immediate operand. Instructions without this operand are generally able to perform two or more operations simultaneously. Many instructions are conditional, and may be preceded with "if condition " in the assembly language. There are a number of condition choices, similar to the choices provided by the x86 flags register.

There are two delay slots. After a jump, two instructions following the jump will normally be executed.

The SHARC processor has built-in support for loop control. Up to 6 levels may be used, avoiding the need for normal branching instructions and the normal bookkeeping related to loop exit.

The SHARC has two full sets of general-purpose registers. Code can instantly switch between them, allowing for fast context switches between an application and an OS or between two threads.

See also
TigerSHARC
Blackfin
Qualcomm Hexagon
Texas Instruments TMS320
CEVA, Inc.

External links
SHARC processors website

Digital signal processors
Very long instruction word computing
VLIW microprocessors