omniomni/omni-engineering huggingface dataset:
Acoustiblok. Acoustiblok, a registered trademark of Acoustiblok Inc., is manufactured in the United States. It is a sound attenuation material that was introduced in 1999.  It is implemented in new construction and remodeling projects. It is designed to be applied behind drywall and other finishing materials.

Physical properties

Acoustiblok is a mass-loaded vinyl sound isolation product. It is a dense yet flexible material that comes in two sizes; 16oz. and 32oz.  

 16oz Acoustiblok is 1/8" thick and has a surface mass density of 1 lb/ft2.
 32oz Acoustiblok is 1/4" thick and has a surface mass density of 2 lb/ft2.
The manufacturer claims it is barium-free, has high UV resistance and has no fungal or algal growth.

Performance data

The ability of a partition to block the transmission of airborne sound can be described by a single number rating of the Sound Transmission Class (STC).  

 The 16oz version of Acoustiblok meets an STC of 26.
 The 32oz version of Acoustiblok meets an STC of 32.
 Adding one layer of Acoustiblok to a standard metal stud gypsum board interior wall has the potential to increase its STC rating.
 Double steel stud partition walls, faced with single layers of drywall and containing fiber-glass insulation and Acoustiblok, can achieve an STC of up to 66, according to the manufacturer.

STC is calculated using a range of frequencies similar to the human voice; attenuation in higher and lower ranges should be estimated from the Sound Transmission Loss graphs provided with standard STC reports. 

Test procedures and the formula for calculation of STC values are defined in ASTM Standards E90-02 and E413-87.

Construction applications

New Construction, Remodel/Renovation   

Acoustiblok material is typically installed in partition walls and floor/ceiling assemblies when they are stripped to the studs.

Classification

Acoustiblok is qualified for use in commercial and institutional construction by its UL Classification file, found under Fire Tests of Building Construction and Materials.  This Classification includes use in wall designs of the U300, U400, and V400 series and floor-ceiling constructions of the L500 series, as specified in ANSI/UL 263 Fire Resistance Ratings. Ratings of 1 and 2 hours can be obtained, depending on the specific partition design.

References

Noise reduction
Alan Mackworth. Alan Mackworth is a professor emeritus in the Department of Computer Science at the University of British Columbia. He is known as "The Founding Father" of RoboCup. He is a former president of the Association for the Advancement of Artificial Intelligence (AAAI) and former Canada Research Chair in Artificial Intelligence from 2001 to 2014.

Education
Mackworth was educated at the University of Toronto (B.A.Sc.), Harvard University (A.M.) and University of Sussex (D.Phil.).

Research
He works on constraint-based artificial intelligence with applications in vision, robotics, situated agents, assistive technology and sustainability. He is known as a pioneer in the areas of constraint satisfaction, robot soccer, hybrid systems and constraint-based agents. He has authored over 100 papers and co-authored two books: Computational Intelligence: A Logical Approach (1998) and Artificial Intelligence: Foundations of Computational Agents (2010).

RoboCup
Mackworth proposed and built the world's first soccer-playing robots, which led to the development of robot soccer as the premier global platform for multi-agent robotic research through the International RoboCup Foundation, where he has been honoured as "The Founding Father". Robot soccer as a challenge problem has great scientific significance. It has now become a standard test environment for cross-testing research ideas: a forum for evolving theories of multi-agent systems. Through regular international RoboCup tournaments many research teams of students and professors compete and cooperate in the development, testing and evolution of new theories and new algorithms.

Career
He served as the founding director of the UBC Laboratory for Computational Intelligence. He was president and trustee of International Joint Conferences on AI (IJCAI) Inc.; he is on the IJCAI executive committee. He has served on many editorial boards and program committees.  He was VP and president of the Canadian Society for Computational Studies of Intelligence (CSCSI). He served as president of the Association for the Advancement of Artificial Intelligence (AAAI).

Awards
Mackworth has received the ITAC/NSERC Award for Academic Excellence, the Killam Research Prize, the CSCSI Distinguished Service Award, the AAAI Distinguished Service Award, the Association for Constraint Programming Award for Research Excellence and the Lifetime Achievement Award of the Canadian AI Association (CAIAC). He is a Fellow of AAAI, the Canadian Institute for Advanced Research and the Royal Society of Canada.

References

External links
 Alan Mackworth web page

Canadian artificial intelligence researchers
Living people
Harvard University alumni
Academic staff of the University of British Columbia
Canada Research Chairs
Fellows of the Association for the Advancement of Artificial Intelligence
1945 births
Fellows of the Royal Society of Canada
Presidents of the Association for the Advancement of Artificial Intelligence
Alumni of the University of Sussex
Fleet Electronic Warfare Support Group. The Fleet Electronic Warfare Support Group's (FEWSG) mission as part of the US Navy was to provide electronic warfare simulation in a controlled environment during fleet exercises to help operators deal with EW threats, VAQ-33, VAQ-34 and VAQ-35 were the primary electronic aggressor squadrons to provide these fleet services flying the ERA-3B, EA-4F, EA-6A, EA-6B, EA-7L, EF-4B, EP-3J and NC-121K.  FEWSG also operated their own aircraft under contract, most notably EB-47E, NKC-135A and an EC-24A.  FEWSG was joined with the Fleet Deception Group Atlantic in May 1992 to form the Fleet Tactical Readiness Group (FTRG). The FTRG had an inventory of EW jammers and threat simulators for realistic training for operators.

External links 
Electronic Aircraft Variants
VAQ-33
VAQ-34
VAQ-34 - Fleet Electronic Warfare Support Group Aircraft and Assets web page
Chronology of Significant Events in Naval Aviation The First Half of the Nineties 1991-1995

United States naval aviation
Hardware bug. A hardware bug is a bug in computer hardware.  It is the hardware counterpart of software bug, a defect in software. A bug is different from a glitch which describes an undesirable behavior as more quick, transient and repeated than constant, and different from a quirk which is a behavior that may be considered useful even though not intentionally designed.

Errata, corrections to the documentation, may be published by the manufacturer to describe hardware bugs, and errata is sometimes used as a term for the bugs themselves.

History

Unintended operation

Sometimes users take advantage of the unintended or undocumented operation of hardware to serve some purpose, in which case a flaw may be considered a feature. This gives rise to the often ironically employed acronym INABIAF, "It's Not A Bug It's A Feature". For example, undocumented instructions, known as illegal opcodes, on the MOS Technology 6510 of the Commodore 64 and MOS Technology 6502 of the Apple II computers are sometimes utilized.

Security vulnerabilities

Some flaws in hardware may lead to security vulnerabilities where memory protection or other features fail to work properly. Starting in 2017 a series of security vulnerabilities were found in the implementations of speculative execution on common processor architectures that allowed a violation of privilege level.

In 2019 researchers discovered that a manufacturer debugging mode, known as VISA, had an undocumented feature on Intel Platform Controller Hubs, known as chipsets, which made the mode accessible with a normal motherboard possibly leading to a security vulnerability.

Pentium bugs
The Intel Pentium series of CPUs had two well-known bugs discovered after it was brought to market, the FDIV bug affecting floating point division which resulted in a recall in 1994, and the F00F bug discovered in 1997 which causes the processor to stop operating until rebooted.

References

Hardware bugs
Engineering concepts
McFadyen–Stevens reaction. The McFadyen–Stevens reaction is a chemical reaction best described as a base-catalyzed thermal decomposition of acylsulfonylhydrazides to aldehydes.

Dudman et al. have developed an alternative hydrazide reagent.

Reaction mechanism

The mechanism of the McFadyen–Stevens reaction is still under investigation.  Two groups have independently proposed a heterolytic fragmentation mechanism.  The mechanism involves the deprotonation of the acyl sulfonamide followed by a 1,2-hydride migration to give the alkoxide (3).  The collapse of the alkoxide results in the fragmentation producing the desired aldehyde (4), nitrogen gas, and an aryl sulfinate ion (5).

Martin et al. have proposed a different mechanism involving an acyl nitrene.

See also
 Hydrazide

References
  
  
  
  
  
  

Organic redox reactions
Rearrangement reactions
Name reactions
Load duration curve. A load duration curve (LDC) is used in electric power generation to illustrate the relationship between generating capacity requirements and capacity utilization.

A LDC is similar to a load curve but the demand data is ordered in descending order of magnitude, rather than chronologically. The LDC curve shows the capacity utilization requirements for each increment of load. The height of each slice is a measure of capacity, and the width of each slice is a measure of the utilization rate or capacity factor. The product of the two is a measure of electrical energy (e.g. kilowatthours).

A price duration curve shows the proportion of time for which the price exceeded a certain value.

Together, the price duration curve and load duration curve enable the analyst to understand the behaviour of the electricity market, for example, the likelihood of peaking power plant being required for service, and the impact that this might have on price.

Mathematically, it is a complementary cumulative distribution function.

References 

Electric power
King-Sun Fu. King-Sun Fu (; October 2, 1930–April 29, 1985) was a Chinese-born American computer scientist. He was a Goss Distinguished Professor at Purdue University School of Electrical and Computer Engineering in West Lafayette, Indiana. He was instrumental in the founding of International Association for Pattern Recognition (IAPR), served as its first president, and is widely recognized for his extensive and pioneering contributions to the field of pattern recognition (within computer image analysis) and machine intelligence. In honor of the memory of Professor King-Sun Fu, IAPR gives the biennial King-Sun Fu Prize to a living person in the recognition of an outstanding technical contribution to the field of pattern recognition. The first King-Sun Fu Prize was presented in 1988, to Azriel Rosenfeld.

Biography
Fu was born on October 2, 1930, in Nanjing, then China's capital. He received B.S. from National Taiwan University in 1953,  M.A. from University of Toronto in 1955, and Ph.D. from the University of Illinois, Urbana-Champaign in 1959.

Fu died on April 29, 1985, in Washington, DC.

Academic life
Fu and others organized the First International Conference Pattern Recognition (ICPR) in 1973 and served as chairman. The conference later evolved into the formation of the International Association for Pattern Recognition by 1976 and was elected to be its president.

He reorganized the Pattern Recognition Committee and was its first chairman in 1974,  which led to the founding of the IEEE Transactions on Pattern Analysis and Machine Intelligence (TPAMI) and he served as its first Editor-in-Chief in 1978.

King-Sun gave invited lectures in China almost every year over the past decades and was a Member of the Academia Sinica in 1978. He was instrumental in establishing the Microelectronics and Information Science and Technology Research Center at the National Chiao Tung University in 1984.

Selected works
 1968. Sequential Methods in Pattern Recognition. Academic
 1970. Sequential Methods in Pattern Recognition and Machine Learning. New York: Academic
 1974. Syntactic Methods in Pattern Recognition. New York: Academic. 
 1980. Statistical Pattern Classification Using Contextual Information.  Wiley
 1982. Syntactic Pattern Recognition and Applications. Prentice-Hall

See also
 Syntactic pattern recognition

References

1930 births
1985 deaths
American computer scientists
Chinese emigrants to the United States
Computer vision researchers
Fellows of the IEEE
Members of Academia Sinica
Members of the United States National Academy of Engineering
National Taiwan University alumni
Purdue University faculty
Scientists from Nanjing
Taiwanese people from Jiangsu
University of Illinois Urbana-Champaign alumni
University of Toronto alumni
Core Multiplexing Technology. Core Multiplexing Technology is a term that appeared in some BIOSes.

Details
A subset of traditional applications are often difficult to parallelize and make use of additional CPU hardware available on the platform, restraining applications to use only one CPU. Core Multiplexing Technology would allow for a process to be split into multiple threads at compilation time and execution time by the introduction of speculative multithreading.

Much in the same way a branch predictor allows for a processor to speculate on the outcome of a branch operation without actually performing the operation, speculative multithreading allows for the processor to speculate deeper, executing entire branches of code on an additional core. Most of the implementation is done in software, with the compiler rearranging code to take better use of a multithreaded platform, which allows Simultaneous multithreading (SMT) and Multicore systems (or a combination of the two) to take advantage of the technology. But, because the data dependencies of speculative multithreading, and the necessity to manage inter-thread dependent data, hardware implementation must be taken into consideration.

Core Multiplexing Technology is thought to leverage Intel's Advanced Smart Cache technology of the upcoming Core 2 chips, which allows two cores to share a single L2 cache, and actively resize the cache between the two processors if one is idle, by allowing the two cores to share data to manage inter-thread dependent data.

See also
3Server
Apulet
BINAC

External Resources
Intel Research on Speculative Multithreading
Coverage of Core Multiplexing Technology BIOS Option

BIOS
Lockstep (disambiguation). Lockstep is a kind of marching that involves all marcher's legs moving in the same way at the same time.

Lockstep or lock step may also refer to:

 Lockstep (computing), a term used in fault-tolerant computing
 Lockstep protocol, a protocol that tackles the look-ahead cheating problem in peer-to-peer gaming networks
 Lockstep compensation, a form of employee compensation based purely on seniority
 Lock step (dance move), dance steps which involve the "locking" of the moving foot
 Lockstep, a science fiction book written by Karl Schroeder
ODVA (company). ODVA, Inc. (formerly Open DeviceNet Vendors Association, Inc.) was founded in 1995 and is a global trade and standard development organization whose members are suppliers of devices for industrial automation applications. To qualify for membership in ODVA, applicants must be an entity that makes and sells products using ODVA technologies.

ODVA technologies include the Common Industrial Protocol or "CIP" - ODVA's media-independent, object-oriented protocol - along with ODVA's network adaptations of CIP - EtherNet/IP, DeviceNet, ControlNet, and CompoNet. ODVA has more than 15 technical working groups, overseen by its Technical Review Board, which develop and enhance ODVA's implementation specifications for its technologies.  These specifications define how a product shall be designed in accordance with the specifications.  ODVA maintains a conformance testing practice to validate that products designed using ODVA technologies comply with the specifications and interoperate in multivendor systems.  ODVA also provides other services to its members to promote the adoption of ODVA technologies by industry.

ODVA is a US 501(c)6 corporation incorporated in the state of Wisconsin.  Its headquarters are in Ann Arbor, Michigan U.S.  It also has conformance test service providers in North America, China, Germany, and Japan.

References

External links
 ODVA.org

Computer network organizations
Robert B. Ferguson Museum of Mineralogy. The Robert B. Ferguson Museum of Mineralogy is a museum in Winnipeg, Manitoba, Canada, located at the University of Manitoba in the Wallace Building.

The museum got its start in 1918 by way of a donation from geologist Joseph Winthrop Spencer. His 1,100 mineral and rock specimen formed the basis of the early museum. The museum has grown over the years through various donations.

Part of the collection is on display for the benefit of students. One sixth of the collection is displayed in the Wallace Building, and is arranged from the most chemically and structurally simple to progressively more complex.

Many of the most attractive mineral specimens are on public display at the Ed Leith Cretaceous Menagerie.

Affiliations
The Museum is affiliated with: CMA,  CHIN, and Virtual Museum of Canada.

References

External links
 (Archived from the original on April 16, 2012)

Museums in Winnipeg
University museums in Canada
Natural history museums in Manitoba
Geology museums in Canada
1918 establishments in Manitoba
University of Manitoba
MassCREST. MassCREST stands for Massachusetts Center for Renewable Energy Science and Technology at the University of Massachusetts Amherst.  It brings together complementary expertise in molecular design and synthesis, physical characterizations, device fabrications and theoretical modeling from at least five different departments within UMass Amherst.

Using their expertise in soft materials and in soft-hard material interfaces, MassCREST researchers are focusing on developing efficient solar cells  and fuel cells, producing hydrogen from water using enzymes and developing catalysts for the conversion of biomass to hydrocarbon fuels.

External links
 MassCREST website 
 Energy Research at MassCREST 
 Participating Faculty at MassCREST 
University of Massachusetts Amherst
Society of Tribologists and Lubrication Engineers. The Society of Tribologists and Lubrication Engineers (STLE) is an American non-profit technical society for the tribology and lubrication engineering sectors worldwide. Its offices are in Park Ridge, Illinois.

Established in 1944 as the American Society of Lubrication Engineers (ASLE), the STLE is now one of the world's largest associations solely dedicated to the advancement of the field of tribology. The STLE currently has over 13,000 members. 

An official STLE journal, Tribology Transactions, is published by Taylor and Francis and the society is also affiliated with Tribology Letters, published by Springer. The STLE also publish a monthly magazine, Tribology and Lubrication Technology.

References

Engineering societies based in the United States
Mechanical engineering organizations
International professional associations
Non-profit organizations based in Chicago
Tribology
Instruction unit. The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetched from memory, and executed, in an appropriate order, and for forwarding them to an execution unit (E-unit or EU). The I-unit may also do, e.g., address resolution, pre-fetching, prior to forwarding an instruction. It is a part of the control unit, which in turn is part of the CPU.

In the simplest style of computer architecture, the instruction cycle is very rigid, and runs exactly as specified by the programmer. In the instruction fetch part of the cycle, the value of the instruction pointer (IP) register is the address of the next instruction to be fetched. This value is placed on the address bus and sent to the memory unit; the memory unit returns the instruction at that address, and it is latched into the instruction register (IR); and the value of the IP is incremented or over-written by a new value (in the case of a jump or branch instruction), ready for the next instruction cycle.

This becomes a lot more complicated, though, once performance-enhancing features are added, such as instruction pipelining, out-of-order execution, and even just the introduction of a simple instruction cache.

See also
Branch prediction and the branch prediction buffer
Branch target predictor and the branch target buffer
Branch delay slot
Instruction scheduling
Instruction selection
Data dependency or data hazard
Scoreboarding
Very long instruction word (VLIW)
Superscalar processor
Opcode
Analysis of Instruction parallelism, Instruction frequencies, Instruction mix
Instruction path length or Instruction count

References

Central processing unit
Hartha. Hartha is a town in the district of Mittelsachsen, in Saxony, Germany. It is situated 11 km west of Döbeln, and 12 km north of Mittweida.

Personalities 
 Carl Grünberg (1847–1906), woven goods manufacturer in Hartha and politician (SPD), MdR, MdL (Kingdom of Saxony)
 Hans Jahn (1885–1960), politician of the Social Democratic Party of Germany, trade unionist and resistance fighter against the National Socialism
 Richard Müller (chemist) (1903–1999), chemist, discoverer of the silicone, Müller-Rochow synthesis

References 

Mittelsachsen