This work presents a compact and low power bandgap voltage reference design using self-biased cur- rent mirror circuit. This design eliminates the standard complementary-to-absolute-temperature (CTAT) bipolar device in the voltage-reference branch, reducing the bipolar area by /two.pnum/zero.pnum percent. Instead, the design shares the same bipolar device in the main CTAT branch for generating the reference voltage. An additional bene/uniFB01t of eliminating the voltage-reference branch is the reduction of total power consump- tion by approximately /three.pnum/zero.pnum percent. This novel topology reduces power and area of the core bandgap reference circuit without compromising temperature drift performance. Designed, fabricated and func- tionally tested in a 0:6mCMOS process. The simulation result shows the temperature coe/uniFB03cient of this design is 6:3ppm=Cfor a temperature range of 40Cto125C. This bandgap reference design occupies a silicon area of 0:018mm2and draws an average quiescent current of 2Afrom a supply voltage of 3:35V. The simulated /uniFB02icker voltage noise is 4:34V=p Hzat10Hz. /one.pnum Introduction Voltage reference circuits are an essential block in most applications from a simple integrated circuit (IC) to a large System-on-Chip (SoC) ranging from purely digital circuits to mixed-signal applications such as Analog to Digital converters (ADCs), Digital to Analog converters (DACs), phase locked loops (PLLs), low noise ampli/uniFB01ers (LNAs), digital multimeters, battery chargers, low-power IoT sensor nodes, portable data acquisition systems and so on. Since the /uniFB01rst bandgap reference (BGR) circuit introduced by Robert Wid- lar Widlar (/one.pnum/nine.pnum/seven.pnum/zero.pnum), BGR has been widely used since it provides a well-de/uniFB01ned voltage reference with a very weak dependence on process, voltage and temperature. Most analog and mixed-signal circuits also re- quire a current reference that sets the internal bias current for the circuits. The BGR can also provide a reference current directly which has positive temperature co-e/uniFB03cient (PTC). For most bias currents, a PTC reference current is su/uniFB03cient. For circuits demanding more stable current reference can achieve so with some additional circuits Ji et al. (/two.pnum/zero.pnum/one.pnum/seven.pnum). Figure /one.pnum, shows two type of traditional BGR circuit: (a) one using operational ampli/uniFB01er (Op-Amp) and (b) using self-biased current mirror circuit Wu et al. (/two.pnum/zero.pnum/zero.pnum/seven.pnum). The principle of operations is the same in both cases where the nodes AandBare forced to be the same by (a) the Op-Amp or (b) the self-biased current mirror. Forcing same node voltages makes the voltage drop across R1be exactly di/uniFB00erence between the base-to-emitter voltage VBEof the two bi-polar transistor provided that, the size of the transistor Q1= NQ2. The voltage across the resistor R1produces a proportional-to-absolute-temperature (PTAT) voltage, which is multiplied with a suitable constant and added to VBEofQ3to generate a stable voltage Allen and Holberg (/two.pnum/zero.pnum/one.pnum/two.pnum) as follows: VREF =VBE3+R2 R1VTln (N) (/one.pnum) Where,VREF is the output reference voltage and VTis the thermal voltage of the semiconductor. Typically, Op-Amp based BGR is preferred over self-biased for better power supply rejection (PSR) perfor- mance and lower supply requirement. Although the self-biased BGR may have a lower performance in those two metrics, it is a simpler design consuming less area and power while achieving almost similar 1 Figure /one.pnum: Traditional BGR circuits; (a) using Op-Amp, (b) using self-biased current mirror temperature drift performance. In most IC or SoC designs the self-biased BGR performance may su/uniFB03ce allowing less design time, lower risk, lower area and power which is always desirable for any SoC design. Moreover, the PSR in a self-biased BGR can be improved by using cascode current mirrors Wu et al. (/two.pnum/zero.pnum/zero.pnum/seven.pnum) or symmetric biasing of both the branches Lam and Ki (/two.pnum/zero.pnum/one.pnum/zero.pnum). In this paper an improved self-biased based bandgap reference circuit has been proposed which further lowers the area and power of the reference circuit while preserving the temperature coe/uniFB03cient performance. The improved circuit generates the ref- erence voltage without using the separate reference-voltage branch as in the traditional self-biased BGR. This paper is organized as follows: Section II describes the proposed architecture of the BGR along with its design procedure and circuit implementation. Simulation and measurement results are presented in Section III, followed by a conclusion in Section IV. /two.pnum Proposed bandgap reference Figure /two.pnum shows the core part of the proposed bandgap reference circuit. As evident from the /uniFB01gure, this modi/uniFB01ed circuit avoids a bi-polar device in the reference branch. Here the BJT Q2used for dual purpose; /uniFB01rstly, it helps for generating a PTAT voltage across resistor R1and secondly, voltage across this adds with voltage across R2for generating reference voltage VREF at the output node. This elegant modi/uniFB01cation in the traditional self-biased current mirror based BGR provides some great advantages particularly in power consumption and silicon area of the core circuit. These advantages are; •Since we eliminate the standard voltage-reference branch, the bi-polar device area reduces by ap- proximately /two.pnum/zero.pnum percent and the PMOS current-mirror area reduces by approximately /three.pnum/zero.pnum percent. Note that, bi-polar devices and the current mirrors are a signi/uniFB01cant portion of the core BGR area., •One-third of the total current is reduced in the core BGR and therefore one-third reduction in power consumption in the core BGR circuit as well. The self-biased current mirror uses two P-MOS transistor MP 1,MP 2and two N-MOS transistor MN 1, MN 2. These four transistor forms the self-biased feedback loop which makes the node voltages at Aand Bequal.The second branch of the circuit uses a single bi-polar device Q2, which produces a CTAT voltage VBE2across the BJT Q2, whereas, in the /uniFB01rst branch, four parallel BJTs are connected with a resistor R1 in series. As both the node voltages at AandBare same and current /uniFB02owing through both the BJTs are /two.pnum Figure /two.pnum: Core part of the proposed self-biased current mirror based BGR same, a PTAT voltage dVBE=VBE2VBE1produced across resistor R1, whereVBE1is voltage across the four parallel BJTs Q1. AsVBE2is a CTAT voltage and dVBEis a PTAT voltage, so addition of CTAT voltage with some appropriate constant multiplication of the PTAT voltage will generate a reference voltage which will be zero temperature coe/uniFB03cients at a reference temperature. The power-supply rejection (PSR) performance does not change signi/uniFB01cantly from the traditional self- biased BGR. The PSR can be improved by using cascode current mirrors Wu et al. (/two.pnum/zero.pnum/zero.pnum/seven.pnum) or symmetric biasing of both the branches Lam and Ki (/two.pnum/zero.pnum/one.pnum/zero.pnum). Our proposed integration of reference branch will also work with symmetric biasing as shown in Lam and Ki (/two.pnum/zero.pnum/one.pnum/zero.pnum). /two.pnum./one.pnum Design Procedure of improved BGR In this section, the expressions to calculate the resistance values of the core BGR circuit for a current value will be shown. For a low power BGR, Q1andQ2were each biased with 1A. Given the bias current, R1 can be expressed as: R1=VTln (4) I1(/two.pnum) WhereVTis the thermal voltage of the semiconductor and its value at room temperature is approximately 25:8mV. Applying the values of VTandI1in Equation /two.pnum, R1evaluates to 35:76k . The reference voltage can be calculated by combining the voltage across the BJT Q2(CTAT in nature) and voltage across the resistor R2(PTAT in nature) as; VREF =VBE2+VR2 (/three.pnum) Where,VR2is the PTAT voltage across resistor R2and can be expressed as: VR2=R2 R1VTln (4) (/four.pnum) /three.pnum Figure /three.pnum: Complete schematic diagram of the proposed BGR circuit Figure /four.pnum: Implementation of the /five.pnum-bit trimmable resistor R2 Equation /three.pnum can be rewritten as; VREF =VBE2+ VT (/five.pnum) Where, = (R2=R1)ln (4) is a constant. For calculating zero temperature coe/uniFB03cient reference voltage at the reference temperature, the derivative ofVREF should be zero. dVREF dT=d(VBE2+ :VT) dT= 0 (/six.pnum) Using@VBE2=@T =1:6mV=Cand@VT=@T = 85V=CAllen and Holberg (/two.pnum/zero.pnum/one.pnum/two.pnum) in Equation /six.pnum, evaluates to 18:82and using Equation /five.pnum, VREF evaluats to 1:155V For this modi/uniFB01ed architecture the current /uniFB02owing through resistor R2is half of that current /uniFB02owing in resistorR1. So the constant for this circuit will be; =R2 2R1ln (4) (/seven.pnum) Applying andR1values in Equation /seven.pnum, R2evaluates to 971k . /four.pnum Figure /five.pnum: Simulation result: VREF-vs-Temperature (Tempco). /two.pnum./two.pnum Implementation of complete BGR Figure /three.pnum shows the complete implementation of the proposed BGR. MP 13,MN 12,R12, andQ12 forms the core part of the bandgap and the value of the resistors are calculated in the previous sub-section. MPS 12andMNS 1form the start up circuitry since there are two stable states. MPBtransistors are the PTAT current sources for biasing internal circuits. MN 12are biased in the deep-sub-threshold (weak in- version) region to provide the maximum gm=IDfor given bias current Harrison and Charles (/two.pnum/zero.pnum/zero.pnum/three.pnum), which ensures the voltages of node AandBare only o/uniFB00set by the VTmismatch of the MN 12and the sys- tematic o/uniFB00set of I1andI2. Typically,gm=ID>20ensures deep-sub-threshold operation. Please note that, this o/uniFB00set is similar to a o/uniFB00set in a Op-Amp based BGR where the input referred o/uniFB00set of the Op- Amp is dominated by the VTmismatch of the input pair of the di/uniFB00erential ampli/uniFB01er which also biased in deep-subthreshold region for low-power application. PMOS current mirrors MP 13andMPBare biased in saturation region where gm=IDis typically less than /one.pnum/zero.pnum Harrison and Charles (/two.pnum/zero.pnum/zero.pnum/three.pnum), to ensure the minimum systematic o/uniFB00set in I1andI2. As mentioned before, this systematic o/uniFB00set can be minimized by using cascode current mirrors Wu et al. (/two.pnum/zero.pnum/zero.pnum/seven.pnum) or sym- metric biasing of both the branches Lam and Ki (/two.pnum/zero.pnum/one.pnum/zero.pnum). The unit sizes of Q1andQ2are chosen to be the minimum allowable in the implemented technology and the ratio between them is chosen such that the area ofQ12andR12is minimized. For the implemented technology, the BJT ratio 4 : 1 was found to be optimum. A high-sheet-rho poly resistor ( Rsheet = 3:76k =sq) was chosen to minimize the resistor area. In order to trim the output temperature coe/uniFB03cient (TC) of the BGR after fabrication, R2is a /five.pnum-bit programmable resis- tor is used as shown in Figure /four.pnum, which is programmed through an Inter-IC Communication (I/two.pnumC) protocol with a range of 890940k . Each of the programmable resistor in R2is made of series-parallel combina- tion of unit resistors of 20k .R1is also constructed from combination of same unit resistors so they can be matched in layout with R2. During startup, MPS 2ensures that the current mirror is pulled out of the zero-Vgsstate and once the circuit is operating normally (VREF1:155) , the voltage drop across MNS 1 should be high enough that it shuts OFF MPS 2.MNS 1needs to be sized such that there is no leakage current during normal operation. MPS 1provides a trickle current for MNS 1andMNS 1is sized with a very long length transistor to provide a large voltage drop for the minimum amount of current. For layout, special care is taken to match MP 13,MN 12,R12, andQ12which a/uniFB00ects the TC directly. /five.pnum Figure /six.pnum: Simulation result: VREF versus Temperature for di/uniFB00erent R2trims. Parameters Value Technology /zero.pnum./zero.pnum/six.pnum mCMOS Power Supply Voltage 3:35V Temperature range 40Cto125C Reference voltage VREF) 1:15V Temperature coe/uniFB03cient 6:3ppm=C Line regulation 16mV=V Flicker noise @ /one.pnum/zero.pnumHz /four.pnum./three.pnum/four.pnum V=p Hz PSR @ DC//one.pnumHz /four.pnum/zero.pnumdB//three.pnum/five.pnumdB Table /one.pnum: Summary of the Simulation Results. /three.pnum Simulation and measurement results /three.pnum./one.pnum Simulation results The improved self-biased bandgap reference has been simulated with a commercially available Spectre simulator using the Process Design Kit (PDK) from the foundry. The /uniFB01rst order temperature drift perfor- mance is simulated over the entire temperature range of 40Cto125C. A simulated reference voltage (VREF)versus temperature curve is shown in Figure /five.pnum. The calculated temperature coe/uniFB03cient (TC) from the /uniFB01gure is 6:3ppm=C. Figure /six.pnum, shows the para- metric plot of VREF versus temperature at all /three.pnum/two.pnum (/five.pnum-bit) trimming resistance values. The simulated PSR performance at room temperature for the improved BGR circuit is about /four.pnum/zero.pnum dB at DC and /three.pnum/five.pnum dB at /one.pnum kHz. The noise performance at room temperature is 4:34V=p Hzat /one.pnum/zero.pnum Hz and 1:47V=p Hzat /one.pnum/zero.pnum/zero.pnumHz which is dominated by the /uniFB02icker noise of current-mirrors, MN 12(/four.pnum/six.pnum percentage) and MP 13(/five.pnum/two.pnum percentage). The simulated average quiescent current is about 2Aover the temperature range of 40Cto125C. Table /one.pnum summarizes the simulation parameters in and its corresponding simulated values. /three.pnum./two.pnum Test setup and measurement results This work has been fabricated in a commercially available 0:6m CMOS technology. The proposed work has been integrated to provide bias voltage to other blocks inside the chip. Figure /seven.pnum shows the chip micro- graph with highlighting the proposed BGR and its corresponding layout view. The whole BGR consumes 0:018mm2of silicon area inside the chip. /six.pnum Figure /seven.pnum: Chip micrograph and Layout of proposed BGR. Figure /eight.pnum: Test Setup for the functional veri/uniFB01cation of the fabricated BGR. /seven.pnum Figure /nine.pnum: Tempco Plot: Measurement and Simulation. Figure /one.pnum/zero.pnum: Line Regulation: Measurement and Simulation. At the time of this writing, ability to do a full temperature characterization using an environmental cham- ber along with R2trimming through I2C was unavailable. A functional test of the fabricated BGR was done using the test setup as shown in Figure /eight.pnum with the R2set to the default value. For the functional test, the packaged silicon chip is mounted on a temporary prototype board to test the functionality. We used a bu/uniFB00er (OP-/nine.pnum/zero.pnum) at the output of chip to avoid loading from the low-impedance measurement de- vice. A hot air stream was used to heat the device to temperatures between 25Cto100Cfrom the top side of the chip. The temperature was changed by changing the distance between the source of the hot air stream and the device. The output of the BGR was measured using high precision (/six.pnum-/one.pnum//two.pnum digit) voltage meter (Keysight /three.pnum/four.pnum/four.pnum/six.pnum/one.pnumA). After each temperature value settled, the temperature of the device was mea- sured using a mounted laser-guided infrared thermometer. The device was powered using a programmable power supply (Keysight E/three.pnum/six.pnum/three.pnum/one.pnumA) Figure /nine.pnum shows the measurement result of output voltage versus temperature. As seen from the result, the untrimmed temperature coe/uniFB03cient is strongly PTAT in nature ( 115ppm=C). Some of the random mismatch pairs that could contribute to this are MP 23,R1andR2ratio,Q12andMN 12as well. In simulation, when R2is increased by /six.pnum./five.pnum percentage and VTo/uniFB00set value of VT=p Ais applied between MP 23andMN 12the simulation results match the test result as shown in Figure /nine.pnum /eight.pnum For the same o/uniFB00sets added as for the tempco simulation, the line regulation in both simulations and mea- surements match closely showing a line regulation of 16mV=V as shown in Figure /one.pnum/zero.pnum. On availability of an environment chamber, we will be able to get to the root of the tempco response by doing accurate temperature characterization for di/uniFB00erent R2trim values. /four.pnum Conclusion In this paper, a self-biased based BGR was improved for area and power by eliminating the reference- voltage branch and integrating it in the main core without compromising temperature drift performance. By using the CTAT voltage in the core of the BGR to generate the reference voltage ( VREF ), the power consumption of the core and area of the BJTs reduces by /three.pnum/three.pnum percent and /two.pnum/zero.pnum percent respectively. The BGR is implemented in a /zero.pnum./six.pnum- m CMOS process with an area of 0:018mm2that includes the core bandgap and bias currents. This architecture greatly simpli/uniFB01es the design complexity with a temperature coe/uniFB03cient of 6:3ppm=Cfor a temperature range of 40Cto125Cfrom simulation. The simulated PSR is /three.pnum/five.pnum dB at /one.pnumkHz which can be improved by using the cascode self-biased current mirror. This architecture gives a spot noise of 4:34V=p Hzdominated by the /uniFB02icker noise of NMOS and PMOS current-mirrors. The /uniFB02icker noise can be reduced by increasing the area of those devices or chopping the current mirror.