ZigBee is a wireless standard deﬁned for low data rate applications with ultra-low power requirements. Devices based on this standard are expected to be low cost with a large battery life or use energy harvesting techniques. As a part of a major project for developing a fully functional RF transceiver chip complying with the standard, frequency synthesizers have been designed based on integer-N phase lock loops which are expected to work as local oscillators for both the transmitter and the receiver. The standard required the PLLs to be programmable to 16 channels in the 2.4-2.5 GHz range. One of the PLLs used an LC VCO while the other used a ring VCO. This work was meant to test these PLLs to make sure that they met the speciﬁcations required of them as per the standard. ii TABLE OF CONTENTS ACKNOWLEDGEMENTS i ABSTRACT ii LIST OF TABLES v LIST OF FIGURES vii ABBREVIATIONS viii 1 Introduction 1 1.1 PLLs as Frequency Synthesizers . . . . . . . . . . . . . . . . . . . 1 1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 The ZigBee Standard and an Introduction to PLLs 3 2.1 The ZigBee Standard . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1.1 System Speciﬁcations . . . . . . . . . . . . . . . . . . . . 3 2.2 Phase Lock Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.1 Type II PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Implementation of the Ring VCO 8 3.1 VCO Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Ring VCO Architecture . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3.1 Differential Ring Oscillator . . . . . . . . . . . . . . . . . 9 3.4 VCO Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4.1 Choice of Delay Cell . . . . . . . . . . . . . . . . . . . . . 9 3.4.2 Delay Cell Tuning . . . . . . . . . . . . . . . . . . . . . . 10 3.4.3 Tuning Circuit . . . . . . . . . . . . . . . . . . . . . . . . 14 iii 3.5 Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.1 Gilbert Multipliers . . . . . . . . . . . . . . . . . . . . . . 15 3.5.2 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Implementation of the PLL 19 4.1 Fixed gmBias Generation . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.1 Basic Fixed gmBias Cell . . . . . . . . . . . . . . . . . . . 19 4.1.2 Improved Fixed gmBias Cell . . . . . . . . . . . . . . . . . 20 4.2 Programmable Frequency Divider . . . . . . . . . . . . . . . . . . 21 4.2.1 Implementation of a 2/3 Divide Cell . . . . . . . . . . . . . 22 4.2.2 Implementation of the Divide Chain . . . . . . . . . . . . . 23 4.3 Differential to Single-ended Converter . . . . . . . . . . . . . . . . 24 4.4 Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . 24 4.5 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 PCB Design and IC Characterization 27 5.1 IC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 IC Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.1 VCO Measurements . . . . . . . . . . . . . . . . . . . . . 28 5.2.2 PLL Measurements . . . . . . . . . . . . . . . . . . . . . . 33 5.3 Problems Encountered . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 Problems with the Chip . . . . . . . . . . . . . . . . . . . . 34 5.3.2 Problems with the PCB . . . . . . . . . . . . . . . . . . . . 35 5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 A PCB Design 36 A.1 PCB Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 A.1.1 Frequency Synthesizer Chip Schematic . . . . . . . . . . . 36 A.1.2 Bias,