Vijaykrishnan Narayanan. Vijaykrishnan Narayanan is the A. Robert Noll Chair Professor of Computer Science and Engineering and Electrical Engineering, Evan Pugh University Professor and the Associate Dean for Innovation at The Pennsylvania State University. He also serves as the director of the Penn State Center for Artificial Intelligence Foundations and Engineering Systems, and as the interim director of limited submission for the University's Office of the Senior Vice President of Research.

Joining Penn State in 1998 as an assistant professor, Vijay has become an international expert in computer architecture. His research and teaching interests encompass embedded and mobile computing systems design, power- and reliability-aware design, emerging computing technologies, application-specific systems, on-chip networks, and design automation.

He received his bachelor's degree in Computer Science and Engineering from the University of Madras, India, in 1993, and his Ph.D. in Computer Science and Engineering from the University of South Florida, USA, in 1998. Vijay is a co-director of the Microsystems Design Lab and a Fellow of the National Academy of Inventors, IEEE, and ACM

Biography

Education
Vijaykrishnan Narayanan received his B.E.(Bachelor of Engineering) in Computer Science and Engineering from University of Madras in 1993, and his Ph.D. in Computer Science and Engineering from the University of South Florida in 1998, respectively.

Career
Vijaykrishnan Narayanan joined the faculty of the Pennsylvania State University as an assistant professor in 1998. He was promoted to the rank of full professor in 2007. Vijaykrishnan Narayanan has worked in the area of power-aware design. With colleagues at Penn State, he developed architectural level power simulators, SimplePower and SoftWatt. He has developed application-specific architectures, including the design, implementation, and field-testing of board level designs for DARPA DESA and DARPA Neovision2 programs.

Research 
Dr. Narayanan's research focuses on power-aware computer systems. Excessive power consumption is a key limiter to the design of modern computer systems ranging from large data centers to tiny and pervasive embedded internet of things. His research has addressed the power challenges in several intersecting domains such as the design of power-efficient computing systems, the design of application specific processors, the design of multicore architectures using emerging technologies like 3D stacking and nanotechnology, and the development of methodologies to understand interplay between performance, power and reliability. His election as Fellow of IEEE and ACM, the two major professional societies in Electrical Engineering and Computer Science, respectively, cite his contributions to power-aware computing.

Dr. Narayanan developed open-access tools and simulation models (downloaded by 100’s) for designing energy-efficient computing systems. He co-led the design of the Simplepower tool, which was the first input-sensitive, architectural-level power estimation framework meaning that it could be used for early-stage design exploration, even before logic design and circuit layout. His subsequent work provided deep insights to the power contribution of individual components such as the clock network (the 2002 IEEE Transactions on VLSI best paper), His work helped reveal the important role of software on power optimization resulting in joint innovations with Industry such as the first energy-efficient embedded Java virtual machines including energy-aware memory management and garbage collection techniques (with Sun Microsystems) and transaction-level power modeling (with IBM). In work that received the ASPDAC Ten-Year Retrospective Most Influential Paper Award in 2012, Vijay proposed new techniques for controlling runtime leakage power. His work developed the first (Computer Aided Design) techniques to address leakage power reduction in FPGAs (with Xilinx, the leading FPGA company) and received a most significant retrospective award in 25 years of Field programmable logic conference. 

With concerns of slowing down of CMOS transistor size (down) scaling, Narayanan's work started exploring two new directions - one on design of domain specific acceleration and another on design using emerging device technologies for memory and compute. Since emerging devices are often not drop-in replacements for CMOS or offer unique characteristics to leverage at higher levels of abstraction, Narayanan’s unique cross layer explorations spanning the entire computing stack – devices, circuits, architecture, and systems was recognized with the IEEE Computer Society Technical Achievement Award. His work is shaping industry directions through contributions to Semiconductor Industry (SRC/SIA) decadal planning, and NIST/SRC benchmarking efforts. The National Security Agency recognized his effort for promoting excellence in scientific research and the National Science Foundation highlighted his research contributions twice in its annual report. His contributions to design of non-volatile processors for energy-harvesting systems was named an IEEE Micro Top Pick.

Dr. Narayanan’s research has involved extensive interdisciplinary and multi-institutional collaborations. In the DARPA Neovision program, his team demonstrated brain-inspired vision systems that reduced power consumption of contemporary state-of-the-art by two orders of magnitude. Students trained in this project, currently lead commercial AI system design in Google, IBM, Intel and Meta. The commercial and societal impact of embedded vision systems for commercial (shopper insights), defense (autonomous weapons) and societal impact (assistive technologies) developed by Narayanan are cited in his election as Fellow of National Academy of Inventors. His work on an NSF expeditions-in-computing project resulted in simultaneous advances in computer vision, hardware, human-machine interface and neuroscience to enable a new generation of assistive vision technologies that enable independent shopping for persons with visual impairments.  Narayanan’s recent work involves partnership with leading semiconductor companies (Intel, IBM. Global Foundries, Samsung and Micron) towards replacing the 50 year von Neumann computing paradigm that treats memory and processing distinct through novel processing-in-memory systems.

In qualitative metrics, Dr. Narayanan has an H-index of eighty-six with 29133 citations. He has received seven best paper awards and two “test-of-time” awards

Service to the Computing Community

Dr. Vijaykrishnan Narayanan is an accomplished academic and researcher in the fields of electronic design automation (EDA), VLSI design, and computer architecture. He has made significant contributions through his leadership roles in various technical committees and editorial positions.

Narayanan has served as the elected chair of the ACM Special Interest Group on Design Automation, overseeing technical conferences in EDA. His editorial roles include editor-in-chief of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2014-2017) and founding co-editor-in-chief of the ACM Journal on Emerging Technologies in Computer Systems (2003-2009). Additionally, he has been an associate editor for prestigious journals such as IEEE Transactions on VLSI and the Journal of Low Power Electronics.

In his conference leadership roles, Narayanan has served on advisory and executive committees, including for the Design Automation Conference and the IEEE Computer Society Annual Symposium on VLSI. He co-chaired the International Symposium on Low Power Electronics and Design and has been involved in the steering committees of various conferences on VLSI and EDA.

Narayanan has contributed as an expert reviewer for numerous international research funding agencies, including the National Research Foundation (Singapore), European Union, U.S. Department of Energy, and the National Science Foundation. He also co-led workshops on hardware support for Java microarchitectures, influencing technology now prevalent in mobile and embedded devices.

His service to the academic and research community includes roles in IEEE, such as chairing the IEEE CS Technical Committee on VLSI and being a member of the IEEE CEDA Publications Board.

Student Advised 
Total Number of Students Supervised: 54 Ph.D. 72 Masters students

Students have won prestigious fellowships during their course of graduate study under Narayanan including IBM fellowship, Alfred Sloan Fellowship, GEM Scholarship and CAC Fellowship. Two of his advisees won the Best Dissertation Award, a global recognition given by the European Design Automation Association. His former students have been successful in academia, entrepreneurship and industry (examples – Tenured Associate Professor (KAIST, Korea;), Principal Engineers (Samsung) and successful entrepreneurs (EDAplayground). He has been a major driver for diversity with multiple African-American and women students that he has mentored. His students won the 2016 IEEE Computer Society Global Student Competition for their entry on ‘Computer Vision for assisting Visually Impaired

Personal life

Honors and awards

A list of all his awards follows.

 2024 AAAS Fellow, elected for contributions to the field of computer architecture and design  automation, particularly for power-aware systems and emerging technologies
 2023 Commendation in Joint Press Release by United States and India released by the White House for the India-U.S. Defense Acceleration Ecosystem (INDUS-X) team. Dr. Narayanan serves as the lead U.S. coordinator for Academic Collaborations for Defense Startups.
 2023 Editors Pick Paper, Biomedical Optics Express Journal
 2022 Micro Hall of Fame, ACM/IEEE International Symposium on Microarchitecture
 2022 ACM SIGDA Distinguished Service Award
 2021 IEEE Computer Society TCVLSI Distinguished Research Award
 2020 Fellow, National Academy of Inventors
 2021 IEEE Computer Society Edward J. McCluskey Technical Achievement Award
 2020 Northeastern Association of Graduate Schools Geoffrey Marshall Mentoring Award
 2019 Nanoarch Best Student Paper
 2018 IEEE CEDA Distinguished Speaker
 2018 IEEE CEDA Outstanding Service Award 
 2017 IEEE Transactions on Multi-Scale Computing Systems Best Paper Award.
 2017 Invited Lecturer, Global Initiative of Academic Network, Ministry of Human Resource Development, Government of India.
 2017 IEEE/ACM ASPDAC Best Paper Award
 2016 Invited demonstration (only one selected nationally by Computing Research Association) at The 22nd Annual Coalition for National Science Funding (CNSF) Exhibition & Reception on Capitol Hill
2016 Invited Technology Speaker, China (Beijing) International Technology Transfer Convention, hosted by China Ministry of Science and Technology and Beijing Municipal People’s Government
2016 Big Ten Network Television Network coverage on “Visual Cortex on Silicon” Project
2016 IEEE Micro's Top Picks.
2015 Most significant paper award for influencing theory and practice in the area of Field Programmable Logic and Applications among those published over the last 25 years
2014 ACM Fellow elected for contributions to Power-Aware Design
2015 IEEE HPCA Best Paper Award
2014 Invited Participant at US White House Brain Conference
2012 Penn State Engineering Alumni Society (PSES) Premier Research Award
2012 ASPDAC 10-year Retrospective Most Influential Paper Award
2011 IEEE Fellow, elected for contributions to Power-Aware Design
2010 Outstanding Alumni Award, Sri Venkateswara College of Engineering, India
2009 The NSF CRI Project (PI: Narayanan) on soft errors was featured as a selected investment by National Science Foundation and described as “One of a Kind Test Facility to Reduce Chip Errors,”.  2009 NSF  HoDoo  Project  (PI:  Narayanan)  was  selected  by  NSF  Computing  and Communications Foundations program cluster as one of the featured projects on the NSF Web site.
2006 PSES Outstanding Research Award
2006 ICA DSN Best Paper Award
2003 IEEE/CAS VLSI Transactions Best Paper of the Year Award
2002 Penn State CSE Outstanding Faculty Teaching Award
2001 NSF CAREER Award
2000 The ACM SIGDA Outstanding New Faculty Award

References

External links
 Home Page

Year of birth missing (living people)
Living people
American computer scientists