MIPS处理器列表

这是一个基于MIPS指令集架构的列表，其中包括推出年份、制程大小、频率、裸晶尺寸等基本信息。这些处理器是被 Imagination Technologies、MIPS科技公司、Wave Computing、龙芯中科、北京君正等其他公司设计出来。这个列表显示了MIPS处理器的基本信息，包括这些处理器在性能，功能和功能上与最新的MIPS Aptiv系列的对比。

MIPS计算系统/MIPS科技公司
MIPS版本处理器推出年份 制程 频率 晶体管  裸晶面积  针脚数 功耗(W) 电压(V) 缓存特性一级二级三级 数据 指令 MIPS I R2000 1985 2000 8 to 16.67  0.11 80     64 external  64 external  none none  5 stage pipelines, FPU: 2010;  R3000 1988 1200 20 to 40    0,11 40  145 4  32 32 1 MB external  none same as R2000; FPU: 3010;Sony PlayStation MIPS II R6000 1990   60 to 66        external  external  none  none 32-bit register size, 36-bit physical address, FPU; A 32 bit ECL microprocessor manufactured by a company called Bipolar Integrated Technology (BIT). Production problems with the chip almost killed MIPS Computers and led to it being taken over by SGI. The CMOS R4000 followed hot on the R6000's heels and was cheaper, cooler, and higher performance as well as being 64 bit so the 6000 quickly become a minor footnote in RISC computing history. MIPS III R4000 1991 800 100 1.35 213 179 15 5 8 8  none  R4400 1992 600 100 to 250 2.3 186 179 15 5 8 8  none  R4200 1993  600 80 1.3 81 179 1.8-2.0 3.3 8 16 128 KB to 4 MB external  none scalar design with a five-stage classic RISC pipeline R4300i 1995  350 100 / 133  45 120 2.2 3.3    none  R4600 1994 640 100 / 133 2.2 77 179 4.6 5 16 16 512 KB external none  R4650 1994  640 133 / 180 2.2 77 179 4.6 5 16 16 512 KB external none  R4640 1995  640    179      none  R4700 1996 500 100 to 200 2.2  179   16 16 External none  MIPS IV R5000 1996 350 150 to 200 3.7 84 223 10 3.3 32 32 1 MB external none  RM7000 1998 250, 180, 130  250 to 600  18  91  304  10, 6, 3  3.3, 2.5, 1.5  16  16  256 KB internal  1 MB external  R8000 1994 700 75 to 90 2.6 299 591 30 3.3 16 16 4 MB external none superscalar, up to 4 instructions per cycle R10000 1996 350, 250 150 to 250 6.7 350 599 30 3.3 32 32 512 KB – 16 MB external none  R12000 1998 350, 250 270 to 360 7.15 229 600 20 4 32 32 512 KB – 16 MB external none single-chip 4-issue superscalar R12000A 2000 180 400         none  R14000 2001 130 500 7.2 204 527 17  32 32 512 KB – 16 MB external none  R14000A 2002 130 600    17  32 32  none  R16000 2003 110 700 to 1000    20  64 64 512 KB – 16 MB external none  R16000A 2004 110 800 to 1000      64 64  none  R18000 2001 130      1.2   1 MB none was planned, but not manufactured MIPS V H1 "Beast"            none was planned, but not manufactured H2 "Captain"            none was planned, but not manufactured MIPS32 4K 1999 180  167   2.5        none  4KE  90  420   1.2        none  24K 2003 130, 65, 40 400 (130 nm) 750 (65 nm) 1468 (40 nm)  0.83    0 to 64 0 to 64 4–16 MB external none  24KE 2003 130, 65, 40          none The MIPS32 24KE Core Family: High-Performance RISC Cores with DSP Enhancements 34K 2006 90, 65, 40 500 (90 nm) 1454 (40 nm)         none  74K 2007 65 1110  2.5     0 to 64  0 to 64   none  1004K 2008 65 1100  4.7     8 to 64  8 to 64   none  1074K 2010 40 1500         none  1074Kf 2010 40          none Floating point microAptiv 2012 90, 65       8 to 64 8 to 64  none  interAptiv 2012        4 to 64 4 to 64 up to 8 MB internal none  proAptiv 2012        32 or 64 32 or 64 up to 8 MB internal none  MIPS64 5K  1999             20K  2000             

Imagination Technologies
MIPS Technologies was acquired 17 December 2012, by Imagination Technologies. Since then, the following processors have been introduced by Imagination Technologies.

The Warrior P-Class CPU was announced on .

The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and MIPS64 release 6, and will come in three classes of performance and features:
 'Warrior M-class': entry-level MIPS cores for embedded and microcontroller applications, a progression from the popular microAptiv family
 'Warrior I-class': mid-range, feature-rich MIPS CPUs following on from the highly efficient interAptiv family. The I6400, with its 64-bit core, was launched September 2014.
 'Warrior P-class': high-performance MIPS processors building on the proAptiv family

 MIPS version level Processor                            Year Process (nm) Frequency (GHz) Transistors (billions) Die area (mm2)                            Pin count Power (W) Voltage (V) D. cache (KB) I. cache (KB) MMU L2 cache L3 cache Features  MIPS32 Release 5 Warrior-P P5600  2013  ? 1.0 to 2.0 ? ? ? ? ? 32/64 32/64 TLb Up to 8 MB external none  VZ, MSA Warrior-M M5100  2014 65/28 0.1 to 0.497 ? 0.04 to 0.77 ?   none none FMT none  none  VZ Warrior-M M5150  2014 65/28 0.372/0.576 ? 0.89/0.26 ?   up to 64 up to 64 TLB none  none  VZ MIPS64 Release 6 Warrior-P P6600  2015 28 Up to 2.0 ? ?  ? ? ? 32/64 32/64 TLB 0.5 - 8 MB external  none SMT, VZ Warrior-I I6400  2014 28 1.0 ? 1/core  ? ? ? 32/64 32/64 TLB 0.5 - 8 MB external  none SMT, VZ Warrior-M M6200  2015 65/40/28 up to 0.750 ? 0.19 ?   none none FMT none  none   Warrior-M M6250  2015 65/40/28 up to 0.750 ? 0.23 ?   up to 64 up to 64 TLB none  none  XPA MIPS version level Processor                            Year Process (nm) Frequency (GHz) Transistors (billions) Die area (mm2)                            Pin count Power (W) Voltage (V) D. cache (KB) I. cache (KB) MMU L2 cache L3 cache Features 

龙芯中科

 系列 型號 頻率 指令集架构微架構推出年份 核心數目 製程 晶體管 裸晶面积 功耗 電壓 缓存峰值浮点性能备注一级二级三级 数据 指令Godson 1 266 MIPS-II 32-bit  2001  1  180 22  71.4 1.0  8 8   0.6 FCR_SOC 266 MIPS-II 32-bit  2007 1  180     8 8   0.6 2B 250 MIPS-III 64-bit  2003 1 180     32 32    2C  450 MIPS-III 64-bit  2004 1 180 13.5 41.5   64 64    2E 1000 MIPS-III 64-bit GS464 (r1) 2006 1 90 47 36 7 1.2 64 64 512   龍芯１ 1A 300 MIPS32 GS232 2010  1  130 22  71.4 1.0  16 16   0.6  1B 266 MIPS32 GS232 2010  1  130 13.3  28 0.6  8  8       1C 300  MIPS32 GS232 2013  1  130  11.1  28.3 0.5  16 16     1C101 8 MIPS32 GS132R 2018  1  130             1D 8  MIPS32  GS132 2014  1  130 1 6 3 × 10−5        龍芯２ 2F 1200 MIPS-III 64-bit GS464 (r1) 2007 1 90 51 43 5 1.2 64 64 512  3.2  2G 1000  MIPS64 GS464 (r2) 2012 1  65     1.15 64 64 4096    2GP 800 MIPS64 GS464 (r2) 2013 1  65  82 65.7 8 1.15 64 64 1024 rowspan="2"  3.22I 2H 1000  MIPS64 GS464 (r2) 2012 1  65  152 117  5 1.15 64  64  512   4 2J0800 800 MIPS64 GS464 (r2) 2013 1 65   8 1.1 64 64 1024   2J1500 800 MIPS64 GS464E 2016 1 40   8  64 64 1024   2K1000 1000 MIPS64 Release 2
LoongISA1.0 GS264 2017 2 40 1900 79 5 1.1 32 32 256 × 2 1024 8  龍芯３ 3A1000 1000 MIPS64 Release 2 GS464 (r2) 2009 4 65 425 174.5 10 1.15 64 64 256 × 4  16  3B1000 1000 MIPS64 Release 2 GS464v 2010 4+4 65 ＞ 600  20 1.15 64 64 128 × 8  128  3B1500 1200–1500 MIPS64 Release 2 GS464v 2012 4+4 32 1140 142.5 3060 1.15–1.35 64 64 128 × 8 8192 150 3A1500-I800–1000MIPS64 Release 2
LoongISA1.0GS464E2015440621202.3151.15–1.256464256 × 4409616 3A2000 3B2000 3A30001500MIPS64 Release 2
LoongISA1.0GS464E2016428＞ 1200155.78301.15–1.256464256 × 4819224 3B30003A40001800-2000MIPS64 Release 5
LoongISA2.0GS464V(GS464EV)2019428??30@1.6GHz

40@1.8GHZ

50@2.0GHz0.95-1.256464256 x 481921283B4000

北京君正
缩略图|Ingenic JZ4725
SoCs incorporating the XBurst microarchitecture:

ModelLaunchFab (nm) XBurst1FPUGPUVPUDatasheetPackageNotes version Core clock (MHz) L1 Dcache[kB] L1 Icache[kB] L2 cache[kB] Jz4720  2005  180 MIPS32 rev1  240 16 16 N/A N/A N/A N/A  Jz4720   Jz4725B  2005  160  360  Jz4725   Jz4730  2005  180  336  Jz4730   Jz4740  2007  180  MIPS32 rev1 + SIMD  360  Jz4740   adds RMVB, MPEG-1/2/4 decoding capability up to D-1 resolution  thanks to SIMD instruction set Jz4750  2009  180 MIPS32 rev1 + SIMD2  360  480p  Jz4750   adds TV encoder Jz4755  2009  160  400  576P  Jz4755  QFP176  second core is for video processing only Jz4760  2010  130  600  yes  Vivante GC200  720p  JZ4760JZ4760B  BGA345  second core is for video processing only, IEEE754-complient FPU Jz4770  2011  65  MIPS32 rev2 + SIMD2  1000  256  yes  Vivante GC860  1080p  JZ4770  BGA379  1080p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension) Jz4775Suspected to be called as JZ4774 sometime     65  MIPS32 rev2 + SIMD2  1000  32  32  256  yes  X2D Core  720p  JZ4775  BGA314  720p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension) Jz4780  2012  40  Dual MIPS32 rev2 + SIMD2  1200JZ4780 Mobile Application Processor Data Sheet  32 each  32 each   512  yes  PowerVR SGX 540  1080p  JZ4780  BGA390  Dual core (SMP) XBurst CPU, 1080p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension)

其他公司
A number of companies licensed the MIPS architecture and developed their own processors.

 MIPS version Licensee Processor Features                             Year Process (nm) Frequency (MHz) Transistors (millions) Die size (mm2)                            Pin count Power (W) Voltage (V) D. cache (KB) I. cache (KB) MMU L2 cache L3 cache MIPS III Sony Computer Entertainment + Toshiba Emotion Engine               MIPS32 Alchemy Semiconductor Au1               Broadcom BMIPS3000               BMIPS4000               BMIPS5000    1300            BCM53001   65  400       32  32     BCM1255               MIPS64 SiByte SB1               Broadcom BCM1125H    400-800      4w @ 400 MHz    32  32  yes   256 KB   BCM1255 Dual-core, DDR2, 4× Gigabit LAN    800-1200     13 W @ 1 GHz   32  32  yes  512 KB   Cavium Octeon: CN30xx, CN31xx, CN36xx, CN38xx  2006              Octeon Plus: CN5xxx  2007              Octeon II: CN6xxx  2009              Octeon III: CN7xxx  2012              NEC VR4305               VR4310               NXP Semiconductors ??               ??               MIPS version Licensee Processor Features                             Year Process (nm) Frequency (MHz) Transistors (millions) Die size (mm2)                            Pin count Power (W) Voltage (V) D. cache (KB) I. cache (KB) MMU L2 cache L3 cache

另见
 PhysX P1 - A multi-core physics processing unit that contains MIPS cores

参考

Category:微处理器列表
Category:MIPS处理器列表
Category:MIPS架构