nyuuzyou/wikis huggingface dataset:
Exams/2013 q2afsm

Consider the FSM described by the state diagram shown below:
This FSM acts as an arbiter circuit, which controls access to some type of resource by three
requesting devices. Each device makes its request for the resource by setting a signal r[i] = 1,
where r[i] is either r[1], r[2], or r[3]. Each r[i] is an input signal to the FSM, and represents one of the
three devices. The FSM stays in state A as long as there are no requests. When one or more
request occurs, then the FSM decides which device receives a grant to use the resource and
changes to a state that sets that device’s g[i] signal to 1. Each g[i] is an output from the FSM. There
is a priority system, in that device 1 has a higher priority than device 2, and device 3 has the
lowest priority. Hence, for example, device 3 will only receive a grant if it is the only device
making a request when the FSM is in state A. Once a device, i, is given a grant by the FSM, that
device continues to receive the grant as long as its request, r[i] = 1.
Write complete Verilog code that represents this FSM. Use separate always blocks for the state
table and the state flip-flops, as done in lectures. Describe the FSM outputs, g[i], using either
continuous assignment statement(s) or an always block (at your discretion). Assign any state
codes that you wish to use.
Exams/2013 q2bfsm

Consider a finite state machine that is used to control some type of motor. The FSM has inputs
x and y, which come from the motor, and produces outputs f and g, which control the motor.
There is also a clock input called clk and a reset input called resetn.
The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a
beginning state, called state A. When the reset signal is de-asserted, then after the next clock
edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the
x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should
be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y
input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1
permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the
FSM should set g = 0 permanently (until reset).
(The original exam question asked for a state diagram only. But here, implement the FSM.)
Exams/2014 q3bfsm

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Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.
Present statey[2:0]Next state Y[2:0]Output z
x=0x=1
0000000010
0010011000
0100100010
0110010101
1000111001
Exams/2014 q3c

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Given the state-assigned table shown below, implement the logic functions Y[0] and z.
Present statey[2:0]Next state Y[2:0]Output z
x=0x=1
0000000010
0010011000
0100100010
0110010101
1000111001
Exams/2014 q3fsm

Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A,
as depicted below. The FSM remains in state A as long as s = 0, and it moves to state
B when s = 1. Once in state B the FSM examines the value of the input w in the next three
clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z
to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for
the next three clock cycles, and so on. The timing diagram below illustrates the required values
of z for different values of w.
Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.
<wavedrom>
{ signal: [{ name: "clk", wave: "p............" },
 { name: "s", wave: "01x.........." },
 { name: "w", wave: "0.101..0.1.0." },
 { name: "z", wave: "0....10.10.10" }
 ],
foot: {
 tock: ['A', 'A', 'B', '...' ]
} }
</wavedrom>
Exams/2014 q4b

Consider the n-bit shift register circuit shown below:
Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four
copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board. 
* Connect the R inputs to the SW switches,
* clk to KEY[0],
* E to KEY[1],
* L to KEY[2], and
* w to KEY[3]. 
* Connect the outputs to the red lights LEDR[3:0].
(Reuse your MUXDFF from exams/2014_q4a.)
Exams/ece241 2013 q12

In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.
First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).
Exams/ece241 2013 q2

A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.
Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.
Exams/ece241 2013 q8

Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.
Exams/ece241 2014 q3

For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.
You are implementing just the portion labelled top_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.
(The requirement to use only 2-to-1 multiplexers exists because the original exam question also wanted to test logic function simplification using K-maps and how to synthesize logic functions using only multiplexers. If you wish to treat this as purely a Verilog exercise, you may ignore this constraint and write the module any way you wish.)
Exams/ece241 2014 q5a

You are to design a one-input one-output serial 2's complementer Moore state machine. 
The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.
For example:
<wavedrom>
{signal: [
 {name: "Input (x)", wave: '0.101.0.'},
 {name: "Output (z)", wave: "0..1.0.1"}
],
 foot: { tock: ['LSB', , , , , , , 'MSB'] }
}
</wavedrom>
Exams/ece241 2014 q5b

The following diagram is a Mealy machine implementation of the 2's complementer. 
Implement using one-hot encoding.
<wavedrom>
{signal: [
 {name: "Input (x)", wave: '0.101.0.'},
 {name: "Output (z)", wave: "0.1.0.1."}
],
 foot: { tock: ['LSB', , , , , , , 'MSB'] }
}
</wavedrom>
Exams/ece241 2014 q7a

Design a 1-12 counter with the following inputs and outputs:
* Reset Synchronous active-high reset that forces the counter to 1
* Enable Set high for the counter to run
* Clk Positive edge-triggered clock input
* Q[3:0] The output of the counter
* c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:
* the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
* logic gates
module count4(
	input clk,
	input enable,
	input load,
	input [3:0] d,
	output reg [3:0] Q
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter's enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.
Exams/ece241 2014 q7b

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.
module bcdcount (
	input clk,
	input reset,
	input enable,
	output reg [3:0] Q
);
Exams/m2014 q6b

Consider the state machine shown below, which has one input w and one output z.
Assume that you wish to implement the FSM using three flip-flops and state codes y[3:1] =
000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this FSM.
Derive a next-state expression for the flip-flop y[2].
Implement just the next-state logic for y[2]. (This is much more a FSM question than a Verilog coding question. Oh well.)
Exams/m2014 q6c

Consider the state machine shown below, which has one input w and one output z.
For this part, assume that a one-hot code is used with the state assignment 'y[6:1] = 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.
Write a logic expression for the next-state signals Y2 and Y4. 
(Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).
Exams/review2015 count1k

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.
<wavedrom>
{ signal: [{ name: "clk", wave: "p..............." },
 { name: "reset", wave: "0............10." },
 { name: "q", wave: "================", data: ['...', '990','991','992','993','994','995','996','997','998','999','0','1','2', "0", "1"] }
] }
</wavedrom>
Exams/review2015 fancytimer

This is the fifth component in a series of five exercises that builds a complex counter out of several smaller circuits. You may wish to do the four previous exercises first (<vlgstat tc="exams/review2015_shiftcount">counter</vlgstat>, <vlgstat tc="exams/review2015_fsmseq">sequence recognizer FSM</vlgstat>, <vlgstat tc="exams/review2015_fsmshift">FSM delay</vlgstat>, and <vlgstat tc="exams/review2015_fsm">combined FSM</vlgstat>).
We want to create a timer with one input that:
# is started when a particular input pattern (1101) is detected, 
# shifts in 4 more bits to determine the duration to delay, 
# waits for the counters to finish counting, and
# notifies the user and waits for the user to acknowledge the timer.
The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. I'll refer to this as the delay[3:0].
After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement).
At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).
The circuit should reset into a state where it begins searching for the input sequence 1101.
Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.
<wavedrom skin="narrow">
{ signal: [{ name: "clk", wave: "p...............|.................." },
 { name: "reset", wave: "10..............|.................." },
 { name: "data", wave: "010.1.010..1x...|........1.01...0x." },
 { name: "count[3:0]", wave: "x...........=...|=...x...........=.", data: ['1', '0', 'e'] },
 { name: "counting", wave: "0...........1...|....0...........1." },
 { name: "done", wave: "0...............|....1...0........." },
 { name: "ack", wave: "x...............|....0..1x........." }
],
 foot: { tock:[,,,,,,,,,,,,'0','1','2','3','...','1996',,,'1999',,,,,,,,,,,,,'0','1'] }
 }
</wavedrom>
Exams/review2015 fsm

This is the fourth component in a series of five exercises that builds a complex counter out of several smaller circuits. See <vlgstat tc="exams/review2015_fancytimer">the final exercise</vlgstat> for the overall design.
You may wish to do FSM: Enable shift register and FSM: Sequence recognizer first.
We want to create a timer that:
# is started when a particular pattern (1101) is detected, 
# shifts in 4 more bits to determine the duration to delay, 
# waits for the counters to finish counting, and
# notifies the user and waits for the user to acknowledge the timer.
In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.
The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles. 
After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.
At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).
The state machine should reset into a state where it begins searching for the input sequence 1101.
Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.
<wavedrom skin="narrow">
{ signal: [{ name: "clk", wave: "p............................." },
 { name: "reset", wave: "10............................" },
 { name: "data", wave: "010.1.01x............1.01x...." },
 { name: "shift_ena", wave: "0.......1...0............1...0" },
 { name: "counting", wave: "0...........1....0...........1" },
 { name: "done_counting", wave: "x...........0...1x...........0" },
 { name: "done", wave: "0................1...0........" },
 { name: "ack", wave: "x................0..1x........" }
] }
</wavedrom>
Exams/review2015 fsmonehot

Given the following state machine with 3 inputs, 3 outputs, and 10 states:
Derive next-state logic equations and output logic equations by inspection assuming the following one-hot encoding is used:
(S, S1, S11, S110, B0, B1, B2, B3, Count, Wait) = (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)
Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated. See <vlgstat tc="fsm3onehot" /> for a description of what is meant by deriving logic equations "by inspection" for one-hot state machines.)
Write code that generates the following equations:
* B3_next -- next-state logic for state B3
* S_next
* S1_next
* Count_next
* Wait_next
* done -- output logic
* counting
* shift_ena
Exams/review2015 fsmseq

This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See <vlgstat tc="exams/review2015_fancytimer">the final exercise</vlgstat> for the overall design.
Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.
<wavedrom>
{ signal: [{ name: "clk", wave: "p..............." },
 { name: "reset", wave: "10............1." },
 { name: "data", wave: "0.101....01.0.1." },
 { name: "start_shifting", wave: "0..........1...0" }
] }
</wavedrom>
Exams/review2015 fsmshift

This is the third component in a series of five exercises that builds a complex counter out of several smaller circuits. See <vlgstat tc="exams/review2015_fancytimer">the final exercise</vlgstat> for the overall design.
As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.
Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).
<wavedrom>
{ signal: [{ name: "clk", wave: "p..............." },
 { name: "reset", wave: "10.....1..0....." },
 { name: "shift_ena", wave: "01...0..1.....0." }
] }
</wavedrom>
Exams/review2015 shiftcount

This is the first component in a series of five exercises that builds a complex counter out of several smaller circuits. See <vlgstat tc="exams/review2015_fancytimer">the final exercise</vlgstat> for the overall design.
Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).
<wavedrom>
{ signal: [{ name: "clk", wave: "p..............." },
 { name: "shift_ena", wave: "0.1...0........." },
 { name: "count_ena", wave: "0........1....0." },
 { name: "data", wave: "x.10.1x........." },
 { name: "q", wave: "=..====...=====.", data: ['0', '1','2','4','9','8','7','6','5','4'] }
] }
</wavedrom>
Fsm3

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See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.
StateNext stateOutput
in=0in=1
AAB0
BCB0
CAD0
DCB1
Fsm3comb

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The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.
Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (state), compute the next_state and output (out) based on the state transition table.
StateNext stateOutput
in=0in=1
AAB0
BCB0
CAD0
DCB1
Fsm3onehot

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The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000. 
Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).
StateNext stateOutput
in=0in=1
AAB0
BCB0
CAD0
DCB1
What does "derive equations by inspection" mean?
One-hot state machine encoding guarantees that exactly one state bit is 1. This means that it is possible to determine whether the state machine is in a particular state by examining only one state bit, not all state bits. This leads to simple logic equations for the state transitions by examining the incoming edges for each state in the state transition diagram.
For example, in the above state machine, how can the state machine can reach state A? It must use one of the two incoming edges: "Currently in state A and in=0" or "Currently in state C and in = 0". Due to the one-hot encoding, the logic equation to test for "currently in state A" is simply the state bit for state A. This leads to the final logic equation for the next state of state bit A: next_state[0] = state[0]&(~in) | state[2]&(~in). The one-hot encoding guarantees that at most one clause (product term) will be "active" at a time, so the clauses can just be ORed together.
When an exercise asks for state transition equations "by inspection", use this particular method. The judge will test with non-one-hot inputs to ensure your logic equations follow this method, rather that doing something else (such as resetting the FSM) for illegal (non-one-hot) combinations of the state bits.
Although knowing this algorithm isn't necessary for RTL-level design (the logic synthesizer handles this), it is illustrative of why one-hot FSMs often have simpler logic (at the expense of more state bit storage), and this topic frequently shows up on exams in digital logic courses.