PM SLP S4 L Timing Troubleshooting

PM_SLP_S4_L Apple Mac Logic Board Signal Timing Discussion
 
When will the CPU or PCH shoot out the PM_SLP_S4_L signal?
This question burdens a lot of component level repair technicians. This article discusses the prerequisites that must be met before the Intel CPU/PCH outputs PM_SLP_S4_L. Once you understand the timing, missing PM_SLP_S4_L signal is not hard to deal with.
 
There are two sets of PM_SLP_S4_L prerequisites. Intel 1st to 5th generation CPUs use the same set of prerequisites called 11+1 conditions. Intel 6th generation onward CPUs use a different set of prerequisites called 13+1 conditions (discuss in a separate article). Intel and Apple use a different naming system. We use the Apple naming system by default. Since Apple uses different names referring to the same Intel CPU/PCH signal in different models, we use MacBook Air 2013 A1466 Haswell-ULT CPU 820-3437 schematics here as an example.
Intel 1st to 5th generation CPUs 11+1prerequisites for PM_SLP_S4_L:
1. PPVRTC_G3H	 	(VCCRTC) – Intel naming system
2. RTC_RESET_L	 	(RTCRST#)
3. PCH_SRTCRST_L	 	(SRTCRST#)
4. PCH_INTVRMEN_L	 	(INTVRMEN)
5. PCH_DSWVRMEN_L	 	(DSWVRMEN)
6. SYSCLK_CLK32K_RTCX1	 	(RTCX1)
7. PP3V3_S5	 	(VCCDSW3-3)
8. PM_DSW_PWRGD	 	(DPWROK)
9. PP3V3_SUS	 	(VCCSUS3)
10. PM_BATLOW_L	 	(BATLOW#)
11. PM_RSMRST_L	 	(RSMRST#)
+1. PM_PWRBTN_L	 	(PWRBTN#)
If PM_SLP_S4_L missing, we need to check these before replacing the CPU/PCH.
1. PPVRTC_G3H (VCCRTC) real-time clock circuit power supply. 3.3V ok
2. RTC_RESET_L (RTCRST#) real-time clock circuit reset. 3.3V ok
3. PCH_SRTCRST_L (SRTCRST#) secondary real-time clock circuit reset. 3.3V ok
4. PCH_INTVRMEN_L (INTVRMEN) internal voltage regulators 1.05V and 1.5V enable. 3.3V ok
5. PCH_DSWVRMEN_L (DSWVRMEN) deep sleep well(power) voltage regulator enable. 3.3V ok
6. SYSCLK_CLK32K_RTCX1 (RTCX1) 32khz clock for RTC circuit. Measured by an oscilloscope.
7. PP3V3_S5 (VCCDSW3-3) deep sleep well (power rail) present. 3.3V ok
8. PM_DSW_PWRGD (DPWROK) deep sleep well not only present but also stable(OK). 3.3V ok
9. PP3V3_SUS (VCCSUS3) suspended mode(shallow sleep mode) power rail present. 3.3V ok
10. PM_BATLOW_L (BATLOW#) if the battery voltage is NOT low, or no battery is connected, SMC will output 3.3V to inform CPU/PCH. 3.3V ok
11. PM_RSMRST_L (RSMRST#) stands for “resume reset”, the system is ready for resuming from suspended mode (from shallow sleep mode to wake up). 3.3V ok
12. PM_PWRBTN_L (PWRBTN#) power button on/off. If the logic board is connected to the battery only, you need to press the power button on the keyboard to send a high-low-high pulse to the CPU/PCH (via SMC). If you connect the logic board to the charger only without connecting the battery, once SMC receives the SMC_BC_ACOK from charging circuit power management IC u7100, SMC will output SMC_ADAPTER_EN (ACPRESENT). In this case, the signal SMC_ADAPTER_EN will act as the same as PM_PWRBTN_L. In other words, the PM_PWRBTN_L is not always a “must" in some situation. It is why we call it “+1" condition.
When the 11 prerequisites are met, once you press the power button (PM_PWRBTN_L) or connect a charger to the logic board (SMC_ADAPTER_EN), CPU/PCH will shoot out PM_SLP_S5_L, PM_SLP_S4_L and PM_SLP_S3_L to enable S4, S3 and S0 state power rails.
In most models, Apple does not utilise PM_SLP_S5_L, just feedback this signal to SMC and that is all. PM_SLP_S4_L will enable the S3 state power rails including the memory module power rail. PM_SLP_S3_L will enable the rest S0 state power rails.
Category:Mac