nyuuzyou/wikis huggingface dataset:
Module cseladd

One drawback of the ripple carry adder (See <vlgstat tc=module_add>previous exercise</vlgstat>) is that the delay for an adder to compute the carry out (from the carry-in, in the worst case) is fairly slow, and the second-stage adder cannot begin computing its carry-out until the first-stage adder has finished. This makes the adder slow. One improvement is a carry-select adder, shown below. The first-stage adder is the same as before, but we duplicate the second-stage adder, one assuming carry-in=0 and one assuming carry-in=1, then using a fast 2-to-1 multiplexer to select which result happened to be correct. 
In this exercise, you are provided with the same module add16 as the previous exercise, which adds two 16-bit numbers with carry-in and produces a carry-out and 16-bit sum. You must instantiate three of these to build the carry-select adder, using your own 16-bit 2-to-1 multiplexer.
Connect the modules together as shown in the diagram below. The provided module add16 has the following declaration:
module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
Category:Modules
Module fadd

In this exercise, you will create a circuit with two levels of hierarchy. Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1.
Like <vlgstat tc=module_add/>, you are given a module add16 that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored).
Connect the add16 modules together as shown in the diagram below. The provided module add16 has the following declaration:
module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
Within each add16, 16 full adders (module add1, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:
module add1 ( input a, input b, input cin, output sum, output cout ); 
Recall that a full adder computes the sum and carry-out of a+b+cin.
In summary, there are three modules in this design:
* top_module — Your top-level module that contains two of...
* add16, provided — A 16-bit adder module that is composed of 16 of...
* add1 — A 1-bit full adder module.
If your submission is missing a module add1, you will get an error message that says Error (12006): Node instance "user_fadd[0].a1" instantiates undefined entity "add1".
Category:Modules
Category:Combinational
Module name

This problem is similar to <vlgstat tc=module/>. You are given a module named mod_a that has 2 outputs and 4 inputs, in some order. You must connect the 6 ports by name to your
top-level module's ports:
Port in mod_a	Port in top_module
output out1 	out1
output out2 	out2
input in1 	a
input in2 	b
input in3 	c
input in4 	d
You are given the following module:
module mod_a ( output out1, output out2, input in1, input in2, input in3, input in4);
Category:Modules
Module pos

This problem is similar to the previous one (<vlgstat tc=module/>). You are given a module named mod_a that has 2 outputs and 4 inputs, in that order. You must connect the 6 ports by position to your
top-level module's ports out1, out2, a, b, c, and d, in that order.
You are given the following module:
module mod_a ( output, output, input, input, input, input );
Category:Modules
Module shift

You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.
The module provided to you is:
module my_dff ( input clk, input d, output q );
Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.
Category:Modules
Module shift8

This exercise is an extension of <vlgstat tc=module_shift/>. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.
You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)
The module provided to you is:
module my_dff8 ( input clk, input [7:0] d, output [7:0] q );
The multiplexer is not provided. One possible way to write one is inside an always block with a case statement inside. (See also: <vlgstat tc="mux9to1v"/>)
Category:Modules
Mt2015 lfsr

Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff
Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.
Mt2015 muxdff

Taken from ECE253 2015 midterm question 5
Consider the sequential circuit below:
Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.
My Stats

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Norgate

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.
An assign statement drives a wire (or "net", as it's more formally called) with a value. This value can be as complex a function as you want, as long as it's a combinational (i.e., memory-less, with no hidden state) function. An assign statement is a continuous assignment because the output is "recomputed" whenever any of its inputs change, forever, much like a simple logic gate.
Reduction

You're already familiar with bitwise operations between two values, e.g., a & b or a ^ b. Sometimes, you want to create a wide gate that operates on all of the bits of one vector, like (a[0] & a[1] & a[2] & a[3] ... ), which gets tedious if the vector is long.
The reduction operators can do AND, OR, and XOR of the bits of a vector, producing one bit of output:
& a[3:0] // AND: a[3]&a[2]&a[1]&a[0]. Equivalent to (a[3:0] == 4'hf)
| b[3:0] // OR: b[3]|b[2]|b[1]|b[0]. Equivalent to (b[3:0] != 4'h0)
^ c[2:0] // XOR: c[2]^c[1]^c[0]
These are unary operators that have only one operand (similar to the NOT operators ! and ~). You can also invert the outputs of these to create NAND, NOR, and XNOR gates, e.g., (~& d[7:0]).
Now you can revisit <vlgstat tc=gates4>4-input gates</vlgstat> and <vlgstat tc=gates100>100-input gates</vlgstat>.
== A Bit of Practice ==
Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.
Ringer

Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.
Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.
Design hint: When designing circuits, one often has to think of the problem "backwards", starting from the outputs then working backwards towards the inputs. This is often the opposite of how one would think about a (sequential, imperative) programming problem, where one would look at the inputs first then decide on an action (or output). For sequential programs, one would often think "If (inputs are ___ ) then (output should be ___ )". On the other hand, hardware designers often think "The (output should be ___ ) when (inputs are ___ )".
The above problem description is written in an imperative form suitable for software programming (if ring then do this), so you must convert it to a more declarative form suitable for hardware implementation (assign ringer = ___). Being able to think in, and translate between, both styles is one of the most important skills needed for hardware design.
Rotate100

Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.
*load: Loads shift register with data[99:0] instead of rotating.
*ena[1:0]: Chooses whether and which direction to rotate. 
** 2'b01 rotates right by one bit
** 2'b10 rotates left by one bit
** 2'b00 and 2'b11 do not rotate.
*q: The contents of the rotator.
Rule110

Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete). 
There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the following table:
LeftCenterRightCenter's next state
1110
1101
1011
1000
0111
0101
0011
0000
(The name "Rule 110" comes from reading the "next state" column: 01101110 is decimal 110.)
In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).
Rule90

Rule 90 is a one-dimensional cellular automaton with interesting properties.
The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:
LeftCenterRightCenter's next state
1110
1101
1010
1001
0111
0100
0011
0000
(The name "Rule 90" comes from reading the "next state" column: 01011010 is decimal 90.)
In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).
Shift18

Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount. 
An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.
There is no difference between logical and arithmetic left shifts.
*load: Loads shift register with data[63:0] instead of shifting.
*ena: Chooses whether to shift.
*amount: Chooses which direction and how much to shift.
** 2'b00: shift left by 1 bit.
** 2'b01: shift left by 8 bits.
** 2'b10: shift right by 1 bit.
** 2'b11: shift right by 8 bits.
*q: The contents of the shifter.
Shift4

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.
*areset: Resets shift register to zero.
*load: Loads shift register with data[3:0] instead of shifting.
*ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
*q: The contents of the shift register.
If both the load and ena inputs are asserted (1), the load input has higher priority.
Sim/circuit1

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom>
{"signal":[["Inputs",{"name":"a","wave":"0....1...0...1...0"},{"name":"b","wave":"0..1.0.1.0.1.0.1.0"}],{"name":""},["Outputs",{"name":"q","wave":"0......1.0.....1.0"}],{"name":""}],"foot":{"tick":[["tspan",{"font-size":9},"5"],["tspan",{"font-size":9},"10"],["tspan",{"font-size":9},"15"],["tspan",{"font-size":9},"20"],["tspan",{"font-size":9},"25"],["tspan",{"font-size":9},"30"],["tspan",{"font-size":9},"35"],["tspan",{"font-size":9},"40"],["tspan",{"font-size":9},"45"],["tspan",{"font-size":9},"50"],["tspan",{"font-size":9},"55"],["tspan",{"font-size":9},"60"],["tspan",{"font-size":9},"65"],["tspan",{"font-size":9},"70"],["tspan",{"font-size":9},"75"],["tspan",{"font-size":9},"80"],["tspan",{"font-size":9},"85"],["tspan",{"font-size":9},"90"]]},"config":{"hscale":1}}
</wavedrom>
Sim/circuit10

This is a sequential circuit. The circuit consists of combinational logic and one bit of memory (i.e., one flip-flop). The output of the flip-flop has been made observable through the output state.
Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom skin="narrow">
{"signal":[["Inputs",{"name":"clk","wave":"lhlhlhlhlhlhlhlhlhlhlhlhlhlh"},{"name":"a","wave":"0......1...0.1.......0......"},{"name":"b","wave":"0....1.0.1.0.1.....0.1.0...."}],{"name":""},["Outputs",{"name":"q","wave":"0....1...0.1.0.1...0...1.0.."},{"name":"state","wave":"0..........1.0.1.........0.."}]],"foot":{"tick":["",["tspan",{"font-size":9},"20"],"",["tspan",{"font-size":9},"30"],"",["tspan",{"font-size":9},"40"],"",["tspan",{"font-size":9},"50"],"",["tspan",{"font-size":9},"60"],"",["tspan",{"font-size":9},"70"],"",["tspan",{"font-size":9},"80"],"",["tspan",{"font-size":9},"90"],"",["tspan",{"font-size":9},"100"],"",["tspan",{"font-size":9},"110"],"",["tspan",{"font-size":9},"120"],"",["tspan",{"font-size":9},"130"],"",["tspan",{"font-size":9},"140"],"",["tspan",{"font-size":9},"150"]]},"config":{"hscale":1}}
</wavedrom>
Sim/circuit2

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom>
{"signal":[["Inputs",{"name":"a","wave":"0........1.......0."},{"name":"b","wave":"0....1...0...1...0."},{"name":"c","wave":"0..1.0.1.0.1.0.1.0."},{"name":"d","wave":"0.10101010101010101"}],{"name":""},["Outputs",{"name":"q","wave":"1.0.101.0.1.010.1.0"}],{"name":""}],"foot":{"tick":[["tspan",{"font-size":9},"5"],["tspan",{"font-size":9},"10"],["tspan",{"font-size":9},"15"],["tspan",{"font-size":9},"20"],["tspan",{"font-size":9},"25"],["tspan",{"font-size":9},"30"],["tspan",{"font-size":9},"35"],["tspan",{"font-size":9},"40"],["tspan",{"font-size":9},"45"],["tspan",{"font-size":9},"50"],["tspan",{"font-size":9},"55"],["tspan",{"font-size":9},"60"],["tspan",{"font-size":9},"65"],["tspan",{"font-size":9},"70"],["tspan",{"font-size":9},"75"],["tspan",{"font-size":9},"80"],["tspan",{"font-size":9},"85"],["tspan",{"font-size":9},"90"],["tspan",{"font-size":9},"95"]]},"config":{"hscale":1}}
</wavedrom>
Sim/circuit3

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom>
{"signal":[["Inputs",{"name":"a","wave":"0........1.......0."},{"name":"b","wave":"0....1...0...1...0."},{"name":"c","wave":"0..1.0.1.0.1.0.1.0."},{"name":"d","wave":"0.10101010101010101"}],{"name":""},["Outputs",{"name":"q","wave":"0.....1..01..01..0."}],{"name":""}],"foot":{"tick":[["tspan",{"font-size":9},"5"],["tspan",{"font-size":9},"10"],["tspan",{"font-size":9},"15"],["tspan",{"font-size":9},"20"],["tspan",{"font-size":9},"25"],["tspan",{"font-size":9},"30"],["tspan",{"font-size":9},"35"],["tspan",{"font-size":9},"40"],["tspan",{"font-size":9},"45"],["tspan",{"font-size":9},"50"],["tspan",{"font-size":9},"55"],["tspan",{"font-size":9},"60"],["tspan",{"font-size":9},"65"],["tspan",{"font-size":9},"70"],["tspan",{"font-size":9},"75"],["tspan",{"font-size":9},"80"],["tspan",{"font-size":9},"85"],["tspan",{"font-size":9},"90"],["tspan",{"font-size":9},"95"]]},"config":{"hscale":1}}
</wavedrom>
Sim/circuit4

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom>
{"signal":[["Inputs",{"name":"a","wave":"0........1.......0."},{"name":"b","wave":"0....1...0...1...0."},{"name":"c","wave":"0..1.0.1.0.1.0.1.0."},{"name":"d","wave":"0.10101010101010101"}],{"name":""},["Outputs",{"name":"q","wave":"0..1.....0.1.....0."}],{"name":""}],"foot":{"tick":[["tspan",{"font-size":9},"5"],["tspan",{"font-size":9},"10"],["tspan",{"font-size":9},"15"],["tspan",{"font-size":9},"20"],["tspan",{"font-size":9},"25"],["tspan",{"font-size":9},"30"],["tspan",{"font-size":9},"35"],["tspan",{"font-size":9},"40"],["tspan",{"font-size":9},"45"],["tspan",{"font-size":9},"50"],["tspan",{"font-size":9},"55"],["tspan",{"font-size":9},"60"],["tspan",{"font-size":9},"65"],["tspan",{"font-size":9},"70"],["tspan",{"font-size":9},"75"],["tspan",{"font-size":9},"80"],["tspan",{"font-size":9},"85"],["tspan",{"font-size":9},"90"],["tspan",{"font-size":9},"95"]]},"config":{"hscale":1}}
</wavedrom>
Sim/circuit5

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
==== Simulation 1 ====
<wavedrom>
{"signal":[["Inputs",{"name":"a","wave":"x=.................","data":["a"]},{"name":"b","wave":"x=.................","data":["b"]},{"name":"c","wave":"x==================","data":["0","1","2","3","4","5","6","7","8","9","a","b","c","d","e","f","0","1"]},{"name":"d","wave":"x=.................","data":["d"]},{"name":"e","wave":"x=.................","data":["e"]}],{"name":""},["Outputs",{"name":"q","wave":"x=====...........==","data":["b","e","a","d","f","b","e"]}]],"foot":{"tick":[["tspan",{"font-size":9},"5"],["tspan",{"font-size":9},"10"],["tspan",{"font-size":9},"15"],["tspan",{"font-size":9},"20"],["tspan",{"font-size":9},"25"],["tspan",{"font-size":9},"30"],["tspan",{"font-size":9},"35"],["tspan",{"font-size":9},"40"],["tspan",{"font-size":9},"45"],["tspan",{"font-size":9},"50"],["tspan",{"font-size":9},"55"],["tspan",{"font-size":9},"60"],["tspan",{"font-size":9},"65"],["tspan",{"font-size":9},"70"],["tspan",{"font-size":9},"75"],["tspan",{"font-size":9},"80"],["tspan",{"font-size":9},"85"],["tspan",{"font-size":9},"90"],["tspan",{"font-size":9},"95"]]},"config":{"hscale":1}}
</wavedrom>
==== Simulation 2 ====
<wavedrom>
{"signal":[["Inputs",{"name":"a","wave":"==.........=.......","data":["a","1","5"]},{"name":"b","wave":"==.........=.......","data":["b","2","6"]},{"name":"c","wave":"==========.========","data":["2","0","1","2","3","4","5","6","7","8","0","1","2","3","4","5","6","7"]},{"name":"d","wave":"==.........=.......","data":["d","3","7"]},{"name":"e","wave":"==.........=.......","data":["e","4","8"]}],{"name":""},["Outputs",{"name":"q","wave":"======.....=====...","data":["a","2","4","1","3","f","6","8","5","7","f"]}]],"foot":{"tick":[["tspan",{"font-size":9},"105"],["tspan",{"font-size":9},"110"],["tspan",{"font-size":9},"115"],["tspan",{"font-size":9},"120"],["tspan",{"font-size":9},"125"],["tspan",{"font-size":9},"130"],["tspan",{"font-size":9},"135"],["tspan",{"font-size":9},"140"],["tspan",{"font-size":9},"145"],["tspan",{"font-size":9},"150"],["tspan",{"font-size":9},"155"],["tspan",{"font-size":9},"160"],["tspan",{"font-size":9},"165"],["tspan",{"font-size":9},"170"],["tspan",{"font-size":9},"175"],["tspan",{"font-size":9},"180"],["tspan",{"font-size":9},"185"],["tspan",{"font-size":9},"190"],["tspan",{"font-size":9},"195"]]},"config":{"hscale":1}}
</wavedrom>
Sim/circuit6

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom>
{"signal":[["Inputs",{"name":"a","wave":"x==========","data":["0","1","2","3","4","5","6","7","0","1"]}],{"name":""},["Outputs",{"name":"q","wave":"x==========","data":["1232","aee0","27d4","5a0e","2066","64ce","c526","2f19","1232","aee0"]}]],"foot":{"tick":[["tspan",{"font-size":9},"5"],["tspan",{"font-size":9},"10"],["tspan",{"font-size":9},"15"],["tspan",{"font-size":9},"20"],["tspan",{"font-size":9},"25"],["tspan",{"font-size":9},"30"],["tspan",{"font-size":9},"35"],["tspan",{"font-size":9},"40"],["tspan",{"font-size":9},"45"],["tspan",{"font-size":9},"50"],["tspan",{"font-size":9},"55"]]},"config":{"hscale":2}}
</wavedrom>
Sim/circuit7

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom>
{"signal":[["Inputs",{"name":"clk","wave":"lhlhlhlhlhlhlhlhlhlhl"},{"name":"a","wave":"0............1......."}],{"name":""},["Outputs",{"name":"q","wave":"x1.............0....."}]],"foot":{"tick":["",["tspan",{"font-size":9},"20"],"",["tspan",{"font-size":9},"30"],"",["tspan",{"font-size":9},"40"],"",["tspan",{"font-size":9},"50"],"",["tspan",{"font-size":9},"60"],"",["tspan",{"font-size":9},"70"],"",["tspan",{"font-size":9},"80"],"",["tspan",{"font-size":9},"90"],"",["tspan",{"font-size":9},"100"],"",["tspan",{"font-size":9},"110"],""]},"config":{"hscale":1}}
</wavedrom>
Sim/circuit8

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom skin="narrow">
{"signal":[["Inputs",{"name":"clock","wave":"0....1.....0.....1.....0...."},{"name":"a","wave":"0.10101010101010.....1010101"}],{"name":""},["Outputs",{"name":"p","wave":"0.....10101......0...10....."},{"name":"q","wave":"0..........1...........0...."}]],"foot":{"tick":[["tspan",{"font-size":9},"65"],["tspan",{"font-size":9},"70"],["tspan",{"font-size":9},"75"],["tspan",{"font-size":9},"80"],["tspan",{"font-size":9},"85"],["tspan",{"font-size":9},"90"],["tspan",{"font-size":9},"95"],["tspan",{"font-size":9},"100"],["tspan",{"font-size":9},"105"],["tspan",{"font-size":9},"110"],["tspan",{"font-size":9},"115"],["tspan",{"font-size":9},"120"],["tspan",{"font-size":9},"125"],["tspan",{"font-size":9},"130"],["tspan",{"font-size":9},"135"],["tspan",{"font-size":9},"140"],["tspan",{"font-size":9},"145"],["tspan",{"font-size":9},"150"],["tspan",{"font-size":9},"155"],["tspan",{"font-size":9},"160"],["tspan",{"font-size":9},"165"],["tspan",{"font-size":9},"170"],["tspan",{"font-size":9},"175"],["tspan",{"font-size":9},"180"],["tspan",{"font-size":9},"185"],["tspan",{"font-size":9},"190"],["tspan",{"font-size":9},"195"],["tspan",{"font-size":9},"200"]]},"config":{"hscale":1}}
</wavedrom>