Problem sets

<vlgstat action="genorder"/>
== Getting Started ==
*<vlgstat tc="step_one">Getting Started</vlgstat>
*<vlgstat tc="zero">Output Zero</vlgstat>
== Verilog Language ==
=== Basics ===
*<vlgstat tc="wire">Simple wire</vlgstat>
*<vlgstat tc="wire4">Four wires</vlgstat>
*<vlgstat tc="notgate">Inverter</vlgstat>
*<vlgstat tc="andgate">AND gate</vlgstat>
*<vlgstat tc="norgate">NOR gate</vlgstat>
*<vlgstat tc="xnorgate">XNOR gate</vlgstat>
*<vlgstat tc="wire_decl">Declaring wires</vlgstat>
*<vlgstat tc="7458">7458 chip</vlgstat>
=== Vectors ===
*<vlgstat tc="vector0">Vectors</vlgstat>
*<vlgstat tc="vector1">Vectors in more detail</vlgstat>
*<vlgstat tc="vector2">Vector part select</vlgstat>
*<vlgstat tc="vectorgates">Bitwise operators</vlgstat>
*<vlgstat tc="gates4">Four-input gates</vlgstat>
*<vlgstat tc="vector3">Vector concatenation operator</vlgstat>
*<vlgstat tc="vectorr">Vector reversal 1</vlgstat>
*<vlgstat tc="vector4">Replication operator</vlgstat>
*<vlgstat tc="vector5">More replication</vlgstat>
=== Modules: Hierarchy ===
*<vlgstat tc="module">Modules</vlgstat>
*<vlgstat tc="module_pos">Connecting ports by position</vlgstat>
*<vlgstat tc="module_name">Connecting ports by name</vlgstat>
*<vlgstat tc="module_shift">Three modules</vlgstat>
*<vlgstat tc="module_shift8">Modules and vectors</vlgstat>
*<vlgstat tc="module_add">Adder 1</vlgstat>
*<vlgstat tc="module_fadd">Adder 2</vlgstat>
*<vlgstat tc="module_cseladd">Carry-select adder</vlgstat>
*<vlgstat tc="module_addsub">Adder-subtractor</vlgstat>
=== Procedures ===
Procedures include always, initial, task, and function blocks. Procedures allow sequential statements (which cannot be used outside of a procedure) to be used to describe the behaviour of a circuit.
*<vlgstat tc="alwaysblock1">Always blocks (combinational)</vlgstat>
*<vlgstat tc="alwaysblock2">Always blocks (clocked)</vlgstat>
*<vlgstat tc="always_if">If statement</vlgstat>
*<vlgstat tc="always_if2">If statement latches</vlgstat>
*<vlgstat tc="always_case">Case statement</vlgstat>
*<vlgstat tc="always_case2">Priority encoder</vlgstat>
*<vlgstat tc="always_casez">Priority encoder with casez</vlgstat>
*<vlgstat tc="always_nolatches">Avoiding latches</vlgstat>
=== More Verilog Features ===
*<vlgstat tc="conditional">Conditional ternary operator</vlgstat>
*<vlgstat tc="reduction">Reduction operators</vlgstat>
*<vlgstat tc="gates100">Reduction: Even wider gates</vlgstat>
*<vlgstat tc="vector100r">Combinational for-loop: Vector reversal 2</vlgstat>
*<vlgstat tc="popcount255">Combinational for-loop: 255-bit population count</vlgstat>
*<vlgstat tc="adder100i">Generate for-loop: 100-bit binary adder 2</vlgstat>
*<vlgstat tc="bcdadd100">Generate for-loop: 100-digit BCD adder</vlgstat>
== Circuits ==
=== Combinational Logic ===
==== Basic Gates ====
*<vlgstat tc="exams/m2014_q4h">Wire</vlgstat>
*<vlgstat tc="exams/m2014_q4i">GND</vlgstat>
*<vlgstat tc="exams/m2014_q4e">NOR</vlgstat>
*<vlgstat tc="exams/m2014_q4f">Another gate</vlgstat>
*<vlgstat tc="exams/m2014_q4g">Two gates</vlgstat>
*<vlgstat tc="gates">More logic gates</vlgstat>
*<vlgstat tc="7420">7420 chip</vlgstat>
*<vlgstat tc="truthtable1">Truth tables</vlgstat>
*<vlgstat tc="mt2015_eq2">Two-bit equality</vlgstat>
*<vlgstat tc="mt2015_q4a">Simple circuit A</vlgstat>
*<vlgstat tc="mt2015_q4b">Simple circuit B</vlgstat>
*<vlgstat tc="mt2015_q4">Combine circuits A and B</vlgstat>
*<vlgstat tc="ringer">Ring or vibrate?</vlgstat>
*<vlgstat tc="thermostat">Thermostat</vlgstat>
*<vlgstat tc="popcount3">3-bit population count</vlgstat>
*<vlgstat tc="gatesv">Gates and vectors</vlgstat>
*<vlgstat tc="gatesv100">Even longer vectors</vlgstat>
==== Multiplexers ====
*<vlgstat tc="mux2to1">2-to-1 multiplexer</vlgstat>
*<vlgstat tc="mux2to1v">2-to-1 bus multiplexer</vlgstat>
*<vlgstat tc="mux9to1v">9-to-1 multiplexer</vlgstat>
*<vlgstat tc="mux256to1">256-to-1 multiplexer</vlgstat>
*<vlgstat tc="mux256to1v">256-to-1 4-bit multiplexer</vlgstat>
==== Arithmetic Circuits ====
*<vlgstat tc="hadd">Half adder</vlgstat>
*<vlgstat tc="fadd">Full adder</vlgstat>
*<vlgstat tc="adder3">3-bit binary adder</vlgstat>
*<vlgstat tc="exams/m2014_q4j">Adder</vlgstat>
*<vlgstat tc="exams/ece241_2014_q1c">Signed addition overflow</vlgstat>
*<vlgstat tc="adder100">100-bit binary adder</vlgstat>
*<vlgstat tc="bcdadd4">4-digit BCD adder</vlgstat>
==== Karnaugh Map to Circuit ====
*<vlgstat tc="kmap1">3-variable</vlgstat>
*<vlgstat tc="kmap2">4-variable</vlgstat>
*<vlgstat tc="kmap3">4-variable</vlgstat>
*<vlgstat tc="kmap4">4-variable</vlgstat>
*<vlgstat tc="exams/ece241_2013_q2">Minimum SOP and POS</vlgstat>
*<vlgstat tc="exams/m2014_q3">Karnaugh map</vlgstat>
*<vlgstat tc="exams/2012_q1g">Karnaugh map</vlgstat>
*<vlgstat tc="exams/ece241_2014_q3">K-map implemented with a multiplexer</vlgstat>
=== Sequential Logic ===
==== Latches and Flip-Flops ====
*<vlgstat tc="dff">D flip-flop</vlgstat>
*<vlgstat tc="dff8">D flip-flops</vlgstat>
*<vlgstat tc="dff8r">DFF with reset</vlgstat>
*<vlgstat tc="dff8p">DFF with reset value</vlgstat>
*<vlgstat tc="dff8ar">DFF with asynchronous reset</vlgstat>
*<vlgstat tc="dff16e">DFF with byte enable</vlgstat>
*<vlgstat tc="exams/m2014_q4a">D Latch</vlgstat>
*<vlgstat tc="exams/m2014_q4b">DFF</vlgstat>
*<vlgstat tc="exams/m2014_q4c">DFF</vlgstat>
*<vlgstat tc="exams/m2014_q4d">DFF+gate</vlgstat>
*<vlgstat tc="mt2015_muxdff">Mux and DFF</vlgstat>
*<vlgstat tc="exams/2014_q4a">Mux and DFF</vlgstat>
*<vlgstat tc="exams/ece241_2014_q4">DFFs and gates</vlgstat>
*<vlgstat tc="exams/ece241_2013_q7">Create circuit from truth table</vlgstat>
*<vlgstat tc="edgedetect">Detect an edge</vlgstat>
*<vlgstat tc="edgedetect2">Detect both edges</vlgstat>
*<vlgstat tc="edgecapture">Edge capture register</vlgstat>
*<vlgstat tc="dualedge">Dual-edge triggered flip-flop</vlgstat>
==== Counters ====
*<vlgstat tc="count15">Four-bit binary counter</vlgstat>
*<vlgstat tc="count10">Decade counter</vlgstat>
*<vlgstat tc="count1to10">Decade counter again</vlgstat>
*<vlgstat tc="countslow">Slow decade counter</vlgstat>
*<vlgstat tc="exams/ece241_2014_q7a">Counter 1-12</vlgstat>
*<vlgstat tc="exams/ece241_2014_q7b">Counter 1000</vlgstat>
*<vlgstat tc="countbcd">4-digit decimal counter</vlgstat>
*<vlgstat tc="count_clock">12-hour clock</vlgstat>
==== Shift Registers ====
*<vlgstat tc="shift4">4-bit shift register</vlgstat>
*<vlgstat tc="rotate100">Left/right rotator</vlgstat>
*<vlgstat tc="shift18">Left/right arithmetic shift by 1 or 8</vlgstat>
*<vlgstat tc="lfsr5">5-bit LFSR</vlgstat>
*<vlgstat tc="mt2015_lfsr">3-bit LFSR</vlgstat>
*<vlgstat tc="lfsr32">32-bit LFSR</vlgstat>
*<vlgstat tc="exams/m2014_q4k">Shift register</vlgstat>
*<vlgstat tc="exams/2014_q4b">Shift register</vlgstat>
*<vlgstat tc="exams/ece241_2013_q12">3-input LUT</vlgstat>
==== More Circuits ====
* Cellular automata
**<vlgstat tc="rule90">Rule 90</vlgstat>
**<vlgstat tc="rule110">Rule 110</vlgstat>
**<vlgstat tc="conwaylife">Conway's Game of Life 16x16</vlgstat>
==== Finite State Machines ====
*<vlgstat tc="fsm1">Simple FSM 1 (asynchronous reset)</vlgstat>
*<vlgstat tc="fsm1s">Simple FSM 1 (synchronous reset)</vlgstat>
*<vlgstat tc="fsm2">Simple FSM 2 (asynchronous reset)</vlgstat>
*<vlgstat tc="fsm2s">Simple FSM 2 (synchronous reset)</vlgstat>
*<vlgstat tc="fsm3comb">Simple state transitions 3</vlgstat>
*<vlgstat tc="fsm3onehot">Simple one-hot state transitions 3</vlgstat>
*<vlgstat tc="fsm3">Simple FSM 3 (asynchronous reset)</vlgstat>
*<vlgstat tc="fsm3s">Simple FSM 3 (synchronous reset)</vlgstat>
*<vlgstat tc="exams/ece241_2013_q4">Design a Moore FSM</vlgstat>
*<vlgstat tc="lemmings1">Lemmings 1</vlgstat>
*<vlgstat tc="lemmings2">Lemmings 2</vlgstat>
*<vlgstat tc="lemmings3">Lemmings 3</vlgstat>
*<vlgstat tc="lemmings4">Lemmings 4</vlgstat>
*<vlgstat tc="fsm_onehot">One-hot FSM</vlgstat>
*<vlgstat tc="fsm_ps2">PS/2 packet parser</vlgstat>
*<vlgstat tc="fsm_ps2data">PS/2 packet parser and datapath</vlgstat>
*<vlgstat tc="fsm_serial">Serial receiver</vlgstat>
*<vlgstat tc="fsm_serialdata">Serial receiver and datapath</vlgstat>
*<vlgstat tc="fsm_serialdp">Serial receiver with parity checking</vlgstat>
*<vlgstat tc="fsm_hdlc">Sequence recognition</vlgstat>
*<vlgstat tc="exams/ece241_2013_q8">Q8: Design a Mealy FSM</vlgstat>
*<vlgstat tc="exams/ece241_2014_q5a">Q5a: Serial two's complementer (Moore FSM)</vlgstat>
*<vlgstat tc="exams/ece241_2014_q5b">Q5b: Serial two's complementer (Mealy FSM)</vlgstat>
*<vlgstat tc="exams/2014_q3fsm">Q3a: FSM</vlgstat>
*<vlgstat tc="exams/2014_q3bfsm">Q3b: FSM</vlgstat>
*<vlgstat tc="exams/2014_q3c">Q3c: FSM logic</vlgstat>
*<vlgstat tc="exams/m2014_q6b">Q6b: FSM next-state logic</vlgstat>
*<vlgstat tc="exams/m2014_q6c">Q6c: FSM one-hot next-state logic</vlgstat>
*<vlgstat tc="exams/m2014_q6">Q6: FSM</vlgstat>
*<vlgstat tc="exams/2012_q2fsm">Q2a: FSM</vlgstat>
*<vlgstat tc="exams/2012_q2b">Q2b: One-hot FSM equations</vlgstat>
*<vlgstat tc="exams/2013_q2afsm">Q2a: FSM</vlgstat>
*<vlgstat tc="exams/2013_q2bfsm">Q2b: Another FSM</vlgstat>
=== Building Larger Circuits ===
*<vlgstat tc="exams/review2015_count1k">Counter with period 1000</vlgstat>
*<vlgstat tc="exams/review2015_shiftcount">4-bit shift register and down counter</vlgstat>
*<vlgstat tc="exams/review2015_fsmseq">FSM: Sequence 1101 recognizer</vlgstat>
*<vlgstat tc="exams/review2015_fsmshift">FSM: Enable shift register</vlgstat>
*<vlgstat tc="exams/review2015_fsm">FSM: The complete FSM</vlgstat>
*<vlgstat tc="exams/review2015_fancytimer">The complete timer</vlgstat>
*<vlgstat tc="exams/review2015_fsmonehot">FSM: One-hot logic equations</vlgstat>
== Verification: Reading Simulations ==
=== Finding bugs in code ===
*<vlgstat tc="bugs_mux2">Mux</vlgstat>
*<vlgstat tc="bugs_nand3">NAND</vlgstat>
*<vlgstat tc="bugs_mux4">Mux</vlgstat>
*<vlgstat tc="bugs_addsubz">Add/sub</vlgstat>
*<vlgstat tc="bugs_case">Case statement</vlgstat>
=== Build a circuit from a simulation waveform ===
*<vlgstat tc="sim/circuit1">Combinational circuit 1</vlgstat>
*<vlgstat tc="sim/circuit2">Combinational circuit 2</vlgstat>
*<vlgstat tc="sim/circuit3">Combinational circuit 3</vlgstat>
*<vlgstat tc="sim/circuit4">Combinational circuit 4</vlgstat>
*<vlgstat tc="sim/circuit5">Combinational circuit 5</vlgstat>
*<vlgstat tc="sim/circuit6">Combinational circuit 6</vlgstat>
*<vlgstat tc="sim/circuit7">Sequential circuit 7</vlgstat>
*<vlgstat tc="sim/circuit8">Sequential circuit 8</vlgstat>
*<vlgstat tc="sim/circuit9">Sequential circuit 9</vlgstat>
*<vlgstat tc="sim/circuit10">Sequential circuit 10</vlgstat>
== Verification: Writing Testbenches ==
*<vlgstat tc="tb/clock">Clock</vlgstat>
*<vlgstat tc="tb/tb1">Testbench1</vlgstat>
*<vlgstat tc="tb/and">AND gate</vlgstat>
*<vlgstat tc="tb/tb2">Testbench2</vlgstat>
*<vlgstat tc="tb/tff">T flip-flop</vlgstat>
== CS450 ==
*<vlgstat tc="cs450/timer">.</vlgstat>
*<vlgstat tc="cs450/counter_2bc">.</vlgstat>
*<vlgstat tc="cs450/history_shift">.</vlgstat>
*<vlgstat tc="cs450/gshare">.</vlgstat>