SCAB computer

The SCAB computer is a Reduced Instruction Set Computer (RISC). It has four instructions and does not use any operand which means that only 2 bits per instruction is needed to code all instructions. Although the instruction set and instruction size is small, the language form by its instruction set is Turing complete. The SCAB is an esoteric or academic computer. as many instructions are needed to do simple operation. However, the SCAB has a very simple architecture and the number of transistor to make a SCAB is extremely limited. Therefore, its performance relative to the number of transistor might still be interesting. For example a huge number of SCAB could easily be integrated in a single chip and massive parallelization could make this concept attractive.
== Architecture and instruction set ==
The data address size and program address size can be selected arbitrarily and should be adjusted to the available memory. The size of a word in the data memory is 1 bit. The size of a word in the program memory is 2 bit. The computer could be Harvard or Von Newman architecture depending on the hardware implementation.
The SCAB has two registers in addition to the data address space. The first register is a working register (w) allowing to address the data memory (dm) and the second is a program counter register (pc) allowing to address the program memory (pm).
Data located at the top of the data memory is a mapping of special registers. The top of the data memory contains 2 registers: (wl) is working register literal having the same size as (w) and (pcl) program counter register having the same size as (pc). Additional special register mapped in the data space may be needed to implement additional hardware features such as timer, interrupt, general purpose IO, computed goto, indirect addressing…
The set and clear instructions set and clear respectively the bit in the data memory at location w then increment w and pc. The arm instruction copy wl in the register w, the register wl is cleared and pc is incremented. The branch instruction increment pc if the bit in the data memory at location w is set otherwise the register pcl is copied in pc. 
At reset the pc register is reset. Any code is an arbitrary suite of mnemonic S, C, A and B.
Mnemonic	Name 	Binary	Function
S 	Set 	00 	dm[w]=1; w++; pc++;
C 	Clear 	01 	dm[w]=0; w++; pc++;
A 	Arm 	10 	w=wl; wl=0; pc++;
B 	Branch	11 	if(dm[w]==1) then pc++; else pc=pcl;
== Emulator ==
The SCAB machine can easily be emulated in software. The following c++ code will emulate the SCAB machine.
 #define PC_SIZE 12
 #define W_SIZE 10
 typedef enum {S,C,A,B} Instruction;
 void main(void){
 Instruction pm[1<< PC_SIZE]={A,A,C,S,C,S,A,C,C,C,C,C,C,C,C,C,C,C,C,A,A,B};
 bool dm [1<< W_SIZE];
 unsigned int w,pc=0,i;
 for(;;) {
 pc&=(1<< PC_SIZE)-1;
 w&=(1<< W_SIZE)-1;
 switch(pm[pc]) {
 case S:
 dm[w]=true;
 w++;
 pc++;
 break;
 case C:
 dm[w]=false;
 w++;
 pc++;
 break;
 case A:
 for(i=0,w=0;i< W_SIZE;i++) {
 if(dm[i]) w+=1<< i;
 dm[i]=false;
 };
 pc++;
 break;
 case B:
 if(dm[w])
 pc++;
 else
 for(i=0,pc=0;i< PC_SIZE;i++)
 if(dm[W_SIZE+i]) pc+=1<< i;
 }
 }
 return;
 }
== References ==
* SCAB computer
Category:Languages
Category:Low-level 
Category:Turing tarpits 
Category:Cell-based 
Category:Implemented 
Category:2007