nyuuzyou/wikis huggingface dataset:
Sim/circuit9

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
<wavedrom skin="narrow">
{"signal":[["Inputs",{"name":"clk","wave":"lhlhlhlhlhlhlhlhlhlhlhlhlhlhlhlhlhlhlhlhl"},{"name":"a","wave":"1....0......................1....0......."}],{"name":""},["Outputs",{"name":"q","wave":"=......=.=.=.=.=.=.=.=.=.=.=.=.....=.=.=.","data":["4","5","6","0","1","2","3","4","5","6","0","1","4","5","6","0"]}]],"foot":{"tick":["",["tspan",{"font-size":9},"20"],"",["tspan",{"font-size":9},"30"],"",["tspan",{"font-size":9},"40"],"",["tspan",{"font-size":9},"50"],"",["tspan",{"font-size":9},"60"],"",["tspan",{"font-size":9},"70"],"",["tspan",{"font-size":9},"80"],"",["tspan",{"font-size":9},"90"],"",["tspan",{"font-size":9},"100"],"",["tspan",{"font-size":9},"110"],"",["tspan",{"font-size":9},"120"],"",["tspan",{"font-size":9},"130"],"",["tspan",{"font-size":9},"140"],"",["tspan",{"font-size":9},"150"],"",["tspan",{"font-size":9},"160"],"",["tspan",{"font-size":9},"170"],"",["tspan",{"font-size":9},"180"],"",["tspan",{"font-size":9},"190"],"",["tspan",{"font-size":9},"200"],"",["tspan",{"font-size":9},"210"],""]},"config":{"hscale":1}}
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Srlatch

A SR latch is a circuit with memory (remembers its old state) that can be Set or Reset by the control inputs. There are many ways to code this, including building it from NOR gates, if-else, or a case statement in a combinational always block.
In the diagrams, the reset input has higher priority than the set input. Build a SR latch where the set input has higher priority.
In this exercise, all of the inputs and outputs are active high.
I've removed this problem from the problem set. SR latches are not always synthesized correctly, depending on coding style. Writing an SR latch is not suitable when you don't have the post-synthesis netlist to verify the output of logic synthesis, nor those new to Verilog and not yet familiar with how logic synthesis tools can synthesize incorrect circuits.
Details: If the logic synthesizer interprets the code as a D-latch + logic, you get:
Enable = set | reset;
Q = Enable ? set : Q;
This produces a non-working latch because the Enable and D inputs change at the same time.
Stats

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Step one

Welcome to HDLBits! 
Getting started in digital logic design can be overwhelming at first because you need to learn new concepts, a new Hardware Description Language (e.g., Verilog), several new software packages, and often an FPGA board, all at the same time. HDLBits provides a way to practice designing and debugging simple circuits with a single click of "Simulate".
Designing a circuit requires several steps: Writing HDL (Verilog) code, compiling the code to produce a circuit, then simulating the circuit and fixing bugs.
=== Writing Code ===
The easiest way to write your code is to do so in the code editor box below. For this problem, we have filled in most of the code for you already. Go ahead and finish the code for this circuit.
Click Simulate to compile and simulate your design.
=== Compiling (Logic Synthesis) ===
Your code is compiled using Altera Quartus to produce a circuit. Quartus produces a large number of messages. Click Show Quartus messages to show/hide them. It's good practice to reduce the number of warnings, but it is sometimes not practical to remove them all.
=== Simulation ===
Your compiled circuit is simulated to test whether it functions correctly. HDLBits use ModelSim to simulate your circuit and our reference solution in parallel, then compares the outputs of the modules. The simulation reports back two things:
First, it reports whether your circuit matches the reference circuit exactly (zero "mismatches") or how many "mismatches" occurred. A mismatch is the number of samples where the output of your circuit does not match the reference output.
Second, it may produce timing diagrams that show your circuit outputs when running our test vectors. The simulation waveform is grouped into three sections: "Inputs", "Yours", and "Ref". In a correct circuit, "Your" outputs will be the same as the "Ref" outputs. The "Mismatch" signals tells you which samples have a mismatch.
The module name and port names of the top-level top_module must not be changed, or you will get a simulation error.
=== Final Status ===
If your circuit was correct, you will see Status: Success!. There are a few other possibilities:
* Compile Error — Circuit did not compile.
* Simulation Error — Circuit compiled successfully, but simulation did not complete.
* Incorrect — Circuit compiled and simulated, but the outputs did not match the reference.
* Success! — Circuit was correct
You can track or share your progress on the My Stats page.
=== Problem Statement ===
We're going to start with a small bit of HDL to get familiar with the interface used by HDLBits. Here's the description of the circuit you need to build for this exercise:
Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).
Tb/and

You are given the following AND gate you wish to test:
module andgate (
 input [1:0] in,
 output out
);
Write a testbench that instantiates this AND gate and tests all 4 input combinations, by generating the following timing diagram:
<wavedrom>
{signal: [{name: "in[1]", wave:"0.1."},{name: "in[0]", wave:"0101"},{name:"out", wave: "0..1"} ],
"foot":{"tick":[["tspan",{"font-size":9},"0"],["tspan",{"font-size":9},"10"],["tspan",{"font-size":9},"20"],["tspan",{"font-size":9},"30"]]} }
</wavedrom>
Category:Testbench
Tb/clock

You are provided a module with the following declaration:
module dut ( input clk ) ;
Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module's clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.
<wavedrom>
{signal: [ {name: "clk", wave: "0101010101"} ],
 foot: { tick: [0,5,10,15,20,25,30,35,40,45,"..." ] }
}
</wavedrom>
Category:Testbench
Tb/tb1

Create a Verilog testbench that will produce the following waveform for outputs A and B:
<wavedrom>
{ signal: [
 { name: "A", wave: "0.1.0......" },
 { name: "B", wave: "0..1....0.." } ],
 foot: {tick:[0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50]} }
</wavedrom>
Category:Testbench
Tb/tb2

The waveform below sets clk, in, and s:
<wavedrom>
{"signal":[{"name":"clk","wave":"lhlhlhlhlhlhlhlh"},{"name":"in","wave":"0...1.0.1.....0."},{"name":"s","wave":"=.=.=.=.=.......","data":["2","6","2","7","0"]}],
"foot":{"tick":["0","5","10","15","20","25","30","35","40","45","50","55","60","65","70","75"]},
"config":{"hscale":1}}
</wavedrom>
Module q7 has the following declaration:
module q7 (
 input clk,
 input in,
 input [2:0] s,
 output out
);
Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.
Category:Testbench
Thermostat

A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate.
The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0).
In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.
Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.
Topics

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Getting Started
Using HDLBits
Verilog Language
Problems that focus on introducing Verilog language syntax and features.
Combinational Logic
Logic gates, modules, vectors, combinational always blocks, k-maps, ...
Sequential Logic
Flip-flops, counters, shift registers, finite-state machines
Reading Simulations
Finding bugs, creating circuits from waveforms.
Writing Testbenches
Writing non-synthesizable Verilog testbenches
Truthtable1

In the previous exercises, we used simple logic gates and combinations of several logic gates. These circuits are examples of combinational circuits. Combinational means the outputs of the circuit is a function (in the mathematics sense) of only its inputs. This means that for any given input value, there is only one possible output value. Thus, one way to describe the behaviour of a combinational function is to explicitly list what the output should be for every possible value of the inputs. This is a truth table.
For a boolean function of N inputs, there are 2N possible input combinations. Each row of the truth table lists one input combination, so there are always 2N rows. The output column shows what the output should be for each input value.
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Row 	Inputs	Inputs	Inputs	Outputs
number	x3 	x2 	x1 	f
0 	0 	0 	0 	0
1 	0 	0 	1 	0
2 	0 	1 	0 	1
3 	0 	1 	1 	1
4 	1 	0 	0 	0
5 	1 	0 	1 	1
6 	1 	1 	0 	0
7 	1 	1 	1 	1
The above truth table is for a three-input, one-output function. It has 8 rows for each of the 8 possible input combinations, and one output column. There are four inputs combinations where the output is 1, and four where the output is 0.
=== Synthesizing a circuit from a truth table ===
Suppose we want to build the above circuit, but we're limited to using only the set of standard logic gates.
How would you build arbitrary logic functions (expressed as a truth table)?
One simple method to create a circuit that implements the truth table's function is to express the function in sum-of-products form. Sum (meaning OR) of products (meaning AND) means using one N-input AND gate per row of the truth table (to detect when the input matches each row), followed by an OR gate that chooses only those rows that result in a '1' output.
For the above example, the output is '1' if the input matches row 2 or row 3 or row 5 or row 7 (This is a 4-input OR gate). The input matches row 2 if x3=0 and x2=1 and x1=0 (This is a 3-input AND gate). Thus, this truth table can be implemented in canonical form by using 4 AND gates that are ORed together.
== A Bit of Practice ==
Create a combinational circuit that implements the above truth table.
Vector0

Vectors are used to group related signals using one name to make it more convenient to manipulate. For example, wire [7:0] w; declares an 8-bit vector named w that is functionally equivalent to having 8 separate wires.
Notice that the declaration of a vector places the dimensions before the name of the vector, which is unusual compared to C syntax. However, the part select has the dimensions after the vector name as you would expect.
wire [99:0] my_vector; // Declare a 100-element vector
assign out = my_vector[10]; // Part-select one bit out of the vector
Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc.
In a diagram, a tick mark with a number next to it indicates the width of the vector (or "bus"), rather than drawing a separate line for each bit in the vector.
Vector2

A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.
AaaaaaaaBbbbbbbbCcccccccDddddddd => DdddddddCcccccccBbbbbbbbAaaaaaaa
This operation is often used when the endianness of a piece of data needs to be swapped, for example between little-endian x86 systems and the big-endian formats used in many Internet protocols.
Vector3

Part selection was used to select portions of a vector. The concatenation operator {a,b,c} is used to create larger vectors by concatenating smaller portions of a vector together. 
{3'b111, 3'b000} => 6'b111000
{1'b1, 1'b0, 3'b101} => 5'b10101
{4'ha, 4'd10} => 8'b10101010 // 4'ha and 4'd10 are both 4'b1010 in binary
Concatenation needs to know the width of every component (or how would you know the length of the result?). Thus, {1, 2, 3} is illegal and results in the error message: unsized constants are not allowed in concatenations.
The concatenation operator can be used on both the left and right sides of assignments.
input [15:0] in;
output [23:0] out;
assign {out[7:0], out[15:8]} = in; // Swap two bytes. Right side and left side are both 16-bit vectors.
assign out[15:0] = {in[7:0], in[15:8]}; // This is the same thing.
assign out = {in[7:0], in[15:8]}; // This is different. The 16-bit vector on the right is extended to
 // match the 24-bit vector on the left, so out[23:16] are zero.
 // In the first two examples, out[23:16] are not assigned.
== A Bit of Practice ==
Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits:
Vector4

The concatenation operator allowed concatenating together vectors to form a larger vector. But sometimes you want the same thing concatenated together many times, and it is still tedious to do something like assign a = {b,b,b,b,b,b};. The replication operator allows repeating a vector and concatenating them together:
{num{vector}}
This replicates vector by num times. num must be a constant. Both sets of braces are required. 
Examples:
{5{1'b1}} // 5'b11111 (or 5'd31 or 5'h1f)
{2{a,b,c}} // The same as {a,b,c,a,b,c}
{3'd5, {2{3'd6}}} // 9'b101_110_110. It's a concatenation of 101 with
 // the second vector, which is two copies of 3'b110.
== A Bit of Practice ==
One common place to see a replication operator is when sign-extending a smaller number to a larger one, while preserving its signed value. This is done by replicating the sign bit (the most significant bit) of the smaller number to the left. For example, sign-extending 4'b0101 (5) to 8 bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8 bits results in 8'b11111101 (-3).
Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.
Vector5

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.
out[24] = ~a ^ a; // a == a, so out[24] is always 1.
out[23] = ~a ^ b;
out[22] = ~a ^ c;
...
out[ 1] = ~e ^ d;
out[ 0] = ~e ^ e;
As the diagram shows, this can be done more easily using the replication and concatenation operators. 
*The top vector is a concatenation of 5 repeats of each input
*The bottom vector is 5 repeats of a concatenation of the 5 inputs
Vectorgates

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.
=== Bitwise vs. Logical Operators ===
Earlier, we mentioned that there are bitwise and logical versions of the various boolean operators (e.g., <vlgstat tc=norgate/>). When using vectors, the distinction between the two operator types becomes important. A bitwise operation between two N-bit vectors replicates the operation for each bit of the vector and produces a N-bit output, while a logical operation treats the entire vector as a boolean value (true = non-zero, false = zero) and produces a 1-bit output.
Look at the simulation waveforms at how the bitwise-OR and logical-OR differ.
Wire

Create a module with one input and one output that behaves like a wire.
Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog "continuous assignment" (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is "continuous" because the assignment continues all the time even if the right side's value changes. A continuous assignment is not a one-time event.
The ports on a module also have a direction (usually input or output). An input port is driven by something from outside the module, while an output port drives something outside. When viewed from inside the module, an input port is a driver or source, while an output port is a sink.
The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. The module and port declarations create the black portions of the circuit. Your task is to create a wire (in green) by adding an assign statement to connect in to out. The parts outside the box are not your concern, but you should know that your circuit is tested by connecting signals from our test harness to the ports on your top_module.
In addition to continuous assignments, Verilog has three other assignment types that are used in procedural blocks, two of which are synthesizable. We won't be using them until we start using procedural blocks.
Wire4

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:
a -> w
b -> x
b -> y
c -> z
The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code.
From outside the module, there are three input ports and four output ports.
When you have multiple assign statements, the order in which they appear in the code does not matter. Unlike a programming language, assign statements ("continuous assignments") describe connections between things, not the action of copying a value from one thing to another.
One potential source of confusion that should perhaps be clarified now: The green arrows here represent
connections between wires, but are not wires in themselves. The module itself already has 7 wires declared (named a, b, c, w, x, y, and z). This is because input and output declarations
actually declare a wire unless otherwise specified. Writing input wire a is the same as input a. Thus, the assign statements are not creating wires, they are creating the connections between
the 7 wires that already exist.
Wire decl

== Declaring wires ==
The circuits so far have been simple enough that the outputs are simple functions of the inputs. As circuits become more complex, you will need wires to connect internal components together. When you need to use a wire, you should declare it in the body of the module, somewhere before it is first used. (In the future, you will encounter more types of signals and variables that are also declared the same way, but for now, we'll start with a signal of type wire).
=== Example ===
module top_module (
 input in, // Declare an input wire named "in"
 output out // Declare an output wire named "out"
);
 wire not_in; // Declare a wire named "not_in"
 assign out = ~not_in; // Assign a value to out (create a NOT gate).
 assign not_in = ~in; // Assign a value to not_in (create another NOT gate).
endmodule // End of module "top_module"
In the above module, there are three wires (in, out, and not_in), two of which are already declared as part of the module's input and output ports (This is why you didn't need to declare any wires in the earlier exercises). The wire not_in needs to be declared inside the module. It is not visible from outside the module. Then, two NOT gates are created using two assign statements. Note that it doesn't matter which of the NOT gates you create first: You still end up with the same circuit.
== Practice ==
Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs. 
If you're following the circuit structure in the diagram, you should end up with four assign statements, as there are four signals that need a value assigned.
(Yes, it is possible to create a circuit with the same functionality without the intermediate wires.)
Zero

Build a circuit with no inputs and one output that outputs a constant 0
Now that you've worked through the previous problem, let's see if you can do a simple problem without the hints.
HDLBits uses Verilog-2001 ANSI-style port declaration syntax because it's easier to read and reduces typos. You may use the older Verilog-1995 syntax if you wish. For example, the two module declarations below are acceptable and equivalent:
module top_module ( zero );
 output zero;
 // Verilog-1995
endmodule
module top_module ( output zero ); 
 // Verilog-2001
endmodule
'CYCLING AT SAN LEANDRO. - Daily Alta California, Volume 41, Number 13602, 26 November 1886

'The misspellings are really something on this one.
==='CYCLING AT SAN LEANDRO. ===
==== The Twenty-five-Mile Race Won by F. A. Elwell in splendid Style. ====
The twenty-five-mile race between the teams of the Bay City Wheelmen, the Oakland Ramblers and the San Francisco Bicycle Club, for a handsome silver pitcher and a drinking cup, came off yesterday. The course chosen was the triangular road which runs around San Leandro. The teams, consisting of three representatives from each club, were as follows:
Bay City Wheelmen - H. A. Adcock, F. A. ELwell, S. F. Boothe, Jr.
Oakland Ramblers - A. S. Irelan, W. W. Harroldeon, H. A. Roseboro.
San Francisco Bicycle Club - O. F. Griffin, Jr., L. R. Lerzelier.
The start took place at 11:30 A. M., and the inhabitants of San Leandro turned out en masse to see the sport. For the first ten miles or so the men kept in a bunch, with the exception of Harroldson, of the Oakland Ramblers, whose bicycle ran foul of a rock, and gave him a header that entirely settled what chance he had for
the race. At the twentieth mile Elwell and Larzelier shot five miles ahead, and the race between the two for the last five miles was one of the most exciting ones ever seen. First one would get a trifle ahead and then the other. At last, by a desperate effort, Elwell got his small wheel in front of his opponent and gradually increased his lead to a length, winning the race and trophies in the fine time (for road work) of 1 hour 37 minutes 20 seconds. Adcock was the third, some ten bicycle lengths behind, and Irelan was fourth, ten lengths behind him.
The winner, F. A. Elwell, is a member of the Bay City Wheelmen's Club, L. R. Larzelier of the San Francisco Bicycle Club, and H. A. Adcock of the Bay City Wheelmen's. The handsome prize was given by the Oakland Ramblers.
Category:articles
Category:San Leandro
Category:Thanksgiving
Category:races