Iverilog

This is a simple web interface to run Verilog simulations using Icarus Verilog. Unlike the rest of the site, this page allows you to run a simulation of anything you want.
If you already have a simulator installed on your own computer, you should probably use that instead, as a web interface is quite limiting for debugging. However, a web-based simulator is good for creating shareable bits of Verilog for demonstration purposes.
<vlgload>module top_module ();
	reg clk=0;
	always #5 clk = ~clk; // Create clock with period=10
	initial `probe_start; // Start the timing diagram
	`probe(clk); // Probe signal "clk"
	// A testbench
	reg in=0;
	initial begin
		#10 in <= 1;
		#10 in <= 0;
		#20 in <= 1;
		#20 in <= 0;
		$display ("Hello world! The current time is (%0d ps)", $time);
		#50 $finish; // Quit the simulation
	end
	invert inst1 ( .in(in) ); // Sub-modules work too.
endmodule
module invert(input in, output out);
 assign out = ~in;
 `probe(in);	// Sub-modules can also have `probe()
 `probe(out);
endmodule
</vlgload>
== Documentation ==
=== Writing Testbenches ===
One of the difficulties of learning Verilog is that only some features of the language can be used to create hardware (the "synthesizable subset" of the language), and the user has to know which part of the language is synthesizable and which isn't. Non-synthesizable Verilog is used in testbench code to test hardware written in synthesizable Verilog. A simulator (such as ModelSim or Icarus) will understand the entire language, while a synthesizer (such as Altera Quartus) will not.
When running a simulation, you would typically have a (synthesizable) module you want to test (the device under test (DUT)), along with a testbench that instantiates your module and drives its inputs at the appropriate time.
A basic testbench uses some regs and an initial block to assign values to them. An initial block is similar to an always block, but it executes only once at the beginning of simulation. Verilog procedural blocks allow delays to be added to statements. For example, x = 0; #10; x = 1; sets x to 0, then waits for 10 time units, then sets x = 1.
Basic debugging can be done by printing out the values of signals using $display, $strobe, or $monitor. $display works similarly to printf in C.
Use the system task $finish to end the simulation.
=== Using Timing Diagrams ===
To show signals in a timing diagram, we've defined three Verilog macros:
* `probe(signal) : Adds signal to the timing diagram. 
* `probe_start : Use this inside an initial block to start a new timing diagram
* `probe_stop : Use this inside an initial block to stop the current timing diagram
You need `probe_start to start a timing diagram.
Limitations: You can only add each signal once. There can be no more than 512 signals. Each signal can be a bus of no more than 512 bits.
=== How it works ===
As usual, your top-level module must be called top_module. Unlike a standard Verilog simulation, we simulate your modules along with some of our modules to provide non-standard features like timing diagrams.
=== Limitations ===
Icarus Verilog doesn't support as many language features and isn't as tolerant of buggy code as commercial tools tend to be.