NEXT GENERATION MULTICORE DSP PROCESSORS

into the commercial arena due to a proliferation of different standards on a single cell phone (for instance GSM, EDGE, WCDMA,
Bluetooth, 802.11, FM radio, and DVB).
CURRENT AND EMERGING MOBILE COMMUNICATIONS AND NETWORKING STANDARDS ARE PROVIDING EVEN MORE CHALLENGES TO DSP.
Sandbridge (see the section “Existing Vendor-Specific Multicore DSP Platforms”) has also been producing DSPs designed for the SDR space for several years.
Signal-Processing On-Demand Architecture (SODA) [40] is one multicore DSP architecture designed specifically for SDR applications. Some key features of SODA are the lack of cache with multiple DMA and scratchpad memories used instead for explicit memory control. Each of the processors has a 32 3 16 b SIMD datapath and a coupled scalar datapath designed to handle the basic DSP operations performed on large frames of data in communication systems.
Another example is the Asynchronous Array of Simple Processors (AsAP) architecture [41] that relies on the dataflow nature of DSP algorithms to obtain power and performance efficiency. Shown in Figure 12, it is similar to the Tilera archi- tecture at a superficial glance, but also takes the mesh network principal
to its logical conclusion, with very small cores
10.17 mm
2 2 and only a minimal amount of memory per core (128 word program and 128 word data). The cores communi- cate asynchronously by doubly clocked FIFO buffers, and each core has its own clock generator so that the device is essential- ly clockless. When
a FIFO is either empty or full, the associated cores will go into a low power state until they have more data to process. These and other power-saving techniques are used in a design that is heavily focused on low power computation. There is also an emphasis on local communication, with each chip connected to its neighbors, in a similar manner to the Tilera multicore.
Even within the core, the connectivity is focused on allowing the core to absorb data rather than reroute it to other cores. The overall goal is to optimize for data flow programming with mostly local interconnect. Data can travel a distance of more than one core but will require more latency to do so. The AsAP chip is interesting as a “pure” example of a tiled array of processors with each processor performing a simple computation. The programming model for this kind of chip is, however, still a topic of research. Ambric produced an architecturally similar chip [42] and showed that,
for simple data flow problems, software tooling could be developed.
An example of this data flow approach to multicore DSP
design can be found in [43], where the concept of bulk-syn- chronous processing, a model of computation where data is shared between threads mostly
at synchronization barriers, is introduced. This deterministic approach to the mapping of algorithms to multicore is in line with the recommendations made in [44] where it is argued that adding parallelism in a nondeterministic manner (such as is commonly done with POSIX threads [14]) leads to systems that are unreasonably hard to test and debug. Fortunately, the parallelization of DSP algorithms can often be done in a deterministic manner using data flow diagrams. Hence, DSP may be a more fruitful space for the development of multicore than the general-purpose programming space.