B2.4.5 Parallel/Serial Devices - FAQs

See http://www.microsoft.com/winlogo/hardware/
B2.4.R Parallel/Serial Devices - Future Requirements
Announcement of additional future requirements will be published at http://www.microsoft.com/winlogo/hardware/
B2.5 PCI Controllers and Devices
All general requirements in B1.0 are included by reference.
B2.5.1.1 Driver device class support in related DDKs
Bus driver support is built in to Windows; see device class-specific entries in the Windows DDK.
B2.5.1.2 Windows compatibility and implementation notes (general)
http://www.microsoft.com/hwdev/bus/pci/
Note: This is a general reference, not a requirement.
B2.5.1.3 PCI Device Subsystem IDs and Windows
http://www.microsoft.com/hwdev/bus/pci/pciids.asp
See B2.5.3.2.1
B2.5.1.4 Compatibility Testing for Hot-Plugging Support for PCI Devices
http://www.microsoft.com/hwdev/bus/pci/hotplugpci.asp
Note: This is a general reference, not a requirement.
B2.5.1.6 See A1.1.5.3 B2.5.1.7 Correct PCI implementations
If PCI is present in the system, the PCI bus and PCI expansion connectors must meet the requirements defined in the PCI 2.2 specification, plus any additional PCI requirements listed here.
B2.5.3.2.1 Device IDs include PCI Subsystem IDs.
The Subsystem ID (SID) and SVID fields must comply with the SID requirement in PCI 2.2 and the implementation details provided in “PCI Device Subsystem IDs and Windows” at http://www.microsoft.com/hwdev/bus/pci/pciidspec.asp.
AMR devices and MR devices on the system board are not exempt from the requirement for SID and SVID.
See also A1.1.3
B2.5.3.2.2 System does not contain ghost devices.
Bus designs must fully implement all bus requirements on every expansion card connector. A computer must not include any ghost devices, which are devices that do not correctly decode the Type 1/Type 0 indicator. Such a device will appear on multiple PCI buses. A PCI card should be visible through hardware configuration access at only one bus/device/function coordinate.
B2.5.3.2.3 System uses standard method to close base address register (BAR) windows on nonsubtractive decode PCI bridges.
Nonsubtractive decode PCI bridges must implement the standard method to close BAR windows as defined in the PCI to PCI Bridge Architecture Specification Rev. 1.1. Setting the BAR to its maximum value and the limit register to zeros effectively closes the I/O or memory window references in that bridge BAR.
B2.5.3.2.4 See B10.1.4.6 B2.5.3.2.5 DELETED B2.5.3.2.6 DELETED B2.5.3.2.7 Configuration Space is correctly populated.
PCI 2.2 describes the configuration space used by the system to identify and configure each device attached to the bus. The configuration space is made up of a header region and a device-dependent region. Each configuration space must have a 64-byte header at offset 0. All the device registers that the device circuit uses for initialization, configuration, and catastrophic error handling must fit within the space between byte 64 and byte 255.
All other registers that the device uses during normal operation must be located in normal I/O or memory space. Unimplemented registers or reads to reserved registers must complete normally and return zero. Writes to reserved registers must complete normally, and the data must be discarded.
All registers required by the device at interrupt time must be in I/O or memory space.
B2.5.3.2.8 Interrupt routing is supported using ACPI.
The system must provide interrupt routing information using a _PRT object, as defined in Section 6.2.3 of ACPI 1.0b (for x86-based systems) and Section 6.2.8 of ACPI 2.0 (for Itanium-based systems). It is important to note that the _PRT object is the only method available for interrupt routing on Itanium-based systems.
B2.5.3.2.9 DELETED B2.5.3.2.10 DELETED B2.5.3.2.11 DELETED B2.5.3.2.12 PCI devices decode only resources found in the Devices BAR.
PCI devices must not decode cycles that are not their own to avoid contention on the PCI bus. Notice that this requirement does not in any way prohibit the standard interfaces provided for by the PCI cache support option discussed in PCI 2.2, which allows the use of a snooping cache coherency mechanism. Auxiliary hardware that is used to provide non-local console support is permitted within the scope of this requirement.
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