Simulasi dan Analisa Desain Komparator Presisi Pada adc pipeline 1-bit/stage dengan Mentor Graphics 0,35 µm

Simulasi dan Analisa Desain Komparator Presisi Pada ADC Pipeline 1-bit/stage dengan Mentor Graphics 0,35 µm
Hamzah Afandi1, Erma Triawati Ch2
Teknik Elektro, Universitas Gunadarma
Jln. Margonda Raya No. 100 Depok, Jawa Barat, 16424, Telp. 02178881112 Ext. 107
1hamzah@staff.gunadarma.ac.id
2ermach@staff.gunadarma.ac.id
ABSTRAK
Penelitian ini merupakan bagian dari penelitian yang bertujuan mendesain ADC yang mampu mendukung kamera kecepatan tinggi 10.000 frames/s. Dari studi dan analisa literatur didapatkan bahwa untuk mendukung kinerja kamera tersebut maka desain ADC yang sesuai adalah dari sisi kecepatan minimal memiliki konversi 80 MSPS, dari sisi resolusi minimal 8-bit dan diharapkan dari sisi biaya desain tidak terlalu tinggi. Melihat dari permasalahan spesifikasi ADC di atas, maka pemilihan jenis ADC yang sesuai adalah pipeline dari sisi kecepatan, hal ini dikarenakan ADC pipeline memiliki konsumsi daya kecil, sebab kebutuhan komponen pendukung di pipeline lebih sedikit. Topologi yang sesuai untuk mendukung kinerja kamera kecepatan tinggi adalah 1-bit/stage, karena komposisi rangkaian pendukung untuk topologi 1-bit/stage lebih sedikit, sehingga mempengaruhi dari sisi konsumsi daya dan area layout. Desain ADC pipeline untuk satu stage membutuhkan komponen pendukung op-amp, komparator, saklar kapasitor (SC) dan pembangkit clock. ADC pipeline 1-bit/stage memerlukan sub ADC yang teliti dan memiliki ketepatan tinggi, yang sesuai adalah komparator presisi yang memiliki Vos mendekati sama dengan 0V. Pada komparator presisi ada tiga bagian penting yang harus didesain yaitu blok pre-amp, blok decisian, dan blok penyangga (buffer). Hasil desain komparator presisi dengan metode perhitungan manual yang didasarkan pada spesifikasi yang diinginkan sudah didapat. Dari hasil desain kemudian disimulasikan dengan CAD mentor graphics dengan teknologi ukuran AMS (Austria Micro System) 0,35 μm CMOS, kemudian hasil simulasi di analisa bila terjadi perbedaan dengan teori dilakukan revisi baik hitungan manual dan simulasi rangkaian. Pada unit komparator presisi (sub ADC), simulasi ditekankan pada offset komparator dan level histeresis untuk menekan noise, simulasi-simulasi tersebut adalah simulasi tegangan offset Vos, simulasi tegangan setpoint VSP, dan simulasi transient komparator presisi. Hasil yang didapat adalah penguatan komparator Av ≈ 5 untuk meminimalkan offset error dengan Iss = 30µA supaya mendapatkan mode bersama pada tegangan ≈ 1,65V.
Kata kunci : komparator presisi, pre-amp, decision, buffer
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