B10.3.3 SCSI Controllers/Devices - Quality

B10.3.3 SCSI Controllers/Devices - Quality B10.3.3.1 Passes WHQL tests - See B1.3, B10.1.4.7.
See “SCSI Controllers” and device-specific topics in HCT documentation.
B10.3.4 SCSI Controllers/Devices - Windows Experience B10.3.4.1 DELETED B10.3.4.2 DELETED B10.3.4.3 Large partition support (>8 GB) and ability to boot from loader is supported B10.3.4.4 Adapter is capable of sharing IRQ and works behind a PCI-PCI bridge
System designers must make a best effort to provide access to non-shared interrupt lines by meeting these conditions:
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The system design enables all PCI slots and PCI device types to obtain exclusive use of an interrupt line when exclusive access increases performance.
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Dedicated PCI interrupts must not use vectors from ISA bus interrupts.
The high-end and low-end commodity server platforms present certain design challenges. For high-end servers, PCI 2.2 taken by itself imposes a limitation for Intel Architecture-based systems because the values written to the Interrupt Line register in configuration space must correspond to IRQ numbers 0-15 of the standard dual 8259 configuration, or to the value 255 which means “unknown” or “no connection.” The values between 15 and 255 are reserved. This fixed connection legacy dual 8259 configuration, if examined alone, constrains Intel Architecture-based systems, even when they use sophisticated interrupt-routing hardware and APIC support. For low-end servers, some core logic offerings provide little or no interrupt-routing support, and designers implement rotating access to interrupt resources using simple wire-OR techniques, such as those illustrated in the implementation note in Section 2.2.6 of PCI 2.2.
Windows, with its support for both MPS 1.4 and ACPI on 32-bit platforms and ACPI on Itanium systems, uses mechanisms beyond the legacy methods of routing all PCI interrupts through the legacy cascaded 8259 interrupt controllers to determine proper allocation and routing of PCI bus IRQs. This Windows capability allows use of interrupts beyond the 0-15 range permitted by the strict reading of the current PCI 2.2 specification language for Intel Architecture systems. System designers should include sufficient interrupt resources in their systems to provide at least one dedicated interrupt per PCI function for embedded devices and one interrupt per PCI INTA# - INTD# line on a PCI slot. This will become a requirement for all servers in a future version of this guideline.
When system designers cannot provide a non-shared interrupt line to a particular PCI device or slot because of the situations cited, the server system’s documentation must explain clearly to the end user of the system how interrupt resources are allocated on the platform and which devices cannot avoid sharing interrupts. System designers may provide this documentation or information as they deem most appropriate for their product. Some possible mechanisms include:
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Documenting slots according to the order in which cards should be inserted to prevent interrupt sharing for as long as possible
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Providing information on interrupt routing and sharing via system setup programs
Some instances need additional clarification to fit within the context of this guideline. At the system designer’s discretion, PCI devices can share an interrupt line under the following conditions:
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One system interrupt line can be shared by all PCI devices on an expansion card. In other words, PCI INTA# - INTD# may share the use of a single system interrupt directed to a given PCI expansion slot. This instance of line sharing applies to both expansion card designs based on PCI multifunction devices and to expansion card designs using PCI-to-PCI bridges.
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Devices can share an interrupt in a design where a system-board set has multiple instances of a given PCI device performing a specific function.
For example, two embedded PCI SCSI controllers on a system board can share a single system interrupt line. A single line can be shared when the functions of the devices are very similar, such as a case where one embedded SCSI controller may be dedicated to “narrow” (8-bit wide) SCSI devices and the other is dedicated to “wide” (16-bit wide) SCSI devices.
On the other hand, an embedded SCSI controller may not share an interrupt with an embedded network adapter on a system board, because they perform two different functions within the system and could contend for the shared interrupt in ways that will reduce overall system performance.
B10.3.4.5 Connector and terminator requirements B10.3.4.5.1 DELETED B10.3.4.5.2 Differential devices support DIFFSENS as defined in SPI-4 standard (or later).
Differential devices support DIFFSENS as defined in SPI-4 standard (or later).
Without DIFFSENS, the differential bus drivers or a single-ended device will suffer fatal thermal damage if a single-ended device is put on a differential bus.
The specification for DIFFSENS is defined in Section 5.4.2 of the SPI-4 standard.
B10.3.4.5.3 Automatic termination circuit and SCSI terminators meet SPI-4 standard (or later).
Parallel SCSI add-on adapters and on-board controllers must use automatic termination that allows a user to add external devices without removing the server case. Terminators used in the SCSI host adapter must be regulated terminators, which are also known as active, SCSI-3 SPI-4, or Boulay terminators. SCSI termination built onto internal cables must meet the SCSI-3 specification.
B10.3.4.5.4 Terminator power is supplied to the SCSI bus with overcurrent protection.
The host adapter must supply terminator power (TERMPWR) to the SCSI bus for system-board implementations using PCI or another expansion bus. All terminators on the external SCSI bus must be powered from the TERMPWR lines in the SCSI bus.
In addition, the circuit that supplies TERMPWR must have overcurrent protection built into it.
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