FpGa

=== GPU deployment ===
https://bdtechtalks.com/2020/11/09/fpga-vs-gpu-deep-learning/ and https://mipsology.com/ No need to Learn about FPGAs Switch to Zebra with One Command https://www.xilinx.com/video/events/mipsology-demonstrates-zebra.html
=== Hackaday ===
https://hackaday.io/project/13048-flea-ohm-fpga-project/details
https://circuitmaker.com/Projects/Details/Konstantin-Dimitrov-6/Configum-2-FPGA-Controller-Module
=== Xilinx ===
https://www.youtube.com/watch?time_continue=2667&v=uO0U-6N7x1A 3ms latency vs GPU 50ms latency Xilinx ZU11
=== cnn ===
https://github.com/awai54st/PYNQ-Classification/blob/master/PYNQ_CLASSIFICATION.pdf
https://github.com/awai54st/PYNQ-Classification
https://www.youtube.com/watch?v=DoA8hKBltV4
=== uCLinux ===
http://www.pengutronix.com/
== Design flow tools for FPGA ==
FFT and other routines used for WiMax and LTE on FPGA use http://www.dilloneng.com , http://www.mentor.com and http://www.bluespec.com/ design automation tools to create low level Verilog code with 4G hardware development platforms from http://www.sundance.com. IP cores SeaSolve are purchased to develop our own WiMax and LTE 4G radio systems. The other means of using parallal processing power is TileraMulticore, TexasInst , PicoChip and FreescaleDsp but their processing boards aren't available to the public, only FPGA is.
* http://www.ht-lab.com/ design flow
* http://www.fishtail-da.com/ design flow
* http://www.averant.com/ design flow
* http://www.agilityds.com/ design flow
* http://www.dilloneng.com Uses Mentor.com to create a higher level working language
* http://www.mentor.com
* http://www.logicvision.com/ Merged with Mentor
* http://www.bluespec.com/
* http://www.altium.com/
* http://www.annapmicro.com
* http://www.logicbricks.com/ IP cores for camera vision distortion
* http://www.mitrionics.com/ With Mitrion you create custom processors, running on FPGAs.
* http://www.eve-team.com/ In competion with mentor
EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics
=== Sundance Simulink to fpga ===
* http://www.sundance.com/prod_info.php?board=PARS 
* http://www.sundance.com/about.php?page=application_stories&story=Altitude%20interference%20mitigation%20module%20system
Key to making the DSP8080-AIMM a reality for the Navy was the decision to use PARS (Parallel Application from Rapid Simulation) design environment. PARS generated the entire target code including, DSP codes, FPGA codes and all of the inter-processor communication and synchronization codes from a Simulink model. The Navy's algorithms were implemented as either IP cores on FPGAs or optimized DSP code targeting the floating and fixed point DSPs.
The DSP8080 utilizes multiple high-performance DSPs from Texas Instruments, including the TMS320C6416, a fixed-point processor running at 1 GHz, and the TMS320C6713, a floating-point DSP. The system also utilizes several Virtex 4 SX55 Xilinx FPGAs with the processing elements mounted onto a range of integrated Sundance platforms including the SMT374, SMT364, SMT318-SX and SMT361Q.
=== video processing ===
http://www.omnitek.tv/fpga-ip-cores
=== Hardware ===
* http://www.nallatech.com/ fpga network processing card
* http://www.gidel.com/
* http://www.ohwr.org FPGA opensource development board
=== Maxeler ===
http://www.maxeler.com/content/frontpage/ Converts JAVA code to FPGA, don't need to know FPGA details so much. Reduces learning curve and opens up FPGA to the masses.
* http://www.wallstreetfpga.com/
http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/when-banks-roll-their-own
In mid-July, JP Morgan announced that it would join the ranks of such institutions, but with a wrinkle. Instead of relying on a board-level financial solutions specialist employing FPGAs, such as Xtreme Data or Wall Street FPGA, Morgan decided it would work with a more generic systems integrator, Maxeler Technologies (http://www.hpcwire.com/hpcwire/2011-07-13/jp_morgan_buys_into_fpga_supercomputing.html). Maxeler is a vertical HPC specialist, bundling hardware with Java compilers, runtime environments, and development tools. Morgan will use the platform for analyzing collateralized debt obligations, those pesky abstracted financial instruments that turned many mortgage bundles into toxic assets in 2007-08.
=== Seasolve Wimax IP ===
* SB3500 Sandblaster chip implements Wimax phy layer
* http://www.optimumsemi-tech.com/sandblaster_ide.html , http://www.optimumsemi-tech.com/products.html The SB3500® series processor changes entirely the rules of wireless product design. Powered by three Sandblaster cores, the SB3500® packs sufficient performance to run the most advanced wireless protocols at power-efficiency levels that rival hardware-centric (ASIC) solutions. Combined with its high-level “C” compiler and intuitive software design tools, the Sandblaster® IDE and Sandblaster® LeaP Development cards, the SB3500® is the first truly universal, flexible processor, providing the ability design, test and revise in simple, intuitive software development methodology.
* http://www.seasolve.com/wimax-ref-design.html Ref design max,phy on single chip sb3500 sandblaster
* http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.103.1999 Abstract. This paper describes a Sandbridge Sandblaster system implementation including both hardware and software elements for a WiMax 802.16e system. The system is implemented on the fully functional multithreaded Sandblaster multiprocessor SB3010 SoC chip. The entire communication protocol, physical layer and MAC, has been implemented in software using pure ANSI C programming language and it executes in real time. In this paper, we also present a radio propagation analysis specific to the Samos island at the workshop location, and the DSP execution performance.
* http://www.mimoon.de/pages/Products/mi-Mobile/ 3G , Wimax SDR radio's for developers. Combine this with 400Mhz RF stage for a 4G solution.
=== MANGO DSP camera solutions ===
http://www.mangodsp.com/default.asp?id=49&productId=20
This combination enables video security devices to analyze video streams and apply a large set of user definable rules. Among these content analysis rules are: traditional VMD, people or vehicles counting, loitering, congestion, video stabilization, slip and fall, video stitching and more.
=== http://www.vitamindinc.com/ ===
http://www.vitamindinc.com/ distinguishes between cars traveling down the road(false alarm) and people loitering. Combine this wiht OpenTLD. A camera trained on the front porch towards the road will trigger an alert only if a person is within the zone and ignore vehicles traveling past.
(or one would have hoped it does, it is just a vanilla motion detection system, no AI, but one can determine the size of the box , thus excluding cats and dogs from triggering alarm)
=== Mixed signal EDA software ===
* http://demosondemand.com/dod/proddemos/frontend/fed_arms.aspx
Links to Cadence, accelicon, ciranova, clio soft, sandwork, synopsys, Tanner EDA, Expedion
=== Hyper computer ===
http://www.starbridgesystems.com/ design flow
Until now, reconfigurable computing has been largely limited to theory because no satisfactory tools have existed to exploit the inherent parallelisms of the underlying programmable hardware, called Field Programmable Gate Arrays (FPGAs). While FPGAs are capable of executing hundreds of thousands of instructions per clock cycle, existing software development tools cannot capture inherent algorithmic parallelisms or complex multi-million gate designs....Most "Grand Challenge" problems are inherently parallel. Once these parallelisms are identified, code can be written (or ported from C, C++, Fortran, or other existing code) to capture these parallel operations, and turn formerly serial operations-or merely distributed operations-into truly parallel algorithms.
=== Journal links ===
 * http://www.dsp-fpga.com/articles/id/?3953
 * http://www.petalogix.com Linux on FPGA
=== What FPGA's do ===
http://tech.slashdot.org/story/03/02/15/1629237/Star-Bridge-FPGA-HAL-More-Than-Just-Hype
=== USB-to-Ethernet IP cores ===
http://www.k-micro.us/products/USB.php
http://www.pricecheck.co.za/products/771366/Manhattan+USB+to+RJ45+10_100+Ethernet+Retail+Box/ R122
http://www.vexon.co.za/vmchk/Converters-USB/Manhattan-USB-to-RJ45-10/100-Ethernet-501262.html
Stlabs USB to Ethernet Adapter
http://www.industrialethernet.com/ubs.html?utm_source=google&utm_medium=cpc&utm_campaign=Ethernet+Products&utm_term=usb+lan+adapter&gclid=CJDhyfyQ4Z4CFWlr4wod513HJA
http://www.industrialethernet.com/ubox.html USB to Ethernet devices server, connect 4 USB devices to Ethernet
=== xmos ===
Implements many FPGA functions in software instead
 * https://www.xmos.com/
 * http://www.xlinkers.com/
=== IP cores for WiMax development ===
 * http://www.ensilica.com/ip_esi_comms.htm Base cores extend to Wimax and 802.11a
 * http://www.chipdesignmag.com/ FPGA industry magazine.
 * SeaSolve is a vendor of IP FPGA cores for Wimax 802.16e PHY and MAC layer.
 * SoftwareDefinedRadio uses FPGA. 
 * http://www.dspfpga.com/?lang=en Camera FPGA like Elphel
 * http://www.zipcores.com/digital-modulation.html Digital-modulation for RF stage
 * http://www.ipcores.com/wimax_802.16e_aes_ccm_core.htm Wimax IP cores Wimax IP cores
 * http://www.amethyst.co.il IP cores for OFDM, Viterbi, Reed-Solomon,Wimax,VDSL2 DsLamError correction etc
 * http://www.microtronix.com/products/?category=3 Video and SDRAM IP cores.
 * http://www.sundance.com/web/files/productpage.asp?STRFilter=DVIP
 * http://www.cadrecodesign.com/technology.html Sundance uses their IP cores
 * http://www.s3group.com/ IP cores 
 * http://www.calypto.com System C
 * http://www.coware.com/PDF/products/SignalProcessingDesigner.pdf 3G, CDMA, WiMax
 * http://www.forteds.com/
 * http://www.hitechglobal.com/ Distributes IP cores
 * http://www.design-reuse.com Lists IP core distributors
 * http://www.delphieng.com/adc3255_dk.asp
 * http://fpgablog.com/posts/cpri-air-interface/ Altera Wimax cores
 * http://www.turboconcept.com/ Altera partner for Wimax
 * http://www.dspia.com Design tools
http://www.dilloneng.com uses the http://www.mentor.com/products/fpga/synthesis/leonardo_spectrum for their FFT routines which they in turn licensed to http://www.sundance.com for the creation of 4G LTE and WiMax systems on FPGA.
=== IP cores ===
brahms_view@yahoo.it MPEG4
=== Wimax development platforms ===
 * http://fpgablog.com/posts/titanv5-xilinx-virtex-fpga/ Four A/D D/A converters with three Virtex-5 FPGA's
 * http://www.sundance.com/web/files/enews_link.asp?id=radio_giga 4G Wimax and LTE hardware platfom and
http://www.sundance.com/web/files/productpage.asp?STRFilter=SMT9091. Cadence has licensed 802.16 PHY and MAC layer for their Gigabit 4G radio development platform. LTE, Wimax, CDMA , UWB are 4G systems. Use the Sundance WiMax development platform loaded with a complete Wimax IP core from SeaSolve for prototyping work. After the design has been verified it is embedded with a dedicated FPGA core for mass distribution via our FrontingCompany to implement a WiMax and FreeSpaceOptics solution on any frequency. http://www.dilloneng.com used http://www.mentorgraphics.com to develop FFT IP cores licensed to Sundance. This allows a developer to implement the Viterbi, FFT, Reed-Solomon cores as building blocks without undue effort on the low level verilog code of an FPGA. There are numerous software patents on Reed-Solomon driving up the price of equipment, hence the use of a FrontingCompany.
=== FPGA based cameras ===
 * http://www.yankeerobotics.com/ Uses FPGA from Dilloeng.com
 * http://www.matrox.com/imaging/buy/home.cfm
 * http://signalconditioningsolutions.com/Aptina-Image-Sensor-Demo-Headboard-Kits.php
 * http://www.dvinfo.net/conf/apertus-open-source-cinema-project/114676-elphel-image-quality-4.html
 * http://www.optomotive.si/ FPGA camera
 * Uses http://www.aptina.com/products/image_sensors/mt9v034c12stm/ image sensor
 * http://www.visengi.com/products/jpeg_hardware_encoder JPEG on FPGA
=== Calypto powerpro ===
http://www.calypto.com PowerProTM CG 2.2 was released on April 15, 2009. This release includes several new enhancements and features including:
* Automatic handling of complex clock-networks
* Enhanced to allow modification of VHDL designs with component declarations and configurations as well as improve QOR of VHDL designs
* Support for asynchronous resets across clock-domains
=== PowerPc on FPGA ===
 * http://www.linuxjournal.com/article/9362
 * http://www.istockanalyst.com/article/viewiStockNews/articleid/2525970
=== FPGA consultants ===
 * http://www.mentor.com/products/fpga/fpga_flow_demo.cfm?PC=L&c=2009_04_fpga_technical_news Mentor web video
 * http://www.c-cor.com/
 * http://www.coreworks.pt/
 * http://www.synplicity.com/products/prototyping_solutions.html
 * http://www.hunt-fpga.com/
 * http://www.dspia.com/
=== Asics encoder-decoder cores ===
Unlimited licensed Reed-Solomon encoder and decoder cores are between $30,000 - $40,000 depending on whether a netlist or sourcecode is desired. Error correction upto 2.5G for a GPON network is possible.
http://www.asics.ws/ FPGA design house
=== Viterbi ===
http://www.design-reuse.com/sip/view.php?id=16110
The R3VIT-WIMAXis a second generation Viterbi decoder targeted for WiMax and Wireless LAN applications. The decoder utilizes an advanced area-efficient architecture which places the traceback memory in RAM with no latency penalty. The design is targeted for use in ASICs and FPGAs. Input symbol metric pairs are decoded into output data bits by the maximum likelihood Viterbi processor core. Input symbol wordlength is selectable. Processor core is optimized for decoding the 133,171 encoder used in 802.11a/g and 802.16 applications.
* http://viterbi-gen.sourceforge.net
* http://opencores.org/?do=project&who=vhcg
* http://www.design-reuse.com/sip/view.php?id=14428 Amethyst Communication Technologies '$10000
* http://www.design-reuse.com/sip/wanted/?id=1304 FFT cores on offer
=== Mathworks ===
 * Mathematical modeling of OFDM using simulink and other high level non-C++ design tools:
http://www.mathworks.com/applications/dsp_comm/userstories.html?file=19636&title=Harman%20Becker%20Designs%20and%20Verifies%20OFDM%20Radio%20Receivers%20Using%20MathWorks%20Tools
=== Sundance radiogiga ===
http://www.3l.com/index.php?option=com_content&view=article&id=41&Itemid=47&3427b79b981394ee803ac6f92d0cb1a2=89689185b6a698270f6f74ec9cef2f17
One final thought, if the MIT team were able to achieve what they did using Virtex2 Pro FPGA for their signal processing module, imagine the possibilities if they revisited their UWB design using the latest Sundance 'Radio Giga' solution that features Virtex 5 Xilinx FPGAs, Dual C Series TI DSP engines with 260MBytes/s Serial RapidIO (SRIO) communication links, Power PC processor cores and 6 channels of low power GHz ADC. If you'd like to take the 'imagine' and convert it to 'reality', get a Radio Giga system.
http://www.mathworks.com/products/instrument/supportedio.html Sundance partner
=== CADENCE ===
Website?
=== C language to Verilog ===
* http://www.forteds.com/
After closely evaluating Forte's Cynthesizer and other options in behavioral synthesis and verification, Epson picked Forte's behavioral synthesis as the high-level design technology we will incorporate into our design flow for our next generation consumer products in our development projects. Conventional design methods can not utilize design results of algorithm verification at the C language level forcing RTL designers to hand-coded their hardware. We have now confirmed that we obtain consistent quality of results at the C language level and the hardware (RTL) design by incorporating Forte's Cynthesizer into our system-level development process. We have chosen Cynthesizer for the design projects in our division and are aiming for significant reduction in SoCs development time by designing IP reusable in other projects and deriving projects."
=== High level to HDL ===
System generator, AccelDSP and Simulink, low-level HDL coding can be skipped, and the engineer can focus more on applications and less on the "bit-level" of things.
=== links ===
http://www.design-reuse.com/sip/
http://www.visengi.com/en/products/zbt_sram_controller Memory interfacing
http://www.fpgacentral.com/fpga-eda-tools/xilinx/system-generator-dsp
http://www.fpgacentral.com/fpga-ip/core/ieee-802-16e-ldpc-encoder
http://www.hunt-fpga.com/info/index.htm?crtag-cr&gclid=CKOP_qKatZkCFQ0gQgod83Ji5A
http://www.fpgaworld.com/
http://www.fpga4fun.com/index.html
http://www.xilinx.com/ise/embedded/edk_examples.htm Ethernet examples 100meg
http://www.innovative-dsp.com/products.php?product=SBC-ComEx%20Embedded%20PC
http://www.xilinx.com/esp/wireless.htm#baseband Xilinx baseband wimax processing
http://www.codetronix.com/?gclid=CLOZ8_u2qpgCFQsyQgodtXKPnA
http://www.edaboard.com/forums.html
=== optics ===
http://adsabs.harvard.edu/abs/2001SPIE.4455..160B
Demonstrating optoelectronic interconnect in a FPGA-based prototype system using flip-chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways
=== Gigabyte PHY ===
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/185337d3f6aa19e7# physical layer gigabyte
National Semi DP83865 Gigabit Ethernet PHY
I did find the ET1011C from LSI (formerly Agere). It is cheap, low power, available, and they give out the datasheets without an NDA. Anybody have any experience with it?
=== asdf ===
http://www.dspdesignline.com/showArticle.jhtml?articleID=202101657
In contrast, ESL tools for FPGAs have many different entry points. Tools like Catapult C and Impulse C use C or C++ as an entry point. Xilinx's AccelDSP uses the MATLAB language. Other tools use a graphical dataflow, such as Simulink or LabView. What's worse, devices from different vendors have different (and incompatible) high-level tool flows. Since designers often use more than one tool flow—and may have to learn multiple unrelated "languages" to get the best results—the learning curve for FPGA design is still unnecessarily steep. Furthermore, if designers switch tool flows or FPGA vendors, they have to start the learning process all over again.
http://en.wikipedia.org/wiki/Electronic_system_level
http://www.xilinx.com/ise/dsp_design_prod/acceldsp/index.htm
http://www.mathworks.com/products/simulink/
http://www.ni.com/labview/
http://en.wikipedia.org/wiki/SystemC
http://www.systemc.org/home
http://www.impulsec.com/
http://www.openpattern.org/
=== USB fpga ===
 * http://www.opalkelly.com/products/xem3050/
http://www.designnews.com/article/161104-FPGA_USB_Module_Cuts_Design_Time_Cost.php
Engineers at Opal Kelly, designers of the new module, say it simplifies product development through the use of software called FrontPanel, which eliminates the details involved in USB design work. "The difficulty in building a USB solution is primarily one of software," notes Jake Janovetz, founder and president of Opal Kelly. "In most complicated USB designs, one needs to develop drivers and build some kind of link to the hardware. We've tried to mitigate all that design effort."
=== Cornell ===
 * http://instruct1.cit.cornell.edu/courses/ece576/FinalProjects/
=== Blog ===
http://fpgablog.com/posts/lattice-ip-core/
=== Ethernet on FPGA ===
http://www.chipethernet.com/
{{{
Gigabit Ethernet IP core for Xilinx FPGA
Ethernet MAC IP cores for Xilinx
IP cores for Ethernet MAC
IEEE 1588 Clock IP core
IEC 61158 ( aka EtherCAT ) IP core
Streaming Data Ethernet network
IP cores for Xilinx FPGA
Ethernet MAC IP cores for FPGA
Gb , 100Mb Ethernet MAC IP cores for Xilinx FPGA
Ethernet MAC IP cores for Altera, Actel, Lattice, Quick Logic
IP cores for Gb Ethernet MAC for Xilinx, Altera, Actel, Lattice, Quick Logic
IP cores for 100 Mb Ethernet MAC
Ethernet MAC IP cores for Spartan, Virtex FPGA
}}}
=== Opencores projects ===
* http://www.chipethernet.com/
* http://www.digicomcore.com/ipcores.html Digital modulation codes
* http://www.opencores.org/projects.cgi/web/fbas_encoder/overview
* http://www.ipcores.com/
* http://www.ipcores.com/wimax_802.16e_aes_ccm_core.htm Wimax IP cores
* http://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core
* http://www.design-reuse.com/download/sip/
* http://www.4dsp.com/ipcores.htm
* http://www.spectrumsignal.com/products/hcdr/fpga_ip_cores.asp
* http://www.spectrumsignal.com/products-services/carriers-modules/fn-rf-boards/rf-4902/ 200mhz - 2.7ghz RF transciever
* http://www.arasan.com/
* http://www.linuxdevices.com/news/NS8480767767.html
* http://www.commsdesign.com/story/OEG20030612S0016
* http://www.commsdesign.com/story/OEG20030612S0016 FFT $2000
* http://www.linuxdevices.com/news/NS8480767767.html FPGA
* http://www.elec.york.ac.uk/research/comms/sigProc/fpga.html
=== Agilent ===
* http://www.commsdesign.com/new_products/showArticle.jhtml?articleID=214502298 LTE testbench
* http://www.design-reuse.com/sip/view.php?id=15762 Coresonic Wimax
=== FPGA ===
http://www.systemcrafter.com
=== Intel ===
Intel fpga will be able to port these github repos to FpGa. It also allows for automatic productivity labor monitoring and decentralized manufacturing. Porting to FPGA and dsp is done from c code, not C++.
=== links ===
 * http://www.fpgajournal.com/news_2005/07/20050725_02.htm
 * http://www.altera.com
 * http://www.morphologic.dk/products/mpl3e.php
FreescaleDsp , TexasInstamod
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