LastCharacter485

Category:Sasecurity
http://groups.google.com/group/comp.arch.embedded/browse_frm/thread/a8155cfd27033065/7daf5a76c1af30f8?lnk=gst&q=RS485&rnum=12#7daf5a76c1af30f8
=== Not disable transmitter till after last char ===
Just replace the RS232 driver chip(s) with RS485 drivers,e.g. MAX485.
Watch for the heffalump trap though- you must not disable the
transmitter until AFTER the last character has been sent. I've done this
in the past by marking the end of a transmitted string (either by a
character e.g. XOFF, or by character count), and at the end starting a
timer to alow the last character to go before disabling the transmitter. 
=== sbuf and shift register ===
> Are you telling me that the 8051 transmitter is double-buffered and the
> transmit-done interrupt actually indicates that the first buffer is
> empty, while the chip is still transmitting from the second buffer?
Of course. You have SBUF and then the shift register. When the SBUF is
loaded into the shift register TI is asserted, however you still have 9 or
10 bit times before the initial character is fully "on the wire". 
AGH! Ignore my previous post! I was thinking of receive! Receive is double
buffered, not Tx. From Intel's "MCS-51 MICROCONTROLLER FAMILY USER’S
MANUAL", p. 3-17:
"As data bits shift out to the right, zeroes come in from the left. When
the MSB of the data byte is at the output position of the shift register,
then the 1 that wasinitially loaded into the 9th position, is just to the
left of the MSB,and all positions to the left of that contain zeroes. This
condition flags the TX Control block to do one last shift and then
deactivate SEND and set TI Both of these actions occur at SIP1 of the 10th
machine cycle after "write to SBUF"."
So TI is not set until the last bit of your byte (including stop bit(s))
has been placed on the wire. 
=== RI interrupt signals end of transmission ===
This technique is usually quite efficient, since the CPU can be
preparing further data while the byte is being shipped without
causing transmission breaks. If the UART has an 'all bits sent'
output pin, it can be used directly to control the RS485 transmit
on condition, without needing any CPU intervention. However, that
is a fairly large if.
A technique I have used in the past is to enable the receiver
during RS485 transmission. Then the echo does two things - it
confirms no collisions occured, if correct, and the receive
interrupt signals the end of the transmission period. 
=== 8051 issues on timing diagram ===
Not dreadfully sure for the 8051. The data book seems to show the TI bit
setting when the last DATA bit is shifted out. Meaning you would still
chop off the tail of the stop bit if you disable the driver immediately.
> Not dreadfully sure for the 8051. The data book seems to show the
> TI bit setting when the last DATA bit is shifted out. Meaning you
> would still chop off the tail of the stop bit if you disable the
> driver immediately.
The stop bit should be the 'line quiescent' condition, so any chop
off should do nothing harmful if the line is properly biased.