Buggy code:
public class lab3 { private static int [ ] memory = new int [ 8192 ] ; private static int pc = 0 ; private static HashMap < String , Integer > registers = new HashMap < String , Integer > ( ) ; private static HashMap < String , Integer > labels = new HashMap < String , Integer > ( ) ; private static ArrayList < String > labelQueue = new ArrayList < String > ( ) ; private static ArrayList < Instruction > program = new ArrayList < Instruction > ( ) ; private static ArrayList < String > R_INSTRUCTIONS = new ArrayList < String > ( ) ; private static ArrayList < String > I_INSTRUCTIONS = new ArrayList < String > ( ) ; private static ArrayList < String > J_INSTRUCTIONS = new ArrayList < String > ( ) ; public static void main ( String [ ] args ) { } private static void initASM ( String fileName ) { } @ SuppressWarnings ( "resource" ) private static void translateAssembly ( String fmtedAsm , HashMap < String , Integer > labels ) { } private static String removeComments ( String line ) { } private static void printHelp ( ) { } private static void printRegisters ( ) { } private static void step ( int numSteps ) { } private static void step ( ) { Instruction i = lab3 . program . get ( lab3 . pc ) ; String instruction = i . getInstruction ( ) ; System . out . println ( i . toString ( ) ) ; ImmediateInstruction ii = null ; RegisterInstruction ri = null ; JumpInstruction ji = null ; int rs ; int rt ; switch ( instruction ) { case "addi" : ii = ( ( ImmediateInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ii . rs ) ; lab3 . registers . put ( ii . rt , ( rs + ( ii . imm ) ) ) ; ( lab3 . pc ) ++ ; break ; case "beq" : ii = ( ( ImmediateInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ii . rs ) ; rt = lab3 . registers . get ( ii . rt ) ; if ( rs == rt ) { lab3 . pc = ii . imm ; } else { ( lab3 . pc ) ++ ; } break ; case "bne" : ii = ( ( ImmediateInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ii . rs ) ; rt = lab3 . registers . get ( ii . rt ) ; if ( rs != rt ) { lab3 . pc = ii . imm ; } else { ( lab3 . pc ) ++ ; } break ; case "lw" : ii = ( ( ImmediateInstruction ) ( i ) ) ; rt = lab3 . registers . get ( ii . rt ) ; lab3 . registers . put ( ii . rs , lab3 . memory [ rt ] ) ; ( lab3 . pc ) ++ ; break ; case "sw" : ii = ( ( ImmediateInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ii . rs ) ; rt = lab3 . registers . get ( ii . rt ) ; <START_BUG> lab3 . memory [ rs ] = rt ; <END_BUG> ( lab3 . pc ) ++ ; break ; case "and" : ri = ( ( RegisterInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ri . rs ) ; rt = lab3 . registers . get ( ri . rt ) ; lab3 . registers . put ( ri . rd , ( rs & rt ) ) ; ( lab3 . pc ) ++ ; break ; case "or" : ri = ( ( RegisterInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ri . rs ) ; rt = lab3 . registers . get ( ri . rt ) ; lab3 . registers . put ( ri . rd , ( rs | rt ) ) ; ( lab3 . pc ) ++ ; break ; case "add" : ri = ( ( RegisterInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ri . rs ) ; rt = lab3 . registers . get ( ri . rt ) ; lab3 . registers . put ( ri . rd , ( rs + rt ) ) ; ( lab3 . pc ) ++ ; break ; case "sll" : ri = ( ( RegisterInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ri . rs ) ; lab3 . registers . put ( ri . rd , ( rs << ( ri . shamt ) ) ) ; ( lab3 . pc ) ++ ; break ; case "sub" : ri = ( ( RegisterInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ri . rs ) ; rt = lab3 . registers . get ( ri . rt ) ; lab3 . registers . put ( ri . rd , ( rs - rt ) ) ; ( lab3 . pc ) ++ ; break ; case "slt" : ri = ( ( RegisterInstruction ) ( i ) ) ; rs = lab3 . registers . get ( ri . rs ) ; rt = lab3 . registers . get ( ri . rt ) ; if ( rs < rt ) { lab3 . registers . put ( ri . rd , 1 ) ; } else { lab3 . registers . put ( ri . rd , 0 ) ; }

Fix:
lab3 . memory [ ( rs + ( ii . imm ) ) ] = rt ;