Program: 5710
Project: 5710
Buggy source:
public void dataReceived(USART source,int data){
  int oldStatus=status;
  if (DEBUG) {
    System.out.println("String_Node_Str" + Utils.hex8(data) + "String_Node_Str"+ ((data >= ' ' && data <= 'Z') ? (char)data : '.')+ ')'+ "String_Node_Str"+ chipSelect+ "String_Node_Str"+ state+ "String_Node_Str"+ stateMachine);
  }
  if ((stateMachine != STATE_VREG_OFF) && chipSelect) {
switch (state) {
case WAITING:
      if ((data & FLAG_READ) != 0) {
        state=READ_REGISTER;
      }
 else {
        state=WRITE_REGISTER;
      }
    if ((data & FLAG_RAM) != 0) {
      state=RAM_ACCESS;
      address=data & 0x7f;
    }
 else {
      address=data & 0x3f;
      if (address == REG_RXFIFO) {
        state=READ_RXFIFO;
      }
 else       if (address == REG_TXFIFO) {
        state=WRITE_TXFIFO;
      }
    }
  if (data < 0x0f) {
    strobe(data);
  }
pos=0;
break;
case WRITE_REGISTER:
if (pos == 0) {
source.byteReceived(registers[address] >> 8);
registers[address]=(registers[address] & 0xff) | (data << 8);
pos=1;
}
 else {
source.byteReceived(registers[address] & 0xff);
registers[address]=(registers[address] & 0xff00) | data;
state=WAITING;
}
break;
case READ_REGISTER:
if (pos == 0) {
source.byteReceived(registers[address] >> 8);
pos=1;
}
 else {
source.byteReceived(registers[address] & 0xff);
if (DEBUG) {
System.out.println("String_Node_Str" + Utils.hex8(address) + "String_Node_Str"+ registers[address]);
}
state=WAITING;
}
return;
case READ_RXFIFO:
if (rxfifoLen == 0) break;
if (DEBUG) System.out.println("String_Node_Str" + rxfifoReadPos + "String_Node_Str"+ (memory[RAM_RXFIFO + rxfifoReadPos] & 0xFF));
source.byteReceived((memory[RAM_RXFIFO + rxfifoReadPos] & 0xFF));
rxfifoReadPos++;
setFIFOP(false);
if (--rxfifoLen == 0) setFIFO(false);
if (rxfifoReadPos >= 128) {
rxfifoReadPos=0;
}
if (rxPacket) {
rxPacket=false;
setFIFOP(false);
}
return;
case WRITE_TXFIFO:
if (txfifoFlush) {
txCursor=0;
txfifoFlush=false;
}
if (DEBUG) System.out.println("String_Node_Str" + data + "String_Node_Str"+ txCursor);
memory[RAM_TXFIFO + txCursor++]=data & 0xff;
break;
case RAM_ACCESS:
if (pos == 0) {
address=address | (data << 1) & 0x180;
ramRead=(data & 0x20) != 0;
if (DEBUG) {
System.out.println("String_Node_Str" + Utils.hex16(address) + "String_Node_Str"+ ramRead);
}
pos++;
}
 else {
if (!ramRead) {
memory[address++]=data;
if (DEBUG && address == RAM_PANID + 2) {
System.out.println("String_Node_Str" + Utils.hex8(memory[RAM_PANID]) + Utils.hex8(memory[RAM_PANID + 1]));
}
}
 else {
source.byteReceived(memory[address++]);
return;
}
}
break;
}
source.byteReceived(oldStatus);
}
}

Fixed version (ground truth):
public void dataReceived(USART source,int data){
  int oldStatus=status;
  if (DEBUG) {
    System.out.println("String_Node_Str" + Utils.hex8(data) + "String_Node_Str"+ ((data >= ' ' && data <= 'Z') ? (char)data : '.')+ ')'+ "String_Node_Str"+ chipSelect+ "String_Node_Str"+ state+ "String_Node_Str"+ stateMachine);
  }
  if ((stateMachine != STATE_VREG_OFF) && chipSelect) {
switch (state) {
case WAITING:
      if ((data & FLAG_READ) != 0) {
        state=READ_REGISTER;
      }
 else {
        state=WRITE_REGISTER;
      }
    if ((data & FLAG_RAM) != 0) {
      state=RAM_ACCESS;
      address=data & 0x7f;
    }
 else {
      address=data & 0x3f;
      if (address == REG_RXFIFO) {
        state=READ_RXFIFO;
      }
 else       if (address == REG_TXFIFO) {
        state=WRITE_TXFIFO;
      }
    }
  if (data < 0x0f) {
    strobe(data);
    state=WAITING;
  }
pos=0;
break;
case WRITE_REGISTER:
if (pos == 0) {
source.byteReceived(registers[address] >> 8);
registers[address]=(registers[address] & 0xff) | (data << 8);
pos=1;
}
 else {
source.byteReceived(registers[address] & 0xff);
registers[address]=(registers[address] & 0xff00) | data;
if (DEBUG) {
System.out.println("String_Node_Str" + Utils.hex8(address) + "String_Node_Str"+ registers[address]);
switch (address) {
case REG_IOCFG0:
  System.out.println("String_Node_Str" + registers[address]);
break;
case REG_IOCFG1:
System.out.println("String_Node_Str" + ((registers[address] & SFDMUX) >> SFDMUX) + "String_Node_Str"+ (registers[address] & CCAMUX));
if ((registers[address] & CCAMUX) == CCA_CCA) setCCA(false);
break;
}
}
state=WAITING;
}
break;
case READ_REGISTER:
if (pos == 0) {
source.byteReceived(registers[address] >> 8);
pos=1;
}
 else {
source.byteReceived(registers[address] & 0xff);
if (DEBUG) {
System.out.println("String_Node_Str" + Utils.hex8(address) + "String_Node_Str"+ registers[address]);
}
state=WAITING;
}
return;
case READ_RXFIFO:
if (rxfifoLen == 0) break;
if (DEBUG) System.out.println("String_Node_Str" + rxfifoReadPos + "String_Node_Str"+ (memory[RAM_RXFIFO + rxfifoReadPos] & 0xFF));
source.byteReceived((memory[RAM_RXFIFO + rxfifoReadPos] & 0xFF));
rxfifoReadPos++;
setFIFOP(false);
if (--rxfifoLen == 0) setFIFO(false);
if (rxfifoReadPos >= 128) {
rxfifoReadPos=0;
}
if (rxPacket) {
rxPacket=false;
setFIFOP(false);
}
return;
case WRITE_TXFIFO:
if (txfifoFlush) {
txCursor=0;
txfifoFlush=false;
}
if (DEBUG) System.out.println("String_Node_Str" + data + "String_Node_Str"+ txCursor);
memory[RAM_TXFIFO + txCursor++]=data & 0xff;
break;
case RAM_ACCESS:
if (pos == 0) {
address=address | (data << 1) & 0x180;
ramRead=(data & 0x20) != 0;
if (DEBUG) {
System.out.println("String_Node_Str" + Utils.hex16(address) + "String_Node_Str"+ ramRead);
}
pos++;
}
 else {
if (!ramRead) {
memory[address++]=data;
if (DEBUG && address == RAM_PANID + 2) {
System.out.println("String_Node_Str" + Utils.hex8(memory[RAM_PANID]) + Utils.hex8(memory[RAM_PANID + 1]));
}
}
 else {
source.byteReceived(memory[address++]);
return;
}
}
break;
}
source.byteReceived(oldStatus);
}
}