Query: fluctuatuin Reconfigurable nanowire silicon

Candidate papers:

abstract: We report on ambipolar gate defined quantum dots in silicon on insulator (SOI) nanowires fabricated using a customised complementary metal oxide semiconductor (CMOS) process. The ambipolarity was achieved by extending a gate over an intrinsic silicon channel to both highly doped n type and p type terminals. We utilise the ability to supply ambipolar carrier reservoirs to the silicon channel to demonstrate an ability to reconfigurably define, with the same electrodes, double quantum dots with either holes or electrons. We use gate based reflectometry to sense the inter dot charge transition(IDT) of both electron and hole double quantum dots, achieving a minimum integration time of 160(100) \mu$s for electrons (holes) Our results present the opportunity to combine, in a single device, the long coherence times of electron spins with the electrically controllable holes spins in silicon.
author_names: Jingyu Duan

Janne Samuel Lehtinen

Michael A Fogarty

Simon Schaal

Michelle Lam

Alberto Ronzani

Andrey Shchepetov

P J Koppinen

Mika Prunnila

Fernando Gonzalez-Zalba

John J L Morton
title: Dispersive readout of reconfigurable ambipolar quantum dots in a silicon on insulator nanowire
year: 2020

abstract: Silicon Nanowire (SiNW) based reconfigurable field effect transistors (RFETs) provide an additional gate terminal called the program gate which gives the freedom of programming p type or n type functionality for the same device at runtime. This enables the circuit designers to pack more functionality per computational unit. This saves processing costs as only one device type is required, and no doping and associated lithography steps are needed for this technology. In this paper, we present a complete design flow including both logic and physical synthesis for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors. We show that in the first of its kind comparison, for these fully symmetrical reconfigurable transistors, the area after placement and routing for SiNW based circuits is 17% more than that of CMOS for MCNC benchmarks. Further, we discuss areas of improvement for obtaining better area results from the SiNW based RFETs from a fabrication and technology point of view. The future use of self aligned techniques to structure two independent gates within a smaller pitch holds the promise of substantial area reduction.
author_names: Shubham Rai

Ansh Rupani

Dennis Walter

Michael Raitza

Andre Heinzig

Tim Baldauf

Jens Trommer

Christian Mayr

Walter M Weber

Akash Kumar
title: A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
venue: 2018 Design, Automation Test in Europe Conference Exhibition (DATE)
year: 2018

abstract: Efficient circuit designs can make use of ambipolar nature of silicon nanowire (SiNW) over CMOS. Conventional circuit Design Flow fails to use this inherent functional flexibility as CMOS based mapping considers a single logical output from logic gates. To address this, we propose an area optimized technology mapping which uses this innate reconfigurability, offered by SiNW transistors for efficient circuit designs. To enable this objective, we use higher order functions (HOF) to encapsulate this extended functionality. Additionally, the electrical properties of SiNW allow us to take advantage of the available inverted forms of fan ins for additional savings of area for XOR logic family. Experimental results using our technology mapping show that area of SiNW based logic design is less by an average of 18.38% as compared to CMOS flow for complete MCNC benchmarks suite. Further, we evaluate our flow for both reconfigurability aware and static layout for SiNW based logic gates. The whole flow including the new SiNW based genlib and the modified ABC tool is made available under open source license to enable further research for any kind of emerging ambipolar transistors.
author_names: Shubham Rai

Michael Raitza

Akash Kumar
title: Technology mapping flow for emerging reconfigurable silicon nanowire transistors
venue: 2018 Design, Automation Test in Europe Conference Exhibition (DATE)
year: 2018

abstract: In this article, the impact of intrinsic process fluctuations on reconfigurable field effect transistor (RFET) is investigated for the first time. Three kinds of process fluctuation sources, including line edge roughness (LER) gate edge roughness (GER) and work function variation (WFV) are performed in RFET using MATLAB and 3 D TCAD. The variation of ON state current <inline formula> <tex math notation="LaTeX"{I}_{ \mathrm{\scriptscriptstyle ON} /tex math>/inline formula> due to LER presents a weak correlation with that of OFF state current <inline formula> <tex math notation="LaTeX"{I}_{ \mathrm{\scriptscriptstyle OFF} /tex math>/inline formula> Performance variation caused by GER is mainly attributed to the control GER. WFV in control gate and source dominates the variations of ON state characteristics. The total overall performance fluctuations are primarily attributed to WFV. In the sight of <inline formula> <tex math notation="LaTeX"{I}_{ \mathrm{\scriptscriptstyle ON} /tex math>/inline formula> WFV contributed up to 84.7% and 82.8% of the total fluctuations for n and p type, respectively.
author_names: Xianglong Li

Xiaoqiao Yang

Zhe Zhang

Teng Wang

Yabin Sun

Ziyu Liu

Xiaojin Li

Yanling Shi

Jun Xu
title: Impact of Process Fluctuations on Reconfigurable Silicon Nanowire Transistor
venue: IEEE Transactions on Electron Devices
year: 2021

abstract: We present a novel reconfigurable metal oxide semiconductor multi gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple gate silicon nanowire field effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.
author_names: Andreas C Betz

Marco Lorenzo Valerio Tagliaferri

Maud Vinet

Myles L Brostrom

Marc Sanquer

Andrew J Ferguson

Miguel Fernando Gonzalez-Zalba
title: Reconfigurable quadruple quantum dots in a silicon nanowire transistor
year: 2016

abstract: Mechanical stress has the potential to be an efficient performance booster for diverse emerging research devices based on tunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable FETs. The effect is highly dependent on the constellation between the stress source and the crystal orientation. Although stress engineering is well established for enhancement carrier mobility, it is rather unexplored for the control of tunneling. In this work stress profiles formed by four different sources are studied by device simulations of reconfigurable silicon nanowire transistor using two independently gated Schottky junctions. Self limited oxidation of the intrinsic silicon nanowire is used as an example to describe the effects of mechanical stress on the multi valley band structure applying the deformation potential theory and on the average effective tunneling mass. The transfer characteristics of strained n and p type transistors are analyzed with respect to the current ratio between electron and hole conduction which is important to implement reconfigurable CMOS circuits. It has been verified that mechanical stress formed by oxidation as well as stressed top layers are effective options to control the current injection through the Schottky junctions and thus to achieve symmetric operation of reconfigurable nanowire devices.
author_names: Tim Baldauf

Andre Heinzig

Thomas Mikolajick

Walter M Weber

Jens Trommer
title: Strain engineering for improved tunneling in reconfigurable silicon nanowire transistors
venue: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI ULIS)
year: 2016

author_names: Sangeeta Singh

Pravin Neminath Kondekar

Ruchir Sinha
title: Estimation of Analog/Radio Frequency Figures of Merits and Circuit Performance of Dynamically Reconfigurable Electrostatically Doped Silicon Nanowire Schottky Barrier FET
year: 2017

abstract: Reconfigurable silicon nanowire field effect transistors (RFETs) combine the functionality of classical unipolar p type and n type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between pand n functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including NAND/NOR, AND/OR, and XOR/XNOR, and compared them with classical implementations. Two 1 bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.
author_names: Jens Trommer

Andre Heinzig

Tim Baldauf

Stefan Slesazeck

Thomas Mikolajick

Walter M Weber
title: Functionality Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors
venue: IEEE Transactions on Nanotechnology
year: 2015

abstract: Abstract In this paper, an ultra steep, symmetric and dynamically configurable, electrostatically doped silicon nanowire Schottky FET (E SiNW SB FET) based on dopant free technology is investigated. It achieves the ultra steep sub threshold slope (SS) due to the cumulative effect of weak impact ionization induced positive feedback and electrostatic modulation of Schottky barrier heights at both source and drain terminals. It consists of axial nanowire heterostructure (silicide intrinsic silicon silicide) with three independent all around gates, two gates are polarity control gates for dynamically reconfiguring the device polarity by modulating the effective Schottky barrier heights and a control gate switches the device ON and OFF. The most interesting features of the proposed structure are simplified fabrication process as the state of the art for ion implantation and high thermal budget no more required for annealing. It is highly immune to process variations, doping control issues and random dopant fluctuations (RDF) and there are no mobility degradation issues related to high doping. A calibrated 3 D TCAD simulation results exhibit the SS of 2 mV/dec for n type E SiNW SB FET and 9 mV/dec for p type E SiNW SB FET for about five decades of current. Further, it resolves all the reliability related issues of IMOS as hot electron effects are no more limiting our device performance. It offers significant drive current of the order of 10 5 10 4 A and magnificently high I ON I OFF ratio of ~10 8 along with the inherent advantages of symmetric device structure for its circuit realization.
author_names: Sangeeta Singh

Ruchir Sinha

Pravin Neminath Kondekar
title: A novel ultra steep dynamically reconfigurable electrostatically doped silicon nanowire Schottky Barrier FET
year: 2016

abstract: Device reconfigurability refers to the ability to choose N or P type for the same structure. Such reconfigurable operation is demonstrated herein for a silicon nanotube (SiNT) structure using three dimensional (3D) technology computer aided design (TCAD) numerical simulations. The reconfigurable field effect transistor (RFET) can exhibit N or P type operation via the application of an appropriate bias to a program gate. The regular (i.e. control) gate is also present in the RFET. In the planar nanowire structure, the program gate is placed beside the regular/control gate. Since the SiNT structure has both inner and outer gates, we propose to use the inner gate as the control gate and the outer gate as the program gate, to achieve device reconfigurability in the SiNT structure. Two approaches are presented to achieve such reconfigurability, based on a (1) single or (2) double program gate. The metrics considered in this work are the ON current I ON OFF current I OFF \frac{{I_{\text{ON} {I_{\text{OFF} I ON I OFF ratio, and unity gain cutoff frequency f T The effects of the outer diameter, inner diameter, and tube wall thickness of the tube are also discussed. The outer and inner diameters of the tube are found to determine the above mentioned performance parameters. While a smaller inner diameter is preferred from the point of view of the \frac{{I_{\text{ON} {I_{\text{OFF} I ON I OFF ratio, a larger inner diameter is desired from the radio frequency (RF) perspective.
author_names: A Nisha Justeena

R Ambika

Priyamvada Sadagopan

R Srinivasan
title: Reconfigurable silicon nanotube using numerical simulations
year: 2020