Query: [5] Complementary tunneling transistor for low power application

Candidate papers:

abstract: Abstract The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a "tunneling epoch" in which multiple leakage current induced by different tunneling effects exist. The complementary Si based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band to band tunneling current is be controlled by the gate to source voltage. Due to the reverse biased p i n diode structure, an ultra low leakage current is achieved. The sub threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
author_names: Pengfei Wang

K Hilsenbeck

Thomas Nirschl

M Oswald

Christoph Stepper

M Weis

Doris Schmitt-Landsiedel

Walter Hansch
title: Complementary tunneling transistor for low power application
year: 2004

abstract: One of the major roadblocks to further scaling of complementary metal oxide semiconductor (CMOS) devices is power consumption. Reduction of power consumption requires low operation voltage, which requires low threshold voltage. In order to decrease the threshold voltage without excessive increase of OFF current, reduction of the subthreshold swing is essential. To reduce the subthreshold swing, various carrier injection mechanisms other than thermal carrier injection have been proposed. Currently, interband tunneling is the most promising mechanism and the device that utilizes such a mechanism is a tunneling field effect transistor (TFET) After the introduction to the fundamentals of TFETs, various approaches to increase the drain current of Si TFETs by device structure engineering are described. The last section focuses on bandgap engineering to enhance the drain current of TFETs.
author_names: Byung-Gook Park
title: Tunneling Field Effect Transistors for Ultra Low Power Application
year: 2016

abstract: The continuous down scaling of transistors has been the key to the successful development of current information technology. However, with Moore's law reaching its limits, the development of alternative transistor architectures is urgently needed 1 Transistors require a switching voltage of at least 60 mV for each tenfold increase in current, that is, a subthreshold swing (SS) of 60 mV per decade (dec) Alternative tunnel field effect transistors (TFETs) are widely studied to achieve a sub thermionic SS and high I 60 (the current where SS becomes 60 mV dec 1 2 Heterojunction (HJ) TFETs show promise for delivering a high I 60 but experimental results do not meet theoretical expectations due to interface problems in the HJs constructed from different materials. Here, we report a natural HJ TFET with spatially varying layer thickness in black phosphorus without interface problems. We have achieved record low average SS values over 4 5 dec of current (SS ave_4dec ~22.9 mV dec 1 and SS ave_5dec ~26.0 mV dec 1 with record high I 60 I 60 0.65 1 mA mm 1 paving the way for application in low power switches. Tunnel field effect transistors with spatially varying layer thickness in black phosphorus enable high performance with a record low subthreshold swing.
author_names: Seungho Kim

Gyuho Myeong

Wongil Shin

Hongsik Lim

Boram Kim

Taehyeok Jin

Sungjin Chang

Kenji Watanabe

Takashi Taniguchi

Sungjae Cho
title: Thickness controlled black phosphorus tunnel field effect transistor for low power switches
venue: Nature Nanotechnology
year: 2020

abstract: Conventional field effect transistors (FETs) have long been considered a fundamental electronic component for a diverse range of devices. However, nanoelectronic circuits based on FETs are not energy efficient because they require a large supply voltage for switching applications. To reduce the supply voltage in standard FETs, which is hampered by the 60 mV/decade limit established by the subthreshold swing (SS) a new class of FETs have been designed, tunnel FETs (TFETs) A TFET utilizes charge carrier transportation in device channels using quantum mechanical based band to band tunneling despite of conventional thermal injection. The TFETs fabricated with thin semiconducting film or nanowires can attain a 100 fold power drop compared to complementary metal oxide semiconductor (CMOS) transistors. As a result, the use of TFETs and CMOS technology together could ameliorate integrated circuits for low power devices. The discovery of two dimensional (2D) materials with a diverse range of electronic properties has also opened new gateways for condensed matter physics, nanotechnology, and material science, thus potentially improving TFET based devices in terms of device design and performance. In this review, state of art TFET devices exhibiting different semiconducting channels and geometries are comprehensively reviewed followed by a brief discussion of the challenges that remain for the development of high performance devices. Lastly, future prospects are presented for the improvement of device design and the working efficiency of TFETs.
author_names: Ghazanfar Nazir

Adeela Rehman

Soo-Jin Park
title: Energy efficient tunneling field effect transistors for low power device applications: challenges and opportunities.
venue: ACS applied materials interfaces
year: 2020

abstract: In order to decrease the threshold voltage while maintaining the OFF current low, reduction of the subthreshold swing is essential in field effect transistors(FETs) To reduce the subthreshold swing below 60 mV/decade, inter band tunneling can be used for injection of carriers and the device that utilizes such a mechanism is tunneling field effect transistor (TFET) Silicon(Si) TFETs, which are favored due to their compatibility with currently dominant complementary metal oxide semiconductor(CMOS) technology, suffer from low ON current because of the relatively large bandgap of Si. The ON current of Si TFETs can be increased by field and area enhancement in a cylindrical nanowire channel. Numerical analysis has confirmed that the cylindrical channel structure shows significantly higher tunneling rate and wider tunneling area than the double gate structure. Si TFETs with a hemicylindrical nanowire channel are fabricated and characterized, and the effectiveness of nanowire channel approach is demonstrated.
author_names: Byung-Gook Park

Min-Chul Sun

Sang Wan Kim
title: Silicon Tunneling Field Effect Transistors with a Hemicylindrical Nanowire Channel for Ultra Low Power Application
year: 2014

abstract: The present research letter is dedicated to a detailed analysis of a double gate tunnel field effect transistor (DG TFET) The DG TFET provides improved on current (ION) than a conventional TFET via bandto band (B2B) tunneling. However, DG TFET is disadvantageous for low power applications because of increased off current (IOFF) due to the large ambipolar current (Iamb) In this research work, a Si/GaAs/ GaAs heterostructure DG TFET is considered as research base for investigation of device performance. The electrical parameters of the DG TFET device have been improved in comparison to the homostructure. The transfer (I V) characteristics, capacitance voltage (C V) characteristic of homo structure Si/ Si/Si and hetero structure Si/GaAs/GaAs, DG TFET both structures is analysed comparatively. The C V characteristics of DG TFET have obtained using operating frequency of 1 MHz. The ambipolar current Iamb is suppressed by 5 x 108 order of magnitude in proposed Si/GaAs/GaAs hetero DG TFET as compared to Si/Si/Si homo DG TFET up to the applied drain voltage very low equal to VDS 0.5 V without affecting onstate performance. The simulation result shows a very good ION/IOFF ratio (10 13) and low subthreshold slope, SS ~36.52 mV/dec) The various electrical characteristics of homo and hetero DGTFET such as on current (ION) off current (IOFF) time delay (id) transconductance (gm) and power delay product (PDP) have been improve in Si/GaAs/GaAs heterostructure DG TFET and compared with Si/Si/ Si homo DG TFET. The advantageous results obtained for the proposed design show its usability in the field of digital and analog applications.
author_names: N Guenifi

Rahi Sb

Mohamed Amine Larbi
title: Suppression of Ambipolar Current and Analysis of RF Performance in Double Gate Tunneling Field Effect Transistors for Low Power Applications
year: 2020

abstract: Junctionless transistors (JLT) are a promising alternative to address the stringent junction requirements in conventional transistors. However, JLTs are plagued by high OFF state leakage current attributed to the band to band tunneling at the channel drain interface. This leakage current is often referred to as gate induced drain leakage (GIDL) In this paper, we propose an effective technique to suppress GIDL in JLTs. We use the charge plasma concept to realize an electrostatically doped drain (EDD) separated from the channel by an intermediate intrinsic region. Therefore, the proposed EDD JLT is an n+ n+ i n+ structure that widens the tunnel barrier at the gate drain interface in the OFF state (VGS 0 V, VDS 1 V) and offers significant reduction in leakage current. We compare, using 2D TCAD device simulations, the EDD JLT with the conventional JLT in terms of various digital and analog performance metrics. We observe that EDD JLTs of gate length 20 nm offer a significant reduction in IOFF 4 orders) while substantially improving ION/IOFF ratio 4 orders) as compared to conventional JLTs. To study the scalability of the proposed technique, the device thickness and gate length were scaled down to 5 nm. We observe that even for scaled down structure, EDD JLTs retain their performance benefit. We observe that the analog performance metrics such as intrinsic gain (GmRo) transconductance generation factor (Gm/ID) output conductance (GD) channel length modulation, and drain induced barrier lowering of EDD JLTs are also significantly improved as compared to conventional JLTs.
author_names: Mohd Adil Raushan

Naushad Alam

M J Siddiqui
title: Electrostatically doped drain junctionless transistor for low power applications
venue: Journal of Computational Electronics
year: 2019

abstract: In this work, we design and analyze complementary metal oxide semiconductor (CMOS) compatible III V compound electron hole bilayer (EHB) tunneling field effect transistors (TFETs) by using two dimensional (2D) technology computer aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias induced band to band tunneling (BTBT) across the electron hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p( p( n TFETs, which utilize BTBT across the source to channel junction. We applied III V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on state current (Ion) of 249.5 mA/mm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS 0.5 V. Based on the DC optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.
author_names: Sung Yoon Kim

Jae Hwa Seo

Young Jun Yoon

Ho-young Lee

Seong Min Lee

Seongjae Cho

In Man Kang
title: Design and Analysis of CMOS Compatible III V Compound Electron Hole Bilayer Tunneling Field Effect Transistor for Ultra Low Power Applications.
venue: Journal of nanoscience and nanotechnology
year: 2015

abstract: A novel vertical channel face tunneling field effect transistor (VC TFET) using Ge/SiGe material is proposed in this paper. The proposed device structure enhances the on state drive current without increasing the device footprint and also provides lower off state leakage current, steeper sub threshold slope and higher $I_{on}/I_{off} current ratio compared to the other TFETs. The design of SiGe material in the drain region suppresses the leakage current, and the channel region with small bandgap Ge enhances the tunneling current. Additionally, the complementary vertical channel TFET is also used to demonstrate the SRAM circuit performance for low power application. Novel SRAM topologies are proposed to eliminate the read disturb and enhance the RSNM/WSNM of SRAM.
author_names: Akancha Gupta

Chen Kuo Chiang

W Y Yang

E R Hsieh

S Chung
title: Design of Low Voltage Vertical Channel Face tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance
venue: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI TSA)
year: 2020

abstract: The two dimensional (2D) vertical van der Waals (vdW) stacked homojunction is an advantageous configuration for fast low power tunneling field effect transistors (TFETs) We simulate the device performance of the sub 10 nm vertical SnSe homojunction TFETs with ab initio quantum transport calculations. The vertically stacked device configuration has an effect of decreasing leakage current when compared with its planar counterpart due to the interrupted carrier transport path by the broken connection. A subthreshold swing over four decades (SSave_4 dec) of 44.2 45.8 mV dec 1 and a drain current at SS 60 mV dec 1 (I60) of 5 7 mA mm 1 are obtained for the optimal vertical SnSe homojunction TFET with Lg 10 nm at a supply voltage of 0.5 0.74 V. In terms of the device's main figures of merit (i.e. on state current, intrinsic delay time, and power delay product) the vertical SnSe TFETs and NCTFETs outperform the 2022 and 2028 targets of the International Technology Roadmap for Semiconductors requirements for low power application (2013 version) respectively.
author_names: Huanqiao Li

Jiakun Liang

Peipei Xu

Jingyao Luo

Fengbin Liu
title: Vertically stacked SnSe homojunctions and negative capacitance for fast low power tunneling transistors
year: 2020