Query: machine learning semiconductor resistance

Candidate papers:

abstract: Recently, the semiconductor counterfeiting has become a serious problem. To counter this problem, Physical Unclonable Function (PUF) has been attracted attention. However, the risk of machine learning attacks for PUF is pointed out. To verify the safety of PUF, the evaluation (tamper resistance) against machine learning attacks in the difference of PUF implementations is very important. However, the tamper resistance evaluation in the difference of PUF implementation has barely been reported. Therefore, this study evaluates the tamper resistance of PUF in the difference of field programmable gate array (FPGA) implementations against machine learning attacks. Experiments using an FPGA clarified the arbiter PUF of the lookup table implementation has the tamper resistance against machine learning attacks.
author_names: Yusuke Nozaki

Masaya Yoshikawa
title: Tamper resistance evaluation of PUF implementation against machine learning attack
venue: ICBEA '17
year: 2017

abstract: With growing process complexity and the increasing number of process steps, early prediction of device performance has become an important task in semiconductor manufacturing process control. Machine learning (ML) techniques allow us to link in line measurements to End Of Line (EOL) electrical tests. In our paper, we use reflectance spectra obtained from the scatterometry tool to predict both metal line resistance and capacitance. We used IMEC N14 process flow with LELE double patterning at the M1 stage. Special designs of experiments (DOE) for multiple parameters allowed us to create a metrology solution for the entire process window and test its accuracy for all POI. Induced variations of both line CDs and space CDs, together with specially designed measurement sites, created wide variations both in metal line resistance and capacitance. Reflectance spectra were collected in line at two process steps defining metal lines: HM etch and Cu CMP at multiple targets, including E test measurement sites, together with reference metrology for overlay (OV) and CD (by using Diffraction Based Overlay (DBO) and CD SEM) EOL electrical test results were used for the ML training procedure for early prediction of patterning effects (both CD and OL) on electrical performance enabling early decisions and cost reduction by discarding out of spec wafers before they reached the electrical test. It was shown that ML OCD predictive techniques are complimentary to the OCD model based solutions for geometrical parameters widely used for in line APC.
author_names: Sayantan Das

Joey Hung

Sandip Halder

Guillaume Schelcher

Roy Koret

Igor Turovets

Mohamed Saib

A L Charley

Matthew Sendelbach

Avron Ger

P Leray
title: Machine learning for predictive electrical performance using OCD
venue: Advanced Lithography
year: 2019

abstract: The physical unclonable functions (PUFs) have been attracted attention to prevent semiconductor counterfeits. However, the risk of machine learning attack for an arbiter PUF, which is one of the typical PUFs, has been reported. Therefore, an XOR arbiter PUF, which has a resistance against the machine learning attack, was proposed. However, in recent years, a new machine learning attack using power consumption during the operation of the PUF circuit was reported. Also, it is important that the detailed tamper resistance verification of the PUFs to consider the security of the PUFs in the future. Therefore, this study proposes a new machine learning attack using electromagnetic waveforms for the XOR arbiter PUF. Experiments by an actual device evaluate the validity of the proposed method and the security of the XOR arbiter PUF.
author_names: Yusuke Nozaki

Masaya Yoshikawa
title: EM based machine learning attack for XOR arbiter PUF
venue: ICMLSC '18
year: 2018

abstract: Interest in resistance switching is currently growing apace. The promise of novel high density, low power, high speed nonvolatile memory devices is appealing enough, but beyond that there are exciting future possibilities for applications in hardware acceleration for machine learning and artificial intelligence, and for neuromorphic computing. A very wide range of material systems exhibit resistance switching, a number of which primarily transition metal oxides are currently being investigated as complementary metal oxide semiconductor (CMOS) compatible technologies. Here, the case is made for silicon oxide, perhaps the most CMOS compatible dielectric, yet one that has had comparatively little attention as a resistance switching material. Herein, a taxonomy of switching mechanisms in silicon oxide is presented, and the current state of the art in modeling, understanding fundamental switching mechanisms, and exciting device applications is summarized. In conclusion, silicon oxide is an excellent choice for resistance switching technologies, offering a number of compelling advantages over competing material systems.
author_names: Adnan Mehonic

Alexander L Shluger

David Z Gao

Ilia Valov

Enrique A Miranda

Daniele Ielmini

Alessandro Bricalli

Elia Ambrosi

Can Li

J Joshua Yang

Qiangfei Xia

Anthony J Kenyon
title: Silicon Oxide (SiOx A Promising Material for Resistance Switching?
venue: Advanced materials
year: 2018

abstract: Power chips such as Metal Oxide Field Effect Transistors (MOSFETs) are widely used and can be found in many electronics and electrical products. The ability to predict the degradation of such power electronic devices can minimise the risk of their failure during operation and support maintenance planning operations. In this study, a data driven prognostics approach using system identification and machine learning modelling technique is developed and used to predict the time to failure of MOSFET TO 220 packages associated with delamination failure mode of the die attachment. Run to failure data under thermal overstress loading conditions for power chip devices, available from the NASA Prognostics Centre data repository, is used to develop a data driven prognostic model that can be used to predict the time to failure (TtF) of power MOSFETs under accelerated test loads. An increment in ON state resistance of the MOSFET is used as precursor for device failure through die attach degradation. Results from this research show that when monitored data from a damage indicator for a particular failure mode of an electronic package changes dynamically, data driven modelling using engineering control techniques such as State Space representation is capable of producing reliable, multi step ahead predictions for the time to failure of the device.
author_names: Mominul Ahsan

Stoyan Stoyanov

Chris Bailey
title: Data Driven Prognostics for Failure of Power Semiconductor Packages
venue: 2018 41st International Spring Seminar on Electronics Technology (ISSE)
year: 2018

abstract: Recently, semiconductor counterfeiting has become serious problems due to the advancement of reverse engineering technologies. The physical unclonable function (PUF) is now attracting attention as a technique to prevent counterfeiting. The PUF utilizes each device's analog characteristics, which are generated by variations on LSI manufacturing, as a measure for individual identification. However, the vulnerability of PUF to machine learning attacks has been pointed out. Therefore, it is important to examine the vulnerability of PUF from a view point of hardware security. This paper discusses the vulnerability of the proposed 4 MUXs PUF for attack using support vector machine (SVM) Experiments show superior resistance for SVM attacks in comparison with conventional PUF.
author_names: S Kiryu

Kensaku Asahi

Masaya Yoshikawa
title: Vulnerability evaluation of multiplexing PUF for SVM attacks
venue: ICSEng
year: 2014

abstract: As the micro electro mechanical machine (MEMS) industry is maturing, an increased array of product applications and devices are being introduced. As these devices are being developed new processes are required to control and attain the desired levels of polysilicon stress. In this work the relationship between polysilicon blanket residual stress and dopant concentration and anneal conditions are investigated. It was found that as the sheet resistance increased, the magnitude of the stress increased several orders of magnitude. Annealing the wafers for increased durations and multiple cycles lowered the level of stress observed while reducing the response to dopant concentration. The response was reduced by fifty percent for a time increase from 20 to 180 minutes. It is suggested that specific levels of stress are best attained with modifications to the dopant concentration for the required thermal cycles. The characterization performed allows for reduced learning cycles and cost in the development of new MEMS process flows to achieve first pass success for device specific requirements.
author_names: Jerzy Woloszyn
title: A method for controlling residual film stress in LPCVD polysilicon films for surface micromachined MEMS
venue: 2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530)
year: 2004

abstract: While spin qubits based on gate defined quantum dots have demonstrated very favorable properties for quantum computing, one remaining hurdle is the need to tune each of them into a good operating regime by adjusting the voltages applied to electrostatic gates. The automation of these tuning procedures is a necessary requirement for the operation of a quantum processor based on gate defined quantum dots, which is yet to be fully addressed. We present an algorithm for the automated fine tuning of quantum dots, and demonstrate its performance on a semiconductor singlet triplet qubit in GaAs. The algorithm employs a Kalman filter based on Bayesian statistics to estimate the gradients of the target parameters as function of gate voltages, thus learning the system response. The algorithm's design is focused on the reduction of the number of required measurements. We experimentally demonstrate the ability to change the operation regime of the qubit within 3 to 5 iterations, corresponding to 10 to 15 minutes of lab time.
author_names: Julian D Teske

Simon Sebastian Humpohl

Ren'e Otten

Patrick Bethke

Pascal Cerfontaine

Jonas Dedden

Arne Ludwig

Andreas Dirk Wieck

Hendrik Bluhm
title: A machine learning approach for automated fine tuning of semiconductor spin qubits
venue: Applied Physics Letters
year: 2019

abstract: Semiconductor manufacturers aim to fabricate defect free wafers in order to improve product quality, increase yields, and reduce costs. Typically, wafer defects form spatial patterns that provide useful information, helping to identify problems and faults during the fabrication process. Machine learning (ML) methods have been used to classify these defects in order to locate the root causes of failure. This paper proposes a novel deep structured ML approach as an extension of our previous randomized general regression network (RGRN) model, to identify and classify both single defect and mixed defect patterns. The principal motivation for this paper is that a shallow structured RGRN performs well on single pattern defects, achieving an accuracy of 99.8% but performs poorly when a wafer has mixed defect patterns. The proposed approach improves RGRN performance, particularly on mixed pattern defects, by incorporating a novel information gain (IG) based splitter as well as deep structured ML. A spatial filter is applied to remove random noise and reduce model bias during training. During the first detection stage, the splitter generates unique rules that are built using the IG theory and splits the defects data into single defect and mixed defect patterns. Single defect patterns are then classified by RGRN, whereas mixed defect patterns are fed into the deep structured ML model for further classification. This combination improves the ability of the proposed approach to classify diverse defect patterns and achieve a better overall performance. Our experimental results demonstrate that the proposed approach achieves an overall detection accuracy of 86.17% on a dataset that contains real data representing both single defect and mixed defect patterns, as commonly found in real manufacturing scenarios, outperforming existing ML based models.
author_names: Ghalia Tello

Omar Y Al-Jarrah

Paul Yoo

Yousof Al-Hammadi

Sami Hakam Muhaidat

Uihyoung Lee
title: Deep Structured Machine Learning Model for the Recognition of Mixed Defect Patterns in Semiconductor Fabrication Processes
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2018

abstract: Semiconductor cluster equipment adds an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric vacuum atmospheric cycle. Such highly automated tools present a complex scheduling challenge where process specific requirements are balanced against a need to achieve maximum wafer throughput in a fault tolerant manner. Software engineers typically build schedulers using a set of manually configured heuristics but this can be a labor intensive process where small changes to the cluster configuration or process requirements can require large changes to the scheduler. Our motivation for this work was to investigate whether a machine learning approach to complex cluster scheduling could be developed more efficiently and at a lower cost than existing methods.
author_names: Doug Suerich

Terry Young
title: Machine Learning for Optimized Scheduling in Complex Semiconductor Equipment
venue: 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
year: 2019