Query: Subthreshold CMOS voltage reference circuit with body bias compensation for process variation

Candidate papers:

abstract: This study presents a subthreshold complementary metal oxide semiconductor (CMOS) voltage reference circuit that adopts dynamical body bias to compensate the process related reference voltage fluctuation. The proposed circuit generates a mean reference voltage of 0.781 V at 1.2 V supply and 27degC, reduces the standard deviation (s) of the reference voltage from 11 mV to only 3 mV, and meanwhile improves the power supply rejection ratio from 30.7 to 51.4 dB. The average temperature coefficient measured from 0 to 100degC is 48 ppm/degC, and the line regulation is 0.34%/V in a supply voltage ranging from 1.2 to 2.3 V. The maximum supply current is 8.1 mA at 1.2 V supply and 100degC, and the chip area is 0.0533 mm 2 in 0.13 mm CMOS technology.
author_names: Hao Luo

Yan Han

Ray C C Cheung

Guojin Liang

Dazhong Zhu
title: Subthreshold CMOS voltage reference circuit with body bias compensation for process variation
venue: IET Circuits Devices Syst.
year: 2012

abstract: This paper proposes a voltage reference operating up to 170 degC for low power high temperature systems. The proposed circuit buffers body voltages to avoid degradation of temperature coefficient from nwell/psub diode leakage. For low power overhead, it measures the diode leakage and adaptively adjusts the bias current of the buffers. This enables low power consumption at low temperature, which can allow an energy harvester to recharge a battery in the target system. Prototype chips, fabricated in a 180 nm CMOS process, show a 3s inaccuracy of 3.4% from 0 degC to 170 degC after single trim at 80 degC and a line sensitivity of 0.088 /V from 1.8 V to 3.6 V. It consumes 76.3 pA at room temperature and 177 nA at 170 degC from 1.8 V.
author_names: Inhee Lee

Dennis Sylvester

David Blaauw
title: Subthreshold voltage reference with nwell/psub diode leakage compensation for low power high temperature systems
venue: 2017 IEEE Asian Solid State Circuits Conference (A SSCC)
year: 2017

abstract: In this paper, a low noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 mW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.
author_names: Sajad Nejadhasan

Fatemeh Zaheri

Ebrahim Abiri

Mohammad Reza Salehi
title: PVT compensated low voltage and low power CMOS LNA for IoT applications
year: 2020

abstract: This paper presents an external capacitor less low dropout(LDO) regulator with a voltage spike detection circuit for the enhanced transition response and with a CMOS only sub bandgap voltage reference(BGR) operated in subthreshold region. CMOS sub BGR adopted a weighted Vgs structure and a body bias technique for reducing the variations from process, voltage and temperature (PVT) The proposed LDO achieved the PSRR of 96dB at DC and 34dB at 1MHz by using 3 stage configuration. The proposed LDO operates with the reference voltage of 283mV from the Sub BGR and provides the output voltage of 1.5V. Simulated results shows that overshoot and undershoot of output voltage were reduced to 62mV and 56mV respectively when the load current changes from 0 to 50mA. Total power consumption was 60mA and the chip area was 0.03358mm2 with 0.18mm CMOS process.
author_names: Chang-Bum Park

Changmin Jung

Shin-Il Lim
title: A transient enhanced external capacitor less LDO with a CMOS only sub bandgap voltage reference
venue: 2016 International SoC Design Conference (ISOCC)
year: 2016

abstract: Process and temperature variations have become a serious concern for ultra low voltage (ULV) technology. The clock generator is the essential component for the ULV very large scale integration (VLSI) MOSFETs is operated in the sub threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators has been studied. A multi phase crystal less clock generator (MPCLCG) with a process voltagetemperature (PVT) calibration circuit is proposed in Chapter 3. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18 m CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65m x75m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degC from 0 to 100degC, and 2 point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58 ps RMS jitter and a 34.55IV ps peak to peak jitter (P2P jitter) at 192 MHz within 12.67k hits. At 192 MHz, it shows a 1 MHz offset phase noise of 102dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3% respectively. Being operated with 0.5V supply voltage in a standard 65nm CMOS process, a new CMOS temperature compensated crystal less clock generator. The bias current provided by the bandgap reference circuit and low dropout operate amplifier are nearly independent of temperature due to the existence of mutual compensation of mobility and threshold voltage variation. The new proposed temperature compensated crystalless clock generator functions well by the analog linear compensation mechanism. Chapter 4 presents an ultra low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance. We also discuss the time to digital converter system for time measurement unit in chapter 5. The Appendix A shows the electron distribution in an amorphous indium gallium zinc oxide (a IGZO) thin film transistor (TFT) with a floating metal semiconductor (MS) back interface is analyzed using a technology computer aided design (TCAD) model. The channel geometry (i.e. length and thickness) effect is carefully investigated. At a high work function (i.e. 5 eV) of the capping metal, the capping metal (electron depletion effect) mostly removes electrons inside a IGZO. The depletion of the IGZO film leads to an increase in threshold voltage in a IGZO TFT. TCAD simulation reveals that increasing channel length and decreasing IGZO thickness significantly enhance such an electron depletion effect. Finally, the electron depletion effect is applied to aIGZO TFT with a high conductivity IGZO film to greatly suppress the leakage current by over 5 orders. The Appendix B shows a voltage reference circuits on poly Silicon TFT. Because this paper is based on author's master thesis, detailed contents could refer the author's master thesis.
author_names: Ting-Chou Lu

Ming-Dou Ker

Hsiao-Wen Zan
title: DESIGN AND IMPLEMENTATION OF CRYSTAL LESS CLOCK GENERATOR WITH PROCESS VOLTAGE TEMPERATURE COMPENSATION
year: 2017

abstract: We present an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using "canary flip flop (FF)" which can predict timing errors. A 32 bit Kogge Stone adder whose performance was controlled by body biasing was fabricated in a 65 nm CMOS process. Measurement results show that the adaptive control can compensate process, supply voltage, and temperature variations and improve the energy efficiency of subthreshold circuits by up to 46% compared to worst case design and operation with guardbanding. We also discuss how to determine design parameters, such as the inserted location and the buffer delay of the canary FF, supposing two approaches: configuration in the design phase and post silicon tuning.
author_names: Hiroshi Fuketa

Masanori Hashimoto

Yukio Mitsuyama

Takao Onoye
title: Adaptive Performance Compensation With In Situ Timing Error Predictive Sensors for Subthreshold Circuits
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2012

abstract: Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub 45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT) smaller VDD/VT ratio, high leakage current, and large Process Variation (PV) In the first chapter, we study ITRS semiconductor roadmap, state of the art lithography techniques, and sub 65nm bulk CMOS manufacturing technologies. Then, we discuss the necessity of low power IC design. We talk about short channel MOSFET modeling and we review the advantages and limitations of the future CMOS candidates, FD SOI and FinFET. In chapter two, we study physical origins of the leakage current and we show why subthreshold leakage is usually the dominant leakage component in an optimized technology. Then, we discuss benefits and disadvantages of available leakage reduction techniques. We also show that high fan in gates could be very energy efficient in sub VT regime. In the third chapter, we study the physical origins of the variability. We study random dopant fluctuation, line edge roughness, random telegraph noise, metal work function variation, and other origins of the statistical variability. In chapter four, first we review conventional post silicon variability compensation techniques, i.e. Adaptive Body Biasing (ABB) and Adaptive Supply Voltage (ASV) We discuss their limitations in the deca nanometer regime. We see that in the planar transistor, body effect is diminishing with scaling; and in the emerging multi gate transistors, body factor is almost zero. Then, we talk about reliability issues and see that increasing the VDD over the nominal voltage, reduces the IC lifetime exponentially. This imposes a major limitation on the ASV technique. We propose Adaptive Vgs Multiplexer (AVGS Mux) technique for FPGA fabric design in chapter five. Proposed method controls the transistor current by the source voltage. It can provide 1.6X control on the delay and 7X exponential control on the sub threshold and gate leakages in the switch box, LUT, and interconnects at the same time. In TT corner, performance, leakage, and dynamic power overheads are almost zero. AVGS Mux is a good replacement of ABB and ASV techniques in emerging manufacturing technologies which have very small body effect and cannot tolerate voltages higher than nominal VDD due to the reliability issues. We designed a full custom mixed signal circuit in 90nm CMOS technology to verify the idea. The measurement results match very well with simulation. In the last chapter, we show that in the logic circuits working at sub nominal VDD, proper selection of the logic architecture and VDD together, can reduce the impact of the intra die and inter die variability on the timing significantly. First we show that s/u ratio of the transistor current and delay strongly depends on the VDD. Then, we compare the PV sensitivity of Low Power Slow (LP S) architectures with High Power Fast (HP F) ones. The results show that for a given technology, equal power budget, and equal delay, LP S circuits working at a higher VDD are less PV sensitive compared with HP F circuits working at a lower VDD. Our method is particularly useful for combating intra die random variability. We designed a full custom mixed signal circuit in 90nm CMOS technology to verify the proposed method. The measurement results show that the proposed method is actually more effective than what we see in simulation.
author_names: Bahman Kheradmand Boroujeni
title: Process Variation and Leakage Power
year: 2011

abstract: This work presents a 0.7 V Subthreshold Symmetrical Low Noise Amplifier (SSLNA) of 16 channel electroencephalogram analog front end. The SSLNA features a low supply voltage of 0.7 V, a low power dissipation of 214 nW, a direct current gain of about 38 dB and a bandwidth of from 0.25 Hz to 480 Hz. On the aspect of the noise, the input referred noise is 2.23 mVrms and the noise efficiency factor is 4.85. All the transistors of this SSLNA operate in the subthreshold region. The SSLNA is designed and verified in a 0.13 mm CMOS process. DOI: 10.29011/BBOA 109. 100009 Introduction Recordings of the neural Electroencephalogram (EEG) signals from many locations of the brain are an important source of the information for studying the function of the brain and various neurological disorders [1,2] Therefore, multichannel Electroencephalogram (EEG) seizure detection SoCs are widely adopted in medical practice and in research [3,4] but most of them have an obvious limitation limited number (no more than 8) of channels, whereas the American Clinical Neurophysiology Association sets the minimum technical standard recommendation for pediatric EEG as16 channels with bipolar and referential montages [4] These recordings occupy a frequency band of from 1 Hz to about 40 Hz and have the small amplitudes ranging from 0.5 mVp to 100 mVp [5] Due to the small amplitudes, EEG signals need to be amplified before digitization. Thus, the Low Noise Amplifiers (LNA) are needed in an EEG signal recording sensor. Usually, the input referred noise of the LNAs should be less than 4 mVrms [6] EEG monitoring is one application where designers have targeted microvolt even sub microvolt input referred noise over a designed signal band [5] For low bandwidth and low noise applications, the front end amplifier of the recording sensor presents a powerconsumption bottleneck since its current draw is noise limited and cannot be scaled with the low data rate [7] Therefore, the prior works to improve the energy efficiency of LNAs includes chopper [8] inverter based LNAs [7] and low supply voltage amplifier design reaching 1.2 V [1,6] However, most of LNAs still struggles on the aspect of energy efficiency and power consumption. Therefore, to further improve the energy efficiency, this paper uses a low supply of 0.7 V to design a 16 channel EEG analog front end. Our Subthreshold Symmetrical LNA (SSLNA) decreases the power dissipation and maintains the other aspects comparable, via scaling the supply voltage to 0.7 V and keeping all the transistors operate in the subthreshold region. This paper is organized as follows. The topologies and analysis of the whole analog front end, the proposed SSLNA and the other circuits are presented in Section II. The results are stated in Section III. Finally, the conclusions are given in Section IV. Topology Analog Front End Topology The whole analog front end topology is shown in Figure 1. It consists of the proposed sampling and processing amplifiers for 16 channels, a 16:1 multiplexer, an 8 bit modified flash ADC, a CMOS reference and a clock tree. The EEG signals are filtered by High Pass Filters (HPF) and then processed by proposed SSLNAs. Then, the corresponding channel is chosen by one multiplexer to transfer one SSLNA output to a modified flash ADC. Then the Citation: Wang C, Morizio J (2018) A 0.7V Supply, 214nW Power, 2.23mVrms Noise Subthreshold Symmetrical Low Noise Amplifier for 16 Channel Analog Front End. Biosens Bioelectron Open Acc: BBOA 109. DOI: 10.29011/BBOA 109. 100009 2 Volume 2018; Issue 01 flash ADC converts the analog signal to digital signals. Moreover, the CMOS reference provides the bias current and voltage. Figure 1: Analog front end topology. Proposed Subthreshold Symmetrical LNA As shown in Figure 2a each channel has one HPF and one closed loop SSLNA. It's easy to obtain the transfer function of HPF and the gain of closed loop SSLNA as the followings where is the filter resistor, is the filter capacitor, and and are the gain resistors. Noting that, the high pass frequency and closed loop gain should respectively be around 0.3 Hz and around 40 dB for EEG signals. Figure 2b shows the SSLNA. The SSLNA is based on a common symmetrical OTA but works at a low supply of 0.7V. It consists of one differential pairs implemented by the transistors M1 and M2, three pairs of current mirrors M3 M5, M4 M6 and M7 M8, a bias current M9, as well as the miller compensation C1 and R1 keeping the SSLNA stable. Figures 2(a,b) Closed loop SSLNA, (b) subthreshold symmetrical LNA. Due to the transistors working in the subthreshold region, the drain current of the transistors should be Citation: Wang C, Morizio J (2018) A 0.7V Supply, 214nW Power, 2.23mVrms Noise Subthreshold Symmetrical Low Noise Amplifier for 16 Channel Analog Front End. Biosens Bioelectron Open Acc: BBOA 109. DOI: 10.29011/BBOA 109. 100009 3 Volume 2018; Issue 01 where and are the basic drain current, channel width, channel length, gate source voltage and drainsource voltage, electron charge, the ration of the sum of oxide and depletion capacitances to oxide capacitance, Boltzmann constant and temperature, respectively. and can be expressed as where and are the oxide capacitance per unit area, depletion capacitance, carrier mobility and the threshold voltage, respectively. According to the OTA principle, the gain and bandwidth can be easily written as where is the capacitance of node OUT, is the equivalent resistance of M8 (M6) and is the transconductor of M1 or M2. The transconductor and the equivalent resistance can be calculated as Therefore, via substituting and into and bandwidth it's easy to find the following Noting that, the target of the bandwidth i.e. a low pass frequency is around 500 Hz for EEG signal. Due to all the transistors operating in the subthreshold region reduce the ultra low power, and hence the root mean square (rms) voltage of the input mosfet at the frequency band of from to is express as [9] where is the crossover frequency which can be written as where is the slope factor slightly dependent on the gate voltage, is the thermal voltage, is the density of oxide traps per unit volume and unit energy and is the attenuation coefficient of the electron wave function in the oxide. For and is of the order of Each transistor in the SSLNA introduces the approximate amount of noise versus their area, and the same number of effective traps for both nMOS and pMOS transistors is assumed [9] Consequently, neglecting the common mode noise of the current source, the input referred noise can be estimated by simply timing the ratio of total and input mosfet areas with the rms voltage of input mosfet [9] as Therefore, via substituting into it's easy to find the following Noting that, for EEG signals the input referred noise should be no more than 2.5 mVrms. Furthermore, the noise efficiency factor can be defined [10] as where is the total drain current in the SSLNA. So, tuning the appropriate widths and lengths of the transistors in the proposed SSLNA can achieve the aforesaid targets. The chosen parameters of the transistors are shown in Figure 2b. Flash ADC A bit modified Flash ADC is achieved combining Threshold Inverter Quantization (TIQ) and multiplexer based decoder. TIQ based on a single NMOS comparator (consisting of a resistor and CMOS inverters) is transplanted to overcome the drawbacks of traditional comparator and TIQ based on two cascaded CMOS inverters. Traditional comparator requires a Citation: Wang C, Morizio J (2018) A 0.7V Supply, 214nW Power, 2.23mVrms Noise Subthreshold Symmetrical Low Noise Amplifier for 16 Channel Analog Front End. Biosens Bioelectron Open Acc: BBOA 109. DOI: 10.29011/BBOA 109. 100009 4 Volume 2018; Issue 01 large number of transistors causing the big chip area and power consumption. TIQ based on two cascaded CMOS inverters requires its ratios being increased up to maybe thousand times when the number of bits is increased. The chosen TIQ based on a single NMOS comparator is shown in Figure 3a [10] The resistor is used to set the voltage between source and bulk the first inverter is used to compare the input and threshold voltage and the second inverter is used to amend the comparison result. of NMOS can be expressed as where is threshold voltage when source and bulk is connected, is body effect parameter, is semiconductor parameter. So can be biased and adjusted by the series resistors to attain reference voltage. The NMOS operating mechanism depended on the relationship of and If NMOS is at the "cutoff" region, there is no current flowing through NMOS and it will output a negative logic "0" Otherwise, NMOS is at the "ON" region (whether in non saturation or saturation) and it will output a positive logic "1" Obviously, ratio of NMOS transistor need be chosen to make a good trade off between input range and area, thus we use Multiplexer based decoder is used to overcome the disadvantages of ROM, Wallace tree and folded decoders. ROM decoder is slow and power consuming. Wallace tree decoder and folded decoder require a larger length of critical path which is approximately third and twice of multiplexer based decoder, respectively. The used multiplexer based decoder is shown in Figure 3b. For an bit flash ADC, the Most Significant Bit of the binary outputs is high if more than half of the outputs in the thermometer scale are logic one. Hence is To find the second most significant bit of the original thermometer scale is divided into two partial thermometer scales, separated by The partial thermometer scale to decode is chosen by a set of 2:1 multiplexers, where the previous decoded binary outputs are connected to the control input of the multiplexers. is then found from the chosen partial thermometer scale in the same way as was found from the full thermometer scale. Similarly, all the bits can be obtained. In general, the dec
author_names: Chuan Jian Wang

James C Morizio
title: A 0.7V Supply, 214nW Power, 2.23mVrms Noise Subthreshold Sym metrical Low Noise Amplifier for 16 Channel Analog Front End
year: 2018

abstract: Behavior of adiabatic logic circuits in weak inversion or sub threshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow power circuit design. This novel approach is efficacious in low speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4 bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on sub threshold adiabatic logic based 4 bit CLA has also been addressed separately. Post layout simulations show that sub threshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Introduction The demand for implementing ultralowpower digital systems in many modern applications, such as mobile systems, sensor networks, and implanted biomedical systems, has increased the importance of designing logic circuits in sub threshold regime. These emerging applications have low energy as the primary concern instead of performance, with the eventual goal of harvesting energy from the environment. In sub threshold logic circuits operate with a supply voltage VDD lower than the transistor threshold voltage VT and utilize the sub threshold leakage current as the operating current. Conventional CMOS logic circuits utilizing sub threshold transistors can typically operate with a very low power consumption, which is mainly due to the dynamic (switching) power consumption and is quadratically dependent upon the supply voltage as CL f V2 DD (where CL, f, and VDD are the load capacitance, operating frequency, and the supply voltage, respectively).Recently, adiabatic logic (or energy recovery logic) style has emerged as a promising approach in strong inversion regime, to reduce dynamic power consumption significantly without sacrificing noise immunity and driving ability. These circuits achieve ultralow energy consumption by steering currents across devices with low voltage differences and by gradually recycling the energy stored in their International Journal On Engineering Technology and Sciences IJETSTM ISSN(P) 2349 3968, ISSN (O) 2349 3976 Volume III, Issue XII, December2016 55 capacitive loads, especially in low frequency regime. Since the performance requirements are quite relaxed in many of these energy efficient subs threshold applications we believe that the adiabatic style can be used efficaciously in a sub threshold regime to make the circuit more energy efficient. To the best of our knowledge, no paper emphasizes the application of adiabatic logic in weak inversion regime for advanced technology node such as 22 nm. Therefore, the attempt to realize the sub threshold adiabatic logic (SAL) concept is a new endeavor. In general, the design of SAL requires a deep knowledge of the main features of the adopted logic style, such as power dissipation, leakage current, and impact of temperature variation, operating frequency, and noise immunity. In this paper, the behaviors of adiabatic logic in sub threshold regime are discussed in depth. To demonstrate the workability of the adiabatic logic circuits in sub threshold regime, a 4 bit carry look ahead adder (CLA) unit is adopted as a reference circuit. Analysis of energy dissipation along with the sensitivity of energy dissipation on supply voltage and temperature variations is also discussed in depth. Moreover, the analytical expression of optimum frequency and supply voltage under minimum energy condition has been verified through simulation in 22 nm technology. Extensive experiments are carried out using CADENCE SPICE Spectra to ensure the high energy efficiency and design feasibility of the proposed logic in weak inversion regime compared with other conventional CMOS logic. 2. Existing System: A CMOS transistor (or device) has four terminals: gate, source, drain, and a fourth terminal that we shall ignore until the next section. A CMOS transistor is a switch. The switch must be conducting or on to allow current to flow between the source and drain terminals (using open and closed for switches is confusing for the same reason we say a tap is on and not that it is closed) The transistor source and drain terminals are equivalent as far as digital signals are concernedwe do not worry about labeling an electrical switch with two terminals 2.1 Existing Technique: Normal CMOS Logic 2.2 Technique explanation: If Vin is down (0 volts) NFET is OFF and PFET is ON pulling Vout to Vdd (high 1) If Vin is up (at Vdd) NFET is ON hard and PFET is OFF pulling Vout low to Gnd "0" 3. Proposed System: In adiabatic logic circuits, ramp type supply voltage is used to slow down the charge transport mechanism. Hence, the supply clock plays the pivotal role. A ramp type supply voltage ph(t) is considered in Fig. 1(a) which gradually swings in International Journal On Engineering Technology and Sciences IJETSTM ISSN(P) 2349 3968, ISSN (O) 2349 3976 Volume III, Issue XII, December2016 56 between logic 0 (Gnd potential) and logic 1 (VDD) in time duration 2T, where f =1/2T is the supply clock's frequency. The power supply waveform ph(t) can be divided into charging phase, when ph(t) ramps up from 0 to VDD in 0 to T unit time and discharging phase when ph(t) ramps down from VDD to 0 in T to 2T unit time. 3.1 Proposed Technique: SAL Adiabatic Logic 3.2 Technique explanation: The design as in SAL basic logic gates have been implemented using either the pull up or the pull down transistors. Therefore, the SAL based CLA is also area efficient in comparison with the conventional structure. 4. Literature survey: 1) A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression Further power and energy reductions via technology and voltage scaling have become extremely difficult due to leakage and variability issues. In this paper, we present a robust and energy efficient computation architecture exploiting an asynchronous timing strategy to dynamically minimize leakage and to self adapt to process variations and different operating conditions. Based on a logic topology with built in leakage suppression, the prototype asynchronous neural signal processor demonstrates robust subthreshold operation down to 0.25 V, while consuming only 460 nW in 0.03 in a 65 nm CMOS technology. These results represent a 4.4 reduction in power, a 3.7 in energy and a 2.2 reduction in power density, when compared to the state of theart processors. As the supply voltage is scaled near or below the device threshold, dramatic increases in leakage and variability severely limit digital processor performances. In this paper, we present robust and energy efficient computation architecture by employing an asynchronous selftimed design methodology. The proposed strategy allows for an adaptive adjustment to latency variations, and supports for an inherent leakage minimization under process variations and changing operating conditions, all of which are major issues in scaling regimes that favor major reduction in supply voltages. Circuit techniques specifically for leakage minimization are aggressively employed at both the logic and system levels. The prototype asynchronous neural signal processor demonstrates robust operation down to 0.25 V while consuming only 460 nW. Compared to the traditional synchronous approach, the asynchronous design shows a 2.3 reduction in power. Moreover, the self timed operation alleviates the impact of variations on processor performance. Therefore, the asynchronous design International Journal On Engineering Technology and Sciences IJETSTM ISSN(P) 2349 3968, ISSN (O) 2349 3976 Volume III, Issue XII, December2016 57 exhibits a better statistical characteristic of power performance than the synchronous counterpart. These results demonstrate that in addition to soliciting better transistors and fabrication technology, leakage and variability issues can be tackled at the circuit and system levels with novel timing schemes and circuit innovations. 2) Design Techniques and Architectures for Low Leakage SRAMs In high performance Systems on Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for memory devices, for two main reasons. First, memories have historically been designed with performance as the primary figure of merit; therefore, they are intrinsically non power efficient structures. Second, memories are accessed in small chunks, thus leaving the vast majority of the memory cells unaccessed for a large fraction of the time. In this paper, we present an overview of the techniques proposed both in the academic and in the industrial domain for minimizing leakage power, and in particular, the sub threshold component, in SRAMs. The surveyed solutions range from celllevel techniques to architectural solutions suitable to system level design. We can observe a couple of facts that allow a few suggestions that can have general value. a) Exploit Orthogonality of Strategies: Although some techniques (e.g. bitline and word line design) have a moderate impact in absolute terms, they are orthogonal to techniques that are based on DPM. The same consideration applies to the customized design of the bitcell. Therefore, whenever the re design of the internals of the SRAM architecture is allowed, designer should try to apply such techniques to decrease the leakage cost of basic memory operations (bitline/word line access and reads/writes) b) Technology Matching: Although many techniques do not scale nicely with technology and/or scaling, designers should try to match the various techniques with the target technology. A technique may become less relevant in future technologies but might be the most suitable for the current ones. A good example is body biasing. Although it is expected
author_names: M Priyanka

P Chandrasekar
title: IMPLEMENTATION OF SUBTHRESHOLD ADIABATIC LOGIC FOR ULTRA LOW POWER APPLICATION
year: 2017

abstract: Building functional thin film transistor (TFT) circuits is crucial for applications such as wearable, implantable and transparent electronics. Therefore, developing a compact model of an emerging semiconductor material for accurate circuit simulation is the most fundamental requirement for circuit design. Further, unique analogue building blocks are needed due to the specific properties and non idealities of TFTs. This dissertation reviews the major developments in thin film transistor (TFT) modelling for the computer aided design (CAD) and simulation of circuits and systems. Following the progress in recent years on oxide TFTs, we have successfully developed a Verilog AMS model called the CAMCAS model, which supports computer aided circuit simulation of oxide TFTs, with the potential to be extended to other types of TFT technology families. For analogue applications, an accurate small signal model for thin film transistors (TFTs) is presented taking into account non idealities such as contact resistance, parasitic capacitance, and threshold voltage shift to exhibit higher accuracy in comparison with the adapted CMOS model. The model is used to extract the zeros and poles of the frequency response in analogue circuits. In particular, we consider the importance of device circuit interactions (DCI) when designing thin film transistor circuits and systems and subsequently examine temperatureand process induced variations and propose a way to evaluate the maximum achievable intrinsic performance of the TFT. This is aimed at determining when DCI becomes crucial for a specific application. Compensation methods are reviewed to show examples of how DCI is considered in the design of AMOLED displays. Based on these design considerations, analogue building blocks including voltage and current references and differential amplifier stages have been designed to expand the analogue library specifically for TFT circuit design. The VT shift problem has been compensated based on unique circuit structures. For a future generation of application, where ultra low power consumption is a critical requirement, we investigate the TFT's subthreshold operation through examining several figures of merit including intrinsic gain (Ai) transconductance efficiency (gm/IDS) and cut off frequency fT Here, we consider design sensitivity for biasing circuitry and the impact of device variations on low power circuit behaviour.
author_names: Xiang Cheng
title: TFTs circuit simulation models and analogue building block designs
year: 2018