Query: Operation and Modeling of the MOS Transistor

Candidate papers:

abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO TERMINAL MOS STRUCTURE 3. THE THREE TERMINAL MOS STRUCTURE 4. THE FOUR TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION IMPLANTED CHANNELS 6. SMALL DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION LARGE SIGNAL MODELING 8. SMALL SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH FREQUENCY SMALL SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION
author_names: Yannis P Tsividis
title: Operation and modeling of the MOS transistor
year: 1987

author_names: Yannis P Tsividis
title: Operation and Modeling of the Mos Transistor (The Oxford Series in Electrical and Computer Engineering)
year: 2004

abstract: A unified modeling approach for the submicron MOS transistor charge/capacitance characteristics in all operation regions is presented. The development of the MOS charge model is based on the charge density approximation to reduce the complexity of the expression. The unified charge densities in gate, channel, and bulk are obtained with assistance of the sigmoid, hyperbola, and exponential interpolation techniques. By carrying out the integration of the charge densities along the channel area, the terminal charges associated with gate and bulk can be obtained. The non reciprocal capacitance behavior is well realized in this model. Good agreement between the measurement data and simulation results is obtained.
author_names: Steve H Jen

Bing J Sheu

A Yoondong Park
title: An efficient MOS transistor charge/capacitance model with continuous expressions for VLSI
venue: ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
year: 1998

abstract: An accurate and computationally efficient charge based model for the intrinsic capacitances in MOS transistors is proposed. The model is valid in the subthreshold regime and is based on the quasi static approximation. By integrating this model with a corresponding one in the strong inversion regime, a complete model valid in all regions of operation is presented. An interpolation scheme which guarantees the continuity of the drain current and the capacitances as well as their derivatives is used to provide a smooth transition from subthreshold to strong inversion. The theoretical predictions of the model are compared to the numerically simulated data extracted from MINIMOS 4.0 and are found to be in good agreement over a wide range of voltages.<ETX>
author_names: A Kushaa

M A El Nokali
title: A CAD model for MOS transistors valid in all regions of operation
venue: [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems
year: 1991

abstract: We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human machine interface applications in neural prostheses and implantable bioelectronics, as well as large scale neural emulation tools for computational neuroscience.
author_names: Venkat Rangan

Abhishek Ghosh

Vladimir Aparin

Gert Cauwenberghs
title: A subthreshold aVLSI implementation of the Izhikevich simple neuron model
venue: 2010 Annual International Conference of the IEEE Engineering in Medicine and Biology
year: 2010

abstract: BACKGROUND Death within 90 days after total hip replacement is rare but might be avoidable dependent on patient and treatment factors. We assessed whether a secular decrease in death caused by hip replacement has occurred in England and Wales and whether modifiable perioperative factors exist that could reduce deaths. METHODS We took data about hip replacements done in England and Wales between April, 2003, and December, 2011, from the National Joint Registry for England and Wales. Patient identifiers were used to link these data to the national mortality database and the Hospital Episode Statistics database to obtain details of death, sociodemographics, and comorbidity. We assessed mortality within 90 days of operation by Kaplan Meier analysis and assessed the role of patient and treatment factors by Cox proportional hazards model. FINDINGS 409,096 primary hip replacements were done to treat osteoarthritis. 1743 patients died within 90 days of surgery during 8 years, with a substantial secular decrease in mortality, from 0*56% in 2003 to 0*29% in 2011, even after adjustment for age, sex, and comorbidity. Several modifiable clinical factors were associated with decreased mortality according to an adjusted model: posterior surgical approach (hazard ratio [HR] 0*82, 95% CI 0*73 0*92; p=0*001) mechanical thromboprophylaxis (0*85, 0*74 0*99; p=0*036) chemical thromboprophylaxis with heparin with or without aspirin (0*79, 0*66 0*93; p=0*005) and spinal versus general anaesthetic (0*85, 0*74 0*97; p=0*019) Type of prosthesis was unrelated to mortality. Being overweight was associated with lower mortality (0*76, 0*62 0*92; p=0*006) INTERPRETATION Postoperative mortality after hip joint replacement has fallen substantially. Widespread adoption of four simple clinical management strategies (posterior surgical approach, mechanical and chemical prophylaxis, and spinal anaesthesia) could, if causally related, reduce mortality further. FUNDING National Joint Registry for England and Wales.
author_names: Linda P Hunt

Yoav Ben-Shlomo

Emma M Clark

P A Dieppe

Andrew Judge

Alexander J Macgregor

Jonathan H Tobias

Kelly Vernon

Ashley W Blom
title: 90 day mortality after 409 096 total hip replacements for osteoarthritis, from the National Joint Registry for England and Wales: a retrospective analysis
venue: The Lancet
year: 2013

abstract: Qucs and QucsStudio open source circuit simulators have a wealth of built in swept data features, including facilities for linear and logarithmic scans of simulation variables and for setting component values and device parameters. These simulators also allow semicolon separated lists of numerical values to be used as swept data. This little known feature provides a very flexible mechanism for generating component and device parameter statistical data. An outline of a statistical circuit simulation technique is presented in this paper. The proposed technique can be used with any general purpose circuit simulator equipped with swept data capabilities and as such is suitable for the study of device and circuit performance resulting from variations in device parameters and component values. The operation of the proposed simulation technique is illustrated with the results from an investigation of the statistical performance of a simple MOS current mirror integrated circuit cell, modeled with a speed optimized Verilog A version of a long channel EPFL EKV v2.6 MOS transistor model.
author_names: Mike Brinson
title: A swept parameter technique for statistical circuit simulation
venue: Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2013
year: 2013

abstract: Design, operation and measurement results of a CMOS camera implemented within a SOI wafer are presented. The peak of photodiode quantum efficiency is obtained for the wavelengths of 400 500 nm. In addition, noise measurements of the 1/f noise in P MOS and N MOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two implementations (in regular and SOI wafers) of 0.35 /spl mu/m CMOS analog process are compared and it is found that they exhibit similar 1/f noise. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits.
author_names: Igor Brouk

Yael Nemirovsky
title: CMOS SOI image sensor
venue: Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.
year: 2004

abstract: For class E power amplifier circuits operating at switching frequencies of the MHz range or higher, the parasitic capacitance of the MOS transistor switch becomes a significant part of the circuit adding to the usual intended circuit components. For the class E power amplifier, this is often regarded as an advantage because the parasitic capacitor can be utilized for achieving zero voltage and current switchings, thus reducing the size of an external capacitor which has to be inserted. However, parallel connection of parasitic, stray and external capacitors may give rise to high frequency ringings of the voltage across the switch, causing the circuit to deviate from the desired class E operation. In this paper, the phenomenon and its underlying cause is studied by simulations and experiments. A circuit model of the amplifier with parasitic or stray components is developed to explain the phenomenon.
author_names: Hao Zhang

Siu-Chung Wong

C K Michael Tse

Xikui Ma
title: Study of parasitic and stray components induced ringings in class E power amplifiers in MHz range
venue: Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.
year: 2005

abstract: This paper presents a graphical approach for the application of a compact current based MOS model, valid in all regimes of operation, in the design of CMOS operational transconductance amplifiers. Since a large amount of information is made available in the form of contour plots, the method provides a deep insight of design feasibility and allows a rapid and reliable determination of transistor dimensions that satisfy design specifications and saturation conditions. The adjustable contour plots are generated by a sizing program implemented in MATLAB.
author_names: H C M Santos

Ana Isabela Araujo Cunha
title: Application of ACM model to the design of CMOS OTA through a graphical approach
venue: Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
year: 2003