Query: 4 bit flash adc

Candidate papers:

abstract: This study describes the highly digital 4 bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time to market and is scalable with technology. The comparators used in the ADC consist of complementary metal oxide semiconductor (CMOS) based inverter and NAND NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal to noise and distortion ratio, signal to noise ratio and spurious free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non linearity (DNL) of this ADC is 0.25 LSB and integral non linearity (INL) is 0.6 LSB.
author_names: Ashima Gupta

Anil Singh

Alpana Agarwal
title: Highly digital voltage scalable 4 bit flash ADC
venue: IET Circuits Devices Syst.
year: 2019

abstract: This article describes a design of 4 bit Flash analogue digital converter (ADC) for Ultra Wideband (UWB) sensor systems. The ADC cell structure was designed and fabricated in 0.35 um SiGe BiCMOS technology. Proposed ADC cell achieves up to 1.1 Gs/s with maximum input signal range 1.6 Vpp at 1 MHz. The power consumption of the designed cell is 30 mA from 3.3 V power supply. For basic measurement, the ADC has been directly wires bonded to PCB. The basic measurements are represented by time domain and input output ADC characteristics. The ADC was primarily designed as a test structure for M sequence UWB SoC radar.
author_names: Miroslav Sokol

Pavol Galajda

Stanislav Slovak

Martin Pecovsky
title: Design of 4 bit Flash ADC Cell for UWB Sensor Systems
venue: 2019 29th International Conference Radioelektronika (RADIOELEKTRONIKA)
year: 2019

abstract: In this paper, a standard cell low power 4 bit flash analog to digital converter (ADC) is proposed. The converter utilizes comparators created using only logic gates for converting analog input signals to digital values. This novel flash architecture consists of several CMOS gates with inputs connected to a common input node or to one of the supply lines. Depending on the relationship between the input signal and a given gate's threshold voltage, the output will either be `0' or `1' The comparator is followed by an encoder to convert the thermometer code to binary code. Low power consumption is achieved by switching off the unused parallel voltage comparators. The proposed ADC was implemented at the transistor level in a 180nm CMOS technology with a 1.8 V supply voltage and was simulated using Cadence Spectre simulator. Simulation results show that for the same speed, this ADC provides about 70% power reduction compared to a previously proposed design.
author_names: Marcel Siadjine Njinowa

Hung Tien Bui

Francois R Boyer
title: Design of low power 4 bit flash ADC based on standard cells
venue: 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)
year: 2013

abstract: Among all the ADC architectures, Flash ADCs are the most preferred ones. High speed operation is the main reason for selecting Flash ADC. Applications which require high speed conversion in mixed mode signal processing needs Flash ADC. In order to have high speed Flash ADC, the design of comparators is the main task. Since comparators in Flash ADC are power hungry components, we should design each compactor in such a way that overall power consumption should be less. Here we have designed a dynamic comparator consuming low power of 0.169uW. Then we have implemented encoder block using 2:1 MUX. Using these components we have implemented 4 bit Flash ADC which is having power dissipation of 7.2394mW and delay of 29.792ns. The design is implemented in Mentor Graphics tool using 180nm Technology.
author_names: H Patil

M R Raghavendra
title: Low power dynamic comparator for 4 bit Flash ADC
venue: 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)
year: 2016

abstract: In this work a high speed flash ADC based on threshold invert quantization (TIQ) comparator has been proposed. Unlike conventional ADC resistive ladder and comparator bank has been replaced by TIQ comparator which compares the varying input with in built switching potential, 2n 1 number of TIQ requires with different switching for n bit ADC. 4 bit flash ADC has been implemented with static and dynamic TIQ; Different threshold of static TIQ is obtained by scaling the width of PMOS and NMOS individually while in dynamic TIQ input to each inverting stage acts as body voltage decide threshold voltage dynamically, threshold of TIQ is function of individual MOS width and body potential. Cadence Spectre based simulation result show that static TIQ should preferred for low power and dynamic TIQ for high speed.
author_names: Abhishek Kumar
title: Design of 4 Bit Flash ADC Using Static and Dynamic TIQ Comparator
year: 2019

abstract: Nowadays, there is the highest use of converters in the industries. The degradation of power consumption by these converters has great importance. This paper represents a new method to decrease the power consumption of the flash type analog to digital converter with 250 nm CMOS technology by using frequency which is of 1MHz. Flash type ADC requires 2 1 Comparator and its power supply voltage 2.5V. The proposed design of ADC using the Quantum Voltage Comparator eliminates the resistor ladder circuit and improves linearity of ADC. For the encoding process, the Pseudo logic encoder has been used and it provides higher data conversion rate and maintain low power consumption. The proposed 4 bit flash ADC paper having 876 MSPS speed and optimized power consumption by using the pseudo logic encoder and Quantum Voltage Comparator.
author_names: Sarang S Karale

Dhanashri M Hogale
title: Design of 876 MSPS, 2.5v, 250nm, 4 Bit Flash ADC using Quantum Voltage Comparator and Pseudo Logic Encoder
year: 2019

abstract: In this paper design of low power 4 bit Flash ADC for high frequency applications is presented. The power consumption of the Flash ADC in this work has been reduced in two phase. In the first phase a low power dynamic comparator has been designed which consumes 329.332 uW power. In the second phase a low power Fat tree encoder has been designed. The proposed encoder design uses reduced number of gates than the conventional design. As a result the average power dissipation of the encoder block is 43.6uw. The above mentioned Flash ADC is designed using CMOS 90nm Technology in Cadence tool. The proposed design has a power consumption of 5.1096 mW at IV power supply and at a sampling frequency of 1GHz.
author_names: David Sundararaj Shylu

S Radha

P Sam Paul

Parakati Sarah Sudeepa
title: Design of low power 4 bit Flash ADC in 90nm CMOS Process
venue: 2019 2nd International Conference on Signal Processing and Communication (ICSPC)
year: 2019

abstract: This paper presents the design of 4 bit flash type analog to digital converter implemented in 22 nm FD SOI technology with 0.8 V supply voltage. This block is part of original sub ranging ADC whose working principle is based on the assumption that sub ADC and sub DAC exhibit high linearity while they nominal resolutions remain relatively low. The linearity of the presented flash ADC has to be as high as in case of 8 bit converter. Thus, the most challenging task was to design comparator with resolution of 1.5 mV. This goal was reached owing to ability offered by the FD SOI process to trim transistor's threshold voltage by means of modulating the back gate polarization. The resulting sampling rate is 500 Ms/s.
author_names: Zbigniew Jaworski
title: Highly Linear 4 bit Flash ADC Implemented in 22 nm FD SOI Process
venue: 2019 MIXDES 26th International Conference "Mixed Design of Integrated Circuits and Systems"
year: 2019

abstract: This paper presents a 35 GS/s, 4 bit flash ADC DAC with active data and clock distribution trees. At mm wave clock frequencies, skew due to mismatch in the clock and data distribution paths is a significant challenge for both flash and time interleaved converter architectures. A full rate front end track and hold amplifier (THA) may be used to reduce the effect of skew. However, it is found that the THA output must then be distributed to the comparators with a bandwidth greater than the sampling frequency in order to preserve the flat regions of the track and hold waveform. Instead, if the data and clock distribution have very low skew, the THA can be omitted thus obviating the associated nonlinearities and resulting in improved performance. In this work, a tree of fully symmetric and linear BiCMOS buffers, called a ldquodata treerdquo, distributes the input to the comparator bank with a measured 3 dB bandwidth of 16 GHz. The data tree is integrated into a complete 4 bit ADC including a full rate input THA that can be disabled and a 4 bit thermometer code DAC for testing purposes. The chip occupies 2.5 mm times 3.2 mm including pads and is implemented in 0.18 mum SiGe BiCMOS technology. The ADC consumes 4.5 W from a 3.3 V supply while the DAC operates from a 5 V supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3 dB effective resolution bandwidth of 8 GHz and a full scale differential input range of 0.24 Vpp. With the THA enabled, the performance degrades rapidly beyond 8 GHz to less than 1 bit, but with the THA disabled, the ENOB remains better than 3 bits for inputs up to 11 GHz with an SFDR of better than 26 dB.
author_names: Shahriar Shahramian

Sorin P Voinigescu

Anthony Chan Carusone
title: A 35 GS/s, 4 Bit Flash ADC With Active Data and Clock Distribution Trees
venue: IEEE Journal of Solid State Circuits
year: 2009

abstract: A 4 bit noninterleaved flash ADC implemented in 0.18 mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10 11 at 4 GS/s.
author_names: Sunghyun Park

Yorgos Palaskas

Michael P Flynn
title: A 4 GS/s 4 bit Flash ADC in 0.18 \mu{\hbox {m} CMOS
venue: IEEE Journal of Solid State Circuits
year: 2007