Query: TIQ flash ADC with threshold compensation

Candidate papers:

abstract: Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation for a flash ADC architecture which is thermally reliable up to 120 degC. The complete circuit is modeled in cadence virtuoso simulation suite with gpdk 180 nm design library.
author_names: George M Joseph

Talaat A Hameed
title: TIQ flash ADC with threshold compensation
venue: 2021 5th International Conference on Intelligent Computing and Control Systems (ICICCS)
year: 2021

abstract: This paper was presented the design of a threshold inverter quantized (TIQ) comparator in flash analog to digital converter. The TIQ comparator has a high speed response; however this circuit involves a lot of transistors hence wasteful power consumption. The design is intended to obtain a low power TIQ comparator and reduces the area of the chip in 0.18 um CMOS technology. The method was proposed to set each of the transistor channel length for the threshold voltage difference gained of the inverter each in the TIQ comparator and adding a transistor as compensation to overcome the limitations of the length channel expansion due to the body effect influence. This method has reduced the drain current of CMOS transistors; hence the power dissipation can be reduced. The event has achieved low power dissipation of 31.14 uW and a chip size of 1065 um2 with 0 to 0.6 V input signal condition.
author_names: Al Al

Mamun Bin Ibne Reaz

Jubayer Jalil

Mohd Alauddin Mohd Ali
title: An Improved A Low Power CMOS TIQ Comparator Flash ADC
year: 2014

abstract: This brief presents the design of an energy efficient flash analogue to digital converter (ADC) with threshold inverter quantiser comparator employing advanced body biasing to compensate for the effects of parameter variability. The proposed calibration scheme is verified against process, voltage, and temperature corners as well as random parameter variability (mismatch) Two proof of concept ADCs of 4 and 6 bit precision are designed and verified in simulations in 28 nm fully depleted silicon on insulator technology. The 6 bit converter achieves sampling rate of 3 GS/s, energy efficiency per conversion step below 20 fJ, and precision of 5.2 effective number of bits. The proposed ADC architecture is dedicated to high speed and low precision applications, such as communication transceivers and data acquisition systems where area and energy efficiency are paramount.
author_names: Przemyslaw Mroszczyk

John Goodacre

Vasilis F Pavlidis
title: Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2019

abstract: A Threshold Inverter Quantization (TIQ) architecture for Flash Analog to Digital Converters (ADCs) uses inverters as a voltage comparator. TIQ approach has many advantages over a differential voltage comparator, but it is hard to create and select comparators for it. Precise selection of gate switching voltage is crucial for Flash Analog to Digital Converters (ADCs) Therefore, Differential Non Linearity (DNL) and Integral Non Linearity (INL) error measurements are used to understand how precisely voltage comparators are selected. Different selection algorithms are used to make selection as precise as possible. In this work, we present two new algorithms based on a dynamic programming approach along with DNL and INL simulation results. Comparison with state of the art methods, 4 times, and 5 times DNL improvements are achieved through the new approach for 6 bit and 8 bit respectively.
author_names: Ali Ozdemir

Mshabab Alrizah

Kyusun Choi
title: Optimization of Comparator Selection Algorithm for TIQ Flash ADC Using Dynamic Programming Approach
venue: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
year: 2019

abstract: Threshold Inverter Quantization (TIQ) for applications of system on chip (SoC) depending on CMOS flash analog to digital converter (ADC) The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low power and low voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1] The findings indicate that the TIQ flash ADC based on Modied mux attain heavy speed transformation and has a tiny size, low power dissipation and operation of lowvoltage compared to another flash ADCs.
author_names: Ch Venkata Dharani

J Ravi
title: TIQ Flash ADC Design using a Low Power Multiplier Based Encoder
venue: International Journal of Recent Technology and Engineering
year: 2019

abstract: In this work a high speed flash ADC based on threshold invert quantization (TIQ) comparator has been proposed. Unlike conventional ADC resistive ladder and comparator bank has been replaced by TIQ comparator which compares the varying input with in built switching potential, 2n 1 number of TIQ requires with different switching for n bit ADC. 4 bit flash ADC has been implemented with static and dynamic TIQ; Different threshold of static TIQ is obtained by scaling the width of PMOS and NMOS individually while in dynamic TIQ input to each inverting stage acts as body voltage decide threshold voltage dynamically, threshold of TIQ is function of individual MOS width and body potential. Cadence Spectre based simulation result show that static TIQ should preferred for low power and dynamic TIQ for high speed.
author_names: Abhishek Kumar
title: Design of 4 Bit Flash ADC Using Static and Dynamic TIQ Comparator
year: 2019

abstract: Objective: To design and implement flash ADC for high speed operation thereby to minimise the power consumption and improve the performance efficiency. Methods: At present, there exists a variety of Analog to Digital Converter (ADC) with different architecture, sampling rates, resolutions, temperature ranges, and power consumption. The existing ADCs used in various multiple applications which include mobile communication hardware to measuring instruments. Therefore, their significant performance and working of ADCs are determined by its architecture, the commonly existing ADC design is not suitable for all applications. In order to meet the high speed operation scenario, a Flash type ADC model is proposed. Findings: Resistor ladder would be commonly used in all type of ADC circuits, but downside it consume maximum area and power. In all existing methods, the average power consumption of Flash ADC is found to be higher when compared with our methodology. This can be overcome by using threshold inverting quantization (TIQ) comparator for low power operation. Improvements: An efficient thermometer to the binary code converter is targeted for 45 nm CMOS technology that has been proposed and implemented Flash CMOS ADC Design using the CADENCE VIRTUOSO Tool. The optimal power analysis has been carried out to prove the design absolutely a low power model.
author_names: Ayyavoo Mithila

Lavanya A

Nithyashree A R

Mithra T R
title: Design of Efficient Low Power Flash ADC Using TIQ in 45 nm Technology
year: 2019

abstract: Integral nonlinearity and differential nonlinearity are the two main performance parameters for a high speed flash analog to digital converter, which determine the accuracy of the converter. Analog to Digital Converter (ADC) circuits are designed to achieve ideal performance zero linearity. However, the linearity is unavoidable due to the process variation, operating temperature variation, and power supply voltage variation when the data converters are manufactured and used in non ideal environments. We present the new and improved transistor sizing algorithms for the Threshold Inverter Quantization (TIQ) flash comparator circuit design software package, the sizing algorithm that will results in minimal linearity for the TIQ ADCs after they are manufactured and used in non ideal environments. In comparison to the previous algorithms, the proposed new transistor sizing algorithms reduce the worst case linearity by 80% or more. In the future, when implementing ADC circuits with below 30nm CMOS FinFET technology, the TIQ flash ADC is the first candidate because only two transistors are present between the power supply rails, and the transistor sizing is based on the discrete count of fins.
author_names: Jun Hyuk Park
title: IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS
year: 2017

abstract: In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL) integral nonlinearity (INL) analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10 bit single channel TIQ flash ADC. Further, it took FADA 6 h to design the 10 bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10 bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10 bit TIQ flash ADC has simulated signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high performance versus low noise TIQ flash ADCs designs.
author_names: Abdulrahman Abumurad

Ali Ozdemir

Kyusun Choi
title: 10 Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design
venue: Circuits Syst. Signal Process.
year: 2019

abstract: The comparator is the most important component in the ADC architecture. Its role is to convert an input voltage Vin into a logic 1 or 0 by comparing a reference voltage Vref with Vin. If the Vin is greater than Vref the output of the comparator is 1 otherwise 0. Commonly used comparator structure in CMOS ADC design is fully defined latch comparators. The TIQ comparator uses two cascaded CMOS inverters as a comparator for high speed conversion and low power dissipation. The aim of the project is to implement MTIQ comparator in Flash ADC by replacing ordinary comparators. It is possible to achieve higher speed, linearity, accuracy, and high resolution The project aims to make a TIQ implemented ADCs for less area and power using different compaction algorithms in layout tools like MAGIC/CADENCE.All the power Calculations are done using SPICE/CADENCE Spectre tools.
author_names: Joshua Daniel Raj J
title: DESIGN OF MULTIPLE THRESHOLD INVERTER QUANTIZATION BASED FLASH ADC USING CUSTOM LAYOUT TOOLS
year: 2018