Query: Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Candidate papers:

abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal oxide semiconductor field effect transistor (MOSFET) In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.
author_names: Isabelle Ferain

Cindy Colinge

J P Colinge
title: Multigate transistors as the future of classical metal oxide semiconductor field effect transistors
venue: Nature
year: 2011

abstract: Device white noise levels in short channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) dictate the performance and reliability of high frequency circuits ranging from high speed microprocessors to Low Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source channel junction. By adopting a semi classical approach and taking retrospectively into account transport, short channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.
author_names: Christos Spathis

Alexios N Birbas

Konstantina-Maria Georgakopoulou
title: Semi classical noise investigation for sub 40nm metal oxide semiconductor field effect transistors
year: 2015

abstract: Abstract N type metal oxide semiconductor field effect transistors (NMOSFETs) using strained silicon carbon alloy (Si 1 x C x surface channels are reported in this work. Tensile strained Si 1 x C x layers with substitutional carbon content up to 1% were epitaxially grown on (100) Si substrates by ultra high vacuum chemical vapor deposition, using silane and methylsilane as the silicon and carbon sources, respectively. NMOSFETs were fabricated using standard MOS processing with reduced thermal treatment in order to minimize the possibility of strain relaxation. A reciprocal space mapping method was used to analyze strain distribution in the silicon carbon alloy thin films on Si substrates. The election inversion layer mobilities of the Si 1 x C x and Si control devices at room temperature are comparable. This is in contrast to the electron mobility enhancement observed in NMOSFETs fabricated using tensile strained Si grown on relaxed Si 1 x Ge x layers. At low temperatures, the electron inversion layer mobility of Si 1 x C x devices is lower than that of the Si controls, and appears to be affected by Coulomb as well as possibly by random alloy scattering.
author_names: B F Hsieh

Shun-Ping Chang

Min-Hung Lee
title: Characterization of silicon carbon alloy materials for future strained Si metal oxide semiconductor field effect transistors
year: 2013

abstract: Steep slope $SS<60$ mV/dec at room temperature) negative capacitance (NC) FETs, based on the 2 D transition metal dichalcogenide semiconductor channel materials, may have a promising future in low power electronics because of their high on state current and very high on/off ratio. In this paper, we develop an analytically compact drain current model for long channel back gated 2 D NC FETs by solving the classical drift diffusion equations. The equations describe the transition from depletion to accumulation regimes of operation as a continuous function of gate/drain voltages. The continuity ensures time efficient simulation of large systems. Several key features of the model are verified by comparing with the experimental data. Specifically, the negative drain induced barrier lowering effect and negative differential resistance effect predicted by the model are successfully observed in our experiments.
author_names: Chunsheng Jiang

Mengwei Si

Renrong Liang

Jun Xu

Peide D Ye

Muhammad Ashraful Alam
title: A Closed Form Analytical Model of Back Gated 2 D Semiconductor Negative Capacitance Field Effect Transistors
venue: IEEE Journal of the Electron Devices Society
year: 2018

abstract: Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top down fabricated gate all around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label free electronic chips for molecular diagnostics.
author_names: Pengpeng Zhang

Theresa S Mayer

Thomas N Jackson
title: 2007 IEEE Device Research Conference: Tour de Force Multigate and Nanowire Metal Oxide Semiconductor Field Effect Transistors and Their Application.
venue: ACS nano
year: 2007

abstract: This article gives a detailed review on the evaluation of present development and future projection of high mobility strained silicon Metal Oxide Semiconductor Field Effect Transistors technology. Recent scaling of integrated circuit technology limits the employment of conventional strained silicon, thus walks the combination of high mobility strained channel with others advanced technologies. Various types of strain channel on relaxed SixGe1 x were reviewed, with focus on the layer architecture, energy band structure and mobility characteristics. Also, an attempt has been made to review the literature on the performance enhancement of strain engineering integrated on various structures, including on insulator, multiple gate, carbon nanotubes as well as the graphic. The combination of high mobility channels with advanced architectures are expected to take a greater share in the near future.
author_names: Eng Siew Kang

Fatimah Hamid

Razali Ismail
title: Future of nanoscale strained Si/SixGe1 x Metal Oxide Semiconductor Field Effect Transistor for performance metric evaluation: A review
year: 2014

abstract: In this paper, the variabilities of threshold voltage (VTH) drain induced barrier lowering (DIBL) and current onset voltage (COV) in intrinsic channel silicon nanowire metal oxide semiconductor field effect transistors (MOSFETs) were evaluated and compared with those of conventional bulk and fully depleted (FD) silicon on insulator (SOI) MOSFETs. The random component of variability is extracted by a "within device" variability method to exclude the systematic component. It is found that the within device variabilities of DIBL and COV as well as VTH are extremely small in intrinsic channel nanowire MOSFETs owing to the non intentionally doped channel and small gate workfunction variability. The intrinsic channel nanowire MOSFET is promising for a future scaled device structure in terms of not only the short channel effect suppression but also the variability suppression.
author_names: Ke Mao

Tomoko Mizutani

Anil Kumar

Takuya Saraya

Toshiro Hiramoto
title: Suppression of Within Device Variability in Intrinsic Channel Tri Gate Silicon Nanowire Metal Oxide Semiconductor Field Effect Transistors
year: 2012

abstract: Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n MOSFET is embedded silicon carbon (eSi:C) However, n MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels.
author_names: S Flachowsky

Ralf Illgen

Tom Herrmann

Wilfried Klix

Roland Stenzel

Ina Ostermay

Andreas Naumann

Andy Wei

Jan Hontschel

Manfred Horstmann
title: Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors
year: 2010

abstract: Metal oxide semiconductor (MOS) field effect transistor (FET) scaling is following the prediction of the Moore's law for the past 45 years, a key factor that enabled the IC industry to cope with the everlasting demand for higher performances. However, this scaling process becomes increasingly difficult as several limits from both process and device capabilities pop up as the technology node reaches 28nm and beyond. To stand the pace of downscaling, non classical devices are currently introduced in the roadmap. In this context, the junctionless FET is part of these attempts. It is a new emerging device that can potentially withstand the downscaling of CMOS technology as it still has an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes. This dissertation focuses on the physics and modeling of nanoscale junctionless double gate MOSFET and junctionless nanowire FETs. The first part of the thesis is focusing on junctionless transistors by discussing the advantages and limitations of such technology. A brief overview of existing models and the current status of symmetrical/asymmetrical operation of junctionless FETs in a planar double gate configuration as well as junctionless nanowires topologies will be presented. Next, the model that is developed in this thesis is detailed in different chapter, each of which will cover a specific aspect. The model relies on Poisson Boltzmann equation and on the drift diffusion transport to derive charges and current in long channel devices. It is based on two set of relationships to cover all the operating regions: from depletion to accumulation; from linear to saturation with no fitting parameter. Following a core analysis, more features are developed and added to the ideal long channel concept. This includes modeling short channel effects and DIBL, modeling full trans capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off state currents. Importantly, we have shown that equivalent symmetric devices could also be used to simulate asymmetric operation, which are likely to be the most common situation. In addition, the charge based approach developed along the thesis has also been generalized to the quite popular junctionless nanowire architecture. Regarding junctionless FETs, technological parameter are very critical. For instance, the device cannot be made of any dimension and doping otherwise it cannot be effectively switched off at a given current. Therefore, we also derived rules providing a design space tool with explicit links between silicon thickness and doping ensuring safe operation. Finally, since the mobility extraction in junctionless FETs is still an issue, we have developed a new method for a reliable measurement of free carriers mobility in real devices which does not assume any predefined mobility law. Based on these developments, the EPFL JL model was implemented into Hspice platforms to be used by circuit designers.
author_names: Farzan Jazaeri
title: Modeling Junctionless Metal Oxide Semiconductor Field Effect Transistor
year: 2015

abstract: We clarified in this study how plasma induced charging damage (PCD) affects the so called "random telegraph noise (RTN)" a principal concern in designing ultimately scaled large scale integrated circuits (LSIs) Metal oxide semiconductor field effect transistors (MOSFETs) with SiO2 and high k gate dielectric were exposed to an inductively coupled plasma (ICP) with Ar gas. Drain current vs gate voltage (Ids Vg) characteristics were obtained before and after the ICP plasma exposure for the same device. Then, the time evolution of Ids fluctuation defined as Ids/mIds was measured, where mIds is the mean Ids. This value corresponds to an RTN feature, and RTN was obtained under various gate voltages (Vg) by a customized measurement technique. We focused on the statistical distribution width of (Ids/mIds) d(Ids/mIds) in order to clarify the effects of PCD on RTN. d(Ids/mIds) was increased by PCD for both MOSFETs with the SiO2 and high k gate dielectrics, suggesting that RTN can be used as a measure of PCD, i.e. a distribution width increase directly indicates the presence of PCD. The dependence of d(Ids/mIds) on the overdrive voltage Vg Vth, where Vth is the threshold voltage, was investigated by the present technique. It was confirmed that d(Ids/mIds) increased with a decrease in the overdrive voltage for MOSFETs with the SiO2 and high k gate dielectrics. The presence of created carrier trap sites with PCD was characterized by the time constants for carrier capture and emission. The threshold voltage shift (DVth) induced by PCD was also evaluated and compared with the RTN change, to correlate the RTN increase with DVth induced by PCD. Although the estimated time constants exhibited complex behaviors due to the nature of trap sites created by PCD, d(Ids/mIds) showed a straightforward tendency in accordance with the amount of PCD. These findings provide an in depth understanding of plasma induced RTN characteristic changes in future MOSFETs.
author_names: Masayuki Kamei

Yoshinori Takao

Koji Eriguchi

Kouichi Ono
title: Effects of plasma induced charging damage on random telegraph noise in metal oxide semiconductor field effect transistors with SiO
year: 2014