Query: Ultrathin Film Organic Transistors: Precise Control of Semiconductor Thickness via Spin‐Coating

Candidate papers:

abstract: Construction of ultrathin film organic transistors is an important challenge towards deeper understanding of the charge transport mechanism and multifunctional applications. We report on precise thickness control of ultrathin films of several organic semiconductors by using a simple spin coating approach. Ultrathin film, n channel organic transistors with mobilities well over 1.0 cm(2) V( 1) s( 1) have been realized and their potential in high sensitivity gas sensing and other applications is demonstrated.
author_names: Fengjiao Zhang

Chong-an Di

Nikolai Berdunov

Yuanyuan Hu

Yun Hua Hu

Xike Gao

Qing Meng

Henning Sirringhaus

Daoben Zhu
title: Ultrathin film organic transistors: precise control of semiconductor thickness via spin coating.
venue: Advanced materials
year: 2013

author_names: Fengjiao Zhang

Chong-an Di

Nikolai Berdunov

Yuanyuan Hu

Yun Hua Hu

Xike Gao

Qing Meng

Henning Sirringhaus

Daoben Zhu
title: Organic Electronics: Ultrathin Film Organic Transistors: Precise Control of Semiconductor Thickness via Spin Coating (Adv. Mater. 10/2013)
year: 2013

abstract: Ultrathin film with thickness below 15 nm of organic semiconductors provides excellent platform for some fundamental research and practical applications in the field of organic electronics. However, it is quite challenging to develop a general principle for the growth of uniform and continuous ultrathin film over large area. Dip coating is a useful technique to prepare diverse structures of organic semiconductors, but the assembly of organic semiconductors in dip coating is quite complicated, and there are no reports about the core rules for the growth of ultrathin film via dip coating until now. In this work, we develop a general strategy for the growth of ultrathin film of organic semiconductor via dip coating, which provides a relatively facile model to analyze the growth behavior. The balance between the three direct factors (nucleation rate, assembly rate, and recession rate) is the key to determine the growth of ultrathin film. Under the direction of this rule, ultrathin films of four organic semiconductors are obtained. The field effect transistors constructed on the ultrathin film show good field effect property. This work provides a general principle and systematic guideline to prepare ultrathin film of organic semiconductors via dip coating, which would be highly meaningful for organic electronics as well as for the assembly of other materials via solution processes.
author_names: Kunjie Wu

Hongwei Li

Liqiang Li

Suna Zhang

Xiaosong Chen

Zeyang Xu

Xi Zhang

Wenping Hu

Lifeng Chi

Xike Gao

Yancheng Meng
title: Controlled Growth of Ultrathin Film of Organic Semiconductors by Balancing the Competitive Processes in Dip Coating for Organic Transistors.
venue: Langmuir the ACS journal of surfaces and colloids
year: 2016

abstract: This work demonstrates that threshold voltage (VT) of organic thin film transistors (OTFTs) can be controlled systematically by introducing new copolymer dielectrics with electropositive functionality. A series of homogeneous copolymer dielectrics are polymerized from two monomers, 1,3,5 trimethyl 1,3,5 trivinyl cyclotrisiloxane (V3D3) and 1 vinylimidazole (VI) via initiated chemical vapor deposition. The chemical composition of the copolymer dielectrics is exquisitely controlled to tune the VT of C60 OTFTs. In particular, all the copolymer dielectrics demonstrated in this work exhibit extremely low leakage current densities (lower than 2.5 x 10 8 A cm 2 at 3 MV cm 1) even with a thickness less than 23 nm. Furthermore, by introducing an ultrathin pV3D3 interfacial layer (about 3 nm) between the copolymer dielectrics and C60 semiconductor, the high mobility of the C60 OTFTs (about 1 cm2 V 1 s 1) remains unperturbed, showing that VT can be controlled independently by tuning the composition of the copolymer dielectrics. Coupled with the ultralow dielectric thickness, the independent VT controllability allows the VT to be aligned near 0 V with sub 3 V operating voltage, which enables a substantial decrease of device power consumption. The suggested method can be employed widely to enhance device performance and reduce power consumption in various organic integrated circuit applications.
author_names: Kwanyong Pak

Hyejeong Seong

Junhwan Choi

Wan Sik Hwang

Sung Gap Im
title: Synthesis of Ultrathin, Homogeneous Copolymer Dielectrics to Control the Threshold Voltage of Organic Thin Film Transistors
year: 2016

abstract: A precise control over the film thickness is a vital requirement for achievement of high performance in thin film electronic devices. On page 2752, Y. Y. Noh and co workers develop an effective way to deposit a large area and uniform ultrathin polymer film with a molecular level precision via a simple wire wound bar coating method for high performance organic transistors and gas sensors.
author_names: Dongyoon Khim

Gi-Seong Ryu

Won-Tae Park

Hyunchul Kim

Myung Sub Lee

Yong-Young Noh
title: Chemical Sensors: Precisely Controlled Ultrathin Conjugated Polymer Films for Large Area Transparent Transistors and Highly Sensitive Chemical Sensors (Adv. Mater. 14/2016)
venue: Advanced materials
year: 2016

abstract: We report here on the rational synthesis, processing, and dielectric properties of novel layer by layer organic/inorganic hybrid multilayer dielectric films enabled by polarizable p electron phosphonic acid building blocks and ultrathin ZrO(2) layers. These new zirconia based self assembled nanodielectric (Zr SAND) films (5 12 nm thick) are readily fabricated via solution processes under ambient atmosphere. Attractive Zr SAND properties include amenability to accurate control of film thickness, large area uniformity, well defined nanostructure, exceptionally large electrical capacitance (up to 750 nF/cm(2) excellent insulating properties (leakage current densities as low as 10( 7) A/cm(2) and excellent thermal stability. Thin film transistors (TFTs) fabricated with pentacene and PDIF CN(2) as representative organic semiconductors and zinc tin oxide (Zn Sn O) as a representative inorganic semiconductor function well at low voltages 4.0 V) Furthermore, the TFT performance parameters of representative organic semiconductors deposited on Zr SAND films, functionalized on the surface with various alkylphosphonic acid self assembled monolayers, are investigated and shown to correlate closely with the alkylphosphonic acid chain dimensions.
author_names: Young-Geun Ha

Jonathan D Emery

Michael J Bedzyk

Hakan Usta

Antonio F Facchetti

Tobin J Marks
title: Solution deposited organic inorganic hybrid multilayer gate dielectrics. Design, synthesis, microstructures, and electrical properties with thin film transistors.
venue: Journal of the American Chemical Society
year: 2011

abstract: For large area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high performance, ultralow voltage operation of thin film transistors (TFTs) In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low temperature solution process to produce ultralow voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid based self assembled monolayers combined with ultrathin high k oxide layers. The nanoscopic thickness controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm2) insulating property (leakage current densities <10 7 A/cm2) and thermal stability (up to 300 degC) as well as smooth surfaces (root mean square roughness <0.35 nm) In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono and bifunctional phosphonic acid based self assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high performance, ultralow voltage operation 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow power and large area electronic devices.
author_names: Hye-Ran Byun

Eun-Ah You

Young-Geun Ha
title: Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow Power Organic and Amorphous Oxide Thin Film Transistors.
venue: ACS applied materials interfaces
year: 2017

abstract: Low voltage driven organic thin film transistors (organic TFTs) with spatially controlled threshold voltages 1.2 and 0.36 V) were fabricated for the first time. Using the microcontact printing method, tetradecylphosphonic acid (HC14 PA) and pentadecylfluoro octadecylphosphonic acid (FC18 PA) were transferred to form ultrathin layers in different regions on a substrate. Together with plasma grown aluminum oxide (AlOx) layer, the stamped layers were shown to have equal insulating ability as the dipped method monolayer. The feasibility of the area selective stamping method was displayed using locally controlled inverter circuits. The shift of turn on voltage for those transistors was consistent with the threshold voltage shift of the transistors. Recently, organic thin film transistors (organic TFTs) have attracted attention because they are a key element in realizing a new class of devices such as flexible displays, radio frequency identification tags, and large area sensor arrays. As a result of organic transistor technology advancement, large scale integration such as processors and shift registers has become possible. An important prerequisite for the reliable operation of such highly complex circuits are large noise margins that are indispensable for the successful suppression of inadvertent switching events in the unavoidable presence of electronic noise. Large noise margins in turn require precise and deterministic control of the threshold voltage of the transistors. Doping is widely used in inorganic transistors to control threshold voltage; however, many dopants are unstable and diffuse into organic materials, which makes it difficult to control the threshold voltage in organic transistors. Alternatively, surface modification is a very effective method to control the threshold voltage in organic transistors. The threshold voltage can be controlled using cross linked organic insulating polymers, thin layers of hexamethyldisilazane, and self assembled monolayers (SAMs) In particular, SAMs in combination with ultrathin metal oxide dielectrics are particularly attractive, since they provide very low operation voltages of only a few volts, along with deterministic control of the threshold voltage, through the alkyl chain length and/or the electron donating or withdrawing properties of materials such as fluoroalkylphosphonic acid. Typically, SAMs are formed by dipping the entire substrate into a solution of the molecules, so that all TFTs on the substrate end up having the same threshold voltage. However, for certain applications it is highly desirable to have TFTs with two different threshold voltages in specific locations on the same substrate. For example, to control the switching voltage of a p type metal oxide semiconductor (pMOS) inverter, the threshold voltages of two transistors that consist of the inverter should be spatially controlled. In principle, this can be accomplished by a printing process such as areaselective microcontact printing, which also provides a wide patterning range of surface modification materials. However, to our knowledge this possibility has not been exploited so far. Reported herein is the fabrication of organic transistors with different threshold voltages on the substrate that are defined by area selective microcontact printing "stamping" using polydimethylsiloxane (PDMS) Solutions of tetradecylphosphonic acid (HC14 PA) or pentadecylfluoro octadecylphosphonic acid (FC18 PA) were printed "stamped" on the surface of Al gate electrodes coated with a few nanometers thick aluminum oxide (AlOx) The average thickness of the stamped ultrathin layer was one or two monolayers. Their insulating MRS Communications (2011) 1, 33 36 (c) Materials Research Society, 2011 doi:10.1557/mrc.2011.11 MRS COMMUNICATIONS VOLUME 1 ISSUE 1 www.mrs.org/mrc 33 properties were equivalent to those of single SAMs prepared by conventional dipping and the leakage current density was two or three orders of magnitude smaller than the transistors without SAMs. The difference in threshold voltage between TFTs with the HC14 PA gate dielectric and TFTs with the FC18 PA gate dielectric was 0.83 V, which is about 42% of the supply voltage (2 V) By stamping HC14 PA and FC18 PA SAMs onto different regions on the same substrate, TFTs having different threshold voltages were realized in specific locations of the substrate, allowing the availability of TFTs with different threshold voltages to be exploited for the realization of robust integrated circuits. The development of the device structure is schematically shown in Fig. 1(a) The Al gate electrodes with a thickness of 30 nm were evaporated through a shadow mask onto a Si substrate with a 500 nm thick oxidized surface. The surface of the electrode was oxidized by plasma (200 W, 30 s) to form a thin, dense AlOx layer. The SAMs were then transferred onto the Al/AlOx stack from a PDMS (Sylgard(r) 184 Silicone Elastomer Kit; Midland, MI) The stamp was first dipped into 2 propanol solution of 1 mmol/l either HC14 PA or FC18 PA solutions for 5 min and then placed onto the Si/Al/ AlOx surface for 10 min to allow a molecular monolayer to selfassemble on the AlOx surface. For comparison, SAMs formed by dipping were also prepared in which the substrate was immersed in a 2 propanol solution of 1 mmol/l of HC14 PA or FC18 PA and then rinsed with pure 2 propanol. The last step in both the stamping and dipping process was to bake the substrate on a hotplate at 100 degC for 10 min. A 30 nm thick layer of organic semiconductor dinaphtho[2,3 b:2',3' f]thieno [3,2 b]thiophene (DNTT) was evaporated at room temperature. Finally, the source and drain electrodes with a channel length of 40 mm were evaporated. An optical microscopic image of the fabricated transistor is shown in Fig. 1(b) Figure 1(c) shows the leakage current density measured on Al/AlOx/SAM/Au capacitors (without semiconductor) based on SAMs of either HC14 PA or FC18 PA prepared by either stamping or dipping, plus a control device without SAM. The top surface size for the Au electrodes was 700 x 100 mm. In Fig. 1(c) it can be seen that all the capacitors with SAMs, either dipped or stamped, exhibited a current density that was two or three orders of magnitude smaller than that without SAM, confirming the important role of SAM in suppressing gate leakage. The difference in current density demonstrates that a pinholefree thin layer was formed using the stamping process. Also note that stamped SAMs exhibited leakage currents that were smaller than dipped SAM samples, which have previously shown the ability to integrate at the circuit level (see also Supplementary information) Further integration studies using stamped SAMs will be examined at a later time. Figure 1. (a) Schematic of the stamping process, including the process to prepare SAMs of two different phosphonic acids in different regions on the same substrate by microcontact printing (stamping) (b) Photograph of a completed organic transistor. (c) Leakage current density as a function of applied voltage measured on five different SAM capacitors (red: dipped HC14 PA; blue: dipped FC18 PA; yellow: stamped HC14 PA; green: stamped FC18 PA; black: control device without SAM) The measurement was replicated ten times to assure uniformity. (d) Capacitance as a function of frequency under a bias voltage of 1 V. 34# MRS COMMUNICATIONS VOLUME 1 ISSUE 1 www.mrs.org/mrc Figure 1(d) shows the capacitance frequency response. It can be seen that the capacitances of all the devices with SAMs were in the range expected from previous reports: close to 800 nF/cm for HC14 PA and (600 100) nF/cm for FC18 PA. Note that dipped samples always exhibit larger capacitance than stamped samples. Assuming that the dielectric constant of SAMs is 2.5, the thickness of the SAM layers was evaluated from the capacitance as 0.9 and 1.2 nm for dipped and stamped HC14 PA layers, respectively, as compared to 1.4 and 2.7 nm for dipped and stamped FC18 PA layers, respectively, which were very close to the SAM molecule length of 2.3 nm. In AFM observation, the surface morphology of DNTT grains on dipped SAM is different from that on stamped SAM, which can be ascribed to the difference of the surface smoothness of SAM layers even though the average thickness was one or two monolayers for both HC14 PA and FC18 PA samples, since the grain size of the DNTT is affected by the smoothness of the SAM layer underneath (see also Supplementary Fig. 1 online) The multilayer of stamped samples is considered to be due to the excess SAM molecules, which were not rinsed. It is important to remember that the leakage current of stamped samples was smaller than that of dipped samples, as shown in Fig. 1(c) Although this is an indirect measure, it still provides evidence that the possible existence of sub monolayer coverage can be excluded. Future structural characterization is necessary. Transistor characteristic properties were measured in ambient air at room temperature using a semiconductor parameter analyzer (Agilent 4156C) Agilent Technologies (Santa Clara, CA) The representative transfer curves for transistors without SAMs and those dipped or stamped with SAMS are shown in Fig. 2 (a) The mobilities and the threshold voltages were extracted from the transfer curves. Histograms of the threshold voltages of 38 transistors are shown in Fig. 2(b) (for a summary, see also Supplementary Table 1 online) along with the field effect mobilities that were also extracted from the transfer curves. Regardless of the process and/or species of SAM, all samples with SAMs exhibited larger mobility than those without SAM, as expected. The HC14 PA samples had a higher mobility than the FC18 PA samples, which is also in line with previous reports. Furthermore, all the samples with SAMs exhibited larger on/off ratios than those samples without SAMs, as a result of smaller gate leakage currents. Most importantly,
author_names: Ikue Hirata

Ute Zschieschang

Frederik Ante

Tomoyuki Yokota

Kazunori Kuribara

Tatsuya Yamamoto

Kazuo Takimiya

Masaaki Ikeda

Hirokazu Kuwabara

Hagen Klauk

Tsuyoshi Sekitani

Takao Someya
title: Rapid Communications Spatial control of the threshold voltage of low voltage organic transistors by microcontact printing of alkyl and fl uoroalkyl phosphonic acids
year: 2011

abstract: Fabrication techniques and process integration considerations for amorphous oxide semiconductor (AOS) thin film transistors (TFTs) constitute the central theme of this dissertation. Within this theme three primary areas of focus are pursued. The first focus involves formulating a general framework for assessing passivation. Avoiding formation of an undesirable backside accumulation layer in an AOS bottom gate TFT is accomplished by (i) choosing a passivation layer in which the charge neutrality level is aligned with (ideal case) or higher in energy than that of the semiconductor channel layer charge neutrality level, and (ii) depositing the passivation layer in such a manner that a negligible density of oxygen vacancies are present at the channel passivation layer interface. Two AOS TFT passivation schemes are explored. Sputter deposited zinc tin silicon oxide (ZTSO) appears promising for suppressing the effects of negative bias illumination stress (NBIS) with respect to ZTO and IGZO TFTs. Solution deposited silicon dioxide is used as a barrier layer to subsequent PECVD silicon dioxide deposition, yielding ZTO TFT transfer curves showing that the dual layer passivation process does not significantly alter ZTO TFT electrical characteristics. The second focus involves creating an adaptable back end process compatible with flexible substrates. A detailed list of possible via formation techniques is presented with particular focus on non traditional and adaptable techniques. Two of the discussed methods, "hydrophobic surface treatment" and "printed local insulator," are demonstrated and proven effective. The third focus is printing AOS TFT channel layers in order to create an adaptable and additive front end integrated circuit fabrication scheme. Printed zinc indium aluminum oxide (ZIAO) and indium gallium zinc oxide (IGZO) channel layers are demonstrated using a SonoPlot piezoelectric printing system. Finally, challenges associated with printing electronic materials are discussed. Organic based solutions are easier to print due to their ability to "stick" to the substrate and form well defined patterns, but have poor electrical characteristics due to the weakness of organic bonds. Inorganic aqueous based solutions demonstrate good electrical performance when deposited by spin coating, but are difficult to print because precise control of a substrate's hydrophillic/hydrophobic nature is required. However, precise control is difficult to achieve, since aqueous based solutions either spread out or ball up on the substrate surface. Thickness control of any printed solution is always problematic due to surface wetting and the elliptical thickness profile of a dispensed solution.
author_names: Eric Steven Sundholm
title: Nontraditional amorphous oxide semiconductor thin film transistor fabrication
year: 2012

abstract: A simple and unidirectional printing of sol gel metal oxide dielectric layers via bar coating was successfully demonstrated while the nanoscale control of ultrathin film thickness (6 30 nm) and the excellent insulating performance were achieved. According to various physical and electrical characterizations, the present bar printing method enabled to fabricate smooth, dense, and uniform thin oxide films which were comparable to or slightly better than those prepared by spin coating. Finally, both semiconductor and dielectric films were successively patterned by bar printing employing the phenomenon of selective surface wetting, leading to high performance low voltage all solution processed metal oxide transistors.
author_names: Myung-Han Yoon

Won-June Lee

Won-Tae Park

Sungjun Park

Yong-Young Noh
title: 71 5: In Depth Study on Large Area Bar Printing and Selective Area Direct Patterning of Metal Oxide Dielectrics for High Performance Transistor Application
year: 2016