Query: Wide-Bandgap Vertical Power FinFETs

Candidate papers:

abstract: FinFET is the backbone device technology for CMOS electronics at deeply scaled technology nodes per Moore's law. Recently, the FinFET concept has been leveraged to develop a new generation of vertical power transistors based on wide bandgap (WBG) and ultrawide bandgap (UWBG) semiconductors for kilovolts and high power applications. The sidewall gate stack in a vertical power FinFET can rely on either a metal oxide semiconductor (MOS) structure or a p n junction, rendering a Fin MOSFET or a fin based junction field effect transistor (Fin JFET) respectively. Although the device technologies are still at the early stage of development, 1.2 kV class WBG gallium nitride (GaN) power Fin MOSFETs have demonstrated one of the highest static and switching performances in all similarly rated power transistors; UWBG gallium oxide power Fin MOSFETs have shown high performance up to a breakdown voltage over 2.6 kV. Early UWBG diamond lateral power Fin MOSFETs have also been demonstrated. Meanwhile, GaN power Fin JFETs are currently under active development. This article provides a comprehensive tutorial and review of the background and recent advances in WBG and UWBG vertical power FinFETs. It covers fundamental device physics, device and process development, as well as the static and switching performance of various power Fin MOSFETs and Fin JFETs. This article is concluded by identifying the current challenges and exciting research opportunities in this very dynamic research field.
author_names: Yuhao Zhang

Tomas Palacios
title: (Ultra)Wide Bandgap Vertical Power FinFETs
venue: IEEE Transactions on Electron Devices
year: 2020

abstract: This work evaluates the switching performance of 1.2 kV vertical GaN power FinFETs using the mixed mode device circuit TCAD simulation. The device simulation is calibrated with the I V and C V characteristics of experimental devices. A double pulse circuit is implemented in the mixed mode simulation and subsequently used to evaluate the device turn on/turn off times and switching losses under hard switching. To improve the switching performance of vertical power FinFETs, a novel inter fin design is proposed based on the split gate geometry. This structure removes the gate metal in the inter fin region and exposes the drift layer to the source metal. During the device turn (on)off transients, the drift layer underneath the inter fin gap region is (dis)charged by the drain to source current instead of gate current, leading to shorter switching times and lower switching losses. By utilizing this split gate structure, over 47% superior switching figure of merit (FOM) and over 30% lower switching losses have been demonstrated in 1.2 kV vertical GaN power FinFETs. The 1.2 kV, 80 mO split gate vertical GaN power FinFETs show over 30% superior switching FOM and over 50% smaller switching losses when compared to commercial 1.2 kV SiC MOSFETs under similar switching conditions. These results provide important guidelines for the design of vertical GaN power FinFETs and show their great potentials for high frequency medium voltage power applications.
author_names: Hengyu Wang

Ming Xiao

Kuang Sheng

Tomas Palacios

Yuhao Zhang
title: Switching Performance Evaluation of 1200 V Vertical GaN Power FinFETs
venue: 2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)
year: 2019

abstract: We review recent development of In(Ga)As channel MOSFETs. Planar UTB devices with raised regrown source and drain scale readily to sub 20nmgate lengths. Low effective mass InAs and InGaAs channels, combined with thin gate dielectrics, provide high transconductance, but off state leakage can be high due to band band and source drain tunneling currents. Leakage is reduced through thin 2.5 3nmchannels, and through InGaAs or wide bandgap InP vertical field spacers in the regrown S/D. Growing the FET channel by atomic layer epitaxy on the sidewall of a sacrificial ridged template will enable InGaAs/InAs finFETs of few nm channel thicknesses. Overview InAs and InGaAs have been recently and extensively studied for potential application in VLSI [1] [9] Interest is motivated by the high mobilities and high carrier injection velocities associated with these materials, parameters providing high transconductance and consequently the potential for high on currents at low power supply voltages. Yet, impact ionization, band band tunneling, and source/drain (S/D) tunneling leakage currents can be high because of low bandgaps and low electron effective mass; until recently [10] Ion (at specified low Ioff and VDD) had not approached or surpassed Si. If III V MOSFETs are to supplant silicon MOSFETs in VLSI, their leakage currents will have to be greatly reduced, to levels varying from 100nA/m for high performance (HP) logic to 30pA/m for low power (LP) logic. Such low leakage currents must be obtained at device dimensions consistent with the next few scaling generations of VLSI; implying gate lengths approach 7 15nm and source/drain contact pitches approaching 20 40nm. Given such tight dimension, reduction of leakage through use of large lateral gate drain spacers has little relevance to VLSI. Here we describe device designs for low leakage III V MOSFETs. In addition to benefiting FET electrostatics, extreme thinning the epitaxial InAs or InGaAs channel to 2 3nm increases the channel quantized bandgap, thereby also decreasing off state leakage arising from BTBT. Inserting undoped vertical spacers within the raised regrowth source/drain (S/D) reduces the otherwise extreme electric field in the gate drain region, reducing band to band tunneling (BTBT) leakage currents. InP, with its wider bandgap, is less prone to BTBT, but, with its higher electron effective mass, its extensive use within the FET channel will decrease the transconductance and on current; by judicious insertion of InP only in the regions of highest field concentration, leakage can be greatly reduced while minimizing the sacrifice in on current. III V MOSFET scaling limitations extend beyond leakage currents. Because of the low effective mass, collapse of mobility from surface roughness scattering in nm thick channels is a more serious challenge with In(Ga)As than with Si. FinFETs, necessary for scaling to very small Lg, demand very thin bodies of precisely controlled thickness, yet III V materials are prone to extreme damage when dry etched. By forming the III V fin by atomic layer epitaxial growth on the sidewall of a sacrificial ridged growth template, high damage dry etch processes are avoided, and fin thicknesses can be controlled by the number of ALE growth cycles. Results Figure 1 shows a schematic cross section of a recent device, and Figure 2 a TEM cross section of the channel. The FET has a 2.5 2.7nm thick InAs channel, a 1.0nm Al2O3/2.5nm ZrO2 gate dielectric [11] and 12nm undoped InGaAs vertical spacers in the raised regrown S/D. Transconductance (Figure 3) is high because of low InAs effective mass and thin channel and dielectric; off state leakage is moderately low (Figure 4) because of the vertical spacers and the strong quantization in the thin channel. Long channel FETs show 61 mV/dec. subthreshold swing S.S.(Figure 6) on current at 500mV VDD and 100nA/m Ioff (Figure 7) is 0.5mA/m, comparable to, or surpassing, leading [12] [13] Si finand nanowire FETs. Because of residual BTBT at negative Vgs, off current (Figure 4) in the FETs of Figure 1 meets the HP but not GP/LP/UPL ITRS requirements. Inserting (Figure 8) [14] raised plus recessed InP S/D spacers reduces off current (Figure 9) more than 10:1 at a given (Vgs Vth) our current efforts seek to minimize the sacrifice in on current through use of InP only in the regions of greatest electric field. Figure 10 illustrates finFET fabrication by atomic layer epitaxy [15] while Figure 11 is a TEM cross section of a 180nm height, 8nm thick InGaAs fin formed by this process. References [1] J. Lin et al. IEDM, p. 421 (2013) [2] T. W. Kim et al. IEDM, p.425 (2013) [3] S. W. Chang et al. IEDM, p.417 (2013) [4] S. Kim et al. IEDM, p.429 (2013) [5] S. Lee et al. APL, vol.103, p.233503 (2013) [6] D. H. Kim et al. IEDM, p.761 (2012) [7] J. J. Gu et al. IEDM, p.633 (2012) [8] M. Radosavljevic et al.,IEDM, p.319 (2009) [9] S. Lee et al. EDL, June 2014 [10] S. Lee et al. VLSI Symposium, June 2014. [11] V. Chobpattana et al. Appl. Phys. Lett. 104, 182912 (2014) [12] C. H. Jan et al. IEDM, p.44 (2012) [13] S. Bangsaruntip et al. IEDM, p.526 (2013) [14] C. Y. Huang et al. IEEE Lester Eastman Conference (2014) [15] D. Cohen Elias et al. IEEE DRC, June 2013. Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials, Tsukuba, 2014, 658 E 8 1 (Invited) pp658 659
author_names: Mark J W Rodwell

Seokbeom Lee

Cheng-Ying Huang

Doron Cohen Elias

Varistha Chobpattana

B J Thibeault

William J Mitchell

Susanne Stemmer

Arthur C Gossard
title: High Performance III V MOS Technologies
year: 2014

author_names: Yinlei Zhang

James S Speck
title: Importance of shallow hydrogenic dopants and material purity of ultra wide bandgap semiconductors for vertical power electron devices
year: 2020

abstract: GaN vertical power FinFETs are promising high voltage switches for the next generation of high frequency power electronics applications. Thanks to a vertical fin channel, the device offers excellent electrostatic and threshold voltage control, eliminating the need for epitaxial regrowth 1 or p type doping 2 unlike other vertical GaN power transistors. Vertical GaN FinFETs with 1200 V breakdown voltage (BV) 5 A current rating and excellent switching figure of merit have been demonstrated recently on free standing GaN substrates 3 Despite this promising performance, the commercialization of these devices has been limited by the high cost $50 $100/cm 2 and small diameter 2 inch) of free standing GaN substrates. The use of GaN on Si wafers could reduce the substrate cost by x1000, however the growth of the thick ~10 mm or thicker) drift layers required for kV class applications is extremely challenging on Si. Alternatively, GaN grown on engineered substrates (QST (r) with a matched thermal expansion coefficient could enable low cost vertical GaN FinFETs with thick >10 mm) drift layers and large wafer diameters (8 12 inch) In this work, we demonstrate GaN power FinFETs on engineered substrates for the first time.
author_names: Ahmad Zubair

Josh Perozek

John Niroula

Ozgur Aktas

Vladimir Odnoblyudov

Tomas Palacios
title: First Demonstration of GaN Vertical Power FinFETs on Engineered Substrate
venue: 2020 Device Research Conference (DRC)
year: 2020

abstract: This letter presents the first experimental study on capacitances, charges, and power switching figure of merits (FOM) for a large area vertical GaN power transistor. A 1.2 kV, 5 A GaN vertical power FinFET was demonstrated in a chip area of 0.45 mm2, with a specific on resistance of 2.1 \text{m}\Omega \cdot \textsf {cm}\textsf {2} and a threshold voltage of 1.3 V. Device junction capacitances were characterized and their main components were identified. This was used to calculate the switching charges and practical switching frequencies. Device FOMs were then derived that take into account the trade offs between the conduction and switching power losses. Our GaN vertical FinFETs exhibit high frequency ~MHz) switching capabilities and superior switching FOMs when compared with commercial 0.9 1.2 kV Si and SiC power transistors. This letter shows the great potential of GaN vertical FinFETs for next generation medium voltage power electronics.
author_names: Yuhao Zhang

Min-Chul Sun

Josh Perozek

Zhihong Liu

Ahmad Zubair

Daniel Piedra

Nadim Chowdhury

Xiang Gao

Kenneth L Shepard

Tomas Palacios
title: Large Area 1.2 kV GaN Vertical Power FinFETs With a Record Switching Figure of Merit
venue: IEEE Electron Device Letters
year: 2019

abstract: This work studies the leakage and breakdown mechanisms of 1.2 kV GaN vertical power FinFETs with edge termination. Two competing leakage and breakdown mechanisms have been identified. The first mechanism is dominated by the electric field, with the leakage current dominated by the electric field in the drift region and destructive breakdown voltage by the peak electric field at the edge termination. The second leakage and breakdown mechanism is controlled by an energy (or potential) barrier in the fin channel. This energy barrier suffers from the drain induced barrier lowering (DIBL) effect and is highly dependent on gate/drain biases, fin geometries, and GaN/oxide interface charges. The electrons injected into the drift region due to the DIBL effect further lead to trap assisted space charge limited conduction, which results in a nondestructive early breakdown. The barrier height in the fin channel determines which mechanism is dominant; the same device could show either destructive or nondestructive breakdown at different gate biases. To enable the normally off power switching, it is important to suppress the leakage from the second mechanism and maintain a sufficiently high energy barrier in the fin channel up to high drain voltages. Finally, the key device parameters determining the energy barrier in the fin channel have been identified. The findings in this work provide critical device understanding and design guidelines for GaN vertical power FinFETs and other "junctionless" vertical high voltage power transistors.This work studies the leakage and breakdown mechanisms of 1.2 kV GaN vertical power FinFETs with edge termination. Two competing leakage and breakdown mechanisms have been identified. The first mechanism is dominated by the electric field, with the leakage current dominated by the electric field in the drift region and destructive breakdown voltage by the peak electric field at the edge termination. The second leakage and breakdown mechanism is controlled by an energy (or potential) barrier in the fin channel. This energy barrier suffers from the drain induced barrier lowering (DIBL) effect and is highly dependent on gate/drain biases, fin geometries, and GaN/oxide interface charges. The electrons injected into the drift region due to the DIBL effect further lead to trap assisted space charge limited conduction, which results in a nondestructive early breakdown. The barrier height in the fin channel determines which mechanism is dominant; the same device could show either destructive or nondestructive bre.
author_names: Ming Xiao

Xiang Gao

Tomas Palacios

Yuhao Zhang
title: Leakage and breakdown mechanisms of GaN vertical power FinFETs
venue: Applied Physics Letters
year: 2019

abstract: This paper presents the first analytical model for the ON resistance <inline formula> <tex math notation="LaTeX"{R}_{ \mathrm{\scriptscriptstyle ON} /tex math>/inline formula> in vertical power FinFETs. The model allows to extract the channel mobility and series resistance and to separate the current conduction through the bulk fin channel and the accumulation mode metal oxide semiconductor (MOS) channel. The model was validated by experiments and simulations. The extracted series resistance was verified by measuring a diode fabricated in the same wafer with the FinFETs. At the same time, simulations using the extracted channel mobility and series resistance agreed well with the experiments. The model was then used to analyze a 1200 V GaN vertical power FinFET. The main <inline formula> <tex math notation="LaTeX"{R}_{ \mathrm{\scriptscriptstyle ON} /tex math>/inline formula> component was identified to be from the drift layer and the substrate, while the gate modulated channel resistance only accounts for ~13% of the total device <inline formula> <tex math notation="LaTeX"{R}_{ \mathrm{\scriptscriptstyle ON} /tex math>/inline formula> Our model enables parameter extraction from the dc characteristics of a single device, and therefore, provides a fast and easy way to understand, analyze, and design vertical power FinFETs. Our model can also be adjusted to allow for fast and accurate parameter extraction in other power transistors with a vertical gate modulated channel, such as trench MOSFETs.
author_names: Ming Xiao

Tomas Palacios

Yuhao Zhang
title: ON Resistance in Vertical Power FinFETs
venue: IEEE Transactions on Electron Devices
year: 2019

abstract: As a promising ultra wide bandgap semiconductor, the <italic>b</italic> phase of Ga<sub>2</sub>O<sub>3</sub> has attracted more and more interest in the field of power electronics due to its ultra wide bandgap (4.8 eV) high theoretical breakdown electric field (8 MV/cm) and large Baliga's figure of merit, which is deemed as a potential candidate for next generation high power electronics, including diodes, field effect transistors (FETs) etc. In this article, we introduce the basic material properties of Ga<sub>2</sub>O<sub>3</sub> and review the recent progress and advances of <italic>b</italic> Ga<sub>2</sub>O<sub>3</sub> based metal oxide semiconductor field effect transistors <sc>mosfet</sc>s) Due to the problematic p type doping technology up to now, the enhancement mode (E mode) <italic>b</italic> Ga<sub>2</sub>O<sub>3</sub> FETs face more difficulties, compared with depletion mode (D mode) This article focuses on reviewing the recent progress of E mode Ga<sub>2</sub>O<sub>3</sub> <sc>mosfet</sc>s, summarizing and comparing various feasible solutions when p type doping is absent. Furthermore, the device fabrication and performances of state of art <italic>b</italic> Ga<sub>2</sub>O<sub>3</sub> <sc>mosfet</sc>s, including D mode, E mode, and planar/vertical structure are fully discussed and compared, as well as potential solutions to the challenges of Ga<sub>2</sub>O<sub>3</sub> FETs.
author_names: Hongpeng Zhang

Lei Yuan

Jichao Hu

Yuming Zhang

Renxu Jia
title: Progress of Ultra Wide Bandgap Ga2O3 Semiconductor Materials in Power MOSFETs
venue: IEEE Transactions on Power Electronics
year: 2020

abstract: Wireless power transfer systems and plasma generators are among the increasing number of applications that use high frequency power converters. Increasing switching frequency can reduce the energy storage requirements of the passive elements that can lead to higher power densities or even the elimination of magnetic cores. However, operating at higher frequencies requires faster switching devices in packages with low parasitics. Wide bandgap (WBG) power devices, such as gallium nitride (GaN) and silicon carbide (SiC) devices, have high critical fields and high thermal conductivity that make them good candidates for efficient high voltage and high frequency operations. Commercially available GaN and SiC devices have ratings targeting different applications. Lateral GaN devices dominate in lower voltage <650 V) and high frequency applications as they have relatively small device capacitances <inline formula><tex math notation="LaTeX"$C_{\text{oss},C_{\text{iss}/tex math>/inline formula> which make them easy to drive at high frequencies. On the other hand, vertical SiC devices are often used in high voltage and low frequency applications since they have higher blocking voltages and larger gate charge than their GaN counterparts. As a result, SiC devices usually require high power and complicated gate drive circuitry. Recent work shows that in both GaN and SiC devices, losses in device <inline formula><tex math notation="LaTeX"$C_{\text{oss}/tex math>/inline formula> can exceed the conduction losses at high switching frequencies and relatively high voltages under zero voltage switching conditions. Moreover, the <inline formula><tex math notation="LaTeX"$C_{\text{oss}/tex math>/inline formula> energy loss <inline formula><tex math notation="LaTeX"$E_{\text{oss}/tex math>/inline formula> per switching cycle increases with frequency in GaN devices but remains roughly independent of frequency in SiC devices. This means that at high frequencies, SiC devices can be preferable due to their smaller <inline formula><tex math notation="LaTeX"$C_{\text{oss}/tex math>/inline formula> energy loss even when taking into consideration the complexity of the gate drive circuit. In this article, we present a WBG high voltage cascode GaN/SiC power device, combining the advantages of both a GaN and an SiC device namely, simple gate drive requirements, <inline formula><tex math notation="LaTeX"$E_{\text{oss}/tex math>/inline formula> loss per cycle roughly independent of frequency, and relatively high voltage blocking capability. Comparing this cascode GaN/SiC device with an SiC <sc>mosfet</sc> and a SiC junction gate field effect transistor of similar voltage ratings and <inline formula><tex math notation="LaTeX"$R_{ds,\text{ON}/tex math>/inline formula> we find that the inverter using the cascode GaN/SiC device has the highest efficiency and simplest auxiliary gate drive circuitry. Finally, integrating the cascode GaN/SiC device has the potential benefits of achieving lower <inline formula><tex math notation="LaTeX"$C_{\text{oss}/tex math>/inline formula> losses, higher device ratings, and better heat removal capability.
author_names: Jiale Xu

Lei Gu

Zhechi Ye

Saleh Kargarrazi

Juan Manuel Rivas-Davila
title: Cascode GaN/SiC: A Wide Bandgap Heterogenous Power Device for High Frequency Applications
venue: IEEE Transactions on Power Electronics
year: 2020