Query: MOS (Metal Oxide Semiconductor) Physics and Technology

Candidate papers:

abstract: Introduction. Field Effect. Metal Oxide Silicon Capacitor at Low Frequencies. Metal Oxide Silicon Capacitor at Intermediate and High Frequencies. Extraction of Interface Trap Properties from the Conductance. Interfacial Nonuniformities. Experimental Evidence for Interface Trap Properties. Extraction of Interface Trap Properties from the Capacitance. Measurement of Silicon Properties. Charges, Barrier Heights, and Flatband Voltage. Charge Trapping in the Oxide. Instrumentation for Measuring Capacitor Characteristics. Oxidation of Silicon Oxidation Kinetics. Oxidation of Silicon Technology. Control of Oxide Charges. Models of the Interface. Appendices. Subject Index. Symbol Index.
author_names: Edward H Nicollian

John Brews
title: Mos (Metal Oxide Semiconductor) Physics and Technology
year: 1982

abstract: (1986) MOS (Metal Oxide Semiconductor) Physics and Technology. Nuclear Technology: Vol. 74, No. 2, pp. 235 237.
author_names: Ahmed R Wazzan
title: MOS (Metal Oxide Semiconductor) Physics and Technology
year: 1986

author_names: K J S Cave
title: MOS (Metal Oxide Semiconductor) Physics and Technology
year: 1983

abstract: A sustainable energy future requires power electronics that can enable significantly higher efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide (4H SiC) is one of the most technologically advanced wide bandgap semiconductor that can outperform conventional silicon in terms of power handling, maximum operating temperature, and power conversion efficiency in power modules. While SiC Schottky diode is a mature technology, SiC power Metal Oxide Semiconductor Field Effect Transistors are relatively novel and there is large room for performance improvement. Specifically, major initiatives are under way to improve the inversion channel mobility and gate oxide stability in order to further reduce the on resistance and enhance the gate reliability. Both problems relate to the defects near the SiO2/SiC interface, which have been the focus of intensive studies for more than a decade. Here we review research on the SiC MOS physics and technology, including its brief history, the state of art, and the latest progress in this field. We focus on the two main scientific problems, namely, low channel mobility and bias temperature instability. The possible mechanisms behind these issues are discussed at the device physics level as well as the atomic scale, with the support of published physical analysis and theoretical studies results. Some of the most exciting recent progress in interface engineering for improving the channel mobility and fundamental understanding of channel transport is reviewed.
author_names: Gang Liu

Blair R Tuttle

Sarit Dhar
title: Silicon carbide: A unique platform for metal oxide semiconductor physics
year: 2015

abstract: Metal oxide semiconductor (MOS) field effect transistor (FET) scaling is following the prediction of the Moore's law for the past 45 years, a key factor that enabled the IC industry to cope with the everlasting demand for higher performances. However, this scaling process becomes increasingly difficult as several limits from both process and device capabilities pop up as the technology node reaches 28nm and beyond. To stand the pace of downscaling, non classical devices are currently introduced in the roadmap. In this context, the junctionless FET is part of these attempts. It is a new emerging device that can potentially withstand the downscaling of CMOS technology as it still has an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes. This dissertation focuses on the physics and modeling of nanoscale junctionless double gate MOSFET and junctionless nanowire FETs. The first part of the thesis is focusing on junctionless transistors by discussing the advantages and limitations of such technology. A brief overview of existing models and the current status of symmetrical/asymmetrical operation of junctionless FETs in a planar double gate configuration as well as junctionless nanowires topologies will be presented. Next, the model that is developed in this thesis is detailed in different chapter, each of which will cover a specific aspect. The model relies on Poisson Boltzmann equation and on the drift diffusion transport to derive charges and current in long channel devices. It is based on two set of relationships to cover all the operating regions: from depletion to accumulation; from linear to saturation with no fitting parameter. Following a core analysis, more features are developed and added to the ideal long channel concept. This includes modeling short channel effects and DIBL, modeling full trans capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off state currents. Importantly, we have shown that equivalent symmetric devices could also be used to simulate asymmetric operation, which are likely to be the most common situation. In addition, the charge based approach developed along the thesis has also been generalized to the quite popular junctionless nanowire architecture. Regarding junctionless FETs, technological parameter are very critical. For instance, the device cannot be made of any dimension and doping otherwise it cannot be effectively switched off at a given current. Therefore, we also derived rules providing a design space tool with explicit links between silicon thickness and doping ensuring safe operation. Finally, since the mobility extraction in junctionless FETs is still an issue, we have developed a new method for a reliable measurement of free carriers mobility in real devices which does not assume any predefined mobility law. Based on these developments, the EPFL JL model was implemented into Hspice platforms to be used by circuit designers.
author_names: Farzan Jazaeri
title: Modeling Junctionless Metal Oxide Semiconductor Field Effect Transistor
year: 2015

abstract: This paper reports recent advances related to the piezoelectric oxide semiconductor field effect transistor (POS FET) based touch sensing system research. We reported in past, the POSFETs with basic electronics realized on planar silicon substrates using CMOS technology. However, the planar POSFETs could not be used on 3D or curved surfaces such as the fingertip of a robot. To overcome this challenge we are now investigating the ultra thin chip approach for obtaining bendable POSFETs tactile sensing array. This paper presents this approach towards obtaining bendable POSFETs. Furthermore, for the first time the theoretical behavior of POSFETs devices are examined by combining the piezoelectric capacitor model proposed and the physics of underlying metal oxide semiconductor (MOS) FETs in the linear and saturation regions. The device characteristic equations are simulated using MATLAB and comparable matching is achieved with the experimental measurements. The model result gives a unique insight into geometrical and material properties of piezoelectric polymer on the electrical properties of transistor for flexible electronics applications. Using this model, the Spice simulation of POSFET device in a single ended op amp configuration, and the effect of chip thickness on deflection are presented.
author_names: Shoubhik Gupta

Hadi Heidari

Leandro Lorenzelli

Ravinder S Dahiya
title: Towards bendable piezoelectric oxide semiconductor field effect transistor based touch sensor
venue: 2016 IEEE International Symposium on Circuits and Systems (ISCAS)
year: 2016

abstract: The introduction of lattice strain in impact ionization metal oxide semiconductor (I MOS) transistors for performance enhancement is reported. Lattice strain affects impact ionization and its impact on device performance is explained in relation to the physics of I MOS device operation. By integrating epitaxial silicon carbon (Si0.99C0.01) source and drain regions in a complementary MOS compatible fabrication process, strained n channel I MOS devices were fabricated. Tensile strain in the channel and impact ionization regions contributes to enhanced electron transport and device characteristics. The strained I MOS technology demonstrates an excellent subthreshold swing of 5.3mV/decade at room temperature. Compared to control I MOS devices with Si raised source/drain, strained I MOS devices show significantly higher drive current and a steeper subthreshold swing.
author_names: Eng Huat Toh

Grace Huiqi Wang

G Q Lo

Lap Chan

Ganesh S Samudra

Yee-Chia Yeo
title: Performance enhancement of n channel impact ionization metal oxide semiconductor transistor by strain engineering
year: 2007

abstract: In this paper, we present a new compact drain current model for double gate or triple gate silicon on insulator (SOI) metal oxide semiconductor field effect transistors, which is based on a physics based 3 D analysis. Explicit analytical model equations for the height of the potential barrier are derived in closed form from a 3 D model for the channel electrostatics without the need to introduce any fitting parameter. The device current is described by a superposition of a surface channel current above threshold and a center current in the subthreshold region, accounting for the movement of the most leaky path in the device cross section. Comparison with Technology Computer Aided Design (TCAD) shows a good scalability of the model down to a gate length of 30 nm. Furthermore, the I V characteristics are compared with measurements and obtain accurate results down to an effective channel length of 53 nm.
author_names: Alexander Kloes

Mike Schwarz

Thomas Holtij
title: \hbox{MOS}{3} A New Physics Based Explicit Compact Model for Lightly Doped Short Channel Triple Gate SOI MOSFETs
venue: IEEE Transactions on Electron Devices
year: 2012

abstract: Atomic layer deposition ALD grown Al2O3 has excellent bulk and interface properties on III V compound semiconductors and is used as gate dielectric for GaAs and GaN metal oxide semiconductor field effect transistors MOSFETs The low temperature LT ALD technology enables us to fabricate 100 nm MOS structures on GaAs, defined by nanoimprint lithography. The electrical characterization of these nanostructured dielectrics demonstrates that the bulk oxide films and the oxide GaAs interfaces are of high quality even in nanometer scale. The submicron gate length GaAs MOSFET formed by LT ALD and lift off process shows well behaved transistor characteristics. This GaAs MOSFET process is ready to scale the gate length below 100 nm for ultra high speed or THz transistor applications. (c) 2005 American Institute of Physics. DOI: 10.1063/1.1954902
author_names: P D Yea
title: Formation and characterization of nanometer scale metal oxide semiconductor structures on GaAs using low temperature atomic layer deposition
year: 2005

abstract: MOS Physics and Technology: E. H. NICOLLIAN J. R. BREWS (J. Wiley, 1982,899 pp. PS51.75) A book of nearly 900 pages on the MOS system which does not quite arrive at the MOS transistor or integrated circuits sound as though it must be rather wordy. I suppose it is, but the words are very good. What we have here is a very detailed analysis ofthe metal oxide semiconductor structure which contains all the physics needed to understand the fine detail of MOS transistor characteristics and performance, coupled with a description of all the applications of MOS measurements to material assessment. The third major component of the book is more technological in nature and is concerned with the kinetics of oxide growth on silicon and the means of controlling oxide quality and particularly oxide charge. This section contains almost all one needs to know in order to make MOS transistors and integrated circuits. The analysis of the MOS structure is both very detailed and very fully explained hence the large number of words. However, this is justifiable because the substance is difficult to understand and presents more serious problems to the student than the bipolar transistor. Applications ofthe analysis include the determination of interface trap concentrations and distributions, and of their response times when the potential is changed, and of non uniformities in their distribution. Also included are measurements on the underlying semiconductor such as dopant distribution and minority carrier lifetime. There is a chapter on the instrumentation needed for these measurements. This is a very good book; it is easy to read and it is also precise. I don't know who will read it at this price, but I still think it is worth the money. DAVID C. NORTHROP, Department ofElectrical Engineering and Electronics. UMIST.
author_names: David C Northrop
title: Book Review: MOS Physics and Technology
year: 1983