Query: A Novel Scalable Energy-Efficient Synaptic Device: Crossbar Ferroelectric Semiconductor Junction

Candidate papers:

abstract: A novel ferroelectric semiconductor junction (FSJ) based two terminal memristor is demonstrated as a synaptic device for the first time. In this novel FSJ device, a metal ferroelectric semiconductor (FS) metal crossbar structure is used, instead of a metal ferroelectric insulator metal structure for a conventional ferroelectric tunnel junction (FTJ) so that an ultra thin ferroelectric insulator is not required. Meanwhile, the FSJ also offers energy efficiency advantage over the conventional filament based resistive random access memory (RRAM) device because the conductance of the FSJ scales with the junction area. Experimentally, a ferroelectric semiconductor a In2Se3 based crossbar FSJ (c FSJ) as a synaptic device is demonstrated. Ferroelectric resistive switching is clearly observed in both planar FSJ (p FSJ) by in plane polarization switching and c FSJ by out of plane polarization switching. Conductance potentiation and depression in the c FSJ are measured and benchmarked at both original size and projected to 32 nm node with different synaptic devices. a In2Se3 c FSJ shows good on line learning accuracy ~92 low latency and energy consumption due to the short write pulse width and large RON.
author_names: Mengwei Si

Peide D Ye

Y Luo

Wonil Chung

Hagyoul Bae

Dongqi Zheng

Jinjun Li

Jingkai Qin

Gang Qiu

S Yu
title: A Novel Scalable Energy Efficient Synaptic Device: Crossbar Ferroelectric Semiconductor Junction
venue: 2019 IEEE International Electron Devices Meeting (IEDM)
year: 2019

abstract: We report on world's smallest HfO2 based Resistive RAM (RRAM) cell to date, featuring a novel Hf/HfOx resistive element stack, with an area of less than 10x10 nm2, fast ns range on/off switching times at low voltages and with a switching energy per bit of #60;0.1pJ. With excellent endurance of more than 5.107cycles, large on/off verified window >50) no closure of the on/off window after 30hrs/200C and failure free device operation after 30hrs/250C thermal stress, the major device level nonvolatile memory requirements are met. Furthermore, we clarify the impact of film crystallinity on cell operation from a scalability viewpoint, the role of the cap layer and bring insight into the switching mechanisms.
author_names: Bogdan Govoreanu

G S Kar

Y -Y Chen

V Paraschiv

S Kubicek

Andrea Fantini

Iuliana P Radu

Ludovic Goux

Sergiu Clima

Robin Degraeve

Nico Jossart

Olivier Richard

T Vandeweyer

Kang Kuk Seo

Paul Hendrickx

Geoffrey Pourtois

Hugo Bender

Laith Altimime

Dirk J Wouters

Jorge A Kittl

Malgorzata Jurczak
title: 10x10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low energy operation
venue: 2011 International Electron Devices Meeting
year: 2011

abstract: A memristor is a two terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon based memristor device and show that a hybrid system composed of complementary metal oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.
author_names: Sung-Hyun Jo

Ting Chang

Idongesit E Ebong

Bhavitavya Bhadviya

Pinaki Mazumder

Wei Yang Lu
title: Nanoscale memristor device as synapse in neuromorphic systems.
venue: Nano letters
year: 2010

abstract: We demonstrate large scale (1 kb) high density crossbar arrays using a Si based memristive system. A two terminal hysteretic resistive switch (memristive device) is formed at each crosspoint of the array and can be addressed with high yield and ON/OFF ratio. The crossbar array can be implemented as either a resistive random access memory (RRAM) or a write once type memory depending on the device configuration. The demonstration of large scale crossbar arrays with excellent reproducibility and reliability also facilitates further studies on hybrid nano/CMOS systems.
author_names: Sung-Hyun Jo

Kuk-Hwan Kim

Wei Lu
title: High density crossbar arrays based on a Si memristive system.
venue: Nano letters
year: 2009

abstract: In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain inspired computing. Performance metrics desirable for large scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented.
author_names: Duygu Kuzum

Shimeng Yu

H -S Philip Wong
title: Synaptic electronics: materials, devices and applications.
venue: Nanotechnology
year: 2013

abstract: In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e. offer steeper subthreshold swings) (ii) are CMOS compatible, (iii) have multiple operating modes (i.e. I V characteristics can also enable compact, 1 transistor, non volatile storage elements, as well as analog synaptic behavior) and (iv) have been experimentally demonstrated (i.e. with respect to all of the aforementioned operating modes) These device level characteristics offer unique opportunities at the circuit, architectural, and system level, and are considered here from device, circuit/architecture, and foundry level perspectives.
author_names: Ahmedullah Aziz

Evelyn T Breyer

An Chen

Xiaoming Chen

Suman Datta

Sumeet Kumar Gupta

Michael Hoffmann

Xiaobo Sharon Hu

Adrian M Ionescu

Matthew Jerry

Thomas Mikolajick

Halid Mulaosmanovic

Kai Ni

Michael Thaddeus Niemier

Ian O'Connor

Atanu K Saha

Stefan Slesazeck

Sandeep Krishna Thirumala

Xunzhao Yin
title: Computing with ferroelectric FETs: Devices, models, systems, and applications
venue: 2018 Design, Automation Test in Europe Conference Exhibition (DATE)
year: 2018

abstract: Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin torque transfer memory (STT RAM, or MRAM) phase change random access memory (PCRAM) and resistive random access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency optimized caches to highly density optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture level NVM related studies.
author_names: Xiangyu Dong

Cong Xu

Yuan Xie

Norman P Jouppi
title: NVSim: A Circuit Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
venue: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
year: 2012

abstract: Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance.
author_names: Sukru Burc Eryilmaz

Duygu Kuzum

Rakesh Gnana David Jeyasingh

Sangbum Kim

Matthew J BrightSky

Chung Hon Lam

H -S Philip Wong
title: Brain like associative learning using a nanoscale non volatile phase change synaptic device array
venue: Front. Neurosci.
year: 2014

abstract: Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low energy, high endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.
author_names: Jianhua Joshua Yang

Dmitri B Strukov

Duncan R Stewart
title: Memristive devices for computing.
venue: Nature nanotechnology
year: 2013

abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high field transport model, and SiGe base bipolar devices.
author_names: Yuan Taur

Tak H Ning
title: Fundamentals of Modern VLSI Devices
year: 1998