Query: capacitor design for ESD protection

Candidate papers:

abstract: The RC based power rail ESD clamp circuit with the n channel metal oxide semiconductor (NMOS) transistor drawn in the layout style of big field effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD transient detection circuit can be greatly reduced by more than 54% as compared to the traditional RC based ESD transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD transient detection circuit with adjustable holding voltage can achieve long enough turn on duration under the ESD stress condition, as well as better immunity against mistrigger and transient induced latch on event under the fast power on and transient noise conditions.
author_names: Chih-Ting Yeh

Ming-Dou Ker
title: Capacitor Less Design of Power Rail ESD Clamp Circuit With Adjustable Holding Voltage for On Chip ESD Protection
venue: IEEE Journal of Solid State Circuits
year: 2010

abstract: This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single pole ten throw (SP10T) transmit/receive (T/R) switch for quad band (0.85/0.9/1.8/1.9 GHz) GSM and multiple band WCDMA smartphones. Implemented in a 0.18 mm SOI CMOS, this SP10T employs a series shunt topology for the time division duplex (TDD) transmitting (Tx) and receiving (Rx) and frequency division duplex (FDD) transmitting/receiving (TRx) branches to handle the high GSM transmitter power. The measured P0.1 dB, insertion loss and Tx Rx isolation in the lower/upper bands are 36.4/34.2 dBm, 0.48/0.81 dB and 43/40 dB, respectively, comparable to commercial products with no/little ESD protection in high cost SOS and GaAs technologies. Feed forward capacitor (FFC) and AC floating bias techniques are used to further improve the linearity. An ESD switch co design technique is developed that enables simultaneous whole chip design optimization for both ESD protection and SP10T circuits.
author_names: X Shawn Wang

Xiao-fan Wang

Fei Lu

Chen Zhang

Zongyu Dong

Lisha Wang

Rui Ma

Zitao Shi

Albert Z Wang

M Frank Chang

Dawn Wang

Alvin J Joseph

C Patrick Yue
title: Concurrent Design Analysis of High Linearity SP10T Switch With 8.5 kV ESD Protection
venue: IEEE Journal of Solid State Circuits
year: 2014

abstract: This paper presents two 60 GHz low noise amplifiers (LNAs) with different electrostatic (ESD) protection schemes, including the diode based and LC based configurations. By codesigning ESD network and input matching, both LNAs are optimized for minimum noise figure (NF) while maintaining a similar gain. Compared with the conventional double diode approach, the proposed LC based design uses a high current capability spiral inductor and a high breakdown voltage metal oxide metal capacitor as effective bidirectional ESD protection, showing much improved ESD protection level and NF under reduced power consumption. The test results demonstrate an over 8 kV human body model ESD level and an over 13 A very fast transmission line pulse current level for charge device model ESD protection. The measured NF and power gain are 5.3 dB and 17.5 dB, respectively, at 58 GHz, under a power consumption of only 18 mW. To the best of our knowledge, the LC based ESD protected LNA demonstrates a highest ESD protection level with a lowest NF, compared with prior arts operating at similar frequencies.
author_names: Ming-Hsien Tsai

Shawn S H Hsu

Fu-Lung Hsueh

Chewnpu Jou

Tzu-Jin Yeh
title: Design of 60 GHz Low Noise Amplifiers With Low NF and Robust ESD Protection in 65 nm CMOS
venue: IEEE Transactions on Microwave Theory and Techniques
year: 2013

abstract: ESD protection structure for vertical NPN transistor in a 5 V 0.6 mm BiCMOS process was designed.A modified self triggered ESD protection structure with P+/N well diode was proposed to solve the problem of high triggering voltage in traditional self triggered ESD structure for vertical NPN device.Parasitic collector base capacitance and PN junction capacitance were used as capacitor coupler.Test results indicated that triggering voltage of the protection structure could be effectively reduced,and its protection level exceeded 4 kV human body model.
author_names: Gu Xiaofeng
title: Design and Analysis of ESD Protection Structure for Vertical NPN Transistors
year: 2012

abstract: By the electrostatic discharge (ESD)/matching co design methodology, a wideband low noise amplifier (LNA) using a grounded spiral inductor in conjunction with a MOM capacitor for ESD protection and wideband matching is demonstrated in a 65 nm CMOS. The shunt inductor provides an effective bidirectional ESD protection to the ground and the series capacitor greatly enhances the breakdown level in the current discharge path. The measurement results demonstrate an over 8 kV human body model ESD protection level with almost no RF characteristic degradation after ESD zapping. Under a power consumption of 5.6 mW, the ESD protected LNA presents a flat NF and power gain of 3.3 3.9 dB and 16.6 17.9 dB, respectively, in the frequency range of 18.5 24.5 GHz, and a 3 dB bandwidth of 17.5 26 GHz is achieved.
author_names: Ming-Hsien Tsai

Shawn S H Hsu

Fu-Lung Hsueh

Chewnpu Jou

Tzu-Jin Yeh
title: A 17.5 26 GHz Low Noise Amplifier With Over 8 kV ESD Protection in 65 nm CMOS
venue: IEEE Microwave and Wireless Components Letters
year: 2012

abstract: This paper presents an ESD protected V band (f0 at 58 GHz) low noise amplifier (LNA) in 65 nm CMOS. Instead of using the conventional diode based RF ESD design, a high current capability spiral inductor and a high breakdown MOM capacitor are employed as effective bi directional ESD protection network, and also as part of the input matching by the co design approach. The measured results demonstrate an over 8 kV HBM ESD protection level with a NF of 5.3 dB and a power gain of 17.5 dB at 58 GHz, under a power consumption of 18 mW. To our best knowledge, this LNA presents a highest ESD protection level and a lowest NF, compared with prior arts in a similar frequency range.
author_names: Ming-Hsien Tsai

Shawn S H Hsu

Tzu-Jin Yeh

Chewnpu Jou

Fu-Lung Hsueh
title: A V band low noise amplifier with 5.3 dB NF and over 8 kV ESD protection in 65 nm RF CMOS
venue: 2012 IEEE/MTT S International Microwave Symposium Digest
year: 2012

abstract: Capacitor couple technique used to lower snapback trigger voltage and to ensure uniform ESD current distribution in deep submicron CMOS on chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire bonding metal pad without increasing extra layout area to the pad. A timing original design model has been derived to calculate the capacitor couple efficiency of this proposed ESD protection circuit. Using this capacitor couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep submicron low voltage CMOS ASIC can be effectively protected.
author_names: Ming-Dou Ker

Chung-Yu Wu

Tao Cheng

Hun-Hsien Chang
title: Capacitor couple ESD protection circuit for deep submicron low voltage CMOS ASIC
venue: IEEE Trans. Very Large Scale Integr. Syst.
year: 1996

abstract: A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35 mm Bipolar CMOS DMOS (BCD) process. The proposed ESD clamp has a non snapback characteristic because of gate coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100 ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC triggered NMOS ESD clamp circuit.
author_names: Jae-Young Park

Dae-Woo Kim

Young-Sang Son

Jong-Kyu Song

Chang-Soo Jang

Won-Young Jung
title: A Non snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 um Bipolar CMOS DMOS Process
venue: IEICE Trans. Electron.
year: 2011

abstract: A design model is proposed to exactly simulate operating principles of gate coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor C/sub n/ and coupling resistor R/sub n/ can be calculated to improve the efficiency of GCNMOS ESD protection circuit.
author_names: Wang Yuan

Jia Song

Chen Zhongjian

Zhang Gang-gang

Ji Lijiu
title: A design model of gate coupling NMOS ESD protection circuit
venue: Proceedings. 7th International Conference on Solid State and Integrated Circuits Technology, 2004.
year: 2004

abstract: The RF junction varactors are employed as electro static discharge (ESD) protection devices and co designed with 60 GHz low noise amplifier (LNA) fabricated in a 65 nm CMOS technology. The junction varactor acts as an ESD diode to bypass ESD current during ESD zapping, and also utilized as a capacitor to be a part of input matching network of the LNA in normal RF operation. By transmission line pulse (TLP) measurement, the ESD protection capabilities of RF junction varactors are characterized with different device parameters. The experimental results demonstrate excellent second breakdown currents (It2) and high ratios of the ESD levels to parasitic capacitances (VESD/CESD) With ESD/matching co design methodology, the ESD protected LNA demonstrates a second breakdown current It2 of 1.4 A, corresponding to a 2 kV human body model (HBM) ESD protection level with a noise figure (NF) of 6.6 dB and a peak gain of 16.5 dB at 60 GHz under a power consumption of only 28 mW.
author_names: Ming-Hsien Tsai

Sing-Kai Huang

Shawn S H Hsu
title: Electro Static Discharge Protection Design for V Band Low Noise Amplifier Using Radio Frequency Junction Varactor (Special Issue Solid State Devices and Materials)
year: 2013