Query: rework in semiconductor manufacturing

Candidate papers:

abstract: We develop an open queueing network model for rapid performance analysis of semiconductor manufacturing facilities. While the use of queueing models for performance evaluation of manufacturing systems is not new, our approach differs from others in the detailed ways in which we model the different tool groups found in semiconductor wafer fabrication, as well as the way in which we characterize the effect of rework and scrap on wafer lot sizes. As an application of the model, we describe a method for performing tool planning for semiconductor lines. The method is based on a marginal allocation procedure which uses performance estimates from the queueing network model to determine the number of tools needed to achieve a target cycle time, with the objective being to minimize overall equipment cost.
author_names: Daniel P Connors

Gerald E Feigin

David D Yao
title: A queueing network model for semiconductor manufacturing
year: 1996

abstract: Simulating semiconductor manufacturing lines is necessary in order to understand how various factors interact to affect the performance of these complex lines. The author reports on the effects of the commonly made assumptions of no rework, representing rework by increasing process times, no operator constraints, and no machine failures. The author uses a detailed, flexible model in which the assumptions may or may not be made. The base case, validated for a real line, makes none of the simplifying assumptions listed and is compared with subsequent runs making each assumption in turn. Generally, performance is degraded. In some cases the performance measures (resources utilization, work in process, and cycle times) remain within 20% of the base case.<ETX>
author_names: Sarah J Hood
title: Detail vs. simplifying assumptions for simulating semiconductor manufacturing lines
venue: Ninth IEEE/CHMT International Symposium on Electronic Manufacturing Technology,Competitive Manufacturing for the Next Decade
year: 1990

abstract: Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in die on device as etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM) Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO) A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per device and per layer basis, the optical target overlay at DI is compared with SEM on device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.
author_names: Honggoo Lee

Sangjun Han

Young-Sik Kim

Myoungsoo Kim

Hoyoung Heo

Sanghuck Jeon

Dongsub Choi

Jeremy S Nabeth

Irina Brinster

Bill Pierson

John C Robinson
title: Device overlay method for high volume manufacturing
venue: SPIE Advanced Lithography
year: 2016

abstract: The present invention provides an exposure method that do not need to perform rework in accordance with the test results, such as at the time of lithography the displacement can suppress a decrease in yield. To this end, the present invention, the step of forming a photosensitive film on a main surface of the semiconductor substrate (S101) the process (S102) for transferring the semiconductor substrate to the device, select the check mark on the mask to the light shielding film exposing the photosensitive film a step of forming a latent image (Qian Xiang of the inspection mark (S105) at least in the heating film is the photosensitivity of which the latent image of the test mark is formed in the area of the second inspection step (S106) hovering the shape of the marks emerged inspection mark step (S107) the process (S109) of changing the set value of the exposure device at the time of selecting an exposure so that the exposure conditions are designed value according to the measuring result of measuring a shape, a device pattern on the mask onto the photosensitive film on the basis of the changed set point exposure to the process (S110) for forming a latent image of the device pattern on the photosensitive film, the process (S111) for heating the photosensitive film front, for developing the photosensitive film It includes information (S112)
title: Method of manufacturing semiconductor device and manufacturing apparatus thereof
year: 2003

abstract: PURPOSE: A method for reworking a semiconductor device manufacturing wafer is to completely remove and rework a photoresist coated abnormally by using an innoxious thinner composition having the proper melting speed and the volatility. CONSTITUTION: A photoresist(23) is coated on a semiconductor substrate(21) to form a specific pattern on the semiconductor substrate. The semiconductor substrate with the photoresist formed thereon is loaded on a rotatable vacuum chuck. A thinner composition is supplied to the loaded semiconductor substrate. The thinner composition is produced by mixing 70 wt to 80 wt of ethyl 3 ethoxy propionate, 17 wt to 23 wt of ethyl lactate, and 4 wt to 7 wt of gamma butyro lactone. The photoresist is soaked in the thinner composition for a predetermined time until it melted by the thinner composition. After rotating the vacuum chuck, the photoresist is removed by using the thinner composition.
title: Method of reworking wafer for semiconductor device and of manufacturing semiconductor device
year: 1998

abstract: Semiconductor wafer fabrication is perhaps one of the most complex manufacturing processes found today. In this paper, we construct a simulation model of partial of a wafer fab using ProModel software and analyze the effect of different input variables on selected parameters, such as cycle time, WIP level and equipment utilization rates. These input variables include arrival distribution, batch size, downtime pattern and lot release control. SEMATECH DATASET which has the original actual wafer fab data is used for our analysis. INTRODUCTION Semiconductor manufacturing differs from many other manufacturing environments by the complexity and variability of its processes. A semiconductor process can be several hundred operations long, and the machines are relatively unreliable due to the leading edge technology involved. At the same time, there are situations of re entrant processes, rework, and scrap etc. in the semiconductor manufacturing process. All of these make semiconductor factories harder to control than other plants of comparable size. Moreover, today's semiconductor industry is more dynamic and competitive than ever. Product's profit cycles are shrinking quarterly. Products that used to have a life cycle of 18 months now have average profit cycle of only 6 months. Customer demand for shorter cycle times and specialized packaging/delivery requirements is an obvious major trend. The entire semiconductor industry is very sensitive to the economic and trade climates. It is typical in the semiconductor market to have large oscillations in demand. Additionally, due to the trade off of waiting time in exchange for high equipment utilization in a factory of unreliable equipment, cycle time in semiconductor manufacturing is long in general. In this paper we provide an overall analysis of the behavior of some key parameters in semiconductor manufacturing, including the cycle time, WIP and utilization rates, in response to changes in the fab environment and lot release patterns using a simulation model of partial of a wafer fabrication (fab) using ProModel software. From these results, the major influencing parameters and the most desirable lot release pattern could be identified. SEMATECH DATASET which has the original actual wafer fab data is used for our analysis. 1 School of Mechanical and Production Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798. Email: pg01538903@ntu.edu.sg 2 School of Mechanical and Production Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798. Email: msiva@ntu.edu.sg Journal of The Institution of Engineers, Singapore Vol. 44 Issue 4 2004 54 In Section 2 we look at the overview of semiconductor manufacturing and wafer fabrication, followed by a general description of our research approach in Section 3. The model description is in Section 4 and experimental results are discussed in Section 5. Section 6 draws the conclusion and ideas for further research. SEMICONDUCTOR MANUFACTURING Overview of Semiconductor Manufacturing Wafer Start Wafer Fabrication Wafer Probe Assembly Final Test Product Ship Wafer Die Package Circuit Tested Circuit
author_names: Qi Chao

Appa Iyer Sivakumar
title: SIMULATION BASED CAUSE AND EFFECT ANALYSIS IN SEMICONDUCTOR WAFER FABRICATION
year: 2004

abstract: The semiconductor manufacturing industry is one of the most important industries in Taiwan. Wafer fabrication is an essential process in semiconductor manufacturing. However, controlling the production system on the shop floor is extremely difficult owing to the complicated manufacturing process and reentrant characteristics. In this paper, the shop floor control (SFC) integration strategies (order review/release, dispatching, and rework strategies) in wafer fabrication are considered with using several performances. We reviewed the literature on SFC strategies in wafer fabrication. The proposed combination simulation and simulated annealing (SA) algorithm is presented for SFC strategies in wafer fabrication. The objective was to seek the near global optimum solution for the combination of SFC strategies for a specific performance indicator. From the results, the proposed methodology was found to perform well for combinations of SFC strategies using different performance indicators in wafer fabrication. However, no single combination of SFC strategies could satisfy all performance indicators. Hence, considering the trade off among these production control strategies, a suitable strategy should be chosen based on the system control tactics. Considerable computational time was saved in this research.
author_names: D Y Sha

Chao-Yang Liu
title: A simulated annealing algorithm for integration of shop floor control strategies in semiconductor wafer fabrication
year: 2003

abstract: This paper presents the processes, steps and inspections, various testing stages involved starting from procurement of wafer onwards to individual Die form. Any semiconductor die or integrated circuit must performed all the processes of inspection and testing once it receives from any manufacturer and then it has to be procured to any Manufacturing Line for further process as a part of any Manufacturing products. This paper is also an attempt to isolate the entire good and bad Semiconductor Dies received from some Semiconductor Manufacturer at one place with complete package before going to Manufacturing Unit. It not only yields the efficiency of the Product in that Manufacturing line but also it saves a lot of manpower given for Failure Analysis, rework, retesting, etc and also it increases the Product reliability Any small change in the product which may be either due to process improvement or due to application requirements or due to material changes had a direct impact on device reliability. The device reliability depends upon avoiding any small and minute changes from the original one. For example any changes in die size which occurred due to scratch, die track cut, chips out, cracks, voids, corrosion on bond pads, glassivation, metallization, passivation, leads to decrement of Product performance. For an instant, the capacitor of cracked Die (1) becomes either half for parallel circuited or get doubled for series circuited. In both the cases, the resonance for the Product affects and hence the performance degrades. If there are any voids or corrosion on bond pads, the series inductance increases which again degrades. Hence for successful Product launching; the associated items should be understood about their functionality, performance and also to be prevented to avoid any type of changes in size and shape.
author_names: Satya Sai Srikant

Rajendra Prasad Mahapatra
title: Semiconductor Die: Processing and Packaging
year: 2012

abstract: Although the national importance of the semiconductor industry is widely acknowledged, it is only recently that the production planning and scheduling problems encountered in this environment have begun to be addressed using industrial engineering and operations research.techniques. These problems have several features that make them difficult and challenging: random yields and rework, complex product flows, and rapidly changing products and technologies. Hence their solution will contribute considerably to die theory and practice of production planning and control. In a two part project we present a review of research in this area to date, discuss the applicability of the various approaches and suggest directions for future research. In this paper, Part I, we describe the characteristics of the semiconductor manufacturing environment and review models related to performance evaluation and production planning. Part II will review research on shop floor control in this industry to date.
author_names: Reha Uzsoy

Chung-Yee Lee

Louis A Martin-Vega
title: A REVIEW OF PRODUCTION PLANNING AND SCHEDULING MODELS IN THE SEMICONDUCTOR INDUSTRY PART I: SYSTEM CHARACTERISTICS, PERFORMANCE EVALUATION AND PRODUCTION PLANNING
year: 1992

abstract: This paper deals with the lot sizing problem in which the key features of imperfections in a production process are explicitly modelled. These features include: process shifting to out of control states, detection of the out of control shifts, corrective actions following the detections, and the fixed setup and variable processing times of reworks. The problem is motivated by the wafer probe operation in semiconductor manufacturing. The key objective that drives the lot sizing decision is to reduce the total processing time on a critical resource. Such an objective is aimed at reducing the congestion level at this resource.
author_names: Hau L Lee
title: Lot sizing to reduce capacity utilization in a production process with defective items, process corrections, and rework
year: 1992