Query: field effect transistor random doping effect

Candidate papers:

abstract: In this paper, a 1T DRAM based on the junctionless field effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer aided design simulation (TCAD) The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band to band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage) intrinsic region length (Lint) and operation bias conditions to obtain a high sensing margin of 49.7 mA/mm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS)
author_names: Min Su Cho

Jun Hyeok Jung

Won Douk Jang

Hye Jin Mun

Jaewon Jang

Jin-Hyuk Bae

In Man Kang
title: Design of a Capacitorless Dynamic Random Access Memory Based on Ultra Thin Polycrystalline Silicon Junctionless Field Effect Transistor with Dual Gate.
venue: Journal of nanoscience and nanotechnology
year: 2021

abstract: Abstract This work reports the realization of high performance n type random network single walled carbon nanotube (rn SWCNT) field effect transistor (FET) by means of contact engineering, where a low work function metal, Yttrium (Y) is used as the source and drain contacts. The presence of crossed metallic m and semiconducting s SWCNT junctions in the channel of rn SWCNT FETs, which form p type rectifying Schottky barrier, is believed to introduce non negligible hole current in the fabricated FETs and lead to undesirable ambipolar characteristic. By means of soaking in 2,4,6 triphenylpyrylium tetrafluoroborate (2,4,6 TPPT) we have successfully converted the ambipolar rn SWCNT FETs to highly unipolar n type devices by selectively removing the m SWCNTs in the FET channel. The best characteristics of our unipolar n type rn SWCNT FETs are as follows: on/off current ratio up to ~10 5 mobility as high as 25 cm 2 V 1 s 1 and transconductance of 0.12 mS/mm; they have demonstrated air stable n type characteristics and are also more reproducibility than individual SWCNT FETs.
author_names: Lei Huang

Eng Fong Chor

Yihong Wu
title: Doping free fabrication of n type random network single walled carbon nanotube field effect transistor with yttrium contacts
year: 2011

abstract: Using calibrated simulations, we report a detailed study of the doping less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping less TFET is similar to that of a corresponding doped TFET. The doping less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping less TFET does not require a high temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon on glass substrates formed by wafer scale epitaxial transfer.
author_names: Mamidala Jagadesh Kumar

S Janardhanan
title: Doping Less Tunnel Field Effect Transistor: Design and Investigation
venue: IEEE Transactions on Electron Devices
year: 2013

abstract: This work investigates the novel device structure, silicon on nothing electrostatically doped junctionless tunnel field effect transistor (SON ED JLTFET) with high K stacked hetero gate technology for its short channel effects (SCEs) immune properties. Here, its analog/RF device performance metrices are also analyzed using calibrated 2 D technology computer aided design (TCAD) simulation study. This device is expected to exhibit the fundamental advantages of SON technology, i.e. it should be more immune towards SCEs, like threshold voltage roll off, drain induced barrier lowering (DIBL) even for devices with less than 10 nm channel length. Moreover, owing to its electrostatic doping instead of metallurgical doping, the detrimental doping control issues, such as mobility degradation, higher fabrication thermal budget and statistical random dopant fluctuations (RDFs) can no more degrade the device performance. This helps in realization of more process variations immune design. Here the detailed device sensitivity analysis with respect to the various crucial devices dimensional parameters variation is also carried out.
author_names: Aishwarya Kaity

Sangeeta Singh

Pravin Neminath Kondekar
title: Silicon On Nothing Electrostatically Doped Junctionless Tunnel Field Effect Transistor (SON ED JLTFET) A Short Channel Effect Resilient Design
venue: Silicon
year: 2020

abstract: Recently, dopingless tunnel FET (DL TFET) has emerged and gathered much attention, for it avoids the physical doping process and provides superior immunity against random dopant fluctuation. Nevertheless, it also suffers from low drive current and severe ambipolar effect. In order to overcome these problems, an L shaped DL TFET (LDL TFET) with the gate engineering technique is proposed in this paper. In this device, the space between the source and the gate electrodes can be further optimized to reduce the tunneling distance, and hence boost the drive current. Also, without much fabrication difficulties, hetero gate dielectric (HGD) and tunneling gate (TG) structures can be utilized in the LDL TFET. Benefiting from the modification of the band energy by HGD and TG, the source channel tunneling distance is further reduced, while the drain channel tunneling distance is enlarged. TCAD simulation results show that in comparison with planar DL TFET (PDL TFET) LDL TFET offers better performance in terms of on current, switch ratio, subthreshold slope, ambipolar current and RF parameters. It indicates that the LDL TFET is a promising device for low power RF and digital logic applications.
author_names: Cong Li

Jia-min Guo

Hao-Feng Jiang

Hailong You

Weifeng Liu

Yiqi Zhuang
title: A novel gate engineered L shaped dopingless tunnel field effect transistor
year: 2020

abstract: In this paper, a Gate stack Doping less Tunnel field effect transistor is proposed using a double gate doping less TFET(DLTFET) with a multilayer gate stack architecture. The device characteristics are demonstrated and compared with DLTFET. It is found that the proposed architecture is having better performance than DLTFET. It is based on Charge plasma concept. There is no Source and Drain doping applied. Thus, it is free from Random dopant fluctuation issue and highly reliable. The gate dielectrics are used in stack manner to form a multilayer architecture. It provides the ON current of about 0.1 mA/um with a low OFF current, 5x10 18 A/um. The threshold voltage is 0.8V and the Sub threshold swing is calculated as 77mV/dec. All the simulations has been performed using SILVACO ATLAS device simulator.
author_names: Deepali Vasnik
title: DESIGN AND ANALYSIS OF GATE STACK DOPING LESS TUNNEL FIELD EFFECT TRANSISTOR
year: 2014

abstract: In this work, we explore for the first time dual material gate (DMG) and inverse DMG devices for suppressing the random dopant (RD) induced characteristic fluctuation in 16 nm metal oxide semiconductor field effect transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD induced threshold voltage, on state current, and off state current fluctuations are 28, 12.3, and 59% respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel doping profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel doping profile has good immunity to fluctuation.
author_names: Yiming Li

Kuo-Fu Lee

Chun-Yen Yiu

Yung-Yueh Chiu

R W Chang
title: Dual Material Gate Approach to Suppression of Random Dopant Induced Characteristic Fluctuation in 16 nm Metal Oxide Semiconductor Field Effect Transistor Devices
year: 2011

abstract: Abstract In this paper, for the first time, DC characteristics and analog/RF performance of polarity control GaAs Ge hetero TFET (GaAs Ge H TFET) structure have been analysed, using electrically doped dynamically configurable concept. For this, we have considered a hetero structure with two distinctive gates (Control gate and Polarity gate) Polarity gate induces p+ region at the source side and n+ region at the drain side, instead of relying on the abrupt doping profile at the junctions. Therefore, the fabrication process of the proposed device avoids ion implantation, photo masking and complicated thermal budget. Hence, it shows high immunity against process variations, doping control issues and random dopant fluctuations (RDF) In order to optimize the device performance, interfacing of III V groups materials with IV group semiconductor is done for hetero junction. The introduction of hetero junction and band gap engineering offer higher ION/IOFF ratio (5.1 x 1012) steep sub threshold slope (18 mV/decade) and significantly change in analog/RF performance. The analog/RF figures of merit are analysed in term of transconductance (gm) output conductance (gds) gate to source capacitance (Cgs) gate to drain capacitance (Cgd) cutoff frequency (fT) and gain bandwidth (GBW) product. The proposed work would be beneficial for low power high frequency applications. The simulation results presented in this paper were carried out by using 2 D ATLAS.
author_names: Kaushal Nigam

Pravin Neminath Kondekar

Dheeraj Sharma
title: DC characteristics and analog/RF performance of novel polarity control GaAs Ge based tunnel field effect transistor
year: 2016

abstract: A novel dual metal gate doping less vertical tunnel field effect transistor (D VTFET) on silicon body, using work function engineering is proposed. The proposed structure does not required impurity doping for formation of the drain and the source regions. In this concern, source and drain regions are formed by selecting appropriate work function of metal electrode. The source and drain regions are not formed by conventional ways of ion implantation or diffusion. Hence, proposed structure is immune greatly to the process variation, issues of doping control and random dopant fluctuations which are serious problems in ultrathin silicon devices. For further improvement in ON state current and analogue/RF figures of merit dual work function of single gate material is considered. The electrical characteristics of the proposed device with the D VTFET are simulated and compared.
author_names: Kaushal Nigam

Pravin Neminath Kondekar

Dheeraj Sharma
title: High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering
year: 2016

abstract: Silicon based Static Random Access Memory (SRAM) has not been keeping pace with technology trends due to the limited improvements in power, performance and density. This paper explores graphene based SRAM as a potential replacement of silicon SRAM for future digital electronics. Due to its higher current on to off ratio, the graphene nanoribbon field effect transistor (GNRFET) has been considered in this paper. In the nanometer regime, process variation is not only inevitable but also very pronounced. To mitigate its effects as much as possible, the Schottky Barrier type GNRFET is considered which presents lower variation in its characteristics due to doping variation. The results show that graphene nanoribbon has a great potential in digital circuit design. The GNRFET based SRAM design presented in this paper leads to significantly lower power consumption, approximately 93% compared to 45 nm silicon technology. This upper bound can be quite achievable as the fabrication technology of graphene reaches maturity.
author_names: Shital Joshi

Saraju P Mohanty

Elias Kougianos

Venkata P Yanambaka
title: Graphene Nanoribbon Field Effect Transistor Based Ultra Low Energy SRAM Design
venue: 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
year: 2016