Query: CMOS voltage-tofrequency converter with temperature drift compensation

Candidate papers:

abstract: This paper presents a new complementary metal oxide semiconductor (CMOS) differential voltage to frequency converter (VFC) suitable for sensor signal conditioning. Designed in a low cost 0.18 mm CMOS process, the proposed VFC consumes less than 0.4 mW at a 1.8 V supply. For a differential input range of 0 1.2 V, output frequency varies from 0.1 to 1.1 MHz with a linearity error of less than 0.4% A new temperature compensation technique keeps the gain error below 2.4% over the whole frequency span for a range of 20degC +120degC.
author_names: Maria de Rodanas Valero Bernal

Santiago Celma

Belen Calvo

Nicolas J Medrano-Marques
title: CMOS Voltage to Frequency Converter With Temperature Drift Compensation
venue: IEEE Transactions on Instrumentation and Measurement
year: 2011

abstract: This paper presents a new CMOS differential voltage to frequency converter (VFC) which targets front end sensor interfacing in wireless sensor network applications. The proposed VFC, designed in a low cost 0.35 micrometer CMOS technology supplied at 3 V, achieves high performances: power consumption below 0.3 mW, 0 2V differential input range operation and nonlinearity error less than 0.3 Thanks to the introduction of a very simple control circuit, linearity is preserved over variations of temperature: the error is less than 2.3 over all the frequency range for a temperature range from 40deg C to +120deg C.
author_names: M R Valero

Santiago Celma

Belen Calvo

Nicolas Medrano
title: A CMOS Differential Voltage to Frequency Converter with Temperature Drift Compensation: European Workshop on Smart Objects: Systems, Technologies and Applications
year: 2010

abstract: A CMOS pulse output readout circuit with temperature compensation for a temperature dependent input voltage is presented. The circuit consists of a voltage to current (V I) converter, a current controlled oscillator (CCO) and a temperature sensor with proportional to absolute temperature (PTAT) output current. An input voltage, Vsen, is converted into a current by the V I converter and then the current is used to generate a pulse output through the CCO. The PTAT current can be mirrored into the CCO in order that the temperature induced current drift of the V I converter can be compensated if the Vsen will decrease with increasing temperature. The output pulse frequency of the CCO is linearly proportional to the Vsen with a linearity of at least 99.998% The suitability of the readout circuit for ion sensitive field effect transistors (ISFETs) which effective gate voltage related to pH value decreases with increasing temperature, was estimated and measurement results show that output frequency variation with temperature is decreased by a factor of at least 10 under the compensation of the PTAT current.
author_names: R L Wang

C Yu

W D Wu

Y F Hao

J L Shi

Hsin-Hao Liao

Hann-Huei Tsai

Ying-Zong Juang
title: Pulse Output Readout Circuit with Temperature Compensation for a Temperature Dependent Input Voltage
year: 2014

abstract: Process and temperature variations have become a serious concern for ultra low voltage (ULV) technology. The clock generator is the essential component for the ULV very large scale integration (VLSI) MOSFETs is operated in the sub threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators has been studied. A multi phase crystal less clock generator (MPCLCG) with a process voltagetemperature (PVT) calibration circuit is proposed in Chapter 3. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18 m CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65m x75m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degC from 0 to 100degC, and 2 point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58 ps RMS jitter and a 34.55IV ps peak to peak jitter (P2P jitter) at 192 MHz within 12.67k hits. At 192 MHz, it shows a 1 MHz offset phase noise of 102dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3% respectively. Being operated with 0.5V supply voltage in a standard 65nm CMOS process, a new CMOS temperature compensated crystal less clock generator. The bias current provided by the bandgap reference circuit and low dropout operate amplifier are nearly independent of temperature due to the existence of mutual compensation of mobility and threshold voltage variation. The new proposed temperature compensated crystalless clock generator functions well by the analog linear compensation mechanism. Chapter 4 presents an ultra low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance. We also discuss the time to digital converter system for time measurement unit in chapter 5. The Appendix A shows the electron distribution in an amorphous indium gallium zinc oxide (a IGZO) thin film transistor (TFT) with a floating metal semiconductor (MS) back interface is analyzed using a technology computer aided design (TCAD) model. The channel geometry (i.e. length and thickness) effect is carefully investigated. At a high work function (i.e. 5 eV) of the capping metal, the capping metal (electron depletion effect) mostly removes electrons inside a IGZO. The depletion of the IGZO film leads to an increase in threshold voltage in a IGZO TFT. TCAD simulation reveals that increasing channel length and decreasing IGZO thickness significantly enhance such an electron depletion effect. Finally, the electron depletion effect is applied to aIGZO TFT with a high conductivity IGZO film to greatly suppress the leakage current by over 5 orders. The Appendix B shows a voltage reference circuits on poly Silicon TFT. Because this paper is based on author's master thesis, detailed contents could refer the author's master thesis.
author_names: Ting-Chou Lu

Ming-Dou Ker

Hsiao-Wen Zan
title: DESIGN AND IMPLEMENTATION OF CRYSTAL LESS CLOCK GENERATOR WITH PROCESS VOLTAGE TEMPERATURE COMPENSATION
year: 2017

abstract: Multi radio (3G/4G/GPS) mobile communication devices impose stringent requirements (1ppm) on a crystal oscillator's (XO) frequency stability over a wide temperature range (100degC) Furthermore, these devices often subject their internal XOs to sudden temperature ramps caused by power switching during sporadic user activities. In order for applications such as GPS to maintain satellite acquisition under such conditions, a low XO frequency drift rate with temperature (50ppb/degC) is strongly desired. Traditionally, a discrete analog temperature compensated XO (TCXO) is often used for crystal frequency temperature compensation. Recently, an integrated digital TCXO (DTCXO) [1] that uses an on chip PTAT sensor and a DS ADC interface was presented. However, this system's accuracy is limited by the proximity induced temperature difference between the crystal and on chip sensor. Moreover, the high converter latency (up to 0.1s) [2] imposed by the low bandwidth DS ADC degrades the system's frequency drift control capability in response to the temperature ramp. The temperature sensing interface presented in this paper addresses these issues by using: (1) an in situ crystal temperature sensor; (2) a digitally calibrated SAR ADC; (3) mixed voltage domain (2.5V/1V) SC front end sampling to accommodate the ADC under a 1V supply; and (4) chopping and digital demodulation to reduce the 1/f noise.
author_names: Zhenning Wang

Richard Lin

Eshel Gordon

Hasnain Lakdawala

Larry Richard Carley

Jonathan C Jensen
title: An in situ temperature sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency temperature compensation of crystal oscillators
venue: 2010 IEEE International Solid State Circuits Conference (ISSCC)
year: 2010

abstract: This paper describes a 10 bit, 500 kHz, low power steering current CMOS D/A converter for portable communications. A triple segmented architecture is used to improve the linearity while minimizing the circuit area and gain error compensating circuitry is employed to correct for full scale errors. The prototype chip fabricated in a 1.2 /spl mu/m standard CMOS technology occupies less than 0.45 mm/sup 2/ and consumes less than 2.4 mW for a 1 V output swing at 5 V supply. Full scale voltage errors due to chip to chip variations are better than /spl plusmn/3% and below /spl plusmn/43 ppm//spl deg/C for temperature drifts in the range 30/spl deg/C to +85/spl deg/C.
author_names: Bernardo G Henriques

K Kananen

Jose E Franca

Juha Rapeli
title: A 10 bit low power CMOS D/A converter with on chip gain error compensation
venue: Proceedings of the IEEE 1995 Custom Integrated Circuits Conference
year: 1995

abstract: In this work, we proposed a linear CMOS temperature to current converter as a temperature sensor, which especially benefit on enhancing the accuracy of thermal monitoring. The proposed design achieves highly linear relationship between temperature and current by annulling the most critical nonlinear square terms of it. Through utilizing a compensation scheme among two current sources driven in saturation region with different bias voltages, the nonlinear effect originated from the temperature dependence of both mobility degradation and threshold voltage drift is cancelled. The experiment results demonstrate competitive performance. The maximum temperature error and average power consumption of temperature sensor are merely 0.022degC and 137.6uW respectively while the die area is about 27.1um*18.3um under the implementation of TSMC 0.35um CMOS process with 3.3V power supply.
author_names: Chun Wei Lin

Sheng-Feng Lin
title: A highly linear CMOS temperature sensor
venue: The 8th Electrical Engineering/ Electronics, Computer, Telecommunications and Information Technology (ECTI) Association of Thailand Conference 2011
year: 2011

abstract: The design of a direct time of flight complementary metal oxide semiconductor (CMOS) image sensor (dToF CIS) based on a single photon avalanche diode (SPAD) array with an in pixel time to digital converter (TDC) must contemplate system level aspects that affect its overall performance. This paper provides a detailed analysis of the impact of process parameters, voltage supply, and temperature (PVT) variations on the time bin of the TDC array. Moreover, the design and characterization of a global compensation loop is presented. It is based on a phase locked loop (PLL) that is integrated on chip. The main building block of the PLL is a voltage controlled ring oscillator (VCRO) that is identical to the ones employed for the in pixel TDCs. The reference voltage that drives the master VCRO is distributed to the voltage control inputs of the slave VCROs such that their multiphase outputs become invariant to PVT changes. These outputs act as time interpolators for the TDCs. Therefore the compensation scheme prevents the time bin of the TDCs from drifting over time due to the aforementioned factors. Moreover, the same scheme is used to program different time resolutions of the direct time of flight (ToF) imager aimed at 3D ranging or depth map imaging. Experimental results that validate the analysis are provided as well. The compensation loop proves to be remarkably effective. The spreading of the TDCs time bin is lowered from: (i) 20% down to 2.4% while the temperature ranges from 0 degC to 100 degC; (ii) 27% down to 0.27% when the voltage supply changes within 10% of the nominal value; (iii) 5.2 ps to 2 ps standard deviation over 30 sample chips, due to process parameters' variation.
author_names: Ion Vornicu

Ricardo Carmona-Galan

Angel Rodriguez-Vazquez
title: Compensation of PVT Variations in ToF Imagers with In Pixel TDC
venue: Sensors
year: 2017

abstract: The aim of this thesis was to develop time to digital converters (TDC) for the integrated receiver of a pulsed time of flight (TOF) laser rangefinder aiming at cm level accuracy over an input range of 10 m 15 m. A simple structure, a high integration level and low power consumption are the desired features for such a TDC. From the pulsed TOF laser rangefinder point of view an integrated receiver consisting of both the TDC and the receiver channel on the same die offers the possibility of manufacturing these laser rangefinders with a high integration level and at a low price to fulfil the needs of mass industrial markets. The heart of the TDC is a CMOS ring oscillator, the clock frequency of which is used to calculate the full clock cycles between timing signals, the positions of the timing signals inside the clock period being determined by storing the state of the phase of the ring oscillator for each timing signal. This will improve the resolution of the TDC. Also, additional delay lines are used to generate multiple timing signals, each having a time difference of a fraction of that of the ring oscillator. This will further improve the resolution of the whole TDC. To achieve stable results regardless of temperature and supply voltage variations, the TDC is locked to an on chip reference voltage, or the resolution of the TDC is calibrated before the actual time interval measurement. The systematic walk error in the receiver channel caused by amplitude variation in the received pulse is compensated for by the TDC measuring the slew rate of the received pulse. This time domain compensation method is not affected by the low supply voltage range of modern CMOS technologies. Three TDC prototypes were tested. A single shot precision standard deviation of 16 ps (2.4 mm) and a power consumption of 5.3 mW/channel were achieved at best over an input range of 100 ns (15 m) The temperature drifts of an on chip voltage reference locked TDC and a TDC based on the calibration method were 90 ppm/degC and 0.27 ps/degC, respectively. The results also showed that a pulsed TOF laser rangefinder with cm level accuracy over a 0 15 m input range can be realized using the integrated receiver with the time domain walk error compensation described here.
author_names: Ilkka Nissinen
title: CMOS time to digital converter structures for the integrated receiver of a pulsed time of flight laser rangefinder
year: 2011

abstract: In this paper we report on the design of a frequency compensation system for AlN on Si MEMS reference oscillator to replace temperature compensated crystal oscillators (TCXOs) in cellular handsets. A 76.8MHz, 105ppm Temperature Stable, AlN on Si MEMS Oscillator is designed to demonstrate the frequency compensation scheme. Double layers of SiO 2 are used for passive temperature compensation. The oscillator consumes 850uA, with phase noise of 127dBc/Hz at 1kHz frequency offset. Temperature drift errors and initial frequency offset of z 8000ppm are combined and further tackled electronically. A simple digital compensation circuitry generates a compensation word to a 21 bit MASH 1 1 1 DS modulator included in LTE fractional N PLL for frequency compensation. Temperature is sensed using 4.6uA, 11.5 bit temperature to digital converter TDC with resolution of 0.1degC in 100ms conversion time. The paper presents the first AlN on Si oscillator platform with z 0.5ppm frequency stability over temperature ranges from 40degC to 85degC. The system runs on 1.8V supply in 32nm CMOS.
author_names: Ali Kourani

Emad Hegazi

Yehea I Ismail
title: Electronic frequency compensation of AlN on Si MEMS reference oscillators
venue: Microelectron. J.
year: 2016