Query: An ultrafast adaptively biased capacitorless LDO with dynamic charging control

Candidate papers:

abstract: This brief presents a current efficient fully integrated low dropout regulator (LDO) for system on a chip applications. A common gate error amplifier with high bandwidth and slew rate is proposed to reduce the output voltage spike and the response time of the LDO greatly. In addition, the loop employs a direct dynamic charging technique to enhance load transient responses by directly detecting voltage variations through a capacitive coupling high pass filter. The circuit has been implemented in a 0.35 mm standard complementary metal oxide semiconductor process and occupies an active chip area of 0.064 mm2. Experimental results show that it can deliver a load current of 100 mA at a dropout voltage of 150 mV. It only consumes a quiescent current of 7 mA at light loads and can recover within 0.15 ms, even under the maximum load current change. Consequently, a faster and more accurate capacitorless LDO can be achieved.
author_names: Xin Ming

Qiang Li

Ze-kun Zhou

Bo Zhang
title: An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2012

abstract: This paper presents the design of a low dropout voltage regulator which has a low area and power consumption, as well as an improved transient response. The area reduction is achieved by biasing the power transistor in the triode region. In addition, a dynamic bias network is used in order to reduce its settling time to 300ns for any change in the load current from 100uA to 100mA. The regulator is designed in a Silterra 0.18um standard CMOS technology and brings a regulated output voltage of 1.8V. All the circuit is biased with 2.3uA only at loads smaller than 1mA, and can recover within 0.3us for maximum load and input voltage changes. Moreover, the regulator does not need any external capacitor to guarantee its stability
author_names: Andres Amaya

Hector Gomez

Guillermo Espinosa
title: An area efficient high speed, fully on chip low dropout LDO voltage regulator
year: 2015

abstract: A fully on chip LDO for very fast load transient up to 15mA/nsec in 28nm FDSOI is presented. Proposed LDO capitalizes on technological boost given to on chip capacitance density and MOS current drives to implement conventional compensation technique without using off chip capacitor. Dominant output pole enables the LDO to achieve its superior load transient performance. Proposed LDO generates 1.0V output from a 1.6V input supply and has maximum output current capacity of 15mA. Simulated worst case PSR at 10kHz is 23dB and current efficiency is 93% at maximum load condition. Three such LDOs are combined to provide dedicated 1.0V supplies to dual lane USB cores and their PLL. Area including reference generator, three LDO and all on chip capacitances is 0.2mm2.
author_names: Saurabh Kumar Singh

Gautam Dey Kanungo
title: Ultra fast Cap less LDO for Dual Lane USB in 28FDSOI
venue: 2015 28th International Conference on VLSI Design
year: 2015

abstract: This brief presents an ultralow quiescent class AB error amplifier (ERR AMP) of low dropout (LDO) and a slew rate (SR) enhancement circuit to minimize compensation capacitance and speed up transient response designed in the 0.11 mm 1 poly 6 metal CMOS process. In order to increase the current capability with a low standby quiescent current under large signal operation, the proposed scheme has a class AB operation operational transconductance amplifier (OTA) that acts as an ERR AMP. As a result, the new OTA achieved a higher dc gain and faster settling time than conventional OTAs, demonstrating a dc gain improvement of 15.8 dB and a settling time six times faster than that of a conventional OTA. The proposed additional SR enhancement circuit improved the response based on voltage spike detection when the voltage dramatically changed at the output node.
author_names: Youngil Kim

Sang-Sun Lee
title: A Capacitorless LDO Regulator With Fast Feedback Technique and Low Quiescent Current Error Amplifier
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2013

abstract: This paper presents an internally compensated capacitor less low dropout regulator (CL LDO) with bulk driven feed forward supply noise cancellation and adaptive compensation for fast settling time <italic>T<sub>S</sub>/italic> A feed forward path from the CL LDO's supply input to the output is implemented to increase power supply rejection (PSR) from mid range frequencies to up to 5 MHz. The CL LDO achieves a 90 dB low frequency and 64 dB PSR at 1 MHz for 50 mA of load current <italic>I<sub>L</sub>/italic> A transconductance amplifier with adaptive Miller compensation based on <italic>I<sub>L</sub>/italic> sense is used to increase the unity gain frequency by 40x at heavy loads. The CL LDO achieves a 0.3 mV/V line regulation, 10 <italic>m</italic>V/mA load regulation, 300 ns of <italic>T<sub>S</sub>/italic> and 0.16 ps figure of merit, which is 7.5x better than current state of the art CL LDOs. The CL LDO was fabricated in CMOS 130 nm technology, consumes <italic>I<sub>Q /sub>/italic> of 42 <italic>m</italic>A, has a dropout voltage <italic>V</italic><sub>DO</sub> of 200 mV for <italic>I<sub>L</sub>/italic> of 50 mA, and occupies an active area of 0.0046 mm<sup>2</sup>
author_names: Fernando Lavalle-Aviles

Joselyn Torres

Edgar Sanchez-Sinencio
title: A High Power Supply Rejection and Fast Settling Time Capacitor Less LDO
venue: IEEE Transactions on Power Electronics
year: 2019

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author_names: Escrito por

C Sandoval
title: H
venue: Saunders Comprehensive Veterinary Dictionary
year: 2021

abstract: An advanced smooth pole tracking technique for a low dropout (LDO) regulator with a ceramic capacitor is presented in this article. Normally, the dominant pole is at the output of an LDO and becomes load dependent, which may cause a loop stability issue during the whole load current application range. The proposed frequency compensation methodology with adaptive load resistor control of an error amplifier (EA) alleviates the problem and reduces the dependence of equivalent series resistance of an output capacitor. Moreover, combined with this compensation strategy, an ultrafast EA by utilizing a transconductance enhancement technique is proposed to greatly reduce output voltage spikes as well as response time of the LDO during transient. This circuit has been implemented in a 0.18 mm standard CMOS process and occupies an active chip area of 0.017 mm2. Experimental results show that it can deliver 150 mA load current at 200 mV dropout voltage. Good loop stability and transient responses are easily achieved without degrading other important LDO parameters.
author_names: Xin Ming

Hua Liang

Zhi-wen Zhang

Yang-Li Xin

Yao Qin

Zhuo Wang
title: A High Efficiency and Fast Transient Low Dropout Regulator With Adaptive Pole Tracking Frequency Compensation Technique
venue: IEEE Transactions on Power Electronics
year: 2020

abstract: This article presents a low quiescent current output capacitorless quasi digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post simulated in HSPICE in a 0.35 um CMOS process to supply a load current between 0 100 mA while consumes 7.6 uA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.
author_names: Alireza Saberkari

Herminio Martinez Garcia

Eduardo Jose Alarcon Cot
title: Quasi digital low dropout voltage regulators uses controlled pass transistors
year: 2016

abstract: In this paper a fully on chip, any capacitor stable linear voltage regulator (LVR) using sub unity gain positive feedback loop and NMOS pass element is presented. Sub unity gain of the loop decouples loop stability from output capacitance value thus realizing any capacitor stable regulator. Regulator is shown to be stable for wide range of output capacitance values from 1nF to 40mF. Regulator output settles i n 0.5ms with peak to peak voltage variation of 158mV for a load current step of 0 to 115mA in 0.14ms with 1nF output capacitance. Response becomes better for higher values of output capacitance. LVR generates 1.25V output from 1.6V input while using another 3.0V input supply and occupies 0.18mm2 in 65nm CMOS.
author_names: Saurabh Kumar Singh

Nitin Bansal
title: Any Capacitor Stable LVR Using Sub unity Gain Positive Feedback Loop in 65nm CMOS
venue: 2015 28th International Conference on VLSI Design
year: 2015

abstract: In this paper, a fully integrated digitally assisted low dropout regulator (LDO) for a NAND flash memory system is proposed and verified using 500 nm I/O CMOS transistors. By combining an amplifier (AMP) based LDO with a comparator (CMP) based LDO, the proposed LDO achieves both fast load response in the transient state and accurate regulation in the steady state, which are advantages of the CMP based LDO and AMP based LDO, respectively. Moreover, loop frequency stability is satisfied in a wide range of load currents between 0 and 150 mA by using the simple structure of the <inline formula><tex math notation="LaTeX"$g_{m}/tex math>/inline formula> boost cell to insert an auxiliary path. For an input voltage range of 2.3 3 V and an output voltage of 2.1 V, the measured output droop is 225 mV for a 150 mA load step in the load transition time of 20 ns with the total bias current of <inline formula><tex math notation="LaTeX"$81\\mu \rm{A}/tex math>/inline formula> The fabricated prototype chip occupies <inline formula><tex math notation="LaTeX"$160\\times ,610\\mu \rm{m}{2}/tex math> /inline formula> with an on chip output capacitor of 2 nF.
author_names: Kye-Seok Yoon

Hyun-Sik Kim

Wanyuan Qu

Young-sub Yuk

Gyu-Hyeong Cho
title: Fully Integrated Digitally Assisted Low Dropout Regulator for a NAND Flash Memory System
venue: IEEE Transactions on Power Electronics
year: 2018