Query: admitance trap SiC

Candidate papers:

abstract: The temperature and carrier trapping effects on the electrical characteristics of a 4H silicon carbide (4H SiC) metal oxide semiconductor field effect transistor (MOSFET) dimensioned for a low breakdown voltage (BVDS) are investigated. Firstly, the impact of the temperature is evaluated referring to a fresh device (defects free) In particular, the threshold voltage (Vth) channel mobility (uch) and on state resistance (RON) are calculated in the temperature range of 300 K to 500 K starting from the device current voltage characteristics. A defective MOSFET is then considered. A combined model of defect energy levels inside the 4H SiC bandgap (deep and tail centers) and oxide fixed traps is taken into account referring to literature data. The simulation results show that the SiO2/4H SiC interface traps act to increase RON, reduce uch, and increase the sensitivity of Vth with temperature. In more detail, the deep level traps in the mid gap have a limited effect in determining RON once the tail traps contributions have been introduced. Also, for gate biases greater than about 2Vth (i.e. VGS 12 V) the increase of mobile carriers in the inversion layer leads to an increased screening of traps which enhances the MOSFET output current limiting the RON increase in particular at low temperatures. Finally, a high oxide fixed trap density meaningfully influences Vth (negative shifting) and penalizes the device drain current over the whole explored voltage range.
author_names: Hichem Bencherif

Lakhdar Dehimi

Fortunato Pezzimenti

Francesco Giuseppe Della Corte
title: Temperature and SiO2/4H SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs
venue: Applied Physics A
year: 2019

abstract: The impact of crystal faces of 4H SiC in SiO2/4H SiC structures on interface trap densities and mobilities were examined by a method that utilizes Hall effect measurements and split capacitance voltage measurements to clarify the mechanism of high field effect mobilities in SiO2/4H SiC and The characterization results show that high field effect mobilities in nitrided SiO2/4H SiC and are caused by both lower interface trap densities near the conduction band edge and higher Hall mobilities compared to those in nitrided SiO2/4H SiC (0001) and
author_names: Tetsuo Hatakeyama

Takeyoshi Masuda

Mitsuru Sometani

Shinsuke Harada

Dai Okamoto

Hiroshi Yano

Yoshiyuki Yonezawa

Hajime Okumura
title: Impact of crystal faces of 4H SiC in SiO2/4H SiC structures on interface trap densities and mobilities
year: 2019

abstract: We report the physical and electrical characterization of the inversion layer carrier and the shallow interface trap sites with n and p channel SiC MOSFET in terms of high temperature electronics. This work proposes a physical model that explains the difference between Id Vg measurement result and calculation result supposing the ideal condition with Pao and Sah double ideal in room temperature. The measurement at 500degC confirmed our model so that inversion carrier were thermally excided, they could not be easily trapped by shallow trap sites, and Id Vg measurement result approached the ideal condition.
author_names: Shintaro Sato

Masahiro Masunaga

Yuki Mori

Nobuyuki Sugii

Akio Shima
title: Impact of Interface Trap Density of SiC MOSFET in High Temperature Environment
venue: Materials Science Forum
year: 2019

abstract: We present preliminary results on minority carrier traps in as grown n type 4H SiC Schottky barrier diodes. The minority carrier traps are crucial for charge trapping and recombination processes. In this study, minority carrier traps were investigated by means of minority carrier transient spectroscopy (MCTS) and high resolution Laplace MCTS measurements. A single minority carrier trap with its energy level position at Ev 0.28 eV was detected and assigned to boron related defects.
author_names: Ivana Capan

Yuichi Yamazaki

Yuya Oki

Tomislav Brodar

Takahiro Makino

Takeshi Ohshima
title: Minority Carrier Trap in n Type 4H SiC Schottky Barrier Diodes
venue: Crystals
year: 2019

abstract: In this paper, the results of electrical reliability measurements of commercially available 1200 V Silicon Carbide (SiC) MOSFETs are reported. The threshold voltage shift caused by interface states and the trapped charges near the SiC/SiO2 interface is observed under positive and negative DC bias stress over 50 hours. Threshold voltage reduction with temperature is also reported for devices from different vendors. Negative shift of subthreshold characteristics under the negative bias stress and high drain bias at elevated temperature indicates that the threshold voltage of the devices should be increased by at least 1 2 V. Extracted interface state density using subthreshold $I V$ curves indicates very different SiC/SiO2 interface for devices from different vendors.
author_names: Susanna Yu

Minseok Kang

Tianshi Liu

Diang Xing

Arash Salemi

Marvin H White

Anant K Agarwal
title: Bias Induced Threshold Voltage Instability and Interface Trap Density Extraction of 4H SiC MOSFETs
venue: 2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)
year: 2019

abstract: SPICE modeling of silicon carbide (SiC) MOSFET considering the influence of interface traps has been carried out, which is able to describe the characteristics of the MOS transistors in all operation modes at different interface trap densities and measurement temperatures. This modeling employs the SPICE level 1 model of MOSFET, but the constant mobility in the piecewise current equations has been replaced by the advanced mobility expression, which can exactly reflect the effect of SiC/SiO2 interface traps on the electrical characteristics of SiC MOSFET. Key parameters in the advanced mobility model are obtained according to charge sheet model (CSM) of MOS system. The static characteristics of the developed SiC MOSFET model have been validated with the production Datasheet, and the dynamic characteristics have been experimentally verified in Boost converter. Based on the developed model, the effect of SiC/SiO2 interface trap densities on the switching performances of SiC MOSFET has been quantitatively discussed, and reasonable gate driving voltage of SiC MOSFET with different interface trap densities has been revealed.
author_names: Yuming Zhou

Hangzhi Liu

Tingting Yang

Bing Wang
title: SPICE modeling of SiC MOSFET considering interface trap influence
year: 2018

abstract: The reverse bias current voltage characteristics of commercial 1200 V 4H silicon carbide junction barrier Schottky (SiC JBS) rectifiers are studied both experimentally and through numerical simulation. The reverse leakage current measured from physical devices is observed to display both a strong temperature and field dependence. A model is presented to explain the observed behavior based on a combination of trap assisted tunneling and a thermionic emission mechanism through a potential barrier located at the metal SiC interface. The study shows that a two level trapping model can be necessary to properly explain the measured data. Excellent agreement between the models and the measurements is obtained over a wide range of bias and temperature.
author_names: G Dolny

Yang Sheng

Yue Fu

Simon C Li

Rahul Radhakrishnan

Richard L Woodin
title: Multi Level Trap Assisted Tunneling Model for the Field and Temperature Dependence of SiC JBS Reverse Leakage Current
year: 2018

abstract: The current voltage characteristics of a 4H SiC MOSFET dimensioned for a breakdown voltage of 650 V are investigated by means of a numerical simulation study that takes into account the defect state distribution at the oxide semiconductor interface in the channel region. The modelling analysis reveals that, for these low voltage devices, the channel resistance component plays a key role in determining the MOSFET specific ON state resistance (RON) under different voltage biases and temperatures. The RON value is in the order of a few mOxcm2.
author_names: Giuseppe de Martino

Fortunato Pezzimenti

Francesco G Della Corte
title: Interface Trap Effects in the Design of a 4H SiC MOSFET for Low Voltage Applications
venue: 2018 International Semiconductor Conference (CAS)
year: 2018

abstract: We report results on the interface trap density (Dit) of 4H and 6H SiC metal oxide semiconductor (MOS) capacitors with different interface chemistries. In addition to pure dry oxidation, we studied interfaces formed by annealing thermal oxides in NO or POCl3. The Dit profiles, determined by the C pss method, show that, although the as oxidized 4H SiC/SiO2 interface has a much higher Dit profile than 6H SiC/SiO2, after postoxidation annealing (POA) both polytypes maintain comparable Dit near the conduction band edge for the gate oxides incorporated with nitrogen or phosphorus. Unlike most conventional C V or G o based methods, the C pss method is not limited by the maximum probe frequency, therefore taking into account the "fast traps" detected in previous work on 4H SiC. The results indicate that such fast traps exist near the band edge of 6H SiC also. For both polytypes, we show that the total interface trap density (Nit) integrated from the C pss method is several times that obtained from the high low method. The results suggest that the detected fast traps have a detrimental effect on electron transport in metal oxide semiconductor field effect transistor (MOSFET) channels.
author_names: C Jiao

Ayayi C Ahyi

Sarit Dhar

Dallas T Morisette

Rachael L Myers-Ward
title: Interface Trap Profiles in 4H and 6H SiC MOS Capacitors with Nitrogen and Phosphorus Doped Gate Oxides
venue: Journal of Electronic Materials
year: 2017

abstract: The paper aims at clarifying the carrier trapping influence on the electrical characteristics of silicon carbide (SiC) power MOSFETs and its inclusion in the simulation of SiC power mosfet based circuits. Special focus is given on the degradation of the switching characteristics due to carrier trapping at SiC/SiO2 interface defects. A compact SiC power mosfet model, considering the trap density in the framework of a complete surface potential description, has been developed by for accurate circuit simulation including power loss prediction. The carrier trapping is verified to cause a switching delay, which results in switching loss increase. To achieve low power loss, trap density reduction is shown to be vital. The maximum allowable trap density, which does not affect switching power loss, is discussed.
author_names: Yuta Tanimoto

Atsushi Saito

Kai Matsuura

Hideyuki Kikuchihara

Hans Jurgen Mattausch

Mitiko Miura-Mattausch

Noriaki Kawamoto
title: Power Loss Prediction of High Voltage SiC mosfet Circuits With Compact Model Including Carrier Trap Influences
venue: IEEE Transactions on Power Electronics
year: 2016