Query: dv dt SiC

Candidate papers:

abstract: Series connection of individual semiconductors is an effective way to achieve higher voltage switches. However, the inherent unequal dynamic voltage sharing problem needs to be solved, even when well matched gate drivers and semiconductors are used. A majority of the existing voltage balancing schemes are developed for slow switching silicon (Si) based semiconductors, and are also associated with a significant amount of additional losses in the control circuit or on the switches. In this paper, a novel method is proposed for balancing the dynamic voltages among series connected silicon carbide (SiC) MOSFETs with high dv/dt rates. The method takes advantage of a small capacitor to provide additional current to the gate of the MOSFETs at turn off, meaning the switching speed (and thus, the device voltage after turn off) is controlled. The proposed method generates negligible losses in the control circuit, and also does not significantly increase the switching losses of the semiconductors. Experimental results are provided to prove the effectiveness of the proposed voltage balancing scheme on two SiC MOSFETs inside a module connected in series. In order to do so, an active gate driver is designed embedding the active dv/dt control scheme as well as other essential functionalities needed for operation of SiC MOSFETs.
author_names: Alinaghi Marzoughi

Rolando Burgos

Dushan Boroyevich
title: Active Gate Driver With dv/dt Controller for Dynamic Voltage Balancing in Series Connected SiC MOSFETs
venue: IEEE Transactions on Industrial Electronics
year: 2019

abstract: Using high voltage (HV) silicon carbide (SiC) power semiconductors in a modular multilevel converter (MMC) is promising because it results in fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulsewidth modulation (NL PWM) is commonly used in the MMC for medium voltage applications. However, with the NL PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of the single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this article, limiting the maximum dv/dt to the dv/dt of a single power semiconductor and also maintaining the voltage balance performance. The proposed voltage balancing control is experimentally validated in a 10 kV SiC mosfet based MMC with four submodules per arm.
author_names: Shiqi Ji

Li Zhang

Xingxuan Huang

James Palmer

Fred Wang

Leon M Tolbert
title: A Novel Voltage Balancing Control With dv/dt Reduction for 10 kV SiC MOSFET Based Medium Voltage Modular Multilevel Converter
venue: IEEE Transactions on Power Electronics
year: 2020

abstract: Advanced high voltage (3.3 15kV) SiC MOSFETs have been developed for future medium voltage converters over the past decade due to their superior performance. In order to better understand the operation limits and potential of these devices, this paper evaluates the Imax fsw dv/dt trade off (maximal current handling capability at a specific switching frequency and at a defined switching speed) for high voltage SiC MOSFETs based on a proposed linearized analytical switching loss model. There, high voltage SiC MOSFETs manufactured by Cree combined with data from literature for scaling are used as reference.
author_names: Anliang Hu

Jurgen Biela
title: Evaluation of the Imax fsw dv/dt Trade off of High Voltage SiC MOSFETs Based on an Analytical Switching Loss Model
venue: 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)
year: 2020

abstract: The high frequency operation of the WBG devices such as SiC emphasizes the effect of parasitics, generating the reflected wave phenomenon and transient overvoltage on motor terminals, reducing the life time and the reliability of electric drives. In this paper the efficiency comparison of two topologies has been considered, a SiC MOSFET based two level and Si IGBT based three level T NPC inverter. The goal was to have the fair comparison, having the same output voltage capabilities and same output current THD. T NPC inverter is considered without an output filter, meeting the standard on voltage stress, while the dv/dt filter of 2L SiC based inverter is designed to meet the same specification as that of the T NPC inverter. The two inverters are considered with fastest switching and minimal losses. The efficiency comparison indicated the convenience of using SiC MOSFET based 2L inverter with an dv/dt filter for lower output power, while Si IGBT T NPC inverter shows higher efficiency for higher output power. The T NPC inverter shows the lowest cost and total volume as well. The goal was to ease the decision process and to have the clearest picture possible when comes to the judicious choice of the practitioners in the motor drive industry. Simulations were carried out by realistic dynamic models of power devices obtained from the manufacturer's experimental tests and verified both in the LTspice and PLECS simulation packages.
author_names: Jelena Loncarski

Vito Giuseppe Monopoli

Riccardo Leuzzi

Pericle Zanchetta

Francesco Cupertino
title: Efficiency, Cost and Volume Comparison of Si IGBT Based T NPC and 2 Level SiC MOSFET Based Topology With dv/dt Filter for High Speed Drives
venue: 2020 IEEE Energy Conversion Congress and Exposition (ECCE)
year: 2020

abstract: Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, HV SiC MOSFET based converters suffer from high dv/dt >100 V/ns) Under high dv/dt environment, sensors are easily interfered due to the power electronic device's fast switching. In this paper, the noise coupling mechanism in a submodule (SM) voltage sensor is analyzed, and the impact of SM voltage sensor noise on MMC phase leg operation is discussed. A simulation model and a 10 kV SiC MOSFET based MMC prototype with 25 kV dc link are built to validate the analysis of the impact.
author_names: Shiqi Ji

James Palmer

Xingxuan Huang

Dingrui Li

Bill Giewont

Leon M Tolbert

Fred Wang
title: Impact of Submodule Voltage Sensor Noise in 10 kV SiC MOSFET Modular Multilevel Converters (MMCs) under High dv/dt Environment
venue: 2020 IEEE Applied Power Electronics Conference and Exposition (APEC)
year: 2020

abstract: Silicon carbide (SiC) power devices are fundamentally capable of operating at a higher switching speed than their silicon (Si) counterparts. However, the ultra high voltage slew rate (dv/dt) aggravates the coupling effect between the two devices of the same phase leg, leading to significant cross talk issues. This paper reveals the driver parameters design method to suppress induced gate voltage spike and oscillation, without the penalty of increasing complexity and cost. The second order dynamic system analysis derives the mechanism of the induced voltage spike and oscillation. Experimental results captured from a double pulse platform justified the second order dynamic system analysis and spike and oscillation mechanism. Finally, the mechanism is used to guide the gate driver design of a 30kW commercial all SiC PWM rectifier.
author_names: Tiancong Shao

Zhijun Li

Zuoxing Wang

Trillion Q Zheng

Bo Huang

Zhipeng Zhang
title: Induced Gate Source Voltage Mechanism and Gate Driver Design in All SiC PWM Rectifier with Ultra High Voltage Slew Rate (dv/dt)
venue: 2020 IEEE 9th International Power Electronics and Motion Control Conference (IPEMC2020 ECCE Asia)
year: 2020

abstract: The dV/dt values for 4H SiC Schottky type diodes with different type packages have been determined experimentally. It is determined that experimental dV/dt values for 4H SiC Schottky type diodes in metal polymeric packages (SOT 89, QFN, PQFN, TO 220) are varying in interval of 645,1103 V/ns. It is established that the dV/dt dependence on maximal amplitude of reverse voltage demonstrate nonlinear character (close to parabolic dependence) for all studied SiC Schottky type diodes in different type packages.
author_names: D A Knyginin

S B Rybalka

E A Kulchenkov

Alexander A Demidov

N A Zhemoedov

Alexandr Y Drakin
title: dV/dt testing of high voltage 4H SiC Schottky diodes with different types of metal polymeric packages
year: 2020

abstract: In this paper, a dv/dt filter is designed for the modular multilevel converters (MMCs) based variable frequency motor drives. This concept utilizes the inherent arm inductors of the MMC as a part of the output low pass filter, thus eliminating the need for an add on inductor. Particularly, a mathematical model is proposed to optimize the filter loss and volume for a given dv/dt requirements. It turns out that with SiC MOSFET based high switching frequency operation, the dv/dt filter improves the output power quality and alleviates the voltage stress in motor drive applications. For applications with various requirements on filter volume and loss, weighted sum optimal solutions are presented. Simulation results based on a seven level MMC are provided to validate the theoretical analysis.
author_names: Xiao Li

Jianyu Pan

Ziwei Ke

Rui Ying Liu

Junchong Fan

Ya-li Zhang

Boxue Hu

Risha Na

Longya Xu

Jin Wang
title: Optimized Dv/dt Filter Design for SiC based Modular Multilevel Converters
venue: 2020 IEEE Energy Conversion Congress and Exposition (ECCE)
year: 2020

abstract: A SiC JFET/GaN HEMT cascode device is recently proposed, incorporating a low voltage (LV) GaN HEMT providing normally off operation and a high voltage (HV) delivering the HV blocking capability. This cascode device exhibits superior thermal stability and switching speed compared to SiC MOSFETs, but also inevitably presents challenge in dv/dt control as the JFET's gate cannot be directly controlled by the gate drive. Since dv/dt control is of great importance to the management and suppression of electromagnetic interference (EMI) in power electronics systems, methods of controlling the dv/dt rates of SiC/GaN cascode devices need to be developed. In this work, we demonstrated a SiC/GaN cascode device in a highly compact package using flip chip co package (FCCP) structure, aiming at minimizing the parasitic influences on its performance evaluation. The dv/dt control method based on RCD control (i.e. resistor capacitor diode control) is proposed and verified through experimental results using the demonstrated FCCP cascode device. The RCD control method is verified to be more effective compared to other more conventional methods regarding to the transient behavior and gate driver losses, owing to its balanced control of the turn on/off dv/dt rates.
author_names: Gang Lyu

Yuru Wang

Jin Wei

Zheyang Zheng

Jiahui Sun

Kevin J Chen
title: Dv/Dt control of 1200 V Co packaged SiC JFET/GaN HEMT Cascode Device
venue: 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)
year: 2020

abstract: A test scheme is designed to qualify MMC submodules based on 10 kV SiC MOSFETs comprehensively, including thermal design, insulation design, and operation under high dv/dt. In the test scheme, the essential step is the continuous test realized with the proposed ac dc continuous test circuit with two MMC submodules in series. With the designed modulation scheme, two cascaded submodules are leveraged to generate high dv/dt. The submodule under test has to continuously withstand 2X normal dv/dt of 10 kV SiC MOSFETs, which could occur during the MMC converter operation. Higher dv/dt can also be generated to fully test the submodule. An open loop voltage balancing method is adopted to simplify the continuous test setup. Simulation and experimental results are provided to validate the proposed test scheme.
author_names: Xingxuan Huang

Shiqi Ji

Dingrui Li

Cheng Nie

William Giewont

Leon M Tolbert

Fred Wang
title: A Test Scheme for the Comprehensive Qualification of MMC Submodule Based on 10 kV SiC MOSFETs under High dv/dt
venue: 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)
year: 2020