Query: embedded power module SiP package

Candidate papers:

abstract: Over the last 2 decades, power semiconductor technology has made impressive progress by increasing the power density of monolithic and system modules (Trends of power packaging and modeling, 2008; Trends in analog and power packaging, 2009; Challenges of power electronic packaging and modeling, 2011; Short course: analog and power packaging, 2011) This is the primary driving force behind power system in package (SiP) stack die, and 3D power packages with heterogeneous functional integration. For low power ultraportable applications such as mobile phones and the iPad(r) tablet, the most critical requirement for the point of load buck converter is its size. There are several ways to build the buck converter power module. The typical approach is to design the product with die side by side placement in a single level module using a QFN or other standard package, but this method cannot get the benefit of smaller package size. Another way is to build the buck converter with stack die or 3D concept, which may significantly reduce the package size to satisfy the power management for portable application. For high power with hybrid integration, side by side die placement power module is the primary design method for motion control such as automotive, railway, wind energy, and so on.
author_names: Yong Liu
title: Power Module/SiP/3D/Stack/Embedded Packaging Design and Considerations
year: 2012

abstract: A miniature LTCC system in package (SiP) module has been presented for millimeter wave applications. A typical heterodyne 61 GHz transmitter (Tx) has been designed and fabricated in a type of the SiP module as small as 36 x 12 x 0.9 mm3. Five active chips including a mixer, driver amplifier, power amplifier, and two frequency multipliers were mounted on the single LTCC package substrate, in which all passive circuits such as a stripline (SL) BPF, 2 x 2 array patch antenna, surface mount technology (SMT) pads, and intermediate frequency (IF) feeding lines have been monolithically embedded by using vertical and planar transitions. The embedded SL BPF shows the center frequency of 60.8 GHz, BW of 4.1% and insertion loss of 3.74 dB. The gain and 3 dB beam width of the fabricated 2 x 2 array patch antenna are 7 dBi and 36 degrees, respectively. The assembled LTCC 61 GHz Tx SiP module achieves an output power of 10.2 dBm and an up conversion gain of 7.3 dB. Because of the integrated BPF, an isolation level between a local oscillation (LO) and RF signal is below 26.4 dBc and the spurious level is suppressed by lower than 22.4 dBc. By using a 61 GHz receiver (Rx) consisting of off the shelf modules, wireless communication test was demonstrated by comparing measured IF spectrums at the Tx and Rx part.
author_names: Young Chul Lee

Chul Soon Park
title: LTCC based monolithic system in package (SiP) module for millimeter wave applications
year: 2016

abstract: Silicon interposers are providing interesting alternatives to organic packages for the fabrication of complex system in package (SIP) modules in particular for RF application. Among the advantages of this technology are the capability to fabricate fine pitch redistribution layers and to embed inside the interposer some high quality passive elements very close to the active chips resulting in a highly integrated solution. To keep the technology at a reasonable cost these last add on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. In this work we present the design and the fabrication of a high resistive silicon interposer conceived for hosting a functional RF SIP transceiver including a Front End Module (FEM) a Dual Band Dual Mode Power Amplifier working at 400 and 900 MHz and some embedded planar and 3D inductors. The interposer consists in symmetrical stack with one thick level of copper RDL on each side of the 200 um thin HR silicon substrate and connected with through silicon via last (TSV last) The inductors are built with no additional metallization level. For the inductors development, a dedicated test vehicle was first designed to study different designs including planar spirals and 3D solenoids and torus. Simulation work was first carried out for dimensioning the structures to target inductance values in the range of 0.5 to 10 nH and high quality factor greater than 20. We present the process used for the fabrication, in particular the realization of the thick copper RDL layers on both sides of the interposer and the of the TSV last module. Physical characterization are presented showing the integrity and the good control of the technology. DC and RF electrical measurements assess the performances achieved for the different inductor variants exhibiting low resistance, constant inductance up to 5 GHz and factor of quality higher than 30. The functional RF transceiver SIP module will be then presented. The architecture is an extremely compact multi chip module composed of four actives CMOS chips (VGA, VCO, modulator and the PA) stacked by flip chip with Cu/SnAg ubumps on the HR silicon interposer and surrounded by a hundred of passive SMD components. With this technology the footprint of the module is reduced by a factor of 2 in comparison with the same module made on a uPCB substrate. The signals and ground are fed through the thick copper RDL lines and the TSVs from LGA pads present on the backside of the interposer for assembly on a test board. Different design configurations are made on the same wafer that include some version using only SMD inductors and some using 2.5 and 3D inductors in order to compare the corresponding performances. Other test structures are also present like filters and individual inductors for DC and RF characterization. We will finally present the resulting performances obtained from this SIP integration.
author_names: Gabriel Pares

Michel Jean-Philippe

Deschaseaux Edouard

Ferris Pierre

Serhan Ayssar

Giry Alexandre
title: Highly Compact RF Transceiver Module Using High Resistive Silicon Interposer with Embedded Inductors and Heterogeneous Dies Integration
venue: 2019 IEEE 69th Electronic Components and Technology Conference (ECTC)
year: 2019

abstract: In this paper, a new structure of power electronic package is addressed. The package structure has high process integration including package assembly and substrate process. Hence, good capability for heterogeneous process integration is very important. To apply the new structure on power SiP module, an integration design of power SiP module that involved an embedded low side MOS (LMOS) an embedded high side MOS (HMOS) and an embedded CMOS controller is demonstrated. The performance of thermal dissipation and power efficiency is better than using power QFN (PQFN) solution. For overall package size, the new structure is also smaller than conventional power package such as PQFN.
author_names: Hung-Chun Kuo

P Chen

C T Chiu

C C Wang

Kay S Essig
title: High efficiency power electronic module with embedded die
venue: 2016 IEEE CPMT Symposium Japan (ICSJ)
year: 2016

abstract: This paper presents a cost effective area IO DRAM (aDRAM)/logic integration implemented with CLC (chip laminate chip) based system in a package (SiP) technology. By inserting 512 area IOs into the area IO DRAM, the bandwidth of the area IO DRAM can achieve 10GB/s when working under 166MHz. An interface module with configurable IO width was also developed to make this implementation platform able to be adapted by various applications. A performance analysis, including bandwidth and power is also presented in this paper. It is demonstrated that area IO DRAM/logic integration with SiP technology provides significant cost effective implementation methodology compared with embedded DRAM and off chip DRAM.
author_names: Anru Wang

Wayne Wei-Ming Dai
title: Area IO DRAM/logic integration with system in a package (SiP)
venue: Proceedings of the ASP DAC 2005. Asia and South Pacific Design Automation Conference, 2005.
year: 2005

abstract: The paper presents a cost effective area IO DRAM (aDRAM)/logic integration implemented with CLC (chip laminate chip) based system in a package (SiP) technology. By inserting 512 area IOs into the aDRAM, the bandwidth of the area IO DRAM can achieve 10 GB/s when working under 166 MHz. An interface module with configurable IO width was also developed to make this implementation platform adoptable by various applications. A performance analysis, including bandwidth and power, is also presented. It is demonstrated that area IO DRAM/logic integration with SiP technology provides a significant cost effective implementation methodology compared with embedded DRAM and off chip DRAM.
author_names: A Wang

Wayne Wei-Ming Dai
title: Design and Analysis of Area IO DRAM/Logic Integration with System in a Package(SiP)
venue: ISQED
year: 2005

abstract: The paper presents a cost effective area IO DRAM (aDRAM)/logic integration implemented with CLC (chip laminate chip) based system in a package (SiP) technology. By inserting 512 area IOs into the aDRAM, the bandwidth of the area IO DRAM can achieve 10 GB/s when working under 166 MHz. An interface module with configurable IO width was also developed to make this implementation platform adoptable by various applications. A performance analysis, including bandwidth and power, is also presented. It is demonstrated that area IO DRAM/logic integration with SiP technology provides a significant cost effective implementation methodology compared with embedded DRAM and off chip DRAM.
author_names: Anru Wang

Wayne Wei-Ming Dai
title: Design and analysis of area IO DRAM/logic integration with system in a package (SiP)
venue: Sixth international symposium on quality electronic design (isqed'05)
year: 2005

abstract: This paper presents a compact multi channel receiver front end using system in package (SiP) integration technology. In the circuit linking design, a power divider network is introduced to keep the amplitude consistency of the local oscillator (LO) signal for each channel. The embedded low temperature co fired ceramic (LTCC) RF filter equipped with two transmission zeros is developed by using substrate integrated waveguide (SIW) technology and its design and tuning techniques are discussed. Based on a viable LTCC SiP structure and micro packaging technology, the receiver front end module is fabricated and all the functional devices are integrated on a single substrate. The measured results indicate that the module has high selectivity as well as the great conversion gain and low noise figure of 50 dB and 2.8 dB respectively. The overall size of the three channel module is about 36 mm x23 mm x 3 mm.
author_names: Yujin Zhou

Anfeng Sun

Jun Zhou

Ya Shen
title: A compact multi channel receiver front end using SiP integration technology on LTCC substrate for wireless communications
venue: 2015 International Conference on Wireless Communications Signal Processing (WCSP)
year: 2015

abstract: In this paper, using low temperature co fired ceramic(LTCC) based system in package(SiP) technology, a very compact power amplifier LTCC module was designed, fabricated, and then characterized for 60 GHz wireless transmitter applications. In order to reduce the interconnection loss between a LTCC board and power amplifier monolithic microwave integrated circuits(MMIC) bond wire transitions were optimized and high isolated module structure was proposed to integrate the power amplifier MMIC into LTCC board. In the case of wire bonding transition, a matching circuit was designed on the LTCC substrate and interconnection space between wires was optimized in terms of their angle. In addition, the wire bonding structure of coplanar waveguide type was used to reduce radiation of EM fields due to interconnection discontinuity. For high isolated module structure, DC bias lines were fully embedded into the LTCC substrate and shielded with vias. Using 5 layer LTCC dielectrics, the power amplifier LTCC module was fabricated and its size is The fabricated module shows the gain of 10 dB and the output power of 11 dBm at P1dB compression point from 60 to 65 GHz.
author_names: Young-Chul Lee
title: A Very Compact 60 GHz LTCC Power Amplifier Module
year: 2006

abstract: This paper brings into light the first prototype miniaturized system in package (SiP) Microsystems built for wireless body area network medical devices which mandate low power consumption and extreme packaging miniaturization. Specifically, this paper focuses on the scenario for a 3D SiP module for wearable demonstrators, namely hearing aids and insulin pups, with an active antenna integrated on top of the individual 2D SiPs. The whole 3D SiP is assembled on the end user device PCB. The presented paper describes in detail all manufacturing steps for the realization of the 3D SiP and all technology developments achieved to reach this goal. Firstly, a 2 layer SiP substrate has been successfully produced with 35 mm ultra fine line copper structuring in conjunction with 100 mm blind vias using semi additive technology. Subsequently, assembly technologies for heterogeneous BAN components were further developed in order to achieve the placement of the tiny IF SAW filters and BAW resonators on the substrate and to implement mixed assembly of soldered passives with fluxed chip packages. Finally, the paper highlights the embedding technology employed in the project for the manufacturing of 3D SiP modules on 9"x12" large panels, as well as the stacking technology for the realization of the 3D SiP microsystems. The whole 3D SiP module has a very small size of 3.48 mm x 3.48 mm x 1.5 mm.
author_names: Dionysios Manessis

A Podlasly

Andreas Ostmann

Rolf Aschenbrenner

Klaus-D Lang
title: Large scale manufacturing of embedded subsystems in substrates and a 3D stacking approach for a miniaturised medical system integration
venue: 2013 Eurpoean Microelectronics Packaging Conference (EMPC)
year: 2013