Query: FPGA Based Digital Magnetic Field Detection System

Candidate papers:

abstract: This paper presents a digital magnetic field detection system, which can collect and analyze the remote sensing data by using the analog to digital converters (ADCs) The proposed digital magnetic field detection system contains two different types of digital pulse width modulation (PWM) ADCs by using the complementary metal oxide semiconductor (C MOS) mixed signal technology and the field programmable gate array platform (FPGA) The 12 bit digital PWM delta sigma \Delta\Sigma$ ADC is implemented in 180nm CMOS mixed signal technology and achieves the signal to noise distortion ratio (SNDR) the spurious free dynamic range (SFDR) and the effective number of bits (ENOB) are 70.68dB, 92.62dB and 11.44 bit with a supply voltage of 1.2V and at a sampling rate of 58.82kS/s. The digital PWM successive approximation register (SAR) ADC is based on FPGA to reduce the interference in the workpiece magnetic field to enhance reliability. Proposed digital PWM ADCs can be combined with a Hall effect sensor to measure the magnitude of a magnetic field without using the microcontroller, which are widely used for proximity sensing, positioning, speed detection, and current sensing applications.
author_names: Hua Fan

Jingxuan Yang

Jia Zhang

Kelin Zhang

Dezhi Xing

Quanyuan Feng
title: FPGA Based Digital Magnetic Field Detection System
venue: IGARSS 2020 2020 IEEE International Geoscience and Remote Sensing Symposium
year: 2020

abstract: Transcranial magnetic stimulation (TMS) a popular technology, acts on the brain by using a pulse magnetic field to cause a series of physiological and biochemical reactions. In order to detect the magnetic field generated by the TMS coil with high speed and multi channel performance, a novel magnetic field detection system based on a field programmable gate array (FPGA) is designed and implemented. The detection system includes an induction coil array, a data acquisition (DAQ) card, and upper computer monitor software. The DAQ card contains analog signal processing circuits, a multiplexer, an analog to digital converter, and a FPGA with a high speed, parallel, and switching idea. The system can sample at a rate of 500 ksps, with 14 bit resolution and 12 channels. The three dimensional (3D) magnetic field can be monitored on the screen with a waveform display and 3D magnetic field vector display. The DAQ card has a good signal noise and distortion and cross talk of 88.35 dB and 79.69 dB, respectively. Compared with the NI DAQ card, the proposed system has a relative error smaller than 1.81% and a mean square error smaller than 2.89 x 10 6, which verifies that the proposed detection system has a good performance. The multi channel high speed magnetic field detection system provides an important platform for the study of TMS in medical, engineering, and other fields.
author_names: Hui Xiong

Chunhou Zheng

Jin-Zhen Liu
title: A multi channel high speed magnetic field detection system based on FPGA for transcranial magnetic stimulation.
venue: The Review of scientific instruments
year: 2018

abstract: We describe the development and implementation of a multifunction digital receiver suitable for magnetic resonance imaging with capability of real time frequency detection and compensation. The digital receiver consists primarily of firmware modules that combine the functionalities of signal acquisition, frequency detection and compensation, and data correction and image reconstruction. The receiver was developed based on a single multiple input multiple output radio frequency electronic board equipped with a reconfigurable Field Programmable Gate Array (FPGA) device. A simple and practical algorithm was developed and implemented on the FPGA to accelerate the data processing for frequency determination. The simplified frequency detection and the higher system integration enable the receiver to reduce dramatically the time for frequency detection and compensation. With this receiver, we are able to detect the frequency of short duration signals in the bandwidth of 10 MHz centered at 400 MHz within 75 ns after the signal acquisition. We describe the designs of the key FPGA modules and how these modules integrate into a multifunction receiver. We also present testing data that validate the simplified algorithm for frequency determination, demonstrate frequency detection and compensation, and demonstrate how real time data correction is performed during image acquisition and reconstruction.
author_names: Limin Li

Alice M Wyrwicz
title: A multifunction digital receiver suitable for real time frequency detection and compensation in fast magnetic resonance imaging.
venue: The Review of scientific instruments
year: 2019

abstract: During operation of present fusion devices, the plasma facing components (PFCs) are exposed to high heat fluxes. Understanding and preventing overheating of these components during long pulse discharges is a crucial safety issue for future devices like ITER. Infrared digital cameras interfaced with complex optical systems have become a routine diagnostic to measure surface temperatures in many magnetic fusion devices. Due to the complexity of the observed scenes and the large amount of data produced, the use of high computational performance hardware for real time image processing is then mandatory to avoid PFC damages. At Tore Supra, we have recently made a major upgrade of our real time infrared image acquisition and processing board by the use of a new field programmable gate array (FPGA) optimized for image processing. This paper describes the new possibilities offered by this board in terms of image calibration and image interpretation (abnormal thermal events detection) compared to the previous system.
author_names: Vincent Martin

Gwenael Dunand

Victor Moncada

M Jouve

J M Travere
title: New field programmable gate array based image oriented acquisition and real time processing applied to plasma facing component thermal monitoring.
venue: The Review of scientific instruments
year: 2010

abstract: Small solid state photomultipliers (SSPMs) are an alternative scintillator light detection technology to traditional photomultiplier tubes that offer advantages such as lower bias voltages and insensitivity to magnetic fields. A digital spectrometer using a commercially available SSPM was constructed and characterized at Oregon State University as a prototype for small, highly mobile, low power, robust spectroscopy devices. The SSPM has over 19,000 microcells in a photo sensitive area of 6.32 x 6.32 mm and was coupled to 6 x 6 x 10 mm reflectively coated CsI(Tl) crystals. The rest of the spectrometer consists of a fast preamplifier and 200 MHz, 12 bit digital pulse processor based around a field programmable gate array (FPGA) The efficiency, resolution, linearity, and peak to Compton ratio of the system were characterized.
author_names: Eric M Becker

Abi T Farsoni

Abdulsalam M Alhawsawi

Bemnet Alemayehu
title: Small Prototype Gamma Spectrometer Using CsI(Tl) Scintillator Coupled to a Solid State Photomultiplier
venue: IEEE Transactions on Nuclear Science
year: 2013

abstract: The small animal positron emission tomography (PET) is dedicated to small animal imaging, which requires high position and energy precision, as well as good flexibility and efficiency of the electronics. This paper presents the design of a digital signal processing logic for a marmoset brain PET system based on lutetium yttrium oxyorthosilicate (LYSO) crystal arrays, SiPMs, and the resistive network readout method. We implement 32 channel signal processing in a single Xilinx Artix 7 Field Programmable Gate Array (FPGA) The logic is designed to support four online modes which are regular data processing mode, flood map construction mode, energy spectrum construction mode, and raw data mode. Several functions are integrated, including 2 D) raw position calculation, crystal locating, events filtering, and synchronization detection. Furthermore, a series of online corrections is also integrated, such as photon peak correction to 511 keV and time measurement result correction with crystal granularity. A gigabit ethernet interface is utilized for data transfer, look up tables (LUTs) configuration, and command issuing. The pipeline logic works at 125 MHz with a signal processing capability beyond the required data rate of 1 000 000 events/s/channel. A series of initial tests is conducted. The results indicate that the logic design meets the application requirement.
author_names: Jiaming Lu

Lei Zhao

Kairen Chen

Peipei Deng

Bowen Li

Shubin Liu

Qi An
title: Real Time FPGA Based Digital Signal Processing and Correction for a Small Animal PET
venue: IEEE Transactions on Nuclear Science
year: 2019

abstract: The demand for digital down converter (DDC) is the cornerstone technology in software radio standard, which converts the frequency translation, especially in down converted complex output. This paper briefs design and implementation of reconfigurable DDC that can process input bandwidth about 70MHz to 270 KHz to meet the specifications of Global System for Mobile (GSM) receiver. The proposed design consists of COordinate Rotation Digital Computer (CORDIC) processor and multi rate decimation filters. By using CORDIC processor the design has achieved maximum spurious free dynamic range (SFDR) Moreover, implementation of multi rate decimation filter requires small hardware resources and improves the performance of the DDC design. The proposed DDC has been designed and tested on Xilinx Kintex 7 field programmable gate array (FPGA) board. The advantages of using this flexible DDC can produce a specific output. Experimental results show that the proposed DDC is operated on high processing speed with optimum area to provide cost effective solution in mobile application.
author_names: Debarshi Datta

Partha Mitra

Himadri Sekhar Dutta
title: FPGA Based Digital Down Converter for GSM Application
venue: 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)
year: 2020

abstract: Field Programmable Gate Array's (FPGAs) are especially popular for prototyping integrated circuits designs. This paper describes the simulation of Peak detector and counter circuit based on FPGAs technology. Complete circuit was designed by writing appropriate program in Very High Speed Integrated Circuit Hardware Description Language (VHDL) ISE foundation 6.1. The designed system was simulated using Modelsim simulator SE f.A maximum frequency of 190.513MHZ was reached with a minimum period of 5.249ns. 12 out of 3584 slices were used. Our system can be implemented on Xilinx Spartan 3 XC3S400~4pq208.
author_names: Amit Pal Singh
title: Design and Simulation of FPGA based Digital System for Peak Detection and Counting
year: 2013

abstract: Embedded computer vision based smart systems raise challenging issues in many research fields, including real time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA) based platforms, supporting massive data parallelism, offer large opportunities to match real time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.
author_names: Cedric Bourrasset

Luca Maggiani

Jocelyn Serot

Francois Berry
title: Dataflow object detection system for FPGA based smart camera
venue: IET Circuits Devices Syst.
year: 2016

abstract: This paper presents the software and hardware design aspects of the first digital MIT system. Excitation signal generation, receiving signal demodulation and channel multiplexing control are all implemented inside a Xilinx FPGA (Spartan III) The image reconstruction software is written in VC+ and real time images up to 200 frames /second can be achieved for 50K Hz excitation. Fitted with an 8 coil MIT sensor, the digital system delivers a much higher signal to noise ratio (SNR) and image stability compared to the analog system previously designed. Metallic samples of different shapes and arrangements were imaged, which confirms the performance of the system.
author_names: Wuliang Yin

Guang Chen

Jian Jiang

Ziqiang Cui
title: The design of a FPGA based digital magnetic induction tomography (MIT) system for metallic object imaging
venue: 2010 IEEE Instrumentation Measurement Technology Conference Proceedings
year: 2010