Query: High k Gate Dielectrics

Candidate papers:

abstract: Recent advances in flexible and stretchable electronics (FSE) a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet of things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin film fabrication techniques for high k (or high capacitance) gate dielectrics when integrated with FSE compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high k dielectrics over low k ones in TFT applications were elaborated. Next, after presenting the design and properties of high k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.
author_names: Binghao Wang

Wenhao Huang

Lifeng Chi

Mohammed Al-Hashimi

Tobin J Marks

Antonio F Facchetti
title: High k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.
venue: Chemical reviews
year: 2018

abstract: We investigated the effects of various high k gate dielectrics as well as microwave annealing (MWA) calcination and a postcalcination oxygen plasma treatment on the electrical properties and stability of electrospun indium gallium zinc oxide (IGZO) nanofiber (NF) based field effect transistors (FETs) We found that the higher the dielectric constant of the gate dielectric, the better the electric field is transferred, resulting in the better performance of the IGZO NF FET. In addition, the MWA calcined IGZO NF FET was superior to the conventional furnace annealing calcined device in terms of the electrical properties of the device and the operation of resistor loaded inverter, and it was proved that the oxygen plasma treatment further improved the performance. The results of the gate bias temperature stress test confirmed that the MWA calcination process and postcalcination oxygen plasma treatment greatly improved the stability of the IGZO NF FET by reducing the number of defects and charge traps. This verified that the MWA calcination process and oxygen plasma treatment effectively remove the organic solvent and impurities that act as charge traps in the chemical analysis of NF using X ray photoelectron spectroscopy. Furthermore, it was demonstrated through scanning electron microscopy and ultraviolet visible spectrophotometer that the MWA calcination process and postcalcination oxygen plasma treatment also improve the morphological and optical properties of IGZO NF.
author_names: Seong-Kun Cho

Won-Ju Cho
title: Performance Enhancement of Electrospun IGZO Nanofiber Based Field Effect Transistors with High k Gate Dielectrics through Microwave Annealing and Postcalcination Oxygen Plasma Treatment
venue: Nanomaterials
year: 2020

abstract: Abstract A layer by layer, in situ H2 plasma treatment in each cycle of atomic layer deposition, referred to as "atomic layer hydrogen bombardment" (ALHB) is applied to improve electrical properties of ZrO2 high k gate dielectrics. The H2 plasma bombardment facilitates the adatom migration due to energy delivery to each as deposited monolayer from the H2 plasma. In addition, the H2 plasma treatment contributes to the removal of precursor ligands for the release of steric hindrance. Hence the ALHB treatment leads to film densification and suppression of oxygen vacancies of ZrO2, as evidenced by X ray reflectivity and X ray photoelectron spectroscopy characterizations. As a result, ~90% decrease of gate leakage current is achieved in the ZrO2 high k gate dielectrics with capacitance equivalent thicknesses of ~1.3 nm and ~0.6 nm in metal insulator semiconductor and metal insulator metal capacitors, respectively. The results manifest that the ALHB treatment is a promising technique to enhance dielectric and electrical characteristics of nanoscale thin films, for further progress of advanced devices such as sensors, solar cells, memories, and nanoelectronics.
author_names: K T Huang

Teng-Jan Chang

Chun-Yuan Wang

Sheng-Han Yi

Chin I Wang

Yu-Sen Jiang

Yu-Tung Yin

Hsin-Chih Lin

Miin-Jang Chen
title: Leakage current lowering and film densification of ZrO2 high k gate dielectrics by layer by layer, in situ atomic layer hydrogen bombardment
year: 2020

abstract: The total ionizing dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al<sub>2</sub>O<sub>3</sub> gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage <inline formula> <tex math notation="LaTeX"$V_{\text {th} /tex math>/inline formula> shifts and subthreshold stretchout <italic>SS</italic> indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and <inline formula> <tex math notation="LaTeX"$I_{d} /tex math>/inline formula> <inline formula> <tex math notation="LaTeX"$V_{\text {gs} /tex math>/inline formula> measurements from cryogenic to high temperatures show the important role of defects in the Al<sub>2</sub>O<sub>3</sub> gate dielectric to the TID response. Radiation induced hole trapping is attributed to oxygen vacancies in the Al<sub>2</sub>O<sub>3</sub> The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near interfacial Al<sub>2</sub>O<sub>3</sub> Analysis of the temperature dependence of <inline formula> <tex math notation="LaTeX"$V_{\text {th} /tex math>/inline formula> and <italic>SS</italic> suggests that the rate at which electrons leave the Al<sub>2</sub>O<sub>3</sub> during a positive to negative gate bias sweep is higher than the rate at which they enter during a negative to positive gate bias sweep.
author_names: Stefano Bonaldo

En Xia Zhang

Simeng E Zhao

Vamsi Putcha

Bertrand Parvais

Dimitri Linten

Simone Gerardin

Alessandro Paccagnella

Robert A Reed

Ronald D Schrimpf

Daniel M Fleetwood
title: Total Ionizing Dose Effects in InGaAs MOSFETs With High k Gate Dielectrics and InP Substrates
venue: IEEE Transactions on Nuclear Science
year: 2020

abstract: The gate oxide layer in vertical double diffused metal oxide semiconductor transistors (VDMOS) plays an important role for the failure of device in harsh radiation environment. The effect of strike of an ion on VDMOS and its effect on the oxide layer with high k dieletric has been observed in this work. Single event gate rupture (SEGR) event for conventional and superjunction VDMOS with SiO2 Si3N4 stack structure is studied in radiation environment. Atlas EDA tool from Silvaco is used for device simulation. It has been observed that the superjunction VDMOS device with SiO2Si3N4 stacks provide better susceptibility for SEGR as compared to the conventional device. The SEGR susceptibility in proposed device is increased by 133% and the area specific on resistance is reduced for a linear energy transfer (LET) of 98 MeVcm2/mg. The physical mechanism regarding SEGR in superjunction VDMOS with SiO2 Si3N4 stack is explained. Such technique can hardened the proposed VDMOS structures that are used in designing of DC to DC converters for satellite in space radiation environment.
author_names: Sanjeev M Ranjan

Saikat Majumder

Alok Naugarhiya
title: SEGR Hardened Superjunction VDMOS with High K Gate Dielectrics
venue: 2020 International Conference on Power Electronics IoT Applications in Renewable Energy and its Control (PARC)
year: 2020

abstract: In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La 2 O 3 is the best gate dielectric material followed by HfO 2 and ZrO 2 It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results
author_names: Ankit Dixit

Navneet Gupta
title: Simulations of the CNFETs using different high k gate dielectrics
year: 2020

abstract: Despite the recent progress in SiC power MOSFET technology and its commercialization, the defective MOS interface still hampers the exploitation of the full potential of these devices. We present results using our high k gate stack technology that shows significantly reduced density of interface states (Dit) along with superior threshold voltage (VTH) stability for low voltage SiC power MOSFETs. The findings indicate virtually no VTH shift during static characterization as function of the starting gate voltage and its ramp. Furthermore, dynamic switching results show virtually no threshold voltage shift for $V_{GS,start} \gt 12$V.
author_names: Stephan Wirths

Yulieth Arango

Andrei Mihaila

Marco Bellini

Gianpaolo Romano

Giovanni Alfieri

Manuel Belanche

Lars Knoll

E Bianda

Elena Mengotti
title: Vertical Power SiC MOSFETs with High k Gate Dielectrics and Superior Threshold Voltage Stability
venue: 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)
year: 2020

abstract: As the technology is scaled down, short channel effects such as Vt variation, leakage current, gate oxide tunneling become predominant due to the reduction in gate oxide thickness. When the device is scaled down beyond 22 nm technology, the use of SiO2 as gate oxide increases tunneling current, thereby increase in power consumption and reduction in reliability of devices. Equivalent gate oxide thickness can be reduced by using high k dielectric materials. FinFET(a type of DG MOSFET) integrated with a high k gate dielectric is a promising device in the subthreshold region. Simulations were performed using Sentarus TCAD. The parameters such as threshold voltage, OFF current, transconductance were analyzed. Simulation results clearly state that Short Channel Effects have been reasonably controlled by using high k spacer material. Index terms FinFET, Short Channel Effects, Effective Oxide Thickness(EOT),High k gate dielectric, SiO2, HfO2
author_names: Meenakshi Kailasam

Murugesan Govindasamy
title: Impact Of High K Gate Dielectrics On Short Channel Effects Of DG N Finfet
year: 2020

abstract: Because the dielectric constant (K) the leakage current density (Jg) and the interfacial state density (Dit) are critical to high K gate dielectrics, the layer by layer, in situ atomic layer bombardment (ALB) is proposed and explored to enhance these electrical properties in this study. The in situ helium/argon plasma bombardment was performed layer by layer in each cycle of atomic layer deposition (ALD) for preparing high K gate dielectrics. As compared with the untreated high K layer, the ALB treatment contributes to a significant reduction in Jg by ~3 orders of magnitude, together with an ~11% increase of K value and a decrease of Dit, of high K gate dielectrics. The suppressed Jg and the enhanced K value are ascribed to an increase of film density and a decrease of oxygen vacancies in the ZrO2 layer by the ALB treatment. The atomic annealing effect due to the ALB technique contributes to the decrease of Dit. The result demonstrates that the ALD together with the ALB technique is highly effective to
author_names: Teng-Jan Chang

Wei-Hao Lee

Chin I Wang

Sheng-Han Yi

Yu-Tung Yin

Hsin-Chih Lin

Miin-Jang Chen
title: High K Gate Dielectrics Treated with in Situ Atomic Layer Bombardment
venue: ACS Applied Electronic Materials
year: 2019

abstract: Abstract Low temperature processable gate dielectrics with high dielectric constants, low leakage current, and good electrical/mechanical stabilities are largely pursued in diverse electronics including flexible transistors, wearable sensors, integrated logic circuits, and various optoelectronic devices. Here, we report low temperature photochemically activated gate dielectrics based on a lanthanum oxide aluminum oxide (La2O3 Al2O3 or LAO) alloy system for a utilization in flexible metal oxide thin film transistors (TFTs) With proper alloying of La2O3 and Al2O3 at an optimal ratio, synergetic effects could be achieved from both gate dielectric materials, high dielectric constant and excellent insulating properties. With a La:Al ratio of 2:8, LAO gate dielectrics with high dielectric constant (k 10.72) low surface roughness (0.517 nm) low leakage current density (1.7 x 10 10 A cm 2 @2 MV cm 1) and high breakdown field ~4.8 MV cm 1) were achieved. By utilizing the photo annealed LAO as a gate dielectric, low operating voltage =5 V) solution processed indium gallium zinc oxide (IGZO) TFTs having saturation mobility of 8.5 3.25 cm2 V 1s 1, linear mobility of 10.8 2.03 cm2 V 1s 1, subthreshold slope of 0.228 V dec 1, and on/off ratio of ~105 are demonstrated. Furthermore, the fabricated IGZO TFTs exhibited negligible hysteresis characteristics
author_names: Jaeyoung Kim

Minho Kim

Youngjin Kang

Kyung-tae Kim

Jae Sang Heo

Sung Kyu Park

Yong-Hoon Kim
title: Photoactivated high k lanthanum oxide aluminum oxide (La2O3 Al2O3) alloy type gate dielectrics for low voltage operating flexible transistors
year: 2020