Query: High Frequency RF Model of NMOS Transistors on 45nm CMOS SOI technology

Candidate papers:

abstract: Nanoscale CMOS technology is an excellent platform for implementing single chip systems because of its low manufacturing cost and integration capability with digital circuits [1] Cutoff frequency fT and maximum oscillation frequency fMAX of advanced nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET) have surpassed 200 GHz mark, enabling microwave and mm wave circuit operation [2] Implementing microwave and mm wave circuits with first time success remains elusive due to limited accuracy of the available device models on conductive Si substrates. Accordingly, comprehensive deep sub 100 nm MOSFET models that accurately capture DC, RF (including nonlinear) and noise characteristics of transistors are of great demand. Device modeling requires the knowledge and expertise in several distinct areas including mathematical modeling, device physics, high frequency and microwave measurement, electro thermal analysis, noise analysis, programming, and statistics. Several MOSFET models have already been fully or partially developed [3] [6] The widely used threshold voltage based BSIM model employs hundreds of parameter many of them empirical to capture linear and nonlinear RF and noise behavior of modern submicron MOSFET devices. Extraction of so many parameters is cumbersome and has led to the development of many BSIM models with insufficient accuracy. The surface potential based Phillips MOS Model utilizes fewer empirical parameters compared to BSIM model. With over 200 parameters to be extracted, however, the model development is still an enormous challenge given the short time to market for advanced CMOS technologies. Another MOSFET model is the so called virtual source (VS) model, which uses about ten parameters to describe the nonlinear DC performance of short channel transistors. This model assumes a semi ballistic transport mechanism inside nanoscale channels of MOSFETs, leading to a good modeling accuracy [4][7] The VS model, however, has to be supplemented with bias and geometry dependent parasitic resistances, capacitances, and inductances to become suitable for deployment at high frequencies. To date, the VS model with high frequency capability has been demonstrated for GaN FETs [8] This model, however, is still unproven for predicting the nonlinear RF to mm wave behavior of MOSFETs. Furthermore, it has no apparent advantage in predicting the noise behavior of nanoscale MOSFETs at high frequencies over other available MOSFET models.
author_names: Yanfei Shen
title: High Frequency RF Model of NMOS Transistors on 45 nm CMOS SOI technology
year: 2016

abstract: We report record RF performance in 45 nm silicon on insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating body NFET and PFET with nearby wiring parasitics (i.e. gate to contact capacitance) included after de embedding, thus representing FET performance in a real design. The measured fT's are the highest ever reported in a CMOS technology. Body contacted FETs are also analyzed that have layout optimized for high frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self gain.
author_names: Sungjae Lee

Basanth Jagannathan

Shreesh Narasimha

A I Chou

Noah D Zamdmer

J Johnson

Richard W Williams

Lawrence F Wagner

Jonghae Kim

Jean-Olivier Plouchart

John J Pekarik

Scott K Springer

G Freeman
title: Record RF performance of 45 nm SOI CMOS Technology
venue: 2007 IEEE International Electron Devices Meeting
year: 2007

abstract: A 45 nm logic technology is described that for the first time incorporates high k metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low k ILD, low cost 193 nm dry patterning, and 100% Pb free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
author_names: Kaizad Mistry

Craig Allen

Chris Auth

B Beattie

D Bergstrom

M Bost

M Brazier

Marc Buehler

Annalisa Cappellani

Robert Chau

Chae Hyoung Choi

G Ding

Kevin Fischer

Tahir Ghani

Rohit Grover

W Han

Dennis G Hanken

Michael L Hattendorf

J He

Jeff Hicks

R Huessner

D Ingerly

Pulkit Jain

R James

L Jong

S Joshi

C Kenyon

Kelin J Kuhn

Kwang-Woon Lee

Honghai Liu

J Maiz

B G Mclntyre

Peter Moon

Johan Neirynck

Sangwoo Pae

C Parker

D Parsons

Chetan Prasad

Leonard C Pipes

M Prince

P Ranade

T Reynolds

Justin S Sandford

Lucian Shifren

Javier Sebastian

J Seiple

D Simon

S Sivakumar

P Smith

C Thomas

Thomas H Troeger

Peter Vandervoorn

S Williams

Keith Zawadzki
title: A 45nm Logic Technology with High k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb free Packaging
venue: 2007 IEEE International Electron Devices Meeting
year: 2007

abstract: Predictive MOSFET model is critical for early circuit design research. In this work, a new generation of predictive technology model (PTM) is developed, covering emerging physical effects and alternative structures. Based on physical models and early stage silicon data, PTM of bulk and double gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10% for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime
author_names: Wei Zhao

Yu Cao
title: Predictive Technology Model for Nano CMOS Design Exploration
venue: 2006 1st International Conference on Nano Networks and Workshops
year: 2006

abstract: A novel design technique is proposed for storage elements which are insensitive to radiation induced single event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.
author_names: Th Calin

Michael Nicolaidis

Raoul Velazco
title: Upset hardened memory design for submicron CMOS technology
year: 1996

abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO TERMINAL MOS STRUCTURE 3. THE THREE TERMINAL MOS STRUCTURE 4. THE FOUR TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION IMPLANTED CHANNELS 6. SMALL DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION LARGE SIGNAL MODELING 8. SMALL SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH FREQUENCY SMALL SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION
author_names: Yannis P Tsividis
title: Operation and modeling of the MOS transistor
year: 1987

abstract: Fully depleted (FD) tri gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non planar devices reported so far, for correctly targeted threshold voltages. The tri gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 2 times greater than either single gate SOI or non planar double gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri gate transistors to conventional bulk CMOS device at the same technology node, these non planar devices are found to be competitive with similarly sized bulk CMOS transistors. Furthermore, three dimensional (3 D) simulations of tri gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri gate device remains fully depleted, with near ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri gate transistor could pose a viable alternative to bulk transistors in the near future.
author_names: Brian Seamus Doyle

Suman Datta

Mark L Doczy

Scott Hareland

Ben Jin

Jack T Kavalieros

Thomas D Linton

Anand S Murthy

Rafael Rios

Robert Chau
title: High performance fully depleted tri gate CMOS transistors
venue: IEEE Electron Device Letters
year: 2003

abstract: Mobile system on chip (SoC) technologies require high quality analog active and passive components along with low power CMOS and dense SRAM. However, area scaling for both the SRAM bit cell and analog CMOS circuits is becoming increasingly difficult due to the impact of transistor random variation. To avoid added cost, co optimizing the process for low random variation along with high performance and low power is required. We report a 45 nm lowpower technology with significantly reduced random variation for high yielding 0.255 mum2 SRAM arrays and analog transistors. Flexible RF and passive components for mobile SoCpsilas are also described. These process techniques enable continued 50% area scaling at 45 nm and beyond.
author_names: Shashank S Ekbote

Kamel Benaissa

Borna Obradovic

Shaorong Liu

Hisashi Shichijo

Frank Hou

T Blythe

Theodore W Houston

S Martin

R Taylor

A D Singh

H Yang

Greg Baldwin
title: 45nm low power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors
venue: 2008 Symposium on VLSI Technology
year: 2008

abstract: The new process module and device architecture options emerging for (sub 45nm CMOS, lead to both opportunities and challenges for analog/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETs) for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for planar bulk CMOS devices, while FinFETs exhibit high voltage gain and excellent matching performance. As a result, FinFETs will be shown to be better suited for analog baseband design and to have acceptable RF performance in the 1 10 GHz range, while planar bulk CMOS outperforms the FinFETs for sub circuits above 10 GHz
author_names: Stefaan Decoutere

Piet Wambacq

Vaidyanathan Subramanian

Jonathan Borremans

Abdelkarim Mercha
title: Technologies for (sub 45nm Analog/RF CMOS Circuit Design Opportunities and Challenges
venue: IEEE Custom Integrated Circuits Conference 2006
year: 2006

abstract: A review of recent results on the low frequency noise in advanced Si based CMOS devices is given. The modeling approaches such as the carrier number and the Hooge mobility fluctuations used for the diagnostic of the noise sources are presented and illustrated through experimental data obtained on modern SOI and Si bulk CMOS generations. For SOI devices fully depleted MOSFET's and double gate structures are focused. The impact of the back gate voltage on the 1/f noise is analyzed. For Si bulk devices, a special emphasis is addressed to the role of gate leakage on both static and LF noise characteristics
author_names: Gerard Ghibaudo

Jalal Jomaah
title: Low Frequency Noise and Fluctuations in Sub 0.1um Bulk and SOI CMOS Technologies
venue: 2006 25th International Conference on Microelectronics
year: 2006