Query: Laser Application in IC and MEMs Fabrication

Candidate papers:

abstract: this research paper introduces the development and principle of the lasers, state the common semiconductor laser fabrication process in detail, and summarize, emphasize the laser application in the IC and MEMs fabrication process. With the help of the lasers, we could improve the lithography, deposition, etching process, and perfect the packaging process.
author_names: Haibin Zhu

Sheng-zong He

Qizheng Ji

Ming Yang

Yu Zhang
title: Laser Application in IC and MEMs Fabrication
venue: 2020 21st International Conference on Electronic Packaging Technology (ICEPT)
year: 2020

abstract: The field of micro electro mechanical systems (MEMS) grew out from the integrated circuit (IC) industry. So far the main fabrication techniques used in MEMS are planar technologies, which set limitations to the sensor/actuator design. Therefore greyscale (3D) technology seems to be the method for fabrication of three dimensional structures in a single lithography and etching step. The idea in fabricating a 3D photoresist structure is the controlled transmission of UV light intensity during the exposure process. The result of this work is to provide a preliminary process solution for the formation of nearly arbitrarily shaped 3D forms in photoresist using Heidelberg Instrument DWL 66FS direct writing lithography tool. For this purpose, the investigation results of the exposure tool possibilities of the photoresist selection for 3D applications and as a real greyscale application, slopes with different angles, which will be used for making a tactile sensor, are provided.
author_names: N Kaste

Alexander Filbert

Ulrich Mescheder

Toomas Rang

G Rang
title: Process development for 3D laser lithography
year: 2014

abstract: MEMS (Micro Electro Mechanical Systems) technology has expanded widely over the last decade in terms of its use in devices and instrumentation for diverse applications. However, access to versatile foundry services for MEMS fabrication is still limited. At INO, the presence of a multidisciplinary team and a complete tool set allow us to offer unique MEMS foundry type services. These services include: design, prototyping, fabrication, packaging and testing of various MEMS and MOEMS devices. The design of a device starts with the evaluation of different structures adapted to a given application. Computer simulation tools, like IntelliSuite, ANSYS or custom software are used to evaluate the mechanical, optical, thermal and electromechanical performances. Standard IC manufacturing techniques such as metal, dielectric and semiconductor film deposition and etching as well as photolithographic pattern transfer are available. In addition, some unique techniques such as on wafer lithography by laser writing, gray scale mask lithography, thick photoresist lithography, selective electroplating, injection moulding and UV assisted moulding are available to customers. The hermetic packaging and a novel patented wafer level micropackaging are also applied. This multifaceted expertise has been utilized to manufacturing of several types of MEMS devices as well as complex instruments including micromirror type devices, microfilters, IR microbolometric detector arrays, complete cameras and multipurpose sensors.
author_names: Christine Alain

Hubert Jerominek

Patrice Topart

Timothy D Pope

Francis Picard

Felix Cayer

Carl Larouche

Sebastien Leclair

Bruno Tremblay
title: Microfabrication services at INO
venue: SPIE MOEMS MEMS
year: 2003

abstract: The advantages of thin film SOI (Silicon on Insulator) technology for MOS circuits compared with thick SOI and bulk silicon MOS techniques are nowadays well known. Among them, we can mention a lower power consumption, better performance on high frequency operation and resistance to irradiation as well as better high temperature characteristics. These advantages in addition to a direct MEMS IC integration make thin film SOI an attractive process for the manufacture of high quality MEMS and MOS integrated circuits for space applications. In this work, we present tridimensional (3 D) self assembled multilayered SOI MEMS structures that can be used (but not limited) as flow sensors, thermal actuators and high frequency inductors. These MEMS consist of layers of Si, Si3N4 and Al deposited at different temperatures, and the final shape of the structure can be very different depending on the number, the nature and the thickness of the layers that are deposited. If the system consists only of one layer of Si, the structure remains flat after the release, whereas in the bilayer case (Si and Si3N4) the structure bends up. This is due to the thermal expansion coefficient of the Si3N4, which is higher than the Si one, and therefore the upper part of the structure contracts more than the lower part resulting in a curved shape. The thermal expansion coefficient of the Al being even greater than the Si3N4 one, we would then expect a larger curvature of the structure in the trilayer case, but considering the Al deposition temperature and the geometry we can demonstrate that the shape is rather flat. To obtain a curly shape in the trilayer structure an additional thermal step is needed. It could be a two minutes RTA (Rapid Thermal Annealing) at 600degC or a lower temperature annealing (432degC) but for a longer time (30 min) In order to make quantitative comparisons with numerical simulations, the final shape of these structures was completely characterized using laser interferometry. Numerical simulations were made using the finite element code Oofelie. This code allows us to simulate the fabrication process in a realistic way adding layers one by one and considering the residual stress of the layers already deposited. In this way, an analysis of intermediate stresses in the different layers can be done, and if it is the case, additional residual stresses that do not have a thermal origin can be included. In order to model accurately the 3 D MEMS final shape, which is characterized by large displacements, the code takes into account the geometric nonlinearity. Numerical simulations are in good agreement with experimental data and with available analytical results. Reliable numerical simulations are very helpful to accelerate the MEMS design phase when complex geometries are involved.
author_names: Carlos Mendez

P De Vincenzo

I Klapka

Veronique Rochus

Francois Iker

Nicolas Andre

J P Raskin
title: 3 D Self assembled SOI MEMS: Fabrication and Numerical Simulation
year: 2005

abstract: In this study, the research of embedded active and passive package is carried out for miniaturized wireless module. We fabricated very small RF module which one bare chip (0.3mm x 0.5mm, SPDT switch IC) and three 0603(0.6mm x 0.3mm, MLCC) passive devices were buried into within 1.85mm x 1.5mm substrate. Used materials were compatible with PCB process such as polymer laminating, dry film patterning, electroless electrolytic copper plating and atmospheric plasma treatment. We studied low pressure bonding process using rheology dependence of polymer on temperature to prevent fracture or crack from embedding chips into PCB. The embedded chip and passives were electrically interconnected by small laser via(30um) and Cu pattern plating process after atmospheric pressure plasma treatment, which revealed an effect on filling of micro via and shape of fine pattern. The interconnection between chip pad and Cu were evaluated by SEM image, which shows Cu pattern of PCB and pad of passive was interconnected without intermetallic formation. However, intermetallic, Cu Sn Ni, formed between passive electrode and plated Cu layer, and molten Sn is segregated along the wall of via hole after reflow. DSC (Differenntial Scanning Calorimetry) analysis was employed to calculate and optimize the amount of curing. Polymer showed maximum 90deg peel strength ~0.7kgf/cm) with Cu pattern when Cu is plated on polymer after pre curing was 80~90% completed. The RF characterization of embedded chip PCB was evaluated by measuring s parameters (S11; return loss and S21; insertion loss) Return loss was below 20dB up to 4GHz. As a results, the embedded chip module is able to be applied for 2~5 GHz frequency application (Bluetooth and WiFi) with small size and good performance.
author_names: Se-Hoon Park

Jong-In Ryu

Jun Chul Kim

N K Kang

Jong Chul Park

Young-Ho Kim
title: Fabrication and characterization of embedded active and passive device for wireless application
venue: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
year: 2010

abstract: In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s parameters (S11; return loss and S21; insertion loss) Insertion loss is less than 0.55 dB in two presented embedded chip board and wire bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire bonding chip board is worse than 20 dB above 2.4 GHz frequency.
author_names: Se-Hoon Park

Jong-In Ryu

Jun-Chul Kim

Je-Hyun Youn

N K Kang

Jong Chul Park
title: The Fabrication and Characterization of embedded switch chip in board for WiFi Application
year: 2008

abstract: This paper describes a kind of silicon based plane spiral inductance coil, whose layout size and fabrication technology process are given. The production of inductance coil adopts the method of an internal down lead produced by ohm contact electrode which is formed by heavily boron diffused and the Al evaporated on the surface of N type high resistivity silicon wafer. Processing the silicon cup on The back of the silicon wafer using MEMS technology, on the basis of thickness reduction of the inductance coil substrate, the porous array substrate of about 5mm thickness is obtained by laser drilling on the underside of the silicon cup, which reduces the vortex of substrate, and greatly improves the Q value of inductance coil. Analyze the effects of series resistance of the coil and metal layer thickness on the Q value in the condition of low frequency and high frequency, and Ansys software is used to simulate the inductance coil current density and magnetic induction intensity, to determine the optimum substrate thickness of inductance coil. The silicon based plane spiralind inductance coil has the advantages of simple manufacturing process and is compatible with IC technology, compared with other manufacturing method, so it has a wide application prospect.
author_names: Gang Li

Xiaofeng Zhao

Dianzhong Wen

Yang Yu
title: Research on Silicon based Planar Spiral Inductance Coil Based on MEMS
year: 2015

abstract: Silicon micromechanics including bulk micromachining and surface micromachining are an emerging field, which are beginning to impact almost every area of science and technology. Since the early days of fiber optics, it has been recognized that micro optics was a fertile ground for the applications of microelectromechanical systems (MEMS) Mechanical movable structures and micromotors can be integrated on silicon using MEMS technology, which is finding its way into both large scale and small scale optical switches, variable optical attenuators, tunable lasers and filters, active equalizers, add/drop multiplexers, optical crossconnects, gain tilt equalizers, data transmitters and many others are beginning to find ubiquitous application in advanced lightwave systems. We are investigating the use of MEMS fabrication technology for applications in optical communications. Also we will describe what they are, how they are built and show how they have the potential to revolutionize lightwave systems. Using silicon microfabrication to produce optical components provides some compelling advantages. First, the silicon surface when treated properly can provide an optical surface of extremely high quality. Second, single crystal silicon allow fabrication of fatigue free devices since it has no dislocation. Third, the electrical properties of silicon allow for the integration of sensors and detectors with extraordinarily high precision. In addition, the require forces provided by microactuators have very limited force capabilities, and often the required displacements in many applications are also quite small, on the order of a wavelength (a few microns) which again provides a good match for the capabilities of MEMS. Finally, the lithographic batch fabrication of these devices, driven and made possible by the infrastructure of the IC industry, provides a relatively inexpensive fabrication method.
author_names: Yali Lu

Jintong Lin
title: Application of MEMS technology in optical communications
venue: SPIE/OSA/IEEE Asia Communications and Photonics
year: 2001

abstract: Currently, MEMS tunable grating draws a lot of attentions due to its promising applications in display, spectrometer, external cavity laser, programmable mask, optical telecommunication, etc. Among phase tunable and incident angletunable grating, period tunable grating distinguishes itself by relative simple structure, ease to fabrication, good performance, and ability to be integrated with IC. In this paper, a novel approach based on compressed period grating is demonstrated. Based on a developed comb drive actuator working in a low voltage of 37V, our grating period was compressed for 12.5% The first resonant mode of the comb drive actuator was simulated to be 3.8 kHz by finite element modeling.
author_names: Xiang Liu

Tie Li

Anjie Ming

Yanxiang Liu

Ping Zhou

Yuelin Wang
title: MEMS compressed tunable grating
venue: Applied Optics and Photonics China
year: 2009

abstract: Thin films are widely used in various devices including micorelectronics and microelectromechanical systems. For this reason, it is important to accurately identify their properties. A Laser Deflectometer (LD) measures the warpage of thin films as temperature varies. To control the temperature, a thermal enclosure is needed. The top quartz plate of the thermal enclosure affects the path of the beam; hence, it distorts the warpage measurement. In this report, we provide two physical models: one relies on geometrical analysis, whereas the other is developed using operator based modeling to correct the wafer warpage measurement. Also, an efficient statistical model based on experimental data predicts the true warpage given the LD measurement. We then analyze the statistical properties and validation using new datasets. In conclusion, we summarize our analysis and provide recommendations. 1 Problem Description Microfabricated thin films are key constituents of coatings, microelectronics, and microelectromechanical systems (MEMS) Thermomechanical behavior of thin films is critical to the functionality and reliability in these applications. Thin films are merely nanometers to micrometers thick and their thermomechanical material properties differ from those observed in bulk dimensions, which is sensitive to fabrication processes. Thin films are fabricated on thicker, functional substrates; removing the films from their substrates can destroy the films. This presents a challenge in characterizing the thin film thermomechanical properties, as isolating the thin films for testing may be impractical and adding fabrication steps to produce film samples free of the substrate may alter the film properties. Therefore, a method to identify thin film properties in situ is needed. The integrated circuit (IC) industry has deployed a non contact, laser based profilometer that is tailored to measuring warpage of thin films on standard substrates (wafers) at varying temperatures. The profilometer determines warpage by measuring how a laser beam impinging on the film surface reflects onto a position sensitive photosensor as it scans across the film. These measurements are readily realized at ambient temperatures; however, to measure warpage at controlled, non ambient temperatures, the wafer must be enclosed to maintain thermal stability. The laser and photosensor lie outside the thermal enclosure, so the laser light must enter the enclosure before reaching the film and exit the enclosure after reflecting off the film during the temperature controlled program. The alteration of the beam path through a quartz window in the enclosure distorts film warpage data. Traditionally, the IC industry has disregarded distortion of warpage data by the enclosure, since it assumes that film stress, a primary quantity of interest derived from differential warpage data, is unaltered. Yet, highly desired thin film mechanical properties can be identified using the absolute warpage data, provided effects of the enclosure are accommodated. Modifying hardware or employing an alternate technology that could be adopted by the IC industry may be a long term solution, but such changes are impractical. Instead, there is an immediate need to use existing profilometer functionality to ascertain non distorted wafer warpage. This project aims to develop computational techniques that can effectively 1Department of Mathematics, University of Texas El Paso 2Department of Mathematics, Southern Methodist University 3Department of Mathematics, University of Central Florida 4Department of Mathematics, Virginia Tech 5Department of Mathematics, University of Michigan 6Applied Mathematics, North Carolina State University 7Sandia National Labs 8Department of Mathematics, North Carolina State University
author_names: Pierre A Gremaud

Mansoor A Haider

Ilse C F Ipsen

Ralph C Smith
title: TWENTY FOURTH MATHEMATICAL AND STATISTICAL MODELING WORKSHOP FOR GRADUATE STUDENTS
year: 2019