Query: wafer map defect

Candidate papers:

abstract: A wafer map contains a graphical representation of the locations about defect pattern on the semiconductor wafer, which can provide useful information for quality engineers. Various defect patterns occur due to increasing wafer sizes and decreasing features sizes, which makes it very complex and unreliable process to identify them. In this paper, we propose a voting ensemble classifier with multi types features to identify wafer map defect patterns in semiconductor manufacturing. Our research contents can be summarized as follows. First, three distinctive features such as density geometry and radon based features were extracted from raw wafer images. Then, we applied four machine learning classifiers, namely logistic regression (LR) random forests (RFs) gradient boosting machine (GBM) and artificial neural network (ANN) and trained them using extracted features of original data set. Then their results were combined with a soft voting ensemble (SVE) technique which assigns higher weights to the classifiers with respect to their prediction accuracy. Consequently, we got performance measures with accuracy, precision, recall, {F} measure, and AUC score of 95.8616% 96.9326% 96.9326% 96.7124% and 99.9114% respectively. These results show that the SVE classifier with proposed multi types features outperformed regular machine learning based classifiers for wafer maps defect detection.
author_names: Muhammad Saqlain

Bilguun Jargalsaikhan

Jong Yun Lee
title: A Voting Ensemble Classifier for Wafer Map Defect Patterns Identification in Semiconductor Manufacturing
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2019

abstract: Wafer maps provide important information for engineers in identifying root causes of die failures during semiconductor manufacturing processes. We present a method for wafer map defect pattern classification and image retrieval using convolutional neural networks (CNNs) Twenty eight thousand six hundred synthetic wafer maps for 22 defect classes are generated theoretically and used for CNN training, validation, and testing. The overall classification accuracy for the 6600 test dataset is 98.2% One thousand one hundred and ninety one real wafer maps are used for CNN performance evaluation for the same model trained by synthetic wafer maps. We demonstrate that by using only synthetic data for network training, real wafer maps can be classified with high accuracy. For image retrieval, a binary code for each wafer map is generated from an output of a fully connected layer with sigmoid activation. A retrieval error rate is 0.36% for the test dataset and 3.7% for the real wafers. Image retrieval takes 0.13 s per wafer map from the 18 000 wafer map library.
author_names: Takeshi Nakazawa

Deepak V Kulkarni
title: Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2018

abstract: In semiconductor manufacturing, the patterns on the wafer map provide important information for engineers to identify the root causes of production problems. The detection and recognition of wafer map patterns is thus an important issue in semiconductor industry. Automatic techniques are required to cut down on cost and to improve accuracy. In this study, we propose an approach to recognize patterns in the wafer maps which uses the extracted features based on the proposed weight masks. The proposed masks contain three types, namely, polar masks, line masks and arc masks. Polar masks aim to extract features of concentric patterns, while line and arc masks are designed to mainly deal with eccentric patterns like scratches. These masks can be applied to extract rotation invariant features for the classification of the defect patterns. To demonstrate the effectiveness of our model, we apply the method to a real world wafer map dataset. Comparisons with alternative methods show superiority of our method in the task of wafer map defect pattern recognition.
author_names: Rui Wang

Nan Chen
title: Wafer Map Defect Pattern Recognition Using Rotation Invariant Features
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2019

abstract: Due to the complexity and dynamics of the semiconductor manufacturing processes, wafer maps will present various defect patterns caused by various process faults. Identification of wafer map defect patterns can help operators in finding out root causes of abnormal processes, and then ensures that the manufacturing process is restored to the normal state as soon as possible. This paper proposes a wafer map defect recognition (WMDR) model based on integration of deep transfer learning. Our model reduces the training time and improves feature learning performance of DenseNet. In addition, the recognition algorithm based on transfer learning can solve the problem of class imbalance in the WMDR task.
author_names: Zongli Shen

Jianbo Yu
title: Wafer Map Defect Recognition Based on Deep Transfer Learning
venue: 2019 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM)
year: 2019

abstract: Wafer map defect classification is one of the most important process for semiconductor manufacturing. Wafer map defects are also cause of die failures. So, we propose a better method for classifying defects of wafer map. We propose deep convolutional neural network architecture and our proposed architecture is the improved version of previous researcher's architecture. We also solve the data imbalance problem by applying data augmentation technique before training of data. The test accuracy of our research is 99.29% which is the best performance so far.
author_names: Ashadullah Shawon

Md Omar Faruk

Masrur Bin Habib

Abdullah Mohammad Khan
title: Silicon Wafer Map Defect Classification Using Deep Convolutional Neural Network With Data Augmentation
venue: 2019 IEEE 5th International Conference on Computer and Communications (ICCC)
year: 2019

abstract: Since machine vision systems (MVS) lead to a wide usage of monitoring systems for industrial applications, the research on the statistical process control (SPC) of image data has been promoted as an automated method for early detection and prevention of unusual conditions in manufacturing processes. In this paper, we propose a non parametric SPC approach based on the 2D wavelet spectrum (WS SPC) to extract the feature that contains the spatial and directional information of each subspace in an image. Using the 2D discrete wavelet transform and spectrum analysis, the representative statistic, the Hurst index, is calculated, and a single matrix space that consists of estimated statistics is reconstructed into a spatial control area for SPC. When a control limit is determined by the density of statistics, real time monitoring based on WS SPC is available for time releasing images. In the application, an analysis of wafer bin maps (WBMs) is conducted at a semiconductor company in Korea in order to evaluate the performance of the suggested approach. The results show that the proposed method is effective in terms of its fast computation speed and spectral monitoring.
author_names: Munwon Lim

Suk Joo Bae
title: Spatial Monitoring of Wafer Map Defect Data Based on 2D Wavelet Spectrum Analysis
year: 2019

abstract: In semiconductor manufacturing processes, defect detection and recognition in wafer maps have received increasing attention from semiconductor industry. The various defect patterns in wafer maps provide crucial information for assisting engineers in recognizing the root causes of the fabrication problems and solving them eventually. This paper develops a manifold learning based wafer map defect detection and recognition system. In this system, a joint local and nonlocal linear discriminant analysis (JLNDA) is proposed to discover intrinsic manifold information that provides the discriminant characteristics of the defect patterns. An unsupervised version of JLNDA (called local and nonlocal preserving projection) is further developed to provide a monitoring chart for defect detection of wafer maps. A JLNDA based Fisher discriminant is further put forward for online defect recognition without the modeling procedure of recognizers. Comparisons with other regular methods, principal component analysis, local preserving projection, linear discriminant analysis (LDA) and local LDA, illustrate the superiority of JLNDA in wafer map defect recognition. The effectiveness of the proposed system has been verified by experimental results from a real world data set of wafer maps (WM 811K)
author_names: Jianbo Yu

Xiaolei Lu
title: Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Linear Discriminant Analysis
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2016

abstract: Defect clusters on the wafer map can provide important clue to identify the process failures so that it is important to accurately classify the defect patterns into corresponding pattern types. In this research, we present an image based wafer map defect pattern classification method. The presented method consists of two main steps: without any specific preprocessing, high level features are extracted from convolutional neural network and then the extracted features are fed to combination of error correcting output codes and support vector machines for wafer map defect pattern classification. To the best of our knowledge, no prior work has applied the presented method for wafer map defect pattern classification. Experimental results tested on 20,000 wafer maps show the superiority of presented method and the overall classification accuracy is up to 98.43%
author_names: Cheng Hao Jin

Hyun-Jin Kim

Yongjun Piao

Meijing Li

Minghao Piao
title: Wafer map defect pattern classification based on convolutional neural network features and error correcting output codes
venue: J. Intell. Manuf.
year: 2020

abstract: With the continuous drive toward integrated circuits scaling, efficient yield analysis is becoming more crucial yet more challenging. In this paper, we propose a novel methodology for wafer map defect pattern classification using deep selective learning. Our proposed approach features an integrated reject option where the model chooses to abstain from predicting a class label when misclassification risk is high. Thus, providing a trade off between prediction coverage and misclassification risk. This selective learning scheme allows for new defect class detection, concept shift detection, and resource allocation. Besides, and to address the class imbalance problem in the wafer map classification, we propose a data augmentation framework built around a convolutional auto encoder model for synthetic sample generation. The efficacy of our proposed approach is demonstrated on the WM 811k industrial dataset where it achieves 94% accuracy under full coverage and 99% with selective learning while successfully detecting new defect types.
author_names: Mohamed Baker Alawieh

Duane S Boning

David Z Pan
title: Wafer Map Defect Patterns Classification using Deep Selective Learning
venue: 2020 57th ACM/IEEE Design Automation Conference (DAC)
year: 2020

abstract: In the IC design process, the test process is the main factor of production cost. Existing tests rely on additional analysis of testing result data by the engineer to determine the status of the process. Thus it could take an additional amount of time and cannot make adjustments of the process immediately. Wafer map defect recognition is an import part of semiconductor. There is lots of information in wafer maps which can quickly help engineers to identify what failure type it is. The location of the error point is graphical represented and the relationship of these points contains the feature of this map. In this paper, we proposed a classifier with reduced weight architecture based on depthwise separable convolutions. The entire work is verified by using the real world wafer map dataset (WM 811K) The accuracy is 96.63% in test set.
author_names: Tsung-Han Tsai

Yu-Chen Lee
title: Wafer Map Defect Classification with Depthwise Separable Convolutions
venue: 2020 IEEE International Conference on Consumer Electronics (ICCE)
year: 2020