Query: FinFETs and Other Multi-Gate Transistors

Candidate papers:

abstract: FinFETs and Other Multi Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field effect transistors (FETs) It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.
author_names: J P Colinge
title: FinFETs and Other Multi Gate Transistors
year: 2007

abstract: To enable the advancement of Si based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. This thesis, on the electrical characterisation of non standard orientated MOSFETs and multi gate transistors displays detailed insight into the carrier transport and resulting performance limiting mechanisms. The results are composed of three parts. Firstly, the standard method of extracting carrier effective mobility from electrical measurements on MOSFETs is reviewed and the assumptions implicit in this method are discussed. A novel technique is suggested that corrects the difference in drain bias during current voltage and capacitance voltage measurements. It is further shown that the lateral field and diffusion corrections, which are commonly neglected, in fact cancel each other. The efficacy of the proposed technique is demonstrated by application to data measured on a quasi planar SOI finFET at 300 K and 4 K. The second part is based on the electrical characterisation of n+poly Si/SiO2/Si nand p MOSFETs fabricated on (100) and (110) substrate orientations with the full range of channel directions. In depth analysis of the electron and hole mobility was performed at 300 K and 4 K. The 4 K mobilities were modelled in terms of ionised dopant impurity, local SiO2/Si interface charge and roughness scattering mechanisms. RMS (root mean squared) roughness values in the range 0.34 0.38nm and correlation lengths of 2.0 2.3 nm were extracted revealing comparable interface quality between the (100) and (110) surfaces. The third part examines the electrical characterisation of TiN/HfSiO2/Si n and pfinFETs. Fin top surface and sidewalls are in the (100) and (110) planes respectively. Fins have a height of 65 nm with widths in the range of 1872 nm (quasi planar) to 12 nm. Detailed analysis revealed vertical compressive strain induced by the gate into the fin sidewalls, which enhanced the electron mobility by 60% above the (110) reference, whilst leaving the hole mobility unaffected. Qualitative analysis of the 4 K mobilities suggests that roughness is higher on the sidewalls than on the top surface. This was attributed to the damage caused by the dry etch, used to pattern the fins. A model for remote charge scattering at the HfSiO2/SiO2 interface was developed. 4 K mobilities from the quasi planar n and pfinFETs were then modelled in terms of remote charge, ionised dopant impurity, local SiO2/Si interface charge and roughness scattering mechanisms. Remote charge densities of 8x1012 cm 2 were subsequently extracted. Scattering from these charges was shown to be the dominant scattering mechanism in the quasi planar n finFET mobility at 300 K.
author_names: Stephen M Thomas
title: Electrical Characterisation of Novel Silicon MOSFETs and finFETs.
year: 2011

abstract: This thesis deals with device design guidelines for nanoscale FinFETs using various analytic models and numerical simulations. The term FinFETs here stands for 'Fin based Field Effect Transistors' including various multi gate transistors. The wrapping of the gate on multiple sides of channel region provides excellent electrostatics which reduces the short channel effects compared to the classical planar devices. These architectural benefits have been realized using tri gate FinFETs successfully integrated in logic CMOS 22 nm generation, also ready for the 14 nm generation. Despite the gate control improvement, the nanoscale FinFETs still suffer from other scaling challenges. One is an increase of parasitic capacitances and resistances. Those parastic components in the nanoscale FinFETs significantly degrade the device and circuit performance, particularly the RF performance. Thereby, it is important to develop the analytic models for the parasitics, to evaluate their effects on device and circuit performance, and ultimately to propose the simple design guidelines to the FinFET designers. First, the parasitic capacitances between gate and source/drain have been evaluated for both planar MOSFET and double gate FinFET. In terms of fin spacing and fin height, optimization to reduce the FinFET's parasitic capacitances has been investigated. It is found that the optimized FinFET may show comparable parasitic capacitances to the planar devices. Also, process induced variations on FinFET's parasitic capacitance have been studied, showing that fin width and height variation should be carefully controlled, otherwise, the uniformity will be worse for FinFETs than it is for planar devices. Then, a simple but accurate model has been developed to analyze source/drain series resistance in tri gate FinFETs. Non rectangular, i.e, triangular or pentagonal, shape of source/drain epitaxy has been specially considered. Among spreading, sheet, and contact resistance contributions, the spreading and sheet resistance contributions have been calculated using standard 1 D or 2 D models. The contact resistance contribution is newly modeled using equivalent models of lossy transmission lines and transformations of 3 D to 2 D geometry. The source/drain series resistance model has been verified by comparing with the 3 D numerical simulations where the epitaxy geometry, silicide contact resistivity, and source/drain doping concentration are varied. It is found that to satisfy an allowable series resistance of 130 O*cm in the semiconductor roadmap with 22 nm node, both materials and geometry for source/drain region should to be optimized. That is, silicide contact resistivity lower than 10 8 O*cm2, source/drain doping concentration higher than 5x1020 cm 3, and contact surface optimization are required simultaneously. Next, the analog/RF performance of tri gate FinFETs has been evaluated to provide insightful design guidelines. Using analytic models, geometry dependent parasitics were calculated as functions of fin spacing and fin height. It is.
title: A Study on Device Design for Nanoscale FinFETs using Analytic Models and Simulations
year: 2013

abstract: [1] J. P. Colinge et al. "FinFETs and Other Multi Gate Transistors" Springer, ISBN 978 0 387 71751 7, 2007. [2] B. Doyle et al. VLSI Tech. Dig. pp. 132 133, 2003. [3] J. T. Park e[2] t al. IEEE EDL, vol. 22, no. 8, pp. 405 406, Aug. 2001. [4] F. L. Yang et al. IEDM'02 Technical Digest, pp. 255 258, 2002. [5] R. Ritzenthaler et al. "3D Analytical Modelling of Subthreshold Characteristics in Pi Gate FinFET Transistors " proc. of the 40th ESSDERC conference, 2010. [6] K. Suzuki et al. "Scaling theory for Double gate SOI MOSFETs" IEEE TED, vol. 40, no. 12, 1993. 1.E 15 1.E 14 1.E 13 1.E 12 1.E 11 1.E 10 1.E 09 1.E 08 1.E 07 1.E 06 1.E 05
author_names: Romain Ritzenthaler

Francois Lime

Olivier Faynot

Sorin Cristoloveanu

Benjamin Iniguez
title: Analytical modelling of short channel planar FDSOI and triple gateFET transistors.
year: 2010

abstract: In this work, we demonstrate the preparation of nickel monosilicide (NiSi) layers on silicon using a conformal NiO ALD process and thin sacrificial Ge interlayers. The interlayers protect the underlying Si from oxidizing during the NiO growth, while allowing for Ni diffusion during a silicidation anneal. The NiSi layers prepared have low amounts of impurities and near bulk resistivities, therefore making the processes promising candidates for applications in advanced semiconductor devices where high quality NiSi layers are needed, such as source drain contacts. Good step coverage provided by ALD enables their use for example in non planar transistors such as FinFETs and other multi gate transistors with complex topographies.
author_names: Viljami Pore

Eva Tois

Raija Matero

S Haukka

Mark T Tuominen

Jacob Woodruff

Brennan Milligan

F Tang

Michael Eugene Givens
title: Nickel silicide for source drain contacts from ALD NiO films
venue: 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)
year: 2015

abstract: The subject of the PhD is focused on theoretical and experimental studies ofnanoscale multi gate Metal Oxide Semiconductor Field Effect Transistors. The theoretical part is orientated towards the derivation of analytical expressions for the potential distribution within the channel of the transistors, from which characteristic parameters ofthe transistors are derived. The final aim of the work is to obtain analytical compact expressions for the drain current, valid in aH regions of operation. First, symmetrical Double Gate MOSFETs are studied, whereas the study of all other types of multi gate MOSFETs (triple gate and gate all around) is based on the derived model of DG MOSFETs. For the experimental part, the transfer characteristics of single FinFETs and 5 FinFETs were measured at room temperature. For analysis of the experimental data, numerical simulations were performed to verify the theoretical speculations and optimize the device performance.
author_names: Andreas Tsormpatzoglou
title: Caracterisation et modelisation des composants MOS a multiples grilles nanometriques
year: 2009

abstract: In this paper by showing the results of an analytical model for the different variations of Multi Gate MOSFETs including the FinFET. All Around Gate MOSFET. Double Gate MOSFET. we present a complete and detailed investigation of all the performance aspects of these novel device structures. By having the values of all the performance metrics of the transistors such as drain current. subthreshold swing. threshold voltage. and gate capacitance. we present detailed discussions on the several advantages of all the Multi Gate structures including the FinFET.
author_names: Javaneh Mohseni

James D Meindl
title: Reliability challenges of FinFET and other multi gate MOSFETs
venue: 2013 IEEE Conference on Reliability Science for Advanced Materials and Devices
year: 2013

abstract: The structure with vertical channel is attractive due to suppression of the short channel effect, where the shape of silicon fin determines the device performance. In this work, the DC characteristics of single fin FinFET are simulated, which shows a better immunity against fluctuation induced by random dopant than that of tri gate and quasi planar fin shapes. Increasing the number of silicon fins of FinFET can further improve the performance. Examining the fluctuation induced by random dopant in CMOS inverter and SRAM circuits with triple fin structure shows that the fluctuation of intrinsic gate delay and SNM in triple fin FinFET are smaller and larger, respectively, than that of others due to higher driving current.
author_names: Hui-Wen Cheng

Yiming Li
title: Electrical characteristics of 16 nm multi gate and multi fin field effect transistors and digital circuits
year: 2010

abstract: Multi gate transistors enable the pace of Moore's Law for another decade. In its 22nm technology node Intel switched to multi gate transistors called TriGate, whereas IBM, TSMC, Samsung and others will do so in their 20nm and 14nm nodes with multi gate transistors called FinFET. Several recent publications studied the drawing of multi gate transistors layout. Designing new VLSI cell libraries and blocks requires massive re drawing of layout. Hard IP reuse is an alternative method taking advantage of existing source layout by automatically mapping it into new target technology, which was used in Intel's Tick Tock marketing strategy for several product generations. This paper presents a cell level hard IP reuse algorithm, converting planar transistors to multi gate ones. We show an automatic, robust transformation of bulk diffusion polygons into fins, while addressing the key requirements of cell libraries, as maximizing performance and interface compatibility across a variety of driving strength. We present a layout conversion flow comprising time efficient geometric manipulations and discrete optimization algorithms, while generating manually drawn layout quality. Those can easily be used in composing larger functional blocks.
author_names: Shmuel Wimer
title: Planar CMOS to multi gate layout conversion for maximal fin utilization
venue: Integr.
year: 2014

abstract: Device and isolation regions in a semiconductor substrate, a semiconductor substrate, a fin field effect transistor, and a (Fin Field Effect Transistor FinFET) FinFET comprises a further semiconductor region between the semiconductor substrate above the channel region, the channel region and the side wall surface on the top of the gate dielectric, the gate dielectric a gate electrode over the source drain region and a source drain region and the channel region. The channel region and the additional semiconductor region is formed from a different semiconductor material, and is substantially horizontal to each other.
author_names: kweo ci-wei

cyao wian-

cen hou-yu

yang swi-hong
title: Multi gate devices with replaced channels and methods for forming the same
year: 2012