Query: fast full chip image

Candidate papers:

abstract: The rapid progression of semiconductor technology has significantly impacted the ability to examine and analyze complex integrated circuits (ICs) Small device feature sizes, combined with large die sizes, add a heavy processing burden that severely limits our timely ability to perform defect validation and anti tampering analysis at full scale. In this paper, we describe the algorithmic steps taken in the processing pipeline to quickly create a global image database of an entire advanced IC. We focused specifically on the image alignment and stitching algorithms necessary to support a combined field of view of a given layer of a die. We describe key algorithmic challenges such as contextual semantics that limits the robustness of the alignment algorithm. We also describe the use of database indexing to manage and traverse the enormous amounts of data. Keywords SEM, chip delayering, image stitching, nanoscale, IC failure analysis, anti tampering, reverse engineering.
author_names: Dafan Zhang

Gooitzen S van der Wal

Phil Miller

David S Stoker

Erik Matlin

Naveen Marri

Gary Gan

Joe Zhang

J Charles Asmuth

Sek M Chai

David Weaver

Michael R Piacentino

Scott Silverman

Michael DiBattista

Robert Chivas

Christopher G L Ferri

David Taylor

Jordan Furlong

Thomas Harper

Dustin Kobs
title: Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits
year: 2019

abstract: Lithography simulation is an increasingly important part of semiconductor manufacturing due to the decreasing k1 value. It is not only required in lithography process development, but also in RET design, RET verification, and process latitude analysis, from library cells to full chip. As the design complexity grows exponentially, pure software based simulation tools running on general purpose computer clusters are facing increasing challenges in meeting today's requirements for cycle time, coverage, and modeling accuracy. We have developed a new lithography simulation platform (TachyonTM) which achieves orders of magnitude speedup as compared to traditional pure software simulation tools. The platform combines innovations in all levels of the system: algorithm, software architecture, cluster level architecture, and proprietary acceleration hardware using application specific integrated circuits. The algorithm approach is based on image processing, fundamentally different from conventional edge based analysis. The system achieves superior model accuracy than conventional full chip simulation methods, owing to its ability to handle hundreds of TCC kernels, using either vector or scalar optical model, without impacting throughput. Thus first principle aerial image simulation at the full chip level can be carried out within minutes. We will describe the hardware, algorithms and models used in the system and demonstrate its applications of the full chip verification purposes.
author_names: Yu Cao

Yen-Wen Lu

Luoqi Chen

Jun Ye
title: Optimized hardware and software for fast full chip simulation
venue: SPIE Advanced Lithography
year: 2004

abstract: This article proposes a hardware accelerator for image feature extraction based on the oriented features from accelerated segment test (FAST) and rotated binary robust independent elementary features (ORB) algorithm. The architecture adopts a hybrid workflow to process three scales in parallel as an octave, and multiple octaves are processed in serial by time sharing the DRAM. In order to support any image resolution, a block wise dataflow is used on the serial parallel architecture. The overlapped data between two blocks is reused. As a result, the on chip memory is limited to 1.47 Mb, and the DRAM bandwidth is compressed by 33% Besides, $3 \times 3$ non maximum suppression with heap sorting is applied to balance keypoint distribution in 2 D. It improves the valid keypoint match ratio by 7.09% In addition, parallel processing in keypoint detection increases $2 \times throughout. Moreover, approximate computing and superscalar processing reduce the timing cost in orientation estimation and descriptor generation by 92.78% and 67% respectively. Compared to the non optimized baseline architecture, the proposed architecture saves the total timing cost by 82.4% The accelerator is implemented in a Xilinx MPSoC, and it achieves 108 fps on full HD images at 200 MHz under 873 mW.
author_names: Rongdi Sun

Jiuchao Qian

Romero Hung Jose

Zheng Gong

Ruihang Miao

Wuyang Xue

Peilin Liu
title: A Flexible and Efficient Real Time ORB Based Full HD Image Feature Extraction Accelerator
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2020

abstract: A fast algorithm based on two dimensions template sampling was presented and optimized.It sets the search step and sample sequence to reduce the computational complexity.It includes two search phases,which settle down the problem of target subimage rotating and guarantee to find the matching positions precisely.The simplicity of the algorithm facilitates its hardware implementation.It has been applied to the image locating system of fully automatic gold wire bonder,ad the real time demand (20 ms) and precision demand 4 mm) of the system are meted well.Experiment results demonstrate that the algorithm is robust and immune to noise.
author_names: Jiang Kai

Chen Hai-xia
title: A Fast Chip Image Locating Algorithm in the Full Automatic Gold Wire Bonder
year: 2003

abstract: ABSTRACT We present a novel mm resolution particle image velocimetry setup capable of automated full chip measurements of microchannel acoustophoresis. Our system allows for fast collection of a sufficient amount of data enabling reliable determination of the influence from the forces from acoustic radiation and acoustic streaming acting simultaneously on microbead suspensions in a microfluidic system. From a series of acoustophoretic focusing experiments on 5 mm, 3 mm, and 2 mm polystyrene (PS) microbead suspensions, we quantify the particle velocity induced by the acoustic radiation force and show that it scales with the expected microbead radius to the power two.
author_names: Rune Barnkob

Per Augustsson

Thomas Laurell

Henrik Bruus
title: An automated full chip micro piv setup for measuring microchannel acoustophoresis: Simultaneous determination of forces from acoustic radiation and acoustic streaming
year: 2011

abstract: A fast full parallel interface adapted to VERSAbus has been designed and specifically optimized for image data transfers between a VAX computer with a DR11 W and a special purpose image computer. The interface has been built around a AM9516 chip, and contains all features to optimize the bus occupation, the data transfer speed as well as the microprocessor over head. Special features of the interface are (1) easy handling of two dimensional image ar rays, (2) all communication via one parallel link including all commands (no additional serial link) and (3) high speed data transfer possibility of up to 600 Kbyte/sec. A software shell is being designed on the VAX computer to provide a userfriendly and efficient environment for the software and the application groups of our department. So, all communication between the VAX computer and the image computer will be made easier.
author_names: Michel Vercruyssen

Luc Van Eycken

Andre Oosterlinck
title: A Fast Full Parallel Interface Between A VAX Computer And A VERSAbus Based Real Time Image Computer
venue: Other Conferences
year: 1987

abstract: The application of vector quantization has been constrained to a great deal since its encoding process is very heavy. This paper presents a fast encoding algorithm called the double feature ordered partial codebook search (DFPS) algorithm for image vector quantization. The DFPS algorithm uses the Walsh Hadamard transform (WHT) for energy compaction and a look up table (LUT) for fast reference. The simulation results show that with elaborate preprocessing and memory cost within a feasible level, the proposed DFPS algorithm is faster than other existing search algorithms. Compared with the exhaustive full search (EFS) algorithm, the DFPS algorithm reduces the computational complexity by 97.0% to 97.8% for a codebook size of 256 while maintaining the same encoding quality as that of the EFS algorithm.
author_names: Chul Ryu

Sungwoong Ra
title: A fast full search equivalent encoding algorithm for image vector quantization based on the WHT and a LUT
venue: Fifth International Workshop on System on Chip for Real Time Applications (IWSOC'05)
year: 2005

abstract: A fast model based technique for SRAF placements is proposed in this paper. This technique first constructed an image pixel map with values presenting the sensitivity of improving process window on the desired pattern. The sensitivity value was derived based on contrast improvement with a defocus model. Then high value pixels were selected and constructed to form SRAF with MRC regulations. This technique does not require iterations to produce SRAF and achieves very fast runtime with simple mask shapes, thus can be used in full chip productions. We called this technique the SRAF guidance map, SGM
author_names: Min-Chun Tsai

Shigeki Nojima

Masahiro Miyairi

Tatsuo Nishibe

Been-Der Chen

Hanying Feng

William S Wong

Zhangnan Zhu

Yen-Wen Lu
title: A full chip MB SRAF placement using the SRAF guidance map
venue: Photomask Technology
year: 2010

abstract: Linear super resolution microscopy via synthesis aperture approach permits fast acquisition owing to its wide field implementations. However, it has been limited in resolution because a spatial frequency band missing occurs when trying to use a shift magnitude surpassing the cutoff frequency of the detection system beyond a factor of two, which distorts the image severely. Here, we propose a method of chip based 3D nanoscopy through a tunable spatial frequency shift effect capable of covering the full extent of the spatial frequency component within a wide passband. The missing of the spatial spectrum can be effectively solved by developing a spatial frequency shift active tuning approach through wave vector manipulation and operation of optical modes propagating along multiple azimuthal directions on a waveguide chip. Besides, the method includes a chip based sectioning capability, which is enabled by the saturated absorption of fluorophores.
author_names: Xiaowei Liu
title: Chip based wide field 3D nanoscopy through tunable spatial frequency shift effect
year: 2020

abstract: A lensless full color holographic projection system is proposed, satisfying the requirement of compactness and flexibility. The system enables projection by illuminating a single chip spatial light modulator (SLM) simultaneously with red (R) green (G) and blue (B) lasers, in which the SLM loads a color multiplexed phase only hologram. To strengthen compactness, filtering and achromatic systems are achieved by digital phase, where the digital lens phase focuses the light field onto the filter plane, and the digital blazed gratings shift the RGB images to achieve a fine alignment. Besides, the flexibility of diffraction calculation is enhanced by the cascaded D FFT and S FFT algorithm (CDS algorithm, where D FFT is acronym of double fast fourier transform and S FFT is acronym of single fast fourier transform) Both simulation and optical experiments are carried out. We conducted 2D image and animation projection and multi image plane projection. The results confirm the feasibility of our method.
author_names: Zhaoyu Gong

Xing Chen

Zhongyuan Guo

Feihong Yu
title: Compact lensless full color holographic projection system with digital phase
year: 2020