Query: Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

Candidate papers:

abstract: Hybrid reconfigurable logic circuits were fabricated by integrating memristor based crossbars onto a foundry built CMOS (complementary metal oxide semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin film memristors served as the configuration bits and switches in a data routing network and were connected to gate level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip flop, and then reconfigure devices.
author_names: Qiangfei Xia

Warren Robinett

Michael Cumbie

Neel Banerjee

Thomas John Cardinali

J Joshua Yang

Wei Wu

Xuema Li

William M Tong

Dmitri B Strukov

Greg Snider

Gilberto Medeiros-Ribeiro

R Stanley Williams
title: Memristor CMOS hybrid integrated circuits for reconfigurable logic.
venue: Nano letters
year: 2009

abstract: Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look Up Tables (LUTs) configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS memristor based architecture using stateful NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82i?area saving, 1.57i?speedup and 3.63i?less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.
author_names: Pravin S Mane

Nishil Talati

Ameya Riswadkar

Ramesh Raghu

C K Ramesha
title: Stateful NOR based reconfigurable architecture for logic implementation
venue: Microelectron. J.
year: 2015

abstract: Device scaling and performance limits in complementary metal oxide semiconductor (CMOS) technology are leading to a rapid proliferation of novel computing paradigms for information processing. To this end, CMOS/memristor hybrid technology, where memristive devices are integrated in 3D, is extremely promising. These technologies are emerging under the joint efforts of industry and academe, with innovations in fabrication processes, materials, devices, and circuits. A prime advantage of such computing technology is its ability to offer tera bit densities with ultra low power and long data retention times. These unique characteristics motivate the development of computational fabrics that can dynamically transform over time to perform heterogeneous computing based on system requirements, with the technological objective of superseding classical CMOS architectures. This book chapter discusses the different models of memristors which can be used for implementing memristors as memory, sensing, logic and nueromorphic units.
author_names: Dhireesha Kudithipudi

Cory E Merkel
title: Reconfigurable Memristor Fabrics for Heterogeneous Computing
year: 2012

abstract: This chapter reviews the application of memristive devices as reconfigurable switches. First, the fundamental performance metrics (power consumption, endurance, switch speed, IV nonlinearity, CMOS compatibility, ON/OFF ratio, etc. of memristors as switches are discussed. Device engineering approaches including fabrication techniques, choice of materials, and geometry engineering are then reviewed. Finally, hybrid memristor/CMOS circuits that integrate CMOS with memristive devices as reconfigurable switches are presented.
author_names: Qiangfei Xia
title: Memristor Device Engineering and CMOS Integration for Reconfigurable Logic Applications
year: 2014

abstract: Memristors have recently begun to be explored in logic operations. In this paper, a compact scheme using complementary resistive switching (CRS) CMOS cells (CCCs) for logic operations and data storage is proposed. Several logic operations, including IMPLY, IMPLY AND, AND, NAND, OR, and NOR, are realized with CCCs. Then the AND OR logic and the OR AND logic are presented to realize the programmable logic arrays built with CCCs, providing opportunities for memristor CMOS integrated circuits.
author_names: Xiaoping Wang

Shuai Li

Zhigang Zeng
title: Configurable Logic Operations Using Hybrid CRS CMOS Cells
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2018

abstract: This paper proposes a hybrid CMOS/memristor implementation of a programmable threshold logic gate. In this gate, memristive devices implement ratioed diode resistor logic, while CMOS circuitry is used for signal amplification and inversion. Due to the excellent scaling prospects and nonvolatile analog memory of memristive devices, the proposed threshold logic is in field configurable and potentially very compact. The concept is experimentally verified by implementing a 4 input symmetric linear threshold gate with an integrated circuit CMOS flip flop, silicon diodes, and Ag/a Si/Pt memristive devices.
author_names: Fabien Alibart

Dmitri B Strukov
title: Programmable CMOS/Memristor Threshold Logic
venue: IEEE Transactions on Nanotechnology
year: 2013

abstract: Optically transparent thin film transistors (TFTs) have recently attracted significant attention for a new generation of transparent electronics where p and n channel transistors form the basic building block for complementary analog and digital integrated circuits (ICs) This paper reports a hybrid integration of p channel carbon nanotube (CNT) and n channel junctionless indium tin oxide (ITO) TFTs using a simple and cost effective shadow mask assisted fabrication process. The fabricated devices exhibit a high transmittance of ~90% in the visible light region and function as inverters, NAND and NOR gates. More interestingly, distinct optoelectronic responses of the CNT and ITO TFTs to ultraviolet light have been clearly observed. In addition to conventional electrically gated logic operations, simple optical reconfigurable logic operations have been realized with hybrid CNT/ITO TFT based logic gates. The results suggest that introducing optical modulation to the logic gates could increase the functionalities compared with the traditional electrically driven counterparts.
author_names: Jianping Zou

Kang Sheng Zhang

Weifan Cai

Tupei Chen

Arokia Nathan

Qing Zhang
title: Optical reconfigurable carbon nanotube and indium tin oxide complementary thin film transistor logic gates.
venue: Nanoscale
year: 2018

abstract: Memristor is a two terminal non linear passive electrical device. After its recently successful fabrication, a variety of applications based on memristor have been explored, such as non volatile memory, reconfigurable computing and neural network. However, one major challenge when designing hybrid CMOS memristor integrated circuit is the lack of SPICE like simulator for design validation. Current approach is to describe memristor device with equivalent circuit, which is however extremely time consuming for large scale design simulation due to additional modeling components. In this paper, a memristor SPICE simulator is introduced based on the recent new modified nodal analysis (MNA) framework, which can effectively support the non conventional state variable such as doping ratio of memristor. As such, the memristor device can be stamped into state matrix similarly as one BSIM MOSFET. Compared with equivalent circuit simulation approach, our new MNA based approach exhibits 40x less simulation time for a 32x32 memristor crossbar circuit. A hybrid CMOS memristor circuit for classic conditioning training has also been studied by the developed SPICE simulator.
author_names: Yuhao Wang

Wei Fei

Hao Yu
title: SPICE simulator for hybrid CMOS memristor circuit and system
venue: 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications
year: 2012

abstract: This chapter describes architectures of digital circuits including memories, general purpose, and application specific reconfigurable Boolean logic circuits for the prospective hybrid CMOS/nanowire/nanodevice "CMOL" technology. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with those of molecular scale nanodevices. Two terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp tipped pins that are distributed all over the circuit area, on top of the CMOS stack. We show that CMOL memories with a nano/CMOS pitch ratio close to 10 may be far superior to the densest semiconductor memories by providing, e.g. 1 Tbit/cm\^2\ density even for the plausible defect fraction of 2% Even greater defect tolerance (more than 20% for 99% circuit yield) can be achieved in both types of programmable Boolean logic CMOL circuits. In such circuits, two terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. Using custom developed design automation tools we have successfully mapped on reconfigurable general purpose logic fabric "CMOL FPGA" the well known Toronto 20 benchmark circuits and estimated their performance. The results have shown that, in addition to high defect tolerance, CMOL FPGA circuits may have extremely high density (more than two orders of magnitude higher that that of usual CMOS FPGA with the same CMOS design rules) while operating at higher speed at acceptable power consumption. Finally, our estimates indicate that reconfigurable application specific "CMOL DSP" circuits may increase the speed of low level image processing tasks by more than two orders of magnitude as compared to the fastest CMOS DSP chips implemented with the same CMOS design rules at the same area and power consumption.
author_names: Dmitri B Strukov
title: Hybrid Semiconductor Molecular Integrated Circuits for Digital Electronics: CMOL Approach
year: 2008

abstract: The volatile nature of the SRAM ce l l s that hold configuration state in most current reconfigurable logic devices is a significant limitation, requiring that the device be re programmed each t ime power is applied. In this paper, w e present a new class of reconfigurable logic elements based on magnetoelectronic devices, known as hybrid Hall effect (HHE) devices. HHE devices can be configured on a cycle by cycle basis to compute a variety of l o g i c functions, and retain their state in definitely even in the absence of an external power supply. In this paper, we present a number of reconfigurable circuits that illustrate the capabilities of the HHE device and show how i t can be integrated with conventional CMOS systems.
author_names: Steve Ferrera

Nicholas P Carter
title: Hybrid Hall Effect Devices A Novel Building Block For Reconfigurable Logic
year: 2003