Query: A sub-1-volt nanoelectromechanical switching device

Candidate papers:

abstract: Nanoelectromechanical (NEM) switches have received widespread attention as promising candidates in the drive to surmount the physical limitations currently faced by complementary metal oxide semiconductor technology. The NEM switch has demonstrated superior characteristics including quasi zero leakage behaviour, excellent density capability and operation in harsh environments. However, an unacceptably high operating voltage (4 20 V) has posed a major obstacle in the practical use of the NEM switch in low power integrated circuits. To utilize the NEM switch widely as a core device component in ultralow power applications, the operation voltage needs to be reduced to 1 V or below. However, sub 1 V actuation has not yet been demonstrated because of fabrication difficulties and irreversible switching failure caused by surface adhesion. Here, we report the sub 1 V operation of a NEM switch through the introduction of a novel pipe clip device structure and an effective air gap fabrication technique. This achievement is primarily attributed to the incorporation of a 4 nm thick air gap, which is the smallest reported so far for a NEM switch generated using a 'top down' approach. Our structure and process can potentially be utilized in various nanogap related applications, including NEM switch based ultralow power integrated circuits, NEM resonators, nanogap electrodes for scientific research and sensors.
author_names: Jeong Oen Lee

Yong-Ha Song

Min-Wu Kim

Min-Ho Kang

Jaehyun Oh

Hyun-Ho Yang

Jun-Bo Yoon
title: A sub 1 volt nanoelectromechanical switching device.
venue: Nature nanotechnology
year: 2013

abstract: Nanoscale metal oxide memristors have potential in the development of brain inspired computing systems that are scalable and efficient. In such systems, memristors represent the native electronic analogues of the biological synapses. In this work, we show cerium oxide based bilayer memristors that are forming free, low voltage |0.8 V| energy efficient (full on/off switching at ~8 pJ with 20 ns pulses, intermediate states switching at ~fJ) and reliable. Furthermore, pulse measurements reveal the analog nature of the memristive device; that is, it can directly be programmed to intermediate resistance states. Leveraging this finding, we demonstrate spike timing dependent plasticity, a spike based Hebbian learning rule. In those experiments, the memristor exhibits a marked change in the normalized synaptic strength >30 times) when the pre and post synaptic neural spikes overlap. This demonstration is an important step towards the physical construction of high density and high connectivity neural networks.
author_names: Cheng-Chih Hsieh

Anupam Roy

Yao-Feng Chang

Davood Shahrjerdi

Sanjay K Banerjee
title: A sub 1 volt analog metal oxide memristive based synaptic device with large conductance change for energy efficient spike based computing systems
year: 2016

abstract: The new class of fully silicon compatible hafnia based ferroelectrics with high switchable polarization and good endurance and thickness scalability shows a strong promise for new generations of logic and memory devices. Among other factors, their competitiveness depends on the power efficiency that requires reliable low voltage operation. Here, we show genuine ferroelectric switching in Hf xZr(1 x)O2 (HZO) layers in the application relevant capacitor geometry, for driving signals as low as 800 mV and coercive voltage below 500 mV. Enhanced piezoresponse force microscopy with sub picometer sensitivity allowed for probing individual polarization domains under the top electrode and performing a detailed analysis of hysteretic switching. The authentic local piezoelectric loops and domain wall movement under bias attest to the true ferroelectric nature of the detected nanodomains. The systematic analysis of local piezoresponse loop arrays reveals a totally unexpected thickness dependence of the coercive fields in HZO capacitors. The thickness decrease from 10 to 7 nm is associated with a remarkably strong decrease of the coercive field, with about 50% of the capacitor area switched at coercive voltages =0.5 V. Our explanation consistent with the experimental data involves a change of mechanism of nuclei assisted switching when the thickness decreases below 10 nm. The practical implication of this effect is a robust ferroelectric switching under the millivolt range driving signal, which is not expected for the standard coercive voltage scaling law. These results demonstrate a strong potential for further aggressive thickness reduction of HZO layers for low power electronics.
author_names: Igor Stolichnov

Matteo Cavalieri

Enrico Colla

Tony Schenk

Terence Mittmann

Thomas Mikolajick

Uwe Schroeder

Adrian M Ionescu
title: Genuinely Ferroelectric Sub 1 Volt Switchable Nanodomains in Hf xZr(1 x)O2 Ultrathin Capacitors.
venue: ACS applied materials interfaces
year: 2018

abstract: Nonvolatile memory design is a discipline that employs digital and analog circuit design techniques and requires knowledge of semiconductor physics and quantum mechanics. Methods for programming and erasing memory are discussed here, and simulation models are provided for Impact Hot Electron Injection (IHEI) Fowler Nordheim (FN) tunneling, and direct tunneling. Extensive testing of analog memory cells was used to derive a set of equations that describe the floating gate characteristics. Measurements of charge retention also revealed several leakage mechanisms, and methods for mitigating leakage are presented. Fabrication of flash memory in a standard CMOS process presents significant design challenges. The absence of multiple polysilicon layers requires that additional devices be used to control the floating gate voltage. Furthermore high voltage devices are often required to isolate the selected memory cells during write and erase cycles. However, a single poly design allows portability to another standard process provided that the floating gate characteristics are known. A flash memory system is presented here that has been fabricated in a standard 130 nanometer CMOS process. The design utilizes capacitive feedback to maintain desired injection current during programming. It also includes a sense amplifier design which features auto zeroing of inherent offsets. Comparisons to existing memory designs show that a significant improvement in areal density was achieved through the elimination of on die high voltage charge pumps and switches. Measurements were performed over a range of clock frequencies and supply voltages. Results show that this memory system is capable of a read access time of 3.5 microseconds with a 1 megahertz clock while consuming less than
author_names: David A Basford
title: Design and Evaluation of a Sub 1 Volt Read Flash Memory in a Standard 130 Nanometer CMOS Process
year: 2017

abstract: Abstract This paper presents the results on the design, fabrication and characterization of a cantilever type NEM relay featuring a hammer shaped tip and built in the back end of a conventional 0.35 mm CMOS technology. A high on/off current ratio (higher than 107) a subthreshold swing of only 285 mV/dec, and zero off state leakage current were experimentally observed. Through an endurance test of 3*103 switching cycles, the relay showed a stable pull in voltage of 31.25 V with an absolute variation of only 0.5 V. The resonant frequency was also characterized, and observed at 456.97 kHz. Finally, the paper discusses the usability of the presented device as a mass sensor with mass stiffness decoupling capability for on chip detection. This innovative feature, which could benefit the application portfolio of the emerging IoT era, lies on the fact that both pull in voltage and resonant frequency can be fully electrically determined.
author_names: Martin Riverola

Arantxa Uranga

Francesc Torres

Nuria Barniol
title: Fabrication and characterization of a hammer shaped CMOS/BEOL embedded nanoelectromechanical (NEM) relay
year: 2018

abstract: There has been remarkable interest in nanomechanical computing elements that can potentially lead to a new era in computation due to their re configurability, high integration density, and high switching speed. Here we present a nanomechanical device capable of dynamically performing logic operations (NOR, NOT, XNOR, XOR, and AND) The concept is based on the active tuning of the resonance frequency of a doubly clamped nanoelectromechanical beam resonator through electro thermal actuation. The performance of this re configurable logic device is examined at elevated temperatures, ranging from 25 degC to 85 degC, demonstrating its resilience for most of the logic operations. The proposed device can potentially achieve switching rate in ms, switching energy in nJ, and an integration density up to 106 per cm2. The practical realization of this re configurable device paves the way for nano element based mechanical computing.
author_names: Syed N R Kazmi

Md Abdullah Al Hafiz

Karumbaiah N Chappanda

Saad Ilyas

Jorge Holguin

Pedro M F J Costa

Mohammad Ibrahim Younis
title: Tunable nanoelectromechanical resonator for logic computations.
venue: Nanoscale
year: 2017

abstract: As CMOS scaling limit is reached, no charge based devices and non equilibrium systems need to be investigated as alternative switching units. We present a non volatile nanoelectromechanical switch with state variable mechanical positioning of a single walled CNT bundle suspended over metal electrodes deposited in dry etched trenches. The switch is fabricated using a single mask fabrication process followed by dielectrophoresis based directed assembly of the CNT bundle. The design exhibits symmetric behavior with the same actuation voltage <5 V) for both ON and OFF states. A coarse grain model is used to investigate the effect of the slack of the assembled CNT bundle over the shoulder of the trench, CNT bundle diameter, surface interaction between the CNT bundle and the underlying substrate, and the actuation voltage on the operational dynamics of these devices.
author_names: Salman Ali Abbasi

Taehoon Kim

Sivasubramanian Somu

Hailong Wang

Zhimin Chai

Moneesh Upmanyu

Ahmed Busnaina
title: Fabrication of a nanoelectromechanical bistable switch using directed assembly of SWCNTs
year: 2020

abstract: Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra low power digital electronics. This paper reports the demonstration of prototype circuits including the first 3 stage ring oscillator built using cell level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub nanosecond switching times, lower operating voltages and VLSI implementation. (C) 2015 Elsevier Ltd. All rights reserved.
author_names: Christopher Lawrence Ayala

Daniel Grogg

Antonios Bazigos

Simon J Bleiker

Montserrat Fernandez-Bolanos

Frank Niklaus

Christoph Hagleitner
title: Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous carbon coated contacts
year: 2015

abstract: Abrupt switching behavior and near zero leakage current of nanoelectromechanical (NEM) switches are advantageous properties through which NEMs can outperform conventional semiconductor electrical switches. To date, however, typical NEMs structures require high actuation voltages and can prematurely fail through permanent adhesion (defined as stiction) of device components. To overcome these challenges, in the present work we propose a NEM switch, termed a "squitch," which is designed to electromechanically modulate the tunneling current through a nanometer scale gap defined by an organic molecular film sandwiched between two electrodes. When voltage is applied across the electrodes, the generated electrostatic force compresses the sandwiched molecular layer, thereby reducing the tunneling gap and causing an exponential increase in the current through the device. The presence of the molecular layer avoids direct contact of the electrodes during the switching process. Furthermore, as the layer is compressed, the increasing surface adhesion forces are balanced by the elastic restoring force of the deformed molecules which can promote zero net stiction and recoverable switching. Through numerical analysis, we demonstrate the potential of optimizing squitch design to enable large on off ratios beyond 6 orders of magnitude with operation in the sub 1 V regime and with nanoseconds switching times. Our preliminary experimental results based on metal molecule graphene devices suggest the feasibility of the proposed tunneling switching mechanism. With optimization of device design and material engineering, squitches can give rise to a broad range of low power electronic applications.
author_names: Farnaz Niroui

Annie Wang

Ellen M Sletten

Yi Song

Jing Kong

Eli Yablonovitch

Timothy M Swager

Jeffrey H Lang

Vladimir Bulovic
title: Tunneling Nanoelectromechanical Switches Based on Compressible Molecular Thin Films.
venue: ACS nano
year: 2015

abstract: This paper qualitatively explores the performance limits, i.e. energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1 dimensional reduced order model (ROM) of the switch; the results given by this simplified model are compared to classical CMOS based, and sub threshold CMOS based adiabatic logic circuits. NEMS based circuits and CMOS based circuits show different optimum operating conditions, depending on the device parameters and circuit operating frequency.
author_names: Samer Houri

Christophe Poulain

Alexandre Valentian

Herve Fanet
title: Performance Limits of Nanoelectromechanical Switches (NEMS) Based Adiabatic Logic Circuits
year: 2013