Query: Suppression in the electrical hysteresis by using CaF2 dielectric layer for  capacitors

Candidate papers:

abstract: The capacitance voltage (C V) hysteresis in the bidirectional measurements of the p GaN metal insulator semiconductor (MIS) capacitor is suppressed by using a CaF2 dielectric layer and a post annealing treatment. The density of trapped charge states at the CaF2/p GaN interface is dramatically reduced from 1.3 x 1013 cm2 to 1.1 x 1011/cm2 compared to that of the Al2O3/p GaN interface with a large C V hysteresis. It is observed that the disordered oxidized interfacial layer can be avoided by using the CaF2 dielectric. The downward band bending of p GaN is decreased from 1.51 to 0.85 eV as a result of the low density oxides related trap states. Our work indicates that the CaF2 can be used as a promising dielectric layer for the p GaN MIS structures.The capacitance voltage (C V) hysteresis in the bidirectional measurements of the p GaN metal insulator semiconductor (MIS) capacitor is suppressed by using a CaF2 dielectric layer and a post annealing treatment. The density of trapped charge states at the CaF2/p GaN interface is dramatically reduced from 1.3 x 1013 cm2 to 1.1 x 1011/cm2 compared to that of the Al2O3/p GaN interface with a large C V hysteresis. It is observed that the disordered oxidized interfacial layer can be avoided by using the CaF2 dielectric. The downward band bending of p GaN is decreased from 1.51 to 0.85 eV as a result of the low density oxides related trap states. Our work indicates that the CaF2 can be used as a promising dielectric layer for the p GaN MIS structures.
author_names: Liwen Sang

B Ren

Meiyong Liao

Yasuo Koide

Masatomo Sumiya
title: Suppression in the electrical hysteresis by using CaF2 dielectric layer for p GaN MIS capacitors
year: 2018

abstract: We report on a high quality p GaN metal insulator semiconductor (MIS) capacitors with sharp interface morphology and the lowest interface trap density by using SiN x as the gate dielectric layer. Transmission electron microscopy and x ray photoelectron spectroscopy (XPS) analysis revealed a high quality interface morphology with the effective removal of carbon and oxygen impurities. Better than the interface properties of Al2O3, SiO2, and CaF2/p GaN metal oxide semiconductor (MOS) or MIS capacitors, the capacitance voltage measurements of SiN x /p GaN showed negligible electrical hysteresis after a two step surface pre treatment, leading to the lowest trapped charge density of 5 x 1010 cm 2. The interface state density distribution was also reduced to be ~1 2 x 1012 cm 2 eV 1 at E t E v 0.2 0.45 eV and 3 5 x 1012 cm 2 eV 1 near the valance band edge after the treatments. The achievement of the high quality MIS interface was attributed to the suppression of the Mg Ga O interfacial disordered layer by the effective surface treatments and oxygen free deposition process, which was usually observed at Al2O3/p GaN MOS interface.
author_names: B Ren

Meiyong Liao

Masatomo Sumiya

Jin Su

Xinke Liu

Yasuo Koide

Liwen Sang
title: High quality SiN x /p GaN metal insulator semiconductor interface with low density trap states
year: 2019

abstract: We demonstrate the electrical performances of AlGaN/GaN metal insulator semiconductorhigh electron mobility transistors (MIS HEMTs) with high quality Al<sub>2</sub>O<sub>3</sub> gate dielectric deposited by plasma enhanced atomic layer deposition using both H<sub>2</sub>O and remote O<sub>2</sub> plasma as oxygen sources. Excellent gate dielectric/GaN interface and Al<sub>2</sub>O<sub>3</sub> film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS HEMT device exhibited high on/off current ratio of <inline formula> <tex math notation="LaTeX"\sim 10^{10} /tex math>/inline formula> steep subthreshold slope, small gate leakage current, low dynamic on resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O<sub>2</sub> plasma in the ALD Al<sub>2</sub>O<sub>3</sub> deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS HEMTs production
author_names: Huan-Chung Wang

Ting-En Hsieh

Yueh-Chin Lin

Quang Ho Luc

Shih-Chien Liu

Chia-Hsun Wu

Chang Fu Dee

Burhanuddin Yeop Majlis

Edward Yi Chang
title: AlGaN/GaN MIS HEMTs With High Quality ALD Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
venue: IEEE Journal of the Electron Devices Society
year: 2018

abstract: Abstract High k HfOxNy film was deposited on amorphous InGaZnO (a IGZO) by radio frequency reactive sputtering using an HfO2 target in nitrogen plus argon ambience, the electrical characteristics and reliability of a IGZO metal insulator semiconductor (MIS) capacitors were investigated. Experimental results indicate that the nitrogen incorporation into HfO2 can produce a strong nitride interfacial barrier layer, thus lead to reducing the interface state density, suppressing the hysteresis voltage, and decreasing the gate leakage current. Improved performance has been achieved for HfOxNy gate dielectric a IGZO MIS capacitors, with a interface state density of 5.1 x 1011 eV 1 cm 2, a gate leakage current density of 3.9 x 10 5 A/cm2 at Vfb 1 V, an equivalent permittivity of 24, and a hysteresis voltage of 105 mV. Moreover, the enhanced reliability of Al/HfOxNy/a IGZO MIS capacitor is observed with a small degradation of electrical characteristics after a high field stressing at 10 MV/cm for 3600 s.
author_names: Xiao Zou

Guojia Fang

Longyan Yuan

Xingsheng Tong

Xingzhong Zhao
title: Improved electrical characteristics and reliability of amorphous InGaZnO metal insulator semiconductor capacitor with high kappa HfOxNy gate dielectric
venue: Microelectron. Reliab.
year: 2010

abstract: In this work, we investigate La"2O"3 as a gate dielectric candidate for Ge devices, using metal insulator semiconductor (MIS) structures. When the deposition temperature increases, the electrical characteristics improve with regard to dispersion in accumulation, hysteresis, stretch out, leakage current and interface state density D"i"t" By analyzing the CV data for films with different oxide thickness we find that the dielectric constant of La"2O"3 has a medium k value of about 11.The same data indicate that there is no interfacial layer, which is confirmed by high resolution transmission electron microscopy (HRTEM) observations. These results suggest that a strong reaction with the Ge substrate may take place so that a La Ge O compound may form over the entire film thickness reducing the k value. This reaction layer could be responsible for the reduction of Dit indicating good passivating properties. However, it may limit gate oxide scaling in future Ge MOS devices.
author_names: G Mavrou

S F Galata

A Sotiropoulos

Polychronis Tsipas

Yerassimos Panayiotatos

Athanasios Dimoulas

Evangelos Evangelou

Jin Won Seo

Christel Dieker
title: Germanium metal insulator semiconductor capacitors with rare earth La2O3 gate dielectric
year: 2007

abstract: Silicon nitride (SiN(x) films for a gate dielectric layer of thin film transistors were deposited by catalytic chemical vapor deposition at a low temperature or 200 degrees C) A mixture of SiH4, NH3 and H2 was used as a source gas. Metal insulator semiconductor (MIS) capacitor structures were fabricated for current voltage (I V) and capacitance voltage (C V) measurements. The breakdown voltage characteristics of the SiN(x) films were improved by the increase of NH3/SiH4 and H2/SiH4 mixing ratios and substrate temperatures. H2 treatment was attempted to improve the breakdown voltage further. A breakdown voltage as high as 6.6 MV/cm was obtained after H2 annealing at 180 degrees C. The defect states inside the SiN(x) films were analyzed by photoluminescence spectra. Silicon dangling bonds (2.5 eV) and nitrogen dangling bonds (3.1 eV) were observed. These defect states inside the SiN(x) films disappeared after H2 annealing. Flat band voltage shifts were observed in C V curves, and their magnitudes decreased as the defect states inside the SiN(x) films decreased.
author_names: Kyoung-Min Lee

W S Hong
title: Suppression of electrical breakdown in silicon nitride films deposited by catalytic chemical vapor deposition at temperatures below 200 degrees C.
venue: Journal of nanoscience and nanotechnology
year: 2011

abstract: The Electrical properties of Bi0.7Dy0.3FeO3 (BDFO) thin films deposited by pulsed laser deposition (PLD) on ZnO/Si films and its potential applications are discussed in this paper. MIS (metal/insulator/semiconductor) Capacitors of Cr Au/BDFO/ZnO/p Si structures have been fabricated and their interface traps and electrical properties have been investigated. To obtain the information about the interface trap states, systematic studies on the frequency dependent capacitances and conductance measurement were performed. Frequency dependent analysis of the device was made in the frequency range of 10kHz 500kHz. It was observed that dispersion of the oxide capacitance was 2% per decade within this frequency range. When the sweeping voltage changes from 3 to +4V the memory aperture was found to be increased from 300 to 850mV. This significant hysteresis property in the C V characteristics may be attributed to the slight ferroelectric behaviour of BDFO/ZnO film, which is essential for a memory device. It was also observed that density of trap state (Dit) is found approximately 9?1011cm 2eV 1 while increasing the frequency from 10kHz to 500kHz, the thickness of the oxide layer was 300nm in this experiment. The calculated dielectric constant of device ~190) is much higher than that of BDFO >30) The dielectric loss tangent of the device was found to initially increase with voltage then decrease, whereas the ac conductivity depicted an opposite trend. Multiferroic BDFO is promising material shows the good coupling between ferroelectric and ferromagnetic properties and ideal behaviour at room temperature. Integration of BDFO films with ZnO piezoelectric can be used directly as electricity generator with enhanced output in MEMS applications as well as in Memory devices. Display Omitted Frequency dependent analysis of the device was made in the frequency range of 10kHz 500 kHz.Memory aperture was found to be increased from 300 to 850 mVDensity of trap state (Dit) is found approximately 9?1011 cm 2 eV 1 for all frequenciesDielectric constant of device ~190) is much higher than that of BDFO >30)Dielectric Loss tangent of the device was found to initially increase with voltage then decrease
author_names: Deepak Bhatia

Sandipta Roy

Sajid Nawaz

Ram Swaroop Meena

V Palkar
title: Room temperature electrical properties of Bi0.7Dy0.3FeO3 thin films deposited by PLD on ZnO films for potential applications
year: 2016

abstract: 1. Background For Ge CMOS, a Ge MIS gate stacks with sub nm EOT at 600degC is necessarily required. Then, an extremely thin GeOx interface layer (IL) is needed to passivate the interface states [1] However, it is difficult in a subnm Ge MIS interface, because the oxidant in O2 PDA to improve the high k gate oxide should diffuse very fast through the very thin gate dielectrics and lead an increase of GeOx IL thickness due to Ge oxidation. Therefore, we have to make oxygen potential lowering at the interface thermodynamically to suppress the oxidation. Although a simple thermodynamic consideration deals with only temperature and pressure as its parameters, the oxygen potential lowering is then expected to suppress the oxidant diffusion dramatically. We have already reported that N doping can make the oxygen potential lowering in GeO2 [2] In this paper, we will demonstrate the effect of the oxygen potential lowering by the N doping into GeO2 on Ge from the viewpoint of the suppression of GeO desorption from GeO2/Ge and Ge MIS interface stabilization. 2. Experimental Procedure HF lasted Ge (100) wafers were used for the substrate. N doped GeO2 (GeON) films were deposited by N2 sputtering of a GeO2 target. N atom composition in GeON (N:O in at. and the film thickness were determined by XPS and GIXR, respectively. For MIS capacitors, Au and Al were evaporated as the gate electrode and the back contact, respectively. 3. Results and discussion First, we investigated the effect of N doping on GeO desorption from GeO2/Ge stacks. Fig. 1 shows that the GeO desorption is dramatically suppressed in GeON (20 at. N)/Ge stacks. Considering that oxygen vacancy (Vo) formation plays a key role for the GeO desorption [3] the N doping is expected to increase the Vo formation energy due to the oxygen potential lowering in GeO2. The suppression of the GeO desorption by N doping is quite advantageous for achieving both sub nm EOT and interface stabilization at 600degC at the same time. However, bulk traps and/or interface states might be still there because their passivation can be achieved by a kinetic process. Therefore, we investigated the effect of N doping on GeO2/Ge MIS characteristics. Fig. 2 shows the C V characteristics of a 6.3 nm thick GeON (15 at. N)/Ge MIS gate stack annealed in pure N2 at 600degC for 5 min. Almost zero hysteresis and well suppressed frequency dispersions are found. Considering that the GeO desorption terribly degrades the MIS properties in such a thin pure GeO2/Ge stacks [4] N doping dramatically affect to stabilize the GeO2/Ge MIS gate stacks. 4. Conclusions To control oxygen potential at the interface is the key to stabilize Ge MIS gate stacks with sub nm EOT. N doping successfully works to stabilize Ge MIS gate stacks without inducing the GeO desorption, bulk traps, and interface states at 600degC. References [1] R. Zhang et al. VLSI symp. p. 161, (2012) [2] T. Tabata et al. JSAP spring conference, 28p G2 9, (2013) [3] S. K. Wang et al. JJAP 50, 04DA01, (2011) [4] C. H. Lee et al. APEX 2, 071404, (2009)
author_names: Toshiyuki Tabata

Choong Hee Lee

Tomonori Nishimura

Kosuke Nagashio

Akira Toriumi
title: Oxygen Potential Lowering in N doped GeO2 for Ge MIS Gate Stack Design in Extremely Thin EOT Region
year: 2013

abstract: We propose the use of an aluminum oxynitride (AlON) gate insulator for 4H SiC MIS devices. Since direct deposition of AlON on 4H SiC substrate generates a large amount of interface charge due to an interfacial reaction, a thick AlON layer was deposited on underlying thin SiO2 thermally grown in N2O ambient. To reduce the negative fixed charge density in the aluminum oxide (Al2O3) film, we used reactive sputtering of Al in an N2/O2 gas mixture. The fabricated MIS capacitor with AlON/SiO2 stacked gate dielectric shows no flat band voltage shift and negligible capacitance voltage hysteresis (30 mV) indicating the dielectric is almost free from both fixed charges and electrical defects. Owing to the high dielectric constant of AlON (k=6.9) as compared to single N2O SiO2 gate insulator, significant gate leakage reduction was achieved by AlON/SiO2 stacked gate dielectrics even at high temperature, especially in a high electric field condition >5 MV/cm)
author_names: Takuji Hosoi

Makoto Harada

Yusuke Kagei

Yuu Watanabe

Takayoshi Shimura

Shuhei Mitani

Yuki Nakano

Takashi Nakamura

Heiji Watanabe
title: AlON/SiO2 Stacked Gate Dielectrics for 4H SiC MIS Devices
year: 2009

abstract: In the recent years a notable progress in the miniaturisation of electronic devices has been achieved in which the main component that has shown great interest is electronic memory. However, miniaturisation is reaching its limit. Alternative materials, manufacturing equipment and architectures for the storage devices are considered. In this work, an investigation on the suitability of silicon nanowires as the charge storage medium in two terminal non volatile memory devices is presented. Silicon nanostructures have attracted attention due to their small size, interesting properties and their potential integration into electronic devices. The two terminal memory devices presented in this work, have a simple structure of silicon nanowires sandwiched between dielectric layers (silicon nitride) on glass substrate with thermally evaporated aluminium bottom and top contacts. The silicon nanostructures and the dielectric layer were deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) technique. The electrical behaviour of the memory cell was examined by Current Voltage (I V) data retention time (Current time) and write read erase read measurements. Metal Insulator Semiconductor (MIS) structures were also prepared for further analysis. The same silicon nanowires were embedded into the MIS capacitors and Capacitance Voltage (C V) analysis was conducted. Strong I V and C V hysteresis as well as an electrical bistability were detected. The memory effect is observed by this electrical bistability of the device that was able to switch between high and low conductivity states.
author_names: Konstantina Saranti

Shashi Paul
title: Two Terminal Non Volatile Memory Devices Using Silicon Nanowires as the Storage Medium
year: 2014