Query: Major verilog

Candidate papers:

abstract: In semiconductor industries, speed of operation and the size of the computational devices are playing a major role. Size of a single transistor may limit the scaling of semiconductor devices. In turn, an alternative technology is needed for faster computation and to reduce the size of computational devices. One such technology is Reversible Logic. Parity preserving is a property that is added to reversible gates with the help of which, presence of errors can be detected. In this Paper, Parity Preserving Reversible Floating point multiplier (RFPM) which uses IEEE 754 standard representation is proposed using P2RG and Fredkin Reversible gates. This RFPM uses Carry select adder for Exponent addition and Carry save Multiplier for Mantissa multiplication. The architecture also includes a multiplexer, Bit slicer, rounding and normalization register. This Pipelined RFPM architecture is coded using Verilog and the same has been simulated using Modelsim 10.7c. Parameters such as Area, Power, Cell Utilization and Maximum operating frequency have been analyzed using Cadence Genus Synthesis 14.25. On Comparison of Pipelined RFPM with Non Pipelined RFPM between 180nm and 90nm technology, the results show that Pipelined RFPM using 90nm technology, occupies lesser Area and uses lesser number of cells by 67.17% and 4.42% respectively whereas, the Maximum operating frequency has increased by a factor of 2.73.
author_names: F Mhaboobkhan

Karuppannan Kokila

R Jothikha

K Lakshmi Preethikha
title: Design of Pipelined Parity Preserving Double Precision Reversible Floating Point Multiplier Using 90 nm Technology
venue: 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS)
year: 2020

abstract: Image enhancement plays an important role in all fields of applications, like biomedical, satellite images, graphical applications and many others. In today's world everything needs to work in real time, hence this study talks about the implementation of image enhancement technique. This technique uses hardware approach for analysing the quality of an image which gives less time and can be worked for parallel processing applications. As histogram of an image contains details such as pixel intensity, distribution of grey levels helps to understand and analyse the quality of an image. Here, we have proposed an efficient architecture for image enhancement technique and was simulated using Verilog HDL. This study outlines brightness enhancement and contrast stretching method which permits better visual appearance of an image. Also here we have proposed design for finding region of interest in an image by developing eight different grey levels which can be used in detecting object in an image as it is one of the major areas of research in biometric application.
author_names: Renuka Chinchwadkar

Vaishali V Ingale

Ashlesha Gokhale
title: Hardware Implementation of Histogram Based Algorithm for Image Enhancement
year: 2020

abstract: Major operation block in any processing unit is a multiplier. There are many multiplication algorithms are proposed, by using which multiplier structure can be designed. Among various multiplication algorithms, Wallace tree multiplication algorithm is beneficial in terms of speed of operation. With the advancement of technology, demand for circuits with high speed and low area is increasing. In order to improve the speed of Wallace tree multiplier without degrading its area parameter, a new structure of Wallace tree multiplier is proposed in this paper. In the proposed structure, the final addition stage of partial products is performed by parallel prefix adders (PPAs) In this paper, five Wallace tree multiplier structures are proposed using Kogge stone adder, Sklansky adder, Brent Kung adder, Ladner Fischer adder and Han carlson adder. All the multiplier structures are designed using Verilog HDL in Xilinix 13.2 design suite. The proposed structures are simulated using ISIM simulator and synthesized using XST synthesizer. The proposed designs are analyzed with respect to traditional multiplier design in terms of area (No. of LUTs) and delay (ns)
author_names: Yamini devi Ykuntam

Katta Pavani

Krishna Saladi
title: Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs
venue: 2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT)
year: 2020

abstract: Reversible logic is considered to be a major promising alternative to traditional digital logic circuits. It eliminates the possibility of information loss and makes the system run in the backward direction there by allowing the recovery of the inputs from the generated outputs. Converting an image from RGB to gray scale is crucial for majority of the image and video processing applications and also various computer vision applications as they reduce the computational complexity, storage space and increase the system speed. In this paper we have proposed three efficient reversible logic based schemes for the implementation of the color space converter units. We have implemented the RGB to gray scale converter units using three different techniques namely average method, desaturation and luminosity methods. The implementation of the proposed design and its functionality verification was done on XILINX 14.7 ISE and using Verilog HDL. The proposed design finds applications in many of the fields including image processing, video processing and high speed low power digital signal processing applications as well as computer vision applications like face gesture recognition, object detection, traffic monitoring systems and surveillance systems.
author_names: Swathi U

Smitha U
title: Design and Implementation of Efficient RGB to Gray scale Converter Architectures Using Reversible Logic
venue: 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)
year: 2020

abstract: A radiation induced single event upset (SEU) is a major disruption to electronics operating in satellites. If not rectified, a single bit error can become uncorrectable. In this paper, we present two interleaved Double Adjacent Error Corrections (DAECs) for Error Detection and Correction (EDAC) using the Hsiao Code and Cyclic Redundancy Code (CRC) From our results, both EDACs can correct 100% of the single bit errors, double adjacent bit errors, and detect double bit errors and up to four adjacent bit errors. The Hsiao Code EDAC encoder design requires less bit weight than the CRC EDAC, which is an attribute of a high speed EDAC. The CRC EDAC, in contrast, has a higher error detection rate for both three and four bit errors, at 96.25% and 91.92% respectively. We also propose two storage formats and algorithm designs that can manage and store the 48 bit codeword in 8 bit and 16 bit memory devices, a typical satellite scenario where board space is scarce. We used Verilog HDL, C+ and ModelSim to create and test our designs.
author_names: Mong Tee Sim

Yanyan Zhuang
title: Design of Two Interleaved Error Detection and Corrections using Hsiao Code and CRC
venue: IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society
year: 2020

abstract: The power efficiency of hardware circuits is of paramount importance for constructing embedded electronic devices, as it is one of the major design constraints in today's embedded systems, limiting performance, battery life, etc. This thesis targets the power efficiency in hardware circuits with symbolic discrete control. In the research proposed in this thesis, we consider hardware circuits, described using the popular Hardware DescriptionLanguage (HDL) Verilog, at the Register transfer Level (RTL) abstraction, as hierarchical compositions of sub circuits. We achieve power efficiency by switching off the clock of each sub circuit according to some clock gating logic, where the technique applied is known as RTL clock gating, which is one of the best low power technique applied on synchronous hardware circuits. We advance the following approaches in order to produce a clock gating logic: to switchoff the clock signal of a sub circuit in the idle status, which is a set of values of the circuit signals when the values of the memory components do not change; to apply power aware scheduling policies for data flow hardware circuits implemented as Kahn Process Networks (KPNs) using the clock gating logic as used to selectively filter the clocks of the sub circuits involved; and to employ an energy efficient configuration manager for choosing the optimal configuration, by means of the clock gating logic, among the alternatives on data flow hardware circuits implemented as KPN, with parallel synchronous processes. We devise a tool supported framework for achieving power efficiency of hardware circuits for each approach. Our approaches rely on formal control techniques, where the goal is to compute a strategy that can be used to drive a given model so that it satisfies a set of control objectives. More specifically, we give an algorithm that derives abstract behavioral models directly in a symbolic form from original designs, and for formulating suitable constraints and objectives. We encode the computation of the latter as several small symbolic Discrete ControllerSynthesis (DCS) problems, and use the resulting controllers to derive power efficient versions from original circuit designs. Finally, we show how a resulting strategy can be translated into a piece of synchronous circuit that, when paired with the original design, ensures the aforementioned objectives. We detail and illustrate our approaches using various hardware designs and objectives, and validate them experimentally by deriving a low power version of the original hardware designs.
author_names: Mete Ozbaltan
title: Achieving power efficiency in hardware circuits with symbolic discrete control
year: 2020

abstract: This paper presents the analysis of various architectures of Low power FFT Processors. FFT is a major building block in DSP and communication system. FFT is an efficient way to implement DFT in a faster manner. Using FFT the number of multiplication and addition order O(N/2log2N) and O(Nlog2N) are reduced. Conventional FFT has more chip area and delay. Hence pipelined FFT is preferred to overcome the demerits of the conventional processor. This paper reports a detailed study of various FFT architectures and mainly about R22SDF SDF FFT. In this paper, to reduce delay an advanced design of 64 point Pipelined Radix 22 Single Path Delay Feedback (R22SDF) FFT architecture has been proposed by using Verilog Hardware Description Language (Verilog HDL) The simulation results has been evaluated by using Modelsim 6.3C and synthesis results are estimated by using Xilinx Planahead 12.4i design tool.
author_names: C Ramesh Kumar

M P Chitra
title: Implementation of Area Efficient Pipelined R22SDF FFT Architecture
venue: 2020 7th International Conference on Smart Structures and Systems (ICSSS)
year: 2020

abstract: Abstract In processors the complex and challenging operations are needed to be handled to overcome the demands, which leads to an increase in processor cores. This leads to an increase in the load of the processor and can be limited by placing a co processors under specific type of functions like signal processing. But anyhow the speed of the ALU replies on the multiplier. Since multipliers are the major components to perform operations in the CPU. To implement fast multiplication operations, Vedic mathematics are involved based on 16 sutras, each with its special characteristics. This technique usually reduces the area, power and delay of the processors. So the existing Wallace tree multiplier technique has been replaced by the Vedic multiplier algorithms based on two different sutras as Urdhva Tiriyagbhyam and Nikhilam algorithms. These types of multipliers were designed and specified using Verilog HDL and have been synthesized and simulated using Xilinx ISE project Navigator v. 14. 7 platform and then compared with the parameters like delay time, area (Number of sliced LUT's and Number of bonded IOB's) and power in 32, 64 and 128 binary bit multiplication
author_names: M Kivi Sona

V Somasundaram
title: Vedic Multiplier Implementation in VLSI
year: 2020

abstract: Prevalent hardware description languages (HDLs) e.g. Verilog and VHDL, employ register transfer level (RTL) as their underlying programming model. One major downside of the RTL model is that it tightly couples design functionality with timing and device constraints. This coupling increases code complexity and yields code that is more verbose and less portable. High level synthesis (HLS) tools decouple functionality from timing and design constraints by utilizing constructs from imperative programming languages. These constructs and their sequential semantics, however, impede construction of inherently parallel hardware and data scheduling, which is crucial in many design use cases. In our work we present a novel dataflow hardware description abstraction layer as basis for hardware design and apply it to DFiant, a Scala embedded HDL. DFiant leverages dataflow semantics along with modern software language features (e.g. inheritance, polymorphism) and classic HDL traits (e.g. bit accuracy, input/output ports) to decouple functionality from implementation constraints. Therefore, DFiant designs are timing agnostic and device agnostic and can be automatically pipelined by the DFiant compiler to meet target performance requirements. With DFiant we demonstrate how dataflow HDL code can be substantially more portable and compact than its equivalent RTL code, yet without compromising its target design performance.
author_names: Oron Port

Yoav Etsion
title: Hardware Description Beyond Register Transfer Level Languages
venue: FPGA
year: 2020

abstract: Airborne Ad hoc Networks (AANETs) are a subclass of Vehicular Ad hoc Networks (VANETs) The major challenge in AANET implementation is the regular route breaks due to very high mobility of aircraft. To deal with this routing challenge in AANETs, we have designed a new protocol named Airborne OLSR (AOLSR) which is based on more optimisation of the MPR selection technique used in existing OLSR protocol. A hardware implementation of any protocol is always crucial for the validation of its design. So, this manuscript also provides a hardware implementation of both OLSR and AOLSR protocols using Verilog. The node architectures for both the protocols have been implemented in Vivado. The node's sub component implementation area, execution time and total power consumption have been used as parameters to compare their performance. The simulation analysis shows that the proposed AOLSR performs better as compared to OLSR in terms of total power consumption and execution time.
author_names: Pardeep Kumar

Seema Verma
title: Hardware implementation of OLSR and improved OLSR (AOLSR) for AANETs
year: 2020