Query: Scaling limits of electrostatic nanorelays

Candidate papers:

abstract: A model to explore the scaling limits of electrostatically actuated nanorelays is presented, which shows that adhesion in a nanorelay's contact interface limits its performance with respect to operating voltage, contact resistance, and switching energy. For logic applications, we show that an ultimately scaled relay can be more efficient than conventional metal oxide semiconductor devices if (1) it is designed with very high contact resistances, leading to 1 MHz operation due to large RC delays, or (2) its actuation area is extremely large compared with its contacting area, leading to very low voltage operation, which reduces overall CV2 losses. We propose new relay scaling relations that account for the scaling of contact interfaces.
author_names: Chytra Pawashe

Kevin L Lin

Kelin J Kuhn
title: Scaling Limits of Electrostatic Nanorelays
venue: IEEE Transactions on Electron Devices
year: 2013

abstract: Static and dynamic mechanical deflections were electrically induced in cantilevered, multiwalled carbon nanotubes in a transmission electron microscope. The nanotubes were resonantly excited at the fundamental frequency and higher harmonics as revealed by their deflected contours, which correspond closely to those determined for cantilevered elastic beams. The elastic bending modulus as a function of diameter was found to decrease sharply (from about 1 to 0.1 terapascals) with increasing diameter (from 8 to 40 nanometers) which indicates a crossover from a uniform elastic mode to an elastic mode that involves wavelike distortions in the nanotube. The quality factors of the resonances are on the order of 500. The methods developed here have been applied to a nanobalance for nanoscopic particles and also to a Kelvin probe based on nanotubes.
title: Electrostatic deflections and electromechanical resonances of carbon nanotubes
venue: Science
year: 1999

abstract: Microelectromechanical switches are of interest for low power circuit applications due to their minimal OFF state leakage current. This paper uses 22 nm CMOS fabrication technology and the clamped cantilever geometry as the basis for establishing design rules for electrostatic nanorelays and estimates the design parameters needed for nanorelay actuation. The adhesive pull off force of various substrate/cantilever combinations is simulated using molecular dynamics with a force field that parameterizes van der Waals interactions, and measured using atomic force microscopy. Both methods show that for the substrates studied, H passivated Si produces the least adhesive surface with adhesive pressure close to the critical pressure required for pull out. Experimental results quantifying adhesion and electrical current conduction show that it is impossible to simultaneously meet the adhesion and current conduction requirements of a nanorelay. We show that contact adhesion is the key parameter limiting the scalability of electromechanical relays at the nanoscale.
author_names: Kevin L Lin

Graham L W Cross

Peter Gleeson

Johann P de Silva

Alejandro Levander

Jorge A Munoz

Chytra Pawashe

Alexis Potie

Patrick Lauren Theofanis

John J Boland

Kelin J Kuhn
title: Adhesion Limits and Design Criteria for Nanorelays
venue: IEEE Transactions on Electron Devices
year: 2016

abstract: The exploding market of portable electronic appliances has fuelled the demand for complex integrated systems that can be run by light weight batteries with long shelf life. But as technology continued to scale, leakage power has proven to be a dominant source of power dissipation. Looking beyond the Complementary Metal Oxide Semiconductor (CMOS) transistor, this paper presents an unexplored alternative the Nanorelay that can potentially eradicate the foreseen crisis in the IC era. By using modern CMOS processes the relay can get a microscopic makeover which can lead to further advances in power reduction as these devices posses "green switch" properties like zero leakage current, infinite sub threshold slope and temperature resilient behavior and are hence ideal candidates for ultra low power (ULP) chips that can run of scavenged energy from light, acoustic vibrations or ambient RF signals and primarily for realizing programmable switches in FPGAs. Power consumption is a key issue in the design of portable systems such as smart cards, pacemakers and defibrillators that posses critical functionality. These systems rely on embedded batteries as their source of power which has limited life. Increased power consumption leads to increased battery size and an increase in product size and weight. Henceforth, methods of reducing power is explored and incorporated.
author_names: S Shetty

Syed Shafiuddin
title: Nanorelays Power Driver of the Next Decade

abstract: We report on the electromechanical actuation and switching performance of nanoconstructs involving doubly clamped, individual multiwalled carbon nanotubes. Batch fabricated, three state switches with low ON state voltages (6.7 V average) are demonstrated. A nanoassembly architecture that permits individual probing of one device at a time without crosstalk from other nanotubes, which are originally assembled in parallel, is presented. Experimental investigations into device performance metrics such as hysteresis, repeatability and failure modes are presented. Furthermore, current driven shell etching is demonstrated as a tool to tune the nanomechanical clamping configuration, stiffness, and actuation voltage of fabricated devices. Computational models, which take into account the nonlinearities induced by stress stiffening of 1 D nanowires at large deformations, are presented. Apart from providing accurate estimates of device performance, these models provide new insights into the extension of stable travel range in electrostatically actuated nanowire based constructs as compared to their microscale counterparts.
author_names: Arunkumar Subramanian

Andreas R Alt

Lixin Dong

Bradley Kratochvil

Colombo R Bolognesi

Bradley J Nelson
title: Electrostatic actuation and electromechanical switching behavior of one dimensional nanostructures.
venue: ACS nano
year: 2009

abstract: We demonstrate the use of torsion in nanorelays to achieve low voltages, high speeds, single lithography step construction, and a form useful for configurability and electronic design enhancements in 3 D integrated implementations. The combined bending and torsion of self aligned nanopillars facilitates the first top down fabricated vertical three terminal nanoscale relay. Experimental devices, even at 500 nm features, operate at ~10 V and 1 3 ms. Scaling to 45 nm suggests operation at approximately 1 V.
author_names: Joshua Rubin

Ravishankar Sundararaman

Moonkyung Mark Kim

Sandip Tiwari
title: A Low Voltage Torsion Nanorelay
venue: IEEE Electron Device Letters
year: 2011

abstract: We proposed and demonstrated a mechanically operated random access memory (MORAM) based on an electrostatically actuated metallic microswitch for nonvolatile memory applications. The metallic microswitch based MORAM successfully showed program and erase operations, wherein the microswitch had an essentially zero off current, an abrupt switching with less than 1 mV/dec, and an on/off current ratio over 107, and its stored charge was investigated with the metal oxide semiconductor (MOS) capacitor. Moreover, first reported were an endurance of up to 105 cycles in air ambient and a retention time of more than 104 s in vacuum ambient.
author_names: Weon Wi Jang

Jeong Oen Lee

Hyun-Ho Yang

Jun-Bo Yoon
title: Mechanically Operated Random Access Memory (MORAM) Based on an Electrostatic Microswitch for Nonvolatile Memory Applications
venue: IEEE Transactions on Electron Devices
year: 2008

abstract: The charge distribution on the surface of a biased conductive, finite length, cylindrical nanotube, free standing above an infinite grounded plane, is investigated. The diameter range of the cylinder tube under study is 20 60 nm, which is much larger than the screening length, meaning the quantum and statistical effects on the charge distribution are negligible. The relationship between the charge distribution and the geometry of the nanotube is examined in detail by classical electrostatics using full three dimensional numerical simulations based on the boundary element method. A model of the concentrated charge at the end of nanotubes is proposed. The charge distribution for a clamped cantilever nanotube is also computed and discussed. The findings here reported are of particular usefulness in the design and modeling of electrostatic actuated nanotube/ nanowire based nano electromechanical systems.
author_names: Changhong Ke

Horacio Dante Espinosa
title: Numerical Analysis of Nanotube Based NEMS Devices Part I: Electrostatic Charge Distribution on Multiwalled Nanotubes
year: 2005

abstract: In this Letter, we demonstrate a strong dependence of the electrostatic deformation of doubly clamped single walled carbon nanotubes on both the field strength and the tube length, using molecular simulations. Metallic nanotubes are found to be more sensitive to an electric field than semiconducting ones of the same size. For a given electric field, the induced deformation increases with tube length but decreases with tube radius. Furthermore, it is found that nanotubes can be more efficiently bent in a center oriented transverse electric field.
author_names: Zhao Wang

Laetitia Philippe
title: Deformation of doubly clamped single walled carbon nanotubes in an electrostatic field.
venue: Physical review letters
year: 2009

abstract: This paper qualitatively explores the performance limits, i.e. energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1 dimensional reduced order model (ROM) of the switch; the results given by this simplified model are compared to classical CMOS based, and sub threshold CMOS based adiabatic logic circuits. NEMS based circuits and CMOS based circuits show different optimum operating conditions, depending on the device parameters and circuit operating frequency.
author_names: Samer Houri

Christophe Poulain

Alexandre Valentian

Herve Fanet
title: Performance Limits of Nanoelectromechanical Switches (NEMS) Based Adiabatic Logic Circuits
year: 2013