Query: Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits

Candidate papers:

abstract: Among the beyond complementary metal oxide semiconductor (CMOS) devices being explored, ferroelectric field effect transistors (FeFETs) are considered as one of the most promising. FeFETs are being studied by all major semiconductor manufacturers, and experimentally, FeFETs are making rapid progress. FeFETs also stand out with the unique hysteretic <inline formula> <tex math notation="LaTeX"$I_{\text {ds} /tex math>/inline formula> <inline formula> <tex math notation="LaTeX"$V_{\text {gs} /tex math>/inline formula> characteristic that allows a device to function as both a switch and a nonvolatile (NV) storage element. We exploit this FeFET property to build two categories of fine grained logic in memory (LiM) circuits: 1) ternary content addressable memory (TCAM) which integrates efficient and compact logic/processing elements into various levels of memory hierarchy; 2) basic logic function units for constructing larger and more complex LiM circuits. Two writing schemes (with and without negative supply voltages respectively) for FeFETs are introduced in our LiM designs. The resulting designs are compared with existing LiM approaches based on CMOS, magnetic tunnel junctions (MTJs) resistive random access memories (ReRAMs) ferrorelectric tunnel junctions (FTJs) etc. that afford the same circuit level functionality. Simulation results show that FeFET based NV TCAMs offer lower area overhead than MTJ (79% and CMOS (42% less) equivalents, as well as better search energy delay products (EDPs) than TCAM designs based on MTJ <inline formula> <tex math notation="LaTeX"$149\times /tex math>/inline formula> ReRAM <inline formula> <tex math notation="LaTeX"$1.7\times /tex math>/inline formula> and CMOS <inline formula> <tex math notation="LaTeX"$1.3\times /tex math>/inline formula> in array evaluations. NV FeFET based LiM basic circuit blocks are also more efficient than functional equivalents based on MTJs in terms of propagation delay <inline formula> <tex math notation="LaTeX"$4.2\times /tex math>/inline formula> and dynamic power <inline formula> <tex math notation="LaTeX"$2.5\times /tex math>/inline formula> A case study for an FeFET based LiM accumulator further demonstrates that by employing FeFET as both a switch and an NV storage element, the FeFET based accumulator can save area (36% and power consumption (40% when compared with a conventional CMOS accumulator with the same structure.
author_names: Xunzhao Yin

Xiaoming Chen

Michael Thaddeus Niemier

Xiaobo Sharon Hu
title: Ferroelectric FETs Based Nonvolatile Logic in Memory Circuits
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2019

abstract: Due to their CMOS compatibility, hafnium oxide based ferroelectric field effect transistors (FeFET) gained remarkable attention recently, not only in the context of nonvolatile memory applications but also for being an auspicious candidate for novel combined memory and logic applications. In addition to bringing nonvolatility into existing logic circuits (Memory in Logic) FeFETs promise to guide the way to compact Logic in Memory solutions, where logic computations are examined in memory arrays or array like structures. To increase the area efficiency of such circuits, a dense integration of FeFETs and standard FETs is essential. In this paper, we show that the ultra dense co integration of FeFETs and nFETs (28nm HKMG) with shared active area does not alter the FeFET's switching behavior, nor does it affect the baseline CMOS. Based on this, we propose the integration of a FeFET based, 2 input look up table (memory) directly into a 4 to 1 multiplexer (logic) which is utilized directly in a 2TNOR memory array or stand alone circuit. The latter one dramatically reduces the transistor count by at least 33% compared to similar FeFET based circuits. By storing values of the look up table in a nonvolatile manner, no energy is consumed during standby mode, which enables normally off computing. To take another step towards novel Logic in Memory designs, we experimentally demonstrate a very compact in array 2T half adder and simulate an array like 14T full adder, which exploit the advantages of the array arrangement: easy write procedure and a very compact, robust design. The proposed circuits exhibit energy efficiency in the (sub)fJ range and operation speeds of 1GHz.
author_names: Evelyn T Breyer

Halid Mulaosmanovic

Jens Trommer

Thomas Melde

Stefan Dunkel

Martin Trentzsch

Sven Beyer

Stefan Slesazeck

Thomas Mikolajick
title: Compact FeFET Circuit Building Blocks for Fast and Efficient Nonvolatile Logic in Memory
venue: IEEE Journal of the Electron Devices Society
year: 2020

abstract: As an emerging nonvolatile device, ferroelectric field effect transistors (FeFETs) have the potential to reduce the power and area by integrating nonvolatile storage elements with logic. The hysteretic behavior allows an FeFET to function as both a nonvolatile storage element and a switch. This paper exploits this feature of FeFETs to design lookup tables (LUTs) and routing switches, which have obvious utility in field programmable gate arrays (FPGAs) Read and write schemes are also designed for the proposed LUTs and routing switches. Evaluation results based on a calibrated FeFET model show that the proposed designs are competitive in power and performance. For example, compared with conventional complementary metal oxide semiconductor (CMOS) based equivalents, the proposed FeFET based LUTs and routing elements improve the power delay product (PDP) by 5.8 <inline formula> <tex math notation="LaTeX"$16\times /tex math>/inline formula> respectively, while compared with resistive random access memory (RRAM) based equivalents, the proposed designs improve the PDP by 1.14 <inline formula> <tex math notation="LaTeX"$1.8\times /tex math>/inline formula> The area of an FeFET based FPGA is 8% smaller than a conventional CMOS based FPGA.
author_names: Xiaoming Chen

Kai Ni

Michael Thaddeus Niemier

Yinhe Han

Suman Datta

Xiaobo Sharon Hu
title: Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2019

abstract: Logic in memory circuits promise to overcome the von Neumann bottleneck, which constitutes one of the limiting factors to data throughput and power consumption of electronic devices. In the following we present four input logic gates based on only two ferroelectric FETs (FeFETs) with hafnium oxide as the ferroelectric material. By utilizing two complementary inputs, a XOR and a XNOR gate are created. The use of only two FeFETs results in a compact and nonvolatile design. This realization, moreover, directly couples the memory and logic function of the FeFET. The feasibility of the proposed structures is revealed by electrical measurements of HKMG FeFET memory arrays manufactured in 28nm technology.
author_names: Evelyn T Breyer

Halid Mulaosmanovic

Stefan Slesazeck

Thomas Mikolajick
title: Demonstration of versatile nonvolatile logic gates in 28nm HKMG FeFET technology
venue: 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
year: 2018

abstract: Systematic design space exploration of negative capacitance ferroelectric field effect transistors (FeFETs) for nonvolatile memory operations was performed, combining load line analyses and circuit simulations. Unlike those FeFETs aiming at a steep subthreshold slope, the key design target here is to achieve bi stable current versus voltage FET characteristics with appropriate hysteresis width (i.e. memory window) Remanent polarization, coercive voltage, and interfacial layer thickness were selected as design parameters. The results show that, if a ferroelectric gate dielectric film obeying ideal single domain Landau Khalatnikov model dynamics with reduced remanent polarization is available, ultralow voltage nonvolatile memories operating with sub one volt voltage swing would become possible. An interesting feature of the negative capacitance FeFETs is that, unlike conventional multiple domain FeFETs, the memory window can be adjusted to a much smaller value than twice the coercive voltage. The lowered remanent polarization is required to suppress the depolarization field to an acceptable level for reliability. It is proposed that considering the abrupt polarization switching, three transistor and two transistor memory cells would be suitable for working and code storage memories, respectively.
author_names: Kiyoshi Takeuchi

Masaharu Kobayashi

Toshiro Hiramoto
title: Design space exploration of hysteretic negative capacitance ferroelectric FETs based on static solutions of Landau Khalatnikov model for nonvolatile memory applications
year: 2021

abstract: Compute in memory (CiM) is a promising method for mitigating the memory wall problem in data intensive applications. The proposed bitwise logic in memory (BLiM) is targeted at data intensive applications, such as database, data encryption. This work proposes a low power BLiM approach using the emerging nonvolatile ferroelectric FETs with direct write back and data adaptive dynamic sensing interface. Apart from general purpose random access memory, it also supports BLiM operations such as copy, not, nand, xor, and full adder (FA) The novel features of the proposed architecture include: (i) direct result write back based on the remnant bitline BLiM charge that avoids bitline sensing and charging operations; (ii) a fully dynamic sensing interface that needs no static reference current, but adopts data adaptive voltage references for certain multi operand operations, and (iii) selective bitline charging from wordline (instead of pre charging all bitlines) to save power and also enable direct write back. Detailed BLiM operations and benchmarking against conventional approaches show the promise of low power computing with the FeFET based circuit techniques.
author_names: Ming-En Lee

Wenjun Tang

Bowen Xue

Juejian Wu

Mingyuan Ma

Yongpan Liu

Deliang Fan

Narayanan Vijaykrishnan

Huazhong Yang

Xueqing Li
title: FeFET based low power bitwise logic in memory with direct write back and data adaptive dynamic sensing interface
venue: ISLPED
year: 2020

abstract: Emerging non volatile memories are getting new interest in the system design community. They are used to design logic in memory circuits and propose alternatives to von Neuman architectures. Hafnium oxide based based ferroelectric memory technology, which is fully compatible with CMOS technologies is particularly interesting for logic in memory designs. Indeed, this compatibility leads to various possibilities for fine grain logic in memory applications where the memory capable element is tightly integrated with the transistors in the system. Nonvolatile and energy efficient computing for Internet of things and embedded artificial intelligence are among the potential applications for this technology.In this article, we focus on ferroelectric field effect transistors (FeFET) and present an overview of three different fine grain logic in memory possibilities with FeFETs: custom operation designs, reconfigurable circuits and a hybrid memory element accessible by content or by address. All presented circuits have been designed within a test chip using 28nm technology provided by GLOBALFOUNDRIES.
author_names: Cedric Marchand

Ian O'Connor

Mayeul Cantan

Evelyn T Breyer

Stefan Slesazeck

Thomas Mikolajick
title: FeFET based Logic in Memory: an overview
venue: 2021 16th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS)
year: 2021

abstract: In this work, we report hafnium zirconium oxide (HZO)/indium gallium zinc oxide (IGZO) based programmable ferroelectric (FE) diode memory array with ultra fast sub ns switching speed, thus extremely low sub fJ switching energy for future in memory and neuromorphic computing applications for the first time. The fabricated devices have electroresistance ratio of 3x105 and show robust cyclic endurance up to 109. In particular, we demonstrated a nonvolatile logic in memory circuit to implement NOT gate and incremental conductance changes to mimic analog nature of synaptic weights.
author_names: Taehwan Moon

Sang Hee Hong

Duk-Hyun Choe
title: Ferroelectric Diodes with Sub ns and Sub fJ Switching and Its Programmable Network for Logic in Memory Applications
venue: 2021 Symposium on VLSI Technology
year: 2021

abstract: This paper presents an overview of the operation and applications of reconfigurable ferroelectric transistors (R FEFETs) which offer unique logic memory coupling in the device characteristics leading to novel circuit design possibilities. R FEFETs feature dynamic reconfiguration between (a) volatile mode for logic operations and (b) nonvolatile mode for memory operation. An R FEFET consists of two FE stacks which interact with each other and a common underlying transistor, to enable run time tuning of hysteresis and the aforementioned reconfigurability. We discuss how such novel features of R FEFETs can be utilized to design energy efficient non volatile memory (NVM) and non volatile flip flop (NVFF) designs. For NVMs, read write conflicts can be effectively mitigated. In particular, R FEFETs based 3T NVM exhibit significant advantage over existing standard FEFET based NVM design with 55% lower write power and 37 72% lower read power at iso access time. R FEFET based NVFFs offer the design options of an auto backup (RNVFF 1) without the need of any additional circuitry back up control signals, or on demand backup (RNVFF 2) with lower normal operational energy over RNVFF 1. Compared to an FEFET based NVFF, RNVFF 1 achieves 47% lower check pointing energy, with a penalty of 6% in operation energy. RNVFF 2 shows 30% lower check pointing energy with similar operation energy. At the system level, the RNVFFs achieve 25 33% register level energy savings, in a state of the art intermittently powered platform.
author_names: Sandeep Krishna Thirumala

Arnab Raha

Narayanan Vijaykrishnan

Vijay Raghunathan

Sumeet Kumar Gupta
title: Non volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
venue: 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
year: 2019

abstract: Future data intensive applications will have integrated circuit architectures combining energy efficient transistors, high density data storage and electro optic sensing arrays in a single chip to perform in situ processing of captured data. The costly dense wire connections in 3D integrated circuits and in conventional packaging and chip stacking solutions could affect data communication bandwidths, data storage densities, and optical transmission efficiency. Here we investigated all ferroelectric nonvolatile LiNbO 3 transistors to function through redirection of conducting domain walls between the drain, gate and source electrodes. The transistor operates as a single pole, double throw digital switch with complementary on/off source and gate currents controlled using either the gate or source voltages. The conceived device exhibits high wall current density and abrupt off and on state switching without subthreshold swing, enabling nonvolatile memory and sensor in logic and logic in memory and sensor capabilities with superior energy efficiency, ultrafast operation/communication speeds, and high logic/storage densities. There is growing interest in non traditional materials for logic applications. Here, the authors demonstrate a domain device architecture based on ferroelectric LiNbO 3 crystals with gate voltage controlled transistor without subthreshold swing and source voltage controlled nonvolatile transistor.
author_names: Xiaojie Chai

Jun Jiang

Qinghua Zhang

Xu Hou

Fanqi Meng

Jianbao Wang

Lin Gu

David-Wei Zhang

An Quan Jiang
title: Nonvolatile ferroelectric field effect transistors
venue: Nature Communications
year: 2020