Query: wafer sort testing in fabs

Candidate papers:

abstract: In this paper, we have performed an empirical evaluation of several analog trimming methodologies used for Semiconductor Manufacturing Wafer Sort testing. The study shows that a dynamic trimming approach is the best among those evaluated. The other methodologies evaluated in this paper suffer for several weaknesses such as: 1) unwanted yield loss when the actual least significant bit (LSB) equivalent value or weight drifts from the characterized value due to fab process variations, 2) higher test time leading to elevated cost of test and delivery cycle time degradation, and 3) continual need for Test Program modifications to account for fab process shifts. Finally, a review of basic trimming principles will be covered. We will discuss the need for parameter trimming in the semiconductor industry along with common analog trimming algorithms and review actual wafer test data at wafer probe.
author_names: Rex F Bullag

Rolando C Ortega

Sorina B Bullag
title: Adaptive trimming test approach The efficient way on trimming analog trimmed devices at wafer sort
venue: 36th International Electronics Manufacturing Technology Conference
year: 2014

abstract: Wafer level packages continue to see strong growth driven by mobile phones, portable players, digital cameras and tablets. All these devices use small form factor and low profile packages such as a wafer level chip scale package (WLCSP) as it fits the requirements. Conventional flip chip die with solder bump is growing due to the increasing number of new design packages converting from wire bond and new flip chip interconnects such as copper pillar and micro bump are growing as a result of strong demand in 3D stacked ICs. Both WLCSP and flip chip need to be electrically tested in wafer format at some point in the assembly process, either as a Known Good Die (KGD) in 3D ICs or an end product that goes into the PCB of an electronic gadget. Wafer sort or wafer level testing was once considered as a method to save packaging cost as this process sorts out bad die before it is assembled into a package. However, today wafer sort or wafer level testing is an important process for yield enhancement of flip chip packages and a final test requirement for WLCSPs. The challenge of wafer level testing has grown significantly due to the increasing complexity of the die or packages. The current technology started to see limitations in hardware and tools. This paper investigates the challenges facing wafer level testing as well as examining the solutions available to overcome these challenges, identifying the gaps and additional innovation needed to overcome these challenges. INTRODUCTION For many years, wafer level testing or wafer sort was employed for two reasons. Firstly, it is to sort out bad dies to prevent them from being assembled into the final package and this would save the cost of packaging. Secondly, the purpose of wafer level testing is to provide yield feedback to the wafer fab in time to control the wafer fabrication process [1] These two purposes are still valid today. However, as packaging technology advances, wafer level packages such as flip chip and WLCSP changes the wafer test requirements not only for yield enhancement of the final package, but also full coverage of testing as it takes the final form of the end package. These bumped types of wafers need to be contacting at solder bumps instead of pads during test. It seems relatively easy compared to contacting pads as bumps are larger in size and wider in pitch; however, the real situation is more complex as the challenges of testing these bumped chips are different. Wafer Level Packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level and it takes many forms. There are WLCSP, flip chip dies built into flip chip or 3D packages and all these dies or packages need wafer level testing. PACKAGES REQUIRE WAFER LEVEL TESTING The traditional functions of a semiconductor device package are to provide environmental protection for the die built in it. However, this need of protection becomes less important with the short expected life of the IC and advancement in material used in building the wafer level package. Wafer Level Chip Scale Packaging (WLCSP) as its name "Chipscale package" implies, is a wafer level packaged die with grid array bumps at pitches of 0.4mm and above. This bumped integrated circuits package goes directly onto printed circuit boards of end electronic products such as mobile phones which are one of the fastest growing package types in the semiconductor industry. Fabrication and testing of WLCSPs are done at the wafer level. As the manufacturing cost drops with increased wafer size and reduced die size, cost competitiveness becomes a main motivation to replace traditional QFN packages in mobile devices with WLCSPs. WLCSP is not new; it started with small size and low I/O a decade ago till today with high pin counts and larger package size as shown in below figure 1. In the extension of WLCSP, fan out wafer level technology overcomes interconnect density limitations on PCBs and Figure 1: Large WLCSP with I/O above 100 reduces the need for bump interconnects [2] One typical example of fan out technology is embedded wafer level BGA (eWLB) show in below figure 2. Flip chip and wire bond are the two standard processes to connect the die to a substrate. The flip chip device continues to see strong growth with an increasing number of new designs converting from wire bond. The reasons for the conversion can be attributed to the advantages of its thermal and electrical properties, lower cost and ability to support high I/O count with a smaller package relative to the die size; as shown in figure 3 below. The connection area required for flip chip is much smaller than what is required for wire bonding because all the I/Os from the chip are connected through the bottom. [3] Flip chip packaging uses area array solder bump configurations and its typical bump pitch is 150mm. Figure 4 shows examples of final flip chip packages in the form of fcBGA and fcFBGA that are in high volume manufacturing now. As the need for increased I/O signal connections grow; the bump pitch has to decrease. In order to maintain standoff height with decreasing pitch, a solid column type bump has to be employed and this is copper column bump. Flip chip with copper column bump is expected to see greater demand as the need the fine pitch solutions increase. There are two approaches for copper column bumps as shown in figure 5 below: one with a solder cap and the other without. Copper column bump pitch can be as low as 40mm and this makes testing them very difficult. 3D packaging is driven by wireless and consumer products that require package level functional integration in a small footprint, low profile and lower in cost. 3D packages come in many different forms. For some, flip chip dies are used in the package and certainly these dies must be known good die (KGD) to ensure the end package quality. Figure 6 shows an example of a 3D package with flip chip die. Figure 2: Embedded Wafer Level BGA (eWLB) Figure 3: Flip chip connection area compared to wire bond connection area Figure 4: Flip Chip packages Figure 5: Copper column bump. (Top photo shows solder cap version) NEW CHALLENGES IN WAFER LEVEL TESTING The paradigm for wafer level test is changing rapidly. The original intent of final yield enhancement and feedback to the wafer fab for process control for performance wafer sort has expanded. With new package or die types needed to test in wafer level, different challenges have surfaced. Comparing package handling in a test handler where wafers are effectively all the same, it would appear that the handling of wafers would be an easier task. The actual handling, though, is probably more difficult since wafers are extremely fragile and damaging even one wafer is unacceptable due to the large number of valuable dies lost. The handling equipment or prober needs to be extremely precise and intelligent to handle these fragile wafers. Wafer level test handling equipment or probers face significant technical challenges in different markets or wafer types. One of the common issues is the need for high parallelism test. For high parallelism requirements, the prober needs to have accurate alignment capability and very high force test chuck for presenting the wafer to probe card for contacting. There is even a need for full wafer contact of a 300mm wafer with thousands of solder bumps and it becomes a challenge for providing increasing insertion force without damaging the fragile wafer. In wafer handling, different types of wafers need to be processed in the same prober. We see thin wafers at high warpage that need to be tested. These wafers go through back grinding to the required end thickness before wafer testing on the prober. Typically a standard prober can handle up to 350mm thickness. For wafers thinner than 350mm, there is an increased tendency to warp badly and make handling in a prober very difficult. In this case, a special tool or kit will be needed to handle this type of thin wafer. However, any wafer thickness of less than 150mm is still a challenge for the prober to handle. With the new type of wafers such as eWLB gaining popularity, the prober now needs to handle wafers with different surfaces or materials. These eWLB wafers are different from normal silicon wafers as the backside of the wafers are a mold compound and they tend to have a higher warpage level with a similar thickness as silicon wafer as shown in figure 7 The above mentioned challenges need to be overcome with good handling equipment. Probers now need to have capability and/or options as listed below: High force chuck for high parallelism Wafer handling arm and chuck to handle thin and warped wafers Chuck that can handle different material of wafer such as eWLB wafers with molded material at backside of the wafer Intelligence optical alignment for fine pitch bumps High speed wafer changing and indexing As the requirements get more stringent, probers will need to continue improving to meet all the new requirements. The overall end user would need a flexible and cost effective prober to handle different requirements and situations. PROBE CONTACT CHALLENGES As the need for increased I/O signal connections grow, the bump pitch has to decrease and maintain a greater standoff height. A solid column type of bump is created either in solid copper column or with an added solder cap. Fine pitch is always a challenge for probe card geometry and precision. A prober that handles fine pitch wafers needs the precision to achieve an accurate probing. Currently, flip chip die with 150mm pitch is in mass production without Figure 6: Example of 3D package Figure 7: eWLB warpage condition issue. Typically this type of bumped wafer uses a vertical probe card with buckling beam type of contact pins. As the pitch of copper column bump scales below 100mm, this type of vertical probe card design cannot scale down to the required pitch. Advanced probe cards with MEMS technology will be need
author_names: Lim Kok Hwa

Andy Chee
title: " Wafer Level Testing Challenges for Flip Chip and Wafer Level Packages "
year: 2013

abstract: In Semiconductor Manufacturing, inline Inspection monitoring by Brightfield and Darkfield scan tool platform is a 2nd line of defence to detect abnormal events to prevent defectivity escape to Wafer Sort or Assembly Test. Early detection and good process tool coverage are essential to the quality of wafers. These have to be balanced with competitive cycle time and cost. There are many newer scan tool, software and manufacturing systems available today that can optimize this sampling monitoring. As a legacy 200mm foundry wafer fab, system upgrade may not be feasible or can be expensive. As a result, an innovative solution had to be developed in order to stay relevant in the semiconductor industry. This paper introduces an inline inspection sampling Artificial Intelligent (AI) methodology to ensure maximum process tool scan coverage without additional CAPEX cost getting more out from the same capacity; getting more coverage with same scan capacity and improve line of defence.
author_names: Ang Kian Huat

Jonathan Boon Kwang Yap

Ning Ning

Tan Siew Fen

Shakar Govindasamy Mani

Myla Terredano
title: Smart Sampling Methodology for Yield Defect Inspection in a 200mm Foundry Wafer Fab
venue: 2018 International Symposium on Semiconductor Manufacturing (ISSM)
year: 2018

abstract: Abstract This paper discusses two airborne molecular contaminants (AMCs) decontamination and control solutions for Front Opening Unified Pods (FOUPs) namely, inert gas purge and aqueous wet cleaning, and the effect these processes have on HF volatile acid cross contamination of Cu coated wafers stored inside FOUPs of different polymer types, polycarbonate (PC) polycarbonate carbon powder (PCCP) and Entegris Barrier Materials (EBMCNT) The obtained results show that continuous FOUP purge appears to be an effective way to control HF cross contamination, to guarantee an optimum yield thanks to low humidity, and to clean chemically the environment from AMCs. Wet cleaning is an option after a high contaminating process. Wet cleaning removes the acid contamination from within the polymer near the surface, and removal efficiency is dependent on queue time; a higher removal rate is expected with a shorter queue time. The EBMCNT FOUP is the best of the materials tested in terms of HF contamination transfer reduction. Finally, numerical simulation (using a simple membrane model) shows that irreversible contamination results from the accumulation of the residual contamination in the polymer.
author_names: Paola Gonzalez-Aguirre

Herve Fontaine

Sung In Moon

Carlos Beitia

Jorgen Lundgren

Jim Ohlsen
title: FOUP decontamination solutions to control AMCs in semiconductor fabs: Gas purge or wet cleaning?
year: 2018

abstract: Semiconductor reliability in applications such as automotive is getting increased attention as design rules shrink to include 1Xnm, semiconductor content per vehicle continues to grow, applications become more critical and reliability requirements tighten. Current automotive requirements stipulate less than one defective part per million (DPPM) Approaches to address reliability include improving design, manufacturing and test. Process control in manufacturing is critical for reliability and includes continuous improvement for reducing process tool defectivity, excursion monitoring of process tools and product lines, golden or best performing tool methods [1] measurement system analysis (MSA) methods and screening. Inline defectivity is known to have an impact on both yield and reliability [2] and defects can impact reliability in one of two ways. Killer defects located in areas that are untested can result in so called Zero Kilometer failures. In other cases, the same types of defects that cause yield loss can also cause latent reliability failures the difference being size, location and density. Latent reliability defects become activated after test and can include defect types such as partial bridges, partial opens, and embedded particles. Current reliability engineering relies on outlier detection rules like parametric part average testing (P PAT) [3] or geographic part average testing (G PAT) both of which are derived from end of line screening data, which is based solely on electrical test data [4] Inline Part Average Testing (I PAT(tm) is enabled by multi channel high speed LED scanning inspection technology and offers an opportunity to apply fab data to reliability engineering. Defect inspection results are analyzed with machine learning (ML) to weigh the defectivity and create a die level defectivity metric allowing the statistical identification of die which are a high reliability risk [5, 6] Two case studies are described. The first case is a feasibility study based on historical fab defectivity data and includes a sample of ~250,000 die, with eight inline defect inspections per wafer, including four front end of line (FEOL) and four back end of line (BEOL) on a high sensitivity broadband inspection system [7, 8] Each defect is assigned a weight based on its impact to various "ground truth" indicators. The combined impact of all defects in a given die stacked across all inspections is aggregated into a die level metric. Plotting the die level I PAT metrics for all the die as a Pareto chart allows outliers to be identified using accepted statistical methods [9] I PAT metrics can then be correlated to electrical wafer sort (EWS) yield or fallout rate, specific wafer sort bins, EWS parametric test performance and post burn in electrical test. Of key importance is that wafer test was not used to train the I PAT model, and therefore this method is an independent validation of latent reliability. The second case study focuses on production screening feasibility with multi channel high speed LED scanning, and addresses overkill, or the over inking of potentially good die based on inline defectivity, which is a critical challenge that must be overcome for production implementation [10] Using inspection enabled by high speed LED scanning technology, die screening is a critical component of a comprehensive automotive Zero Defect program. Applications include early detection of fab excursions, feedback for continuous improvement of inline defectivity, feedforward to optimize electrical test methods and screening of die containing possible latent reliability defects. The I PAT methodology can be used to enhance standard end of line outlier detection rules such as P PAT [3] which is based solely on parametric testing.
author_names: John C Robinson

Kara Sherman

Dave W Price

Jay Rathert
title: Inline Part Average Testing (I PAT) for automotive die reliability
venue: Advanced Lithography
year: 2020

abstract: Typical usage of test wafers (TW) in semiconductor manufacturing involves testing and development of new processes, equipment qualification, and process monitoring activities. A 300 mm fab can potentially spend millions of dollars each year purchasing test wafers. Over the years, improvements in TW management systems have led to a reduction in cost by enabling better inventory control. However, even with the increased level of automation of 300 mm fabs, the TW management process still leaves much to be automated. In this paper, we describe an automated TW management system and the performance benefits derived from its usage.
author_names: Anam Faruqi

Raymond Goss

Diwas Adhikari

Thomas Kowtsch
title: Test Wafer Management and Automated Wafer Sorting
venue: 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
year: 2008

abstract: Wafer Level Reliability (WLR) programs have been active in many semiconductor companies since the mid 1980's. Test structures are designed to accelerate known reliability failure mechanisms (similar to ET structures for parametric testing) Large samples of these test structures are packaged and tested to determine reliability failure rates. These WLR programs typically focus on electromigration (EM) hot carrier, and TDDB testing of packaged parts. National Semiconductor has developed and implemented a WLR program which differs from the traditional approach. Wafer manufacturing personnel need to know which people, equipment, or process variables need to be better controlled to prevent reliability problems in the field. They also need faster feedback. Our WLR program looked at these issues and designed a more practical approach to eliminating fab related reliability problems. Wafers, not packaged parts, are tested in line and at the end of line (before sort test) to provide near real time feedback. We identified our top ten reliability failure mechanisms of concern based on past field failure rates and reliability monitors. WLR test structures and test methods were then designed to measure the effect of wafer fab process variability on reliability risk. Designed experiments were used extensively to correlate fab process monitors, WLR test results, and reliability test results.
author_names: S Garrard
title: Production implementation of a practical WLR program [wafer level reliability]
venue: Proceedings of 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC)
year: 1994

abstract: A semiconductor supply network involves many expensive steps, which have to be executed to serve global markets. The complexity of global capacity planning combined with the large capital expenditures to increase factory capacity makes it important to incorporate optimization methodologies for cost reduction and long term planning. The typical view of a semiconductor supply network consists of layers for wafer fab, sort, assembly, test and demand centers. We present a two stage stochastic integer programming formulation to model a semiconductor supply network. The model makes strategic capacity decisions, (i.e. build factories or outsource) while accounting for the uncertainties in demand for multiple products. We use the model not only to analyze how variability in demand affects the make/buy decisions but also to investigate how the correlation between demands of different products affects these strategic decisions. Finally, we demonstrate the value of incorporating demand uncertainty into a decision making scheme.
author_names: A P Rastogi

John W Fowler

W Matthew Carlyle

Ozgur M Araz

Arnold Maltz

Burak Buke
title: Supply network capacity planning for semiconductor manufacturing with uncertain demand and correlation in demand considerations
year: 2011

abstract: Integrated circuit manufacturing has major operations of fabrication, sort, assembly, and test. The dynamic behavior of these operations can be modeled in terms of a highly structured queueing network. A model is presented of the components and interactions of wafer movements, processing equipment, and process steps. The model considers multiple process flows, fab organization and layout, and equipment properties such as batch size, process time, failure, and repair distributions. The model is implemented as a discrete event simulation and has been used in a number of case studies concerning realistic factory situations. This simulation model is general and can be used to study many types of discrete manufacturing.
author_names: Judith E Dayhoff

Robert W Atherton
title: A Model for Wafer Fabrication Dynamics in Integrated Circuit Manufacturing
venue: IEEE Transactions on Systems, Man, and Cybernetics
year: 1987

abstract: Acknowledgments. 1. Running Start. About This Book. Some Words to Know. 2. Semiconductor Family Tree. Semiconductor Family Tree. Simple Analog Components. Advanced Analog Components. A/D and D/A Converters. MEMS. Medium Scale Digital Chips. Highly Integrated Digital Chips. 3. How Chips Are Designed. Old Style Design Process. New Style Design Process. Verifying the Design Works. Using Outside IP. Getting to Tape Out and Film. Current Problems and Future Trends. 4. How Chips Are Made. Clean Rooms and Fabs. Developing Technology: Chips and Photography. Silicon Ingots to Start. Polishing the Wafer Smooth. Building the Layer Cake. Laser Surgery: Etching Away the Transistors. Step and Repeat. Etching Bath. Ready for the Metal Round. Testing Phase. Bringing Out the Diamonds. Sorting the Fast from the Merely Good. Wrap It Up. How Many Nanometers in a Micron? Let's Get Small. 5. Business and Markets. Worldwide Production of Semiconductors. Worldwide Consumption of Semiconductors. Military Electronics. The Business of Making Semiconductors. 6. Essential Guide to Microprocessors. Overview of Microprocessors. Microprocessor History and Evolution. What's a Processor Architecture? Microprocessor Anatomy and Gazetteer. What Do 4 Bit, 8 Bit, 16 Bit, and 32 Bit Mean? Performance, Benchmarks, and Gigahertz. What Is Software? Choosing Microprocessors. Microprocessor Future Trends. 7. Essential Guide to Memory Chips. Overview of Memory Chips. Nonvolatile ROM. Volatile RAM. Memory Interfaces. Future Memories. 8. Essential Guide to Custom and Configurable Chips. Overview of Custom Chips. Field Programmable Chips. Custom ASIC Chips. Dynamically Reconfigurable Chips. Intellectual Property Licensing. Future Outlook for Custom Chips. 9. Theory. Digital and Binary Concepts. Gates and Logic Functions. How Transistors Work. About Electrons and Electronics. Appendix: Standard Bodies and Reference. Standards Bodies and Organizations. Conferences and Trade Shows. Other Resources. Glossary. Index.
author_names: James L Turley
title: The Essential Guide to Semiconductors
year: 2002