Query: mixed signal neurocompucting based on floating-gate memories

Candidate papers:

abstract: Author(s) Guo, Xinjie Advisor(s) Strukov, Dmitri Abstract: Nervous systems inspired neurocomputing has shown its great advantage in object detection, speech recognition and a lot of other machine learning technology driven applications from speed and power efficiency. Among handful neurocomputing implementation approaches, analog nanoelectronic circuits are very appealing because they may far overcome digital circuits of the same functionality in circuit density, speed and energy efficiency. Device density is one of the most essential metrics for designing large scale neural networks, allowing for high connectivity between neurons. Thanks to the high density nature of traditional memory applications, building artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memory devices would enable the high parallelism as well as achieve the performance advantages.Synapses, the most numerous elements of neural networks, are efficiently implemented by memory devices. This application, however, imposes a number of requirements, such as the continuous change of the memory resistance state, creating the need for novel engineering approaches. Here we report such engineering approaches for advancedcommercial 180 nm ESF1 and 55 nm ESF3 NOR flash memory, facilitating fabrication and successful test of high performance analog vector by matrix multiplication which is the key operation performed at signal propagation through any neuromorphic network. Furthermore, we discuss the recent progress toward neuromorphic computing implementations based on nonvolatile floating gate devices, in particular the experimental results for a prototype 28x28 binary input, 10 output, 3 layer neuromorphic network based on arrays of highly optimized embedded nonvolatile floating gate cells. The fabricated neuromorphic network's active components, including 101,780 floating gate cells, have a total area below 1 mm2. The network has shown a 94.7% classification fidelity on the common MNIST benchmark, close to the 96.2% obtained in simulation. The classification of one pattern takes sub 1 ms time and sub 20 nJ energy both numbers much better than for the best reported digital implementations of the same task. Estimates show that a straightforward optimization of the hardware, and its transfer to the already available 55 nm technology may increase this advantage to more than 100X in speed and 10000X in energy efficiency.As pure analog circuits cannot address the noise accumulation problem, a practical solution would also require inclusion of analog to digital and digital to analog stages for signal restoration. High energy efficient and compact data converters are therefore expected to play an important role in future computing platforms. We perform an experimental demonstration of 6 bit digital to analog (DAC) and 4 bit analog to digital conversion (ADC) operations implemented with a hybrid circuit consisting of Pt/TiO2 x /Pt resistive switching devices (also known as ReRAMs or memristors) and a CMOS operational amplifier (opamp) In particular, ADC is implemented with a Hopfield neural network circuit.
author_names: Xinjie Guo
title: Mixed Signal Neurocomputing Based on Floating gate Memories
year: 2017

abstract: Potential advantages of analog and mixed signal nanoelectronic circuits, based on floating gate devices with adjustable conductance, for neuromorphic computing had been realized long time ago. However, practical realizations of this approach suffered from using rudimentary floating gate cells of relatively large area. Here, we report a prototype <inline formula> <tex math notation="LaTeX"$28\times28$ /tex math>/inline formula> binary input, ten output, three layer neuromorphic network based on arrays of highly optimized embedded nonvolatile floating gate cells, redesigned from a commercial 180 nm nor flash memory. All active blocks of the circuit, including 101 780 floating gate cells, have a total area below 1 mm<sup>2</sup> The network has shown a 94.7% classification fidelity on the common Modified National Institute of Standards and Technology benchmark, close to the 96.2% obtained in simulation. The classification of one pattern takes a sub 1 <inline formula> <tex math notation="LaTeX"\mu \text{s} /tex math>/inline formula> time and a sub 20 nJ energy both numbers much better than in the best reported digital implementations of the same task. Estimates show that a straightforward optimization of the hardware and its transfer to the already available 55 nm technology may increase this advantage to more than <inline formula> <tex math notation="LaTeX"$10^{2}\times /tex math>/inline formula> in speed and <inline formula> <tex math notation="LaTeX"$10^{4}\times /tex math>/inline formula> in energy efficiency.
author_names: Farnood Merrikh-Bayat

Xinjie Guo

Michael Klachko

Mirko Prezioso

Konstantin K Likharev

Dmitri B Strukov
title: High Performance Mixed Signal Neurocomputing With Nanoscale Floating Gate Memory Cell Arrays
venue: IEEE Transactions on Neural Networks and Learning Systems
year: 2018

abstract: We have designed, fabricated, and successfully tested a prototype mixed signal, 28x28 binary input, 10 output, 3 layer neuromorphic network "MLP perceptron" It is based on embedded nonvolatile floating gate cell arrays redesigned from a commercial 180 nm NOR flash memory. The arrays allow precise ~1% individual tuning of all memory cells, having long term analog level retention and low noise. Each array performs a very fast and energy efficient analog vector by matrix multiplication, which is the bottleneck for signal propagation in most neuromorphic networks. All functional components of the prototype circuit, including 2 synaptic arrays with 101,780 floating gate synaptic cells, 74 analog neurons, and the peripheral circuitry for weight adjustment and I/O operations, have a total area below 1 mm^2. Its testing on the common MNIST benchmark set (at this stage, with a relatively low weight import precision) has shown a classification fidelity of 94.65% close to the 96.2% obtained in simulation. The classification of one pattern takes less than 1 us time and ~20 nJ energy both numbers much better than for digital implementations of the same task. Estimates show that this performance may be further improved using a better neuron design and a more advanced memory technology, leading to a >10^2 advantage in speed and a >10^4 advantage in energy efficiency over the state of the art purely digital (GPU and custom) circuits, at classification of large, complex patterns.
author_names: Farnood Merrikh-Bayat

Xinjie Guo

Michael Klachko

Mirko Prezioso

Konstantin K Likharev

Dmitri B Strukov
title: Sub 1 us, Sub 20 nJ Pattern Classification in a Mixed Signal Circuit Based on Embedded 180 nm Floating Gate Memory Cell Arrays
venue: ArXiv
year: 2016

abstract: We present the field programmable array of analog and digital devices (FPAADD) as a novel implementation of a field programmable mixed signal array (FPMA) The FPAADD is a hybrid combination of a field programmable analog array (FPAA) and a field programmable gate array (FPGA) Unlike other FPMAs where the FPGA and FPAA portions are kept separate, this architecture closely integrates the two in a fine grained interleaved array. Instead of using hard coded data converters, the FPAADD synthesizes data converters out of its reconfigurable fabric. The analog and digital portions share a common global interconnect. Floating gate (FG) transistors are used as the switch and memory elements of the chip, providing better switch performance and power over traditional static random access memory based approaches. The precise programmability of the FG switches also allows for computation to take place in the interconnect. These key differences make the FPAADD much more general purpose than previous FPMA architectures. The FPAADD consists of 27 x 8 array of 108 digital and 108 analog tiles and peripheral circuitry on 5 x 5 mm2 die fabricated in a 0.35 mm CMOS process, and contains more than 130 000 FG transistors.
author_names: Richard B Wunderlich

Farhan Adil

Paul E Hasler
title: Floating Gate Based Field Programmable Mixed Signal Array
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2013

abstract: The key operation in stochastic neural networks, which have become the state of the art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot product. While there have been many demonstrations of dot product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy efficient, and scalable stochastic dot product circuits based on either passively integrated metal oxide memristors or embedded floating gate memories. The circuit's high performance is due to mixed signal implementation, while the efficient stochastic operation is achieved by utilizing circuit's noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four node graph partitioning problem, and a Boltzmann machine with 10 input and 8 hidden neurons. Providing efficient and scalable specialized hardware for stochastic neural networks remains a challenge. Here, the authors propose a fast, energy efficient and scalable stochastic dot product circuit that may use either of two types of memory devices metal oxide memristors and floating gate memories.
author_names: M R Mahmoodi

Mirko Prezioso

Dmitri B Strukov
title: Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization
venue: Nature Communications
year: 2019

abstract: We have designed, fabricated, and tested a prototype mixed signal, 28x28 binary input, 10 ouput, 3 layer neuromorphic network based on embedded nonvolatile floating gate cell arrays redesigned from a commercial 180 nm NOR flash memory. Each array performs a very fast and energy efficient analog vector by matrix multiplication, which is the bottleneck for signal propagation in neuromorphic networks. All functional components of the prototype circuit, including 2 synaptic arrays with 101,780 floating gate synaptic cells, 74 analog neurons, and the peripheral circuitry for weight adjustment and I/O operations, have a total area below 1 mm2. Its testing on the MNIST benchmark set has shown a classification fidelity of 94.65% close to the 96.2% obtained in simulation. The classification of one pattern takes <1 ms time and ~20 nJ energy both numbers >103x better than those of the 28 nm IBM TrueNorth digital chip for the same task at a similar fidelity. Estimates show that this performance may be further improved using a better neuron design and a more advanced memory technology, leading to a >102x advantage in speed and a >104x advantage in energy efficiency over the state of the art purely digital circuits for classification of large, complex patterns. Experimental results for the chip to chip statistics, long term drift, and temperature sensitivity show no evident showstoppers on the way toward practical deep neuromorphic networks with unprecedented performance.
author_names: X Guo

F Merrikh Bayat

Mojtaba Bavandpour

Michael Klachko

M R Mahmoodi

Mirko Prezioso

Konstantin K Likharev

Dmitri B Strukov
title: Fast, energy efficient, robust, and reproducible mixed signal neuromorphic classifier based on embedded NOR flash memory technology
venue: 2017 IEEE International Electron Devices Meeting (IEDM)
year: 2017

abstract: This work presents a mixed signal physical compu tation electronics for monitoring three vital signs; namely heart rate, blood pressure, and blood oxygen saturation; from electrocardiography, arterial blood pressure, and photoplethysmography signals in real time. The computational circuits are implemented on a reconfigurable and programmable signal processing platform, namely field programmable analog array (FPAA) The design leverages the core enabling technology of FPAA, namely floating gate CMOS devices, and an on chip low power microcontroller to achieve energy efficiency while not compromising accuracy. The custom physical computation electronics operating in CMOS subthreshold region, performs low level (i.e. physiologically relevant feature extraction) and high level (i.e. detecting arrhythmia) signal processing in an energy efficient manner. The on chip microcontroller is used (1) in the programming mode for controlling the charge storage at the analog memory elements to introduce patient dependency into the system and (2) in the run mode to quantify the vital signs. The system has been validated against digital computation results from MATLAB using datasets collected from three healthy subjects and datasets from the MIT/BIH open source database. Based on all recordings in the MIT/BIH database, ECG R peak detection sensitivity is 94.2% The processor detects arrhythmia in three MIT/BIH recordings with an average sensitivity of 96.2% The cardiac processor achieves an average percentage mean error bounded by 3.75% 6.27% and 7.3% for R R duration, systolic blood pressure, and oxygen saturation level calculations; respectively. The power consumption of the ECG, blood pressure and photo plethysmography processing circuitry are 126 nW, 251 nW and 1.44 mW respectively in a 350 nm process. Overall, the cardiac processor consumes 1.82 mW.
author_names: Sahil S Shah

Hakan Toreyin

Cihan Berk Gungor

Jennifer Olson Hasler
title: A Real Time Vital Sign Monitoring in the Physical Domain on a Mixed Signal Reconfigurable Platform
venue: IEEE Transactions on Biomedical Circuits and Systems
year: 2019

abstract: We have built a 48 tap, mixed signal adaptive FIR filter with 8 bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed signal multipliers, and adapt the tap coefficients using pulse based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35 /spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6 mA differential output current.
author_names: Miguel Figueroa

Seth Bridges

David Hsu

Chris Diorio
title: A 19.2 GOPS mixed signal filter with floating gate adaptation
venue: IEEE Journal of Solid State Circuits
year: 2004

abstract: Recently, availability of big data and enormous processing power along with maturing of the applied algorithms, especially for deep learning, have led to a breakthrough in the performance of machine learning algorithms for various applications such as image classification, speech recognition, natural language processing, and so on. The rapidly growing range of machine learning applications, especially in IoT/mobile devices (smart phones, self driving cars, virtual reality gadgets, medical devices, etc. call for a specialized efficient neural processing platform. Of that, there is much more demand for fast, low precision neural inference accelerators than for higher precision systems for network training. Though custom designed digital accelerators significantly outperform their conventional counterparts, their performance is limited due to inherent separation of storage and computing elements and their large footprint. Analog domain in memory computing using nonvolatile memory (NVM) devices appears to be a promising bio inspired solution to break the performance barrier of today's neural accelerators. Small footprint of the storage cells, and their ability to operate as multiplier and accumulators enable compact, fast, and energy efficient implementation of vector by matrix multipliers (VMMs) as the core processing element in the neural accelerators. In this work, we develop several compact, energy efficient time domain VMM approaches based on various NVM devices such as 1T1R resistive cells, 2D NOR floating gate devices, and 3D NAND flash memories. In these approaches, the computation is solely performed via charge transfer while no static power is consumed in the peripheral circuitry. Moreover, the digital nature of the peripheral circuitry in these approaches significantly relaxes the technology node scaling limitation which is a serious challenge for analog domain computing circuits. One of the key advantages of our time domain approach is its full compatibility with complex and compact structure of the commercial 3D NAND memory block enabling the implementation of ultra compact mixed signal neural operators based on this NVM platform. In the second phase of this work, we propose "aCortex" an extremely energy efficient, fast, compact, and versatile neuromorphic processor architecture suitable for acceleration of a wide range of neural network inference models. The most important feature of our processor is a configurable mixed signal computing array of vector by matrix multiplier (VMM) blocks utilizing embedded NVM arrays for storing weight matrices. In this architecture, power hungry analog peripheral circuitry for data integration and conversion is shared among a very large array of VMM blocks enabling efficient instant analog/time domain VMM operation for different neural layer types with a wide range of layer specifications. This approach also maximizes the processor's area efficiency through sharing the area hungry high voltage programming switching circuitry as well as the analog peripheries among a large 2D array of NVM blocks. Such compact implementation further boosts the energy efficiency via lowering the digital data transfer cost. Other unique features of aCortex include configurable chain of buffers and data buses, a simple and efficient Instruction Set Architecture (ISA) and its corresponding multi agent controller, and a customized refresh free embedded DRAM memory. Using aCortex estimator, we perform rigorous system level analysis targeting various NVM devices (1T1R ReRAM, and 2D NOR/3D NAND flash) as well as different computing approaches (current/time mode) and propose a roadmap for the future efforts in this domain.
author_names: Mohammad Bavandpour
title: Toward Efficient Mixed Signal Neural Processors Using Non Volatile Memory Devices
year: 2020

abstract: Test of Integrated Circuits (ICs) is a topic that has been growing in importance in the last decades. Nowadays, about 50% of the total IC cost is related to test. In the past few years, the improvements of microelectronic technology gave the tool to include Analog and Digital structures sharing a unique IC substrate, in what went by the name of Mixed Signal (M S) ICs. The continuous variability of analogue signals and the lack of widely accepted fault models in this domain make analogue and M S Test more demanding and harder than Digital Testing. The analog part of an M S IC uses to take up little IC area but its test is still one of the challenges for microelectronic designers and researchers. On the other hand, Automatic Test Equipments (ATEs) require higher bandwidths than the circuit being tested and demand high speed sampling techniques. In addition, the signal processing is performed off line and requires extensive resources in Analog ATE time and memory, while been reduced the accessibility to some internal parts of the chip. Alternative solutions have been proposed to diminish the AATE cost. Usually the solution comes by moving the test procedure (total or partial) inside the chip. Build In Test (BIT) is a method that weaves most of these problems into a satisfying solution. In this thesis, a BIT approach is proposed, theoretically studied and validated with simulation and experimental results. The proposal is intended to detect parametric and structural faults in the Circuit Under Test (CUT) From the first electronic devices on, Lissajous curves have been used in electronics to test and tune filters and other resources. In this project, human eye has been substituted by an electronic element able to detect changes in the shape of the orthogonal composition of two electronic signals. The proposal is based on an X Y zoning Monitor that uses the CUT's input/Output signals in order to generate a Lissajous composition. The BIT output generates a digital signature which can be internally processed by other embedded structures of the M S circuit or be externally connected to a digital ATE. The thesis includes theoretical studies to model and look for the best configuration of the Analog X Y zoning Monitor. Based on this theory, a first experimental prototype based on programmable analog devices has been developed. Results showed the viability of the method. However, BIT also means minimum IC area, influence of the test on the CUT and other IC related aspects, which need silicon validation. Then, a full custom IC was designed, based on Floating Gate (FG) and Quasi Floating Gate (QFG) transistors, exhaustively simulated and fabricated in a standard CMOS process. Extensive experiments demonstrate that FG and QFG implementations worked as expected, according the extracted simulation results and offer a good compromise area performance. For the CUT&BIT demonstrator cells, Montecarlo simulations have been done to evaluate how process variations affect the CUT&BIT behavior and establish the possible escapes and yield losses. Experimental results, on samples after IC fabrication, show the viability of the integrated Monitor and the X Y zoning approach.
author_names: Ricard Sanahuja Moliner
title: On chip monitor for mixed signal testing based on x y zoning
year: 2006