Query: Modern Semiconductor Devices for Integrated Circuits sol

Candidate papers:

abstract: Most modern integrated circuits and semiconductor devices experience strong current loads. This leads to the creation of areas of local heating and high temperature gradients. High currents and thermal expansion promote the formation of point and line defects both in the bulk and on the surface of the semiconductor. Moreover, the long term current effects can result in breakaway and motion of line defects. This situation is accompanied by an acoustic emission (AE) the monitoring of which allows in situ investigation of the mechanical properties of materials and the study of the physical nature of durability and plasticity. Therefore, the purpose of this work is the construction and approbation of a firmware complex for the acoustic diagnostic of line defects in semiconductors.
author_names: A M Orlov

A A Scvortsov

A A Solov'ev

M P Astashin
title: Firmware complex for the acoustic diagnostic of line defects in semiconductors
venue: Proceedings of the 7th International Scientific and Practical Conference of Students, Post graduates and Young Scientists. Modern Techniques and Technology. MTT'2001 (Cat. No.01EX412)
year: 2001

abstract: 3. Electrons and holes are the major characters in the play and carry opposite charge. Their mass however is altered from the mass of an electron in vacuum. The altered mass is called e ective mass, mn and mp 4. The band model is the tool required for quantitative analysis of semiconductors. From this model one can get the energy gap, E K diagrams allowing the determination of e ective masses, analysis of the energy levels with in the gap and the conduction/valence bands etc
author_names: Chenming Calvin Hu
title: Modern Semiconductor Devices for Integrated Circuits
year: 2009

abstract: Recently, p type metal oxide semiconductors have attracted considerable interests for the applications in optoelectronic devices and low power complementary metal oxide semiconductor circuits. In this report, ternary p type CuAl<sub>x</sub>O<sub>y</sub> semiconductor thin films were fabricated by sol gel method and integrated as channel layers in thin film transistors (TFTs) The electrical performances of CuAl<sub>x</sub>O<sub>y</sub> TFTs, together with the characteristics of CuAl<sub>x</sub>O<sub>y</sub> thin films (e.g. crystalline phases, chemical compositions, surface morphology, and optical transmittances) were systematically studied at various annealing temperatures <inline formula> <tex math notation="LaTeX"{T}_{a} /tex math>/inline formula> The phase pure CuAlO<sub>2</sub> thin films were obtained at <inline formula> <tex math notation="LaTeX"{T}_{a} /tex math>/inline formula> above 800deg C in N<sub>2</sub> atmosphere. CuAlO<sub>2</sub> TFTs annealed at 900 deg C based on high k Al<sub>2</sub>O<sub>3</sub> exhibited optimized electrical performance, including a hole mobility of 1.36 cm<sub>2</sub>/Vs and on/off current ratio of <inline formula> <tex math notation="LaTeX"\sim 1 \times 10^\textsf {5} /tex math>/inline formula> This paper not only demonstrates the successful fabrication of high quality p type CuAlO<sub>2</sub> semiconductor thin film and electronic devices by sol gel process but also provides guidelines for related ternary p type oxide semiconductor material and device performance improvements.
author_names: Chunfeng Wang

Haotian Zhu

You Meng

Shengbin Nie

Yuna Zhao

Byoung Chul Shin

Elvira Fortunato

Rodrigo Martins

Fukai Shan

Guoxia Liu
title: Sol Gel Processed p Type CuAlO2 Semiconductor Thin Films and the Integration in Transistors
venue: IEEE Transactions on Electron Devices
year: 2019

abstract: Thermo mechanical stress accumulation in the power electronic integrated circuit (PIC) devices influences their lifetime and reliability. In order to determine both the temperature and the stress accumulation, numerical simulation is a very important tool in the design of PIC devices for quantifying and enhancing their lifetime and reliability. An open source solution integrated in Salome Meca and Code_Aster based on the finite element method (FEM) is used in this paper to analyze the thermo mechanical behavior on a simple metal semiconductor structure, which is typically found in a PIC. The computational time and accuracy of the simulations results is improved by finding the optimal mesh configuration. A convergence study is computed for five different cases by progressively reducing the size of the discretization elements (hence, increasing the number of mesh elements) in the area of interest. The results for an optimal relative error and computational time are compared with the results obtained using the commercial software Comsol. The simulated mechanical stress is compared with similar results reported in literature.
author_names: Adrian Bojita

Alexandru M Avram

Marius Purcar

Calin Munteanu

Vasile Topa
title: Thermo mechanical simulation of the metal semiconductor structures of power integrated circuits
venue: 2017 International Conference on Modern Power Systems (MPS)
year: 2017

abstract: The silicon Integrated circuits (ICs) continues to have an unprecedented impact on improving almost every aspect of modern society including communications, military, security, healthcare, energy saving, industrial automation, transport, and entertainment. Over the last four decades, the relentless pursuit of IC device miniaturization for manufacturing high performance and high density IC chips and system on a chip (SoC) led to the creation of Internet and social media. The semiconductor components are used in smart cars, smart homes, smart cities, smart health, smart energy, smart security, smart appliances, and so on. The Internet enables connecting any and every smart devices or "things" creating "Internet of Things" (IoT) or Internet of everything (IoE) And, the IoT connected smart devices constitute a smart environment and integrated ecosystem that can be accessed via personal computers, tablets, and smartphones from anywhere without human interaction. However, the performance of nanoscale MOSFETs in the design and manufacturing of "smart" electronic products necessary to create smart networks or "smart things" to enable smart environments and integrated ecosystems is inadequate due to the fundamental physical limitations such as short channel effects (SCEs) Shrinking conventional bulk MOSFET device dimensions in the decananometer regime degrades device performance including degradation in the subthreshold swing and decrease in device turn on voltage. As a result, the scaled MOSFETs cannot be turned off easily by lowering the gate voltage leading to excessive leakage current. Due to SCEs, the device characteristics become increasingly sensitive to process variation that imposes a serious challenge for continued scaling of bulk MOSFETs for the nanometer technology nodes. In addition, at gate length below 20 nm, the sub surface leakage paths are weakly controlled by the gate irrespective of gate oxide thickness and their potential barriers can be easily lowered by drain bias through the enhanced electric field coupling to the drain. Thus, to surmount the continuous scaling challenges of conventional bulk MOSFET devices new device technologies such as FinFET has emerged as the real alternative to MOSFETs. This tutorial provides the basic features and operating principles of FinFETs required for the understanding of design and manufacturing of advanced ICs at the nanometer nodes for smart electronic products. In addition, this tutorial also discusses the emerging undoped or lightly doped channel MOSFETs with performance comparable to FinFETs for design and manufacturing of smart IC products.
author_names: Samar K Saha
title: TUTORIAL 01: Advanced Silicon Devices for VLSI Circuits and Systems at Nanometer Nodes
venue: 2018 IEEE International Conference on Semiconductor Electronics (ICSE)
year: 2018

abstract: Materials and processes to create monolithic 111 V+CMOS circuits have been developed iteratively with inputs from potential market application needs and semiconductor industry infrastructure. The GaN LED and III V HEMT platforms are earliest to develop and driven by currently anticipated market needs. The developed process flow involves conventional 200mm CMOS front end processing in a CMOS foundry, merging the CMOS wafer with a III V/Si wafer, processing III V devices in a silicon fabrication environment, and final interconnection via returning the wafer to a CMOS foundry for back end interconnection. III V+CMOS silicon ICs are designed in a Cadence environment using foundry PDKs modified with insertion of the integrated III V device models. The overall method described above is invariant for the different III V's that are integrated into silicon ICs. Circuits have been designed using GaN LED+CMOS, GaN HEMT+CMOS, InGaAs HEMT+CMOS, and InGaP LED+CMOS platforms.
author_names: Eugene A Fitzgerald
title: Materials, Processes, and Markets for Monolithic III V Devices in Silicon Integrated Circuits
venue: 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)
year: 2018

abstract: The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state of the art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.This Review Article examines state of the art metrology methods for integrated circuits and highlights how new integrated circuit device design and industry requirements affect lithography options and consequently metrology requirements.
author_names: Ndubuisi G Orji

M Badaroglu

Bryan M Barnes

Carlos Beitia

Benjamin D Bunday

Umberto Celano

R Joseph Kline

Mark O Neisser

Yaw S Obeng

A E Vladar
title: Metrology for the next generation of semiconductor devices
venue: Nature electronics
year: 2018

abstract: Silicon avalanche light emitting devices (Si Av LEDs) offer various possibilities for realizing micro and even nano optical biosensors directly on chip. The light emitting devices (LEDs) operate in the wavelength range of about 450 850nm, and their optical power emitted is of the order of a few hundreds of nW/um2. These LEDs could be fabricated in micro and nano dimensions by using modern semiconductor fabrication processing technologies through the mainstream of silicon material. Through a series of experiments, the dispersion phenomena in the Si Av LED are observed. Also, its light emission point was proved to locate at about one micron just below the silicon silicon oxide interface. Subsequently, a micro fluidic channel sensor was designed by using the dispersion characteristics owned by the Si Av LED. The analytes flowing through a micro fluidic channel could be studied by their specific transmittance and absorption spectra. Moreover, simulations verify that a novel designed waveguide based sensor could be fabricated on chip between the Si optical source and the Si P I N detector.
author_names: Kaikai Xu

Yanxu Chen

T A Okhai

Lukas W Snyman
title: Micro optical sensors based on avalanching silicon light emitting devices monolithically integrated on chips
venue: Optical Materials Express
year: 2019

abstract: Metal semiconductor field effect transistors (MESFETs) have been fabricated using a 45 nm silicon on insulator CMOS technology available from Global Foundries. MESFETs with gate lengths of 200 nm show good manufacturability with well controlled run to run variations. The DC and RF performance of devices with different drain access lengths are compared to illustrate the design trades between high breakdown voltage and high frequency operation. Two applications of the MESFETs for RF integrated circuit design are presented. The first demonstrates integrated n channel MOSFET MESFET cascode amplifiers that combine the enhanced voltage operation of the MESFET with the high frequency capability of the scaled MOSFET. The resulting small signal amplifiers demonstrate cut off frequencies of 50 GHz when operated with supply voltages of 6 V, significantly higher than the nominal 1 V breakdown voltage of the CMOS transistors. The second application demonstrates a watt level MESFET power amplifier integrated with a CMOS current steering digital to analog converter (DAC) The MESFET serves as the RF output device, while the 4 bit CMOS DAC enables average power tracking. Both examples demonstrate the design flexibility enabled by the CMOS compatible MESFETs.
author_names: Payam Mehr

Soroush Moallemi

Xiong Zhang

William Lepkowski

Jennifer Kitchen

Trevor J Thornton
title: CMOS Compatible MESFETs for High Power RF Integrated Circuits
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2019

abstract: Silicon carbide (SiC) is an emerging wide bandgap semiconductor having superior physical properties such as high critical electric field and high saturated drift velocity. Discrete high voltage, low loss SiC power devices such as 600 1700 V Schottky barrier diodes and FETs (MOSFETs and JFETs) have currently been developed, and small scale production has started. SiC is also attractive for advanced integrated circuits operating in high temperature and radiation hard circumstances. This paper reviews the present status, future prospects, and technological challenges of SiC devices and circuits.
author_names: Tsunenobu Kimoto
title: Progress and future challenges of silicon carbide devices for integrated circuits
venue: Proceedings of the IEEE 2014 Custom Integrated Circuits Conference
year: 2014