Query: Heterogeneous Integration for High Frequency RF Applications

Candidate papers:

abstract: Heterogeneous integration (HI) has become a key technology development and production effort in the past few years. HI for RF has become an important task for applications such as 5G in the commercial world and for many higher frequency applications in space and defense. Several factors need to be considered to select a suitable approach, including active semiconductor technologies, performance, materials for interposers, the HI method and interface, cost, yield, and last but not least the overall reliability of the integration.
author_names: Augusto Gutierrez-Aitken
title: Heterogeneous Integration for High Frequency RF Applications
venue: 2020 IEEE International Electron Devices Meeting (IEDM)
year: 2020

abstract: We have demonstrated industry's first 300mm 3D heterogeneous integration of high performance, low leakage high K dielectric metal gate enhancement mode (e mode) GaN NMOS and Si PMOS transistors on 300mm high resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 300mm 3D layer transfer. The fabricated (bottom device layer) high K dielectric e mode GaN NMOS transistors, integrated on a 300mm HR Si(111) substrate, show excellent electrical characteristics and figure of merits (FOM) for realizing energy efficient, compact voltage regulators and RF front end components such as power amplifiers, low noise amplifiers and RF switches, with (i) IOFF as low as 100pA/mm (VD=5V, VG=0V) (ii) high ID,max=1.5mA/mm; (iii) RON as low as 610O mm, significantly better than industry standard Si transistors at equivalent drain breakdown (BVD) (iv) excellent RF performance: fT=190GHz, fMAX=300GHz, PAE=56% at mmwave frequency (f=28GHz) and PAE=70% at sub 7GHz (f=5GHz) significantly better than industry standard GaAs and Si RF transistors, (v) excellent RF switch FOM, RonCoff=110fs, and (vi) low noise figure, NFmin=1.36dB (f=28GHz) 0.4dB (f=5GHz) and 0.27dB (f=1.8GHz) all at SoC compatible voltages. The fabricated (top device layer) LG=65nm and 130nm Si PMOS transistors, which are monolithically integrated on top of the bottom GaN NMOS transistors by 300mm 3D layer transfer, show respectively, high drive current of 0.85mA/mm, and low Ioff of 150pA/mm at VD= 1.2V. Such a monolithic 3D integration of GaN NMOS and Si PMOS enables full integration of energy efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory functions and analog circuitries for next generation power delivery, RF (5G and beyond) and SoC applications.
author_names: Han Wui Then

C Y Huang

Brian Krist

Kimin Jun

Kevin L Lin

N Nidhi

T Michaelos

B Mueller

R Paul

J Peck

Willy Rachmady

Sansaptak Dasgupta

D Staines

T Talukdar

N Thomas

Tristan A Tronic

Paul Fischer

Walid M Hafez

Marko Radosavljevic

P Agababov

Ibrahim Ban

Robert L Bristol

Manish Chandhok

Siddharth Chouksey

Brandon Jay Holybee
title: 3D heterogeneous integration of high performance high K metal gate GaN NMOS and Si PMOS transistors on 300mm high resistivity Si substrate for energy efficient and compact power delivery, RF (5G and beyond) and SoC applications
venue: 2019 IEEE International Electron Devices Meeting (IEDM)
year: 2019

abstract: We demonstrate and review the unique fine pitch high aspect ratio tungsten filled through silicon vias (W TSVs) technology developed by Fraunhofer EMFT in high resitivity silicon substrates. The proposed process flow is fully compatible with both CMOS and MEMS technology, allowing 3D heterogeneous integration of highperformance, low power, compact tunable RF front ends. We have assessed the figures of merit of the technology for RF functionality by fabricating and characterizing different configurations for CPWs with TSV transitions, mm wave antennas and LC resonators as well as record high performance wideband out of plane micro inductors.
author_names: Montserrat Fernandez-Bolanos

Wolfgang A Vitale

Mariazel Maqueda Lopez

Adrian M Ionescu

Armin Klumpp

Karl-Reinhard Merkel

Josef Weber

Peter Ramm

Ilja Ocket

Walter De Raedt

Amin Enayati
title: 3D TSV based high frequency components for RF IC and RF MEMS applications
venue: 2016 IEEE International 3D Systems Integration Conference (3DIC)
year: 2016

abstract: The push to conquer the sparsely used electromagnetic spectrum between 100 and 1,000 GHz, commonly known as the millimeter wave (mmW) and sub mmW regions, is now in full force. The current rapid development of electronic circuits and subsystems beyond 100 GHz is enabled by improvements in high frequency semiconductor technology and packaging techniques. In this article, we highlight recent advances we have developed in heterogeneous semiconductor material chip integration for application toward the mmW frequency bands?in essence, a waferlevel integration approach that replaces chip to chip connections with monolithic integration.
author_names: Nils G Weimann

Maruf Hossain

Viktor Krozer

Wolfgang Heinrich

Marco Lisker

Andreas Mai

Bernd Tillack
title: Tight Focus Toward the Future: Tight Material Combination for Millimeter Wave RF Power Applications: InP HBT SiGe BiCMOS Heterogeneous Wafer Level Integration
venue: IEEE Microwave Magazine
year: 2017

abstract: In the last few years, radio frequency (RF) applications have driven the advanced electronics packaging market to encompass different sectors. With products such as Automotive Radar, High End Smartphones or WiGig devices, the RF packaging market is expected to grow in every sector. Wafer level packaging (WLP) 3D through silicon vias (TSVs) SiPs (Systems in Packages) and electromagnetic interference (EMI) shielding are key enablers for heterogeneous integration in segments where RF devices require small form factors, high speed operation and a high degree of isolation. Also, cost efficiency is critical. Based on images extracted from physical analyses of several RF devices, we will demonstrate the present power of RF packaging solutions for manufacturers such as Qualcomm, Broadcom, and Skyworks, from the manufacturing cost to the functional integration. We will extract some clues for future fifth generation (5G) and millimeter wave (mmWave) applications. We will also present how these companies manage to provide highly integrated SiPs featuring several advanced packaging technologies cost effectively. Finally, moving forward in 5G and mmWave applications, SiPs will get more complex to maintain high performance levels, with innovations like integrated EMI shielding and integrated passive devices. We will therefore introduce some key features, like advanced substrate technologies. These are also next generation technologies for 5G and mmWave systems.
author_names: Stephane Elisabeth
title: Advanced RF Packaging Technology Trends, from WLP and 3D Integration to 5G and Mmwave Applications
venue: 2019 International Wafer Level Packaging Conference (IWLPC)
year: 2019

abstract: Three dimensional system in package (3D SiP) based on silicon carriers or interposer is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through silicon via (TSV) The development of 3D SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to poor RF performance. In this paper, a coaxial TSV structure in silicon carrier is presented for high frequency applications. The coaxial TSV is able to suppress undesirable substrate loss as well as provide good impedance matching. Electrical modeling of coaxial TSV structure was carried out to obtain the required geometries for impedance matching. Three different types of test vehicles were fabricated; Cu plug TSV in both low ~10 Omega cm) and high resistivity ~4000 Omega cm) silicon substrate, and coaxial TSV in low resistivity silicon substrate. The S parameters of the via structure of the test vehicles were measured from 100 MHz to 10 GHz. The measured results show that the coaxial TSV structure is able to suppress silicon substrate loss and provide good RF performance compared to Cu plug TSV structure.
author_names: Soon Wee Ho

Seung Wook Yoon

Qiaoer Zhou

Kalpendu R Pasad

Vaidyanathan Kripesh

John H Lau
title: High RF performance TSV silicon carrier for high frequency application
venue: 2008 58th Electronic Components and Technology Conference
year: 2008

abstract: For radar applications, the W band frequency range (75 110 GHz) is a good candidate for high resolution distance measurement and remote detection of small or hidden objects in distances of 10 cm to 20 m. As electromagnetic waves in this frequency range can easily penetrate rough atmosphere like fog, smoke or dust, W band radars are perfectly suited for automotive, aviation, industrial and security applications. Additional benefit is that atmosphere has an absorption minimum at 94 GHz, so relative small output power is sufficient to achieve long range coverage. By combining and enhancing knowledge from the disciplines of heterogeneous integration technology and compound semiconductor technology, the Fraunhofer Institutes IAF, IPA and IZM developed a miniaturized and low cost 94 GHz radar module. Result of this approach is a highly miniaturized radar module built using a modular approach. The radar components are mounted on a dedicated RF NF hybrid PCB while the signal processing is done on a separate b.
author_names: K -F Becker

Leopold Georgi

Ruben Kahle

Steve Voges

F Brandenburger

Jan Hofer

Christian Ehrhardt

Christian Zech

Benjamin Baumann

Axel Huelsmann

A Grasenack

Steffen Reinold

Bernhard Kleiner

Tanja Braun

Martin Schneider-Ramelow

Klaus-D Lang
title: Heterogeneous integration of a miniaturized W band radar module
year: 2015

abstract: Applications using rf radios operating at frequencies above 1 GHz are proliferating. The highest operating frequencies continue to increase and applications above 10 GHz and up to 77 GHz are already emerging. Systems become more complex and devices need to operate at several different frequency bands using different wireless standards. The rf front end sections of these devices are characterized by a high diversity of components, in particular high precision passive components. In order to be produced cost effectively, these elements need to be integrated along with the semiconductor devices. This paper describes the requirements for successful integration of rf passive devices and proposes multilayer thin film technology as an effective rf integration technology.
author_names: Eric Beyne

Walter De Raedt

Geert Carchon

Philippe Soussan
title: Heterogeneous Integration of Passive Components for the Realization of RF System in Packages
year: 2008

abstract: System in package (SiP) based on silicon carriers is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through wafer interconnects. The development of SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to substrate crosstalk and poor RF performance. In this paper, a novel coaxial shielded via in silicon carrier is presented for high frequency applications. Electrical modeling was carried out to obtain the required geometries for optimum performance. The coaxial shield via is able to suppress undesirable substrate crosstalk between vertical interconnects as well as provide excellent RF performance. The detailed fabrication process is also presented. A negative tone SU 8 photoresist is used as the dielectric for the coaxial shield via structure. A test vehicle is fabricated on 8 inch, 10 Omegamiddotcm resistivity silicon wafer with a target of achieving a transmission coefficient, S21 of greater than 0.5 dB at 40 GHz. SU 8 dielectric of approximately 112 mum thickness was deposited on the via sidewall of a 300 mum diameter through wafer via holes, and the via holes filled with copper using bottom up electroplating approach to achieve a radius ratio, n of 4
author_names: Soon Wee Ho

Vempati Srinivasa Rao

Qratti Kalandar Navas Khan

Seung Uk Yoon

Vaidyanathan Kripesh
title: Development of coaxial shield via in silicon carrier for high frequency application
venue: 2006 8th Electronics Packaging Technology Conference
year: 2006

abstract: Integrated fan out wafer level packaging (InFO WLP) technology with state of the art inductors (quality factor of 42 and self resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO WLP promises superior form factor, pin count, and thermal performance to existing flip chip ball grid array (FC BGA) packages. In addition, InFO WLP's high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.
author_names: C C Liu

Shuo-Mao Chen

Feng-Wei Kuo

Huan-Neng Ron Chen

En-Hsiang Yeh

Cheng-chieh Hsieh

Li-Hsien Huang

M Y Chiu

John Yeh

Tsung-shu Lin

Tzu-Jin Yeh

S Y Hou

J P Hung

Jing-Cheng Lin

Chewnpu Jou

Chuei-Tang Wang

Shin-puu Jeng

D C H Yu
title: High performance integrated fan out wafer level packaging (InFO WLP) Technology and system integration
venue: 2012 International Electron Devices Meeting
year: 2012