Query: Reconfigurable and programmable System-On-Chip hardware platform for real-time ultrasonic testing applications

Candidate papers:

abstract: Present day ultrasonic signal processing applications such as medical imaging and non destructive testing has stringent requirements on low cost and portability to provide high quality diagnostics and characterization at real time pace. Advancements in the field of digital signal processing, embedded computing, and semiconductor technologies, have significantly assisted ultrasound researchers in the development of low cost, portable, and computationally efficient systems. In this study, a reconfigurable and programmable ultrasonic testing system (RPUTS) is designed and developed to effortlessly test and evaluate a wide variety of ultrasonic signal processing applications. RPUTS integrates a reconfigurable Analog Front End (AFE) which supports up to 8 transducers suitable for phased array implementations. The back end processing is provided by Xilinx Zynq System on Chip (SoC) which includes a powerful embedded ARM processor. Zynq SoC manages the overall system configuration as well as the execution of the signal processing algorithms. This study demonstrates the capabilities of RPUTS by realizing a complete ultrasonic testing system which acquires ultrasonic data and performs high speed 3D compression on the acquired data at real time rate.
author_names: Pramod Govindan

Boyang Wang

Pingping Wu

Ivan Palkov

Vidya Vasudevan

Jafar Saniie
title: Reconfigurable and programmable System On Chip hardware platform for real time ultrasonic testing applications
venue: 2015 IEEE International Ultrasonics Symposium (IUS)
year: 2015

abstract: Ultrasonic testing systems have been extensively used in medical imaging and non destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS) which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front End (AFE) which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased array implementation. Xilinx Zynq System on Chip (SoC) based Zedboard provides the back end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real time ultrasonic signal processing applications. This Linux based system is utilized for ultra sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.
author_names: Pramod Govindan

Vidya Vasudevan

Thomas Gonnot

Jafar Saniie
title: Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front End and Reconfigurable System on Chip Hardware
year: 2015

abstract: This study presents a scheme for enhancing the capabilities of an ultrasonic hardware platform leading to a fully reconfigurable system allowing for dynamic control over the analog front end. This system presents a robust approach for nondestructive testing, data analysis and imaging applications. The fully programmable analog front end system proposed in this paper supports up to 8 ultrasonic sensors. The components of this system are dynamically configurable by a Zynq system on chip (SoC) module for real time ultrasonic data acquisition and analysis. This reconfigurable system enables ultrasonic researchers to efficiently prototype different experiments and to incorporate high performance ultrasonic signal and image processing algorithms.
author_names: Vidya Vasudevan

Pramod Govindan

Jafar Saniie
title: Programmable analog front end system for ultrasonic SoC hardware
venue: IEEE International Conference on Electro/Information Technology
year: 2014

abstract: Ultrasonic signal processing applications require huge amounts of data to be processed. Further, high computational performance is essential to meet the real time requirements. Compression of the signal helps to reduce the data size and storage requirements as well as allow for rapid transmission of data to remote locations. High signal fidelity is significant in many of practical applications like ultrasound medical imaging and nondestructive testing. In this study, we discuss two methods for ultrasonic signal compression which offer high signal fidelity Discrete Wavelet Transform and signal decimation with the Nyquist rate limit. The compression algorithm is implemented on a reconfigurable system on chip platform using programmable hardware logic as well as in software using an embedded processor. The implementation details and the performance of the compression algorithms on both the hardware and software are analyzed in this paper.
author_names: Pramod Govindan

Thomas Gonnot

Spenser Gilliland

Jafar Saniie
title: 3D ultrasonic signal compression algorithms for high signal fidelity
venue: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)
year: 2013

abstract: Abstract. Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real time or near real time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field programmable gate arrays (FPGAs) are widely used. This paper proposes an FPGA based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq 7020 system on chip FPGA based on the Artix 7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high performance, low cost embedded systems, opening perspectives for onboard hyperspectral image processing.
author_names: Jose M P Nascimento

Mario Pereira Vestias
title: System on chip field programmable gate array design for onboard real time hyperspectral unmixing
year: 2016

abstract: The field of Internet of Things (IoT) and smart sensors has expanded rapidly in various fields of research and industrial applications. The area of IoT robotics has become a critical component in the evolution of Industry 4.0 standard. In this paper, we developed an IoT based reconfigurable System on Chip (SoC) robot that is fast and efficient for computer vision applications. It can be deployed in other IoT robotics applications and achieve its intended function. A Terasic Hexapod Spider Robot (TSR) was used with its DE0 Nano SoC board to implement our IoT robotics system. The TSR was designed to provide a competent computer vision application to recognize different shapes using a machine learning classifier. The data processing for image detection was divided into two parts, the first part involves hardware implementation on the SoC board and to provide real time interaction of the robot with the surrounding environment. The second part of implementation is based on the cloud processing technique, where further data analysis was performed. The image detection algorithm for the computer vision component was tested and successfully implemented to recognize shapes. The TSR moves or reacts based on the detected image. The Field Programmable Gate Array (FPGA) part is programmed to handle the movement of the robot and the Hard Processor System (HPS) handles the shape recognition, Wi Fi connectivity, and Bluetooth communication. This design is implemented, tested and can be used in real time applications in harsh environments where movements of other robots are restricted.
author_names: Naheel Faisal Kamal

Mazen Abdelfattah

Marouane Ferjani

Abbes Amira

Naveed Nawaz
title: An IoT Reconfigurable SoC Platform for Computer Vision Applications
venue: 2019 International Symposium on Systems Engineering (ISSE)
year: 2019

abstract: Ultrasonic industrial and medical imaging applications involve acquisition of large amount of volumetric data in real time. Therefore, data storage becomes critical in many current day applications which utilise ultrasound technology. Compressing the acquired data allows possessing minimal storage and also helps to rapidly transmit information to remote locations for expert analysis. The objective of this study is to design computationally efficient architectures for implementing discrete wavelet transform based ultrasonic three dimensional (3D) data compression algorithm on a reconfigurable ultrasonic system on chip (SoC) hardware platform. In this study, hardware and software architectures of the 3D ultrasonic compression algorithm are realised using Xilinx Zynq all programmable SoC. This study demonstrates that, compressing 33 MB of experimental ultrasonic 3D data into 0.42 MB (98.7% compression) requires only 84 ms for hardware architecture, and 1 min for software architecture, making both designs highly suitable for real time ultrasonic imaging applications. Furthermore, the 3D compression is implemented by using Open Computing Language (OpenCL) targeted on Nvidia GT 750M graphical processing unit. OpenCL implementation of ultrasonic 3D compression algorithm completes the execution in <1 sec. This approach provides improved computational performance as that of hardware architecture, and comparable flexibility as that of software implementation.
author_names: Pramod Govindan

Boyang Wang

Prashaanth Ravi

Jafar Saniie
title: Hardware and software architectures for computationally efficient three dimensional ultrasonic data compression
venue: IET Circuits Devices Syst.
year: 2016

abstract: Ultrasonic testing systems have been widely used in medical and industrial fields, demanding strict requirements for processing speed and re configurability of the hardware system. This paper presents a prototype of a reconfigurable, high performance, low cost and real time Ultrasonic Signal Acquisition and Processing (USAP) platform based on Zynq System on Chip (SoC) The USAP platform consists of five major components: Multi level voltage power supply; High voltage pulse generation; Ultrasonic signal acquisition; Sampling control unit and Digital signal processing module. The system uses Xilinx Zynq SoC as main processor and controller. It combines both ARM processor and field programmable gate array (FPGA) on the same chip, which makes the system capable of doing complex system configuration and performing high speed data processing. With this arrangement, the developed system is highly reconfigurable, where software and hardware configuration can be changed on both ARM and FPGA. This paper presents a system design flow of a complete ultrasonic testing system which is capable of acquiring ultrasonic data and performing advanced signal processing algorithms in real time.
author_names: Boyang Wang

Jafar Saniie
title: Ultrasonic Signal Acquisition and Processing platform based on Zynq SoC
venue: 2016 IEEE International Conference on Electro Information Technology (EIT)
year: 2016

abstract: Image Processing architecture and algorithms are used for the purpose of improving the image quality and to extract complete information in more precise manner. The need to process in real time has led to implement them on the target device with real time constraints like power and area. To implement image processing algorithms and architecture with the help of high level languages needs more blocks of code apart from inefficient in terms of time constraint. The easiest way to deal with facilitating usage of Xilinx System Generator/XSG blocks, XSG is a tool where we can build our design using pre existing block level components which are captured by using Xilinx block set from library environment and implement as per user requirement. The main responsibility of system generator is Xilinx block sets that provides the package integration with MATLAB Simulink and helps in co simulating FPGA hardware module. As per part application category, edge detection is a major essential application in medical field for proper diagnosis and correct treatments. Field Programmable Gate Arrays (FPGAs) have become more popular computing platforms as target device for digital signal processing. The Zynq System on Chip (SOC) is a dual processor platform with shared memory. This paper describes a fast architecture implementation of Sobel edge detection using the Zynq as a reconfigurable device. Our implementation is to merge both software and hardware using the Vivado and Zynq (SoC) As a result, our implementation is fast in terms of performance compare to the pre existing models. We make a comparison with other conventional edge detection techniques and show that the speed of operation of this design is much faster. This approach is tested over hardware or different gradient test vectors. Finally the algorithms are evaluated for the major essential images from the medical field to extract lasting effect in detecting the edges using gradient factor. The area and power factors are evaluated for reconfigurable hardware i.e, Zynq FPGA.
author_names: Chiranjeevi Gubbi Narasimhamurthy

Subhash Kulkarni
title: Fast Architecture for Low Level Vision and Image Enhancement for Reconfigurable Platform
venue: 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT)
year: 2021

abstract: Invited Keynote. The Rising Wave of Field Programmability. Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. Network Processors. A Dynamically Reconfigurable FPGA Based Content Addressable Memory for Internet Protocol Characterization. A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors. Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits. Internet Connected FPL. Prototyping. Field Programmable Communication Emulation and Optimization for Embedded System Design. FPGA Based Emulation: Industrial and Custom Prototyping Solutions. FPGA Based Prototyping for Product Definition. Implementation of Virtual Circuits by Means of the FIPSOC Devices. Dynamically Reconfigurable I. Static and Dynamic Reconfigurable Designs for a 2D Shape Adaptive DCT. A Self Reconfigurable Gate Array Architecture. Multitasking on FPGA Coprocessors. Design Visualisation for Dynamically Reconfigurable Systems. Verification of Dynamically Reconfigurable Logic. Miscellaneous I. Design of a Fault Tolerant FPGA. Real Time Face Detection on a Configurable Hardware System. Multifunctional Programmable Single Board CAN Monitoring Module. Self Testing of Linear Segments in User Programmed FPGAs. Implementing a Fieldbus Interface Using an FPGA. Technology Mapping and Routing Placement. Area Optimized Technology Mapping for Hybrid FPGAs. CoMGen: Direct Mapping of Arbitrary Components into LUT Based FPGAs. Efficient Embedding of Partitioned Circuits onto Multi FPGA Boards. A Placement Algorithm for FPGA Designs with Multiple I/O Standards. A Mapping Methodology for Code Trees onto LUT Based FPGAs. Biologically Inspired Methods. Possibilities and Limitations of Applying Evolvable Hardware to Real World Applications. A Co processor System with a Virtex FPGA for Evolutionary Computation. System Design with Genetic Algorithms. Implementing Kak Neural Networks on a Reconfigurable Computing Platform. Compact Spiking Neural Network Implementation in FPGA. Invited Keynote. Silicon Platforms for the Next Generation Wireless Systems What Role Does Reconfigurable Hardware Play? Invited Papers. From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains. A Specific Test Methodology for Symmetric SRAM Based FPGAs. Mobile Communication. DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications. Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re configurable Logic. Software Radio Reconfigurable Hardware System (SHaRe) Analysis of RNS FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. Dynamically Reconfigurable II. Partial Run Time Reconfiguration Using JRTR. A Combined Approach to High Level Synthesis for Dynamically Reconfigurable Systems. A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs. Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer. Design Space Exploration. Generation of Design Suggestions for Coarse Grain Reconfigurable Architectures. Mapping of DSP Algorithms on Field Programmable Function Arrays. On Availability of Bit Narrow Operations in General Purpose Applications. A Comparison of FPGA Implementations of Bit Level and Word Level Matrix Multipliers. A New Floorplanning Method for FPGA Architectural Research. Miscellaneous II. Efficient Self Reconfigurable Implementations Using On chip Memory. Design and Implementation of an XC6216 FPGA Model in Verilog. Reusable DSP Functions in FPGAs. A Parallel Pipelined SAT Solver for FPGA's. A Multi node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller. Applications I. A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. A CORDIC Arctangent FPGA Implementation for a High Speed 3D Camera System. Reconfigurable Computing for Speech Recognition: Preliminary Findings. Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic. The Fastest Multiplier on FPGAs with Redundant Binary Representation. Optimization. High Level Area and Performance Estimation of Hardware Building Blocks on FPGAs. Balancing Logic Utilization and Area Efficiency in FPGAs. Performance Penalty for Fault Tolerance in Roving STARs. Optimum Functional Decomposition for LUT Based FPGA Synthesis. Optimization of Run Time Reconfigurable Embedded Systems. Invited Keynote. It's FPL, Jim But Not as We Know It! Opportunities for the New Commercial Architectures. Invited Paper. Reconfigurable Systems: New Activities in Asia. StReAm: Object Oriented Programming of Stream Architectures Using PAM Blox. Architectures. Stream Computations Organized for Reconfigurable Execution (SCORE) Memory Access Schemes for Configurable Processors. Generating Addresses for Multi dimensional Array Access in FPGA On chip Memory. Combining Serialisation and Reconfiguration for FPGA Designs. Methodology and Technology. Multiple Wordlength Resource Binding. Automatic Temporal Floorplanning with Guaranteed Solution Feasibility. A Threshold Logic Based Reconfigurable Logic Element with a New Programming Technology. Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT Based FPGAs. Compilation and Related Issues. Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. Behavioural Language Compilation with Virtual Hardware Management. Synthesis and Implementation of RAM Based Finite State Machines in FPGAs. Applications II. Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware. Multiplexer Based Reconfiguration for Virtex Multipliers. Efficient Building of Word Recognizer in FPGAs for Term Document Matrices Construction. Short Papers. Reconfigurable Computing between Classifications and Metrics The Approach of Space/Time Scheduling. FPGA Implementation of a Prototype WDM On Line Scheduler. An FPGA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard Real Time Systems. Formal Verification of a Reconfigurable Microprocessor. The Role of the Embedded Memories in the Implementation of Artificial Neural Networks. Programmable System Level Integration Brings System on Chip Design to the Desktop. On Applying Software Development Best Practice to FPGAs in Safety Critical Systems. Pre route Assistant: A Routing Tool for Run Time Reconfiguration. High Speed Computation of Lattice Gas Automata with FPGA. An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers. Toward Uniform Approach to Design of Evolvable Hardware Based Systems. Educational Programmable Hardware Prototyping and Verification System. A Stream Processor Architecture Based on the Con.gurable CEPRA S. An Innovative Approach to Couple EDA Tools with Recon.gurable Hardware. FPL Curriculum at Tallinn Technical University. The Modular Architecture of SYNTHUP, FPGA Based PCI Board for Real Time Sound Synthesis and Digital Signal Processing. A Rapid Prototyping Environment for Microprocessor Based System on Chips and Its Application to the Development of a Network Processor. Configuration Prefetching for Non deterministic Event Driven Multi context Schedulers. Wireless Base Station Design Using a Reconfigurable Communications Processor. Placement of Linear Arrays.
author_names: Reiner W Hartenstein

Herbert Grunbacher
title: Field Programmable Logic and Applications: The Roadmap to Reconfigurable Computing
venue: Lecture Notes in Computer Science
year: 2002