Query: problems of single core

Candidate papers:

abstract: Abstract The further practical applications of halide perovskite quantum dots (QDs) are blocked by problems of instability and nonradiative Auger recombination manifested as photoluminescence blinking. Here, single core/shell structured perovskite semiconductor QDs are successfully fabricated by capping CsPbBr3 QD core with CdS shell. It is demonstrated that CsPbBr3/CdS core/shell QDs exhibit ultrahigh chemical stability and nonblinking photoluminescence with high quantum yield due to the reduced electronic traps within the core/shell structure. Efficiency of amplified spontaneous emission exhibits obvious enhancement compared to that of pure CsPbBr3 QDs, originating from the mitigated competition between stimulated emission and suppressed nonradiative biexciton Auger recombination. Furthermore, low threshold whispering gallery mode lasing with a high quality factor is achieved by incorporating CsPbBr3/CdS QDs into microtubule resonators. Density functional theory (DFT) based first principles calculations are also performed to reveal the atomic interface structure, which supports the existence of CsPbBr3/CdS structure. An interesting feature of spatially separated charge density at CsPbBr3/CdS interface is found, which may greatly contribute to the suppressed Auger recombination. The results provide a practical approach to improve the stability and suppress the blinking of halide perovskite QDs, which may pave the way for future applications for various optoelectronic devices.
author_names: Xiaosheng Tang

Jie Yang

Shiqi Li

Zhengzheng Liu

Zhiping Hu

Jiongyue Hao

Juan Du

Yuxin Leng

Haiyan Qin

Xing Lin

Yue Lin

Yuxi Tian

Miao Zhou

Qihua Xiong
title: Single Halide Perovskite/Semiconductor Core/Shell Quantum Dots with Ultrastability and Nonblinking Properties
venue: Advanced science
year: 2019

abstract: This paper shows a multicore sensor node can eliminate a task scheduler, and reduces power consumption and task execution delay, which are problems in an existing single core sensor node. To quantify the power consumption and the task execution delay, an experimental evaluation run various services on a wireless sensor node. The evaluation result shows that it is difficult to reduce power consumption and task execution delay at the same time because there is a trade off between them. Additionally, to validate feasibility of the multicore sensor node, the task flow analysis on software in wireless sensor networks is conducted. The analysis result shows that we can estimate a number of required cores to implement the software on a multicore sensor node. 1. ha zi me ni
author_names: Sotaro Ohara

Makoto Suzuki

Shunsuke Saruwatari

Masateru Minami

Hiroyuki Morikawa
title: Quantitative Evaluations of Problems in Single Core Wireless Sensor Nodes
year: 2009

abstract: Nowadays high performance computing (HPC) architectures are designed to resolve assorted sophisticated scientific as well as engineering problems across an ever intensifying number of HPC and professional workloads. Application and computation of key trigonometric functions sine and cosine are in all spheres of our daily life, yet fairly time consuming task in high performance numerical simulations. In this paper, we have delivered a detailed deliberation of how the micro architecture of single core Itanium(r) and Alpha 21264/21364 processors as well as the manual optimization techniques improve the computing performance of several mathematical functions. On describing the detailed algorithm and its execution pattern on the processor, we have confirmed that the processor micro architecture side by side manual optimization techniques ameliorate computing performance significantly as compared to not only the standard math library's built in functions with compiler optimizing options but also Intel(r) Itanium(r) library's highly optimized mathematical functions.
author_names: Md Haidar Sharif
title: High Performance Mathematical Functions for Single Core Architectures
venue: J. Circuits Syst. Comput.
year: 2014

abstract: Current microprocessors face constant thermal and power related problems during their everyday use, usually solved by applying a power budget to the processor/core. Dynamic voltage and frequency scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, the continuous increase of leakage power due to technology scaling along with low resolution of DVFS makes it less attractive as a technique to match a predefined power budget as technology goes to deep submicron. In this paper, we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We will predict the processor power dissipation at cycle level (power token throttling) or at a basic block level (basic block level mechanism) using the dissipated power translated into tokens to select between different power saving microarchitectural techniques. We also introduce a two level approach in which DVFS acts as a coarse grain technique to lower the average power dissipation towards the power budget, while microarchitectural techniques focus on removing the numerous power spikes. Experimental results show that the use of power saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed over the power budget, than only using DVFS to match a predefined power budget.
author_names: Juan M Cebrian

Daniel Sanchez

Juan L Aragon

Stefanos Kaxiras
title: Managing power constraints in a single core scenario through power tokens
venue: The Journal of Supercomputing
year: 2013

abstract: We give deterministic \tilde{O}(2^{2n} time \tilde{O}(2^n) space algorithms to solve all the most important computational problems on point lattices in NP, including the shortest vector problem (SVP) closest vector problem (CVP) and shortest independent vectors problem (SIVP) This improves the $n^{O(n) running time of the best previously known algorithms for CVP [R. Kannan, Math. Oper. Res. 12 (1987) pp. 415 440] and SIVP [D. Micciancio, Proceedings of the $19$th Annual ACM SIAM Symposium on Discrete Algorithms, 2008, pp. 84 93] and gives a deterministic and asymptotically faster alternative to the $2^{O(n) time (and space) randomized algorithm for SVP of Ajtai, Kumar, and Sivakumar [Proceedings of the $33$rd Annual ACM Symposium on Theory of Computing, 2001, pp. 266 275] The core of our algorithm is a new method to solve the closest vector problem with preprocessing (CVPP) that uses the Voronoi cell of the lattice (described as intersection of half spaces) as the result of the preproces.
author_names: Daniele Micciancio

Panagiotis Voulgaris
title: A Deterministic Single Exponential Time Algorithm for Most Lattice Problems Based on Voronoi Cell Computations
venue: SIAM J. Comput.
year: 2013

abstract: The relevance of the study is determined by the fact that now the problem of stable social economicdevelopment of single industry towns refers to one of the priorities of the state policy. Particularly critical thisproblem was showing in a financial crisis of 2008 2009. which indicated the interrelation of single industrytowns on the city forming enterprise's activity results. City forming enterprise's risks makes the typical risks ofsingle industry towns. Few core enterprises have funds to invest them in their own development and thesingle industry towns development, what determine necessity of budget funds applying in programs ofmono towns development.
author_names: Elena Mihajlovna Kryukova

Ekaterina A Vetrova

Aleksandr Maloletko

Olga V Kaurova

Svetlana V Dusenko
title: Social Economic Problems of Russian Mono Towns
year: 2014

abstract: With many of today's oil wells located offshore, the production of high volumes of water compared to oil poses major challenges to oil operators. The use of liquid liquid hydrocyclone (LLHC) is one effective way to arrest these uphill problems of produced water. However, the nature of fluid flow within the LLHC device is very vital to the separation process and performance. This study through numerical simulation lends understanding to the way oil water fluid migrates within LLHC device and shows how the flow structure can affect the efficiency of the separation process. Unsteady wavering flow was realized for the use of the single inlet due to flow imbalance just after entry into the cyclone. This affected the efficiency of separation as water droplets in the vicinity of the reverse flow core boundary could be carried to the overflow. In addition, there was the realization of frequent recirculation zones which cause some fluid droplets to be unseparated. Uniform unwavering fluid flow structure was observed in the case of dual inlet LLHC which assisted in the segregation of the oil and water into their respective core regions as oil rich core (inner) and water rich core (outer) The separation efficiency achieved from the use of the dual inlet LLHC outperformed that from the single inlet LLHC. An efficiency of 82.3% was obtained for the dual inlet LLHC as against 73.7% for the single inlet LLHC at 0.5 m3/h. At 1.0 m3/h, a great separation performance of 93.6% was achieved from the dual inlet LLHC, whereas separation efficiency of 88.5% was obtained when the same feed was treated in the single inlet LLHC.
author_names: Hussain H Al-Kayiem

Harrison Osei

Fakhruldin Bin Mohd Hashim

Jaseer E Hamza
title: Flow structures and their impact on single and dual inlets hydrocyclone performance for oil water separation
venue: Journal of Petroleum Exploration and Production Technology
year: 2019

abstract: In this paper, we revisit the design and implementation of Branch and Bound (B&B) algorithms for solving large combinatorial optimization problems on GPU enhanced multi core machines. B&B is a tree based optimization method that uses four operators (selection, branching, bounding and pruning) to build and explore a highly irregular tree representing the solution space. In our previous works, we have proposed a GPU accelerated approach in which only a single CPU core is used and only the bounding operator is performed on the GPU device. Here, we extend the approach (LL GB&B) in order to minimize the CPU GPU communication latency and thread divergence. Such an objective is achieved through a GPU based fine grained parallelization of the branching and pruning operators in addition to the bounding one. The second contribution consists in investigating the combination of a GPU with multi core processing. Two scenarios have been explored leading to two approaches: a concurrent (RLL GB&B) and a cooperative one (PLL GB&B) In the first one, the exploration process is performed concurrently by the GPU and the CPU cores. In the cooperative approach, the CPU cores prepare and off load to GPU pools of tree nodes using data streaming while the GPU performs the exploration. The different approaches have been extensively experimented on the Flowshop scheduling problem. Compared to a single CPU based execution, LL GB&B allows accelerations up to (x160) for large problem instances. Moreover, when combining multi core and GPU, we figure out that using RLL GB&B is not beneficial while PLL GB&B enables an improvement up to 36% compared to LL GB&B.
author_names: Imen Chakroun

Nouredine Melab

Mohand-Said Mezmaz

Daniel Tuyttens
title: Combining multi core and GPU computing for solving combinatorial optimization problems
venue: J. Parallel Distributed Comput.
year: 2013

abstract: Physarum polycephalum, a single celled, multinucleate slime mould, is a seemingly simple organism, yet it exhibits quasi intelligent behaviour during extension, foraging, and as it adapts to dynamic environments. For these reasons, Physarum is an attractive target for modelling with the underlying goal to uncover the physiological mechanisms behind the exhibited quasi intelligence and/or to devise novel algorithms for solving complex computational problems. The recent increase in modelling studies on Physarum has prompted us to review the latest developments in this field in the context of modelling and computing alike. Specifically, we cover models based on (i) morphology, (ii) taxis, and (iii) positive feedback dynamics found in top down and bottom up modelling techniques. We also survey the application of each of these core features of Physarum to solving difficult computational problems with real world applications. Finally, we highlight some open problems in the field and present directions for future research.
author_names: Chao Gao

Chen Liu

Daniel Thorsten Schenz

Xuelong Li

Zili Zhang

Marko Jusup

Zhen Wang

Madeleine Beekman

Toshiyuki Nakagaki
title: Does being multi headed make you better at solving problems? A survey of Physarum based models and computations.
venue: Physics of life reviews
year: 2018

abstract: We give deterministic ~O(22n+o(n) time algorithms to solve all the most important computational problems on point lattices in NP, including the Shortest Vector Problem (SVP) Closest Vector Problem (CVP) and Shortest Independent Vectors Problem (SIVP) This improves the nO(n) running time of the best previously known algorithms for CVP (Kannan, Math. Operation Research 12(3):415 440, 1987) and SIVP (Micciancio, Proc. of SODA, 2008) and gives a deterministic and asymptotically faster alternative to the 2O(n) time (and space) randomized algorithm for SVP of (Ajtai, Kumar and Sivakumar, STOC 2001) The core of our algorithm is a new method to solve the closest vector problem with preprocessing (CVPP) that uses the Voronoi cell of the lattice (described as intersection of half spaces) as the result of the preprocessing function. In the process, we also give algorithms for several other lattice problems, including computing the kissing number of a lattice, and computing the set of all Voronoi relevant vectors. All our algorithms are deterministic, and have 2O(n) time and space complexity.
author_names: Daniele Micciancio

Panagiotis Voulgaris
title: A deterministic single exponential time algorithm for most lattice problems based on voronoi cell computations
venue: STOC '10
year: 2010