Query: Development of Low-Cost Silicon BiCMOS Technology for RF Applications

Candidate papers:

abstract: It is well known that combining the benefits of bipolar and CMOS (Complementary Metal Oxide Semiconductor) devices in BiCMOS technology, one can achieve better speed and power density in microelectronic circuitry. In this work, we present the device design, process development and optimization of diffusion bipolar junction transistor (BJT) for the first time in India, for analog and RF applications. The baseline 180nm CMOS process of Semi Conductor Lab (SCL) at Chandigarh is used to develop the BiCMOS process. All the TCAD simulations are calibrated with the measured data of baseline BJT from 180nm CMOS process with two different process splits. Calibrated simulations of our proposed silicon BJT show current gain 90 and current driving capacity 10 mA. The breakdown voltage of the transistor is above 25 V (BVCB0) with cut off frequency (fT) and maximum oscillation frequency (fmax) more than 5 GHz and 3 GHz, respectively.
author_names: Suresh Balanethiram

S Pande

Ashutosh Kumar Singh

B Umapathi

H S Jatana

Nihar Ranjan Mohapatra

Anjan Chakravorty
title: Development of Low Cost Silicon BiCMOS Technology for RF Applications
venue: 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS AK India)
year: 2019

abstract: SiGe BiCMOS is reviewed with focus on today's production 0.18 /spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/ as well as lower power consumption, noise figure, and improved large signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz)
author_names: Marco Racanelli

Paul Kempf
title: SiGe BiCMOS technology for RF circuit applications
venue: IEEE Transactions on Electron Devices
year: 2005

abstract: The generation of RF/microwave power is required not only in wireless communications, but also in applications such as jamming, imaging, RF heating, and miniature dc/dc converters. Each application has its own unique requirements for frequency, bandwidth, load, power, efficiency, linearity, and cost. RF power is generated by a wide variety of techniques, implementations, and active devices. Power amplifiers are incorporated into transmitters in a similarly wide variety of architectures, including linear, Kalm, envelope tracking, outphasing, and Doherty. Linearity can be improved through techniques such as feedback, feedforward, and predistortion.
author_names: Frederick H Raab

Peter M Asbeck

Steve C Cripps

Peter B Kenington

Zoya Popovic

Nick Pothecary

John F Sevic

Nathan O Sokal
title: Power amplifiers and transmitters for RF and microwave
year: 2002

abstract: The construction and electrical characteristics of two port transformers (1:1 and 1:n turns ratio) and multi port transformer baluns fabricated in a production silicon technology are presented. A high linearity 5 GHz mixer design illustrates the advantages of the trifilar transformer in an RF IC application.
author_names: D T S Cheung

John R Long

Robert A Hadaway

David L Harame
title: Monolithic transformers for silicon RF IC design
venue: Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198)
year: 1998

abstract: Today more than ever, low cost, high performance RF devices are in high demand due to explosive growth in the wireless communications business. As the RF performance of silicon based technologies improve, silicon solutions are an obvious choice due to its low cost, high reliability and the ability to integrate other analog and logic functions on chip. This paper will highlight some of the development efforts that are taking place to improve silicon device technologies for RF and microwave applications. Performance of current state of the art silicon bipolar, MOSFET, TFSOI and SiGe HBTs will be discussed.<ETX>
author_names: Natalino Camilleri

David K Lovelace

J Costa

David Ngo
title: New development trends for silicon RF device technologies
venue: Proceedings of 1994 IEEE Microwave and Millimeter Wave Monolithic Circuits Symposium
year: 1994

abstract: A subharmonic transceiver for sensing and imaging applications in the 122 GHz ISM band has been proposed. The receiver consists of a single ended LNA, a push push VCO with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with fT/fmax of 255GHz/315GHz. Its differential down conversion gain is 31 dB at 122 GHz, and the corresponding noise figure is 11 dB. The 3 dB bandwidth reaches from 121 GHz to 124 GHz. The input 1 dB compression point is at 44 dBm. The receiver consumes 113 mA at a supply voltage of 3.2 V.
author_names: Klaus Schmalz

Wolfgang Winkler

Johannes Borngraber

Wojciech Debski

Bernd Heinemann

J Christoph Scheytt
title: 122 GHz ISM band transceiver concept and silicon ICs for low cost receiver in SiGe BiCMOS
venue: 2010 IEEE MTT S International Microwave Symposium
year: 2010

abstract: 1 Introduction. 2 SOI Materials. 2.1 Introduction. 2.2 Heteroepitaxial techniques. 2.2.1 Silicon on Sapphire (SOS) 2.2.2 Other heteroepitaxial SOI materials. 2.2.2.1 Silicon on Zirconia (SOZ) 2.2.2.2 Silicon on Spinel. 2.2.2.3 Silicon on Calcium Fluoride. 2.3 Dielectric Isolation (DI) 2.4 Polysilicon melting and recrystallization. 2.4.1 Laser recrystallization. 2.4.2 E beam recrystallization. 2.4.3 Zone melting recrystallization. 2.5 Homoepitaxial techniques. 2.5.1 Epitaxial lateral overgrowth. 2.5.2 Lateral solid phase epitaxy. 2.6 FIPOS. 2.7 Ion beam synthesis of a buried insulator. 2.7.1 Separation by implanted oxygen (SIMOX) 2.7.1.1 "Standard"SIMOX. 2.7.1.2 Low dose SIMOX. 2.7.1.3 ITOX. 2.7.1.4 SMOXMLD. 2.7.1.5 Related techniques. 2.7.1.6 Material quality. 2.7.2 Separation by implanted nitrogen (SIMNI) 2.7.3 Separation by implanted oxygen and nitrogen (SIMON) 2.7.4 Separation by implanted Carbon. 2.8 Wafer Bonding and Etch Back (BESOI) 2.8.1 Hydrophilic wafer bonding. 2.8.2 Etch back. 2.9 Layer transfer techniques. 2.9.1 Smart Cut(R) 2.9.1.1 Hydrogen rare gas implantation. 2.9.1.2 Bonding to a stiffener. 2.9.1.3 Annealing. 2.9.1.4 Splitting. 2.9.1.5 Further developments. 2.9.2 Eltran(R) 2.9.2.1 Porous silicon formation. 2.9.2.2 The original Eltran(R) process. 2.9.2.3 Second generation Eltran(R) process. 2.9.3 Transferred layer material quality. 2.10 Strained silicon on insulator (SSOI) 2.11 Silicon on diamond. 2.12 Silicon on nothing (SON) 3 SOI Materials Characterization. 3.1 Introduction. 3.2 Film thickness measurement. 3.2.1 Spectroscopic reflectometry. 3.2.2 Spectroscopic ellipsometry. 3.2.3 Electrical thickness measurement. 3.3 Crystal quality. 3.3.1 Crystal orientation. 3.3.2 Degree of crystallinity. 3.3.3 Defects in the silicon film. 3.3.3.1 Most common defects. 3.3.3.2 Chemical decoration of defects. 3.3.3.3 Detection of defects by light scattering. 3.3.3.4 Other defect assessment techniques. 3.3.3.5 Stress in the silicon film. 3.3.4 Defects in the buried oxide. 3.3.5 Bond quality and bonding energy. 3.4 Carrier lifetime. 3.4.1 Surface Photovoltage. 3.4.2 Photoluminescence. 3.4.3 Measurements on MOS transistors. 3.4.3.1 Accumulation mode transistor. 3.4.3.2 Inversion mode transistor. 3.4.3.3 Bipolar effect. 3.5 Silicon/Insulator interfaces. 3.5.1 Capacitance measurements. 3.5.2 Charge pumping. 3.5.3 MOSFET. 4 SOI CMOS Technology. 4.1 SOI CMOS processing. 4.1.1 Fabrication yield and fabrication cost. 4.2 Field isolation. 4.2.1 LOCOS. 4.2.2 Mesa isolation. 4.2.3 Shallow trench isolation. 4.2.4 Narrow channel effects. 4.3 Channel doping profile. 4.4 Source and drain engineering. 4.4.1 Silicide source and drain. 4.4.2 Elevated source and drain. 4.4.3 Tungsten clad. 4.4.4 Schottky source and drain. 4.5 Gate stack. 4.5.1 Gate material. 4.5.2 Gate dielectric. 4.5.3 Gate etch. 4.6 SOI MOSFET layout. 4.6.1 Body contact. 4.7 SOI bulk CMOS design comparison. 4.8 ESD protection. 5 The SOI MOSFET. 5.1 Capacitances. 5.1.1 Source and drain capacitance. 5.1.2 Gate capacitance. 5.2 Fully and partially depleted devices. 5.3 Threshold voltage. 5.3.1 Body effect. 5.3.2 Short channel effects. 5.4 Current voltage characteristics. 5.4.1 Lim Fossum model. 5.4.2 C? continuous model. 5.5 Transconductance. 5.5.1 gm/ID ratio. 5.5.2 Mobility. 5.6 Basic parameter extraction. 5.6.1 Threshold voltage and mobility. 5.6.2 Source and drain resistance. 5.7 Subthreshold slope. 5.8 Ultra thin SOI MOSFETs. 5.8.1 Threshold voltage. 5.8.2 Mobility. 5.9 Impact ionization and high field effects. 5.9.1 Kink effect. 5.9.2 Hot carrier degradation. 5.10 Floating body and parasitic BJT effects. 5.10.1 Anomalous subthreshold slope. 5.10.2 Reduced drain breakdown voltage. 5.10.3 Other floating body effects. 5.11 Self heating. 5.12 Accumulation mode MOSFET. 5.12.1 I V characteristics. 5.12.2 Subthreshold slope. 5.13 Unified body effect representation. 5.14 RF MOSFETs. 5.15 CAD models for SOI MOSFETs. 6 Other SOI Devices. 6.1 Multiple gate SOI MOSFETs. 6.1.1 Multiple gate SOI MOSFET structures. 6.1.1.1 Double gate SOI MOSFETs. 6.1.1.2 Triple gate SOI MOSFETs. 6.1.1.3 Surrounding gate SOI MOSFETs. 6.1.1.4 Triple plus gate SOI MOSFETs. 6.1.2 Device characteristics. 6.1.2.1 Current drive. 6.1.2.2 Short channel effects. 6.1.2.3 Threshold voltage. 6.1.2.4 Volume inversion. 6.1.2.5 Mobility. 6.2 MTCMOS/DTMOS. 6.3 High voltage devices. 6.3.1 VDMOS and LDMOS. 6.3.2 Other high voltage devices. 6.4 Junction Field Effect Transistor. 6.5 Lubistor. 6.6 Bipolar junction transistors. 6.7 Photodiodes. 6.8 G4 FET. 6.9 Quantum effect devices. 7 The SOI MOSFET in a Harsh Environment. 7.1 Ionizing radiations. 7.1.1 Single event phenomena. 7.1.2 Total dose effects. 7.1.3 Dose rate effects. 7.2 High temperature operation. 7.2.1 Leakage current. 7.2.2 Threshold voltage. 7.2.3 Output conductance. 7.2.4 Subthreshold slope. 8 SOI Circuits. 8.1 Introduction. 8.2 Mainstream CMOS applications. 8.2.1 Digital circuits. 8.2.2 Low voltage, low power digital circuits. 8.2.3 Memory circuits. 8.2.3.1 Non volatile memory devices. 8.2.3.2 Capacitorless DRAM. 8.2.4 Analog circuits. 8.2.5 Mixed mode circuits. 8.3 Niche applications. 8.3.1 High temperature circuits. 8.3.2 Radiation hardened circuits. 8.3.3 Smart power circuits. 8.4 Three dimensional integration.
author_names: J P Colinge
title: Silicon on Insulator Technology: Materials to VLSI
year: 1991

abstract: Electrostatic discharge (ESD) continues to be a semiconductor quality and reliability area of interest as semiconductor components are reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, ESD robustness will continue to be a technology concern. With the transition from silicon bipolar junction transistor to modern BiCMOS silicon germanium (SiGe) semiconductor technologies, new semiconductor process and integration issues have evolved which influence both device performance and ESD protection. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of on chip ESD protection and design. With the growth of interest of ESD in RF technology, new innovations and inventions are occurring at a rapid pace. In this paper, we will provide an introductory review of silicon germanium technology and ESD.
author_names: Steven H Voldman
title: A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I ESD
venue: Microelectron. Reliab.
year: 2005

abstract: The low resistivity substrate that is used in bulk silicon processes (CMOS and BiCMOS) limits the integration of high quality passives components and gives rise to severe substrate coupling issues. This paper shows how to take advantage of HR SOI to improve RF circuit performances as well as the effectiveness of HR SOI to reduce substrate coupling. Potentiality of mm wave passive integration is also shown.
author_names: Carlo Tinella

Frederic Gianesello

Daniel Gloria

Christine Raynaud

P Delatte

A Engelstein

J M Fournier

Philippe Benech

Jalal Jomaah
title: Partially depleted CMOS SOI technology for low power RF applications
venue: European Gallium Arsenide and Other Semiconductor Application Symposium, GAAS 2005
year: 2005

abstract: A detail fabricating process and characterization of thin film microstrip line (TFML) on low K polyimide, used for interconnects in radio frequency integrated circuits (RFICs) technology, is reported in this study. By incorporating a spin on dielectric polyimide and sputtering of aluminum, the TFML is fabricated on low cost low resistivity silicon (LRS) substrate @r=[email protected] The TFML with a thickness of [email protected] polyimide dielectric layer presents attenuation losses of 0.385dB/mm at 25GHz and 0.438dB/mm at 50GHz. Effective dielectric constant and attenuation of TFML on polyimide are carefully investigated and discussed.
author_names: Hung-Wei Wu

Yan Kuin Su

Ru-Yuan Yang

Min-Hang Weng

Yu-Der Lin
title: Fabrication of low loss thin film microstrip line on low resistivity silicon for RF applications
venue: Microelectron. J.
year: 2007