Query: ESD: Circuits and Devices

Candidate papers:

abstract: About the Author. Preface. Acknowledgments. Chapter 1: Electrostatic Discharge. 1.1 Electricity and Electrostatics Discharge. 1.2 Fundamental Concepts of ESD Design. 1.3 Time Constants. 1.4 Capacitance, Resistance and Inductance and ESD. 1.5 Rules of Thumb and ESD. 1.6 Lumped versus Distributed Analysis and ESD. 1.7 ESD Metrics and Figures of Merit. 1.8 Twelve Steps to Building an ESD Strategy. 1.9 Summary and Closing Comments. Problems. References. Chapter 2: Design Synthesis. 2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection. 2.2 Electrical and Spatial Connectivity. 2.3 ESD, Latchup, and Noise. 2.4 Interface Circuits and ESD Elements. 2.5 ESD Power Clamps Networks. 2.6 ESD Rail to Rail Devices. 2.7 Guard Rings. 2.8 Pads, Floating Pads, and No Connect Pads. 2.9 Structures Under Bond Pads. 2.10 Summary and Closing Comments. Problems. References. Chapter 3: Electrostatic Discharge (ESD) Design: MOSFET Design. 3.1 Basic ESD Design Concepts. 3.2 ESD MOSFET Design: Channel Width. 3.3 ESD MOSFET Design: Contact. 3.4 ESD MOSFET Design: Metal Distribution. 3.5 ESD MOSFET Design: Silicide Masking. 3.6 ESD MOSFET Design: Series Cascode Configurations. 3.7 ESD MOSFET Design: Multi Finger Design Integration of Coupling and Ballasting Techniques. 3.8 ESD MOSFET Design: Enclosed Drain Design Practice. 3.9 ESD MOSFET Interconnect Ballasting Design. 3.10 ESD MOSFET Design: Source and Drain Segmentation. 3.11 Summary and Closing Comments. Problems. References. Chapter 4: Electrostatic Discharge (ESD) Design: Diode Design. 4.1 ESD Diode Design: ESD Basic. 4.2 ESD Diode Design: Anode. 4.3 ESD Diode Design: Interconnect Wiring. 4.4 ESD Diode Design: Polysilicon Bound Diode Designs. 4.5 ESD Diode Design: n Well Diode Design. 4.6 ESD Diode Design: np/p Substrate Diode Design. 4.7 ESD Diode Design: Diode String. 4.8 ESD Diode Design: Triple Well Diodes. 4.9 ESD Design: BiCMOS ESD Design. 4.10 Summary and Closing Comments. Problems. References. Chapter 5: Silicon on Insulator (SOI) ESD Design. 5.1 SOI ESD Basic Concepts. 5.2 SOI ESD Design: MOSFET with Body Contact (T Shaped Layout) 5.3 SOI ESD Design: SOI Lateral Diode Structure. 5.4 SOI ESD Design: Buried Resistors (BR) Elements. 5.5 SOI ESD Design: SOI Dynamic Threshold MOSFET (DTMOS) 5.6 SOI ESD Design: Dual Gate (DG) MOSFETs. 5.7 SOI ESD Design: FinFET Structure. 5.8 SOI ESD Design: Structures in the Bulk Substrate. 5.9 SOI ESD Design: SOI To Bulk Contact Structures. 5.10 Summary and Closing Comments. Problems. References. Chapter 6: Off Chip Drivers (OCD) and ESD. 6.1 Off Chip Drivers (OCD) 6.2 Off Chip Drivers: Mixed Voltage Interface. 6.3 Off Chip Drivers Self Bias Well OCD Networks. 6.4 Off Chip Drivers: Programmable Impedance (PIMP) OCD Networks. 6.5 Off Chip Drivers: Universal OCDs. 6.6 Off Chip Drivers: Gate Array OCD Design. 6.7 Off Chip Drivers: Gate Modulated Networks. 6.8 Off Chip Driver ESD Design: Integration of Coupling and Ballasting Techniques. 6.9 Off Chip Driver ESD Design: Substrate Modulated Resistor Ballasted MOSFET. 6.10 Summary and Closing Comments. Problems. References. Chapter 7: Receiver Circuits and ESD. 7.1 Receivers and ESD. 7.2 Receivers and ESD. 7.3 Receivers and Receiver Evolution. 7.4 Receiver Circuits with Pseudo Zero VT Half Pass Transmission Gates. 7.5 Receiver Circuits with Zero Transmission Gate. 7.6 Receiver Circuits with Bleed Transistors. 7.7 Receiver Circuits with Test Functions. 7.8 Receiver With Schmitt Trigger Feedback Networks. 7.9 Bipolar Transistor Receivers. 7.10 Summary and Closing Comments. Problems. References. Chapter 8: SOI ESD Circuits and Design Integration. 8.1 SOI ESD Design Integration. 8.2 SOI ESD Design: Diode Design. 8.3 SOI ESD Diode Design: Mixed Voltage Interface (MVI) Environments. 8.4 SOI ESD Networks in SOI CPU with Aluminum (Al) Interconnects. 8.5 SOI ESD Design in Copper (Cu) Interconnects. 8.6 SOI ESD Design with Gate Circuitry. 8.7 SOI and Dynamic Threshold ESD Networks. 8.8 SOI Technology and Miscellaneous ESD Issues 8.9 Summary and Closing Comments. Problems. References. Chapter 9: ESD Power Clamps. 9.1 ESD Power Clamp Design Practices. 9.2 ESD Power Clamps: Diode Based. 9.3 ESD Power Clamps: MOSFET Based. 9.4 ESD Power Clamps: Bipolar Based. 9.5 ESD Power Clamps: Silicon Controlled Rectifier Based. 9.6 Summary and Closing Comments. Problems. References. Index.
author_names: Steven H Voldman
title: ESD: Circuits and Devices
year: 2005

abstract: This work describes an ESD empirical simulation flow for circuits containing snapback based devices. Regular ESD transistors SPICE models were combined with empirical models, based on TLP measurements. Behavioral language VerilogA code has been used to add measured characteristics of the transistor at triggering voltage dependent on simulated gate voltage.
author_names: Efraim Aharoni

Avi Parvin

Yosi Vaserman

Evan Grund
title: Empirical ESD simulation flow for ESD protection circuits based on snapback devices
venue: 2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)
year: 2016

abstract: Since large array devices of MOSFETs are huge for driving capabilities, ESD self protections are also required. Then, the large drain contact to poly gate spacing layout rule is usually adopted with large layout areas. In this paper, a new control circuit is implemented for adopting the minimum device layout rule in the LAD. Hence, it results in a very small layout area and ESD self protection capabilities can be established.
author_names: Hung-Wei Chen

Shao-Chang Huang

Mi-Chang Chang

Jen-Hang Yang

Tingyou Lin
title: ESD protection and driving capability switch control circuits for large array NMOSFET driving devices
venue: 2017 International Conference on Electron Devices and Solid State Circuits (EDSSC)
year: 2017

abstract: This paper presents a detailed study of turn on uniformity under electrostatic discharge events in single finger and multi finger traditional DDSCR devices. Since the structure of the multi finger DDSCR device is not completely symmetrical, the electric field strength of each finger breakdown junction is different, resulting in different impact ionization rates. Therefore, each finger of device cannot be turned on at the same time, and the turned on finger enters the snap back region and pull down the voltage of the device. If the ESD failure voltage Vt2 of the multi finger device is less than the trigger voltage Vt1, then other fingers will not turn on until the device fails, and the ESD current can be only discharged through the partial area. The transmission line pulse (TLP) test results show that the failure currents It2 of the single finger, 2 finger and 4 finger DDSCR devices are 6.22A, 11.83A and 13.33A, respectively, and the 4 finger device cannot be uniformly turned on.
author_names: Dandan Jia

Xijun Chen

Xiangliang Jin
title: Analysis of Turn on Uniformity of Multi finger DDSCR Devices under ESD Stress
venue: 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)
year: 2019

abstract: Abstract A novel cascaded complementary dual directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5 mm 20 V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4 V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64 mA/mm 2 The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance trigger effect is finally confirmed by Sentaurus simulations.
author_names: Hailian Liang

Weidong Nie

Xiaofeng Gu

Shurong Dong

Wai Shing Lau
title: An investigation on capacitance trigger ESD protection devices for high voltage integrated circuits
venue: Microelectron. Reliab.
year: 2014

abstract: A CMOS SCR compact model is developed for circuit simulation of ESD protection circuits. The model is comprised of coupled NPN and PNP transistors. A previously unnoted interaction between these transistors is described, resulting in improved agreement between simulation and measurement. This model addresses fundamental limitations of previous models, allowing for improved simulation accuracy, while limiting the number of parameters. The model parameters are scalable with respect to the layout spacings.
author_names: Robert Mertens

Elyse Rosenbaum
title: A physics based compact model for SCR devices used in ESD protection circuits
venue: 2013 IEEE International Reliability Physics Symposium (IRPS)
year: 2013

abstract: Through Silicon Via (TSV) has been utilized in vertically stacking IC dice to implement real system in chip applications. However, threshold voltage and mobility of MOSFETs can be influenced by induced mechanical strain of the TSV, causing degradation or non stability of functional circuits. Therefore, a Keep out Zone (KOZ) is defined, meaning that active devices are forbidden in this area. This paper investigates the impact on ESD protection devices placed inside this KOZ in bulk FinFET process.
author_names: Shih-Hung Chen

Steven Thijs

Dimitri Linten

Mirko Scholz

Geert Hellings

Guido Groeseneken
title: ESD protection devices placed inside keep out zone (KOZ) of through Silicon Via (TSV) in 3D stacked integrated circuits
venue: Electrical Overstress Electrostatic Discharge Symposium Proceedings 2012
year: 2012

abstract: Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system on chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high speed operation cause the ICs more sensitive to charged device model (CDM) ESD events, especially under cross domain stresses. The traditional cross domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal oxide semiconductor (MOS) structure against cross domain CDM ESD stresses was proposed in this work and verified in 0.18 \mu \text{m} CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking MOS protection designs was also investigated in detail.
author_names: Cheng-Yun Hsueh

Ming-Dou Ker
title: Stacking MOS Protection Design for Interface Circuits Against Cross Domain CDM ESD Stresses
venue: IEEE Transactions on Electron Devices
year: 2021

abstract: In this paper, the total ionizing dose effects on electrostatic discharge (ESD) protection devices are investigated. Irradiation is conducted with 1.5 MeV He+ from a RPEA 4.0 MV Dynamitron accelerator, and the Barth 4002 transmission line pulse (TLP) tester is used for measurements. The ESD devices considered are a P+/NW diode, a Zener diode, gate grounded NMOS (GGNMOS) and lateral silicon controlled rectifiers (LSCR) fabricated in a 0.35 um BCD (Bipolar CMOS DMOS) technology. The pre and post irradiated TLP I V characteristics are analyzed and compared in detail. Significant degradation in ESD protection is observed after exposure of devices to ionizing irradiation.
author_names: Wei Liang

Kostas Alexandrou

Maxim Klebanov

Chung-Chen Kuo

Ioannis Kymissis

Kalpathy B Sundaram

Juin J Liou
title: Characterization of ESD protection devices under total ionizing dose irradiation
venue: 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
year: 2017

abstract: Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a wafer level characterization method is proposed in this work. By separating the detection rail from the supply rail, triggering actions resulted from detection circuits can be clearly captured by the proposed method. Besides, both the component level triggering criteria and system level transient induced latch up (TLU) immunity of ESD protection circuits can be fully characterized by the proposed method. Silicon data based case studies are presented in this work to verify the validity of the proposed method.
author_names: Yuan Wang

Guangyi Lu

Xing Zhang
title: A wafer level characterization method of ESD protection circuits for both component level and system level applications
venue: 2016 Asia Pacific International Symposium on Electromagnetic Compatibility (APEMC)
year: 2016