Query: Model-based clustering for integrated circuit yield enhancement

Candidate papers:

abstract: This paper studies the defect data analysis method for semiconductor yield enhancement. Given the defect locations on a wafer, the local defects generated from the assignable causes are classified from the global defects generated from the random causes by model based clustering, and the clustering methods can identify the characteristics of local defect clusters. The information obtained from this method can facilitate process control, particularly, root cause analysis. The global defects are modeled by the spatial non homogeneous Poisson process, and the local defects are modeled by the bivariate normal distribution or by the principal curve.
author_names: Jung Yoon Hwang

Way Kuo
title: Model based clustering for integrated circuit yield enhancement
venue: Eur. J. Oper. Res.
year: 2007

abstract: The manufacturing yield challenge of 3 D integrated circuit is one of the key obstacles in the industry adoption of 3 D integration based on through silicon vias (TSVs) The addition of spare TSVs to repair faulty functional TSVs (f TSVs) is an effective method for yield and reliability enhancement, but this approach results in significant hardware cost and delay overhead. Most existing solutions are only suitable for a "dual uniform" scenario in which both the placement and the defect probabilities of f TSVs are assumed to be uniform. In this paper, we propose a design technique that is compatible with nonuniform TSV placement and it can repair faulty TSVs based on a realistic clustered defect distribution model. The proposed solution is based on two consecutive stages, which utilize a greedy algorithm and an integer linear programming formulation, respectively. By considering the tradeoff between chip yield, hardware cost, and delay overhead, the proposed technique provides higher yield and reliability under a clustered defect distribution, and with minimum hardware cost and delay overhead, compared to the previous work.
author_names: Shengcheng Wang

Krishnendu Chakrabarty

Mehdi Baradaran Tahoori
title: Defect Clustering Aware Spare TSV Allocation in 3 D ICs for Yield Enhancement
venue: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
year: 2019

abstract: The manufacturing yield challenge of three dimensional integrated circuit (3D ICs) is one of the key obstacles in the industry adoption of 3D integration based on through silicon vias (TSVs) The addition of spare TSVs to repair faulty functional TSVs is an effective method for yield and reliability enhancement, but this approach results in significant hardware cost and delay overhead. Most existing solutions are only suitable for a "dual uniform" scenario in which both the placement and the defect probabilities of functional TSVs are assumed to be uniform. In this paper, we propose a design technique that is compatible with non uniform TSV placement and it can repair faulty TSVs based on a realistic clustered defect distribution model. The proposed solution is based on two consecutive stages, which utilize a greedy algorithm and an integer linear programming formulation, respectively. By considering the trade off between chip yield, hardware cost, and delay overhead, the proposed technique provides higher yield and reliability under a clustered defect distribution, and with minimum hardware cost and delay overhead, compared to the previous work.
author_names: Shengcheng Wang

Mehdi Baradaran Tahoori

Krishnendu Chakrabarty
title: Defect clustering aware spare TSV allocation for 3D ICs
venue: 2015 IEEE/ACM International Conference on Computer Aided Design (ICCAD)
year: 2015

abstract: Clustered faults that affect the manufacture of integrated circuits are modeled by a simulation approach in which the fault formation is a function of time. In one such approach, the probability of generating a fault in a given subarea of an integrated circuit at any given time is assumed to depend on the number of faults already in that area and on the number of faults in the nearest neighbor adjacent subareas. Although such procedures had been used heuristically, technical considerations show that this stochastic approach actually is analytically justifiable. It is found that the resulting distribution functions, the joint probability distribution function, the distribution function of the sum of dependent random variables, and the correlation between these variables are identical to results obtained with a large area cluster model using compound Poisson statistics. This offers a unique insight into a statistical isomorphism that has been a puzzling issue.
author_names: Charles H Stapper
title: Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement
venue: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
year: 1991

abstract: The manufacturing of integrated circuits is not a perfect fault free process. The constant downscaling of integrated circuits requiring higher accuracy each generation also allows the designer to fit more transistors in the same area. From a manufacturing point of view, this downscaling introduces additional possible sources of error, which forces a constant struggle to keep the yield or ratio of successfully manufactured chips high enough to be profitable. The manufacturing success ratio, or yield, is a major component of what determines the time and material cost it takes to manufacture an integrated circuit. To increase yield a common approach is to add redundant or spare parts to the system requiring only enough of them to work. Redundancy has long been a common concept in memories. For random logic blocks, the overhead cost has been too large to be reasonable. But for multi core systems, with several instances of the same logic block, the situation is starting to resemble the case of a memory. The manufacturing yield can be predicted by statistical models. Such models may consist of analytical expressions based on very low level information such as the exact layout features of every transistor and wire of the entire chip. However the addition of a spare core for a multi core cluster is an architectural decision that has to be made in the early stages of the design where low level details are not readily available. The modeling approach taken in this project uses a collection of simplified models previously used for yield calculations for memories. The model results in estimates of the yield before and after the addition of redundant cores. The input parameters to the model are based on gate counts and global routing estimates of an early floor plan together with information about the manufacturing process in the form a fault density. When sources of defects are found and suppressed, the yield ramps up. The yield model presented here also shows the effect the redundancy has on the yield ramp, pushing it towards an earlier volume production date, potentially decreasing the product time to market.
author_names: Mikael Andersson
title: Integrated Circuit Yield Enhancement Redundant Multi Core DSP Cluster
year: 2010

abstract: This paper proposes a new yield model for integrated circuits using a spatial point process. The defect density variation by location on a wafer is modeled by a spatial nonhomogeneous Poisson process. The intensity function of the yield model describes the defect pattern on wafers. As a result, the model differs from the existing compound Poisson yield models in its capability to describe the spatial defect distribution. Using model based clustering, the defect clusters from assignable causes, which contain the information about the variations of manufacturing processes, can be classified from others. The proposed model considers the defect density variation among wafers and the impact of defect size on the probability of a defect causing the circuit failure. The performance of the new yield model is verified using simulated data and real data. Simulation results show that the new yield model performs better than a compound Poisson yield model.
author_names: Jung Yoon Hwang

Way Kuo

Chunghun Ha
title: Modeling of Integrated Circuit Yield Using a Spatial Nonhomogeneous Poisson Process
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2011

abstract: The integrated yield reliability model for integrated circuits allows one to estimate the yield, following both wafer probe and burn in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures, and defects causing infant mortality failures. The 2 parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/ while known to play a key role in accurately determining wafer probe yields, is shown, for the first time, to play a similar role in determining burn in fall out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ appreciably from calculations that ignore clustering. This is particularly apparent when wafer probe yields are low, and clustering is high.
author_names: Thomas S Barnett

Adit D Singh

Victor P Nelson
title: Extending integrated circuit yield models to estimate early life reliability
venue: IEEE Trans. Reliab.
year: 2003

abstract: This dissertation is focussed on developing new approaches for defect and yield modeling and yield enhancement. The research is inspired by the continuing trend of feature size reduction and chip area increments in integrated circuit (IC) manufacturing. A hierarchical taxonomic system for process defects is constructed. The taxonomic system possesses both predictive and explanatory powers, and is therefore a versatile tool in defect and yield modeling and yield enhancement. In defect modeling, a framework for modeling inter layer and intra layer short circuits and intra layer open circuits due to three dimensional spot defects is proposed. The main feature of this framework is parametrization of open circuits from the viewpoint of conductor's resistance, thereby allowing accurate estimations of defect sensitive regions in ICs. A yield model based on generalized Poisson statistics is developed to offer a natural explanation for the presence of defect clusters on integrated circuit chips and wafers. Also, several measures for empirical evaluation of spatial properties of defect patterns on wafers are proposed. Finally, a Design for Yield methodology at the layout synthesis level in IC design is proposed. The focus is on improving routing solutions in terms of layout critical area reduction against short circuits due to spot defects.
author_names: Aakash Tyagi
title: A framework for yield modeling and yield enhancement in integrated circuit design and fabrication
year: 1993

abstract: Two models for the effect of area scaling on reliability are derived from two distinct yield models with different assumptions on defect distributions. One is derived from the Poisson yield model assuming a uniform random distribution of defects as in an early model. The other is based on the negative binomial yield model to account for deviation from a uniform random distribution of defects caused by clustering. Experimental data from backend test structures show that the model based on defect clustering explains observed data well while the model assuming a uniform random distribution shows a significant departure from it.
author_names: Changsoo Hong

Linda S Milor

Munkang Choi

To Ki Lin
title: Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models
venue: Microelectron. Reliab.
year: 2005

abstract: Accurate yield prediction to evaluate productivity, and to estimate production costs, is a critical issue in the highly competitive semiconductor industry. We propose yield models based on hierarchical Bayesian modeling of clustered spatial defects produced in integrated circuits (IC) manufacturing. We use spatial locations of the IC chips on the wafers as covariates, and develop four models based on Poisson regression, negative binomial (NB) regression, zero inflated Poisson (ZIP) regression, and zero inflated negative binomial (ZINB) regression. Along with the hierarchical Bayesian approaches, spatial variations of defects within one wafer as well as among different wafers are effectively incorporated in the yield models. Wafermap data obtained from an industrial collaborator are used to illustrate the proposed models. The results indicate that the Poisson regression model consistently underestimates the true yield because of extraneous Poisson variation caused by defect clustering. On the contrary, NB regression, ZIP regression, and ZINB regression models provide more reliable yield estimation and prediction in real applications.
author_names: Tao Yuan

Saleem Z Ramadan

Suk Joo Bae
title: Yield Prediction for Integrated Circuits Manufacturing Through Hierarchical Bayesian Modeling of Spatial Defects
venue: IEEE Transactions on Reliability
year: 2011