Query: Cleaning technology after semiconductor manufacturing CMP process

Candidate papers:

abstract: The global situation has become increasingly uncertain and it has been a long time since the so called VUCA era began. The semiconductor market, however, is now booming and semiconductor technology seems to have overcome its stagnation. The market has now entered the so called Multi driver era, driven by the IoT, Cloud, AI, Car, and 5G applications, collectively referred to as ICAC5, in addition to the former single set applications, such as PCs and mobile phones. Technologies adapted to the ICAC5 market have also been developed, and device development has been active in three directions: MM (More Moore) MtM (More than Moore) and BC (Beyond CMOS) With the development of semiconductor devices, new technologies are also required for manufacturing equipment such as CMP. Based on the uncertain global outlook, this paper provides an overview of device technology up to 2030 by showing the uniqueness of the semiconductor market, and presents as an example how the CMP process should evolve. Semiconductors are immortal as long as there is human desire. Semiconductors will continue to lead the future of technologies. And semiconductor manufacturing equipment will continue to support the evolution of semiconductor devices.
author_names: Manabu Tsujimura
title: Lead the Future Semiconductor Evolution as Seen by CMP Manufacturers
venue: 2020 China Semiconductor Technology International Conference (CSTIC)
year: 2020

abstract: The research aims at wafer front side defects causing by faulty back sides during the semiconductor manufacturing. The rapid semiconductor development of semiconductor technology comes with the extremely tight control of SPC and small tolerance of defects even the defects in wafer backside could cause the fail of front side chips while technologies entered nanometer node. The wafer backside be polluted and damaged repeatedly by mechanical chucks or robots during manufacturing processes, and which combined with gas or liquid chemical processes could make uneven produce marks. The formation mechanism of the abnormal backside condition was investigated, and the corresponding front side's defect condition was drawn out. In Cu backend, backside clean is required to remove metal ions, however, the difference of acid etching rate on poly silicon and silicon nitride would lead to the abnormal leveling of lithography. Optimizing chemical formulation can improve backside leveling obviously.
author_names: JianGang Zhou

Hungling Chen

Yin Long

Kai Wang

Hao Guo
title: Investigation and Reduction of Systematic Defects by Wafer Backside Process in Nanometer Semiconductor Manufacturing
venue: 2020 China Semiconductor Technology International Conference (CSTIC)
year: 2020

abstract: Many enterprises cannot cost down and quality improve. So, speeding up production time is a new competition ability. Most Product Data Management (PDM) can automate to input files and data through known procedures. But some technology cannot satisfy the requirement for production information in precision, clearness and customization. This paper proposed a technique using application product data management on Integrated Circuit (IC) Design. Using internet, network and circuit simulation for solution problems, resulting from R&D process and the compatibility of customer required products. Using the proposed model in PDM to reduce the correction rate after the IC design and production in order to satisfy customers' demands. The results of this paper are the participating teams of strategic alliance can develop IC product to integrate enterprise subject to the related product quality. Support correct information of product for customer demands to develop relative products. Through the function of IC circuit simulation. The proposed model can verify customers' product instantly to reduce time and cost, and to increase the design efficiency and quality. The customer can use ICs products from building up IC courses. Using this technology can forecast customers' demands, development business trend and strengthen communicate with customers to build customer relationship, put IC products into the commercial market more quickly and enhance customer competition ability. Therefore, for ICs designer can get better product quality, shorten product R&D time and strengthen the competition ability.
author_names: Bin Li

Ruey-Shun Chen

Ci-Chu Chuang

Yuan Tian

Najla Abdulrahman Al-Nabhan
title: Using product data management technology to semiconductor manufacturing industry
year: 2020

abstract: JSR developed family of photoresist, topcoats, underlayer materials and process chemicals for semiconductor manufacturing. JSR's high performance lithography materials are utilized in various critical and non critical lithography applications. JSR underlayer materials are key enabler of complex patterning schemes at advanced technology node. JSR is also a leader in process chemicals solutions including advanced cleans technology, materials for packaging and CMP materials. Our process materials solutions are essential part of advance semiconductor manufacturing.
author_names: Ramakrishnan Ayothi
title: JSR Micro, Inc. JSR patterning materials for semiconductor manufacturing
year: 2021

abstract: In this study, the imaging of metal ions and nanoparticles deposited on a structured silicon surface was investigated using a laser ablation inductively coupled plasma mass spectrometry (LA ICP MS) For application, 8 <inline formula> <tex math notation="LaTeX"\times /tex math>/inline formula> 8 Petri dish pillars, each with a diameter of 250 <inline formula> <tex math notation="LaTeX"\mu \text{m} /tex math>/inline formula> and height of 300 <inline formula> <tex math notation="LaTeX"\mu \text{m} /tex math>/inline formula> were constructed on a silicon wafer. The etched pillar surface took a droplet of approximately 4.3 nL aqueous solution from a capillary tip through the surface liquid attraction. The dissolved materials were found at the intersecting edge of pillar bottom after evaporation, and their positions were matched with the peaks of elements in the mass spectrum for imaging. Results suggest that the trace contaminants in the cleaning solution are gathered at the intersecting edges of the patterned wafer, and the multi elemental images of the contaminants can be successfully obtained using LA ICP MS.
author_names: H B Lim

Katherine M McLachlin

Ciaran O'Connor

Daniel R Wiederin

Hyuck Ki Hong
title: Imaging of Metal Ions and Nanoparticles on Structured Silicon Surface Using Laser Ablation Inductively Coupled Plasma Mass Spectrometer for Contamination Control in Semiconductor Manufacturing Process
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2021

abstract: In Microwave module, wire bonding is usually gold wedge bonding. The reliability of wedge bonding mainly depends on the surface characteristics of joint. The contamination on bond pads may result in low strength and poor strength uniformity. Therefore, contaminants must be removed from the bonding area before wedge bonding. In the present study, the effects of plasma cleaning on the reliability of wedge bonding are investigated. The cleaning methods of different process parameters were studied, and the appropriate process parameters were found. Plasma cleaning was performed on different substrates and chips and compared with those before plasma cleaning. The influence of plasma cleaning on bond contact quality has been examined by pull force measurements, which is an established test method in semiconductor packaging industry for evaluating the quality of wire bonds. From the experimental data, it is observed that the plasma cleaning with proper parameter tuning can improve the contact angle characteristics and the reliability of wire bonding, and the wire bonding strength after plasma cleaning meets microwave hybrid integrated circuit requirements. The results can provide reference for plasma cleaning, and process optimization of wedge bonding.
author_names: Zhidan Liu

Zhiping Zhao

Shuai Chen

Fei Zhang
title: Investigation on Plasma Cleaning Technology of Wedge Bonding
venue: 2020 21st International Conference on Electronic Packaging Technology (ICEPT)
year: 2020

abstract: Abstract This study prepared high purity indium metal using raw materials recovered from process chips (Cu Chip) in the electronics industry, and designed and modified a pilot device based on the Czochralski (CZ) method. The crystallinity of indium metal, which is crystallized at the reaction temperature of 180 230 was lowered since its rotation speed and pulling speed were faster than the crystal growth rate. Next, surface oxidation and corrosion during the CZ process were solved in a relatively simple manner. Only C, Al, and In were detected from the crystallized indium metal surface, while no O was detected. The study showed that the impurity content before and after the CZ process decreased and detected very small amounts of Sn, Fe, Si, Pb, etc. in several ppb with the purity of grade 6N (99.99996%
author_names: Ho Se Lee

Jae Yeol Yang

Byung Jo Jung

Jae Sik Yoon
title: The manufacturing technology of grade 6 N high purity indium metal for compound semiconductor
year: 2020

abstract: Sulfuric Peroxide Mixture (SPM, H2SO4 H2O2) has been widely used in semiconductor manufacturing processes due to its high reactivity and attractive price. However, SPM releases SO42 ions that can be high impact on the environmental contaminations. Therefore, the SPM process requires a high cost wastewater treatment. So, the development of alternative chemicals has been becoming an important task in the semiconductor manufacturing process. In this paper, we evaluated the feasibility of replacing SPM with dissolved ozone water (DIO3) in the wafer cleaning process, and confirmed that the Particle removal efficiency (PRE) was improved around 68% by mixing with diluted hydrofluoric acid (DHF) And, the PRE was also increased when the concentration of ozone in dissolved ozone water increased. Additionally the PRE was improved up to 98% by combining physical cleaning after O3 process.
author_names: Hyeon Joon Han

Hunhee Lee

Charles Kim

Yong-mo Kim

Jinok Moon

Dukmin Ahn

Seokjun Hong

Taesung Kim
title: Ultrafine Particle Removal in the Wafer Cleaning Process Using an Aqueous Solution with a High Concentration of Dissolved O3 and HF
year: 2021

abstract: Chemical mechanical polishing (CMP) is a key process in integrated circuit (IC) manufacturing. Successful fabrication of semiconductor devices is highly dependent on the final planarity of the processed layers. Post CMP topography variation may cause degradation of the circuit performance. Moreover, the depth of focus (DOF) requirement is critical for lithography of subsequent layers. As such, planarity requirements are critical for maintaining IC manufacturing technology scaling trends, and supporting device innovation. To mitigate post CMP planarity issues, dummy fill insertion has become a commonly used technique. Many factors impact dummy fill insertion results, including fill shapes, sizes, and the spacing between both fill shapes and the drawn layout patterns. The goal of the CMP engineer is to optimize design planarity, but the variety of fill options means just verifying the design rules for fill is a challenging task. This data collection currently requires a long development cycle, consuming a great deal of time and resources. In this paper, we show how CMP modeling can help resolve these issues by applying CMP modeling and simulations to drive Calibre YieldEnhancer SmartFill parameters that have been optimized for dummy fill. Additional capabilities in the SmartFill functionality automate CMP hotspot fixing steps. Using CMP simulations, engineers can get feedback about post CMP planarity for given fill options in a much shorter time. Not only does this move dummy fill optimization experiments from a real lab into a virtual lab of CMP modeling and simulation, but it also provides more time for these experiments, providing improved results.
author_names: Liwei Jiang

Yun Cao

Jiao-Long Zhang

Fang Wei

Zhengfang Liu

Chunshan Du

Ruben Ghulghazaryan

Davit Piliposyan

Jeff Wilson

Qijian Wan

Xinyi Hu

Zhixi Chen
title: CMP simulation based dummy fill optimization
year: 2020

abstract: Chemical mechanical polishing/planarization (CMP) is one of the most important fabrication technologies in the semiconductor industry. CMP is used to achieve planar surfaces and remove excess deposited material from the wafer. During CMP, a chemical "slurry" containing abrasive particles and chemical reagents is deposited on the polishing pad. The polishing pad is then pressed against the rotating wafer. The combined action of the polishing pad and chemical slurry results in material removal and planarization of the wafer surface. Modeling of the CMP process allows detection of potential planarization defects in chips before manufacturing. Accurate computation of pressure distribution across the wafer surface is crucial for accurate modeling of the CMP process. The pressure distribution calculation is usually done using the Hertz contact theory and Chekina model, which involves computations of direct and inverse fast Fourier transforms (FFT and IFFT) and pad displacements updates. In this paper, we adopted an obstacle problem approach for calculating the pressure distribution across the wafer/die surface for CMP modeling. In an obstacle problem, the pad is assumed to be an elastic membrane with fixed boundaries that is displaced by the wafer surface. The goal is to find the equilibrium position for the pad and calculate the pressure distribution over the surface in contact. The main advantage of this approach is that computations of FFT and IFFT and recalculations of the pad displacements can be avoided. This can lead to a more accurate model that is independent of pad displacement update method. The approach is tested on several examples. The results show correct physical behaviour and are in agreement with expectations.
author_names: Davit Piliposyan

Ruben Ghulghazaryan

Martin Poghosyan

Hayk H Nersisyan
title: Pressure calculation using obstacle problem for CMP modeling
year: 2020