Query: Variability Modeling and Statistical Parameter Extraction for CMOS Devices

Candidate papers:

abstract: Semiconductor technology has been scaling down at an exponential rate for many decades, yielding dramatic improvements in power, performance and cost, year after year. Today's advanced CMOS transistors have critical dimensions well below 24nm. This means that controlling the manufacturing process is increasingly difficult. Process and material fluctuations cause device and circuit characteristics to deviate from design goals, and introduce significant device to device variability due to spatial variations across silicon wafers. Accurate modeling of these spatial process variations has become critical to both foundries and circuit designers that seek optimal power/speed/area balance. To understand the nature of spatial process variations, we first carried out a comprehensive variability analysis of data measured from thousands of variability sensitized test structures, including ring oscillators, SRAM bit cells and their internal transistors. We manufactured these test chips using early stage 90nm and 45nm commercial semiconductor processes. We proposed a hierarchical variability model to capture the systematic and random components of device parameter variations across silicon wafers, and across chips. The detailed decomposition of the process variation profile reveals significant across wafer systematic component for the delay and leakage of ring oscillators, and across chip systematic component for the read/write margins of SRAM bit cells, as well as their internal transistors. The proper modeling of each hierarchical component proved to be crucial for the accurate estimation of the statistics of device performance distribution and its parametric yield.The knowledge gained about process variation from carefully designed test structures was leveraged into estimating the variation and parametric yield of new devices and circuits. This was accomplished by improved the statistical compact model parameter extraction methodology, and by proposing a stepwise parameter selection method. We used a normalized notional confidence interval and, and the sum of squares of fitting residuals as extraction and fitting quality criteria. This allowed us to determine the essential model parameters for accurate fitting over a large number of transistors. We applied this methodology to EKV and PSP with both simulated and experimental data, demonstrating its effectiveness. Finally, we combined the results from statistical parameter extraction with the hierarchical spatial variability model. This, compared to traditional methods, produced much improved estimates of device performance and manufacturing yield.
author_names: Kun Qian
title: Variability Modeling and Statistical Parameter Extraction for CMOS Devices
year: 2015

abstract: Statistical variability is a major challenge for CMOS scaling and integration. In order to achieve variability aware design, it's critical important to reliably transfer device characteristics statistical variability information into compact models. A PCA based statistical compact modeling strategy is benchmarked against 'atomistic' device simulation and direct statistical parameter extraction strategy. The results indicate that PCA based approach may introduce considerable error in tail of distribution, which in turn may generate pessimistic or optimistic conclusions in statistical circuit simulation.
author_names: Binjie Cheng

Negin Moezi

Daryoosh Dideban

Gareth Roy

Subhasish Subhasish

Asen Asenov
title: Benchmarking the Accuracy of PCA Generated Statistical Compact Model Parameters Against Physical Device Simulation and Directly Extracted Statistical Parameters
venue: 2009 International Conference on Simulation of Semiconductor Processes and Devices
year: 2009

abstract: As CMOS scales down to sub 50 nm, it faces critical dimensions of charge and matter granularities, leading to the drastic increase of device parameter dispersion, named statistical variability, which is one of the main contemporary challenges for further downscaling and makes each device atomistically different leading to broad dispersion of their electrical characteristics. In addition, device reliability concerns gain inertia; among them Bias Temperature Instability (BTI) shortens device lifetime by trapping charges in defect states of the insulator or at the interface. The interplay between statistical variability and BTI results in more variations on device performance and thus greatly affect circuit performance. In turn design methodologies must evolve towards variability and reliability aware design. To do so statistical compact models including both the effects of statistical variability and BTI induced ageing are required for the large scale statistical circuit simulation of variability and reliability. In this study, the application of accurate compact models, that describe performance variation in the presence of both statistical variability and reliability at arbitrary BTI induced ageing levels, to SRAM circuit simulation is described. Both SRAM cell stability and write performance are evaluated and it is seen that, due to the accurate description of device performance distributions provided by the compact models and the sensitivity of these SRAM performance metrics on device performance, the approach presented here is better suited to high sigma statistical circuit analysis than conventional approaches based upon assumed Gaussian distributions. The approach is demonstrated using a 25 nm gate length bulk MOSFET whose performance variation is obtained from statistical TCAD simulation using the GSS simulator GARAND. The simulated performance data is then used directly as the target for BSIM4 compact model extraction that ensures device figures of merit are well resolved for each device in a statistical ensemble. The distribution of compact model parameters is then generalised into an algebraic form using Generalized Lambda Distribution (GLD) methods, so that a sufficiently large number of compact models can later be generated and interpolated at arbitrary ageing levels. Finally compact models generated in this way are used to evaluate SRAM write performance and stability under the influence of statistical variability and BTI induced ageing.
author_names: Jie Ding
title: Accurate CMOS compact model and the corresponding circuit simulation in the presence of statistical variability and ageing
year: 2015

abstract: Abstract This paper presents an effective statistical compact modelling strategy that can precisely capture a statistical set of MOSFET characteristics into industrial strength statistical compact models. 3D simulation of large statistical sample of microscopically different devices is required for statistical compact model extraction when studying the impact of variability in next CMOS technology generations on circuit and system design. For a particular nominal device design the statistical 3D physical simulations needs two orders of magnitude more CPU time compared to conventional TCAD simulations. A data sampling strategy is presented to reduce the number of bias points in simulated device characteristics used as extraction targets for statistical compact model parameter extraction. We show that for a well balanced set of statistical compact model parameters carefully chosen small number of strategic bias points in the simulated I V characteristics of each microscopically different transistor is sufficient to capture accurately the statistical device behaviour. The corresponding increase in the RMS error is below 1% compared to results from comprehensive bias point set. The impact of the slight reduction of the compact model accuracy on the accuracy of statistical circuit simulation has also been investigated.
author_names: B Bindu

Binjie Cheng

Gareth Roy

Xingsheng Wang

Scott Roy

Asen Asenov
title: Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction
year: 2010

abstract: Intrinsic statistical variability (SV) associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. There are several standard statistical parameter generation strategies to transfer SV information into compact models, and their accuracy is essential for achieving reliable variability aware design. We investigate the accuracy of these strategies based on the direct statistical compact model parameter extraction results for industry standard compact models BSIM4 and PSP. Statistical circuit simulation results indicate that the standard assumption for uncorrelated normal distribution of the statistical compact model parameters may introduce considerable errors in the statistical distribution of circuit figure of merits.
author_names: Binjie Cheng

Daryoosh Dideban

Negin Moezi

Campbell Millar

Gareth Roy

Xingsheng Wang

Scott Roy

Asen Asenov
title: Benchmarking statistical compact modeling strategies for capturing device intrinsic parameter fluctuations in BSIM4 and PSP
year: 2010

abstract: One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it is necessary to transfer reliably the MOSFET statistical variability information into compact models to facilitate variability aware design practice. The aim of this project is the development of a statistical extraction methodology essential to capture statistical variability with optimum set of parameters particularly in industry standard compact model BSIM. This task is accomplished by using a detailed study on the sensitivity analysis of the transistor current in respect to key parameters in compact model in combination with error analysis of the fitted Id Vg characteristics. The key point in the developed direct statistical compact model strategy is that the impacts of statistical variability can be captured in device characteristics by tuning a limited number of parameters and keeping the values for remaining major set equal to their default values obtained from the "uniform" MOSFET compact model extraction. However, the statistical compact model extraction strategies will accurately represent the distribution and correlation of the electrical MOSFET figures of merit. Statistical compact model parameters are generated using statistical parameter generation techniques such as uncorrelated parameter distributions, principal component analysis and nonlinear power method. The accuracy of these methods is evaluated in comparison with the results obtained from 'atomistic' simulations. The impact of the correlations in the compact model parameters has been analyzed along with the corresponding transistor figures of merit. The accuracy of the circuit simulations with different statistical compact model libraries has been studied. Moreover, the impact of the MOSFET width/length on the statistical trend of the optimum set of statistical compact model parameters and electrical figures of merit has been analyzed with two methods to capture geometry dependencies in proposed statistical models.
author_names: Negin Moezi
title: Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability
year: 2012

abstract: Combined C V/I V and RTN CMOS Variability Characterization Using An On Chip Measurement System Simeon Dimitrov Realov With the number of transistors integrated into a single integrated circuit (IC) crossing the one billion mark and complementary metal oxide semiconductor (CMOS) technology scaling pushing device dimensions ever so close to atomic scales, variability in transistor performance is becoming the dominant constraint in modern day CMOS IC design. Developing novel approaches for device characterization, which allow a detailed study of electrical transistor characteristics across large statistical sample sets, is crucial for the proper identification, characterization, and modeling of different physical sources of device variability. On chip characterization methodologies have the potential to address all of these issues by enabling the characterization of large statistical device sample sets, while also allowing for high measurement quality and throughput. In this work, a fully integrated system for on chip combined capacitance voltage (C V) and current voltage (I V) characterization of a large integrated test transistor array implemented in a 45 nm bulk CMOS process is presented. On chip I V characterization is implemented using a four point Kelvin measurement technique with 12 bit sub 10 nA current measurement resolution, 10 bit sub 1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C V characterization is performed using a novel leakageand parasitics insensitive charge based capacitance measurement (CBCM) technique with atto Farad resolution. The on chip system is employed in developing a comprehensive CMOS transistor variability characterization methodology, studying both random and systematic sources of quasi static device variability. For the first time, combined C V/I V characterization of circuit representative devices is demonstrated and used to extract variations in the underlying physical parameters of the device. Additionally, the fast current sampling capabilities of the system are used for the characterization of random telegraph noise (RTN) in small area devices. An automated methodology for the extraction of RTN parameters is developed, and the statistics of RTN are studied across device type, bias, and geometry.
author_names: Simeon Realov
title: Combined C V/I V and RTN CMOS Variability Characterization Using An On Chip Measurement System
year: 2012

abstract: The development of a statistical compact model strategy for nano scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized.
author_names: Daryoosh Dideban
title: Statistical modelling of nano CMOS transistors with surface potential compact model PSP
year: 2012

abstract: The implementation of a viable statistical circuit design methodology requiring detailed knowledge of the variabilities of, and correlations among, the circuit simulator model parameters utilized by designers, and the determination of the important relationships between these CAD model parameter variabilities and the process variabilities causing them is presented. This work addresses the above requirements by detailing a new framework which was adopted for a 2 /spl mu/m CMOS technology to enable realistic statistical circuit performance prediction prior to manufacture. Issues relating to MOSFET modeling, the derivation of fast "direct" parameter extraction methodologies suitable for rapid parameter generation, the employment of multivariate statistical techniques to analyze statistical parametric data, and the linking of the CAD model parameter variations to variabilities in process quantities are discussed. In this approach the correlated set of model parameters is reduced to a smaller and more manageable set of uncorrelated process related factors. The ensuing construction and validation of realistic statistical circuit performance procedures is also discussed. Comparisons between measured and simulated variabilities of device characteristics is utilized to demonstrate the accuracy of the techniques described. The advantages of the proposed approach over more traditional "worst case" design methodologies are demonstrated.
author_names: James A Power

Brian Donnellan

Alan Mathewson

William A Lane
title: Relating statistical MOSFET model parameter variabilities to IC manufacturing process fluctuations enabling realistic worst case design
year: 1994

abstract: This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3 D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated.
author_names: Noor Ain Kamsani
title: Statistical Circuit Simulations: From 'Atomistic' Compact Models to Statistical Standard Cell Characterisation
year: 2012