Query: Dry etching technology for Semiconductors

Candidate papers:

author_names: Kazuo Nojiri
title: Dry Etching Technology for Semiconductors
year: 2014

abstract: The author joined the semiconductor industry in 1975. Combined with his 3 earlier years spent on semiconductor research in college and in graduate school, the author's total involvement with semiconductors has spanned approximately 40 years. During that time, semiconductor technology has made incredible advances in terms of device scaling, density increases, and larger wafer diameters. As mentioned in Chap. 1, the device minimum feature size has been shrunk by approximately 30 every 3 years, and the LSI device density has been increasing pretty much according to Moore's law. In 1975, when the author first started in the semiconductor industry, a large number of discrete bipolar transistors were still in manufacturing, and 16K DRAM, based on the 5 mm process, was just about to begin. As of 2011, logic devices and memory products, with minimum feature sizes of 32 28 nm, had gone into volume production. This means that minimum feature sizes were scaled to 1/200 in 36 years. At the same time, the number of transistors on each microprocessor chip grew by approximately 100,000 fold. Furthermore, the Si wafer diameter, which used to be 75 mm in 1975, had grown to 300 mm. It is a different world today.
author_names: Kazuo Nojiri
title: Future Challenges and Outlook for Dry Etching Technology
year: 2015

abstract: The recent advances in the material quality of the group III nitride semiconductors (GaN, A1N, and InN) have led to the demonstration of high brightness light emitting diodes, blue laser diodes, and high frequency transistors, much of which is documented in this issue of MRS Bulletin While further improvements in the material properties can be expected to enhance device operation, further device advances will also require improved processing technology. In this article, we review developments in two critical processing technologies for photonic and electronic devices: ion implantation and plasma etching. Ion implantation is a technology whereby impurity atoms are introduced into the semiconductor with precise control of concentration and profile. It is widely used in mature semiconductor materials systems such as silicon or gallium arsenide for selective area doping or isolation. Plasma etching is employed to define device features in the semiconductor material with controlled profiles and etch depths. Plasma etching is particularly necessary in the III nitride materials systems due to the lack of suitable wet etch chemistries, as will be discussed later. Figure 1 shows a laser diode structure (after Nakamura) where plasma etching is required to form the laser facets that ideally should be vertical with smooth surfaces. The first III nitride based laser diode was fabricated using reactive ion etching (RIE) to form the laser facets but suffered from rough mirror facet surfaces that contributed to scattering loss and a high lasing threshold. This is a prime example of how improved material quality alone will not yield optimum device performance.
author_names: John C Zolper

Randy John Shul
title: Implantation and Dry Etching of Group III Nitride Semiconductors
year: 1997

abstract: Electron cyclotron resonance (ECR) plasma etching of GaAs, AlGaAs, and GaSb in Cl2/Ar or BCl3/Ar, and of InP in CH4/H2/Ar discharges is performed down to 30 degC substrate temperature and characterized in terms of rate, anisotropy, damage introduction and near surface stoichiometry. Below 10 degC the vertical etch rates of all these semiconductors decrease due to reduced volatility of the products, and there is suppression of lateral etching with chlorine based mixtures, but no change in anisotropy of CH4/H2/Ar etched features. Etching of typical dielectrics (SiNx,SiO2) and metals (W) used in bipolar or field effect transistors in SF6/Ar discharges was also characterized, and for substrate temperatures below 20 degC increased concentrations of fluorine containing residues are found on the exposed semiconductor surface after removal of the dielectric or metal. These can be removed by a 500 W microwave ECR H2 plasma with low additional 25 V) dc bias on the sample. The effect of an additional lower collimatin.
author_names: Stephen J Pearton

Cammy Renee Abernathy

Fan Ren
title: High density, low temperature dry etching in GaAs and InP device technology
year: 1995

abstract: of optoelectronic and electronic devices involving III V materials, due to the need for careful control of the critical dimensions of components. Fast etch rates, repeatability, uniformity, clean chemistries, vertical profile and low device damage are some of the most desirable aspects of the etching processes. Inductively coupled plasma (ICP) etching is ideally suited to these requirements, since it provides high ion densities and hence fast etch rates, while allowing separate control of ion density and ion energy (giving a low damage capability) To meet these demands, Oxford Instruments Plasma Technology (OIPT) has developed a wide range of ICP etch processes for III V semiconductors. This article focuses on etching processes for InP and related materials, discussing various etching chemistries and system requirements for different applications and providing an update of the latest new process developing results.
author_names: Ligang Deng
title: Dry etching of InP based materials using a high density ICP plasma system
year: 2013

abstract: The Si bulk FinFET (BFFT) concept was developed about 10 years ago [1, 2] Moreover, Intel has recently announced that this technology, named tri gate transistors, is ready to be used in production for the 22nm node and it will be available in their new "Ivy Bridge" microprocessors [3] Though it is not quite clear whether all main IC manufacturers will follow the BFFT concept (the challenges and opportunities of BFFT architecture compared to the planar transistor based on SOI are still being discussed in the literature [4, 5] there seems to be a consensus on the limitations of Si based technology for the smaller generation nodes. According to the International Technology Roadmap for Semiconductors (ITRS) the Ge (in pMOS) and III V semiconductors (in nMOS) are, most likely, the new channel materials that can substitute Si and they are to be introduced in the CMOS mainstream starting from the 14nm node and below. While the main efforts of such material integration are currently directed towards the selective epitaxial growth of Ge and III V in the STI trenches after the Si recess, we have demonstrated the patterning of the BFFT structure directly in the blanket epitaxially grown relaxed SiGe layer with the Ge content of 75% by using dry plasma etching. Due to the challenges of defectivity control in the layers grown epitaxially from the recessed Si in STI, a combined epi dry etch approach might be needed to obtain defect free fins. The dry etch plasma development was performed in the 300mm conductor etch reactor, 2300 KiyoC Series (from Lam Research) The SiCl4 based advanced chamber condition control strategy (AC6) was used for every wafer etched in the chamber in order to provide equal conditions. The patterning stack is composed of the following layers: Resist/Barc/Darc/APF/SiN/padoxide/SiGe. Fig.1. shows the comparative etching of Si and SiGe BFFTs with one and the same recipe based on an oxidelike passivation layer, which is attributed to the Cl2/O2/N2 type of silicon etch chemistries [6, 7]
author_names: A Milenin

Liesbeth Witters

B Deweerdt

C Vrancken

M Demand
title: Direct SiGe BFFT Patterning by Dry Plasma Etching
year: 2012

abstract: The invention discloses an early stage production method for machining a surface of a sapphire substrate for dry etching, and belongs to the technical field of semiconductors. The method comprises the following steps of: preparing a photoetching pattern on the sapphire substrate by a photoetching technology; performing evaporation on the sapphire substrate by using vacuum evaporation equipment to form a multilayer metal structure of A/Ni/B/Ni/C/Ni..to serve as a mask layer for etching the sapphire substrate; placing the sapphire substrate in a photoresist removing agent corresponding to a photoresist; and performing a photoresist stripping process to obtain a metal mask structure. A prepared semi finished product, namely the sapphire substrate with the metal mask structure, can meet the process requirements of the sapphire substrate on various kinds of dry etching of different depth dimensions; and the surface can be machined by a dry etching technology.
title: Early stage production method for machining surface of sapphire substrate for dry etching
year: 2010

abstract: Dry process technology represents a new and exciting technique for defining images in insulators, semiconductors, and metals. It is attractive for application in the semiconductor industry because it results in increased dimensional and shape control for etched images. In addition, it represents a potentially less expensive process which is inherently safer for the people involved. Several different plasma etch system configurations are available for experimentation. Each has unique capabilities for different films. The different equipment configurations are described, including their ability to etch particular films, and the effects of the process on the etched image formed. Information is presented on other halogenated gases that may have potential application as a part of the dry process technology. Since experimental evidence is not available to explain the mechanisms involved in this technology, the published information speculating as to whether radicals, ions, or neutrals are responsible for etchin.
author_names: James A Bondur
title: Dry process technology (reactive ion etching)
year: 1976

abstract: Producing densely packed high aspect ratio In0.53Ga0.47As nanostructures without surface damage is critical for beyond Si CMOS nanoelectronic and optoelectronic devices. However, conventional dry etching methods are known to produce irreversible damage to III V compound semiconductors because of the inherent high energy ion driven process. In this work, we demonstrate the realization of ordered, uniform, array based In0.53Ga0.47As pillars with diameters as small as 200 nm using the damage free metal assisted chemical etching (MacEtch) technology combined with the post MacEtch digital etching smoothing. The etching mechanism of InxGa1 xAs is explored through the characterization of pillar morphology and porosity as a function of etching condition and indium composition. The etching behavior of In0.53Ga0.47As, in contrast to higher bandgap semiconductors (e.g. Si or GaAs) can be interpreted by a Schottky barrier height model that dictates the etching mechanism constantly in the mass transport limited regime because of the low barrier height. A broader impact of this work relates to the complete elimination of surface roughness or porosity related defects, which can be prevalent byproducts of MacEtch, by post MacEtch digital etching. Side by side comparison of the midgap interface state density and flat band capacitance hysteresis of both the unprocessed planar and MacEtched pillar In0.53Ga0.47As metal oxide semiconductor capacitors further confirms that the surface of the resultant pillars is as smooth and defect free as before etching. MacEtch combined with digital etching offers a simple, room temperature, and low cost method for the formation of high quality In0.53Ga0.47As nanostructures that will potentially enable large volume production of In0.53Ga0.47As based devices including three dimensional transistors and high efficiency infrared photodetectors.
author_names: Lingyu Kong

Yi-Zuo Song

Jeong Dong Kim

Lan Yu

Daniel Wasserman

Wai Kin Chim

Sing Yang Chiam

Xiuling Li
title: Damage Free Smooth Sidewall InGaAs Nanopillar Array by Metal Assisted Chemical Etching.
venue: ACS nano
year: 2017

abstract: Wide bandgap semiconductors have many properties that make them attractive for high power, high temperature device applications. In this paper we review wet etching of three important materials, namely ZnO, GaN and SiC. While ZnO is readily etched in many acid solutions including HNO3/HCl and HF/HNO3, and in the nonacid acetyleacetone, the group III nitrides and SiC are very difficult to wet etch and generally dry etching is used. Various etchants for GaN and SiC have been investigated, including aqueous mineral acid and base solutions, and molten salts. Wet etches have a variety of applications to wide bandgap semiconductor technology, including defect decoration, polarity and polytype (for SiC) identification by producing characteristic pits or hillocks, and device fabrication on smooth surfaces. Electrochemical etching is successful at room temperature in some situations for GaN and SiC. In addition, photo assisted wet etching produces similar rates independent of crystal polarity.
author_names: Stephen J Pearton

Won-Jun Lim

Fan Ren

David P Norton
title: Wet Chemical Etching of Wide Bandgap Semiconductors GaN, ZnO and SiC
year: 2007