Query: Gate diffusion input

Candidate papers:

abstract: Abstract A full swing high speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic has been proposed in this work. The design has been verified and compared with ten existing state of the art FAs to validate its performance. Simulations were conducted using Cadence Computer Aided Design (CAD) tool in 45 nm CMOS process. The proposed design shows significant performance improvement in terms of speed and Power Delay Product (PDP) To evaluate performance parameters in large structures, the FAs have been cascaded and extended up to 32 bits. The proposed design, along with five out of ten existing designs worked flawlessly when extended to 32 bits. However, the proposed design achieved the best performance parameters in large cascaded circuits.
author_names: Mehedi Hasan

Hasan U Zaman

Mainul Hossain

Parag Biswas

Sharnali Islam
title: Gate Diffusion Input technique based full swing and scalable 1 bit hybrid Full Adder for high performance applications
year: 2020

abstract: Gate diffusion input (GDI) method using a simple cell makes it possible to design low power logic gates with reduced chip area and less complexity. In this work, a novel design of single bit optimized reversible logic based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field effect transistors (CNTFETs) based on modified GDI (m GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non dominated sorting genetic algorithm II (NSGA II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise tolerable criterions, compared to those competitors with similar design in non optimized conditions. The proposed optimized and non optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible based applications, such as future generations of FPGA chips and CNTFET based computers.
author_names: Ebrahim Abiri

Abdolreza Darabi

Mohammad Reza Salehi

Ayoub Sadeghi
title: Optimized Gate Diffusion Input Method Based Reversible Magnitude Arithmetic Unit Using Non dominated Sorting Genetic Algorithm II
venue: Circuits Syst. Signal Process.
year: 2020

abstract: The priority encoder finds its wide scope as microprocessor interrupt controllers in digital and computer systems, where they classify the highest priority input. A Priority level is assigned to every input. The currently active input that has the highest importance agrees well with the output. A proficient implementation of 4 bit priority encoder using the modified gate diffusion input technique has been proposed in this research work. A simulation was carried out using Cadence 180 nm technology comparison made with complementary CMOS and Modified Gate Diffusion Input technique quality test matrices. This technique is much higher in speed and is a technique with limited power consumption
author_names: Radha N

R Dagineeshwari

B Devadharshini
title: A Modified Gate Diffusion Input Technique Based Proficient 4 Bit Priority Encoder
venue: 2020 International Conference on Inventive Computation Technologies (ICICT)
year: 2020

abstract: Gate Diffusion Input (GDI) is a technique of low power combinational circuit design. Complex logic functions like F1, F2, OR, AND, MUX and NOT can be implemented using just two transistors. GDI reduces area, propagation delay and power consumption of digital circuits, and has lower logic complexity than traditional CMOS and existing pass transistor logic techniques. Low power dissipation is achieved by reducing transistor count. Reducing area lowers the interconnect effects. In this paper, first the logic gates (GDI and CMOS) were implemented in Cadence in 90 nm and gate libraries were created for these. To estimate the complexity and scalability of GDI, ISCAS 85 benchmark circuits were synthesized using these libraries and compared in terms of area, power and delay. GDI circuits prove to be better in terms of area and power than their CMOS counterparts though slightly slower. They may be made faster by buffering logic after every few stages.
author_names: Utsav Vasudevan

U B Meghana

Deepali Koppad

S Vignesh

M Sowjanya
title: Design of Digital Circuit Implementations Using Gate Diffusion Input and CMOS
venue: 2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)
year: 2020

abstract: This paper presents a novel approach to the design of Null Convention Logic threshold gates using Gate Diffusion Input design methodology. Power and delay are the metrics of comparison between the proposed Gate Diffusion Input based Null Convention Logic gates and the conventional Null Convention Logic gates developed in literature. The efficiency of the proposed gates is illustrated by the design and simulation of NCL threshold gates using FSGDI and comparing the same with conventional static CMOS gates. The proposed FSGDI NCL gates offered 37% 23% and 44% reduction in average power, average delay and average power delay product. Keywords: FSGDI, full swing gate diffusion input, gate diffusion input, GDI, low power, NCL, NCL threshold gates, null convention logic Cite this Article: Anitha Juliette Albert, Murugan R. Muthammal R. Full swing gate diffusion input based NCL threshold gates. International Journal of Mobile Computing Devices. 2020; 6(1) 13 20p.
author_names: Anitha Juliette Albert

R Bala Murugan

Ramula Muthammal
title: Full Swing Gate Diffusion Input Based NCL Threshold Gates
year: 2020

abstract: Multi threshold null convention logic (MTNCL) is a novel low power paradigm for designing asynchronous null convention logic (NCL) circuits. To further reduce the dynamic power consumption, a new methodology that utilizes gate diffusion input technique is proposed. The proposed approach is used to realize MTNCL gates and a decrease in the transistor count is observed that tend to reduce the dynamic power consumption. Compared to SMTNCL approach, the proposed methodology shows a 5.6% is reduction in the power consumption for the MTNCL gates.
author_names: Prashanthi Metku

Minsu Choi

Yong-bin Kim
title: Gate Diffusion Input Multi Threshold Null Convention Logic Circuit Design Approach
venue: 2020 International SoC Design Conference (ISOCC)
year: 2020

abstract: Low Power Fin Field Effect Transistor Based Combinational Circuits Design Using Gate Diffusion Input Method Thamizhpriya Muthamizhselvan and Krithiga Sukumaran 1 PG ScholarApplied Electronics, Thanthai Periyar Government Institute of Technology Vellore, T. N India 2 Assistant Professor, Department of ECE, Thanthai Periyar Government Institute of Technology Vellore, T. N India E mail: mthamizhpriyaece@gmail.com, krithiga.sri@gmail.com
author_names: Thamizhpriya Muthamizhselvan

Krithiga Sukumaran
title: Low Power Fin Field Effect Transistor Based Combinational Circuits Design Using Gate Diffusion Input Method
year: 2020

abstract: The rapid growth in the use of portable systems has sparked research and development in the field of microelectronics especially for power consumption. Since battery technology does not match the speed of microelectronics, Low power technology has become an important technological factor. MGDI is a minimum power architecture design, which is quite a Gate Diffusion Input (GDI) change and is the lowest design method optimal for rapid, low power circuitry model using a reduced number of a transistor. Here, primitive cells AND, OR, and XOR gates, full adders, full subtractors, and 4x4 multiplier have been proposedusing the 180nm technology dependent MGDI in Cadence Virtuoso device. The main downside associated with GDI is that this strategy cannot resolve the bulk terminal which is not sufficiently biased. So that the number transistor count and delay will be reduced.
author_names: S N

Radha N
title: Design and Implementation of Primitive Cells, Full Adder, Full Subtractor, and Multiplier using Modified Gate Diffusion Input Logic
venue: 2020 International Conference on Electronics and Sustainable Communication Systems (ICESC)
year: 2020

abstract: GDI technique allows minimization of area and power consumption of digital circuits. The reversible gate preserves same parity between output and input vectors is called fault tolerant but the dimension should be 3. In this design, Peres Gate is designed using Gate Diffusion Input using 8 transistors. The proposed new Peres Gate is used to design full adder with power efficient and fault tolerant. In this work power consumption 51.62mW is achieved for supply voltage 1V and the total area is 492mm2. The schematic is designed in DSCH 2 and layout is done in Microwind 2.
author_names: Somashekhar Malipatil

Avinash Gour

Vikas Maheshwari
title: Fault Tolerant Reversible Full Adder Design Using Gate Diffusion Input
venue: 2020 International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE)
year: 2020

abstract: Gate diffusion input (GDI) is a new technology of digital circuit design for low power. Compared with traditional CMOS technology, GDI technology can reduce the power consumption, the propagation delay and the circuit area. This work uses the GDI technology to build a 16 bit arithmetic logic unit (ALU) to perform logic operations (AND, OR, NAND and XOR) and math operations (addition, subtraction, adding 1 and subtracting 1) and finally compares it with traditional CMOS circuits.
author_names: Yihang Duanmu

Jianguo Yang

Jinbao Li

Xiaoyong Xue

Ming-e Jing

Xiaoyang Zeng
title: A 16 bit Arithmetic Logic Unit Design by Using Gate Diffusion Input
venue: 2020 IEEE 15th International Conference on Solid State Integrated Circuit Technology (ICSICT)
year: 2020