Query: Process improvement in semiconductor

Candidate papers:

abstract: New design for a certain issue in semiconductor industry is another way to modify the standard configuration into specified limit or to make a possible solution of the problem. This paper presents a new modified design for wirebond top plate with a bias platform structure that will maintain a consistent second bond into a leadframe leads with half etch configuration on quad flat no leads (QFN) packages especially in wirebond process. This paper used a side by side comparison to proof that the new design is better than the older design. With the new specialized wire clamp and top plate design, parts per million (PPM) level performances is improved by almost 90%
author_names: Jonathan C Pulido

Frederick Ray I Gomez

Edwin M Graycochea Jr
title: Wirebond Process Improvement with Enhanced Stand off Bias Wire Clamp and Top Plate
year: 2020

abstract: Overall Equipment Effectiveness (OEE) is an effective tool in identifying bottleneck. It can be integrated with other continuous improvement tools and techniques. OEE has been utilized through Lean Six Sigma DMAIC and the resulting framework is applied to a bottleneck process for a multi national semiconductor company in the Philippines. The conceptual framework covered the integration of various approaches proven by related studies such as Total Productive Maintenance (TPM) FMEA, Visual Management, Mistake Proofing, Single Minute Exchange of Dies (SMED) and DOE. Results showed that Overall OEE increased from 68% to 87% which indicated a 30% improvement. In terms of Hit Rate, it increased from 35% to 66% which is a 25% improvement. The highest improvement contributor is from the Performance component equivalent to a 24% improvement in OEE and 67% improvement in Hit Rate. The conceptual framework derived from this study can be a guide in improving bottleneck processes for similar industries.
author_names: Yogi Tri Prasetyo

Felix Concepcion Veroya
title: An Application of Overall Equipment Effectiveness (OEE) for Minimizing the Bottleneck Process in Semiconductor Industry
venue: 2020 IEEE 7th International Conference on Industrial Engineering and Applications (ICIEA)
year: 2020

abstract: The preparation process of indium oxide semiconductor nanomaterials was improved gradually, and ultimately, ordered In 2 O 3 fibers with hollow structure were successfully synthesized by electrospinning method with a special made collector. Compared with the other samples, the ordered sample has the biggest specific surface area, the minimum grain size, and the minimum conduction resistance. So it also has the best gas sensitivity, which is more than twice that of other samples.
author_names: Chao Shi

Yabo Zhu

Qijie Xu

Nao Zhang

Tingting Xie

Zhongbing Wang

Heliang Fan
title: Morphology modulation and gas sensitivity improvement of indium oxide semiconductor nanomaterials
venue: Journal of Materials Science: Materials in Electronics
year: 2020

abstract: Cycle time for a product is one of the key performance indicators in semiconductor manufacturing. Reduction of cycle time will shorten product time to market, increase throughput, reduce operational cost and develop customer trust. Semiconductor manufacturing that process 40,000 to 50,000 work in progresses (WIP) usually takes 50 to 70 days, 300 to 400 equipments and 300 to 900 steps to complete. Thus, any task related to manual data collection to make indices reports or analysis usually needs high resources requirements to spend for manual work and risk for mistake. In the modern facility of semiconductor fabrication, a system like Manufacturing Execution Systems (MES) was implemented to ease the process and operation traceability. The information is well kept in the appropriate databases. Many applications then are integrated with MES database to perform indices reports. In this paper, the improve method for data collection related to cycle time improvement is introduced. In this approach, the automated systems was developed using existing Advance Productivity Family (APF) programming platform to collecting the data. The system is integrated between MES and APF to have the real time data collection and analysis. In the systems, manual data collection is replaced with respective automated data transfer from real situation in the manufacturing environment. This program then able to shows real root caused with proper relational charting to display real problem for engineering to prioritize and resolve respectively. As a result, 39% reduction of cycle time gained by implementing this technique. The system has successfully implemented and supports the cycle time reduction.
author_names: Syahril Ridzuan Ab Rahim

Ibrahim Ahmad

Mohd Azizi Chik
title: Technique to improve visibility for cycle time improvement in semiconductor manufacturing
venue: 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)
year: 2012

abstract: The developments in lithography of ASML have increased the complexity of their machines and the replacement of some parts has become a very hard task for engineers. The different processes within engineering, logistics and the local office at the customer factory are not lean and can be optimized. Following the 8D problem solving methodology used by ASML, we deduced that the software tool that is supporting the replacement process is obsolete. Coach, which is the current software tool, is about 20 years old, and cannot support the need of a new way of working brought by the increased complexity of the machine. The main goal of the project is to provide efficient software tools to ASML engineers so that they can prepare and execute replacements of new machines' critical parts, the fastest, the easiest and the most cost effective way possible. Three alternatives to solve these problems are ranked using a Multi Criteria Analysis method. These alternatives are: Incorporate ARE (Automatic Recovery Engine) to replacements, adapt a module called SAP ME from Manufacturing Engineering department and, last, to implement an external software called Cortona 3D that uses CAD designs to create Work Instructions for the procedures. The result is that adapting SAP ME is the best alternative, and with that the goal initially set, has been properly achieved. The collaboration of experts in the field of this project was essential to reach them. It is a profitable solution in 4 years long and its implementation will give high benefits such as time saving as well as benefits to the customers by increasing the up time of the machine. Sensibility analysis proves that it is a robust solution, but it is not feasible at the moment due to problems of property rights of having connectivity to ASML network at the customer factory.
author_names: Alejandro Tortras Raventos
title: Proposal of field replacement process improvement of the new lithography machine in the semiconductor industry
year: 2013

abstract: Laser induced forward transfer (LIFT) has been used to deposit pixels of an organic semiconductor, distyryl quaterthiophenes (DS4T) The dynamics of the process have been investigated by shadowgraphic imaging for the nanosecond (ns) and picosecond (ps) regime on a time scale from the laser iradiation to 1.5 ms. The morphology of the deposit has been studied for different conditions. Intermediate sacrificial layer of gold or triazene polymer has been used to trap the incident radiation. Its role is to protect the layer to be transferred from direct irradiation and to provide a mechanical impulse strong enough to eject the material.
author_names: Ludovic Rapp

Christophe Cibert

Sebastien Nenon

Anne-Patricia B Alloncle

Matthias Nagel

Thomas K Lippert

Christine Videlot-Ackermann

Frederic Fages

Philippe Delaporte
title: Improvement in semiconductor laser printing using a sacrificial protecting layer for organic thin film transistors fabrication
year: 2011

abstract: Semiconductor fabrication is known to be the one of the most complex manufacturing operations. This is due to total processing steps in semiconductor fabrication is as high as 1000 steps and the process will re enter through same equipments multiple times. This will always pose a challenge to the operational team to achieve goal for optimal cycle time and maximum output. One of the WIP (Work In Progress) management approach used to achieve this goal is to use the right WIP prioritization. In general, giving priority to respective WIP usually will result in faster cycle time to fulfill customer expectation. This is done by identifying specific products as priority 1 to be executed first and priority 2 next. The methodology in this research uses simulation software to configure a real 200mm semiconductor fabrication facility. The input parameters used in this analysis include technology product specification, products demand based on real market trend, manufacturing, and equipment specification and requirements. The results from this study re instate that prioritization has direct impact to the overall product cycle time and monthly wafer output. The results in this study also shows that categorizing product into two types of priorities will improve the cycle time by 2.21% and monthly wafer output will increase by 2.1% compared to when the WIP were managed by the same priority. In conclusion, this is desirable because increasing 2.1% monthly output can easily contribute to increase revenue of more than USD 4 million per year, which is vital for company's survival in this competitive business.
author_names: Puvaneswaran Balakrishna

Mohd Azizi Chik

Ibrahim Ahmad

Bashir Mohamad
title: Throughput improvement in semiconductor fabrication for 0.13mm technology
venue: 2011 IEEE Regional Symposium on Micro and Nano Electronics
year: 2011

abstract: We present a capacitorless one transistor dynamic random access memory (1T DRAM) based on a Si/SiGe heterojunction double gate MOSFET. In the proposed 1T DRAM, the program process is based on band to band tunneling (BTBT) between gate 1 and gate 2 regions, and a sensing margin is defined by the amount of excess holes stored in the SiGe body region. Therefore, the sensing margin and retention time were affected by SiGe in the body region. The BTBT rate, enhanced by the small band gap energy in SiGe, increased the sensing margin. The Si/SiGe heterojunction between the source/drain and body regions formed a potential barrier for hole carriers. The retention time was improved by suppressing the diffusion of hole carriers in the floating body storage node. In addition, the retention characteristic was also enhanced by applying a gate underlap structure, which significantly reduced the electric field induced recombination rate. The optimized device with a Si0.7Ge0.3 body and underlap length (Lunderlap) of 5 nm exhibited a high sensing margin of 6.16 uA/um and long retention time of 131 ms at a high temperature of 358 K.
author_names: Young Jun Yoon

Min Su Cho

Bo Gyeong Kim

Jae Hwa Seo

In Man Kang
title: Capacitorless One Transistor Dynamic Random Access Memory Based on Double Gate Metal Oxide Semiconductor Field Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time.
venue: Journal of nanoscience and nanotechnology
year: 2019

abstract: New and upcoming semiconductor devices and technologies are getting more challenging in assembly manufacturing process due to many factors such as complex package layout, process capability and critical bill of materials. This paper focused on the mitigation of the top major assembly reject of a semiconductor sensor device, that is the wire to wire shorting issue at wirebonding process. Parameter optimization particularly the looping segment 1 parameter, as well as using a reverse stitch on ball (RSOB) were employed to eliminate the wire to wire defect in wirebonding process. Finally, with the process optimization and improvement, a reduction of 98 percent wire to wire shorting occurrence was attained.
author_names: Anthony R Moreno

Edwin M Graycochea Jr

Frederick Ray I Gomez
title: Wire Shorting Elimination through Wirebond Process Optimization of Semiconductor Sensor Device
year: 2020

abstract: A gallium nitride (GaN) based normally off metal oxide semiconductor field effect transistor (MOSFET) using a dual metal gate (DMG) structure was proposed and fabricated to improve current drivability. Normally off operation with a high Vth of 2.3 V was obtained using a Cl2/BCl3 based recess etching process. The DMG structure was employed to improve current characteristics, which can be degraded by recess etching. The ID and gm of a DMG based device with nickel (Ni) aluminum (Al) were improved by 42.1% and 30.9% respectively, in comparison to the performances of a single metal gate based device with Ni because the DMG structure increased electron velocity in the channel region. This demonstrates that the DMG structure with a large work function difference significantly improves the carrier transport efficiency. GaN based recessed gate MOSFETs based on the DMG structure hold promising potentials for high efficiency power devices.
author_names: Young Jun Yoon

Jae Sang Lee

Dong-Seok Kim

Jung-Hee Lee

In Man Kang
title: Gallium Nitride Normally Off MOSFET Using Dual Metal Gate Structure for the Improvement in Current Drivability
year: 2020