Query: Quick reference manual for silicon integrated circuit technology

Candidate papers:

abstract: Physical Constants Physical Properties Basic Expressions Measurements Chemical Recipes Diffusion Ion Implantation Process Data IC Structures and Wafer Properties Conductivity of Diffused Layers Properties of p n Junctions Metal Semiconductor Junctions Surface Properties MOS Reliability Index.
author_names: W E Beadle

Joseph C C Tsai

R D Plummer
title: Quick reference manual for silicon integrated circuit technology
year: 1985

author_names: Arthur Kenneth Covington
title: Quick Reference Manual for Silicon Integrated circuit Technology
year: 1986

author_names: H A Kemhadjian
title: Book review: Quick Reference Manual for Silicon Integrated Circuit Technology
year: 1986

abstract: Integrated silicon photonics is an exciting emerging technology, utilizing the high bandwidth and high timing resolution that optics provides in many applications. To maximize the benefits of these optical electrical systems, tight integration of the electronic and photonic components are necessary. In light of this need, we've developed a Cadence toolkit library written in VerilogA that simulates both the amplitude and phase of optical signals, as well as optical electrical interactions. The runtime is greatly improved by simulating the optical signal relative to a reference frequency, which is chosen to be close to the frequency range of interest. We have identified a set of fundamental photonic components, and described each at the physical level, such that the characteristics of a composite device will be created organically. We show that the simulated results match analytic solutions for simple devices like resonant ring filters and more complicated devices like single sideband modulators. Adding to this toolkit library, we then discuss devices that are required for handling more special cases, such as chromatic dispersion in the waveguide, and non ideal optoelectronic devices. Finally, we demonstrate simulations of complicated systems such as WDM links and Pound Drever Hall loops. This will allow designers to unify our photonic device designing and modeling environment with circuit and system level design, giving us greater insight on the trade offs that take place between the two realms.
author_names: Jonathan Leu
title: Integrated silicon photonic circuit simulation
year: 2018

abstract: In this paper, the design of a RF MEMS oscillator on a silicon ceramic composite substrate using a high Q Lamb wave resonator as frequency selective device is described. The MEMS resonator is designed on a 1.8 mm thick piezoelectric AlN layer, deposited on silicon using thin film processes. The finite element simulation results of the resonator structure are presented, and the derivation of the electrical equivalent circuit is described. The active part of the MEMS oscillator, which was laid out in a Pierce topology, has been integrated in an application specific integrated circuit fabricated in CMOS technology. Both, amplifying and frequency selective parts are hybrid integrated on a unique silicon ceramic composite substrate, which enables a very compact high quality module design with minimal parasitics. The MEMS oscillator serves as a technology demonstrator combining the advantages of microelectronic and microelectromechanical components towards a compact and power efficient hybrid technology, e.g. for mobile communications or wireless sensors.
author_names: Johannes Stegner

Uwe Stehr

Dmitry Podoskin

Sebastian Gropp

Michael Fischer

Martin Hoffmann

Jens Muller

Matthias A Hein
title: Hybrid integrated RF MEMS based reference oscillator using a silicon ceramic composite substrate
venue: 2016 German Microwave Conference (GeMiC)
year: 2016

abstract: Silicon Carbide is a promising wide bandgap material and gradually becoming the first choice of semiconductor for high density and high efficiency power electronics in medium voltage range (500 1500V) SiC has also excellent thermal conductivity and the devices fabricated with the material can operate at high temperature 400 0 C) Thus, a power electronic system built with SiC devices requires less cooling requirement and saves board space and cost. The high temperature applications of SiC material can also be extended to space exploration, oil and gas rigging, aerospace and geothermal energy systems for data acquisition, sensing and instrumentation and power conditioning and conversion. But the high temperature capability of SiC can only be utilized when the integrated circuits can be designed in SiC technology and high fidelity compact models of the semiconductor devices are a priori for reliable and high yielding integrated circuit design. The objective of this work is to develop industry standard compact models for SiC NMOS and PMOS devices. A widely used compact model used in silicon industry called BSIM3V3 is adopted as a foundation to build the model for SiC MOSFET. The models optimized with the builtin HSPICE BSIM3V3.3 were used for circuit design in one tape out but BSIM3V3 was found to be inadequate to model all of the characteristics of SiC MOSFET due to the presence of interface trapped charge. In the second tape out, the models for SiC NMOS and PMOS were optimized based on the built in HSPICE BSIM4V6.5 and a number of functioning circuits which have been published in reputed journal and conference were designed based on the models. Although BSIM4 is an enhanced version of BSIM3V3, it also could not model a few deviant SiC MOSFET characteristics such as body effect, soft saturation etc. The new model developed for SiC NMOS and PMOS based on BSIM4V7.0 is called BSIM4SIC and can model the entire range of device characteristics of the devices. The BSIM4SIC models are validated with a wide range of measured data and verified using the models in the simulation of numerous circuits such as op amp, comparator, linear regulator, reference and ADC/DAC.
author_names: Shamim Ahmed
title: Modeling and Validation of 4H SiC Low Voltage MOSFETs for Integrated Circuit Design
year: 2017

abstract: Abstract Manipulation of nanostructures is difficult, making it tough to fabricate nano device, let alone the fabrication of integrated nano sensor. In this paper, a monolithically integrated H 2 nano sensor array on a GaN honeycomb nanonetwork (GaN HN) are proposed and realized by combining GaN HN MBE growth with standard silicon micromachining techniques. For each H 2 nano sensor unit, a H 2 sensing element, a reference sensor, a micro heater, a resistive temperature detector (RTD) and the current circuit are integrated on a single chip. The H 2 sensing element Pt/GaN HN Schottky diode was well fabricated on the suspended GaN HN with 20 nm out of plane deformation and 0.0016 mm 1 curvature. An Au/GaN HN Schottky diode is proposed as the reference sensor and it is effective to reduce the output signal shift caused by ambient fluctuation to 20% Moreover, the micro heater on the free standing GaN HN has high heating efficiency with fast heating and cooling time (2.3 ms and 2.5 ms, respectively) In addition, the performance of H 2 nano sensor unit at room temperature and at 75 degC heated by the integrated micro heater with low power of 5.8 mW was recorded and discussed. At 75 degC, the response time t res and the recovery time t rec of the integrated H 2 sensor are significantly shortened by a factor of 3.
author_names: Aihua Zhong

Takashi Sasaki

Ping Fan

Dong-ping Zhang

Jingting Luo

Kazuhiro Hane
title: Integrated H2 nano sensor array on GaN honeycomb nanonetwork fabricated by MEMS based technology
year: 2018

abstract: The last two decades has witnessed the CMOS processes and design techniques to develop and prosper with unprecedented speed. It has been widely employed in contemporary integrated circuit (IC) commercial products resulting in highly added value. Tremendous efforts have been devoted to extend and optimize the CMOS process and its application into future wireless communication systems. Meanwhile, the last twenty years have also seen the fast booming of the wireless communication technology typically characterized by the mobile communication technology, WLAN technology, WPAN technology, and etc. Nowadays, the spectral resource is getting increasingly scarce particularly over the frequency from 0.7 to 6 GHz, whether the employed frequency band is licensed or not. To combat this dilemma, the ultra wideband (UWB) technology emerges to provide a promising solution for short range wireless communication while using an unlicensed wide band in an overlay manner. Another trend of obtaining more spectrum is moving upwards to higher frequency bands. The WiFi Alliance has already developed a certification program of the 60 GHz band. On the other side, millimeter wave (mmWave) frequency bands such as 28 GHz, 38 GHz, and 71 GHz are likely to be licensed for next generation wireless communication networks. This new trend poses both a challenge and opportunity for the mmWave integrated circuits design. This thesis combines the state of the art IC and hardware technologies and design techniques to implement and propose the UWB and 5G prototyping systems. First of all, by giving a thorough analysis of a transmitted reference pulse cluster (TRPC) scheme and mathematical modeling, a TRPC UWB transceiver structure is proposed and its features and specifications are derived. Following that, the detailed design, fabrication and verification of the TRPC UWB transmitter front end and wideband voltage controlled oscillators (VCOs) in CMOS process is presented. The TRPC UWB transmitter demonstrates a starte of the art energy efficiency of 48 pJ/pulse. Secondly, a novel system architecture named distributed phased array based MIMO (DPA MIMO) is proposed as a solution to overcome design challenges for the future 5G cellular UE design. In addition, a prototyping design of on chip mmWave antenna with radiation efficiency enhancement is presented for the IEEE 802.11ad application. Furthermore, two wideband K band VCO prototypes based on two different topologies are designed and fabricated in a standard CMOS process. They both show good performance at center frequency of 22.3 and 26.1 GHz. Finally, two CMOS mmWave VCO prototypes working at the potential future 5G frequency bands are presented with measurement results.
author_names: Yiming Huo
title: Integrated silicon technology and hardware design techniques for ultra wideband and next generation wireless systems
year: 2017

abstract: (NOTE: Chapters 3 11 include an Introduction, Historical Development and Basic Concepts, Manufacturing Methods and Equipment, Measurement Methods, Models and Simulation, Limits and Future Trends in Technologies and Models, Summary of Key Ideas, References, and Problems. 1. Introduction and Historical Perspective. Introduction. Integrated Circuits and the Planar Process Key Inventions That Made It All Possible. Semiconductors. Semiconductor Devices. Semiconductor Circuit Families. Modern Scientific Discovery Experiments, Theory and Computer Simulation. The Plan for This Book. 2. Modern CMOS Technology. CMOS Process Flow. 3. Crystal Growth, Wafer Fabrication and Basic Properties of Silicon Wafers. 4. Semiconductor Manufacturing Clean Rooms, Wafer Cleaning and Gettering. 5. Lithography. 6. Thermal Oxidation and the Si/SiO2 Interface. 7. Dopant Diffusion. 8. Ion Implantation. 9. Thin Film Deposition. 10. Etching. 11. Backend Technology.
author_names: James D Plummer

Michael D Deal

Peter B Griffin
title: Silicon VLSI Technology: Fundamentals, Practice, and Modeling
year: 2020

abstract: During post silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs. Bug localization involves identification of a bug trace (a sequence of inputs that activates and detects the bug) and a hardware design block where the bug is located. Existing bug localization practices during post silicon validation are mostly manual and ad hoc, and, hence, extremely expensive and time consuming. This is particularly true for subtle electrical bugs caused by unexpected interactions between a design and its electrical state. We present E QED, a new approach that automatically localizes electrical bugs during post silicon validation. Our results on the OpenSPARC T2, an open source 500 million transistor multicore chip design, demonstrate the effectiveness and practicality of E QED: starting with a failed post silicon test, in a few hours (9 h on average) we can automatically narrow the location of the bug to (the fan in logic cone of) a handful of candidate flip flops (18 flip flops on average for a design with ~1 Million flip flops) and also obtain the corresponding bug trace. The area impact of E QED is ~2.5% In contrast, determining this same information might take weeks (or even months) of mostly manual work using traditional approaches.
author_names: Eshan Singh

Clark W Barrett

Subhasish Mitra
title: E QED: Electrical Bug Localization During Post silicon Validation Enabled by Quick Error Detection and Formal Methods
venue: CAV
year: 2017