Query: A New Robust Design of Dual-Rail Checker in QCA Technology, Capable of Testing of Digital Electronics Circuit

Candidate papers:

abstract: As metal oxide semiconductor (MOS) based devices and circuits faces glowingly physical barriers down the popularity and some constraints such as limitation of scaling, short channel effect, and hot carrier effect, so innovative technique for the synthesis of circuits in Nano scale have been developed to raise the popularity of computing. These Nano computing techniques have shown good performance in term of speed, area and integration density. This article is devoted to the robust architecture of dual rail checker using the co planar technique in QCA Designer tool. These designs are of concern to modern testing approach. These circuits are also included a modern approach for physical implementation such as Quantum Dot cellular automata. The main concern of this article is on the synthesis of nano computing testing circuit in QCA. The interest of this article is not only synthesis aspects it covers the physical implementation aspect also. Dual rail checker is an inherent module of the testing digital logic circuit. High device density happens to be an important factor in the synthesis of the Dual rail checker. The article proposed a robust architecture of Dual rail checker using QCA Technology, which consumes a less number of quantum cell and latency. To tackle the fault during the computing, we have synthesis a novel dual rail checker design for 4 dot, 2 electron based QCA architecture via co planar technique.
author_names: D Kiran Kumar

Vijay Shankar

K Vittal
title: A New Robust Design of Dual Rail Checker in QCA Technology, Capable of Testing of Digital Electronics Circuit
venue: 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT)
year: 2019

abstract: "In contemporary electronics 80% of a chip may perform digital functions but the 20% of analog functions may take 80% of the development time." [1] Aggravating this, the demands on analog design is increasing with rapid technology scaling. Most designs have moved away from analog to digital domains, where possible, however, interacting with the environment will always require analog to digital data conversion. Adding to this problem, the number of sensors used in consumer and industry related products are rapidly increasing. Designers of ADCs are dealing with this problem in several ways, the most important is the migration towards digital designs and time domain techniques. Time to Digital Converters (TDC) are becoming increasingly popular for robust signal processing. Biological neurons make use of spikes, which carry spike timing information and will not be affected by the problems related to technology scaling. Neuromorphic ADCs still remain exotic with few implementations in sub micron technologies Table 2.7. Even among these few designs, the strengths of biological neurons are rarely exploited. From a previous work [2] LUCOS, a high dynamic range image sensor, the efficiency of spike processing has been validated. The ideas from this work can be generalized to make a highly effective sensor signal conditioning system, which carries the promise to be robust to technology scaling. The goal of this work is to create a novel spiking neural ADC as a novel form of a Multi Sensor Signal Conditioning and Conversion system, which Will be able to interface with or be a part of a System on Chip with traditional analog or advanced digital components. Will have a graceful degradation. Will be robust to noise and jitter related problems. Will be able to learn and adapt to static errors and dynamic errors. Will be capable of self repair, self monitoring and self calibration Sensory systems in humans and other animals analyze the environment using several techniques. These techniques have been evolved and perfected to help the animal sur vive. Different animals specialize in different sense organs, however, the peripheral neural network architectures remain similar among various animal species with few ex ceptions. While there are many biological sensing techniques present, most popularly used engineering techniques are based on intensity detection, frequency detection, and edge detection. These techniques are used with traditional analog processing (e.g. colorvi sensors using filters) and with biological techniques (e.g. LUCOS chip [2] The local ization capability of animals has never been fully utilized. One of the most important capabilities for animals, vertebrates or invertebrates, is the capability for localization. The object of localization can be predator, prey, sources of water, or food. Since these are basic necessities for survival, they evolve much faster due to the survival of the fittest. In fact, localization capabilities, even if the sensors are different, have convergently evolved to have same processing methods (coincidence detection) in their peripheral neurons (for e.g. forked tongue of a snake, antennae of a cockroach, acoustic localization in fishes and mammals) This convergent evolution increases the validity of the technique. In this work, localization concepts based on acoustic localization and tropotaxis are investigated and employed for creation of novel ADCs. Unlike intensity and frequency detection, which are not linear (for e.g. eyes saturate in bright light, loose color perception in low light) localization is inherently linear. This is mainly because the accurate localization of predator or prey can be the difference between life and death for an animal. Figure 1 visually explains the ADC concept proposed in this work. This has two parts. (1) Sensor to Spike(time) Conversion (SSC) (2) Spike(time) to Digital Conversion(SDC) Both of the structures have been designed with models of biological neurons. The combination of these two structures is called SSDC. To efficiently implement the proposed concept, a comparison of several biological neural models is made and two models are shortlisted. Various synapse structures are also studied. From this study, Leaky Integrate and Fire neuron (LIF) is chosen since it fulfills all the requirements of the proposed structure. The analog neuron and synapse designs from Indiveri et. al. [3] [4] were taken, and simulations were conducted using cadence and the behavioral equivalence with biological counterpart was checked. The LIF neuron had features, that were not required for the proposed approach. A simple LIF neuron stripped of these features and was designed to be as fast as allowed by the technology. The SDC was designed with the neural building blocks and the delays were designed using buffer chains. This SDC converts incoming Time Interval Code (TIC) to sparse place coding using coincidence detection. Coincidence detection is a property of spiking neurons, which is a time domain equivalent of a Gaussian Kernel. The SDC is designed to have an online reconfigurable Gaussian kernel width, weight, threshold, and refractory period. The advantage of sparse place codes, which contain rank order coding wasvii Figure 1: ADC as a localization problem (right) Jeffress model of sound localization visualized (left) The values t 1 and t 2 indicate the time taken from the source to s1 and s2 respectively. described in our work [5] A time based winner take all circuit with memory was created based on a previous work [6] for reading out of sparse place codes asynchronously. The SSC was also initially designed with the same building blocks. Additionally, a differential synapse was designed for better SSC. The sensor element considered wasviii a Wheatstone full bridge AMR sensor AFF755 from Sensitec GmbH. A reconfigurable version of the synapse was also designed for a more generic sensor interface. The first prototype chip SSDCa was designed with 257 modules of coincidence detectors realizing the SDC and the SSC. Since the spike times are the most important information, the spikes can be treated as digital pulses. This provides the capability for digital communication between analog modules. This creates a lot of freedom for use of digital processing between the discussed analog modules. This advantage is fully exploited in the design of SSDCa. Three SSC modules are multiplexed to the SDC. These SSC modules also provide outputs from the chip simultaneously. A rising edge detecting fixed pulse width generation circuit is used to create pulses that are best suited for efficient performance of the SDC. The delay lines are made reconfigurable to increase robustness and modify the span of the SDC. The readout technique used in the first prototype is a relatively slow but safe shift register. It is used to analyze the characteristics of the core work. This will be replaced by faster alternatives discussed in the work. The area of the chip is 8.5 mm 2 It has a sampling rate from DC to 150 kHz. It has a resolution from 8 bit to 13 bit. It has 28,200 transistors on the chip. It has been designed in 350 nm CMOS technology from ams. The chip has been manufactured and tested with a sampling rate of 10 kHz and a theoretical resolution of 8 bits. However, due to the limitations of our Time Interval Generator, we are able to confirm for only 4 bits of resolution. The key novel contributions of this work are Neuromorphic implementation of AD conversion as a localization problem based on sound localization and tropotaxis concepts found in nature. Coincidence detection with sparse place coding to enhance resolution. Graceful degradation without redundant elements, inherent robustness to noise, which helps in scaling of technologies Amenable to local adaptation and self x features. Conceptual goals have all been fulfilled, with the exception of adaptation. The feasibility for local adaptation has been shown with promising results and further investigation is required for future work. This thesis work acts as a baseline, paving the way for R&D in a new direction. The chip design has used 350 nm ams hitkit as a vehicle to prove the functionality of the core concept. The concept can be easily ported to present aggressively scaled technologies and future technologies.
author_names: K N Subramanyam

Aniruddha Chandra
title: Conception and First Implementation of Novel Sensory Signal Conditioning and Digital Conversion Electronics Based on Spiking Neuron Ensembles for Inherently Robust Processing in Aggressively Scaled Integration Technologies
year: 2017

abstract: Quantum dot cellular automata (QCA) is the beginning of novel technology and is capable of an appropriate substitute for orthodox semiconductor transistor technology in the nanoscale extent. A competent adder and subtractor circuit can perform a substantial function in devising arithmetic circuits. The future age of digital techniques will exercise QCA as preferred nanotechnology. The QCA computational procedures will be simplified with an effective full adder and subtractor circuit. The deficiencies of variations and assembly still endure as a setback in QCA based outlines, and being capricious and inclined to error is the limitation of these circuits. In this study, a new full adder and subtractor design using unique 3 input XOR gate with cells redundancy is proposed. This designs can be utilized to form different expedient QCA layouts. The structures are formed in a single layer deprived of cross wiring. Besides, this study is directed to the analysis of the functionality and energy depletion possessions of the outlined full adder and subtractor circuits. For the first time, QCADesigner Energy (QD E) version 2.0.3 tool is utilized to find the overall depleted energy. The attained effects with QCADesigner have verified that the outlined design has enhanced functioning in terms of intricacy, extent, and latency in contrast to the earlier designs. Moreover, the redundant form of full adder and subtractor has uncomplicated and robust arrangement competing typical styles.
author_names: Ali Newaz Bahar
title: An Architecture of 2 Dimensional 4 Dot 2 Electron QCA Full Adder and Subtractor with Energy Dissipation Study
year: 2018

abstract: In today's budgetary environment, there is significant interest within the National Aeronautics and Space Administration (NASA) to enable small robotic science missions that can be executed faster and cheaper than previous larger missions. To help achieve this, focus has shifted from using exclusively radiationtolerant or radiation hardened parts to using more commercial off the shelf (COTS) components for NASA small satellite missions that can last at least one year in orbit. However, there are some portions of a spacecraft's avionics, such as the Command and Data Handling (C&DH) subsystem and the Power System Electronics (PSE) that need to have a higher level of reliability that goes beyond what is attainable with currently available COTS parts. While there are a number of COTS components that can withstand a total ionizing dose (TID) of tens or hundreds of kilorads, there is still a great deal of concern about tolerance to and mitigation of single event effects (SEE) The Goddard Modular SmallSat Architecture (GMSA) is an initiative at NASA Goddard Space Flight Center (GSFC) to address these radiation tolerance and reliability issues, while also minimizing development cost and schedule. The goal of GMSA is to develop a highly reliable, modular, flexible, and extensible small satellite implementation approach that can incorporate spacecraft components and subsystems that either developed within NASA or procured from industry. This paper provides details of a new technology development effort that will implement a miniaturized C&DH and PSE within a 6U (10cm x 20cm x 30cm) satellite. This effort has a goal of enabling ambitious science missions using SmallSats that can operate for longer durations in harsher environments than can be achieved with existing SmallSat technologies. The GMSA PSE uses Direct Energy Transfer (DET) topology with the battery connected directly to the bus. The shunt control technique is a linear sequential full shunt which provides a simple solar array interface and can support both 3 axis stabilized and spinner satellites. The PSE includes all the circuits needed to perform telemetry and command functions using an I2C interface with the C&DH. In addition, the PSE has been designed, tested, and verified to meet launcher vehicle safety requirement. The GMSA C&DH functionality is implemented as a SmallSat Common Electronics Board (SCEB) and an Adapter Board. The SCEB can be configured to implement a variety of serial communication interfaces including RS 422, I2C, SPI, and SpaceWire. There are also a number of available general purpose input/output (GPIO) signals. The SCEB includes a reprogrammable FPGA that contains a soft core processor running flight software (FSW) based on NASA GSFC's Core Flight System (cFS) Lastly, the SCEB interfaces with an Adapter Board that contains the analog circuitry that converts temperature, voltage, and current data collected from multiple points within 6U satellite to a digital format that can be processed, stored, and downlinked using the front end communication interface.
author_names: Hanson Cao Nguyen

James Fraction
title: Robust, Radiation Tolerant Command and Data Handling and Power System Electronics for SmallSats
year: 2018

abstract: Binary Decision Diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits and other applications like security, shape analysis of geometric objects etc. In this work, we have reported a new BDD based approach for the synthesis of dual rail adiabatic MUX circuits, which works much better in low frequency application. For high frequency application the best dual rail logic for BDD based synthesis is Dynamic Cascode Voltage Switch with Pass Gate (DCVSPG) logic, which we have used as library cell and made logic synthesis more optimized in area and power. As technology mapping has become significant in reducing chip area in terms of number of logical block we have also introduced an efficient mapping algorithm which can map single rail logic cells like LEAP (Lean Integration with Pass Transistors) cells from BDD for better optimization in terms of area, power and delay. Testing of such VLSI circuits is another challenge for chip manufacturer. ATPG (Automatic Test Pattern Generator) is ruling this sector for many years. But circuit realized from special type of graph like BDD an alternative to ATPG can be employed to find test vectors for optimum fault coverage. In this work, we consider the open problem of generating in polynomial time, the exact minimum set of test vectors for detecting all single stuck at faults in such a BDD based circuit synthesized with multiplexers. This procedure not only generates the optimal test set in polynomial time, but also obviates the need of employing an ATPG and a fault simulator. We have also reported a simple algorithm for determining the maximum independent set of edges of a BDD that has got direct relation for finding optimal stuck at fault test set in a BDD based circuit. We have also considered how to detect stuck at faults when circuit is ON. For this we have reported a BDD based methodology for designing low power and low area online testing (OLT) device which can efficiently detect all the stuck at faults in smaller cycle time. Next, in this work, we have designed a BDD based asynchronous adder that obviates the need of complex ASIC flow. Also, the design takes much less area and power compared to the design with other standard library cell. We have also shown that a slight modification of such circuit can be made secure from external attack like side channel attack (SCA) For both the designs we have achieved a significant amount of reduction in area and power compared to the contemporary designs. We have successfully taped out these chips using TSMC fabrication unit. Another application of BDD on security has been proposed in the area of internet firewall design. We have implemented a BDD based packet filter firewall which is robust and more efficient than the existing list based packet filter firewall system.
author_names: Ajit Pal

Bhargab B Bhattacharya

Gopal Paul
title: Studies in logic synthesis, testing, and security issues of digital circuits based on binary decision diagrams
year: 2011

abstract: With the scaling of CMOS technology slowly coming to a halt due to quantum mechanics effects progressively eroding its performance as transistor dimensions shrink, new and experimental technologies for digital circuits are being explored and prototyped with increased effort. Design tools for such technologies have been created for these purposes and their development and refinement is now more critical than ever. ToPoliNano, developed by the VLSI group of the Polytechnic University of Turin, is one such tool, dedicated to the design and simulation of digital circuits built with nanomagnetic technologies based on Magnetic QCA. A robust EDA tool by itself with an easy to use GUI, it only missed, with regards to the more established professional software available to circuit designers that work with CMOS technology, the flexibility of a dual GUI/command line offering. The aim of this Master's thesis consisted therefore of expanding the capabilities of ToPoliNano by equipping it with a text based workflow, allowing users to access the program's powerful features by means of text commands and automation scripts. In order to bring the aforementioned text based workflow to life, three software modules have been developed in succession as part of the thesis, each complementing the others: a command line interface (CLI) able to tokenize, parse and interpret a variety of text commands mapped to the functionalities of ToPoliNano (for example: layout generation, layout import/export, circuit simulation, etc. a new general purpose preprocessor capable of processing variables, loops and conditional statements, which unlocks the possibility of writing complex scripts that go beyond a simple list of commands; a console mode (loaded into terminal) referred to as no GUI mode, which directly interfaces the user with the CLI (and, by extension, to ToPoliNano) without the need to load the GUI (which also allows the user to interact with the CLI but via widgets included in the graphical interface) As the final part of the thesis, a comprehensive user manual was written illustrating the purpose of each supported text command, the structure of the command line workflow and the advanced scripting features available to the user, including a collection of example scripts to help the user gain a complete, in depth understanding of the new instruments at their disposal for designing digital circuits.
author_names: Francesco Russo
title: CAD Tools for Emerging Nanotechnologies
year: 2019

abstract: Abstract In this paper we will present the design status of the Digital Front End Electronic system (DFEE) that will be used for the EUSO photon detector. The DFEE is able to count the single photoelectrons coming form the detector for a given time period, store the numbers in a memory buffer and read them out after a trigger, using a serial communication line. Because of space, mass and power consumption constraints, the system will be implemented in an ASIC using a deep submicron technology. The actual design follows the original ideas of the system, though adding several new functionalities. A fully functional prototype chip has been submitted for fabrication in fall 2002. Extensive tests will be performed on it both with bench instrumentations and with the real sensor (the multi anode photomultiplier Hamamatsu R7600 M64) expecting significant results by early Summer 2003. Future work is needed to convert the design into a more robust RAD hard technology, suitable for space applications and to include in the final die an additional circuit used to optimize the performances at high photons rates: the Analog Front End Electronics (AFEE) Moreover the base board used to house the multi anode photomultipliers is presented: it is the back bone of the microcell and will be the basic block used to build up the EUSO focal surface.
author_names: Paolo Musico

Marco Pallavicini

Alessandro Petrolini

Fernando Angulo Pratolongo
title: Digital front end electronics design for the EUSO photon detector
year: 2003

abstract: Quantum Cellular Automata (QCA) has been widely used to digital circuits and systems in recent years. QCA technology is a promising alternative to CMOS technology, which offers a novel electronics paradigm for information processing and communication. It has the attractive features such as faster speed, higher scale integration, smaller size and lower power consumption than transistor technology. Previously, adder designs based on conventional designs were examined for implementation by QCA technology. A briefness cell is used as the basic element, which is a building block to construct gates and wires. In this paper, we propose two kinds of new adder designs based on QCA. One is full adder, and the other is carry look ahead half adder. The simulation results show that the adder designs we proposed are more robust and reliable compared with previous works in the aspects of complexity, area, crossing and delay.
author_names: Airong Nie

Ping Fan
title: Novel Adder Design Using Quantum Cellular Automata Implementation
year: 2017

abstract: Continuing increases in both the size and complexity of digital signal processing (DSP) systems places a considerable demand on the design engineer to develop hardware architectures capable of fulfilling the growing functional requirements expected of modem DSP devices. Automated circuit design techniques provide the design engineer with a tool to more effectively generate high performance signal processors capable of meeting demanding specifications. Evolvable hardware (El lW) is a relatively new approach to automated circuit design which utilises advances in reconfigurable hardware technology and the power of modem micro processors to generate circuits based on the principles of natural selection and evolution. This thesis investigates the suitability of software biased and hardware oriented programmable platforms, configured via EHW, and tailored for the automated design of high performance DSP circuits. Performance criteria such as timing, area and circuit robustness are considered. A number of benchmarked DSP circuits were initially considered. It was shown that by using larger functional logic macros as building blocks El lW is more successful at generating circuit solutions than if only gate primitives are used. In addition, the circuits generated are of comparable or better performance than equivalent circuits developed using a standard digital design methodology. Results also indicated that for more complex DSP functions to be generated, EHW platforms must use larger functional blocks, constrained for a specific application. Finite Impulse Response (FIR) filters were identified as the key function of many DSP applications, and the multiplication unit was targeted as the performance critical component. A novel Programmable Arithmetic Logic Unit (PALU) was therefore developed as a functional building block suitable for automated digital filter design using EHW. The PALU replaces coefficient multiplication with a series of bit shifts, additions and subtractions. Two distinct arrays of PALU were developed based on conventional FPGA and PLA re configurable hardware architectures. Results show that a PLA architecture with 2 levels of hierarchical interconnect and column based fixed tap outputs provides a platform most suited to automated filter design using the EHW technique. The PLA was also shown to be be robust to faults covering up to 25% of the array when configured using EHW. Declaration of originality I hereby declare that the research recorded in this thesis and the thesis itself was composed and originated entirely by myself in the Department of Electronics and Electrical Engineering at The University of Edinburgh.
author_names: Ben I Hounsell
title: Programmable architectures for the automated design of digital FIR filters using evolvable hardware
year: 2001

abstract: The latest phased array radar and communications systems being developed for Actively Electronically Scanned Array (AESA) 5G and Tactical communications are following trends of higher frequency operation and physical densification. With greater numbers of antenna elements, transmit/receive modules, antenna processors, and other analog/hybrid/digital beamforming modules in a single phased array antenna system, additional RF interconnect design considerations emerge. These new designs involve fitting a greater number of RF connectors and cable assemblies that also house more integrated PCBs that support analog, digital, and RF circuits. Reducing the size, weight, cost, and installation complexity of RF interconnects must also be considered. This article aims to educate engineers and industry professionals working with phased array antenna systems for radar and the new design considerations and solutions that help mitigate the challenges associated with building the next generation of phased array radar. Phased Array Radar Trends Phased array antennas, and subsequent radar and communication systems, benefit from the physics of electromagnetics, in that the size of optimized RF structures is inversely proportional to the frequency at which they operate. This means that antennas built for higher frequencies are smaller and otherwise more compact than antennas for lower frequency applications. In the case of multi element antennas, such as phased array antennas, this means that increasing the operating frequency has a dramatic impact on the size, weight, cost, and even power of these systems. There is a caveat, however, in that a variety of losses, such as RF loss and atmospheric attenuation, are also greater at higher frequencies. These additional losses can be compensated for by adding additional antenna elements in phased array radars. Moreover, incorporating active phase and amplitude control enables an operator or algorithm to precisely control the antenna pattern of a phased array antenna. In the case of AESA radars, jammers, and Tactical Communications, this ability is critical in avoiding harm to sensitive receivers, or more effectively controlling beam patterns to target enemy radar or friendly communications. This ability has given rise to a variety of actively controlled antenna techniques that allow for low probability of intercept/low probability of detection (LPI/LPD) Moreover, at higher frequencies, the beam width of an antenna becomes more narrow, enhancing the directivity over a comparable, but lower frequency, multi element antenna. These factors have given rise to the interest in using millimeter wave (mmWave) phased array antennas for radars, jammers, Tactical Communications, and upcoming mmWave 5G communications [1, 2, 3] Though the compact nature of mmWave antennas becomes attractive from a size, weight, power, and cost (SWAP C) perspective, the reduction in overall antenna size, alongside the dramatic Resources and References 1. https:/www.mwrf.com/defense/darpa launches millimeter wave program 2. https:/www.darpa.mil/program/millimeter wave digital arrays 3. https:/www.upi.com/Raytheon tapped by DARPA for high frequency digital communications research/3351541528087/ RF INTERCONNECT FOR THE NEXT GENERATION OF PHASED ARRAY RADAR AND COMMUNICATIONS belfuse.com/cinch increase in antenna elements, means that the associated RF interconnect must also be contained within these reduced size modules. High density RF interconnect, which still meet stringent MIL SPEC ruggedness requirements, are necessary to provide the interconnect between the growing diversity of transmit/receive (TR) modules, Antenna Processing Units (APUs) hybrid beamforming circuitry, and/or analog beamforming components. High quality RF interconnect that meet the SWAP C requirements of these new phased array antenna systems is essential during the prototyping, testing, and production phases, and are also key components of deployed phased array systems. With the intended use cases of mmWave 5G extending to industrial, automotive, and infrastructure applications, it is likely that many of the same ruggedization and reliability requirements used by military/aerospace markets will extend to mmWave 5G. Phased Array Radar Signal Chain A basic phased array antenna consists of RF interconnect, attenuators/amplifiers, phase shifters, and antenna elements. In this basic case, RF interconnect is needed to connect between the transmitter, receiver, circulator/isolator/ switch, attenuators/amplifier, phase shifter, and antenna elements. Another topology (that is becoming increasingly common) is the use of TR modules, which place the transmitter power amplifier (PA) and receiver low noise amplifier (LNA) in a module that is then connected through the same RF path to switches/circulators from the phase shifter to the antenna element. TR modules are used to enable the benefits of integration and modularity, further reducing the overall size of the antenna. This approach tends to require much smaller pitch and higher density RF interconnect than basic phased array antennas, as using larger RF interconnect negates many of the size and weight benefits of mmWave reduced element size. The next level of this integration is to use hybrid, or digital, beamforming phased array antenna topologies that allow for much more compact components, such as System on Chip (SoC) System in package (SiP) integrated RF frontend modules, APU ASICs, and other types of compact assemblies, modules, or ICs. Hybrid and digital beamforming enable much more compact phased array antennas and can employ high speed digital communications instead of RF communications between the modulation circuitry and the RF circuitry. In these cases, even tighter pitch and higher density RF interconnect are needed to provide connections between the high speed communication buses of the modems and the beamforming electronics. Though jammers and some lower frequency radars will require larger sized RF components and interconnect due to the power requirements of such systems, both Tactical Communications and mmWave 5G communications are likely to continue to greater levels of integration and densification. The need for this stems from reducing SWAP C parameters and enabling the deployment of massive numbers of mmWave base stations, which would otherwise be limited if the SWAP C parameters of the communication systems were comparable to radar and jammer systems. The densification of mmWave phased array antenna systems also brings into consideration the sensitivity of such a system to external and internal interference, especially when considering the high speed data lines and multitudes of low power mmWave RF interconnect inevitable in communication systems. Coaxial cable assemblies and interconnect are excellent at providing shielded communications with minimizing insertion loss and attenuation. This concept also applies to highly sophisticated radar, which uses many of the same modulation technologies (spread spectrum) as modern communications. Hence, there is, and will be, a growing need for a wide range of high density RF interconnect technologies, from ruggedized SMA cable assemblies to compact ultra miniature ganged connector modules. RF INTERCONNECT FOR THE NEXT GENERATION OF PHASED ARRAY RADAR AND COMMUNICATIONS Even with greater integration, RF interconnect is still needed for high speed digital signals and output to the antenna elements, though the interconnect will likely need to be denser. RF Interconnect Design Considerations for Phased Array Antenna Though radar, jamming, Tactical Communications, and mmWave 5G communications have very different end goals and deployment scenarios, many of the RF interconnect considerations are the same. The following sections are dedicated to discussing the top design considerations for mmWave phased array antenna systems and include application specific details and examples. Phase Stability and Phase Matched Coaxial Cable Assemblies The benefits of a phased array antenna are derived by the ability to precisely control the phase of the RF signal at the output of the antenna. This is only possible if the phase of the signal is stable and predictable throughout the phased array antenna system signal chain. There are two main RF interconnect considerations in this area. One is the phase stability of signals passing through a coaxial cable, based on environmental factors such as shock, vibration, flexure, warp, temperature, etc. Using "phase stable" coaxial cables helps to ensure that environmental influence is minimized. RF INTERCONNECT FOR THE NEXT GENERATION OF PHASED ARRAY RADAR AND COMMUNICATIONS belfuse.com/cinch The other consideration is the phase match between the coaxial cables used. Systematic phase error could be introduced by the coaxial cable production process, leading to even same length coaxial cables exhibiting variances in the phase response. Hence, using phase matched coaxial cables (which are cables ordered to have an incredibly similar phase response) can help to eliminate the concern of phase variances from RF interconnect and enhance predictability and performance of phased array antenna systems. Mechanically Robust Connections Military/aerospace manufacturers are required to use MIL SPEC coaxial cables, connectors, and assemblies, which must meet a minimum standard of ruggedness and reliability. These standards include resilience to damage from shock, vibration, thermal cycles, and environmental agents. Especially with highly sensitive phased array antenna systems operating at mmWave frequencies, mechanical reliability is essential for all mission critical RF communications, radar, and jamming. Even slight mechanical forces, if allowed to affect a phased array antenna system, could reduce overall system performance, produce hard to identify transient failures, or otherwise render the system inoperable. Many of these high r
title: RF Interconnect for the Next Generation of Phased Array Radar and Communications
year: 2019