Query: Offset free high-resolution D/A converter

Candidate papers:

abstract: The features of high resolution and high bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high resolution hybrid analog to digital converter (ADC) is proposed to meet those requirements, and a 16 bit two step pipelined successive approximation register (SAR) analog to digital converter (ADC) with first order continuous time incremental sigma delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high bandwidth two step pipelined SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal to noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator's resolution in both stages for a given power budget, compared with a conventional Pipelined SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post layout simulation results show that the proposed hybrid ADC achieves a signal to noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.
author_names: Bo Gao

Xiantao Li

Jie Sun

Jianhui Wu
title: Modeling of High Resolution Data Converter: Two Step Pipelined SAR ADC based on ISDM
year: 2020

abstract: The analog frontend (AFE) coupling circuit is a crucial processing element for data acquisition systems based on analog to digital converters (ADCs) Currently, high speed and high resolution ADCs are predominantly designed with differential input stages. Conventional high speed ADC drivers are mainly AC coupled by employing transformers (Baluns) or fully differential amplifiers (FDAs) with blocking capacitors. However, the results of this study indicate that a certain degree of DC offset error exists and manifests itself as the baseline error in the presence of power dividers connecting several DC coupled channels that implement high dynamic range (HDR) signal conditioning. The study involves a theoretical analysis and explanation of the baseline offset error. The offset error can potentially lead to unexpected out of range issues for sampling devices, including high speed ADCs and switched capacitor array ASICs. High performance FDAs are adopted, and an offset free DC coupled AFE circuit is proposed to address the aforementioned issue using two stage amplification and a resistive attenuator. The proposed methodology is verified via circuit simulations and hardware design. Thus, the baseline offset problem can be accurately solved using the proposed circuit by minimizing the neglectable error. The proposed circuit facilitates improvements in the high precision measurement of HDR signals in many nuclear physics experiments and some applications in the DC coupling scheme with FDAs involving resistive power dividers.
author_names: Yafei Du

Jun Wu

Chen Yuan

Chuanfei Zhang

Yinong Liu
title: Offset free DC coupled analog frontend circuit for high dynamic range signals
year: 2020

abstract: An arbiter based simple phase decision circuit (PDC) optimized for high resolution phase to digital converter made up of an analog phase frequency detector and a time to digital converter for all digital phase locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input to output delay than the previously reported PDC. Proposed PDC is realized using 130 nm CMOS process and demonstrated by transistor level simulations. A 5 bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic lock free and small phase offset delay locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.
author_names: Kwang-Chun Choi

Min-Hyeong Kim

Woo-Young Choi
title: An Offset and Deadzone Free Constant Resolution Phase to Digital Converter for All Digital PLLs
year: 2013

abstract: Aim Here, we describe the web based tool EpHLA Converter, a free program designed to reduce the complexity of the problem to predict high resolution HLA typing. Methods Our program allows one to determine the most probable high resolution HLA class I and II genotypes using as data input just low or medium resolution HLA A, B, C, DRB1, DRW, DQA1 and DQB1 typing and the population it came from. Allelic conversion is based on public databases (NMDP, IMGT) queries and allele frequencies determined from either reference populations or private HLA typing databases. The program was developed to run independently or to be integrated to third part programs including the recently developed EpHLA program to analyze epitopic HLA serum reactivity. We validated the EpHLAConverter to HLA class II inference by using three different approaches: (i) We determined the percentage of matched results between the 100 predicted high resolution typing with the actual high resolution typing to HLA DRB1, (ii) the concordance to predict HLA DQA1 and HLA DQB1 assignments by using NMDP published DRB1/DQB1/DQA1 associations and (iii) by computing the time spent in the conversion from medium to high resolution HLA A, B and DRB1 typing for database with more than 10,000 typings each one. Results Percentage matched predicted High Resolution vs. Actual High resolution typing for HLA DRB1 and DQB1 was 94% and 83% respectively. Besides, we showed that our tool is able to safely convert HLA typing databases with 10,000 typings HLA A, B DRB1 in 191 minutes (more than five inferences per second) The limitation of the EpHLA Converter program is if the allele DRB1 is uncommon, the association HLA DRB1/DQA1/DQB1 will not be able to be inferred because the association is not listed on the available frequencies tables. Conclusions Our data demonstrates that EpHLA Converter has an excelent accuracy rate to predict DRB1 and DRB1/DQA1/DQB1 association at high resolution level.
author_names: Jose Renato Pereira de Moura Barroso

Semiramis Jamil Hadad do Monte

Adalberto Socorro da Silva

Herton Luiz Alves Sales Filho

Anaregina S Araujo

Antonio Vanildo de Sousa Lima

Deylane Menezes Teles e Oliveira

Rubens de Sousa Santana

Marayza Gomes Carvalho

L C D da M Sousa
title: 13 P EpHLA CONVERTER: A TOOL FOR AUTOMATIC INFERENCE OF HIGH RESOLUTION HLA FOR SOLID ORGAN TRANSPLANTATION
year: 2013

abstract: The sampling rate plays a key role in wireless applications at very high frequency range. Flash analog to digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state of the art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for novel coarse and fine conversion separately. The kick back noise is also reduced by using sample and hold switches at the input. The 10 bit ADC architecture is designed with 45 nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/*C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal tonoise and distortion (SNDR) ratio and spurious free dynamic range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.
author_names: Farhana Begum

Sandeep Mishra

Anup Dandapat
title: Low Power 10 Bit Flash Analog to Digital Converter with Divide and Collate Subranging Conversion Scheme
year: 2019

abstract: An offset free switched capacitor gain stage is described. By combining the gain stage with a binary weighted capacitor array, a D/A converter is obtained. A cascaded design of an offset free D/A converter with greatly reduced capacitor ratio is also described.
author_names: R Gregorian
title: High resolution switched capacitor D/A converter
year: 1981

abstract: A low noise 8.95~11GHz all digital frequency synthesizer (ADPLL) with a metastability free first order noise shaping time to digital converter (TDC) and a high frequency resolution digitally controlled oscillator (DCO) is presented. An input stage for TDC is proposed to solve the problem of metastability and a specific technique is used to power down the high speed counter as soon as the ADPLL is about to lock for power saving consideration. The ADPLL is fabricated in 65nm CMOS technology and the core area is 0.385mm2. With about 8.5ms locking time, the measured phase noise performance at 1MHz offset is 106.4dBc/Hz from a carrier of 10GHz. The ADPLL core consumes 17.52mW from a supply of 1V.
author_names: Chen Jiang

Junren Liu

Yumei Huang

Zhiliang Hong
title: A low noise, 8.95 11GHz all digital frequency synthesizer with a metastability free time to digital converter and a sleepy counter in 65nm CMOS
venue: 2012 Proceedings of the ESSCIRC (ESSCIRC)
year: 2012

abstract: This work proposes a calibration free 14b 70MS/s 0.13um CMOS ADC for high performance integrated systems such as WLAN and high definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3 D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back end sub ranging flash ADC with open loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low noise current and voltage references are employed on chip with optional off chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is
author_names: Kyoung-Jun Moon

Kyung-Hoon Lee

Seung-Hoon Lee
title: A Calibration Free 14b 70MS/s 0.13um CMOS Pipeline A/D Converter with High Matching 3 D Symmetric Capacitors
year: 2006

abstract: Analog to Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional converters, and yet they are capable of offset free and accurate conversion. Most of the previous research on incremental converters was for single channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20 bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal to quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.
author_names: Sung-Hwan Bae

Changki Lee
title: Multi Channel AD Converters with High Resolution and Low Speed
year: 2008

abstract: Sample and hold amplifier less (SHA less) pipelined analog to digital converters (ADCs) are well suited for high resolution, high speed and low power applications. Apart from the comparator static offset, a dynamic offset is induced due to the timing skew and bandwidth mismatch between the multiplying digital to analog converter and the comparator input paths in the first stage, which brings a serious design challenge. This brief presents a novel background calibration technique for these offsets. First, the comparator's static offset and dynamic offset are discussed and analyzed. Then, a new evaluation technique is proposed to synchronously extract the values of the static offset and dynamic offset through the residue output at decision points. In this brief, the new calibration method is validated using behavioral models. The effective number of bits is improved from 5.04 bits to 11.96 bits, while the spurious free dynamic range is improved by 50.7 dB from our simulation. Thanks to the background calibration, comparator offset errors exceeding the built in redundancy of the architecture become acceptable. The proposed method relaxes comparator design requirements effectively. More importantly, the calibration can maximize the input frequency of the SHA less pipelined ADCs.
author_names: Congyi Zhu

Jun Lin

Zhongfeng Wang
title: Background Calibration of Comparator Offsets in SHA Less Pipelined ADCs
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2019