Query: Signaling Analysis and Optimal Channel Data Rates for High-Performance FPGA Interfaces

Candidate papers:

abstract: The study of the optimal data rates of high speed channels supported by typical high performance FPGA chips is presented. First, the representative channels are grouped into distinct categories that have drastically dissimilar characteristics. Consequently, the range of the channel operating data rates are expected to be significantly different. Special circuitries of various complexity are often implemented in the transmitters and receivers to mitigate the channel attenuation and enable the link to operate at the desired data rates. This paper attempts to shed a light on the optimal intrinsic channel data rates. Based on the signaling power, receiver sensitivity and the channel frequency responses, the range or optimal signaling rates of the channels are derived for each category. Finally, the paper summarizes the main differences of the channels in terms of characteristics, transceiver complexity, and optimal data rates when the high speed links are implemented in suitable semiconductor technology.
author_names: Wendemagegnehu T Beyene

Ashkan Hashemi

Changwook Yoon

Hyo-soon Kang

Xiaoping Liu

Guang Chen

Karthik Chandrasekar

David Greenhill
title: Signaling Analysis and Optimal Channel Data Rates for High Performance FPGA Interfaces
venue: 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
year: 2018

abstract: COTS (commercial off the shelf) hard ware using an industry standard Camera Link interface is proposed to accomplish the task of designing, building, assembling, and testing electronics for an airborne spectrometer that would be low cost, but sustain the required data speed and volume. The focal plane electronics were designed to support that hardware standard. Analysis was done to determine how these COTS electronics could be interfaced with space qualified camera electronics. Interfaces available for spaceflight application do not support the industry standard Camera Link interface, but with careful design, COTS EGSE (electronics ground support equipment) including camera interfaces and camera simulators, can still be used. The Camera Link data path is expandable. By adding another pair of interface circuits, and five more LVDS (low voltage differential signaling) pairs (the "medium" Camera Link interface) the data rate can be doubled (4,080 Mbps) By adding a third pair of interface circuits and five more LVDS pairs (the "full" Camera Link interface) data rates of 64 bits x 85 MHz 5,440 Mbps (over 5 Gbps) can be realized. The 28 bit commercial Camera Link interface is backwards compatible with the 21 bit spacequalified Channel Link interface. With proper circuit design and EGSE programming, the space qualified chip set can be used to implement a compatible Camera Link interface using COTS Camera Link EGSE. COTS EGSE in the form of instrument (camera) simulators is also readily available. This allows easy, early checkout of the EGSE and flight systems. This work was done by David P. Randall and John C. Mahoney of Caltech for NASA's Jet Propulsion Laboratory. For more information, contact iaoffice@jpl.nasa.gov. NPO46991 Adaptation of the Camera Link Interface for Flight Instrument Applications NASA's Jet Propulsion Laboratory, Pasadena, California
author_names: Loren P Clare

Jordan L Torgerson

Jackson Pang
title: High Performance CCSDS Encapsulation Service Implementation in FPGA
year: 2010

abstract: Over the past few decades, incessant growth of Internet networking traffic and High Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL) The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter Symbol Interference (ISI) crosstalk, and environmental noise. Therefore, todayas advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power performance trade offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi Tone (NRZ/MT) signaling method has been developed during the course of this research. The system level and circuit level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi tone signaling, especially orthogonality among different sub bands, to reduce the effect of crosstalk in high dense wireline interconnects. A four channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate.
author_names: Kiarash Gharibdoust
title: Hybrid NRZ/Multi Tone Signaling for High Speed Low Power Wireline Transceivers
year: 2016

abstract: Bandwidth demand is exploding due to internet video/TV streaming, Web surfing, file sharing, VoIP, video calling, online gaming, and etc. The bandwidth requirement leads us to develop 400G line card solution for communication systems. 28Gb/s electrical interface can increase port density and reduce power per bit. New heterogeneous SSIT (Stacked Silcon Interconnect Technology) design to implement 28Gb/s SerDes transceivers into an FPGA package will be introduced. The silicon interposer was used in this technology and it includes a significant number of TSVs (Through Silicon Vias) for the high speed signals. It is imperative that the signal path including the interposer is accurately modeled over the high operating frequency range by considering all those requirements before design optimization. Detailed design optimization for interposer has been performed to evaluate optimum design rules by taking into consideration of manufacturability and the TSV's parasitic effects from DC to high frequency, which can cause major performance degradation. A package channel design methodology for 28Gb/s SerDes signal support will be introduced. The package material selection to minimize dielectric loss and trace design to minimize copper/surface roughness loss for package substrate are very important. In addition, the design topologies to minimize signal attenuation loss, reflection loss, crosstalk and power coupling noise will be presented. Package and PCB design co optimization is very important to minimize reflections from solder ball interface. Any single mismatch in the very high speed system can result in the significant closer of the eye diagram. Once full channel analysis has been performed including optimized stacked silicon interposer model on top of low loss package substrate and PCB model, the simulation data is compared to the measured 28Gb/s Eye diagram and showing very good correlation. The proposed optimized channel system enables high performance signaling and great visibility of 28Gb/s Serdes FPGA applications.
author_names: Namhoon Kim

D Wu

Jack Carrel

Joong-Ho Kim

P Wu
title: Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology
venue: 2012 IEEE 62nd Electronic Components and Technology Conference
year: 2012

abstract: To enable 28 Gb/s transceiver operation, Xilinx has employed many innovative techniques for circuits, packaging and systems. Virtex(r) 7 HT FPGAs are designed to use Stacked Silicon Interconnect (SSI) technology that relies on an interposer built on low loss package substrate material. Channel loss, reflection loss and crosstalk noise are critical factors in determining system performance at this very high speed. The new concept of SSI in an FPGA device will be introduced. The interposer includes a significant number of TSVs (Through Silicon Vias) for the high speed signals. Technology requirements and manufacturing processes to support 28Gb/s SerDes application will be presented. It is imperative that the signal path including the interposer is accurately modeled over the high frequency operating range by considering all those requirements before design optimization. Detailed design optimization for the interposer has been performed to find optimum design rules by taking into consideration manufacturability and parasitic effects of the TSV's from DC to high frequency, which can cause major performance degradation. We will also introduce a package design methodology for 28Gb/s SerDes signal support. The package material selection to minimize dielectric loss and trace design to minimize copper/surface roughness loss for the package substrate is very important. In addition, the design topologies to minimize signal loss, reflection loss and crosstalk will be presented. Package and PCB design co optimization is very important to minimize reflections from solder ball interface. Any single mismatch in the very high speed system can result in the significant closure of the eye diagram. Once full channel analysis has been performed including the optimized silicon interposer model on top of a low loss package substrate and PCB model, the simulation data is then compared to the measured 28Gb/s eye diagram, showing very good correlation. The proposed optimized channel system enables high performance signaling and great visibility of 28Gb/s SerDes enabled FPGA products.
author_names: Zhaoyin Daniel Wu
title: Channel Co optimization for 28 Gb s SerDes FPGA Applications with Stacked Silicon Interconnect Technology
year: 2011

abstract: Brain machine interfaces (BMIs) may be used to investigate neural mechanisms or to treat the symptoms of neurological disease and are hence powerful tools in research and clinical practice. Wireless BMIs add flexibility to both types of applications by reducing movement restrictions and risks associated with transcutaneous leads. However, since wireless implementations are typically limited in terms of transmission capacity and energy resources, the major challenge faced by their designers is to combine high performance with adaptations to limited resources. Here, we have identified three key steps in dealing with this challenge: (1) the purpose of the BMI should be clearly specified with regard to the type of information to be processed; (2) the amount of raw input data needed to fulfill the purpose should be determined, in order to avoid over or under dimensioning of the design; and (3) processing tasks should be allocated among the system parts such that all of them are utilized optimally with respect to computational power, wireless link capacity and raw input data requirements. We have focused on step (2) under the assumption that the purpose of the BMI (step 1) is to assess single or multi unit neuronal activity in the central nervous system with single channel extracellular recordings. The reliability of this assessment depends on performance in detection and sorting of spikes. We have therefore performed absolute threshold spike detection and spike sorting with the principal component analysis and fuzzy c means on a set of synthetic extracellular recordings, while varying the sampling rate and resolution, noise level and number of target units, and used the known ground truth to quantitatively estimate the performance. From the calculated performance curves, we have identified the sampling rate and resolution breakpoints, beyond which performance is not expected to increase by more than 1 5% We have then estimated the performance of alternative algorithms for spike detection and spike sorting in order to examine the generalizability of our results to other algorithms. Our findings indicate that the minimization of recording noise is the primary factor to consider in the design process. In most cases, there are breakpoints for sampling rates and resolution that provide guidelines for BMI designers in terms of minimum amount raw input data that guarantees sustained performance. Such guidelines are essential during system dimensioning. Based on these findings we conclude by presenting a quantitative task allocation scheme that can be followed to achieve optimal utilization of available resources.
author_names: Palmi Thor Thorbergsson

Martin Garwicz

Jens Schouenborg

Anders J Johansson
title: Minimizing data transfer with sustained performance in wireless brain machine interfaces.
venue: Journal of neural engineering
year: 2012

abstract: Rapid developments in neural interface technology are making it possible to record increasingly large signal sets of neural activity. Various factors such as asymmetrical information distribution and across channel redundancy may, however, limit the benefit of high dimensional signal sets, and the increased computational complexity may not yield corresponding improvement in system performance. High dimensional system models may also lead to overfitting and lack of generalizability. To address these issues, we present a generalized modulation depth measure using the state space framework that quantifies the tuning of a neural signal channel to relevant behavioral covariates. For a dynamical system, we develop computationally efficient procedures for estimating modulation depth from multivariate data. We show that this measure can be used to rank neural signals and select an optimal channel subset for inclusion in the neural decoding algorithm. We present a scheme for choosing the optimal subset based on model order selection criteria. We apply this method to neuronal ensemble spike rate decoding in neural interfaces, using our framework to relate motor cortical activity with intended movement kinematics. With offline analysis of intracortical motor imagery data obtained from individuals with tetraplegia using the BrainGate neural interface, we demonstrate that our variable selection scheme is useful for identifying and ranking the most information rich neural signals. We demonstrate that our approach offers several orders of magnitude lower complexity but virtually identical decoding performance compared to greedy search and other selection schemes. Our statistical analysis shows that the modulation depth of human motor cortical single unit signals is well characterized by the generalized Pareto distribution. Our variable selection scheme has wide applicability in problems involving multisensor signal modeling and estimation in biomedical engineering systems.
author_names: Wasim Q Malik

Leigh R Hochberg

John P Donoghue

Emery N Brown
title: Modulation Depth Estimation and Variable Selection in State Space Models for Neural Interfaces
venue: IEEE Transactions on Biomedical Engineering
year: 2015

abstract: Today's designs have grown in size and complexity by orders of magnitude in comparison to common designs of only a few years ago. FPGAs have also grown in size and density, with 100k gate FPGAs now available. Because of this growth in FPGA density, designs that previously required an ASIC implementation may now be targeted to an FPGA. However, schematic based design is no longer the ideal method of design entry when attempting to meet time to market requirements. Hardware Description Languages (HDLs) such as VHDL and Verilog are necessities for high speed design targeting high density FPGAs. Because of the need for HDLs, HDL synthesizers play a vital role in the design process. Moreover, once placeand route of the design has been completed, FPGA level and system level timing verification become critical design paths. This paper analyzes the entire design process required to implement a high complexity, high speed design a Peripheral Component Interface (PCI) Bus Target Controller Interface in a high density FPGA. Selection of a design methodology will be discussed as well as the ramifications of this choice in regards to the selection of a suite of tools for performing design entry and analysis and the selection of the target technology. The design process will be examined and common problems that were encountered will be discussed as well as the implemented solutions. Finally, design performance will be analyzed based on maximum frequency of operation, ease of system level integration and analysis, as well as time and effort required to complete the design process. I. PCI Bus Target Controller Interface Requirements As detailed in [13] a PCI Bus Target Controller Interface has the following critical design parameters at the FPGA level: Maximum clock rate of 33 MHz. Minimum input set up time to clock of 7 ns. Minimum hold time from clock of 0 ns. Maximum clock to signal valid delay of 11 ns. 36 bit parity generation and checking for I/O, memory, and configuration spaces. 36 bit input and output pipelines. 48 PCI bus connections and 70+ back end connections. Full speed burst support in memory space. PCI interrupt support. PCI configuration space registers for device ID, vendor ID, status, command, class code, revision ID, memory base address, I/O base address, interrupt line, and interrupt pin. As detailed in [13] a PCI Bus Target Controller Interface has the following critical design parameters at the system level: AC output drive characteristics defined as I/V curves for minimum and maximum drive current. Maximum input pin capacitance of 10 pF. Maximum leakage current of 70 nA. II. Design Methodology As design complexity and speed increase, the complexity of the targeted FPGA's architecture must also increase. A schematic based design methodology is incapable of supporting this increase in FPGA architectural complexity. Therefore, a language based design methodology was used to implement the PCI Bus Target Controller Interface. Language based design, originally a design methodology reserved for ASIC targets[3] is performed at a higher level of abstraction than schematic based design and is therefore geared toward more complex design solutions. As stated in [2] this method of designing at a higher level of abstraction, also known as top down design, is more efficient than the traditional methodology of bottom up design, where lower implementation levels are designed and verified before connected to the higher levels of the design. Changes to the design are far easier to implement and evaluate at this higher level of abstraction and result in minor implementation changes at the lower levels, therefore decreasing the length of the design cycle. Language based design is more conducive to partitioning of the design into submodules in a hierarchical manner, allowing for more efficient design management[4] Hierarchical design also results in a hierarchy of functions that allow for simulation of submodules and a comp arison of the results with higher level behavioral descriptions. This process yields accurate predictions of a design's performance prior to place and route[2] Finally, HDLs allow for the development of designs that are independent of the target technology. As stated in [7] for high density designs, it is more efficient and error free to create and verify designs at a technologyindependent level. However, through the use of an intelligent synthesizer, technology specific solutions are possible. Many vendors provide technology specific and optimized implementations an intelligent synthesizer will take advantage of these implementations to yield a design that is optimized for area and speed[5] Synthesis tools also allow for the integration of the modeling, verification, and implementation processes. The same HDL code can be used for verification and implementation, reducing code maintenance and the risk of inconsistencies between models[6] III. Selection of the Design Tool Suite Because of the choice of a language based design methodology, a high performance tool suite was required to allow for optimal implementation of the design. The chosen tool suite had to allow for HDL design entry, architectural synthesis, and preand post route simulation. The synthesis tools had to provide architecture specific optimizations and design implementations at the FPGA level as part of the design flow. These architecture specific optimizations and implementations would result in the synthesis of a design that is efficient in its usage of area in the FPGA as well as maximizing the speed capability of the design. At the system level, tools that allow for the evaluation of signal integrity and static timing analysis were a necessity when analyzing board level interconnection delays and cross talk between signals. Automation of the design flow as well as ease of use of the individual point tools was also considered while selecting a suite of tools[1] Finally, the tool suite had to be fully integrated with all FPGA vendor tools to guarantee a smooth design flow. In the past, most language based design was performed in a UNIX environment and targeted toward ASICs. However, due to the decrease in cost and the increase in performance of today's PCs, as well as the availability of vendor placeand route tools for the PC environment, the choice was made to design in the PC environment, necessitating a PC based tool suite that may be used in both the Windows NT and Windows95 operating systems. The tool suite chosen for design development was WorkView Office, provided by Viewlogic Systems, Inc. WorkView Office provides a suite of tools that satisfied the design entry, synthesis, simulation, and automation requirements, both at the FPGA level and the board level. ViewSynthesis was used for synthesis of the HDL design. Digital Fusion was used for all phases of simulation at the FPGA level due to its support of both HDL and gate level simulation. Motive was used for board level static timing analysis and XTK was used for board level signal integrity analysis. Finally, IntelliFlow was used to automate the design flow, allowing for concentration on the design itself rather than on the tool interfaces[1] IV. Selection of the Target Technology FPGA architectural granularity is extremely important in evaluating possible target technologies. Fine grained architectures employ simple transistor level elements while coarsegrained architectures involve multiple transistors implemented in pre wired blocks. Generally, the more fine grained the architecture, the more ASIC like the FPGA[8] The importance of granularity is obvious the more ASIC like architecture will generally yield better synthesized results from the HDL code since language based design was originally created for ASIC targets. Another important factor in selecting a target technology is FPGA density, which is defined in terms of usable gates. Many FPGA vendors list the number of total gates available for a given FPGA. However, the true indication of an FPGA's density is in terms of usable gates. The number of usable gates is determined by the effectiveness of the vendor's place and route tools, and is defined as the percentage of the total gates available that the place and route tools can successfully route. As an FPGA's usable gate count increases, there is a resulting increase in design performance in respect to both routability and speed. I/O capacity is also a deciding trait when choosing an FPGA. While more I/O is always desirable, the obvious tradeoff occurs in board space. Selecting an FPGA with increased I/O capacity results in a corresponding increase in package size and hence the amount of board space required. Normally, the physical size of the FPGA would be an important criteria for device selection. However, no limitation on available board space was given as a design requirement, therefore eliminating the issue of fitting the FPGA into a specified area in the system. In designs where board space is limited, it is important to remember that the I/O capacity of the FPGA is greatly affected by the package type selected. The PCI Bus Target Controller Interface requires 123 I/O pins. On chip RAM is another extremely useful feature available on some FPGAs. On chip RAM has faster access times than off chip RAM and does not require the extra board space for off chip RAM. If on chip RAM is not present, the only available method for implementing RAM within the FPGA is to use the flip flops that implement gate level functions as look up tables (LUTs) in logic elements (LEs) However this underutilizes the LEs and results in poor overall FPGA utilization. Table I lists usable gates, maximum I/O, and on chip RAM bits available for four FPGA vendors. Data is from [8] [9] [10] and [11] and is displayed for equivalent FPGAs that meet the minimum I/O requirement of the PCI Bus Target Controller Interface. Data for the Actel A32200DX, Lucent OR2C15A, and Xilinx XC4013E ar
author_names: Adam J Elbirt
title: Implementation of a PCI Bus Target Interface in a High Density FPGA
year: 2002

abstract: Data converters are critical elements in communication systems forming bridges between analog transmission media such as fiber optics, microwave, RF, and digital processing blocks like FPGAs and DSPs. System designers often focus on selecting the most appropriate data converters for the application, while much less consideration may be given to the selection of the clock generation devices supplying the data converters. A broad range of clock generators with widely different performance attributes are available. However, without careful consideration of clock generator, phase noise, and jitter performance characteristics, data converter, dynamic range, and linearity performance can be severely impacted. This article discusses the effect of clock generator, phase noise, and jitter on the dynamic range and linearity of data converters (ADCs and DACs) in detail. Theoretical analysis of clock jitter on converter SNR is presented and simulation results are provided using Analog Devices' high performance clock generators. Analog Devices has developed a unique line of high performance clock distribution and clock generation products that enable the system designer to maximize the performance from data converters. The HMC1032LP6GE and the HMC1034LP6GE are SMT packaged clock generators, which are ideal for a wide range of high performance cellular/4G infrastructure, fiber optic, and networking applications, and deliver best in class jitter and industry leading phase noise floor. The HMC987LP5E 1:9 fanout buffer is ideal as a clock driver in critical applications and features an ultralow noise floor of 166 dBc/Hz. Key specifications for these devices are shown in Tables 1 and 2. System Considerations A typical LTE (long term evolution) base station utilizing MIMO (multiple input multiple output) architecture is shown in Figure 1. The architecture consists of multiple transmitters, receivers, and DPD (digital predistortion) feedback paths. Various transmitter/receiver components, such as data converters (ADCs/ DACs) and local oscillators (LO) require low jitter reference clocks to improve performance. Other baseband components also require clock sources of various frequencies. Share on Twitter Share on LinkedIn Email Table 1. Clock Generators Typical Performance Characteristics Part Number Maximum Frequency (MHz) Function Typical Phase Jitter (fs rms) Phase Noise Floor (dBc/Hz) Maximum Reference Frequency (MHz) Typical Power Consumption (W) Figure of Merit (Frac/Int) (dBc/Hz) HMC1032LP6GE 350 High performance clock generator with fractional N PLL and VCO 75 165 350 0.86 227/ 230 HMC1034LP6GE 3000 High performance clock generator with fractional N PLL and VCO 78 165 350 0.86 227/ 230 Table 2. Clock Distribution Products Typical Performance Characteristics Part Number Maximum Clock Rate (GHz) Function Input Output Phase Jitter (12 kHz to 20 MHz) Rise/Fall Time (ps) Channel Skew (ps) Channel Disable Mode Power Supply (V) HMC987LP5E 8 1:9 fanout buffer LVPECL, LVDS, CML, CMOS LVPECL 8 fs rms 65 3.1 Yes 3.3 2 The Impact of Clock Generator Performance on Data Converters The clock source used to achieve interbase station synchronization typically comes from a GPS (global positioning system) or CPRI (common public radio Interface) link. Such a source typically has excellent long term frequency stability; however, it requires frequency translation to the required local reference frequency with excellent short term stability, or jitter. A high performance clock generator, such as the HMC1032LP6GE, performs the frequency translation and provides a low jitter clock signal, which may then be distributed to various base station components. Selecting the optimal clock generator is critical because a suboptimal reference clock contributes to higher LO phase noise, resulting in higher transmit/receive EVM (error vector magnitude) and system SNR (signal to noise ratio) High clock jitter and noise floor also affects data converters by reducing system SNR, and introducing data converter spurious emissions, thereby further reducing the data converter SFDR (spurious free dynamic range) Consequently, a low performance clock source ultimately reduces system capacity and throughput. Clock Generator Specifications While there are various definitions of clock jitter, the most applicable definition in data converter applications is phase jitter, which is specified in time domain units of ps rms or fs rms. Phase jitter (PJBW) is the jitter derived by the integration of the clock signal's phase noise over a specific range of offsets from the carrier and is given by the following equation: fCLK is the frequency of operation; fMIN/fMAX indicate the bandwidth of interest, and S(fCLK) represents the SSB phase noise. The upper and lower limits of the integration bandwidth (fMIN/fMAX) are unique to each application and are set by the relevant spectral content that the design will be sensitive to. A designer's goal then is to choose a clock generator with the lowest integrated noise, or phase jitter in the desired bandwidth. Traditionally, clock generators are characterized by integrating over 12 kHz to 20 MHz, which is the specified requirement for optical communication interfaces, such as SONET. While this may be applicable in some data converter applications, a broader spectrum of integration, particularly extending beyond 20 MHz is usually needed to capture the relevant noise profile of the sample clock for a high speed data converter. When measuring phase noise the noise offsets far from the carrier frequency. For example, the actual clock frequency used for data converter sampling are commonly referred to as far from carrier phase noise. The limit of this noise is usually referred to as the phase noise floor, as shown in Figure 2. This figure shows the actual measurement plot of ADI's HMC1032LP6GE clock generator. The phase noise floor takes on additional importance in data converter applications because of the sensitivity of the converter SNR to broadband noise on its clock input. When designers evaluate options for clock generators, the phase noise floor performance must be considered as a key benchmark.
author_names: Max Operatinq Frequency

Max Reference
title: THE IMPACT OF CLOCK GENERATOR PERFORMANCE ON DATA CONVERTERS
year: 2015

abstract: Due to increasing demand for more bandwidth and higher data rates, the design complexity and constraints of high performance digital system have increased rapidly. Apart from the circuit design challenges, high speed interconnects have brought new challenges in signal transmission integrity and timing requirements. It is known that memory play a vital part of high performance digital system and, the feasible data transfer rate from memory is greatly influenced by performance of interconnects between memory and controller. Increase in data transfer rate from memory and decrease in access latency reduce the timing margin available to each component such as memory controller, PHY, memory module and interconnects. Hence, a diligent budgeting of timing requirement for each sub system is essential to achieve better end to end performance. In this paper, timing optimization of interconnects on signal integrity and timing analysis perspective is presented. As a case study an 800 Mbps interface between a dual rank DDR3 memory and Virtex 6 FPGA has been analyzed and validated. The adopted techniques enabled deriving appropriate timing budget for interconnects and ascertain end to end data rate is not degraded due to sub optimal design of interconnects. Further, the analysis also assisted to derive appropriate routing density, trace length matching, and addressing impedance discontinuities, via selection and signal integrity aware routing.
author_names: Hitesh Sharma

J Mervin

David Selvakumar
title: DDR3 interconnect optimization Signal integrity and timing analysis perspective
venue: 2015 International Conference on Control, Electronics, Renewable Energy and Communications (ICCEREC)
year: 2015