Query: high density computing assembly architecture

Candidate papers:

abstract: Successful transition from today's general purpose programmable systems, based on the concept of planar topology, to tomorrows intelligent, highly adaptable and not necessarily programmable systems would require integration of several unorthodox approaches. We cannot predict exactly which technology will become post CMOS and post silicon computing mainstream. Whether it will belong to a quantum, molecular, DNA, optical, or neural paradigm, several speculations can be made to ease the transition and to create a processing infrastructure that will allow coexistence of today's semiconductor based approach with its successor. An attempt is made here to introduce such a transitional architecture. The proposed concept of system architecture allows high performance computing capabilities and high density free space optical interconnects to be seamlessly integrated with power supply and cooling subsystems. This is achieved by bringing twenty hexagon base and twelve pentagon base pyramids into close proximity, forming truncated icosahedron. Each pyramid is an Integrated Processing Power supply Cooling Module (IPPCM) IPPCM has a conical cavity within, which is occupied by a power supply/cooling unit; the optoelectronic components are attached to the faces of the pyramids. In the proposed instance, 180 trapezoidal multi chip processing modules, with total die attach area equal to 2000cm2, are brought into a volume of less than two liters. By bringing multiple pyramids into close proximity to each other, a free space optical link is formed for inter pyramidal communication. Some of the spaces formed between pyramids can be used for future unorthodox processing technologies.
author_names: V V Gorelik
title: High performance computing based on 3D system assembly
venue: SPIE Optics Photonics
year: 2000

abstract: Emerging nanoscale devices hold tremendous potential in terms of integration density, low power operation and switching speed. Unlike CMOS devices, however, majority of these devices are not suitable for implementing cascaded, irregular logic structure. On the other hand, dense and periodic structures of most emerging nanodevices as well as their bi stable nature make them amenable to large high density memory array design. Moreover, self assembly of many nanostructures is efficient for a bottom up system design flow. Hence, reconfigurable computing paradigms that use memory as underlying computing element, appear promising for these devices. In this paper, first we study nanoscale FPGA, which extends conventional spatial CMOS FPGA architecture using nanoscale memory and interconnect. Next, we focus on a time multiplexed memory based computing paradigm that employs two dimensional memory for improved performance, integration density and resource usage.
author_names: Somnath Paul

Swarup Bhunia
title: Computing with nanoscale memory: Model and architecture
venue: 2009 IEEE/ACM International Symposium on Nanoscale Architectures
year: 2009

abstract: The assembly of integrated circuits in three dimensions (3D) provides a possible solution to address the ever increasing demands of modern day electronic devices. It has been suggested that by using the third dimension, devices with high density, defect tolerance, short interconnects and small overall form factors could be created. However, apart from pseudo 3D architecture, such as monolithic integration, die, or wafer stacking, the creation of paradigms to integrate electronic low complexity cellular building blocks in architecture that has tile space in all three dimensions has remained elusive. Here, we present software and hardware foundations for a truly 3D cellular computational devices that could be realized in practice. The computing architecture relies on the scalable, self configurable and defect tolerant cell matrix. The hardware is based on a scalable and manufacturable approach for 3D assembly using folded polyhedral electronic blocks (E blocks) We created monomers, dimers and 2 x 2 x 2 assemblies of polyhedral E blocks and verified the computational capabilities by implementing simple logic functions. We further show that 63.2% more compact 3D circuits can be obtained with our design automation tools compared to a 2D architecture. Our results provide a proof of concept for a scalable and manufacture ready process for constructing massive scale 3D computational devices.
author_names: Shivendra Pandey

Nicholas J Macias

Carmen Ciobanu

ChangKyu Yoon

Christof Teuscher

David H Gracias
title: Assembly of a 3D Cellular Computer Using Folded E Blocks
venue: Micromachines
year: 2016

abstract: High bandwidth density silicon photonic interconnects offer the potential to address the massive increase in bandwidth demands for data center traffic and high performance computing. One of the major challenges in realizing silicon photonics transceivers is the integration and packing of photonic ICs (PIC) with electronic ICs (EIC) This paper presents our version one, 2.5D integrated multi chip module (MCM) transceiver for 4 channel wavelength division multiplexing (WDM) operation, targeting 10 Gbps per channel. We identify five key areas critical to successful integration of MCM transceivers, which we have used in developing our version two MCM transceiver: integration architecture, equivalent circuit model development, PIC to EIC interface modelling, MCM I/O design, and design for assembly.
author_names: Nathan C Abrams

Qixiang Cheng

Madeleine Strom Glick

Evgeny Manzhosov

Moises A Jezzini

Padraic E Morrissey

Peter O'Brien

Keren Bergman
title: Design considerations for multi chip module silicon photonic transceivers
year: 2020

abstract: During last couple years, the market of IC packag successful to implement Cu pillar Bump as a mainstream of high density flip chip packaging solution in each of product application market. High performance computing product requires advanced Si node, large die and multiple die side by side floor plan on large FCBGA. However, large scale die dimension and substrate form factor to brings up expensive wafer mask fabrication, substrate fee, complex backend assembly process control and specific bill of material to maintain better mechanical performance. In other words, there is a significant help from package assembly since Moore Law is slowing down. After reviewed the package evolution trend of 2.5D package, Cu pillar bump owns better electron migration performance which is suitable for high power and low latency product application. 3D package with mBump architecture has three kinds of advantages. First, die partition to shrink die area and enhance wafer yield; Second, reduce signal latency insertion loss compared to 2.5D since applying 50um TSV wafer thick. to reduce signal transmission path; Third, high power IC which used advanced Si node and put on top position of 3D stacking to contact thermal interface material and heat sink directly to realize better system thermal dissipation requirement.In order to well define optimum construction while utilizing less than 30um mBump pitch 3D package vehicle rely on mechanical simulation trend to find out critical dimension on mBump of top die and TSV wafer structure design. The paper will compare die to die signal connection architecture such as 2.5D, FO MCM and FO EB packages. Uses a series of fundamental studies to define mBump stack up composition and protection material in terms of 3DIC platform baseline establishment. Based on dominated key factors of stress simulation and actual verification result to find out bump joint methodology. First of all, chip module of 3D TV (Test Vehicle) samples is stacked with top die and bottom die by the joint of mBump and mPad. mBump has three structures: CS (Cu Solder) CNS (Cu Ni Solder) and CNCS (Cu Ni Cu Solder) Moreover, the validation flow is proposed. In the first phase, the metallic reaction test of 1st 3D TV samples and stress simulation of mBump are performed. In the second phase, based on the results of the first phase, to modify the dimension and materials of mBump and mPad, and to build the 2nd 3D TV samples for reflow test then obtain the best combination of structure and dimension for mBump by multiple reflow test.In conclusion, this study successfully completed pathfinding activity of 3D package with the joint of mBump (less than 15/30, mm) and mPad, and found the best structure and dimension for mBump and mPad.
author_names: Nistec Chang

C Key Chung

Yu-Po Wang

C F Lin

P J Su

Teny Shih

N H Kao

Joseph Hung
title: 3D Micro Bump Interface Enabling Top Die Interconnect to True Circuit Through Silicon Via Wafer
venue: 2020 IEEE 70th Electronic Components and Technology Conference (ECTC)
year: 2020

abstract: Designing high speed and low power interconnects is a challenge for high performance computing applications, while silicon photonics can provide attractive solutions to perform high density communications. This paper presents an electro optic transmitter operating at 20 Gbps (gigabit per second) as a first step toward the demonstration of chip to chip optical links. The architecture is based on a dual drive Mach Zehnder interferometer co integrated with a 55 nm CMOS driver. Design optimizations and trade offs analysis enable low energy and negligible bit error rate $BER 10^ 12} transmission at 20 Gbps, by exploring a firstly reported low extinction ratio (ER) modulator. A wire bonding board assembly is then carried out to co integrate hybrid transmitter. Co simulations are presented and show good agreement with experiments. Combined with an adequate MZM bias, this solution achieves a minimal energy consumption of 0.9 pJ/bit while ensuring a sufficiently large ER of 0.73 dB for chip to chip interconnects applications.
author_names: Audrey Michard

J F Carpentier

Nicolas Michit

Patrick Le Maitre

Philippe Benabes

Pietro M Ferreira
title: A Sub pJ/Bit, Low ER Mach Zehnder Based Transmitter for Chip to Chip Optical Interconnects
venue: IEEE Journal of Selected Topics in Quantum Electronics
year: 2020

abstract: Abstract Effective ultra dense integrated digital information processing strains the leading edge of current chemistry and materials science, and requires hybrid top down and bottom up assembly techniques, with highly reliable defect and fault tolerant architecture. We have fabricated and assembled molecular scale logic elements based on overlapping semiconducting nanowire arrays using novel wafer scale assembly techniques. Based on breakthrough addressing techniques, we have connected these logic blocks to ultra dense memory blocks, and to external CMOS process lithographic interfaces for testing as well as test applications. Our architecture to construct highly reliable components out of high defect density logic and memory, using new sublithographic scale PLA array architectures include novel reliable circuit techniques and higher level redundancy mechanisms. Using state of the art modeling and simulation platforms, we have optimized test designs, developed defect tolerance approaches, and are continuing to develop and optimize larger systems.
author_names: Charles M Lieber
title: Assembly of Ultra Dense Nanowire Based Computing Systems
year: 2006

abstract: Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designing Multi Processor based System on Chip. SPMD (Single Program Multiple Data) is a massively parallel execution model based on the assembly of a given number of homogeneous Processing Elements (PEs) This model is often relaying on Master/Slaves architecture composed by a Master PE that manages the parallel execution of a set of identical slave PEs. Furthermore, Dynamic Partial Reconfiguration (DPR) feature allows such computing system to be reconfigured on the fly for a given application requirement. Given the growing number of PEs in Master/Slaves architecture, it is difficult to estimate the time of specification and design during the phase of allocation and floorplanning of Partial Reconfigurable Regions (PRRs) because it is still performed manually. In this work, we present AFFORDe, a tool enable to automate the Xilinx DPR flow for SPMD architecture that allows parsing the resource requirements of the static and the dynamically reconfigurable parts to perform an automatic floorplanning. The floorplanning is based on a Heuristic Algorithm for Automatic Floorplanning in SPMD Architectures (HAAFSA) This tool is used to generate a configuration file that allows floorplanning of reconfigurable regions in an automatic way of a given Master/Slaves configuration. Experimental results show the effectiveness of our tool to increase the design productivity for dynamically reconfigurable SPMD based architecture.
author_names: Wissem Chouchene

Rabie Ben Atitallah

Jean-Luc Dekeyser
title: AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture
venue: 2016 IEEE 10th International Symposium on Embedded Multicore/Many core Systems on Chip (MCSOC)
year: 2016

abstract: Both bottom up and top down techniques have been used to fabricate assemblies of devices and interconnect where key, density defining feature sizes are on the order of ten atoms wide. We show how complete computing architectures can be constructed from these new techniques and building blocks despite high defect rates, extreme regularity requirements, and statistical assembly. We further highlight the paradigm shifts in integrated circuit design and architecture which appear necessary to accommodate these atomic scale effects. Our estimates suggest a 10 nm full pitch FPGA like design can achieve one to two orders of magnitude greater logic density than ideal, defect free lithographic scaling to 22 nm.
author_names: Andre DeHon
title: Architecture approaching the atomic scale
venue: ESSCIRC 2007 33rd European Solid State Circuits Conference
year: 2007

abstract: Increasing demand for advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven semiconductor industry to develop more innovative and emerging advanced packaging technologies. Memory bandwidth has become a bottleneck to mobile processor performance and lower power consumption for high performance computing needs. To reduce obstacles, a revolution in device architecture and package technologies is require. 3D TSV (Through Silicon Via) stacking is to be one of the technologies that can meet those requirements. This paper mainly describes the 3D TSV MEOL process and packaging technology, especially TSV wafer process and thin die bonding process with Cu column bump on substrates. In order to prove the quality of this 3D package, some stress tests were conducted to evaluate the reliability on the package and board level. The innovative TSV MEOL process and flip chip assembly with micro Cu column contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structures which consisted of a 28 nm logic device and Wide I/O memory. The logic device was fabricated by via middle process and accompanied with over 1200 TSVs, and 40 mm 50 mm bump pitch layout. Advanced 300mm backside via reveal (BVR) process was developed with thin wafer handling and temporary bonding/debonding process. Thermocompression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. As reliability test items, temperature cycling test, high temperature storage test, humidity test, unbiased highly accelerated stress test and pressure cooker test were performed and passed JEDEC standard reliability tests as well as board level reliability test. After functional test with stacked 3D TSV with logic and Wide IO memory, 12.8 GB/s transmission and drastic I/O power saving compared to LPDDR3 were observed.
author_names: Duk Ju Na

KyawOo Aung

Won Kyung Choi

Tsuyoshi Kida

Toshihiko Ochiai

Tomoaki Hashimoto

Michitaka Kimura

Keiichiro Kata

Seung Wook Yoon

Andy Chang Bum Yong
title: TSV MEOL (Mid End of Line) and packaging technology of mobile 3D IC stacking
venue: 2014 IEEE 64th Electronic Components and Technology Conference (ECTC)
year: 2014