Query: vlsi latest technology

Candidate papers:

abstract: Digital integrated circuits require thorough testing in order to guarantee product quality. This is usually achieved with the use of scan chains and automatically generated test patterns. However, functional approaches are often used to complement test suites. Software Based Self Test (SBST) can be used to increase defect coverage in microcontrollers, to replace part of the scan pattern set to reduce tester requirements, or to complement the defect coverage achieved by structural techniques when advanced semiconductor technologies introduce new defect types. Delay testing has become common practice with VLSI integration, and with the latest technologies, targeting small delay defects (SDDs) has become necessary. This chapter deals with SBST for delay faults and describes a case of study based on a peripheral module integrated in a System on Chip (SoC) A method to develop an effective functional test is first described. A comparative analysis of the delay faults detected by scan and SBST is then presented, with some discussion about the obtained results.
author_names: Kai Rannenberg
title: VLSI SoC: New Technology Enabler: 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI SoC 2019, Cusco, Peru, October 6 9, 2019, Revised and Extended Selected Papers
venue: VLSI SoC
year: 2020

abstract: Fractional motion estimation (FME) is used in all the latest video coding standards to reduce the bit rate. In FME, Hadamard transform (HT) is used to calculate total distortion. HT helps to find the best matched candidate block. Unlike the earlier video coding standards, HEVC supports the variable size of HT such as 2 x 2, 4 x 4, 8 x 8, 16 x 4 and 4 x 16. Therefore, the development of an efficient scalable VLSI architecture for HT compatible with HEVC is a challenging task. In this paper, we have proposed a scalable architecture for HT which supports all the sizes of HT adopted by HEVC. Simulation and synthesis of the proposed architecture are carried out using standard 90 nm Technology. Simulation results show that the proposed architecture can process 4K video sequences and occupies only 0.2517 mm2of the area. The proposed architecture consumed 19.0225 mW of power for the operating frequency of the 250 MHz.
author_names: Karam Singh

Shaik Rafi Ahamed
title: Scalable VLSI Architecture for Hadamard Transforms of HEVC/H.265 Video Coding Standard
venue: 2020 24th International Symposium on VLSI Design and Test (VDAT)
year: 2020

abstract: Machine learning (ML) provides the high end automation of data processing for the widerange of human brain with machine interfacing. Deep machine learning (DML) performs like humanbrain to achieve automated features extraction, reducing the dimension of the complex data set.Analog signal processing (ASP) need much higher energy efficiency than digital signal processing(DSP) presenting a way for overcoming of these limitations. This paper have reviewed MLtechniques which propose analogue memory which can be essential component for learning system.VLSI architecture and circuits are discussed for k mean clustering algorithm in analogue signalprocessing. Discussed about unsupervised learning system for different computation node in DML.In addition, also discussed about ultra low power circuit to provide similarity measures in analoguesignal processing and technique matched with latest development in VLSI, ULSI for CMOStransistor with compact technology. Moreover the compact technology node size of nanometer (nm)VLSI design and complex fabrication have extreme high complexity which generates heavygigabytes data Such result helps in designing of VLSI architecture, lithography hotspot detection,and also increases the dependability of physical design with face recognition. The face recognitionstudied, based on Hidden Markov Models (HMMs) and discrete wavelet transform (DWT) Asequence of overlapping sub images is extracted from each face image computing the DWTcoefficients for each of them.
author_names: Arpit Singh Yadav

Swapnil Jain
title: Efficient VLSI Architecture using Machine Learning Algorithms
year: 2020

abstract: Machine learning (ML) provides the high end automation of data processing for the wide range of human brain with machine interfacing. Deep machine learning (DML) performs like human brain to achieve automated features extraction, reducing the dimension of the complex data set. Analog signal processing (ASP) need much higher energy efficiency than digital signal processing (DSP) presenting a way for overcoming of these limitations. This paper have reviewed ML techniques which propose analogue memory which can be essential component for learning system. Discussed about unsupervised learning system for different computation node in DML. In addition, also discussed about ultra low power circuit to provide similarity measures in analogue signal processing and technique matched with latest development in VLSI, ULSI for CMOS transistor with compact technology. The face recognition studied, based on Hidden Markov Models (HMMs) and discrete wavelet transform (DWT) A sequence of overlapping sub images is extracted from each face image computing the DWT coefficients for each of them.
author_names: Arpit Singh Yadav
title: Designing of VLSI Architecture using Machine Learning Algorithms
year: 2020

abstract: In this article, a low complexity and high throughput sorted QR decomposition (SQRD) for multiple input multiple output (MIMO) detectors is presented. To reduce the heavy hardware overhead of SQRD, we propose an efficient SQRD algorithm based on a novel modified real value decomposition (RVD) Compared to the latest study, the proposed SQRD algorithm can save the computational complexity by more than 44.7% with similar bit error rate (BER) performance. Furthermore, a corresponding deeply pipelined hardware architecture implemented with the coordinate rotation digital computer (CORDIC) based Givens rotation (GR) is designed. In the design, we propose a time sharing Givens rotation structure utilizing CORDIC modules in idle state to share the concurrent GR operations of other CORDIC modules, which can further reduce hardware complexity and improve hardware efficiency. The proposed SQRD processor is implemented in SMIC 55 nm CMOS technology, which processes 62.5 M SQRD per second at a 250 MHz operating frequency with only 176.5 kilo gates. Compared to related studies, the proposed design has the best normalized hardware efficiency and achieves a 6 Gbps MIMO data rate which can support current high speed wireless communication systems such as IEEE 802.11ax.
author_names: Lu Sun

Bin Wu

Tianchun Ye
title: Design and VLSI Implementation of a Reduced Complexity Sorted QR Decomposition for High Speed MIMO Systems
year: 2020

abstract: Deblocking filter (DBF) is an efficient tool to reduce the bit rate in the latest video coding standard, High Efficiency Video Coding (HEVC) This work presents an SRAM free deblocking filter VLSI architecture with high throughput and efficiency. To avoid the usage of SRAM inside the DBF module, the basic filter unit (BFU) is designated as 8 x 8 block size and the vertical boundaries in 8 x 8 block will be filtered firstly followed by the horizontal. Besides, the block in out and block filtering will be performed by pipeline to improve DBF throughput. Based on the proposed architecture, it takes 4 cycles to finish one BFU processing, one cycles for one boundary between two 4 x 4 blocks. The experimental result shows that our design can support 8K@120fps real time video coding with TSMC 65nm process, which occupies 23.5K gates at 400NHz.
author_names: Genwei Tang

Xiaoyang Zeng

Yibo Fan
title: An SRAM free HEVC Deblocking Filter VLSI Architecture for 8K Application
venue: 2018 14th IEEE International Conference on Solid State and Integrated Circuit Technology (ICSICT)
year: 2018

abstract: The next generation 8K ultra high definition video format involves an extremely high bit rate, which imposes a high throughput requirement on the entropy decoder component of a video decoder. Context adaptive binary arithmetic coding (CABAC) is the entropy coding tool in the latest video coding standards including H.265/High Efficiency Video Coding and H.264/Advanced Video Coding. Due to critical data dependencies at the algorithm level, a CABAC decoder is difficult to be accelerated by simply leveraging parallelism and pipelining. This letter presents a new very large scale integration arithmetic decoder, which is the most critical bottleneck in CABAC decoding. Our design features a variable clock cycle path architecture that exploits the differences in critical path delay and in probability of occurrence between various types of binary symbols (bins) The proposed design also incorporates a novel data forwarding technique (rLPS forwarding) and a fast path selection technique (coarse bin type decision) and is enhanced with the capability of processing additional bypass bins. As a result, its maximum throughput achieves 1010 Mbins/s in 90 nm CMOS, when decoding 0.96 bin per clock cycle at a maximum clock rate of 1053 MHz, which outperforms previous works by 19.1%
author_names: Jinjia Zhou

Dajiang Zhou

Shuping Zhang

Shinji Kimura

Satoshi Goto
title: A Variable Clock Cycle Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC
venue: IEEE Transactions on Circuits and Systems for Video Technology
year: 2018

abstract: More recently, "chiplets" are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over a few decades. The symbolic configuration of this concept based on the chiplets is 3D integration with TSV we have worked on since 1989. This paper introduces our 3D and heterogeneous system integration research from its historical activities to the latest efforts, including capillary self assembly of tiny dies with a size of less than 0.1 mm and advanced flexible hybrid electronics (FHE) using fan out wafer level packaging (FOWLP)
author_names: Takafumi Fukushima
title: Chiplet Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE
venue: 2021 Symposium on VLSI Circuits
year: 2021

abstract: More recently, "chiplets" are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over a few decades. The symbolic configuration of this concept based on the chiplets is 3D integration with TSV we have worked on since 1989. This paper introduces our 3D and heterogeneous system integration research from its historical activities to the latest efforts, including capillary self assembly of tiny dies with a size of less than 0.1 mm and advanced flexible hybrid electronics (FHE) using fan out wafer level packaging (FOWLP)
author_names: Takafumi Fukushima
title: Chiplet Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE
venue: 2021 Symposium on VLSI Technology
year: 2021

abstract: Recent progress on FeFET gate first technology development is presented. New characterization results from FeFET endurance degradation are shown and assigned to interfacial layer degradation. Two methods to overcome endurance degradation in terms of proper choice of device geometry or program erase algorithms are highlighted. Moreover, statistical variation of FeFET memory states is characterized for single memory cells as well as mini arrays across wafer. This is complemented by 136 Kbit FeFET array results which demonstrate tail to tail separation of ~3mA which represents the basis for read out operations below 25 ns. Latest results from FeFET variability from 180nm x 180nm as well as 72nm x 72nm memory cells is presented and a 32 Mbit macro incorporating 180nm x 180nm cells has been designed for future characterization.
author_names: A Benoist

Johannes Ocker

Marko Noack

Georgi Krasimirov Kuzmanov

R Iqbal

D Le Minh

M Ghazaryan

V Anjaneyamoorthi

A Daraghmah

Menno Mennenga

Foroozan S Koushan

Fabio Tassan

Stefan Dunkel

Sven Beyer

Steven Soss

Ali Pourkeramati
title: Development status of gate first FeFET technology
venue: 2021 Symposium on VLSI Technology
year: 2021