Query: analysis adder area per bit

Candidate papers:

abstract: This paper proposes the use of alternative approximate adders for fully parallel energy efficient complementary metal oxide semiconductor (CMOS) finite impulse response (FIR) filters design. The filters to be approximated are first optimized for low power by a state of the art multiplier less multiple constant multiplication algorithm. We further evaluate magnitude error and accuracy for different state of the art approximate adder techniques plus the truncation of adders, and validate this with 16 bit audio signals histogram analysis. Once the approximation is performed for all the filters, we evaluate the signal to noise ratio (SNR) response for ten recorded audio signals. All precise and approximate filters benchmark cases with different SNR targets are synthesized and mapped onto a 45 nm CMOS PDK for full ASIC implementation. Energy efficiency results show that our proposed approximate filters, subject to a 50 dB Signal to Noise Distortion Ratio required floor, reduce on average the energy per filtered sample by up to 24.8 and 23.8 for 100 and 10 MHz circuit operation, respectively.
author_names: Leonardo Bandeira Soares

Eduardo Costa

Sergio Bampi
title: Design of area and energy efficient digital CMOS FIR filters with approximate adder circuits
year: 2016

abstract: A good VLSI Design is one with low area occupancy and high speed of operation. As per Moore's law the number of transistors on a chip, increase and so does the overall chip Area. Optimizing the parameters of Area and Delay is of high importance in VLSI Design. Performance analysis and comparison of Area occupancy and Delay has been performed for 4 adders the Ripple Carry Adder (Adder 1) the Kogge Stone Adder (Adder 2) the Carry Skip Adder (Adder 3) and the Brent Kung Adder (Adder 4) each being a 16 bit adder. The Adders were designed using Verilog code and then simulated and synthesized using RTL Encounter tool. Netlists were generated using the nclaunch tool for the three technologies. The Area and Delay results have been obtained for three technologies namely 180nm, 90nm and 45nm. At 180m, the Ripple Carry Adder occupies the least area of 1118nm2and Kogge Stone Adder has the smallest Delay of 3.495ns. At 90nm, the Ripple Carry Adder occupies the smallest Area of 315nm2 and the Kogge Stone Adder has the smallest delay of 2.957ns. The Ripple Carry Adder has a delay of 3.875ns in [3] The reduction of delay in the paper is 10.99% The Carry Skip Adder has a delay of 8.106ns in [3] and a reduction of 64.16% is obtained in this paper. The Kogge Stone Adder has a delay of 6.7ns in [3] A delay reduction of 63.65% is obtained in this paper. In [3] The Brent Kung Adder has a delay of 8.094ns. A reduction of 71.14% is obtained Amongst the four adders it has been found that the Brent Kung occupies the least Area of 123nm2 at 45nm and also has the smallest delay of 2.336 ns.
author_names: A Raghunandan

RAVISH ARADHYA H V
title: Area and Timing Analysis of Advanced Adders under changing Technologies
venue: 2019 4th International Conference on Recent Trends on Electronics, Information, Communication Technology (RTEICT)
year: 2019

abstract: As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16 bit adder circuit by Carry Select Adder (CSA) using different pass transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16 bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR) energy per instruction (EPI) Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.
author_names: Chinnaiyan Senthilpari

Krishna M Diwakar

Ajay Kumar Singh
title: Low Power, Low Latency, High Throughput 16 Bit CSA Adder Using Nonclocked Pass Transistor Logic
venue: J. Circuits Syst. Comput.
year: 2009

abstract: In this paper has discussion about the new design of pre encoded multiplier were explored at offline the standard co efficient and storing them in system memory. The co efficient was used in non redundant radix 4 signed digit (NR4SD) form. The proposed NR4SD encoding scheme uses one of the following sets of digit values 2, 1,0,+1} or 1,0,+1,+2} In order to cover the dynamic range of the 2's complement form, all digits of the proposed representation were encoded according to NR4SD except the most significant bit that was MB encoded. Pre encoding the standard coefficients are stored into ROM in a condensed form (i.e. 2 bits per digit) Compared to the pre encoded MB multiplier in which the encoded coefficients need 3 bits per digit, the proposed NR4SD scheme reduces the memory size. Also, compared to the MB form, which uses five digit values 2, 1,0,+1,+2}.This encoding technique was less complex partial product implementation, less area and more power efficient design. Analysis was verifying the proposed system was efficient from the existing system.
author_names: Jyothi Maddala

T Neelima
title: Novel NAND NR4SD Encoding of Low Power Carry Skip adder based On Pre Encoded Multipliers
year: 2017

abstract: This paper explains an efficient design and analysis of binary adders using Quantum dot cellular Automata (QCA) tools. Main goal of this work such as faster speed, smaller size, and less area than transistor based technology. The 64 bit binary adders are modeled using cell minimization techniques and detailed simulation using QCAD. Techniques are used two cells inverter and suitable arrangement of cells without overlapping of neighboring cells. These structures are designed with minimum number of cells in adders by using cell minimization techniques Performance of 64 bit adder results the less area, delay and achieved the minimum area delay product (ADP)
author_names: K Sabitha Banu

P Karuppasamy

Sathish Kumar Selvaperumal

P Nedumal Pugazhenthi
title: Modal based analysis of binary adders with fault tolerance using QCA in marine applications
year: 2017

abstract: Asynchronous quasi delay insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. The literature proposes several QDI design templates with different trade offs, giving designers a large spectrum of options to use, adapt or even mix. Among these, NULL Convention Logic (NCL) NCL+ Autonomous Signal Validity Half Buffer (ASVHB) and Sleep Convention Logic (SCL) are potential alternatives for low and ultra low power applications. This paper evaluates these four QDI templates through an 8 bit Kogge Stone full adder case study, showing analysis on cycle time, energy per operation, leakage power, energy delay product (EDP) leakage delay product (LDP) and area consumption. It also qualitatively evaluates each template, pointing out specific characteristics that can be suitable for low power applications.
author_names: Ricardo A Guazzelli

Matheus T Moreira

Ney Laert Vilar Calazans
title: A comparison of asynchronous QDI templates using static logic
venue: 2017 IEEE 8th Latin American Symposium on Circuits Systems (LASCAS)
year: 2017

abstract: Compared with performance of adder's implement mode such as delay,power and area and so on,two design schemes adopt carry look ahead adder to suit structural character and demand of high speed,low power for DSP compatible with TMS320C54X;overpass performance compare and result analysis for two design schemes,finally grouping structure of a partion per four bits is adopted and design of 40 bit adder of DSP has been finished.
author_names: Zhang Sheng-bing
title: Design of Adder Based on DSP Processor
year: 2007

abstract: The main contribution of this study is the development of an area /energy efficient cascaded direct truncation (DT) datapath with the so called static floating point (SFP) arithmetic to realize a low delay analysis filter bank (AFB) for digital hearing aids. In the proposed SFP LPFIR (linear phase finite impulse response) filter engine, lower silicon area and lesser power consumption facilitate better SNR performance than that achieved with the conventional post truncation (PT) datapath with integer arithmetic. Moreover, in the proposed LPFIR filter engine, a cascaded 16 bit SFP A M S Acc datapath is used that consists of two embedded 1 bit shifters to improve hardware usage and parallelism, one 16 bit DT adder (A) one 16 bit DT multiplier (M) one 16 bit barrel shifter (S) and one 16 bit DT accumulator (Acc) The operations per cycle (OPC) of the proposed SFP LPFIR filter engine reaches 6, which enables efficient fabrication of the low latency AFB for hearing aids. To verify the effectiveness of the proposed 16 bit SFP LPFIR filter engine, a 10 ms 18 band quasi ANSI S1.11 1/3 octave AFB for digital hearing aids was implemented using UMC 90 nm CMOS technology. The AFB was operated at 792kHz to process, in real time, 24kHz audio, with the power consumption being approximately 80.6uW (at 1V) Compared to the previous design in which the conventional PT datapath with integer arithmetic was used, approximately 9.6% of total power and 8.3% of silicon area were saved and almost the same SNR (signal to noise ratio) performance was achieved with the new system, when evaluated by a 3.96 s sequence of Mandarin speech. This paper presents an area /energy efficient FIR filter engine for hearing aids.The proposed FIR filter engine exploits the static floating point (SFP) arithmetic.A low power 18 band quasi ANSI S1.11 1/3 octave filter bank is implemented.
author_names: Shih-Hao Ou

Kuo-Chiang Chang

Chih-Wei Liu
title: An energy efficient, high precision SFP LPFIR filter engine for digital hearing aids
venue: Integr.
year: 2015

abstract: This paper mainly focuses on pass logic based design, which gives an low Energy Per Instruction (EPI) and high throughput COrdinate Rotation Digital Computer (CORDIC) cell for application of robotic exploration. The basic components of CORDIC cell namely register, multiplexer and proposed adder is designed using pass transistor logic (PTL) design. The proposed adder is implemented in bit.parallel iterative CORDIC circuit whereas designed using DSCH2 VLSI CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The propagation delay, area and power dissipation are calculated from the simulated results for proposed adder based CORDIC cell. The EPI, throughput and effect of temperature are calculated from generated layout. The output parameter of generated layout is analysed using BSIM4 advanced analyzer. The simulated result of the proposed adder based CORDIC circuit is compared with other adder based CORDIC circuits. From the analysis of these simulated results, it was found that the proposed adder based CORDIC circuit dissipates low power, gives faster response, low EPI and high throughput.
author_names: Velrajkumar Pitchandi

Senthil kumar Chinnaiyan

Murthy Gajula Ramana

W E Kiong
title: Design of Low EPI and High Throughput Cordic Cell to Improve the Performance of Mobile Robot
year: 2014

abstract: The multiplier speed is a necessary feature because the multiplier forms a vital part of several systems like FIR filters, microprocessors, DSPs etc. The multiplier is slow as compared to other parts of the system thus it is the speed determining factor of the system. An improvement in multiplier speed eventually end up in an improvement in speed of the overall system. The multiplier speed not solely depends on the multiplication technique used it additionally depends on the sort of adder employed for the addition of the partial product. The proposed work is relies on the vedic multiplication technique and high speed modified Kogge Stone adders are used. An 8 bit multiplier is complete victimization changed 4 bit multipliers which intern area unit complete victimization changed 2bit vedic multipliers. The design is simulated using Xilinx 14.7 software tool.
author_names: Vegireddi Swapna

Nihar Panda

Bandi Sarada
title: Performance analysis of 32 bit vedic multiplier design using nikilam and kogge stone adder
year: 2019