Query: There is plenty of Room aT the top

Candidate papers:

abstract: From bottom to top The doubling of the number of transistors on a chip every 2 years, a seemly inevitable trend that has been called Moore's law, has contributed immensely to improvements in computer performance. However, silicon based transistors cannot get much smaller than they are today, and other approaches should be explored to keep performance growing. Leiserson et al. review recent examples and argue that the most promising place to look is at the top of the computing stack, where improvements in software, algorithms, and hardware architecture can bring the much needed boost. Science, this issue p. eaam9744 BACKGROUND Improvements in computing power can claim a large share of the credit for many of the things that we take for granted in our modern lives: cellphones that are more powerful than room sized computers from 25 years ago, internet access for nearly half the world, and drug discoveries enabled by powerful supercomputers. Society has come to rely on computers whose performance increases exponentially over time. Much of the improvement in computer performance comes from decades of miniaturization of computer components, a trend that was foreseen by the Nobel Prize winning physicist Richard Feynman in his 1959 address, "There's Plenty of Room at the Bottom," to the American Physical Society. In 1975, Intel founder Gordon Moore predicted the regularity of this miniaturization trend, now called Moore's law, which, until recently, doubled the number of transistors on computer chips every 2 years. Unfortunately, semiconductor miniaturization is running out of steam as a viable way to grow computer performance there isn't much more room at the "Bottom." If growth in computing power stalls, practically all industries will face challenges to their productivity. Nevertheless, opportunities for growth in computing performance will still be available, especially at the "Top" of the computing technology stack: software, algorithms, and hardware architecture. ADVANCES Software can be made more efficient by performance engineering: restructuring software to make it run faster. Performance engineering can remove inefficiencies in programs, known as software bloat, arising from traditional software development strategies that aim to minimize an application's development time rather than the time it takes to run. Performance engineering can also tailor software to the hardware on which it runs, for example, to take advantage of parallel processors and vector units. Algorithms offer more efficient ways to solve problems. Indeed, since the late 1970s, the time to solve the maximum flow problem improved nearly as much from algorithmic advances as from hardware speedups. But progress on a given algorithmic problem occurs unevenly and sporadically and must ultimately face diminishing returns. As such, we see the biggest benefits coming from algorithms for new problem domains (e.g. machine learning) and from developing new theoretical machine models that better reflect emerging hardware. Hardware architectures can be streamlined for instance, through processor simplification, where a complex processing core is replaced with a simpler core that requires fewer transistors. The freed up transistor budget can then be redeployed in other ways for example, by increasing the number of processor cores running in parallel, which can lead to large efficiency gains for problems that can exploit parallelism. Another form of streamlining is domain specialization, where hardware is customized for a particular application domain. This type of specialization jettisons processor functionality that is not needed for the domain. It can also allow more customization to the specific characteristics of the domain, for instance, by decreasing floating point precision for machine learning applications. In the post Moore era, performance improvements from software, algorithms, and hardware architecture will increasingly require concurrent changes across other levels of the stack. These changes will be easier to implement, from engineering management and economic points of view, if they occur within big system components: reusable software with typically more than a million lines of code or hardware of comparable complexity. When a single organization or company controls a big component, modularity can be more easily reengineered to obtain performance gains. Moreover, costs and benefits can be pooled so that important but costly changes in one part of the big component can be justified by benefits elsewhere in the same component. OUTLOOK As miniaturization wanes, the silicon fabrication improvements at the Bottom will no longer provide the predictable, broad based gains in computer performance that society has enjoyed for more than 50 years. Software performance engineering, development of algorithms, and hardware streamlining at the Top can continue to make computer applications faster in the post Moore era. Unlike the historical gains at the Bottom, however, gains at the Top will be opportunistic, uneven, and sporadic. Moreover, they will be subject to diminishing returns as specific computations become better explored. Performance gains after Moore's law ends. In the post Moore era, improvements in computing power will increasingly come from technologies at the "Top" of the computing stack, not from those at the "Bottom" reversing the historical trend. CREDIT: N. CARY/SCIENCE The miniaturization of semiconductor transistors has driven the growth in computer performance for more than 50 years. As miniaturization approaches its limits, bringing an end to Moore's law, performance gains will need to come from software, algorithms, and hardware. We refer to these technologies as the "Top" of the computing stack to distinguish them from the traditional technologies at the "Bottom" semiconductor physics and silicon fabrication technology. In the post Moore era, the Top will provide substantial performance gains, but these gains will be opportunistic, uneven, and sporadic, and they will suffer from the law of diminishing returns. Big system components offer a promising context for tackling the challenges of working at the Top.
author_names: Charles E Leiserson

Neil C Thompson

Joel S Emer

Bradley C Kuszmaul

Butler W Lampson

Daniel S Sanchez

Tao B Schardl
title: There's plenty of room at the Top: What will drive computer performance after Moore's law?
venue: Science
year: 2020

abstract: Abstract Richard Feynman's famous words, "there's plenty of room at the bottom," referred to the opportunities for revolutionizing the electronics industry by developing the science and technology of how to manufacture very small components (sub micron to nanometer sized features) [1] In additive manufacturing (AM) the opposite may be true: There's plenty of room at the top. AM's strength is in the low volume production of complex components, which is demanded in big industries such as oil and gas, construction, tooling, wind and water turbines, and infrastructure. Is AM's 'big' future in the manufacture of large structures? This special issue surveys the technical challenges and enormous opportunities associated with large scale additive manufacturing while discussing the materials, processes and applications that are enabled by scaling to much larger structures, much faster speeds and lower manufacturing costs. The authors believe that, if Professor Feynman was alive, he'd say "There's plenty of room at the top."
author_names: L J Love

Brian K Post

Mark W Noakes

Andrzej Nycz

Vlastimil Kunc
title: There's plenty of room at the top
year: 2020

abstract: The virtuous cycle of integrated circuit technology advancement has been sustained for over 50 years, resulting in the proliferation of information technology (IT) with dramatic economic and social impact. Although there is still some "room at the bottom" today to manipulate and control matter at ever smaller scales, physics and economics limit the benefits of further transistor scaling. This paper discusses how the computational functionality and energy efficiency of microchips can be enhanced by integrating MEM switches on top of transistors, to sustain the IT revolution.
author_names: Tsu-Jae King Liu

Urmita Sikder

Kimihiko Kato

Vladimir M Stojanovic
title: There's plenty of room at the top
venue: 2017 IEEE 30th International Conference on Micro Electro Mechanical Systems (MEMS)
year: 2017

abstract: Channelling chemical intuition to conquer larger scales.
author_names: Charles E Leiserson

Neil C Thompson

Joel S Emer

Bradley C Kuszmaul

Butler W Lampson

Daniel S Sanchez

Tao B Schardl
title: There's plenty of room at the top
venue: Nature Nanotechnology
year: 2019

author_names: Stephanie Jane Richards Howard

Kathy Jo Wetter
title: Nanotechnology and Geopolitics: There's Plenty of Room at the Top
year: 2018

abstract: There is a growing realization that the expected fault rates and energy dissipation stemming from increases in CMOS integration will lead to the abandonment of traditional system reliability in favor of approaches that offer reliability to hardware induced errors across the application, runtime support, architecture, device and integrated circuit (IC) layers. Commercial stakeholders of multimedia stream processing (MSP) applications, such as information retrieval, stream mining systems, and high throughput image and video processing systems already feel the strain of inadequate system level scaling and robustness under the always increasing user demand. While such applications can tolerate certain imprecision in their results, today's MSP systems do not support a systematic way to exploit this aspect for cross layer system resilience. However, research is currently emerging that attempts to utilize the error tolerant nature of MSP applications for this purpose. This is achieved by modifications to all layers of the system stack, from algorithms and software to the architecture and device layer, and even the IC digital logic synthesis itself. Unlike conventional processing that aims for worst case performance and accuracy guarantees, error tolerant MSP attempts to provide guarantees for the expected performance and accuracy. In this paper we review recent advances in this field from an MSP and a system (layer by layer) perspective, and attempt to foresee some of the components of future cross layer error tolerant system design that may influence the multimedia and the general computing landscape within the next ten years.
author_names: Yiannis Andreopoulos
title: Error Tolerant Multimedia Stream Processing: There's Plenty of Room at the Top (of the System Stack)
venue: IEEE Transactions on Multimedia
year: 2013

abstract: Due to the possibility of nanotechnology becoming the next general purpose technology, generating considerable socio economic benefits, it has become popular with policy makers and academics around the world, and led to massive investments in national R&D programmes. While in some cases nanotechnology is still in its early stages of research, in many others it has already resulted in innovations within many disparate sectors. This is important because in today's knowledge based economy, innovation is a dominant factor, quite radically influencing economic performance of firms, regions, and states alike emphasizing a growing need for a strong, coherent, and up to date policy support. From an innovation systems perspective this thesis looks at the rapidly growing field of nanotechnology in the Czech Republic, exploring the innovation policy of the Czech Republic, barriers to innovation, and the extent to which policy addresses these barriers. An innovation survey within Czech nano companies has been carried out in order to zoom in on some of the strengths and weaknesses of the policy support. (Less)
author_names: Stepan Bartl
title: There's plenty of room at the bottom but is there room at the top? Nanotechnology in the Czech Republic: policy and barriers to innnovation
year: 2013

abstract: Microchip manufacturers have developed a tremendous skill in depositing materials at the nanometer scale. One can wonder why this skill is predominantly used to develop new generations of memory and signal processing chips. The answer lies in the economic rationale behind Moore's Law,1 implying that straightforward miniaturization is the most predictable and effective means of improving the microchip value. But today, the end of traditional scaling is in sight. According to the authoritative ITRS Roadmap,2 the miniaturization of CMOS, DRAM and flash memory technologies will end around the year 2018, at which point disruptive approaches will become necessary to further decrease the cost per function in these types of microchips. The community therefore has embarked on a massive parallel search for new technologies, employing the same microtechnology skill set, but introducing novel device architectures and novel materials. Examples are subthermal switches3 and magnetic memories such as the STT MRAM,4 among many. Innovation in microchip technology can also involve the addition of new functionality to the chip, often denominated as "more than Moore" When a microchip goes beyond the traditional functions of data storage, computation and electrical communication, it may become more valuable. Usually this requires modifications to the microchip fabrication process. Such modifications are reviewed in this chapter. We will first discuss the physical location where new functions can be added to a microchip, and which considerations may lead to the above IC approach. Then, the boundary conditions for post processing are sketched. A variety of example microsystems is subsequently reviewed, followed by the conclusions.
author_names: Jurriaan Schmitz
title: Microchip post processing: There is plenty of room at the top
year: 2013

author_names: Paul J Chirik
title: An FeVI nitride: there is plenty of room at the top!
venue: Angewandte Chemie
year: 2006

author_names: Paul J Chirik
title: An Fe(VI) Nitride: There Is Plenty of Room at the Top
year: 2007