Query: Analog memristive memory with applications in Audio signal storage

Candidate papers:

abstract: Since the development of the HP memristor, much attention has been paid to studies of memristive devices and applications, particularly memristor based nonvolatile semiconductor memory. Owing to its unique properties, theoretically, one could restart a memristor based computer immediately without the need for reloading the data. Further, current memories are mainly binary and can store only ones and zeros, whereas memristors have multilevel states, which means a single memristor unit can replace many binary transistors and realize higher density memory. It is believed that memristors can also implement analog storage besides binary and multilevel information memory. In this paper, an implementation scheme for analog memristive memory is considered. A charge controlled memristor model is derived and the corresponding SPICE model is constructed. Special write and read operations are demonstrated through numerical analysis and circuit simulations. In addition, an audio analog record/play system using a memristor crossbar array is designed. This system can provide great storage capacity (long recording time) and high audio quality with a simple small circuit structure. A series of computer simulations and analyses verify the effectiveness of the proposed scheme.
author_names: Shukai Duan

Xiaofang Hu

Lidan Wang

Chuandong Li
title: Analog memristive memory with applications in audio signal processing
venue: Science China Information Sciences
year: 2013

abstract: Memristor, a two terminal device with dynamic conductance depending on the charge or the flux flowing it was predicted by Leon Chua about four decades ago and named the fourth fundamental circuit element. In 2008, Hewlett Packard (HP) laboratory announced they have found the missing memristor in nano scale physical device. Since that memristor has garnered extensive interests among numerous researchers and proposed in many applications. In this paper, an implement scheme of a memristive multilevel memory with a single unit storing a bit multilevel information (several bits of binary data) is presented. A record/play system with the memristive multilevel memory is designed as an application in audio signal storage. Due to the multilevel memory ability and nano scale size of the memristor, this design possesses simpler, smaller circuit structure, greater data density and nonvolatile. A series of computer simulations verify the effectiveness of the memristive memory and provide a new solution for audio signal storage and processing.
author_names: Xiaofang Hu

Shukai Duan

Lidan Wang
title: Memristive Multilevel Memory with Applications in Audio Signal Storage
venue: AICI
year: 2011

abstract: Neural networks (NN) have been widely used in various applications. However, the high computational complexity and energy consumption of NNs impede their deployment on embedded and mobile platforms, where computational resources and energy are limited. Most of the existing accelerators are based on traditional Von Neumann(VN) architecture, which separates computing from storage, and the massive data movement between the processor and off chip memory causes great power consumption. In memory computing (IMC) architecture integrates computing and storage together to eliminate explicit memory access, reducing energy hungry data transmission. On the other hand, binary neural network (BNN) restricts the weight and activation value to either 1 or +1, converting a large number of multiplications into simple bit wise XNOR logical operations, and significantly reduces the complexity of computation and amount of memory access. We propose an energy efficient in memory BNN architecture that performs matrix vector multiplication (MxV) of FC layers. The bit wise XNOR operation is realized on the bit line of SRAM, making the data fetching is part of the computation. The accumulation and binarization are performed in time domain with analog and digital mixed signal processing, which can be blended with SRAM to minimize the data transmission overhead. In the operating condition of TT 0.5V 25 c 50MHZ, the energy efficiency is 96.249 TOPS/W, surpassing the conventional digital implementation with similar performance by 2.09x.
author_names: Tao Wang

Weiwei Shan
title: An Energy Efficient In Memory BNN Architecture With Time Domain Analog and Digital Mixed Signal Processing
venue: 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
year: 2019

abstract: Mapping neuro inspired algorithms to sensor backplanes of on chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non volatile memory technologies. Recently, a memristive multi level memory cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.
author_names: Aidana Irmanova

A P James
title: Neuron inspired data encoding memristive multi level memory cell
venue: ArXiv
year: 2018

abstract: Analog memory is of great importance in neurocomputing technologies field, but still remains difficult to implement. With emergence of memristors in VLSI technologies the idea of designing scalable analog data storage elements finds its second wind. A memristor, known for its history dependent resistance levels, independently can provide blocks of binary or discrete state data storage. However, using single memristor to save the analog value is practically limited due to the device variability and implementation complexity. In this paper, we present a new design of discrete state memory cell consisting of sub cells constructed from a memristor and its resistive network. A memristor in the sub cells provides the storage element, while its resistive network is used for programming its resistance. Several sub cells are then connected in parallel, resembling potential divider configuration. The output of the memory cell is the voltage resulting from distributing the input voltage among the sub cells. Here, proposed design was programmed to obtain 10 and 27 different output levels depending on the configuration of the combined resistive networks within the sub cell. Despite the simplicity of the circuit, this realization of multilevel memory provides increased number of output levels compared to previous designs of memory technologies based on memristors. Simulation results of proposed memory are analyzed providing explicit data on the issues of distinguishing discrete analog output levels and sensitivity of the cell to oscillations in write signal patterns.
author_names: Aidana Irmanova

A P James
title: Multi level memristive memory with resistive networks
venue: 2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)
year: 2017

abstract: As the fourth basic electronic component, the application fields of the memristive devices are diverse. The digital resistive switching with sudden resistance change is suitable for the applications of information storage, while the analog memristive devices with gradual resistance change are required in the neural system simulation. In this paper, a transparent device of ZnO films deposited by the magnetron sputtering on indium tin oxides (ITO) glass was firstly prepared and found to show typical analog memristive switching behaviors, including an I V curve that exhibits a 'pinched hysteresis loops' fingerprint. The conductive mechanism of the device was discussed, and the LTspice model was built to emulate the pinched hysteresis loops of the I V curve. Based on the LTspice model and the Pavlov training circuit, a conditioned reflex experiment has been successfully completed both in the computer simulation and the physical analog circuits. The prepared device also displayed synapses like characteristics, in which resistance decreased and gradually stabilized with time under the excitation of a series of voltage pulse signals.
author_names: Tie Dong Cheng

Jingjing Rao

Xingui Tang

Lirong Yang

Nan Liu
title: Analog Memristive Characteristics and Conditioned Reflex Study Based on Au/ZnO/ITO Devices
year: 2018

abstract: Advances in electronics have revolutionized the way people work, play and communicate with each other. Historically, these advances were mainly driven by CMOS transistor scaling following Moore's law, where new generations of devices are smaller, faster, and cheaper, leading to more powerful circuits and systems. However, conventional scaling is now facing major technical challenges and fundamental limits. New materials, devices, and architectures are being aggressively pursued to meet present and future computing needs, where tight integration of memory and logic, and parallel processing are highly desired. To this end, one class of emerging devices, termed memristors or memristive devices, have attracted broad interest as a promising candidate for future memory and computing applications. Besides tremendous appeal in data storage applications, memristors offer the potential to enable efficient hardware realization of neuromorphic and analog computing architectures that differ radically from conventional von Neumann computing architectures. In this review, we analyze representative memristor devices and their applications including mixed signal analog digital neuromorphic computing architectures, and highlight the potential and challenges of applying such devices and architectures in different computing applications.
author_names: Mohammed Affan Zidan

An Chen

Giacomo Indiveri

Wei Lu
title: Memristive computing devices and applications
venue: Journal of Electroceramics
year: 2017

abstract: Due to their specific memory effects, memristive systems are potentially useful building blocks for innovative implementations of classical techniques of nonlinear analog signal processing. This paper discusses such properties of memristive systems which would amplify their usefulness in concrete applications. It turns out that systems behaving as ideal memristors may not be suitable candidates for such implementations. Attention is paid to a simple memristive system with threshold switching as a potentially useful building block for various analog applications.
author_names: Dalibor Biolek

Viera Biolkova

Zdenek Kolka
title: Memristive systems for analog signal processing
venue: 2014 IEEE International Symposium on Circuits and Systems (ISCAS)
year: 2014

abstract: Memristive devices have been a hot topic in nanoelectronics for the last two decades in both academia and industry. Originally proposed as digital (binary) nonvolatile random access memories, research in this field was predominantly driven by the search for higher performance solid state drive technologies (e.g. flash replacement) or higher density memories (storage class memory) However, based on their large dynamic range in resistance with analog tunability along with complex switching dynamics, memristive devices enable revolutionary novel functions and computing paradigms. We present the prospects, opportunities, and materials challenges of memristive devices in computing applications, both near and far terms. Memristive devices offer at least three main types of novel computing applications: in memory computing, analog computing, and state dynamics. We will present the status in the understanding of the most common redox based memristive devices while addressing the challenges that materials research will need to tackle in the future. In order to pave the way toward novel computing paradigms, a rational design of the materials stacks will be required, enabling nanoscale control over the ionic dynamics that gives these devices their variety of capabilities.
author_names: Regina Dittmann

John Paul Strachan
title: Redox based memristive devices for new computing paradigm
venue: APL Materials
year: 2019

abstract: This study introduces a feasible read/write technique applicable to the diverse applications of memristive devices including neuromorphic circuits, logic units, and memory devices. Interest on memristive devices keeps growing in the electronics industry thanks to their nonvolatile property and lower layout density. The proposed readout circuitry is primarily designed for multi bit logic operations, which enables its use of large scale biomimicking circuits. The architecture combines bit select decoders, read and write switches for each bit, operational transconductance amplifiers (OTA) connected to readout circuit and an analog to digital converter (ADC) to digitalize the signal coming from memristor. Our investigations on various circuit configurations suggest the utilization of a second order Delta Sigma ADC operating with an oversampling ratio (OSR) of 256 and a sampling frequency of 128 kHz. An isolation amplifier is utilized to reduce the loading effects between memristor and ADC. As compared to others, the second order modulator with isolation amplifier demonstrates linear characteristics in multi bit operations. The whole circuit uses a single type of two stage opamp design that combines a Miller capacitor and voltage follower in the feedback path for compensation. Overall design works successfully for memristorbased single and multi bit reading operations.
author_names: Seyma Songul Ozdilli

Dincer Gokcen
title: Design of a Second Order Delta Sigma ADC Based Read/Write Circuit for Memristive Crossbar Arrays
venue: 2019 3rd International Symposium on Multidisciplinary Studies and Innovative Technologies (ISMSIT)
year: 2019