Query: reliabilty semiconductor presspack

Candidate papers:

abstract: espanolEl agresivo escalamiento de la tecnologia de proceso CMOS plantea serios desafios en la fiabilidad de los circuitos integrados debido a las estrictas condiciones de funcionamiento y al aumento de las variaciones de los parametros de proceso. La fiabilidad se ha convertido en una preocupacion importante de la industria de semiconductores y debe ser mejorado con cada nodo tecnologico con el fin de mejorar el "yield" del proceso. Desde la perspectiva de semiconductores, fiabilidad es la capacidad de un dispositivo para realizar su funcion bajo determinadas condiciones por un periodo especifico de tiempo. Un dispositivo semiconductor falla cuando los parametros de respuesta de el dispositivo ya no pueden realizar su funcion prevista. El fallo del dispositivo puede ocurrir en cualquier momento de la vida del dispositivo. A medida que la tecnologia CMOS se escala, la probabilidad de la presencia de defectos de fabricacion, tales como defectos tipo abiertos y puentes, aumenta debido a la tasa de crecimiento de las interconexiones. Algunos de estos defectos son dificiles de detectar por metodos de test tradicionales y podrian dar lugar a "test escapes" causando serios problemas de fiabilidad. Por otro lado, "soft errors" o "errores suaves" han surgido como una importante preocupacion de fiabilidad en memorias SRAM debido a las menores capacitancia en nodos del circuito y a las condiciones de funcionamiento mas rigurosas. Las contribuciones de este trabajo de tesis son: Un analisis de riesgo en la fiabilidad de defectos de fabricacion tipo abierto en "vias" El riesgo de fiabilidad es cuantificado estimando el tiempo medio entre fallos (Mean Time to Failure MTF) en funcion del tamano del defecto. Tres modelos de defectos en vias son considerados. De los resultados obtenidos, se concluye que las reglas de diseno deben mejorarse teniendo en cuenta el riesgo en la fiabilidad por electromigracion debido a la presencia de defectos abiertos resistivos. Una metodologia para mejorar la deteccion de defectos tipo puente. En este trabajo se muestra que a pesar de las variaciones del proceso, combinando Bajo VDD y "Reverse Body Bias" (RBB) mejora la deteccion de defectos puente. Ademas, un simulador que determina la cobertura de deteccion de este tipo de defectos es desarrollado. El simulador esta basado en un marco de analisis estadistico de tiempos para calcular la probabilidad de deteccion de defectos tipo puente para diferentes combinaciones de VDD y RBB. Un analisis de fiabilidad en celdas de memoria SRAM basadas en FinFETs debido al impacto de particulas de radiacion. En este trabajo, la respuesta transitoria de una celda SRAM FinFET al impacto de particula de radiacion es analizada utilizando simulaciones TCAD. Se demuestra que en FinFETs, el mecanismo de coleccion de carga es diferente a los transistores CMOS planares, ya que depende de la ubicacion y direccion del impacto. De igual manera se analiza el efecto de incrementar el numero de aletas y la altura de la aleta en el mecanismo de coleccion de carga. Como resultado del analisis, se propone una nueva metrica para quantificar la robustez a efectos de radiacion de una celda de memoria SRAM FinFET. EnglishThe aggressive scaling of CMOS process technology poses serious challenges on the lifetime reliability of ICs due to the stringent operating conditions and the increase of process parameter variations. Reliability has become an important concern of semiconductor industry and should be improved with each scaled technological node in order to enhance yield. As technology scales down, the likelihood of manufacturing defects such as open and bridge defects increases due to the growth rate of interconnections. Some of these defects are hard to be detected by traditional test methods and could result in test escapes posing reliability issues. In addition, soft errors have emerged as an important reliability concerns in SRAM memories due to lower node capacitance and more stringent operating conditions. Thus, the main contributions of this thesis are: An analysis of the reliability risk of resistive open vias: The aggravated via reliability due to a manufacturing narrowing defect is analyzed. The reliability risk is quantified by estimating the mean time to failure (MTF) as a function of the void size due to narrowing by applying Black's law to three possible geometric models for a defective via. The obtained results suggest a negative impact on chip level reliability analysis that is based on the element level failure probability that is a function of its MTF. A methodology to improve the detection of reliability resistive bridge defects.In this work it is shown that in spite of process variations, combining Low VDD and reverse body bias (RBB) improve bridge defect detection. The methodology is applied to ISCAS benchmark circuit in a commercial 65nm CMOS technology to determine the test conditions (VDD and RBB values) to improve the fault coverage of circuits. The obtained results show clearly that the SFC increases significantly when VDD is lowered, and increases even more when RBB is applied at Low VDD. In addition, the obtained results suggest that the final VDD and RBB values should be selected based on the tradeoff between desired fault coverage and test time penalization. A reliability analysis of FinFET SRAM cells to single event upsets. In this work the transient response of FinFET SRAM cell to heavy ion strikes is analyzed by TCAD Sentaurus simulations. It is shown that the charge collection mechanism in FinFET devices is different in comparison to CMOS planar devices. This is because FinFET transistor is a non planar device. Due to of this, two ion strike directions are considered in simulations: k direction and j direction. The obtained results show the collected charge of the FinFET transistor depends on the strike direction. Heavy ions require more energy to cause a bit flip when they strike in j direction than when they strike in k direction. In addition, the effect of channel width modulation on collected charge and critical charge by increasing the number of fins (NFIN) and the fin height (HFIN) of the FinFET is analyzed. The results obtained suggest that the critical charge is not enough to quantified the FinFET SRAM cell hardening. Therefore, a robustness metric is proposed. The metric considers the impact of increasing HFIN and NFIN on the critical charge and on the collected charge. catalaL'escalat agressiu de la tecnologia CMOS presenta desafiaments seriosos per a la confiabilitat dels circuits integrats degut a les condicions estrictes de funcionament i augment de les variacions dels parametres del proces de fabricacio. En aquest sentit, la confiabilitat ha esdevingut en una preocupacio important per a la industria de semiconductors i s'ha de millorar a cada fita tecnologica per a millorar el rendiment del proces. Des de la perspectiva dels semiconductors, la confiabilitat es la capacitat que presenta un dispositiu de realitzar la seva funcio sota unes condicions determinades durant un temps concret. Un dispositiu semiconductor realitza fallada quan no pot realitzar la seva funcio. Aquesta fallada pot ocorrer en qualsevol moment de la vida del dispositiu. A mesura que la tecnologia CMOS es miniaturitza, la probabilitat d'ocurrencia de defectes de fabricacio, tals com oberts i/o curtcircuits augment degut a la tassa de creixement de les interconnexions. Alguns d'aquests defectes son dificils de detectar per metodes tradicionals i podrien donar lloc als coneguts com fallades de verificacio sent causa de problemes seriosos de confiabilitat. D'altra banda, durant els ultims anys s'ha observat la proliferacio dels anomenats errors tous que suposen una preocupacio important en la confiabilitat dels circuits de memoria SRAM degut a la reduccio dels condensador associats als seus nodes interns. En aquest sentit, les contribucions d'aquest treball son: Realitzacio d'una analisi de risc en la confiabilitat dels defectes de fabricacio de tipus obert en interconnexions entre capes de metall (o vies) El risc de confiabilitat s'ha quantificat realitzant una estimacio del temps mig entre fallades (MTF) en funcio de la grandaria del defecte. Dels resultats obtinguts es conclou que les regles de disseny s'han de millorar considerant el risc de confiabilitat degut a electromigracio causada per la presencia de defectes tipus obert resistius. Desenvolupament d'una metodologia per a la deteccio de defectes tipus curtcircuit. En aquest treball es mostra que tot i les variacions del proces, la combinacio d'una tensio d'alimentacio reduida juntament amb la polaritzacio del substrat millora la deteccio d'aquests defectes. D'altra banda s'ha desenvolupat un simulador que determina la cobertura d'aquest tipus de defectes, basat en un marc d'analisi estadistica d'intervals per a determinar la probabilitat de deteccio per diferents combinacions dels dos parametres esmentats. Realitzacio d'una analisi de confiabilitat de cel*les de memoria SRAM basades en dispositius tipus FinFETS degut a l'impacte de particules ionitzants. S'analitza la resposta transitoria d'una cel*la SRAM FinFET front a l'impacte de particules de radiacio utilitzant simulacions amb l'eina TCAD. Es demostra que en FinFETs el mecanisme de col*leccio de carrega es diferent al dels transistors CMOS planars, ja que depen de la posicio i direccio de l'impacte. De la mateixa forma s'analitza l'efecte d'incrementar el numero seccions i la seva alcada en el mecanisme de col*leccio de carrega. Com a resultat de l'analisi es proposa una nova metrica per a quantificar la robustesa front a efectes de la radiacio d'una cel*la de memoria SRAM FinFET
author_names: Hector Luis Villacorta Minaya
title: Reliabilty enhancement of nanometer scale digital circuits
year: 2016

title: bandoce waieo bondingeseo waieo gyeolhabryeoggwa sinroeseonge gwanhan yeongu WIRE BONDING STRENGTH AND RELIABILTY ON SEMICONDUCTOR ASSEMBLY PROCESS
year: 1986

abstract: Because of the increasing in power density of electronic devices for medium and high power application, reliabilty of these devices is of great interest. Understanding the avalanche behaviour of a power device has become very important in these last years because it gives an indication of the maximum energy ratings which can be seen as an index of the device ruggedness. A good description of this behaviour is given by the static IV blocking characteristc. In order to avoid self heating, very relevant in high power devices, very short pulses of current have to be used, whose value can change from few milliamps up to tens of amps. The most used method to generate short pulses is the TLP (Transmission Line Pulse) test, which is based on charging the equivalent capacitance of a transmission line to high value of voltage and subsequently discharging it onto a load. This circuit let to obtain very short square pulses but it is mostly used for evaluate the ESD capability of semiconductor and, in this environment, it generates pulses of low amplitude which are not high enough to characterize the avalanche behaviour of high power devices Advanced TLP circuit able to generate high current are usually very expensive and often suffer of distorption of the output pulse. In this article is proposed a simple, low cost circuit, based on a boosted TLP configuration, which is capable to produce very square pulses of about one hundreds of nanosecond with amplitude up to some tens of amps. A prototype is implemented which can produce pulses up to 20A of amplitude with 200 ns of duration which can characterize power devices up to 1600V of breakdown voltage. Usage of microcontroller based logic make the circuit very flexible. Results of SPICE simulation are provided, together with experimental results. To prove the effectiveness of the circuit, the I V blocking characteristics of two commercial devices, namely a 600V PowerMOS and a 1200V Trench IGBT, are measured at different operating temperature.
author_names: Michele Riccio

Giovanni Ascione

Giuseppe De Falco

Luca Maresca

Martina de Laurentis

Andrea Irace

Giovanni Breglio
title: Transmission line pulse system for avalanche characterization of high power semiconductor devices
venue: Microtechnologies for the New Millennium
year: 2013

abstract: IGBT power semiconductor modules have become of the utmost importance for traction applications. Their control circuitry is of much lower expenditure than those for GTOs. Power converters for tramways, elevators and railway locomotives will be equipped with IGBT modules in the future. However, the reliability of these power modules is still a serious concern, compared to the comparable good reliability of GTO presspack technology. Although first approaches have already been announced, the presspacking of IGBTs is a rather difficult and expensive process, because of the complex IGBT structure and the wafer processing yields in IGBT wafer manufacturing. On the other hand, tough operation conditions in case of traction applications cause reliability requirements which need significant improvements of the present conventional wire bond/die attach module packaging technology. Reliability tests, which should represent traction operation of modules in the field, show that wire bonding and soldering may cause failures of the modules. The paper presents analysis results and ways of how these problems might be solved.
author_names: Peter Jacob

M Held

P Scacco

Wu-chen Wu
title: Reliability testing and analysis of IGBT power semiconductor modules
year: 1995

abstract: This paper reviews the industry roadmaps on commercial off the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC) The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA) The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN) a data driven PHM, was discussed in details. Finally, it presented inter and extra polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies.
author_names: Reza Ghaffarian
title: MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS
year: 2016

abstract: PROBLEM TO BE SOLVED: To provide a non solvent liquid silver paste formulation having high thermal conductivity and high reliabilty, formulation which does not contain a solvent, such as a viscosity modifier, since a low viscosity is achieved even in a silver paste containing a volume of silver powders, and to provide a semiconductor device using it. SOLUTION: The formulation, which combines a liquid thermosetting resin and spherical silver powders, is characterized by having a viscosity of =10 Pas at 5 rpm at room temperature and a heat conductivity of =6 W/mK. The semiconductor device uses this formulation. COPYRIGHT: (C)2005,JPO&NCIPI
author_names: Gang Hao Wei

Xin Jing Ke Fu

Yong Jing Huang

Shi Jing Li Zhao

Jian Ye Zheng Yi

Jian Jing Xiu Zheng
title: Solventless liquid silver paste composition and semiconductor device using the same
year: 2003

abstract: The integrated gate commutated thyristor and presspack power diodes have been successfully applied in medium voltage neutral point clamped converters in the power range from hundreds of kilowatt to tenths of megawatt. Responsible for driving key processes in the industry, high reliability and availability are crucial for these converters, since their repair or replacement after failure events may take too long. Given the vital importance of such equipment for the drive systems, they are equipped with protection schemes that are usually reliable, but not infallible. If the protection scheme of the converter does not work properly in a short circuit situation, serious damages may be expected on its power semiconductor devices. In this paper, the power semiconductors thermal behavior is investigated using finite element models in the COMSOL Multiphysics software. Three dimensional thermal models of the power devices were raised by industrial radiography techniques, aiming to expand the information provided by the manufacturers. The authors show how these results can be used in a real equipment to attenuate the catastrophic effects of the protection scheme malfunction, so limiting the damage pattern within the converter to their least complex power devices.
author_names: Anderson Vagner Rocha

Subhashish Bhattacharya

Giti Karimi Moghaddam

Richard D Gould

Helder de Paula

Braz de Jesus Cardoso Filho
title: Thermal Stress and High Temperature Effects on Power Devices in a Fault Resilient NPC IGCT Based Converter
venue: IEEE Transactions on Power Electronics
year: 2016

abstract: New assembly process of the substrates system with high performance has been establised by adopting the same bonding condition of both Cu sheet Mo sheet by vaccum diffusion bonding process and Cu sheet alumina by the adjusting Ti content in active brazing metal. The substrates system has been consisted by the conductors with three layered structure of Cu and Mo sheets, and 96% alumina as insulator, as already reported.The bond with high reliability of Cu and Mo sheets has made by vacuum diffusion bonding process under the condition of 1, 300K for 2, 400s under the pressure of 10 2 Pa. Furthermore, in order to assemble the substrates system with high performance by one processing stage, the bonding condition of Cu sheet and alumina requires to coincide with that of Cu and Mo sheets. It was shown experimen tally that the bond of Cu sheet alumina with high reliabilty was obtained by selecting nearly 30 wt% Ti powder mixed with Cu powder as active brazing metal. As the results, the assemly process of the both the conductor and the insulator Mo sheet, Cu sheet and alumina has been able to be achieved with bonding of one processing stage by adopting the bonding condition of 1, 300 K for 2, 400 s. In addition, it was also confirmed that voids or other defects are not observed in the bond interface by the inspection of SEM etc.
author_names: Yoshihiro Kashiba

Masaharu Moriyasu

Kazumichi Machida

Shuji Nakata
title: Design and Assembly Process of Substrates System for Power Semiconductor. (Report 3) Investigation of New Assembly Prcess of Substrates System with High Performance.
year: 1995

abstract: IGBT (Insulated Gate Bipolar Transistor) power semiconductor modules become of importance for traction applications. However, the reliability of these power modules is still a concern, compared to those of press packed GTOs. Although first IGBT press pack solutions have been presented to the market, IGBT presspacking remains difficult and expensive. Besides this, customers prefer module technology solutions, because of their economical advantage and easiness of device mounting. Reliability tests have been developed and modules have been analyzed to judge critical reliability points and to show ways for improvement.
author_names: Peter Jacob

M Held

P Scacco
title: IGBT power semiconductor reliability analysis for traction application
venue: Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits
year: 1995

abstract: Improvement in the reliability of grid connected inverters is desirable with their increasing use. Inverter reliability tests usually focus on thermal testing of semiconductor devices. Regenerative methods are adopted to minimize the energy consumed during these tests. Regeneration requires additional systems converters or passive components. In this paper, a novel method for thermal testing of the passive components associated with a grid connected inverter is proposed. The method can be used to test the output filter inductors, output ac filter capacitors and input dc electrolytic capacitors. Thermal stress affects the working life of capacitors and can cause insulation failure in inductors. Thermal testing of these passive components, besides the semiconductor device thermal testing, contributes to improved reliabilty of the grid connected inverter system. Unlike regenerative methods that require additional systems of high power rating, the proposed method circulates rated current within the three legs of the inverter under test. The only additional system required is a low power dc supply with variable output voltage. The variable dc input supplies the losses in the system under test. The applicability of the proposed test for both three wire and four wire grid connected inverter systems is discussed.
author_names: B Arun Karuppaswamy

Srinivas Gulur

Vinod John
title: A novel thermal performance evaluation method for inverter passive components
venue: 2015 IEEE International Transportation Electrification Conference (ITEC)
year: 2015