Query: Al2O3 based charge trap memory

Candidate papers:

abstract: In this paper, we review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. First, we provide a brief historical overview of the research in this field. We also provide a technological overview and the epoch making achievements, followed by an account of the current understanding of both bipolar and unipolar ReRAM operations. Finally, we summarize the challenges facing the ReRAM technology as it moves toward the beyond 2X nm generation of nonvolatile memories and the so called beyond complementary metal oxide semiconductor (CMOS) device.
author_names: Hiroyuki Akinaga

Hisashi Shima
title: Resistive Random Access Memory (ReRAM) Based on Metal Oxides
venue: Proceedings of the IEEE
year: 2010

abstract: This paper reviews recent advances in Charge Trap Flash (CTF) memories. CTFs are predicted to replace the traditional floating gate flash devices beyond the 32 nm node. The paper focuses on work done at IIT Bombay in the areas of both nitride based SONOS devices as well as nanocrystal (NC) based devices. For SONOS devices, results are presented for optimization of the nitride layer to obtain the best characteristics, and the simulation of the program/erase transients. For NC devices, experimental characteristics of single and dual layer cells, as well as simulation results are presented.
author_names: C Sandhya

P K Singh

Swati Kedia Gupta

Hitasha Chandar Rohra

M Shivatheja

Udayan Ganguly

Ralf Hofmann

Gautam Mukhopadhyay

Souvik Mahapatra

J M Vasi
title: Recent advances in charge trap flash memories
venue: 2009 2nd International Workshop on Electron Devices and Semiconductor Technology
year: 2009

abstract: Charge trapping is dramatically suppressed in ZnO transparent thin film transistors (TFTs) employing a multilayered gate insulator with HfO2 layer sandwiched by Al2O3 layers. In spite of its high dielectric constant, HfO2 has critical drawbacks including huge charge trap density in interfaces. We suggest and demonstrate an elegant solution to minimize the charge trapping introducing Al2O3 buffer layers. The operation of Al2O3/HfO2/Al2O3 multilayered gate insulator structure in the ZnO transparent TFT is evaluated to ensure the voltage difference in the hysteresis loop as low as 0.2V, and the immunization to the threshold voltage shift induced by repeated sweeps of gate voltage.
author_names: Seongpil Chang

Yong-Won Song

Sanggyun Lee

Sang Myeon Lee

Byeong Kwon Ju
title: Efficient suppression of charge trapping in ZnO based transparent thin film transistors with novel Al2O3/HfO2/Al2O3 structure
year: 2008

abstract: Abstract The program/erase (P/E) characteristic of tunnel barrier engineered charge trap flash (TBE CTF) memory with MAHOS (Metal/Al 2 O 3 /HfO 2 /SiO 2 /Si) structure and MAHAHOS (Metal/Al 2 O 3 /HfO 2 /Al 2 O 3 /HfO 2 /SiO 2 /Si) structure were investigated. The tunnel barrier structures for nonvolatile memory (NVM) application were designed by using the quantum mechanical tunnel model (QM) and then the CTF memory devices were fabricated by stacking various dielectric materials for tunnel barrier, charge trap layer and blocking layer. As a result, a faster P/E speed and a longer data retention time were obtained from the MAHAHOS memory device. Especially, the program speed was enhanced by 10 4 times from 100 ms to 10 us, and the erase speed was enhanced by 10 2 times from 1 s to 10 ms. Also, the MAHAHOS device showed an improved retention characteristic compared with the MAHOS device. In addition, it is found that a high work function gate electrode (Pt) contributes to a significant reduction of data erasing time and an improved data retention characteristic of MAHAHOS memory device.
author_names: Se-Man Oh

Hee-Wook You

Kwan-Su Kim

Young-Hie Lee

Won-Ju Cho
title: Electrical properties of HfO2 charge trap flash memory with SiO2/HfO2/Al2O3 engineered tunnel layer
year: 2010

abstract: MHOS (metal HfO2 SiO2 Si) structure capacitors were fabricated to investigate the charge trapping properties of HfO2 layer with various thicknesses for the applications of charge trap flash (CTF) memory devices. Also, the centroid of charge trap in HfO2 layer was extracted by constant current stress method and compared with that of conventional Si3N4 layer. The gate leakage current of MHOS capacitor due to tunneling was significantly reduced by stacking the HfO2 trap layer on thin SiO2 tunnel layer. The MHOS capacitors showed a larger memory window than the MNOS (metal Si3N4 SiO2 Si) capacitors at the same trap layer thickness, because the HfO2 layer has better charge trapping efficiency than the Si3N4 layer. It is found that ultrathin HfO2 trap layer with a thickness of 2 nm stored almost the same charges with Si3N4 layer with a thickness of 7 nm. Consequently, the application of ultrathin HfO2 to charge storage layer can considerably improve the performance and enhance the high density of CTF memory.
author_names: Hee-Wook You

Won-Ju Cho
title: Charge trapping properties of the HfO2 layer with various thicknesses for charge trap flash memory applications
year: 2010

abstract: A characterization technique capable of measuring the electrical charge injected during programming operations in silicon nitride based charge trapping memories has been developed. The trapping efficiency, defined as the fraction of carriers which gets trapped in the device with respect to the total injected charge, is extracted and is evaluated along the programming transient for a wide set of devices, featuring different material deposition techniques and different thicknesses. The trapping efficiency is found to be almost insensitive to the injection conditions, whereas it depends on the quantity of filled traps, the thickness of the trapping layer and the conduction band offset between the trapping layer and the top oxide. A higher trapping efficiency in general leads to faster programming transients and more effective programming when increasing the gate voltage.
author_names: Amit Suhane

Antonio Arreghini

Geert Van den bosch

Laurent Breuil

Antonio Cacciato

A Rothschild

Malgorzata Jurczak

Jan Van Houdt

Kristin De Meyer
title: Experimental evaluation of trapping efficiency in silicon nitride based charge trapping memories
venue: 2009 Proceedings of the European Solid State Device Research Conference
year: 2009

abstract: A new memory structure using threshold shifting from charge stored in nanocrystals of silicon (5nm in size) is described. The devices utilize direct tunneling and storage of electrons in the nanocrystals. The limited size and capacitance of the nanocrystals limit the numbers of stored electrons. Coulomb blockade effects may be important in these structures but are not necessary for their operation. The threshold shifts of 0.2 0.4 V with read and write times less than 100's of a nanosecond at operating voltages below 2.5 V have been obtained experimentally. The retention times are measured in days and weeks, and the structures have been operated in an excess of 109 cycles without degradation in performance. This nanomemory exhibits characteristics necessary for high density and low power.
author_names: Sandip Tiwari

Farhan Rana

Hussein Ibrahim Hanafi

Allan Hartstein

Emmanuel F Crabbe

Kevin K H Chan
title: A silicon nanocrystals based memory
year: 1996

abstract: Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g. including Fin Fets. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques
author_names: Karl-Heinz Kuesters

Christoph Ludwig

Thomas Mikolajick

Nicolas Nagel

Michael Specht

V Pissors

N Schulze

E Stein

Josef Willer
title: Future trends in charge trapping memories
venue: 2006 8th International Conference on Solid State and Integrated Circuit Technology Proceedings
year: 2006

abstract: Operating properties of charge trapping type Flash memory devices with single or stacked structures on trapping layer are investigated in this letter. Improved operation and reliability characteristics can be achieved by adapting the stacked high k films as charge trapping layer due to the modification in the trap density and the energy level of traps, the mechanism of electron/hole transmission, and the suitable band offset. Moreover, with a small bandgap of second film in the stacked trapping layer, operating characteristics of devices are further enhanced.
author_names: Ping-Hung Tsai

Kuei-Shu Chang-Liao

Te-Chiang Liu

Tien-Ko Wang

Pei-Jer Tzeng

Cha-Hsin Lin

L -S Lee

Ming-Jinn Tsai
title: Charge Trapping Type Flash Memory Device With Stacked High $k$ Charge Trapping Layer
venue: IEEE Electron Device Letters
year: 2009

abstract: Atomically thin layered two dimensional materials, including transition metal dichalcogenide (TMDC) and black phosphorus (BP) have been receiving much attention, because of their promising physical properties and potential applications in flexible and transparent electronic devices. Here, for the first time we show nonvolatile charge trap memory devices, based on field effect transistors with large hysteresis, consisting of a few layer black phosphorus channel and a three dimensional (3D) Al2O3/HfO2/Al2O3 charge trap gate stack. An unprecedented memory window exceeding 12 V is observed, due to the extraordinary trapping ability of the high k HfO2. The device shows a high endurance of over 120 cycles and a stable retention of ~30% charge loss after 10 years, even lower than the reported MoS2 flash memory. The high program/erase current ratio, large memory window, stable retention and high on/off current ratio, provide a promising route towards flexible and transparent memory devices utilising atomically thin two dimensional materials. The combination of 2D materials with traditional high k charge trap gate stacks opens up an exciting field of nonvolatile memory devices.
author_names: Qi Feng

Faguang Yan

Wengang Luo

Kaiyou Wang
title: Charge trap memory based on few layer black phosphorus.
venue: Nanoscale
year: 2016