Query: “StrainedSi/strained-Ge type-II staggered heterojunction gate-normal-tunneling field-effect transistor

Candidate papers:

abstract: A SiGe based n channel tunnel field effect transistor design employing a strained Si/strained Ge staggered gap heterojunction with a small effective band gap (122 meV) at the interface is investigated via numerical simulations using a semi classical quantum correction obtained from the density gradient model. A gate normal tunneling geometry is used to increase tunneling area and reduce subthreshold swing. The strain leads to degeneracy breaking among the silicon conduction band valleys, reducing the density of states and associated quantum capacitance with better gate to tunnel barrier coupling. Performance evaluation using a figure of merit "I60," where the drain current corresponds to a subthreshold slope of 60 mV/decade, suggests that the device has the potential to be competitive with modern metal oxide semiconductor field effect transistors.
author_names: William Hsu

Jason Mantey

Leonard Franklin Register

Sanjay K Banerjee
title: Strained Si/strained Ge type II staggered heterojunction gate normal tunneling field effect transistor
year: 2013

abstract: A strained Ge1 x ySixSny/Ge1 a bSiaSnb direct type II staggered heterojunction n channel tunneling field effect transistor (FET) with a dual material double gate is proposed herein. A high K gate dielectric is used to improve the overall device performance. The energy bandgap for strained Ge1 x ySixSny grown on a relaxed Ge1 a bSiaSnb layer is determined using the generalized approach of Menendez and Kouvetakis (MK) Poisson's equation is solved by using a parabolic approximation to determine the surface potential and electric field. The drain current is calculated using the tunneling generation rate obtained from Kane's model. A significant improvement of the drain current is observed as compared with that of previously reported Si based TFETs.
author_names: Namrata Shaw

Bratati Mukhopadhyay

Gopa Sen
title: Study of the electrical parameters of a dual material double gate TFET using a strained type II staggered Ge1 x ySixSny/Ge1 a bSiaSnb heterojunction
year: 2020

abstract: We investigate GaAs<sub><italic>1 x</italic>/sub>Bi<sub><italic>x</italic>/sub>/GaAs<sub><italic>1 y</italic>/sub>N<sub><italic>y</italic>/sub> type II staggered heterojunction tunneling field effect transistors (TFETs) with the analytical model. GaAs<sub><italic>1 x</italic>/sub>Bi<sub><italic>x</italic>/sub>/GaAs<sub><italic>1 y</italic>/sub>N<sub><italic>y</italic>/sub> exhibits a remarkable type II band lineup and the effective bandgap <inline formula> <tex math notation="LaTeX"{E} _{{G,\mathrm{ eff} /tex math>/inline formula> at interface is significantly reduced with the increasing of bismuth (Bi) and nitrogen (N) compositions. Theoretical characterization shows that the band to band tunneling probability and current of TFETs are boosted with the decreasing of <inline formula> <tex math notation="LaTeX"{E} _{{G,\text {eff} /tex math>/inline formula> at the GaAs<sub><italic>1 x</italic>/sub>Bi<sub><italic>x</italic>/sub>/GaAs<sub><italic>1 y</italic>/sub>N<sub><italic>y</italic>/sub> staggered tunnel ing junction by increasing Bi and N compositions. It is demonstrated by the analytical calculation that GaAs<sub><italic>1 x</italic>/sub>Bi<sub><italic>x</italic>/sub>/GaAs<sub><italic>1 y</italic>/sub>N<sub><italic>y</italic>/sub> heterostructure is a potential candidate for high performance TFET.
author_names: Yibo Wang

Genquan Han

Yan Liu

Chunfu Zhang

Qian Feng

Jincheng Zhang

Yue Hao
title: Investigation of GaAsBi/GaAsN Type II Staggered Heterojunction TFETs with the Analytical Model
venue: IEEE Transactions on Electron Devices
year: 2017

abstract: Heterojunction tunneling field effect transistors (HTFETs) that use strained silicon/strained germanium type II staggered band alignment for band to band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gate controlled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained Si/strained Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained Si/strained Ge/relaxed Si0.5Ge0.5 hetero junctions is used to extract a valence band offset of 0.64 eV at the strained Si/strained Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low operating voltage (Vdd 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON state currents.
author_names: Osama M Nayfeh

Cait Ni Chleirigh

John J Hennessy

Leonardo Gomez

Judy L Hoyt

Dimitri A Antoniadis
title: Design of Tunneling Field Effect Transistors Using Strained Silicon/Strained Germanium Type II Staggered Heterojunctions
venue: IEEE Electron Device Letters
year: 2008

abstract: Tunneling field effect transistors (TFETs) are of considerable interest owing to their capability of low power operation. Here, we demonstrate a novel type of TFET which is composed of a thin black phosphorus tin diselenide (BP SnSe2) heterostructure. This combination of 2D semiconductor thin sheets enables device operation either as an Esaki diode featuring negative differential resistance (NDR) in the negative gate voltage regime or as a backward diode in the positive gate bias regime. Such tuning possibility is imparted by the fact that only the carrier concentration in the BP component can be effectively modulated by electrostatic gating, while the relatively high carrier concentration in the SnSe2 sheet renders it insensitive against gating. Scanning photocurrent microscopy maps indicate the presence of a staggered (type II) band alignment at the heterojunction. The temperature dependent NDR behavior of the devices is explainable by an additional series resistance contribution from the individual BP and SnSe2 sheets connected in series. Moreover, the backward rectification behavior can be consistently described by the thermionic emission theory, pointing toward the gating induced formation of a potential barrier at the heterojunction. It furthermore turned out that for effective Esaki diode operation, care has to be taken to avoid the formation of positive charges trapped in the alumina passivation layer.
author_names: Junhong Na

Youngwook Kim

Jurgen H Smet

Marko Burghard

Klaus Kern
title: Gate Tunable Tunneling Transistor Based on a Thin Black Phosphorus SnSe2 Heterostructure
venue: ACS applied materials interfaces
year: 2019

abstract: Abstract In the advanced technology nodes, conventional MOSFETs are being replaced by tunnel field effect transistors (TFETs) due to its potential of achieving subthreshold swing (SS) less than 60 mV/decade. However, certain constraints are to be met to improve the performance of TFET in terms of higher ON current (ION) and lower threshold voltage (Vth) Here, in this paper, magnesium silicide/silicon (Mg2Si/Si) heterojunction double gate TFET (Mg2Si/Si HDG TFET) is explored and is simultaneously compared with conventional silicon double gate TFET (Si DG TFET) Results depict superior performance of Mg2Si/Si HDG TFET as compared to conventional Si DG TFET, in terms of dc characteristics, i.e. ION, Vth, SS, and ION/IOFF ratio. Obtained Vth (0.26 V) SS (10.05mV/decade) and ION/IOFF ratio (1013) for the case of Mg2Si HDG TFET shows an improvement of 77% 49% and 10 decades respectively compared to counterpart i.e. Si DG TFET. In particular, this improvement in the performance of Mg2Si/Si HDG TFET over Si DG TFET is attributed to staggered type II heterojunction interface at the source channel junction, which leads to reduction of the width for interband tunneling barrier and hence, improves ION. This viability of the device is also determined by analyzing the impact of non idealities present in the device. In this respect, the Gaussian and tail defects are considered in the bulk of Mg2Si. The results reveal that the Gaussian defects alter the device characteristics mainly in the subthreshold regime, whereas, in the ON state, the impact of defects is minimal. Further, it is obtained that the device is much immune for tail defects in comparison with the Gaussian defects. The CV analysis reveals a marginal degradation in parasitic capacitances for Mg2Si/Si HDG TFET as compared to Si DG TFET. However, this degradation can be overlooked against the remarkably enhanced drain current. Thus, the device overcomes the bottleneck of TFET and provides high ION and low Vth without degrading the other performance parameters and hence is suitable for low power analog and digital applications.
author_names: Jaya Madan

Minaxi Dassi

Rahul Pandey

Rishu Chaujar

Rajnish Sharma
title: Numerical analysis of Mg2Si/Si heterojunction DG TFET for low power/high performance applications: Impact of non idealities
year: 2020

abstract: Introduction. The ability to scale CMOS to future technology nodes is jeopardized primarily by power constraints. Supply voltage scaling is the best method to reduce power consumption in logic circuits; however, the thermionic nature of the turn off mechanism in MOSFETs forces a fundamental trade off between leakage power and performance when the voltage is reduced. Tunneling field effect transistors (TFETs) could overcome this limitation since these devices have been theoretically shown to be capable of subthreshold slopes 60 mV/decade [1] However, the band gap of silicon (1.12 eV) is too large to provide acceptable drive currents in Si based TFETs. TFETs fabricated using Si/SiGe heterojunctions [2] have the potential for increased drive current since the type II band alignment reduces the effective band gap for tunneling at the source electrode. In this talk, I will show experimental results on Si/SiGe heterojunction tunneling transistors (HETTs) along with quantum transport simulations on a variety of heterojunction TFET geometries, and then describe the implications of these results on the viability of the Si/SiGe material system for TFET fabrication. Si/SiGe HETTs. The devices were fabricated using a conventional CMOS process flow that was modified to allow the source and drain electrodes to be formed in separate processing steps. The devices utilized SOI starting substrates and a high k/poly gate stack. The n drain was formed by conventional As implantation and anneal, while the source electrode was formed by selective etching of Si underneath the gate electrode and regrowth of in situ doped p Si1 xGex. Typical Id vs. Vgs characteristics at room temperature for HETTs with source Ge concentrations of 7% and 25% are shown in Fig. 2 [3] The improved performance for the devices with x 25% over x 7% provides a clear indication of the heterojunction benefit on TFET performance. However, the devices fall short of achieving sub 60 mV/dec subthreshold slopes or the necessary drive currents for practical applications. Broken gap TFETs. In order to further explore the heterojunction band structure requirements for TFETs, quantum transport simulations are performance on a variety of HETTs with band alignment ranging from staggered to broken gap [4] The results, shown in Fig.3, indicate that the optimal performance is achieved in broken gap heterojunction devices. These results further demonstrate the efficacy of the heterojunction design in improving TFET drive current, but also suggest that novel device geometries [5] or material systems with direct band gaps (e.g. III Vs [6] graphene nanoribbons [7] may be needed to achieve the performance levels necessary for practical applications. References. [1] J. Appenzeller, et al. Phys. Rev. Lett. 2004, [2] O. Nayfeh, et al. IEEE Elect. Dev. Lett. 2008, [3] S. J. Koester, et al. unpublished, [4] S. Koswatta, et al. IEDM, 2009, [5] A. Bowander, et al. VLSI. 2008, [6] S. Mookerjea, et al. IEDM, 2009, [7] Q. Zhang, et al. IEEE Elect Dev. Lett. 2008. n+ poly
author_names: Steven J Koester

Isaac Lauer

A Majumdar

J Cai

Jeffrey W Sleight

Stephen W Bedell

Paul M Solomon

Steven E Laux

Leland Chang

Siyuranga O Koswatta

Wilfried E Haensch

Pierre Tomasini

Shawn G Thomas
title: (Invited) Are Si/SiGe Tunneling Field Effect Transistors a Good Idea?
year: 2010

abstract: In this paper, we demonstrate the performance improvement in SiGeSn/GeSn p channel hetero line tunneling field effect transistor (HL TFET) via numerical simulation. The GeSn is located at the pocket region and forms the type II staggered tunneling junction (TJ) that perpendicular to channel direction with the lattice matched SiGeSn. The HL TFET demonstrates the smaller onset voltage (VONSET) the higher on state current (ION) and the steeper subthreshold swing (SS) in comparison with the GeSn homo Line TFET (L TFET) and the conventional SiGeSn/GeSn double gate hetero TFET (H TFET) devices. The performance enhancement is mainly owing to the larger tunneling area in HL TFET attributing to the presence of heterojunction and the tunneling junction (TJ) that perpendicular to the channel direction.
author_names: Hongjuan Wang

Genquan Han

Yan Liu

Jincheng Zhang

Yue Hao

Xiangwei Jiang
title: The performance improvement in SiGeSn/GeSn p channel hetero Line Tunneling FET (HL TFET)
venue: 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)
year: 2017

abstract: Single crystal AlN/diamond heterojunction with high density interface hole channel is successfully obtained by metal organic vapor phase epitaxy. The AlN layer is epitaxially grown on hydrogen terminated (H )diamond(111) substrate. The thermal treatment of diamond substrate just before AlN growth under hydrogen and ammonia mixture environment at 1250 degC leads to surface sheet hole density as high as ~1.0 x 1014 cm 2 without structural reconstruction of diamond surface. In addition, the use of smaller off cut angle (0.20 0.25deg) H diamond(111) substrate combined with this treatment enables to obtain single crystal epitaxial AlN layer, which simultaneously acts as passivation of the surface hole channel with such a high density. The AlN/H diamond(111) heterojunction reveals type II staggered energy band configuration with valence band offset of ~2.0 eV, which is suitable for the fabrication of p channel field effect transistor using AlN gate insulator/diamond heterojunction. These results are promising for.
author_names: Masataka Imura

Ryan G Banal

Meiyong Liao

Jiangwei Liu

Takashi Aizawa

Akihiro Tanaka

Hideo Iwai

Takaaki Mano

Yasuo Koide
title: Effect of off cut angle of hydrogen terminated diamond(111) substrate on the quality of AlN towards high density AlN/diamond(111) interface hole channel
year: 2017

abstract: A lattice matched d doped In0.34Al0.66As0.85Sb0.15/InP heterostructure field effect transistor (HFET) which provides large band gap ~1.8 eV) high Schottky barrier height (phB>0.73 eV) and large conduction band discontinuity (DEc>0.7 eV) has been proposed. In0.34Al0.66As0.85Sb0.15/InP heterostructures are shown to be type II heterojunctions with the staggered band lineup. This HFET demonstrates a output conductance of less than 1 mS/mm. Two terminal gate source breakdown voltage is more than 20 V with a leakage current as low as 170 mA at room temperature. High three terminal off state breakdown voltage as high as 36 V, and three terminal on state breakdown voltage as high as 18.6 V are achieved. The gate voltage swing is also significantly improved.
author_names: Yi-Jing Lin

W Y Hsu

Chia-Yen Yeh

H M Shieh
title: In0.34Al0.66As0.85Sb0.15/d(n+ InP heterostructure field effect transistors
year: 2000