Query: 20nA sub-threshold biased CMOS reference current source

Candidate papers:

abstract: A low voltage low power CMOS reference current source is designed by biasing MOSFETs in the sub threshold region. This current source operates with the battery of 0.8V produces stable reference current of 20nA. The circuit has been designed using 180nm CMOS technology of Semiconductor Laboratory of ISRO India simulated using "Analog design Environment" of Cadence. This reference current source provides a current sensitivity of 0.65 percent per volt with power supply voltage, a variation in reference current is just 0.001 percent with a variation of the load from 1 ohm to 1 Mega Ohm, temperature sensitivity of reference current is 0.032 percent per deg C consumes just 232nW. This reference current source is quite suitable for biomedical applications implantable devices where low voltage and low power stable reference current source is the primary requirement.
author_names: Chetali Yadav

Sunita Prasad
title: 20nA sub threshold biased CMOS reference current source
venue: 2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC)
year: 2017

abstract: This paper presents the design and application of a CMOS sub 1V voltage reference using a 2 transistor Self Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of 0.18% from 20degC to 75degC (or less than 15ppm/degC) operates from 3.6V down to 800mV while biased with a 5nA resistor less PTAT current source that varies 30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2 PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip point of the voltage detector vary 5.5% and 3.3% respectively, over temperature, without trimming.
author_names: Alfredo Olmos

Fabricio Jorge Antunes Ferreira

Fernando da Rocha Paixao Cortes

Fernando Chavez
title: A 2 Transistor Sub 1 V Low Power Temperature Compensated CMOS Voltage Reference Design and Application
year: 2015

abstract: This paper presents the design of a CMOS sub 1V voltage reference using a 2 transistor Self Cascode MOSFET structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. Besides that, the two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a 0.18 mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of 0.18% from 20degC to 75degC (or less than 15ppm/degC) operates from 3.6V down to 800mV while biased with a 5nA resistor less PTAT current source that varies 30% over PVT, and consumes less than 20nA. The complete circuit including the current source and the 2 transistor Self Cascode MOSFET occupies an area of 0.01mm2.
author_names: Alfredo Olmos

Juan Pablo Martinez Brito

Fabricio Jorge Antunes Ferreira

Fernando Chavez

Marcelo Lubaszewski
title: A 2 transistor sub 1V low power temperature compensated CMOS voltage reference
venue: 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI)
year: 2014

abstract: Because of the universal adoption of global biasing technique for IC design,the stability of biased circuit has important influence on the performance of the whole circuit.One kind of bias current reference based on VT and working in its subthreshold domain,which is able to meet the requirement of less working current and low power consumption is analyzed in this paper.At the same time,the bias current reference is extremely unsensitive to current change.The output current shifts within 9%0 while the power voltage changes from 0.7 V to 5 V.The entire circuit is simulated with Cadence Spectre,and the result shows low power consumption and high PSRR.
author_names: Chang Chang-yuan
title: Design and Analysis of a Sub threshold Operation CMOS Reference Current Source
year: 2007

abstract: A nano watt bandgap voltage reference (BGR) is presented. To provide a low voltage and low power BGR, the circuit has been biased in the sub threshold region; thereby, drawing a few nano amperes current from the source, has been achieved. In order to reduce die area and also power consumption, instead of resistor, transistor is used. To generate PTAT voltage, self cascode composite structure is used for the transistors. The results from post layout simulation using 0.18 mm standard CMOS technology show that the proposed BGR circuit generates a reference voltage of 625 mV, obtaining temperature coefficient of 13 ppm/ degC in the temperature range of 25 degC to 110 degC. The simulated power supply rejection ratio is 42 dB. Fully designed with MOS transistors, the circuit draws 18 nA from a 0.9 V supply. The active area of the proposed BGR is 0.00067 mm 2
author_names: Iman Fakharyan

Mehdi Ehsanian

Hadi Hayati
title: A 0.9 V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub threshold operation
venue: Analog Integrated Circuits and Signal Processing
year: 2019

abstract: This paper presents an original low voltage CMOS, bipolar transistor free, sub threshold voltage reference capable of operating with sub 1V supply voltages. Novel aspects of the proposed solution are (i) use of a bandgap core with a single MOSFET to avoid threshold voltage error terms and (ii) adoption of an high gain, low offset inverter like amplifier in the bandgap feedback loop. Relatively high output current sourcing capabilities are obtained by means of an output source follower stage based on native MOSFETs. The circuit potentiality is demonstrated by means of electrical simulations performed on a prototype designed with a standard 0.18um CMOS process. A reference voltage of 0.483 V, with a maximum variation of 4mV in a temperature range of 20/80degC, has been obtained with a supply voltage of 0.7 V. The maximum output current is 200mA with a quiescient current consumpion of only 9.8mA.
author_names: Andrea Ria

Alessandro Catania

Mattia Cicalini

Lorenzo Benvenuti

Massimo Piotto

Paolo Bruschi
title: A Sub 1V CMOS Switched Capacitor Voltage Reference with high output current capability
venue: 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
year: 2019

abstract: This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180nm UMC CMOS technology. The proposed circuit consists of start up, Bias voltage, currentsource sub circuits with most of the MOSFETs operating in sub threshold region. Simulation results shows that the circuit generates a stable reference current of 4 nA in supply voltage range 1 V1.8 V with line sensitivity of .The temperature coefficient of the current was at 1.8 V in the range of The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub threshold operated power aware large scale integration.
author_names: Dinesh Kushwaha

D K Mishra
title: Nano Power Current Reference Circuit consisting of Sub threshold CMOS Circuits
year: 2017

abstract: In this work a new topology for a self biased current reference, based on an asymmetric bulk modified MOS (ABM) composite transistor is presented. Two current references based in this technique were designed: a 13.5nA current reference in a $1.5\mu \mathrm{m} CMOS technology, and a 100nA current reference in a $0.18\mu \mathrm{m} CMOS technology. The latter was designed to minimize the temperature dependence of the output current; the result was less than 5% from 0degC to 100degC, which is a very good result in comparison to other reported similar current references.
author_names: Diego Costa

Matias R Miguez

Joel Gak

Fabian Torres

Alfredo Arnaud
title: A Self biased Current Source, using an Asymmetric Bulk modified MOS Composite Transistor
venue: 2020 Argentine Conference on Electronics (CAE)
year: 2020

abstract: Abstract The sub threshold circuit design is regarded as a promising technique to provide considerable power reduction for ultra low power applications under tight energy constraints. This paper presents Power Gating Sub Threshold Source Coupled Logic (PG STSCL) which employs the fine grain power gating at the gate level. It introduces isolation and retention circuits to ensure reliable propagation of data along a pipeline of power gated circuits, called a micro pipeline. While the conventional STSCL circuits can considerably cut down the active power consumption, they have the drawback of continuous static current flow. To overcome this drawback, the proposed architecture shuts off the static current by utilizing the fine grain power gating technique. We have designed a 32 bit adder based on the proposed PG STSCL gates in a 65 nm CMOS technology. The adder was simulated and compared to reference adders using standard CMOS gates, and conventional STSCL gates. Simulations demonstrated that the proposed gates provide a power reduction of 89.56% and 99.78% when compared to the standard CMOS and STSCL gates, respectively.
author_names: Hossam Hassan

Sameh A Ibrahim

Hyungwon Kim
title: Power Gating Sub Threshold Source Coupled Logic (PG STSCL) circuits for ultra low power applications
venue: Microelectron. J.
year: 2018

abstract: The invention belongs to the technical field of simulation integrated circuits, and discloses a low power consumption sub threshold type CMOS band gap reference voltage circuit. The circuit comprises a start circuit, a reference current source generation circuit, a voltage division circuit and a reference voltage output circuit. The start circuit is used for enabling a reference voltage source to get rid of a zero degeneracy point and to work under specific work voltage. The reference current source generation circuit is used for generating current to provide bias for a rear end circuit, and MOS transistors in the rear end circuit all work in a sub threshold region. The voltage division circuit is used for enabling an output circuit to reach required technical indexes and generating a negative temperature coefficient. The reference voltage output circuit is used for generating voltage with a positive temperature coefficient and making the output voltage Vref have the zero temperature characteristic. The low power consumption sub threshold type CMOS band gap reference voltage circuit has the advantages of being low in work voltage, low in power consumption and low in temperature coefficient.
title: Low power consumption sub threshold type CMOS band gap reference voltage circuit
year: 2015