Query: sense amplifier of SRAM

Candidate papers:

abstract: The invention discloses a programmable tracking circuit of an SA (sense amplifier) of an SRAM (static random access memory) The programmable tracking circuit comprises a word line driving circuit (WLDRIVER) a programmable timing control circuit and a sense amplifier driving circuit (SA Driver) wherein the WLDRIVER is used for driving word line signals WL and DWL; the programmable timing control circuit is controlled by DWL, and is a programmable array DBL (duplicated bit line) discharging circuit mainly comprising NMOSs (N channel metal oxide semiconductors) the SA Driver is used for controlling the on and off of the SA. According to the programmable tracking circuit, the influence of process variations, voltage and temperature on the on off time of the SA is avoided.
title: Programmable tracking circuit of SA (sense amplifier) of SRAM (static random access memory)
year: 2013

abstract: An analysis of timing and input referred offset of sense amplifiers (SA) is presented, and a new SA architecture with capacitive offset correction is proposed. Offset sources are first analyzed in a cross coupled latch based SA design, and the analysis is then extended to the proposed SA. The results show the proposed offset correction technique can reduce the total sensing time by up to 40% while eliminating dynamic offset due to the difference in resolving inverters trip points. A self timed SRAM with a new replica timing structure is designed to generate optimal SA enable timing with respect to the total input referred offset. Calculations for timing delay and offset are compared with simulation results in both a conventional and a proposed SA design. The presented simulation results are based on a 10 Kb CMOS SRAM array in 130 nm BiCMOS SiGe technology operating at a 500 MHz clock and 1.5 V supply.
author_names: Roman Fragasse

Ramy Tantawy

Brian Dupaix

Trevor Dean

D diSabato

Matthew R Belz

Dale Shane Smith

Jamin Mccue

Waleed Khalil
title: Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self Timing
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2019

abstract: A novel cascade control replica bitline delay (CCRBD) technique has been proposed to reduce timing process variation of SRAM sense amplifier in this brief. The main idea of this technique is that both replica bitlines (RBLs) are utilized, and one is cascade controlled by the other. Simulation results show that the timing process variation of this technique decreases by 41.83% compared with conventional strategy. Simultaneously, the cycle time is also reduced by 19% at the supply voltage of 800mV in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that with conventional replica bitline technique.
author_names: Chunyu Peng

Youwu Tao

Wenjuan Lu

Zhengping Li

Xinchun Ji

Jinlong Yan

Junning Chen
title: A novel cascade control replica bitline delay technique for reducing timing process variation of SRAM sense amplifier
venue: IEICE Electron. Express
year: 2015

author_names: Bhupendra Singh Reniwal
title: Variability aware design of SRAM in conventional and non conventional MOS technologies a sense amplifier perspective
year: 2017

abstract: Variability and reliability have become major threats in nano scale era. Both leads to variation in transistor parameters that eventually affect the performance parameters. One of the failure mechanism is Bias Temperature Instability (BTI) which impacts mobility and threshold voltage (Vth) of the transistor. This paper investigates the impact of BTI on SRAM sense amplifier at different process corners along with variability effect in 45nm technology. The results depict that, impact of Positive BTI (PBTI) is less than Negative BTI (NBTI) on sensing delay of sense amplifier. Moreover across all process corners sensing delay increases as supply voltage (Vbd) decreases and temperature increases. A surrogate model has been developed by using support vector machine (SVM) for variability and reliability analysis of sensing delay. Adaptive learning is used in order to develop the model with less number of samples which attributes to less run time. Evaluation of single sample of sensing delay requires 0.077ms and 0.081ms for read 0 and read 1 respectively. Correlation coefficient has been obtained between HSPICE and SVM in order to validate the model. The values of correlation coefficients are 0.9996 and 0.9997 for read 0 and read 1 respectively.
author_names: Sapna Khandelwal

Jyoti Meena

Lokesh Garg

Dharmendar Boolchandani
title: Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier
venue: 2016 20th International Symposium on VLSI Design and Test (VDAT)
year: 2016

abstract: Random variations play a critical role in determining SRAM yield, by affecting both the bitcell and the read sense amplifiers (SA) In this work, a process control monitor for SRAM SA offset is proposed and implemented in 28nm LP CMOS technology. The monitor provides accurate measurement of SA offset from a large sample size and accounts for all proximity effects that may affect the SA offset. The all digital design of the monitor makes it adequate for low voltage testing, high speed data collection, and ease of migration to newer technologies. Detailed measurement results are provided for two of the most commonly used sense amplifiers at different supply and temperature conditions. Statistical yield estimation using the measured sense amplifier offset shows good correlation with measured yield for a 512Kb SRAM. The monitor is a critical part of SRAM silicon yield validation, which is becoming of increasing importance with technology scaling, and the significant increase in random variations.
author_names: Mohamed H Abu-Rahma

Ying Chen

Wing Sy

Wee Ling Ong

Leon Yeow Ting

Sei Seung Yoon

Michael Han

Esin Terzioglu
title: Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS
venue: 2011 IEEE Custom Integrated Circuits Conference (CICC)
year: 2011

abstract: Random variations play a critical role in determining SRAM yield because they affect both the bitcell and the read sense amplifiers (SA) In this chapter, a process control monitor for SRAM SA offset is proposed and implemented in 28nm LP CMOS technology. The monitor accurately measures SA offset from a large sample size and accounts for all the layout proximity effects. The all digital design of the monitor makes it appropriate for low voltage testing, high speed data collection, and migration to newer technologies. Detailed measurement results are provided for two of the most commonly used sense amplifiers at different supply voltage and temperature conditions. Statistical yield estimation using the measured sense amplifier offset correlates well with measured yield for a 512Kb SRAM.
author_names: Mohamed H Abu-Rahma

Mohab H Anis
title: Characterization of SRAM Sense Amplifier Input Offset for Yield Prediction
year: 2013

author_names: Chunyu Peng

Youwu Tao

Wenjuan Lu

Zhengping Li

Xinchun Ji

Jinlong Yan

Junning Chen
title: Erratum: A novel cascade control replica bitline delay technique for reducing timing process variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]
venue: IEICE Electron. Express
year: 2015

abstract: A highly sensitive sense amplifier for static random access memory (SRAM) with a very low offset voltage, negligible static current, and low kickback noise is presented in this paper. We propose to use a preamplifier stage instead of positive feedback between the input and the sense amplifier to improve the sensitivity of the sense amplifier. The proposed sense amplifier is designed and simulated using 0.18 mm CMOS technology node. With a supply voltage of 1.4 V and an operating frequency of 1 GHz, the proposed sensing amplifier has a sensing delay of 193.2 ps, which is 85% better than conventional designs. The sense amplifier has an offset voltage of 18 mV.
author_names: Pallab Pran Dutta

B ArunMohan

Saroj Mondal
title: An 18 mV Offset, 193 ps Sensing Delay, and Low Static Current Sense Amplifier for SRAM
venue: 2020 24th International Symposium on VLSI Design and Test (VDAT)
year: 2020

abstract: Abstract In modern computer memory role is to sense the low power signals, this paper optimally finds the best solutions to improve the performance of the Sense Amplifier for CMOS SRAM. The circuit is designed and simulated in the Advanced Design System. The simulation result shows that the required output voltage 1.2 V is available after addition of an Inverter at the output having identical PMOS NMOS in the circuit. It is observed that the performance of the sense amplifier has been improved drastically. To have better results now our future work will concern the 22 nm technology.
author_names: Raja Saravana Kumar Selvakumar

M Ganesh Lakshmana Kumar

S Raja Gopal
title: Material analysis of high degree of variability in thin CMOS for SRAM current sense amplifier
year: 2020