Query: Preparation of silicon dioxide nanowires

Candidate papers:

abstract: The present invention provides a kind of silicon nanowires tunneling field effect transistor and preparation method thereof, including step:1)One SOI substrate, including bottom silicon, oxygen buried layer and top layer silicon are provided;2)The top silicon layer is thinned and forms silicon dioxide layer in surface;3)Silicon nanowires raceway groove, source region and drain region are formed using photoetching process and wet corrosion technique;4)Protective layer is formed in the side of the source region, the week side of boss in drain region and silicon nanowires raceway groove, the opposite side of the silicon nanowires raceway groove is corroded using wet corrosion technique, forms the silicon nanowires raceway groove with triangular section;5)Oxide layer is formed in the silicon nanowires channel surface;6)Form source region and drain region;7)Make source electrode and drain electrode.The silicon nanowires of the present invention is based on top down methods, is realized and made using silicon nitride sidewall protection and TMAH anisotropy etch stop, technical process is simple, and controllability is strong, and completely compatible with existing semiconductor technology, cost is relatively low, suitable for industrial production.
title: A kind of silicon nanowires tunneling field effect transistor and preparation method thereof
year: 2014

abstract: Silicon nanowires were synthesized from nanometer silicon dioxide powder under potentiostatic electrolysis at 1.20 V(vs Pt reference) for 4 h in molten CaCl2 at 900 .The morphology,structure and chemical composition of the samples prepared by electroreduction method were characterized by field emission scanning electron microscopy(FE SEM),High resolution transmission electron microscopy(HRTEM) coupled with electron energy dispersive spectroscopy(EDS),laser Raman and X ray diffraction(XRD).The results revealed that silicon nanowires were crystalline with a diamond cubic structure,the diameter was distributed from 50 nm to 80 nm and the length was generally several micrometers.The formed nanowires basically consisted of silicon monocrystalline and amorphous oxide sheath.
author_names: Yang Juan
title: Preparation of Silicon Nanowires by Electrochemical Method
year: 2009

abstract: Silicon carbide nanowires were synthesized by mixing formaldehyde resin carbon and nanometer silicon dioxide(atomic Si/C ratio, 1:1) under cell voltage of 2.0 V in molten CaCl2at 900 The morphology,structure and chemical composition of the samples prepared by electro reduction method were characterized by field emission scanning electron microscopy(FE SEM) transmission electronic microscope(TEM) Highresolution transmission electron microscopy(HRTEM) coupled with electron energy dispersive spectroscopy(EDS) X ray diffraction(XRD) and laser Raman spectroscopy. The results reveal that silicon carbide nanowires are crystalline with a cube structure, the diameter is distributed from 4 nm to 13 nm and the length is generally several micrometers. Two broad photoluminescence(PL) peaks at the center wavelength of about 415 nm and 534nm were observed at room temperature. The formation mechanism of the SiC nanowires is also discussed.
author_names: Zhao Chun
title: Preparation of SiC Nanowires by Direct Electro reduction of SiO_2/C Pellets in Molten Salt
year: 2013

abstract: The invention relates to a method for preparing silicon nanowires, belonging to the nanophase material preparation technical field. The method comprises the following steps that: a silicon chip is washed and shaken by acetone and alcohol and is processed by an acid cleaning liquid and a No.1 standard cleaning solution; a silicon dioxide spheres solution with a weight percentage density between 0.02 and 2.0 percent is added on the silicon chip surface which is washed off in the step one drop by drop by a micro pipette, the processed silicon chip is placed in air to air naturally; the silicon chip with silicon dioxide sphere arrays is annealed for one to three hours at a temperature of between 900 and 1000 DEG C; afterwards, the silicon chip is put into a diluent hydrofluoric acid solution to be eroded for 2 to 20 minutes so that the diameters of the spheres become small; an Ag film with a thickness between 20 and 80nm is deposited on the silicon chip surface by the plating technique or the vacuum evaporating technique; and a sample deposited with the Ag film is dipped into the hydrofluoric acid and hydrogen peroxide etching solution (or ferric nitrate) to be eroded for 4 to 100 minutes. The preparation method can rapidly prepare a large area of silicon nanowire arrays, thereby being suitable for the large scale industrial production.
title: Preparation of silicon nanowire array
year: 2008

abstract: The invention relates to a preparation method of a silicon nanowire fence device, comprising the following steps: providing an SOI (Silicon On Insulator) substrate; successively forming a silicon dioxide buffer layer and a silicon nitride layer; defining an active area; carrying out local oxidation treatment on a silicon film out of the active area to cause the oxidized silicon film to form a beak structure on the edge of the active area; removing the silicon nitride layer and the silicon dioxide buffer layer; photoetching to define protective source leakage, and etching the silicon film to form a groove; forming silicon nanowires on the silicon film below the beak structure; etching silicon dioxide formed after the silicon film is subjected to local oxidation treatment and burying parts of oxide layers to cause the silicon nanowires to hang in the air; oxidizing a grid to form a grid medium layer surrounding the silicon nanowires; depositing polysilicon to form a fence; and finishing the common CMOS (Complementary Metal Oxide Semiconductors) technologies of injecting source leakage, depositing a silicon dioxide isolated layer, etching contact holes, mutually connecting and leading out metal and the like to form the silicon nanowire fence device. In the preparation method of the silicon nanowire fence device, the silicon nanowire can be simply prepared while one time photoetching is reduced, manufacture cost is reduced, and the technology difficulty is lowered.
title: Preparation method of silicon nanowire fence device
year: 2010

abstract: SiC nanowires have been synthesized by microwave vacuum heating method at 1480degC, using silicon powders, silica dioxide powders and artificial graphite as raw materials. SEM, TEM and XRD were employed to investigate the micro structure of obtained specimens. It was shown that b SiC can be directly synthesized directly without any catalyst on the basis of the vapor solid (VS) growth mechanism. The obtained specimens exhibited various morphologies and sizes, due to the differences in the reaction temperatures and the distribution of components in the crucible. Products existed in upper crucible were bright green and more pure, mainly consisting of nanorods with a diameter of about 150nm and some SiC micro crystals. At the same time, the surface oxidation phenomenon was not obvious. As to the grey green products existed in other zone, lots of SiC/SiO2 coaxial nanowires with a diameter around 20 50 nm (the thickness of SiO2 surface layer was about 2nm) were successfully obtained. Besides, there also remained some un reacted graphite and silica dioxide. The excitation light with wavelength of 240nm was used to test the photoluminescence properties of the products. Results showed that both of the SiC nanorods and SiC/SiO2 coaxial nanowires exhibited a strong broad photoluminescence peak at wavelength of about 390nm, displaying a higher degree of blue shift in comparison to the reported luminescence results of b SiC nanomaterials.
author_names: Shan Huang

Ji Gang Wang

Song Liu

Yue Zhang

Liu Qian

Jie Liang
title: Study on the Preparation and Micro Structural Characterization of SiC Nanowires Obtained by Direct Microwave Heating
year: 2013

abstract: SiC/SiOx coaxial nanowires were rapidly synthesized via direct microwave irradiation in low vacuum atmosphere. During the preparation process, only graphite, silicon, silicon dioxide powders were used as raw materials and iron containing substance was employed as catalyst. Comprehensive characterizations were employed to investigate the microstructure of the products. The results showed that a great quantity of coaxial nanowires with uniform sizes and high aspect ratio had been successfully achieved. The coaxial nanowires consist of a silicon oxide (SiOx) shell and a b phase silicon carbide (b SiC) core that exhibited in special tube brush like. In additional, nearly all the products were achieved in the statement of pure SiC/SiOx coaxial nanowires without the existence of metallic catalyst, indicating that the self removal of iron (Fe) catalyst should be occurred during the synthesis process. Photoluminescence (PL) spectral analysis result indicated that such novel SiC/SiOx coaxial nanowires exhibited significant blue shift. Besides, the measurement results of field emission (FE) demonstrated that the SiC/SiOx coaxial nanowires had ultralow turn on field and threshold field with values of 0.2 and 2.1 V/mm, respectively. The hetero junction structure formed between SiOx shell and SiC core, lots of emission sites, as well as clear tips of the nanowires were applied to explain the excellent FE properties.
author_names: Qing Zhou

Yongzhi Yu

Shan Huang

Jiang Meng

Jigang Wang
title: Field emission property of self purification SiC/SiOx coaxial nanowires synthesized via direct microwave irradiation using iron containing catalyst
venue: Electronic Materials Letters
year: 2017

abstract: Abstract Electrochemical deposition allows the preparation of ZnO nanostructures with precisely controlled morphology and properties, by finely tuning the process parameters. ZnO nanowires were deposited onto gold substrates by electrodeposition from a low concentration zinc nitrate bath. Photolithography was employed for patterning interdigitated electrode systems onto silicon/silicon dioxide substrates and ZnO electrodeposition lead to wires connected to each other by bridging neighboring interdigits allowing electronic transport characterization. Optical measurements, i.e. reflection and photoluminescence spectroscopy, were performed and the results were correlated to electronic transport data. We found that we deal with a system for which one can apply a model of space charge limited currents with different traps energy distribution as a consequence of electrodeposition rate. Current versus temperature measurements show different behavior for lower and higher range of temperatures. Such nanowires, fabricated and contacted in a straightforward way, allow a wide area of applications ranging from conductometric bio or chemo sensors to optoelectronic devices.
author_names: Elena Matei

Andreea Costas

Camelia Florica

Monica Enculescu

Ioana Pintilie

Lucia Pintilie

Ionut Enculescu
title: Electrical properties of templateless electrodeposited ZnO nanowires
year: 2016

abstract: Abstract Bulk quantity amorphous silica nanowires (SiONWs) have been synthesized by carbothermal reduction reaction between silicon dioxide and active carbons. Transmission electron microscopy (TEM) image shows the formation of the nanowires at a diameter of 60 110 nm and a length up to hundreds micrometers. Besides most smooth surface polyp shaped nanowires, two other forms of nanowires, named amoeba shaped and frog egg shaped nanowires, have also been observed. The nanowires can emit stable and high brightness blue light at 435 nm (2.85 eV) under excitation at 260 nm (4.77 eV) The formation of the nanowires into different shapes may be explained by the vapor liquid solid (VLS) mechanism.
author_names: Xingcai Wu

W H Song

Ke Yu Wang

T Hu

B R Zhao

Yan Sun

Jiaju Du
title: Preparation and photoluminescence properties of amorphous silica nanowires
year: 2001

abstract: The present invention discloses a method for manufacturing a laminated structure SiGe nanowire, the method comprising: alternating SiGe epitaxial germanium thin film single crystal substrate surface, and the surface of the germanium thin film and silicon germanium film is subjected to photolithography and etching, to obtain silicon germanium germanium line structure; oxidizing the obtained silicon germanium germanium line structure under pure oxygen or a mixed gas atmosphere containing oxygen, the use of germanium to germanium different oxidation rate of silicon germanium preferential oxidation germanium dioxide, while maintaining the silicon germanium is not oxidized; and chemical etching method for removing germanium dioxide, germanium, silicon nanowire obtained stacked structure. Method for fabricating SiGe nanowire structures of the present invention provides, having a large area growth, the process is simple, and the preparation of controlled diameter nanowires low cost.
title: Method for manufacturing a silicon germanium nanowire stacked structure
year: 2013