Query: Low-Voltage Tunnel Transistors for Beyond CMOS_Logic

Candidate papers:

abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal oxide semiconductor field effect transistor (MOSFET) basic current transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.
author_names: Alan C Seabaugh

Qin Zhang
title: Low Voltage Tunnel Transistors for Beyond CMOS Logic
venue: Proceedings of the IEEE
year: 2010

abstract: A novel, tunnel field effect transistor (TFET) based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N 2N2P, positive feedback adiabatic logic) operating in the ultra low voltage $0.3~\text{V}\geq V_{DD} \leq 0.6~\text{V} regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub threshold circuit operation, shows the feasibility of TBAL for energy efficient Internet of Things applications.
author_names: Jheng-Sin Liu

Michael B Clavel

Mantu K Hudait
title: TBAL: Tunnel FET Based Adiabatic Logic for Energy Efficient, Ultra Low Voltage IoT Applications
venue: IEEE Journal of the Electron Devices Society
year: 2019

abstract: Low voltage transistors are being developed to achieve steep, less than 60 mV/decade, subthreshold swings at room temperature. This paper outlines progress, technical challenges, and applications for these devices.
author_names: Alan C Seabaugh

Cristobal Alessandri

Mina Asghari Heidarlou

Hua-Min Li

Leitao Liu

Hao Lu

Sara Fathipour

Paolo Paletti

Pratyush Pandey

Trond Ytterdal
title: Steep slope transistors: Tunnel FETs and beyond
venue: 2016 46th European Solid State Device Research Conference (ESSDERC)
year: 2016

abstract: Atomically thin layers of van der Waals (vdW) crystals offer an ideal material platform to realize tunnel field effect transistors (TFETs) that exploit the tunneling of charge carriers across the forbidden gap of a vdW heterojunction. This type of device requires a precise energy band alignment of the different layers of the junction to optimize the tunnel current. Amongst two dimensional (2D) vdW materials, black phosphorus (BP) and indium selenide (InSe) have a Brillouin zone centered conduction and valence bands, and a type II band offset, both ideally suited for band to band tunneling. Here, we demonstrate TFETs based on BP/InSe heterojunctions with diverse electrical transport characteristics: forward rectifying, Zener tunneling and backward rectifying characteristics are realized in BP/InSe junctions with different thickness of the BP layer or by electrostatic gating of the junction. Electrostatic gating yields a large on/off current ratio of up to 108 and negative differential resistance at low applied voltages (V 0.2V) These findings illustrate versatile functionalities of TFETs based on BP and InSe, offering opportunities for applications of these 2D materials beyond the device architectures reported in the current literature.
author_names: Quanshan Lv

Faguang Yan

Nobuya Mori

Wenkai Zhu

Ce Hu

Zakhar R Kudrynskyi

Zakhar D Kovalyuk

Amalia Patane

Kaiyou Wang
title: Interlayer Band to Band Tunneling and Negative Differential Resistance in van der Waals BP/InSe Field Effect Transistors
year: 2020

abstract: As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low power, high performance flip flop designs. Due to the nature of TFETs, some of the flip flop designs that are evaluated require additional modifications beyond simple device replacement most notably the pseudo static D flip flop (DFF) We find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.
author_names: Matthew Cotter

Huichu Liu

Suman Datta

Narayanan Vijaykrishnan
title: Evaluation of tunnel FET based flip flop designs for low power, high performance applications
venue: International Symposium on Quality Electronic Design (ISQED)
year: 2013

abstract: Tunnel FET (TFET) is a major candidate for beyond CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs) current mirrors, and track and hold circuits are examined. It is shown that TFETs are promising for low power and low voltage designs, wherein transistors are biased at low to moderate current densities. Comparing 14 nm III V TFET based OTAs with Si MOSFET based designs demonstrates up to 5 times reduction in the power dissipation of the amplifiers and more than an order of magnitude increase in their DC voltage gain. The challenges and opportunities that come with the special characteristics of TFETs, namely asymmetry, ambipolar behavior, negative differential resistance, and superlinear operation are discussed in detail.
author_names: Behnam Sedighi

Xiaobo Sharon Hu

Huichu Liu

Joseph Nahas

Michael Thaddeus Niemier
title: Analog Circuit Design Using Tunnel FETs
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2015

abstract: By means of advanced numerical simulation, the thermoelectric properties of a Si quantum dot based single electron transistor operating in sequential tunneling regime are investigated in terms of figure of merit, efficiency and power. By taking into account the phonon induced collisional broadening of energy levels in the quantum dot, both heat and electrical currents are computed in a voltage range beyond the linear response. Using our homemade code consisting in a 3D Poisson Schrodinger solver and the resolution of the Master equation, the Seebeck coefficient at low bias voltage appears to be material independent and nearly independent on the level broadening, which makes this device promising for metrology applications as a nanoscale standard of Seebeck coefficient. Besides, at higher voltage bias, the non linear characteristics of the heat current are shown to be related to the multi level effects. Finally, when considering only the electronic contribution to the thermal conductance, the single electron transistor operating in generator regime is shown to exhibit very good efficiency at maximum power.
author_names: Vincent Talbo

Jerome Saint-Martin

Sylvie Retailleau

Philippe Dollfus
title: Non linear effects and thermoelectric efficiency of quantum dot based single electron transistors
venue: Scientific Reports
year: 2017

abstract: In this review article for Internet of Things (IoT) applications, important low power design techniques for digital and mixed signal analog digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy constrained hardware security issues are reviewed. Specifically, light weight encryption based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs) logic obfuscation using silicon nanowire FETs, and all spin logic devices are highlighted. Furthermore, a novel ultra low power design using bio inspired neuromorphic computing and spiking neural network security are discussed.
author_names: Jiann-Shiun Yuan

Jie Lin

Qutaiba Alasad

Shayan Taheri
title: Ultra Low Power Design and Hardware Security Using Emerging Technologies for Internet of Things
year: 2017

abstract: 1. Energy efficiency limits of digital circuits based on CMOS transistors Elad Alon 2. Beyond transistor scaling: alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn 3. Benchmarking alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn 4. Extending CMOS with negative capacitance Asif Islam Khan and Sayeef Salahuddin 5. Designing a low voltage, high current tunneling transistor Sapan Agarwal and Eli Yablonovitch 6. Tunnel transistors Alan Seabaugh, Zhengping Jiang and Gerhard Klimeck 7. Graphene and 2D crystal tunnel transistors Qin Zhang, Pei Zhao, Nan Ma, Grace (Huili) Xing and Debdeep Jena 8. Bilayer pseudospin field effect transistor Sanjay Bannerjee, Frank Register and Dharmendar Reddy 9. Computation and learning with metal insulator transitions and emergent phases in correlated oxides You Zhou, Sieu D. Ha and Shriram Ramanathan 10. The piezo electronic transistor Paul M. Solomon, Bruce G. Elmegreen, Matt Copel, Marcelo A. Kuroda, Susan Trolier McKinstry, Glenn J. Martyna and Dennis M. Newns 11. Mechanical switches Tsu Jae King Liu and Rhesa Nathanael 12. Nanomagnetic logic: from magnetic ordering to magnetic computing Gyorgy Csaba, Gary H. Bernstein, Alexei Orlov, Michael T. Niemier, X. Sharon Hu and Wolfgang Porod 13. Spin torque majority gate logic Dmitri E. Nikonov and George I. Bourianoff 14. Spin wave phase logic Alexander Khitun 15. Interconnect considerations Ahmet Ceyhan, Shaloo Rakheja and Azad Naeemi.
author_names: Tsu-Jae King Liu

Kelin J Kuhn
title: CMOS and beyond logic switches for terascale integrated circuits
year: 2015

abstract: Using Schrodinger poison formalism, a Carbon Nano tube Field Effect Transistor (CNTFET) has been studied. To improve the saturation range in the output characteristics, new transistor structures has been proposed. These structures are simulated and compared with the conventional structure. It is found that proposed structures have better output characteristic. KEY WORD Mathematical physics, electronics, double dielectric medium. 1.Introduction: A CNT is a sheet graphene rolled up as a tube ,with a diameter typically in the nanometer range, which can be from less than one nanometer,up to several nanometers. CNTs are one dimensional (1 d)device in which electron transport is quasi ballistic Moreover, mobility of CNTs is considerably larger than silicon and can be as large as 10cm2/v.s. These properties have emerged CNTs as candidate for nanometer(10nm) electronic technology. CNTs can be semiconducting or metallic according to the chiral vector .Single wall semiconducting CNTs, with few nanometers in diameter can be as channels for field effect transistors (FETs).a zig zag CNT field effect transistor with schottky barrier contacts is simulated and its characteristics are evaluated. Then, novel structures are proposed which have superior characteristics ,specially, for digital application. 2. CNT modeling: We consider a (16.0) nanotube with radius R1=0.6nm, bandgap Eg=0.62ev,dielectric constant r=1, and the tube length Lt=20nm. Due to the azimuthal symmetry of the tube, the simulation domain is two dimensional (2 D) The gate insulator has ins=25 and thickness Rg=2.5nm. Drain and source metals make Schottky contact to the channel with Fb=0.3ev.Figure1 shows the CNTFET structure. To derive I V characteristics of the transistor, the ID schrodinger equation is solved consistently with the Poisson's equation. Poisson's equation with azimuthal symmetry is: v r r 1 v rr2 v z2 Q/ (1) In this equation r is the tube radial direction, z is the channel direction, Q is the charge density on the tube surface and is derived from schrodinger equation.Poission's equation is solved using finite difference method. The charge density is zero everywhere except at the tube surface: Q= q(p n)d(r Rl) 2pr (2) Where n and p are electron and hole densities respectively and are derived from the Schrodinger equation. In the carbon nanotube, the electron transport is almost ballistic therefore, the Schrodinger equation is solved to compute the charge density and the transmission probability: ps z2 8p2m h2 (E U)ps (3) (c) 2020 JETIR April 2020, Volume 7, Issue 4 www.jetir.org (ISSN 2349 5162) JETIR2004287 Journal of Emerging Technologies and Innovative Research (JETIR) www.jetir.org 609 Where E is the electron or hole energy U is the potential energy, which is qv for the electron and qv Eg for the hole. The Schrodinger equation is solved using central difference discretization method. For a conventional CNTFET depicted in fig.4.1, drain current (Id) versus drain source voltage (vds) for various gate source voltage (vgs is shown in fig.4.2. For Vds up to 0.6v, output characteristics is similar to conventional FET transistors. But for larger voltages, the drain current is suddenly increased. This is due to the hole injection from the drain to the source. As this figure shows, the saturation region in the output characteristics is about 0.6v, which is small for typical applications. Figure 4.3 shows the electron potential energy for the gate voltage Vgs=0.4v and three values of drain voltages. For Vds =0.2v electrons surmount (or tunnel) through the source and drain schottkey barriers and makes the drain current. With increasing the drain voltage, the potential on the drain side decreases and the electron current increases. At a special Vds, the drain barrier vanishes. If the schottky barrier equals Eg/2,at Vds=Vgs the drain barrier vanishes. In Fig.4.3 this happens for Vds=0.4v. For larger Vds, hole injection is increased. At Vds=2Vgs hole and electron current would be equal. Beyond Vds=2Vgs, hole current will increase exponentially as is known for a schottkey diode. 3. Novel transistor structures: In the conventional CNTFETs, for low vgs, exponentially increasing of the drain current takes place at low drain voltages (tens of iv) This limits usage of the transistor for most applications, especially for digital circuit. To overcome this problem one most prevent the drain schottky diome form entering on stat, and consequently increase the saturation rang in the output characteristics. In this section, novel structures are proposed in increase the saturation range. 4. Double dielectric: For the transistor of Fig.4.1. if an insulator with higher dielectric is used, the gate control on the channel increases and vice versa. Keeping this in mind, the transistor in Fig.4.4 is proposed, in which, gate length is divided into two equal section. In this transistor, the gate dielectric at the drain side selected from a material with lower dielectric constant. Therefore, the gate control on the drain side of the channel is decreased. Fig. 4.5 shows Id Vds for this transistor. The dielectric constant at the drain side is assumed 5, where as at the source side the dielectric constant is assumed 25, As Fig.5.5 shows, the saturation range of the transistor is slightly increased. 5. Double metal gate: In this structure, as the previous one, the gate length is divided into two parts, with uniform dielectric, but with different gate metals The gate metal on the drain side is selected with lower work function.Fig.4.6 shows Id Vds for a transistor with gate metal of 0.2v lower work function. The figure shows that current saturation portion is almost 0.2v wider than the conventional transistor. 6. Partially gate metallization: In this structure the gate metal on drain side is not deposited. With this, gate affects the channel near the source, and has no effect on the channel near the drain.Fig.4.7 depicts the Id Vds characteristics of the transistor. It is obvious from this figure that the saturation range of this transistor is wider than two former structures. Moreover this structure is easier to fabricate. Figure 4.1 Figure 4.2 (c) 2020 JETIR April 2020, Volume 7, Issue 4 www.jetir.org (ISSN 2349 5162) JETIR2004287 Journal of Emerging Technologies and Innovative Research (JETIR) www.jetir.org 610 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 7. Discussion: A CNTFET is simulated based on Schrodinger poisson formalism. This evaluation showed that the saturation range in the output characteristics is small. Three different structures are proposed to increase this range. It is shown that proposed transistors have wider FET saturation range. This makes them suitable for digital application. References: [1] T Durkop, B M Kim and M S Fuhrer, Properties and applications of high mobility semiconducting nanotubes, J. Phys. Condens. Matter V.16, 2004, pp.R553 R580. [2] J. Appenzeller, J. Knoch, M. Radosavljevic and Ph. Avouris, Multimode Transport in Schottky Barrier Carbon Nanotube FieldEffect Transistors, Physical Review Letters V.92, No. 22, 2004, p.226802 1. [3] J. Guo, S. Datta, and M. Lundstrom, A Numerical Study of Scaling Issues for SchottkyBarrier Carbon Nanotube Transistors, IEEE Transactions on Electron Devices V.51, No.2, 2004. [4] M. Pourfath, A. Gehring, E. Ungersboeck, H. Kosina, S. Selberherr, B. H. Cheong, W. J. Park, Separated carrier injection control in carbon nanotube field effect transistors, Journal of Applied Physics V.97, 2005, p.106103. [5] Hisashi Kajiura, Anil Nandyala, Alexey Bezryadin, Quasi ballistic electron transport in as produced and annealed multiwall carbon nanotubes, Carbon, V.43, 2005, p.1317. [6] V. N. Popov, Carbon nanotubes: properties and application, Materials Science and Engineering R 43, 2004, pp.61 102. [7] S. Datta, Electronic Transport in Mesoscopic System Cambridge University Press, 1995 [8] Javey, A.,Guo,Wang,Q. Lundstrom,M.&Dai,H.J.Ballistic carbon Nanotube field effect transistors.Nature424,654 657(2003) [9] Heinz,S.et al.Carbon nanotubes as schottkybarrier transistors.phys. Rev. Lett.89.6801 (2002)
author_names: D N Jha
title: CARBON NANO TUBE FIELD EFFECT TRANSISTORS WITH IMPROVED CHARACTERISTICS
year: 2020