Query: cdfe wafer analysis

Candidate papers:

abstract: Wafer map defect pattern contains the critical information about semiconductor manufacturing, effective defect analysis technology can improve the yield of products. This paper develops a wafer defect pattern recognition and analysis method based on convolutional neural network (CNN) We build an 8 layer CNN model to inspect wafer map defect and a 13 layer model to classify defect patterns. To analyze the defects, we first extract features based on the classification network, then perform PCA dimensionality reduction and similarity ranking, we infer the root causes of tested samples according to the retrieved wafer maps. In particular, we analyze the impacts of different network layers and feature dimensions on image retrieval performance, it turns out that the appropriate dimensionality reduction can increase the accuracy and speed of wafer map retrieval. The models are trained and tested on the WM 811K wafer map dataset, which are collected from real wafer maps. The experimental results show that the proposed method is able to identify common wafer defect patterns and analyze the root causes accurately and effectively.
author_names: Naigong Yu

Qiao Xu

Honglu Wang
title: Wafer Defect Pattern Recognition and Analysis Based on Convolutional Neural Network
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2019

abstract: A robotic cluster tool involves many activities whose time is subject to some disturbance, thus leading to the activity time variation. It results in wafer sojourn time fluctuation in a process module, which may in turn violate wafer residency time constraints. Some wafer fabrication requires a revisiting process. With wafer revisiting, the effect of activity time variation on wafer sojourn time fluctuation is so complicated that no analysis was reported to the best knowledge of the authors. It is vitally important to accurately analyze it. To do so, this paper adopts a Petri net model to describe the dynamical behavior of cluster tools. With this model, a real time control policy is proposed to offset the effect of the activity time variation on wafer sojourn time fluctuation as much as possible. Then, the wafer sojourn time delay is analyzed and algorithms are developed to calculate its exact upper bound. With the proposed method, one can check if a given schedule is feasible under bounded activity time variation. Some practical examples are given to show the application of the proposed approach.
author_names: Yan Qiao

Naiqi Wu

Fajun Yang

Mengchu Zhou

Qinghua Zhu
title: Wafer Sojourn Time Fluctuation Analysis of Time Constrained Dual Arm Cluster Tools With Wafer Revisiting and Activity Time Variation
venue: IEEE Transactions on Systems, Man, and Cybernetics: Systems
year: 2018

abstract: This paper investigates on wafer characterization of SiGe HBTs up to 500 GHz. Test structures for on wafer thru reflect line (TRL) calibration have been designed and are presented. The TRL calibration method with silicon standards has first been benchmarked through electromagnetic simulation. Passive and active components are then characterized up to 500 GHz. The slight discontinuities between the frequency bands are explored. A specific focus was placed on incorrect horizontal probe positioning as well as on probe deformation, resulting in a better assessment of possible measurement errors.
author_names: Sebastien Fregonese

Magali De matos

Marina Deng

Manuel Potereau

Cedric Ayela

Klaus Aufinger

Thomas Zimmer
title: On Wafer Characterization of Silicon Transistors Up To 500 GHz and Analysis of Measurement Discontinuities Between the Frequency Bands
venue: IEEE Transactions on Microwave Theory and Techniques
year: 2018

abstract: Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF) communications/sensing (mmWave) and automotive applications. However, to date its application space has been limited to a small die form factor due to challenging chip board interaction (CBI) control. The combination of ultralow dielectric constant (ULK) based advanced silicon technology and WLP is another challenge for industry to overcome.In this article, to systematically address the CBI, a large test vehicle based on 22 nm fully depleted silicon on insulator (FD SOI) technology platform and WLP technology is described. In particular, CBI during drop test and temperature cycle on board is investigated and its failure mode analysis is discussed. The impact of silicon die thickness and ball grid array (BGA) metallurgy is also explored.
author_names: Jae Kyu Cho

Jens Paul

Simone Capecchi

Dirk Breuer

Frank Kuechenmeister

Doug Scott

Jong-Gyu Choi

Wonjoon Kang
title: Chip Board Interaction Analysis of 22 NM Fully Depeleted Silicon on Insulator (FD SOI) Technology in Wafer Level Packaging (WLP)
venue: 2018 International Wafer Level Packaging Conference (IWLPC)
year: 2018

abstract: In modern foundry industry, capacity and yield are the two very important indicators to show how good the foundry is. In the past decades, the size of silicon wafer has been increased from 100nm to current 300nm, so that more dies can be packed the wafer. However, due to process constrains and increasing in the wafer dimension, the yield loss on wafer edge becomes more severe. Failure analysis acts as a powerful tool to help Fab in identifying the root cause of the wafer edge failure. In this paper, several wafer edge cases caused by different process modules were presented. The FA findings provided the evidence to show how the process uniformity limitation can cause the failure on wafer edge. Hence, Fab can take the corresponding actions to solve the issue, also continuously process tuning activities can be carried out, hence the yield loss on wafer edge can be reduced.
author_names: N Y Xu

HP Ng

G B Ang

C Q Chen

Angela Teo

Andrew Jerome

Y S Tam

Yajing Li

Zhihong Mai
title: Failure Analysis Case Studies on Wafer Edge Failure due to Process Uniformity Issue
venue: 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
year: 2018

abstract: In this paper, a low yield case relating to IDD leakage at active mode due to the systematic breakdown signature consistently at the top MIM edge was studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP probing, layout path tracing, FIB circuit edit, SEM XTEM and top down PFA methodology together with Fab investigation are used to understand the root cause as well as failure mechanism. This paper highlights that there are 2 types of leakage (high leakage in mA and low leakage in uA) The high leakage dies revealed spot directly at the MIM cap and anomaly can be observed at the MIM edge. However, for the low level leakage, hotspot was seen at the PMOS transistor and NOT at the MIM Cap. Besides layout tracing that enable to pinpoint the suspected MIM cap, 2 types of simulation (Intentionally induced damage and FIB Circuit Edit) were performed to prove and validate the MIM defect is the only root cause for this low yield issue and the RF circuitry has no contribution to it. Additionally, top down PFA methodology was engaged to reveal the physical evidence of the damage at the edge of the MIM. This confirmed that both type of leakage are due to similar MIM breakdown issue.
author_names: Angela Teo

Ang Ghim Boon

Ng Hui Peng

Chen Chang Qing

Xu Nai Yun

N Dayanand

Tam Yong Seng

Mai Zhi Hong

Jeffrey Lam
title: Failure Analysis Methodology on Systematic MIM failure in Wafer Fabrication
venue: 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
year: 2018

abstract: In semiconductor manufacturing processes, defect detection and recognition in wafer maps have received increasing attention from semiconductor industry. The various defect patterns in wafer maps provide crucial information for assisting engineers in recognizing the root causes of the fabrication problems and solving them eventually. This paper develops a manifold learning based wafer map defect detection and recognition system. In this system, a joint local and nonlocal linear discriminant analysis (JLNDA) is proposed to discover intrinsic manifold information that provides the discriminant characteristics of the defect patterns. An unsupervised version of JLNDA (called local and nonlocal preserving projection) is further developed to provide a monitoring chart for defect detection of wafer maps. A JLNDA based Fisher discriminant is further put forward for online defect recognition without the modeling procedure of recognizers. Comparisons with other regular methods, principal component analysis, local preserving projection, linear discriminant analysis (LDA) and local LDA, illustrate the superiority of JLNDA in wafer map defect recognition. The effectiveness of the proposed system has been verified by experimental results from a real world data set of wafer maps (WM 811K)
author_names: Jianbo Yu

Xiaolei Lu
title: Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Linear Discriminant Analysis
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2016

abstract: In Part I, we have established a wafer scale, CMOS compatible graphene transfer for the back end of the line integration. In Part II of this paper, we analyze statistical data of device properties and draw conclusions about possible causes of device failure. Statistical analysis is performed for device mobility and compared with the yield analysis. To complement this analysis, detailed Raman spectra are employed to analyze strain. In addition, device models developed in Part I are examined and provide further insight. From the analysis, it appears that compressive strain introduced during the graphene transfer process is may be the primary source for device failure. Moreover, we speculate based on the device statistics that the mitigation of compressive strain will improve device mobility, carrier density, and reduce variability. In addition, the presence of residues, tears, and cracks in the graphene may result in some device failure.
author_names: Anderson David Smith

Stefan Wagner

Satender Kataria

Bengt Gunnar Malm

Max Christian Lemme

Mikael Ostling
title: Wafer Scale Statistical Analysis of Graphene Field Effect Transistors Part II: Analysis of Device Properties
venue: IEEE Transactions on Electron Devices
year: 2017

abstract: We analyze the completion time of wafer lots in single armed cluster tools with parallel processing modules (PMs) by considering the lot switching operation. To effectively assign wafer lots and dispatch overhead hoist transports (OHTs) to manufacturing tools, it is crucial to obtain the completion time of wafer lots. However, estimating the completion time is not straightforward, due to the concurrent processing of two consecutive wafer lots during lot switching operation, which often increases wafer sojourn times in PMs. In this paper, we derive closed form expressions of the completion time of wafer lots in single armed cluster tools with parallel PMs. We assume that the robot unloads wafers in the order of their loading sequence. We then experimentally show that the formulas derived can be used even when processing time variation exists or another robot task sequence, which is of first in first out (FIFO) is assumed.Note to Practitioners Due to the larger wafer size and circuit width reduction, cluster tools often perform the lot switching operation with each pair of consecutive wafer lots. In addition, since most tools are operated with parallel chambers, concurrent processing with two different wafer lots occurs frequently. Such transient periods in operating tools make it hard to estimate the completion time of wafer lots. In this paper, we derive closed form expressions to obtain the completion time of wafer lots in single armed cluster tools with parallel chambers. We further show that the formulas can be used with processing time variation or the FIFO rule. With the formulas, OHTs can be sent just in time to tools to load or unload wafer cassettes, and wafer lots can be assigned while minimizing the transient periods. In addition, the estimated completion time can be utilized in the planning and scheduling of wafer fabrication processes.
author_names: Jun-Ho Lee

Hyun-Jung Kim
title: Completion Time Analysis of Wafer Lots in Single Armed Cluster Tools With Parallel Processing Modules
venue: IEEE Transactions on Automation Science and Engineering
year: 2017

abstract: Wafer scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing.
author_names: Anderson David Smith

Stefan Wagner

Satender Kataria

Bengt Gunnar Malm

Max Christian Lemme

Mikael Ostling
title: Wafer Scale Statistical Analysis of Graphene FETs Part I: Wafer Scale Fabrication and Yield Analysis
venue: IEEE Transactions on Electron Devices
year: 2017