Query: Memristor-based nonvolatile latch circuit

Candidate papers:

abstract: Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1% during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal oxide semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor based memory cell can be fast, fine grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.
author_names: Warren Robinett

Matthew D Pickett

Julien Borghetti

Qiangfei Xia

Greg Snider

Gilberto Medeiros-Ribeiro

R Stanley Williams
title: A memristor based nonvolatile latch circuit.
venue: Nanotechnology
year: 2010

abstract: In this paper, a modified design of memristor based logic circuits integrated with CMOS components is introduced. Design of a compact and nonvolatile S R Latch is examined using a general memristor model as the nonvolatile element to store data. The proposed design operates efficiently in both "Set" and "Reset" modes. The simulation results demonstrate that this novel S R latch design offers better performance in terms of power, non volatility, and size of the topology compared with other memristor based designs proposed in the literature. We proved that this design has non volatile characteristics and is able to store data. This nonvolatile memristor based S R latch is a real alternative for future low power applications adding non volatility.
author_names: Khaoula Mbarek

Sami Ghedira

Faten Ouaja Rziga

Kamel Besbes
title: Design and Analysis of Nonvolatile Memristor based S R Latch
venue: 2020 IEEE International Conference on Design Test of Integrated Micro Nano Systems (DTS)
year: 2020

abstract: Sequential devices are the fundamental building blocks for almost all digital electronic systems with memory. Due to the importance of instant data recovery after unexpected data loss such as unplanned power down, sequential devices need to have the nonvolatile property, which motivates the recent research and practice in integrating the nonvolatile memristor into CMOS devices. In this paper, we study how to apply this approach to improve the quality of nonvolatile D latch. Unlike the structure of conventional design, the proposed D latch consists of only one memristor, several transmission gates, and CMOS inverters. Our design overcomes the negative effect due to the threshold loss of the transistors. As simulation shows, compared with the current designs, our proposed memristor based D latch can support the memristor to switch between different resistance states 2.3X 3.6X faster, and thus achieving a clock of higher frequency. In addition, our design allows the threshold value of the memristor to be selected from a much wider range. As an application, we use the proposed memristor based D latch to implement a nonvolatile master slave D flip flop, which has smaller delay than all the state of the art designs and smaller area than all but one of them. Our designs improve the quality of memristor based D latch and D flip flop in terms of latency, area, and flexibility of threshold voltage selection, making them a promising option for data backup in real life systems.
author_names: Zhenxing Chang

Aijiao Cui

Ziming Wang

Gang Qu
title: Novel Memristor based Nonvolatile D Latch and Flip flop Designs
venue: 2021 22nd International Symposium on Quality Electronic Design (ISQED)
year: 2021

abstract: Flip flops are basic units for all kinds of sequential logic circuits and complex digital electronics systems, which can be used to store binary data owing to their two stable logic states 0 and 1. SR flip flop and D flip flop are widely employed in digital circuits as representative types of basic flip flops. In this paper, logic circuits of nonvolatile synchronous SR flip flop and D flip flop are proposed, which utilize nanoscale memristors as the nonvolatile memory elements to store the information with different conductance states. The resistive switching property of memristors is well suited for implementing trigger function in flip flop circuits. Compared with traditional flip flop ones, the proposed memristor based SR flip flop and D flip flop have nonvolatile characteristic, which is suitable for occasions with unstable power supply. Meanwhile, the designed circuits provide experimental references for the development of digital circuit structures based on the feasibility of tight integration of memristors with CMOS circuitry.
author_names: Jian Zheng

Zhigang Zeng

Yidong Zhu
title: Memristor based nonvolatile synchronous flip flop circuits
venue: 2017 Seventh International Conference on Information Science and Technology (ICIST)
year: 2017

abstract: This paper presents a chaotic circuit based on a nonvolatile locally active memristor model, with non volatility and local activity verified by the power off plot and the DC V I plot, respectively. It is shown that the memristor based circuit has no equilibrium with appropriate parameter values and can exhibit three hidden coexisting heterogeneous attractors including point attractors, periodic attractors, and chaotic attractors. As is well known, for a hidden attractor, its attraction basin does not intersect with any small neighborhood of any unstable equilibrium. However, it is found that some attractors of this circuit can be excited from an unstable equilibrium in the locally active region of the memristor, meaning that its basin of attraction intersects with neighborhoods of an unstable equilibrium of the locally active memristor. Furthermore, with another set of parameter values, the circuit possesses three equilibria and can generate self excited chaotic attractors. Theoretical and simulated analyses both demonstrate that the local activity and an unstable equilibrium of the memristor are two reasons for generating hidden attractors by the circuit. This chaotic circuit is implemented in a digital signal processing circuit experiment to verify the theoretical analysis and numerical simulations.
author_names: Yujiao Dong

Guangyi Wang

Herbert Ho-Ching Iu

Guanrong Chen

Long Chen
title: Coexisting hidden and self excited attractors in a locally active memristor based circuit.
venue: Chaos
year: 2020

abstract: Memristor, one of the fundamental circuit elements, has promising applications in non volatile memory and storage technology as it can theoretically achieve infinite states. Information can be stored independently in these states and retrieved whenever required. In this paper, we have proposed a non volatile memory cell based on memristor emulator. The circuit is able to perform read and write operations. In this memristor based memroy cell, unipolar pulse is used for writing and bipolar pulse is used for reading. Unlike other earlier designs, the circuit does not need external read/write enable switches to switch between read and write operations; the switching is achieved by the zero average bipolar read pulse given after the completion of write cycle. In our proposed memristor based memory cell, single bit can be read and any voltages from 0 to 5 volts can be written. Mathematical analysis and the simulation results of memristor emulator based read write circuit have been presented to confirm its operation.
author_names: S Parajuli

Ram Kaji Budhathoki

Hyongsuk Kim
title: Nonvolatile Memory Cell Based on Memristor
year: 2020

abstract: For ultra low power Internet of Things (IoT) devices powered by batteries or energy harvesting, a nonvolatile flip flop (NV FF) operating in the near threshold voltage (NTV) region has been widely studied to save both standby and active power. However, in the NTV region, the NV FF suffers from restore yield and performance degradation due to the increase in process variation combined with the decrease in supply voltage. This paper presents a comparative analysis of the previous NV FFs according to supply voltage scaling and suggests the design directions for implementing the NV FF that can operate with compact area and high performance even in the NTV region. Through the comparative analysis, a novel offset cancellation sensing circuit (OCSC) based NV FF, which adopts a separate latch and sensing circuit structure and an offset cancellation technique, is proposed. The Monte Carlo HSPICE simulation results using industry compatible 65 nm model parameters show that the proposed NV FF satisfies a target restore yield with 32% area, 88% speed, and 82% energy savings in comparison with a representative NV FF of the merged latch and sensing circuit structure.
author_names: Byungkyu Song

Sara Choi

Seung H Kang

Seong-ook Jung
title: Offset Cancellation Sensing Circuit Based Nonvolatile Flip Flop Operating in Near Threshold Voltage Region
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2019

abstract: Reduction of leakage power and vulnerability to radiation are of critical challenges in modern nanometer CMOS technologies because of scaling down requirement. Spintronic logic has been progressed to realize these demands based on magnetic based elements properties especially magnetic tunnel junction (MTJ) such as radiation hardened, non volatility, and CMOS process compatibility. A novel soft error tolerant and highly reliable latch circuit is proposed in this paper which is a promising choice for reliable and low power architectures. Furthermore, employing the proposed shadow latch based on MTJ cells as a backup structure along with the rad hard main latch is aimed to the realization of a nonvolatile and SEU immune flip flop which is applicable in next generation CMOS circuits. Simulations of proposed circuits have been performed by SPICE tool and a 45 nm CMOS technology model to evaluate the effectiveness of topologies.
author_names: Abdolah Amirany

Fahimeh Marvi

Kian Jafari

Ramin Rajaei
title: Nonvolatile Spin Based Radiation Hardened Retention Latch and Flip Flop
venue: IEEE Transactions on Nanotechnology
year: 2019

abstract: Latches and flip flops are the basic unit in digital systems and for almost all sequential circuits. They preserve their state in the absence of the clock signal and hence store information as 0s (low voltage level) and 1s (high voltage level) This paper presents a novel design of a non volatile D Latch having minimum components using memristors. The circuits are designed and simulated in Cadence Virtuoso Analog Design Environment Product Suite and Spectre(r) Circuit simulation platform and the simulation results are also presented. The simplicity and the highly efficiency area utilization of the proposed D Latch makes it an ideal candidate to be used in various aspects of digital domain.
author_names: R Arundeepakvel

Parth Khatter

Neeta Pandey
title: Realization of Memristor based D Latch
venue: 2019 International Conference on Computing, Power and Communication Technologies (GUCON)
year: 2019

abstract: Memristor, one of the fundamental circuit elements, has promising applications in non volatile memory and storage technology as it can theoretically achieve infinite states. Information can be stored independently in these states and retrieved whenever required. In this paper, we have proposed a non volatile memory cell based on memristor emulator. The circuit is able to perform read and write operations. In this memristor based memroy cell, unipolar pulse is used for writing and bipolar pulse is used for reading. Unlike other earlier designs, the circuit does not need external read/write enable switches to switch between read and write operations; the switching is achieved by the zero average bipolar read pulse given after the completion of write cycle. In our proposed memristor based memory cell, single bit can be read and any voltages from 0 to 5 volts can be written. Mathematical analysis and the simulation results of memristor emulator based read write circuit have been presented to confirm its operation.
author_names: S Parajuli

Ram Kaji Budhathoki

Hyongsuk Kim
title: Nonvolatile Memory Cell Based on Memristor Emulator
venue: ArXiv
year: 2019