Query: decrease energy   compiler

Candidate papers:

abstract: Due to the power constraints of the current semiconductor technology, energy consumption has become an important factor for computer systems. Reducing energy consumption can mean more battery life for mobile devices or reduction of financial costs for data centers. One of the energy bottlenecks of computer systems is the information traffic between the processor and memory hierarchy. In this paper we evaluate the energy reduction of our new spill code minimization technique called color flipping in comparison with classical approaches. We implemented the Briggs' register allocator in the LLVM compiler framework with and without color flipping strategy and we ran some SPEC CPU 2006 benchmarks in a modified gem5 simulator for Cortex A9. Then the energy consumption was estimated using the McPAT framework. Experimental results showed that our technique can reduce about 1% of the energy consumption of integer programs.
author_names: Marcelo F Luna

Felipe L Silva

Wesley Attrot
title: Decreasing Spill Code to Decrease Energy Consumption
venue: 2015 Brazilian Symposium on Computing Systems Engineering (SBESC)
year: 2015

abstract: Annotation In this paper we analyze a problem of compilation, which increase energy efficiency of programs through use of techniques, implemented in the compiler. This problem is formulated as a multiple criteria optimization problem, with constraints on compile time increase and performance decrease. Non linearity of performance decrease and energy consumption decrease at given frequency decrease is explained. Short description of software capabilities of controlling system on chip frequency and voltage is provided. Genetic algorithm for solving this problem is provided. Result of application of this algorithm are measured and provided. Up to 13.5% energy efficiency increase in archived on tests from SPEC2000 testsuite.
author_names: Tocar Ilya
title: Compiler optimization of application's energy efficiency
year: 2014

abstract: A large and increasing number of Internet of Things devices are not equipped with batteries and harvest energy from their environment. Many of them cannot be physically accessed once they are deployed (embedded in civil engineering structures, sent in the atmosphere or deep in the oceans) When they run out of energy, they stop executing and wait until the energy level reaches a threshold. Programming such devices is challenging in terms of ensuring memory consistency and guaranteeing forward progress. Previous work has proposed to insert checkpoints in the program so that execution can resume from well defined locations. In this work, we propose to define these checkpoint locations based on statically computed worst case energy consumption of code sections. We also apply classical compiler optimizations in order to decrease the required number of checkpoints at runtime. As our method is based upon worst case energy consumption, we can guarantee memory consistency and forward progress.
author_names: Bahram Yarahmadi

Erven Rohou
title: Compiler Optimizations for Safe Insertion of Checkpoints in Intermittently Powered Systems
venue: SAMOS
year: 2020

abstract: In this paper, a 32 bit approximate Dadda Multiplier is implemented using 4:2 compressor. A Dadda Multiplier much alike to a Wallace Multiplier. The above multipliers are used to reduce the partial products but Dadda Multiplier is quite faster when compared to other multipliers as it requires few gates than Wallace Multiplier and thus leads to lower power consumption. The compressors used here has it's own accuracy level in approximate mode with variable delay and less power consumption. The proposed multiplier can also perform exact operation but 1.5625% error for average case. Synopsys Design Compiler using SCL 180nm CMOS technology was used to evaluate the efficiency of the compressors in 32 bit Dadda Multiplier and compared with other 4, 8 and 16 bit Dadda multipliers. The comparative study results depicts around 59.5% 54.5% and 14% decrease in power consumption with an area of 17504 um2.
author_names: Saurav Chanda

Koushik Guha

Santu Patra

Loukrakpam Merin Singh

Krishna Lal Baishnab

Prashanta Kumar Paul
title: An Energy Efficient 32 Bit Approximate Dadda Multiplier
venue: 2020 IEEE Calcutta Conference (CALCON)
year: 2020

abstract: In this paper, a 32 bit exact Dadda Multiplier is realized using 4:2 compressor. A Dadda Multiplier is similar to Wallace Multiplier. Both of the multipliers are used to reduce the partial products but Dadda Multiplier is faster than other multipliers and require less gates than Wallace Multiplier and a low power consumption. The compressors used has it's own accuracy level in both the exact and approximate mode with variable delay and less power consumption. Synopsys Design Compiler using SCL 180nm CMOS technology was used to evaluate the efficiency of the compressors in 32 bit Dadda Multiplier and compared with other 4, 8 and 16 bit Dadda multipliers. The results depicts around 48% decrease in power consumption with an area of 18955.74mm2.
author_names: Saurav Chanda

Koushik Guha

Santu Patra

Anupam Karmakar

Loukrakpam Merin Singh

Krishna Lal Baishnab
title: A 32 bit Energy Efficient Exact Dadda Multiplier
venue: 2019 IEEE 5th International Conference for Convergence in Technology (I2CT)
year: 2019

abstract: Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. Relatively simpler issue logic and the presence of a large number of function units in the VLIW and the clustered VLIW architectures attribute a large fraction of this leakage energy consumption in the functional units. However, functional units are not fully utilized in the VLIW architectures because of the inherent variations in the ILP of the programs. This underutilization is even more pronounced in the context of clustered VLIW architectures because of the contentions for the limited number of slow intercluster communication channels which lead to many short idle cycles.In the past, some architectural schemes have been proposed to obtain leakage energy bene .ts by aggressively exploiting the idleness of functional units. However, presence of many short idle cycles cause frequent transitions from the active mode to the sleep mode and vice versa and adversely a ffects the energy benefits of a purely hardware based scheme. In this paper, we propose and evaluate a compiler instruction scheduling algorithm that assist such a hardware based scheme in the context of VLIW and clustered VLIW architectures. The proposed scheme exploits the scheduling slacks of instructions to orchestrate the functional unit mapping with the objective of reducing the number of transitions in functional units thereby keeping them off for a longer duration. The proposed compiler assisted scheme obtains a further 12% reduction of energy consumption of functional units with negligible performance degradation over a hardware only scheme for a VLIW architecture. The benefits are 15% and 17% in the context of a 2 clustered and a 4 clustered VLIW architecture respectively. Our test bed uses the Trimaran compiler infrastructure.
author_names: Rahul Nagpal

Y N Srikant
title: Compiler assisted leakage energy optimization for clustered VLIW architectures
venue: EMSOFT '06
year: 2006

abstract: In order to decrease latency and energy consumption, processors use hierarchical memory systems to store temporally and spatially related instructions close to the core. Instruction register file (IRF) is an energy efficient solution for the lowest level in the instruction memory hierarcy. Being compiler controlled, it removes the area and energy overheads involved in cache tag checking and adds flexibility in the separation of the instruction fetch and execution. In this paper, we systematically evaluate for the first time the effect of three IRF design variations on energy and delay against an unoptimized baseline IRF. Having instruction fetch and decode with IRF in the same pipeline stage allows minimal delay branching, but results in low operating clock frequency and impaired energy delay product compared to splitting them into two stages. Assuring instruction presence in IRF before execution with software reduces the area and increases maximum clock frequency compared to assurance with hardware, but requires compiler analysis. With a proposed compiler analyzed instruction placement and co designed hardware implementation, energy consumption with the best IRF variant is reduced by 9% on average with EEMBC Coremark and CHStone benchmaks. The energy delay product is improved by 23% when compared to the baseline IRF approach.
author_names: Joonas Multanen

Heikki O Kultala

Pekka Jaaskelainen
title: Energy Delay Trade Offs in Instruction Register File Design
venue: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS) NORCHIP and International Symposium of System on Chip (SoC)
year: 2018

abstract: The holy grail of computer hardware across all market segments has been to sustain performance improvement at the same pace as silicon technology scales. As the technology scales and the size of transistors shrinks, the power consumption and energy usage per transistor decrease. On the other hand, the transistor density increases significantly by technology scaling. Due to technology factors, the reduction in power consumption per transistor is not sufficient to offset the increase in power consumption per unit area. Therefore, to improve performance, increasing energy efficiency must be addressed at all design levels from circuit level to application and algorithm levels. At architectural level, one promising approach is to populate the system with hardware accelerators each optimized for a specific task. One drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low as they perform one specific function. Using software programmable accelerators is an alternative approach to achieve high energy efficiency and programmability. Due to intrinsic characteristics of software accelerators, they can exploit both instruction level parallelism and data level parallelism. Coarse Grained Reconfigurable Architecture (CGRA) is a software programmable accelerator consists of a number of word level functional units. Motivated by promising characteristics of software programmable accelerators, the potentials of CGRAs in future computing platforms is studied and an end to end CGRA research framework is developed. This framework consists of three different aspects: CGRA architectural design, integration in a computing system, and CGRA compiler. First, the design and implementation of a CGRA and its instruction set is presented. This design is then modeled in a cycle accurate system simulator. The simulation platform enables us to investigate several problems associated with a CGRA when it is deployed as an accelerator in a computing system. Next, the problem of mapping a compute intensive
author_names: Mahdi Hamzeh
title: Compiler and Architecture Design for Coarse Grained Programmable Accelerators
year: 2015

abstract: Govt. of India scaled up of budget during 12th five year plan for Rooftop solar project to achieve the target of 40 GWp as committed before UNFCC (United Nations Framework Convention on Climate Change) In this connection through a case study it is shown that there is a chance to reduce the target and also the space of solar project installation if a manual solar tracking based on optimum tilt angle as proposed in the study can be included in the policy for future small solar project initiatives. An equation set of monthly solar optimum tilt angle has been proposed based on an anisotropic validated model developed by FORTRAN 77 Compiler. The equation set is applicable for a wide latitude range of 13deg to 39deg of northern hemisphere i.e. it includes all over India. If the proposed optimum tilt based manual tracking has been adopted in Govt. policy of solar project then the target to UNFCC will be reduced to 36.5 kWp i.e. a decrease of 8.75% and the required area for solar installation will also be decreased of 8.84%
author_names: Arindam Dutta

Subhasis Neogi
title: Reassessment of the Indian renewable energy policy through technology implementation
venue: 2016 21st Century Energy Needs Materials, Systems and Applications (ICTFCEN)
year: 2016

abstract: Managing power consumption while simultaneously delivering acceptable levels of performance is becoming a critical issue in several application domains such as wireless computing. We integrate compiler assisted techniques with power aware operating system services and present scheduling techniques to reduce energy consumption of applications that have deadlines. We show by simulation that our dynamic power management schemes dramatically decrease energy consumption
author_names: Daniel Moss

Hakan Aydin

Bruce R Childers

Rami G Melhem
title: Compiler assisted dynamic power aware scheduling for real time applications
year: 2000