Query: common drain in cmos

Candidate papers:

abstract: This research paper presents a design and study of a common source/drain active balun circuit implemented in a standard 90 nm complementary metal oxide semiconductor (CMOS) technology. The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8GHz and supply voltage of 1V. Measurements are taken for parameters namely gain difference, phase difference, and noise figure. The common source active balun design achieved a minimal gain difference of 0.016dB, phase difference of 180deg 7.1deg, and noise figure of 7.42 9.85dB, which are comparable to past active balun designs and researches. The design eventually achieved a low power consumption of 2.56mW.
author_names: Frederick Ray I Gomez

Maria Theresa Gusad de Leon

John Richard E Hizon
title: Design of Common Source/Drain Active Balun Using 90nm CMOS Technology
venue: Journal of Engineering Research and Reports
year: 2019

abstract: In this paper, a power amplifier implemented with a common drain structure is introduced. With proper input matching, this structure is shown to provide a reasonable power gain and superior linearity and efficiency in comparison to other low power topologies. This is shown to be due to the low dependency of the power gain to the transistor transconductance and the low voltage variations across the gate source capacitance. This power amplifier is suitable for low power and short range applications such as Bluetooth Low Energy (BLE) Based on the calculated S parameters, the operation frequency of this amplifier and its design trade offs are presented, along with a comparison with competitive topologies. The design is simulated in a 0.13 mm CMOS technology, operates with a 1.2 V supply, and provides a power gain of 8.5 dB with a DC power consumption of 3.6 mW. The input 1 dB compression point is 2.2 dBm, yielding a power added efficiency of 43%
author_names: Parvaneh Saffari

Mohammad Taherzadeh-Sani

Ali Basaligheh

Frederic Nabki

Mohamad Sawan
title: Low energy CMOS common drain power amplifier for short range applications
venue: 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)
year: 2015

abstract: The Low Noise Amplifier (LNA) is the first stage in RF CMOS receivers. The Common Gate (CG) LNA and Inductively Degenerated Common Source (CS) LNA are one of the widely used topologies for realizing RF CMOS receivers. The present work emphasizes a simple and exhaustive search procedure for the synthesis and analysis of CMOS CG and Inductively Degenerated CS LNA circuits. The width (W) gate source voltage V_{gs} $Vgs) and drain source voltage V_{ds} $Vds) of the transistors constitute the design space in the circuit design. The design first involves the use of a circuit simulator (HSPICE) to obtain the small signal parameters of the circuit for various W, V_{gs}$Vgs, and V_{ds} $Vdsof the transistors and then to generate a Look Up Table (LUT) for all design points using the obtained values. This LUT is used to meet the target performance specifications along with appropriate analytical expressions derived from the circuit in a numerical simulator (MATLAB) This will enable one to explore the whole design space quickly and fastly for arriving at the optimal values for the device dimensions, bias voltages and bias currents of the two LNA circuits. The design methodology is demonstrated by designing CG and Inductively Degenerated CS LNA circuits using 90 nm CMOS technology library in which Inductively Degenerated CS LNA gets high gain and low noise figure than CG LNA.
author_names: D Malathi

M P Gomathi
title: Design of inductively degenerated common source RF CMOS Low Noise Amplifier
year: 2018

abstract: This letter proposes a differential common drain Colpitts VCO circuit suitable for low phase noise oscillation at the sub 1V supply voltage. Oscillation with low phase noise at the sub 1V supply voltage is facilitated by employing inductors as the current sources of the proposed circuit. One of the two feedback capacitors in the half circuit of the proposed VCO circuit is replaced by a MOS varactor in order to further increase negative resistance. Post layout simulation results using a 0.18um RF CMOS technology show that the phase noise performances of the proposed circuit at the sub 1V supply voltages are much better than those of the well known cross coupled VCO at the same supply voltages.
author_names: Man-Young Jeon

Haeng-Woo Lee
title: A differential common drain Colpitts VCO circuit suitable for sub 1V low phase noise
venue: IEICE Electron. Express
year: 2011

abstract: This paper presents a CMOS W band amplifier adopting a novel neutralization technique for high gain and stability. The W band amplifier consists of four common source differential gain cells that are neutralized by a cross coupled MOS varactor pair. Contrary to conventional neutralizations, the proposed technique enables tunable neutralization, so that the gate to drain capacitance of transistors is accurately tracked and neutralized as the varactor voltage is adjusted. This makes the neutralization tolerant of capacitance change caused by process voltage temperature (PVT) variation or transistor model inaccuracy, which commonly occurs at mm wave frequencies. The proposed tunable neutralization is experimentally confirmed by measuring gain and stability of the W band amplifier fabricated in a 65 nm CMOS process. The amplifier achieves a measured gain of 17.5 dB at 79 GHz and a 3 dB bandwidth from 77.5 to 84 GHz without any stability issue. The DC power consumption is 56.7 mW and the chip area is 0.85 mm2.
author_names: Byungho Yook

Kwangwon Park

Seung-Won Park

Hyunkyu Lee

Taehoon Kim

Jong Sung Park

Sanggeun Jeon
title: A CMOS W Band Amplifier with Tunable Neutralization Using a Cross Coupled MOS varactor Pair
venue: Electronics
year: 2019

abstract: An ultra wideband (UWB) low noise amplifier (LNA) for 3.3 13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common gate (CG) topology utilizing feedback body biasing (FBB) which improves noise figure (NF) by a considerable amount. Parallel series tuned LC network was used between the common gate first stage and the cascoded common source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common drain buffer stage at the output provides high output reflection coefficient (S22) It achieves an average power gain (S21) of 14.7 0.5 dB with a noise figure (NF) of 3.0 3.7 dB. It has an input reflection coefficient (S11) less than 11.7 dB for 3.3 13.0 GHz frequency and output reflection coefficient (S22) of less than 10.6 dB with a very high reversion isolation (S12) of less than 72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.
author_names: Vikram Singh

Sandeep Kumar Arya

M Kumar
title: A 0.7 V, Ultra Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications
year: 2018

abstract: In this paper three types of 3.1 10.6GHz low noise amplifiers are analysed for RF receivers. Common gate LNA with differential active inductor is used capacitor cross coupled technique to improve nonlinear distortions, noise performance, inband gain flatness, linearity, frequency response and derivative super position technique is used to overcome capacitor cross coupled induced linearity deterioration. UWB CMOS LNA with presence of active inductor basis input matched network is presented. UWB CMOS LNA has 3 stages; a gm boosted CG input stage, a common source stage, and a common drain stage. Cascode CS LNA is designed in the absence of active inductor. These LNA's were designing under 1.8v supply.
author_names: Vajrala Venkata Santosh Krishna
title: Design of an Active Inductor based Low Noise Amplifier using 180nm Cmos Technology for RF Receivers
year: 2017

abstract: This paper presents a simple but accurate semi empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS LNA) in 2.5 GHz and 5.3 GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the model, circuit and validation results are done by computing and electrical simulations.
author_names: Rafaella Fiorelli

Eduardo J Peralias
title: Semi empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation
venue: Integr.
year: 2016

abstract: This brief presents the design and analysis of a 5.5 V class D stage used in two fully integrated watt level, +32.0 and 29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130 and 65 nm CMOS technologies. The class D stage utilizes a cascode configuration, driven by an ac coupled low voltage driver, to allow a 5.5 V supply in the 1.2 /2.5 V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common source transistors, and the equivalent on resistances are reduced by approximately 25% 50% and 25% compared to a conventional cascode (inverter) stage. To the authors' best knowledge, the class D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state of the art output power and bandwidth.
author_names: Jonas Fritzin

Christer Svensson

Atila Alvandpour
title: Analysis of a 5.5 V Class D Stage Used in 30 dBm Outphasing RF PAs in 130 and 65 nm CMOS
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2012

abstract: ABSTRACT This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high efficient common drain circuit provides high driving capability with relatively low power dissipation. It is used in more application for bandwidth and power and a high resolution is available for analog to digital converters (ADCs) Under 1 V supply voltage, the simulation results show that the proposed FLASH ADC Design is having a differential topology along with latching circuit.
author_names: M AbhilashKumar

Ajay Kumar Dadoria

Kavita Khare
title: Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology
year: 2014