Query: 3d chip stacking

Candidate papers:

abstract: We have successfully improved the scaling of Cu Cu hybrid bonding. In this study, 3 \mu \mathrm{ m} pitch and 3M Cu Cu connections with sufficient electrical properties and reliabilities were achieved. The ultra fine pitch Cu Cu connections correspond to the 0.75x scaling of conventional Cu Cu hybrid bonding that we previously reported. Our high density 3D chip stacking technology is expected to enhance not only the function of back illuminated CMOS image sensors (BI CIS) but also that of coming 3D stacked semiconductor devices.
author_names: Yoshihisa Kagawa

Shogo Hida

Y Kobayashi

Keishi Takahashi

Shunichi Miyanomae

M Kawamura

Hiroshi Kawashima

H Yamagishi

Tomoyuki Hirano

Keiji Tatani

H Nakayama

K Ohno

Hayato Iwamoto

S Kadomura
title: The Scaling of Cu Cu Hybrid Bonding For High Density 3D Chip Stacking
venue: 2019 Electron Devices Technology and Manufacturing Conference (EDTM)
year: 2019

abstract: Abstract Due to the advantages of small form factor, high performance, low power consumption, and high density integration, three dimensional integrated circuits (3D ICs) have been generally acknowledged as the next generation semiconductor technology. Low temperature bonding is the key technology to ensure the chip (or wafer) stacking in 3D ICs. In this paper, different low temperature bonding methods for chip (or wafer) stacking were reviewed and described systematically. Materials, processing and reliability will be extremely important, their effects on the 3D IC structure were addressed in detail, the challenging reliability issues may be considered as the major concern in the future work. The latest development of low temperature bonding in 3D ICs is also given here, which helpful may provide a reference for the further study of low temperature bonding.
author_names: Zhang Liang

Zhi-Quan Liu

Sinn-wen Chen

Yao-dong Wang

Wei-min Long

Guo Yonghuan

Song Wang

G Ye

Wen-yi Liu
title: Materials, processing and reliability of low temperature bonding in 3D chip stacking
year: 2018

abstract: 3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer) vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point source to provide fluid for each layer. The free dots form a capillary flow to fill the under chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller 'keep out' area occupation on the substrate.
author_names: Fuliang Le

Shi Wei Ricky Lee

Qiming Zhang
title: 3D chip stacking with through silicon vias (TSVs) for vertical interconnect and underfill dispensing
year: 2017

abstract: This article consists of a collection of slides from the author's conference presentation on low cost 3D chip stacking with ThruChip's wireless connections. Some of the specific topics discussed include: the challenges of current 3D stacking methods; the deployment of wireless technologies from a cost and bandwidth perspective; advancements in wafer thinning; stacked wireless data communication; and power distribution facilities.
author_names: David R Ditzel
title: Low cost 3D chip stacking with ThruChip wireless connections
venue: 2014 IEEE Hot Chips 26 Symposium (HCS)
year: 2014

abstract: Abstract The study aims at assessing the growth reaction of the Ni3Sn4 intermetallic compound (IMC) during bonding process and its dependences on the thermal cycling reliability of the Cu/Ni/SnAg micro joints of an advanced 3D chip stacking package under accelerated thermal cycling (ATC) loading. The growth reaction of the IMC during bonding process is also predicted through experiment and classical diffusion theory, and the relation between the IMC thickness and bonding process temperature and time is derived according to the predicted activation energy of the chemical reaction between Sn and Ni by experiment. Moreover, the micro joint reliability prediction is made using finite element (FE) analysis incorporated with an empirical Coffin Manson fatigue life prediction model and also ATC experimental test. To facilitate the FE modeling, the temperature dependent thermoelastic properties of both single crystal and polycrystalline Ni3Sn4 IMC are characterized through molecular dynamics simulation and the Voigt Reuss bound and Voigt Reuss Hill approximation. Results show that monoclinic single crystal Ni3Sn4 reveals a high elastic anisotropy or direction dependence of elasticity. The diffusion reaction of Sn and Ni exhibits that a longer bonding process time and a higher bonding temperature could not only increase the IMC thickness but also vary its surface morphology. In addition, the thermal mechanical performance of the micro joints is strongly affected by the geometry and material of IMC layer, where IMC with a thicker thickness, a less Young's modulus, a smaller CTE and even a more rounded surface morphology can better the reliability.
author_names: Wen-Hwa Chen

Ching-Feng Yu

Hsien-Chie Cheng

Yu-min Tsai

Su-Tsai Lu
title: IMC growth reaction and its effects on solder joint thermal cycling reliability of 3D chip stacking packaging
venue: Microelectron. Reliab.
year: 2013

abstract: With the impressive size shrinkage of advanced transistors and Cu/low k interconnect systems, the introduction of through silicon via integrated with three dimensional (3D) chip stacking approaches has become one of the major packaging technologies to meet the desired requirements of multifunctionality. The use of microbump @m bump) interconnected silicon chips to ensure the reliability of the interconnections is regarded as a critical issue that must be resolved. In this research, wafer level underfill (WLUF) joined with flip chip technology are proposed, and a nonlinear finite element analysis, combined with a process oriented simulation technique, is used to investigate the packaging assembly effect of the WLUF thermal compressive process. The stress predictions during the temperature cycling test is also systematically explored. The proposed simulation methodology is successfully validated through comparison with experimental data. The analytical results indicate that both the assembly and thermomechanical reliabilities of @m bumps are determined by the arrangement of the @m bump arrays. Consequently, the optimal designs of @m bump layouts within the chips must be seriously considered, given that silicon chips thinner than 100@mm are assembled in 3D advanced packages.
author_names: Chang-Chun Lee

Tsung-Fu Yang

Chih-Sheng Wu

Kuo-shu Kao

Ren-Chin Cheng

Tai-Hong Chen
title: Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer level underfill
year: 2013

abstract: The misalignment effect in three dimensional (3D) chip packages is studied numerically using the finite element method (FEM) The model features a through silicon via (TSV)/micro bump bonding structure connecting two adjacent silicon (Si) chips, with and without surrounding underfill. Misalignment is implemented through a prescribed shear deformation, and we seek to parametrically explore the trend of stress and deformation fields as affected by the geometry and material. Different solder thicknesses in the micro bump, as well as a special case where the entire solder region is transformed into the intermetallic compound, are considered in this study. The effects of shear deformation are also compared with those due to thermal expansion mismatch. A thinner solder region in the micro bump is found to have a higher propensity of damage initiation. The existence of underfill enhances the resistance to overall shear deformation, although with a much greater buildup of local stresses. With an intermetallic layer in place of the soft solder alloy in the micro bump, the overall shear strength of the structure increases but with a concomitant increase in the risk of local brittle failure.
author_names: Y -L Shen

R Wayne Johnson
title: Misalignment induced shear deformation in 3D chip stacking: A parametric numerical assessment
venue: Microelectron. Reliab.
year: 2013

abstract: 3D integration, using fine pitch and high density vertical interconnects (TSVs) has been drawing considerable interest due to its promise for higher performance and smaller form factor. As the number of I/O increases and the pitch size decreases, interconnect joining process and reliability become critical in the assembly of 3D chip stacks. In this study, 3D chip stacks with more than 48,000 Pb free solder micro bump interconnects at 50 mm pitch were assembled and the joint reliability evaluated. Multiple bonding processes were developed, enhanced and characterized by investigating the influence of various bonding parameters such as atmosphere, compression mode and temperature profile on the joint formation. Various test vehicle sizes with multiple layers of thinned die were successfully assembled using the enhanced bonding profile. Underfilling of the narrow gaps between the stack dies was demonstrated using underfills with fine particle fillers. The assembly yield and interconnection parasitic resistance was quantitatively studied as a function of the number of die layers. The reliability silicon die stacks integrated into modules with organic laminates was characterized by thermal cycling tests.
author_names: J Maria

Bing Dang

Steven L Wright

Cornelia K Tsang

Paul S Andry

Robert J Polastre

Yong Liu

L Wiggins

John U Knickerbocker
title: 3D Chip stacking with 50 mm pitch lead free micro c4 interconnections
venue: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC)
year: 2011

abstract: Recently, the three dimensional chip stacking technology with fine pitch and high input/output interconnects has emerged due to the requirements of multi function and high performance in electronic devices. When the electronic packaging technology develops toward the miniaturization trend, the reliability of interconnect with fine pitch and high density solder bump interconnections will become a critical issue in advanced 3D chip stacking technology. In this study, assembly of chip on chip test vehicle with a micro bump pitch of 30 um was demonstrated and the joint reliability was also evaluated. The Si chip/carrier used in this study had more than 3000 micro bumps with Sn2.5Ag solder material. Ni/Cu under bump metallurgy layer (UBM) was selected on both the top and bottom chip. 3D chip stacking was achieved by thermo bonding and subsequently underfill dispensing for fine gap filling was also conducted with different kinds of underfills. The temperature cycling test was performed on the chip on chip stacking module over 1000 cycles. In addition, with the joint size becoming small, the current for each solder bump carried continues to increase. This leads high current flowing in each individual joint. Therefore, electromigration has become a major reliability issue in microelectronic devices. In this study, electromigration in SnAg solder micro bump with a pitch of 30 mm was investigated under 0.12A at 135degC. Electromigration characteristics of fine pitch micro bump was discussed with the microstructure evolution of micro bump during current stressing. The assembly of 3D stacking chip using two layers of chip with fine pitch and lead free interconnects was achieved in this study. The results of reliability test showed that the reliability of fine pitch solder micro bump interconnections was acceptable under mechanical and electrical evaluations.
author_names: Chau-Jie Zhan

Chun-Chih Chuang

Jin-Ye Juang

Su-Tsai Lu

Tao-Chih Chang
title: Assembly and reliability characterization of 3D chip stacking with 30mm pitch lead free solder micro bump interconnection
venue: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
year: 2010

abstract: Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chip stacking technology have received a great number of attentions. Solder micro bumps are widely applied in high density interconnections packaging, but its bonding temperature is still high during process. During chip stacking process, high bonding temperature would lead chip damage and chip warpage induced by the mismatch of coefficient of thermal expansion among each structure within the chip. Also, warpage would cause stress concentration happened within the chip and damage the device and micro interconnections. In order to meet the purpose of low temperature bonding, we demonstrated the chip to chip stacking module with a bump pitch of 30um by using non conductive film in this study. The reliability of the chip stacking module produced by such low temperature bonding approach was also estimated. A chip on chip (COC) structure was used as the test vehicles. There were about 3000 bumps totally in this test vehicle. For evaluating the feasibility of adhesive bonding by NCF in fine pitch micro bumps, Cu/Ni/Au micro bumps joined with Cu/Sn solder micro bumps was conducted by using NCF in this study. After assembly process, thermal cycling test, thermal humidity storage test and high current test were carried out to evaluate the reliability performance of the micro interconnections by such low temperature bonding approach. In this investigation, the chip on chip stacking module with a bump pitch of 30mm by using non conductive film was achieved. The bonding results revealed that the contact resistance of micro joints was about 100 350 MO. The high deviation of contact resistance was due to the non melting contact between joined micro bump by soft tin solder. The reliability results revealed that the chip stacking module produced by NCF could pass the reliability test of 1000 cycles of TCT and 1000 hours of THST. The results of high current test also showed that the NCF joint had excellence endurance against high current density of 5x104 A/cm2 for more than 1300 hours with an increase of contact resistance less than 2% This study displayed that the NCF material had great potential to be applied in fine pitch 3D chip stacking. The multi chip stacking module with a TSV pitch of 20mm produced by NCF will also be presented in this investigation.
author_names: Yu-Min Lin

Chau-Jie Zhan

Kuo-shu Kao

Chia-Wen Fan

Su-Ching Chung

Yu-wei Huang

Shin-Yi Huang

Jing-Yao Chang

Tsung-Fu Yang

John H Lau

Tai-Hung Chen
title: Low temperature bonding using non conductive adhesive for 3D chip stacking with 30mm pitch micro solder bump interconnections
venue: 2012 IEEE 62nd Electronic Components and Technology Conference
year: 2012