Query: ESD Physics and Devices

Candidate papers:

abstract: About the Author.Preface.Acknowledgements.1. Electrostatics and Electrothermal Physics.2. Electrothermal and Methods of Analysis ESD Models.3. Semiconductor Device Physics and ESD.4. Substrates and ESD.5. Wells and Sub collectors and ESD.6. Isolation Technology and ESD.7. Drain Engineering, Salicides and ESD.8. Dielectrics and ESD.9. Interconnects and ESD.10. Silicon on Insulator (SOI) and ESD.11. Silicon Germanium and ESD.12. Nanostructures and ESD.Index.
author_names: Steven H Voldman
title: ESD: Physics and Devices
year: 2004

abstract: This paper revisits the physics of current filamentation in grounded gate NMOS (ggNMOS) devices and presents new physical insights which were not addressed in earlier works. A clear distinction between electrical and thermal instabilities is presented. Moreover, filament dynamics under electrical and thermal instability in both silicided and silicide blocked devices is discussed while highlighting observations which contradict with established theory of current ballasting. Interplay between electrical and thermal instabilities and its dependence on the presence or absence of silicide blocking is explored further. Filament spreading in ggNMOS devices and it is dependence on silicide blocking is discussed. Finally, while using the developed physical insights, missing correlation between TLP and HBM extracted failure current of silicided ggNMOS device is explained.
author_names: Milova Paul

Christian C Russ

B Sampath Kumar

Harald Gossner

Mayank Shrivastava
title: Physics of Current Filamentation in ggNMOS Devices Under ESD Condition Revisited
venue: IEEE Transactions on Electron Devices
year: 2018

abstract: This article provides an understanding of the transient voltage overshoot physics observed with electro static discharge (ESD) n type, p type, and n type diffusions (NPN) bipolar devices through the use of calibrated technical computer aided design (TCAD) with measured silicon results. This analysis graphically steps through each stage of the measured transient electrical response, to explain the inertia that limits the speed of the NPN ESD cell, and then uses this knowledge to provide a fully characterized silicon solution for ultrafast ESD events to achieve an 8 kV IEC61000 4 4 rating. This solution is developed by exploring five different integrated designs that are constructed on an 80 V bipolar and complimentary double diffused metal oxide semiconductor (BiCDMOS) process platform to protect against a product level 125 V voltage overshoot gate oxide ruptures as measured with a 0.6 ns rise time transmission line pulse (TLP) The fully characterized electrical results for each test overshoot structure with a fixed layout area of <inline formula> <tex math notation="LaTeX"$200\\mu \text{m}\times200\\mu \text{m} /tex math>/inline formula> are in parallel to NPN ESD cells arranged with two in series and two in parallel <inline formula> <tex math notation="LaTeX"$200\\mu \text{m}\times 80\\mu \text{m} /tex math>/inline formula> and compared in terms of the current carrying capability before the gate oxide rupture voltage of 125 V is reached. The results show that a diode engineered with a vertical breakdown achieves an ESD strength of 9.7 A before the overshoot voltage reaches the target of 125 V, resulting in a net 0.17 mA<inline formula> <tex math notation="LaTeX"\mu \text{m} {2} /tex math>/inline formula> The combined use of this vertical diode structure in parallel to the NPN ESD cell translates into a 7 A improvement in the strength of a conventional NPN for ultrafast timescales, which achieves the 8 kV International Electrotechnical Commission (IEC) ESD performance for this case study.
author_names: Edward Coyne

Dave Clarke

Stephen Heffernan

Brian Moane
title: Designing ESD Protection Devices for Ultrafast Overvoltage Events
venue: IEEE Transactions on Electron Devices
year: 2019

abstract: Abstract In this work, we build circuit models to understand the physics of electro thermal instability and associated thermal runway in advanced ESD protection devices under filamentation. The circuit building methodology takes into account, the instability arising out of inhomogeneous triggering of 2 D planar bipolar and looks into inherent instability causing the 3 D phenomenon. Subsequently, the electro thermal coupling is analyzed to get SPICE model, as we develop a physics based methodology to comprehend the 3 D localization in the device. Furthermore, we understand the instability through appropriate modeling of localization behavior using area factor a and related electro thermal circuit models.
author_names: Dheeraj Kumar Sinha

Amitabh Chatterjee
title: SPICE level implementation of physics of filamentation in ESD protection devices
venue: Microelectron. Reliab.
year: 2017

abstract: Circuits design that meets various IEC electrical overstress (EOS) standards is still a challenge, for that different kinds of EOS are at different frequency bands. In this paper, a physics based transient simulation and modeling method is proposed, which can simulate wide frequency EOS including electrostatic discharge (ESD) and AC characteristics. In this method, the physical model is used to characterize the nonlinear semiconductor devices in the finite difference timedomain (FDTD) SPICE co simulation. Moreover, the modeling and physical parameters extraction method of the ESD protect devices, the transient voltage suppressor diode, is demonstrated. Taking an EOS protection circuit for example, it is modeled and simulated by the proposed method. Moreover, the circuit is also simulated by the widely used System Efficient ESD Design (SEED) method, in which the TVS diode is modeled based on 100 ns Transmission Line Pulse (TLP) measurements. The experiments show that both this method and SEED method can characterize the IEC system level ESD behaviors well. However, the error of the SEED is about 219.2% at 10 MHz AC characteristics, but the maximum error of the proposed method is only 7.8% Hence, compared with the widely used SEED method, this method is more accurate when characterizing the EOS event during AC operation and switching. Index Terms Electric overstress, electrostatic discharge (ESD) transient simulation, wide frequency.
author_names: Zhenzhen Chen
title: A Physics based Transient Simulation and Modeling Method for Wide frequency Electrical Overstress Including ESD
year: 2021

abstract: A CMOS SCR compact model is developed for circuit simulation of ESD protection circuits. The model is comprised of coupled NPN and PNP transistors. A previously unnoted interaction between these transistors is described, resulting in improved agreement between simulation and measurement. This model addresses fundamental limitations of previous models, allowing for improved simulation accuracy, while limiting the number of parameters. The model parameters are scalable with respect to the layout spacings.
author_names: Robert Mertens

Elyse Rosenbaum
title: A physics based compact model for SCR devices used in ESD protection circuits
venue: 2013 IEEE International Reliability Physics Symposium (IRPS)
year: 2013

abstract: This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.
author_names: Mayank Shrivastava

Harald Gossner
title: A Review on the ESD Robustness of Drain Extended MOS Devices
venue: IEEE Transactions on Device and Materials Reliability
year: 2012

abstract: In order to obtain the damage rule of microwave semiconductor devices caused by electromagnetic pulse and study the electrostatic damage mechanism of the devices,the failure mode of semiconductor devices caused by ESD,such as apparent failure and potential failure,is introduced.The damage modeling is analyzed.Finally,the inherent damage reason of the device under electrostatic discharge stress is obtained by analyzing the physics mechanism of the burned device.Breakdown may happen under the action of ESD EMP,the internal electric field and the current density of the device increase,which cause the temperature rise and result in microwave semiconductor device burned.
author_names: Tan Zhiliang
title: Analysis of failure mechanism of microwave semiconductor devices caused by ESD
year: 2013

abstract: In this paper, we present the detailed physical insights into the electrostatic discharge (ESD) behavior of hydrogenated amorphous silicon (a Si:H) based thin film transistor (TFT) technology. Device failure under ESD conditions is studied in detail using electrical and optical techniques. Device degradation under ESD timescales is studied using real time capacitance voltage and a spatially variant degradation behavior is reported. Variations in material properties are studied before and after device failure using Raman spectroscopy. Device dimension dependent failure mechanism is explored. Impact of stressing conditions and presence of top passivation on failure behavior is also explored. Failure physics of technologically relevant device architectures including diode connected transistors (gated diodes) and drain underlap TFTs and their increased ESD robustness is discussed. Finally, ESD behavior of a Si:H based TFTs is discussed.
author_names: Rajat Sinha

Prasenjit Bhattacharya

Icko Eric Timothy Iben

Sanjiv Sambandan

Mayank Shrivastava
title: ESD Reliability Study of a Si:H Thin Film Transistor Technology: Physical Insights and Technological Implications
venue: IEEE Transactions on Electron Devices
year: 2019

abstract: In this paper, for the first time, the record high performance top gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top gate as well as back gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step by step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness.
author_names: Kranthi Karmel Nagothu

Abhishek Mishra

Adil Meersha

Mayank Shrivastava
title: On the ESD Behavior of Large Area CVD Graphene Transistors: Physical Insights and Technology Implications
venue: IEEE Transactions on Electron Devices
year: 2019