Query: A generic system simulator with novel on-chip cache and throughput models for gigascale integration

Candidate papers:

abstract: Future opportunities of gigascale integration are governed by a hierarchy of limits of which system limits are the most numerous, constraining, and difficult to define. A generic system simulator, GENESYS, is proposed as the most promising approach to identifying future system limits and opportunities. The GENESYS analysis tool assimilates the entire hierarchical description of a chip through a concise set of input parameters and projects its key performance metrics by engaging a set of interrelated models incorporating both physical principles and empirical knowledge. This research enables simultaneous consideration of both the implementation technology and architecture of future microprocessors through the unique integration of phenomena from each level of the hierarchy as well as the utilization of novel cycle time, generic on chip memory, and instructions per cycle models. GENESYS and its core models are verified by simulating commercial microprocessors and comparing the predictions with the actual areas, power dissipations, and throughputs. Based on the technology and integration levels projected by the National Technology Roadmap for Semiconductors (NTRS) and optimal multi level interconnect architectures and memory hierarchies identified by GENESYS, throughput is projected across the NTRS roadmap. Simulations indicate that the clock frequency and throughput become limited by global interconnects after 2006. For a given technology, GENESYS identifies the optimal zone of synchrony at which throughput reaches a maximum. Cellular array architectures or alternative novel architectures that ensure short wires will be required to sustain current rates of performance growth. This dissertation provides the first systematic approach to predicting the throughput of gigascale integration systems and elucidates the tradeoffs and physical limits as well as the opportunities of these systems.
author_names: John C Eble

Scott Wills

James D Meindl
title: A generic system simulator with novel on chip cache and throughput models for gigascale integration
year: 1998

abstract: The growing complexity of embedded multiprocessor architectures for digital media processing will soon require highly scalable communication infrastructures. Packet switched networks on chip (NoC) have been proposed to support the trend for systems on chip integration. In this paper, an advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on chip multi processors is introduced. It consists of a library of soft macros (switches, network interfaces and links) that are design time composable and tunable so that domain specific heterogeneous architectures can be instantiated and synthesized. Links can be pipelined with a flexible number of stages to decouple link throughput from its length and to get arbitrary topologies. Moreover, a tool called XpipesCompiler, which automatically instantiates a customized NoC from the library of soft network components, is used in this paper to test the Xpipes based synthesis flow for domain specific communication architectures.
author_names: Davide Bertozzi

Luca Benini
title: Xpipes: a network on chip architecture for gigascale systems on chip
venue: IEEE Circuits and Systems Magazine
year: 2004

abstract: The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs) combine the IPs into a working SoC. Moreover, the industry expects platform based SoC design to evolve to communication centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best effort services.
author_names: Kees G W Goossens

John Dielissen

Andrei Radulescu
title: AEthereal network on chip: concepts, architectures, and implementations
venue: IEEE Design Test of Computers
year: 2005

abstract: On chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system on chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time to market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug and play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.
author_names: Luca Benini

Giovanni De Micheli
title: Networks on Chips: A New SoC Paradigm
venue: Computer
year: 2002

abstract: We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC) and derive related Network on Chip (NoC) architecture and design process. SoC inter module communication traffic is classified into four classes of service: signaling (for inter module control signals) real time (representing delay constrained bit streams) RD/WR (modeling short data access) and block transfer (handling large data bursts) Communication traffic of the target SoC is analyzed (by means of analytic calculations and simulations) and QoS requirements (delay and throughput) for each service class are derived. A customized Quality of Service NoC (QNoC) architecture is derived by modifying a generic network architecture. The customization process minimizes the network cost (in area and power) while maintaining the required QoS.The generic network is based on a two dimensional planar mesh and fixed shortest path (X Y based) multiclass wormhole routing. Once communication requirements of the target SoC are identified, the network is customized as follows: The SoC modules are placed so as to minimize spatial traffic density, unnecessary mesh links and switching nodes are removed, and bandwidth is allocated to the remaining links and switches according to their relative load so that link utilization is balanced. The result is a low cost customized QNoC for the target SoC which guarantees that QoS requirements are met.
author_names: Evgeny Bolotin

Israel Cidon

Ran Ginosar

Avinoam Kolodny
title: QNoC: QoS architecture and design process for network on chip
venue: J. Syst. Archit.
year: 2004

abstract: Single chip multiprocessors are an important research direction for future microprocessors. The stigma of this approach is that many important applications cannot be automatically parallelized. This chapter presents a single chip multiprocessor that engages aggressive speculation techniques to enable dynamic parallelization of irregular, sequential binaries. Thread speculation (multiscalar execution) and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning and includes an aggressive correlated value predictor. Several new microarchitectural structures manage inter thread dependencies. On an eight processor system, simulated execution of SPECint95 binaries delivers a speedup of 3.4 over uniprocessor performance. This improvement is due entirely to the exploitation of dynamically extracted thread level parallelism. Introduction As semiconductor technology pushes towards billions of fast transistors on a chip, interconnect delay and design complexity become critical issues [56][23][84] The processor architectures popular today exploit Instruction Level Parallelism (ILP) The fundamental ILP techniques in use today were developed in an era when transistor size
author_names: Lucian Codrescu

D Scott Wills

James D Meindl
title: Atlas: a dynamically parallelizing chip multiprocessor for gigascale integration
year: 2000

abstract: Using on chip interconnection networks in place of ad hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc. communicate by sending packets to one another over the network. The structured network wiring gives well controlled electrical parameters that eliminate timing iterations and enable the use of high performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on chip network is modest, we estimate 6.6% This paper introduces the concept of on chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
author_names: William J Dally

Brian Towles
title: Route packets, not wires: on chip interconnection networks
venue: Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
year: 2001

abstract: Multiprocessor system on chip (MP SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system on chip (SoC) namely, those that incorporate modularity and explicit parallelism. To enable these MP SoC platforms, researchers have recently pursued scaleable communication centric interconnect fabrics, such as networks on chip (NoC) which possess many features that are particularly attractive for these. These communication centric interconnect fabrics are characterized by different trade offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade offs.
author_names: Partha Pratim Pande

Cristian Grecu

Michael Jones

Andre Ivanov

Resve A Saleh
title: Performance evaluation and design trade offs for network on chip interconnect architectures
venue: IEEE Transactions on Computers
year: 2005

abstract: Traditionally, design space exploration for systems on chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from computation based to communication based design becomes mandatory. As a result, the communication architecture plays a major role in the area, performance, and energy consumption of the overall system. This article presents a comprehensive evaluation of three on chip communication architectures targeting multimedia applications. Specifically, we compare and contrast the network on chip (NoC) with point to point (P2P) and bus based communication architectures in terms of area, performance, and energy consumption. As the main contribution, we present complete P2P, bus and NoC based implementations of a real multimedia application (i. e. the MPEG 2 encoder) and provide direct measurements using an FPGA prototype and actual video clips, rather than simulation and synthetic workloads. We also support the experimental findings through a theoretical analysis. Both experimental and analysis results show that the NoC architecture scales very well in terms of area, performance, energy, and design effort, while the P2P and bus based architectures scale poorly on all accounts except for performance and area, respectively.
author_names: Hyung Gyu Lee

Naehyuck Chang

Umit Y Ogras

Radu Marculescu
title: On chip communication architecture exploration: A quantitative evaluation of point to point, bus, and network on chip approaches
venue: TODE
year: 2008

abstract: Based on physical models, distributed circuit models are presented for single walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough <20 mum) For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3 nm2 cross sectional area
author_names: A Naeemi

James D Meindl
title: Design and Performance Modeling for Single Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems
venue: IEEE Transactions on Electron Devices
year: 2007