Query: Silicon VLSI technology: Fundamentals, Practice, and Modeling

Candidate papers:

abstract: (NOTE: Chapters 3 11 include an Introduction, Historical Development and Basic Concepts, Manufacturing Methods and Equipment, Measurement Methods, Models and Simulation, Limits and Future Trends in Technologies and Models, Summary of Key Ideas, References, and Problems. 1. Introduction and Historical Perspective. Introduction. Integrated Circuits and the Planar Process Key Inventions That Made It All Possible. Semiconductors. Semiconductor Devices. Semiconductor Circuit Families. Modern Scientific Discovery Experiments, Theory and Computer Simulation. The Plan for This Book. 2. Modern CMOS Technology. CMOS Process Flow. 3. Crystal Growth, Wafer Fabrication and Basic Properties of Silicon Wafers. 4. Semiconductor Manufacturing Clean Rooms, Wafer Cleaning and Gettering. 5. Lithography. 6. Thermal Oxidation and the Si/SiO2 Interface. 7. Dopant Diffusion. 8. Ion Implantation. 9. Thin Film Deposition. 10. Etching. 11. Backend Technology.
author_names: James D Plummer

Michael D Deal

Peter B Griffin
title: Silicon VLSI Technology: Fundamentals, Practice, and Modeling
year: 2020

abstract: silicon vlsi technology fundamentals practice and modeling is available in our digital library an online access to it is set as public so you can download it instantly. Our books collection hosts in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the silicon vlsi technology fundamentals practice and modeling is universally compatible with any devices to read.
author_names: Paul Ba 1/4 rger
title: Silicon Vlsi Technology Fundamentals Practice And Modeling
year: 2016

abstract: The continued scaling of integrated circuit technologies, along with the increased design complexity, has exacerbated the challenges associated with manufacturability and yield. In today's semiconductor manufacturing, lithography plays a fundamental role in printing design patterns on silicon. However, the growing complexity and variation of the manufacturing process have tremendously increased the lithography modeling and simulation cost. Besides, both the role and cost of resolution enhancement techniques (RETs) now indispensable in the design process have increased. Parallel to these developments are the recent advancements in Machine Learning (ML) which have provided a far reaching data driven perspective for problem solving. In this work, we shed light on the recent Deep Learning (DL) based approaches that have provided a new lens to examine traditional manufacturability and yield challenges. We present lithography modeling and simulation techniques, leveraging advanced learning paradigms, which have demonstrated unprecedented efficiency. Moreover, we demonstrate the role DL can play in advancing RETs by presenting its successful application in assist feature generation. Also critical to yield is the post fabrication wafer map defect analysis step which our work tackles using a novel confidence aware deep learning scheme. This paper further discusses the future prospects of DL based approaches in the scope of circuits manufacturability and yield.
author_names: Mohamed Baker Alawieh

Wei Ye

David Z Pan
title: Re examining VLSI Manufacturing and Yield through the Lens of Deep Learning (Invited Talk)
venue: 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
year: 2020

abstract: International Federation for Information Processing The IFIP series publishes state of the art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human computer interaction. Proceedings and post proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springer.com. For more information about IFIP, please visit www.ifip.org.
author_names: Ricardo Reis

Adam Osseiran

H Pfleiderer
title: VLSI SoC: From Systems to Silicon IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip VLSI SoC2005
year: 2007

abstract: After dominating the electronics industry for decades, silicon is on the verge of becoming the material of choice for the photonics industry: the traditional stronghold of III V semiconductors. Stimulated by a series of recent breakthroughs and propelled by increasing investments by governments and the private sector, silicon photonics is now the most active discipline within the field of integrated optics. This paper provides an overview of the state of the art in silicon photonics and outlines challenges that must be overcome before largescale commercialization can occur. In particular, for realization of integration with CMOS very large scale integration (VLSI) silicon photonics must be compatible with the economics of silicon manufacturing and must operate within thermal constraints of VLSI chips. The impact of silicon photonics will reach beyond optical communication its traditionally anticipated application. Silicon has excellent linear and nonlinear optical properties in the midwave infrared (IR) spectrum. These properties, along with silicon's excellent thermal conductivity and optical damage threshold, open up the possibility for a new class of mid IR photonic devices. Photonic band gap (PBG) materials are periodic dielectric structures that forbid propagation of electromagnetic waves in a certain frequency range. They are able to engineer the most fundamental properties of electromagnetic waves, such as the laws of refraction, diffraction and emission of light from atoms. Such PBG materials not only open up a variety of possible applications, but also give rise to new physics. Unlike electronic micro cavity, optical waveguides in a PBG microchip can simultaneously conduct hundreds of wavelength channels of information in a three dimensional circuit path. The thesis starts with the numerical modeling techniques for modeling as well as simulation of photonic crystal designs are introduced. The modeling techniques include finite difference time domain (FDTD) method and Plane Wave Expansion (PWE) method. The FDTD method has been represented in context to modal and polarization properties of the photonic design and PWE method has been represented in context to band gap analysis of the designed photonic structure.
author_names: Hem Pushp Mittal

Sanjay Sharma
title: Performance Analysis and Evaluation of Photonic Waveguides for Multiprocessor Communications A thesis submitted in partial fulfillment of the requirements for the award of degree of Master of Technology in VLSI Design CAD Submitted By:
year: 2011

abstract: Semiconducting carbon nanotubes (CNTs) have gained immense popularity as possible successors to silicon as the channel material for ultra high performance field effect transistors. On the other hand, their metallic counterparts have often been regarded as ideal interconnects for the future technology generations. Owing to their high current densities and increased reliability, metallic single walled CNTs (SWCNTs) have been of fundamental research both in theory as well as experiments. Metallic CNTs have been modeled for RF applications using an LC model. In this paper, we present an efficient circuit compatible RLC model for metallic SWCNTs, and analyze the impact of SWCNTs on the performance of ultra scaled digital VLSI design.
author_names: Arijit Raychowdhury

Kaushik Roy
title: Modeling and analysis of carbon nanotube interconnects and their effectiveness for high speed VLSI design
venue: 4th IEEE Conference on Nanotechnology, 2004.
year: 2004

abstract: Future collider experiments are typically motivated by the search for new particles and precision measurements of physical observables. The goal is to find deviations from existing theories. In practice, this requires advances towards higher luminosities at higher collision energies, finally resulting in a more difficult experimental environment. At the same time, more precise measurements are required. One such collider is the high luminosity upgrade of the LHC (HL LHC) that is planned to start operation in 2026. Compared to LHC, the number of simultaneous collisions (pile up) will increase by roughly a factor four and the radiation exposure of the detectors will be an order of magnitude larger than for LHC. Another proposed collider is the Compact Linear Collider (CLIC) that would provide electronpositron collisions at a centre of mass energy of up to 3TeV. As the collision partners are fundamental particles, the initial state and energy are well known. This allows for precision measurements of Higgs and Top quark observables, including a wide variety of measurements that are particularly sensitive to physics beyond the standard model. Here, the detector is required to deliver an unprecedented precision on the measurement of jet energy, impact parameter and particle momentum. For both colliders and their associated experiments, silicon detectors play an essential role in meeting the detection requirements. For CLIC, the desired momentum resolution together with the flavour tagging performance will require a vertex detector with a spatial resolution of around 3 mm and a time resolution better than 5 ns, all at a material budget of only 0.2%X0 per layer. This can be achieved by using thin silicon pixel sensors of around 50mm thickness. The design of the CLIC calorimeter is driven by the need of an unprecedented jet energy resolution. To achieve this, CLIC will employ a highly granular sampling calorimeter optimised for Particle Flow techniques. Silicon pad sensors will be used as active material in the electromagnetic calorimeter due to their compactness, operational stability, excellent signal to noise ratio and good segmentation properties. More recently, the CMS collaboration has decided to adopt a similar concept in the upgrade of their endcap calorimeters for the HL LHC phase, a project commonly called HGCAL. Here, the reasoning to use silicon as active calorimeter material is however broader. It is additionally driven by the need for radiation hardness and precise time stamping for pile up mitigation. In this work, the role of silicon detectors in the CLIC vertex detector as well as the calorimeters for
author_names: Florian Michael Pitters
title: Silicon Detector Technologies for Future Particle Collider Experiments
year: 2019

abstract: The ability to carry out signal processing, classification, recognition, and computation in artificial spiking neural networks (SNNs) is mediated by their synapses. In particular, through activity dependent alteration of their efficacies, synapses play a fundamental role in learning. The mathematical prescriptions under which synapses modify their weights are termed synaptic plasticity rules. These learning rules can be based on abstract computational neuroscience models or on detailed biophysical ones. As these rules are being proposed and developed by experimental and computational neuroscientists, engineers strive to design and implement them in silicon and en masse in order to employ them in complex real world applications. In this paper, we describe analog very large scale integration (VLSI) circuit implementations of multiple synaptic plasticity rules, ranging from phenomenological ones (e.g. based on spike timing, mean firing rates, or both) to biophysically realistic ones (e.g. calcium dependent models) We discuss the application domains, weaknesses, and strengths of various representative approaches proposed in the literature, and provide insight into the challenges that engineers face when designing and implementing synaptic plasticity rules in VLSI technology for utilizing them in real world applications.
author_names: Mostafa Rahimi Azghadi

Nicolangelo Iannella

Said F Al-Sarawi

G Indiveri

Derek Abbott
title: Spike Based Synaptic Plasticity in Silicon: Design, Implementation, Application, and Challenges
venue: Proceedings of the IEEE
year: 2014

abstract: The thermal environment in VLSI circuits is characterized by the existence of both small and isolated heat sources near the channel region and a vast volume (e.g. substrate) serving as the heat conduction media. The presence of a buried oxide layer in Silicon on Insulator technology introduces an additional thermal barrier between the device and Si substrate. The modeling and simulation of such situations are usually handled with either element based simulations (e.g. finite element methods, lumped element methods) or direct methods based on integral transform. In practice neither approach can maintain both accuracy and efficiency at the same time. We have developed a new methodology for the simulation of the thermal behavior of high density integrated circuits at various levels of complexity. It treats the structured thermal conduction media hierarchically and thus is capable of relating thermal behaviors over a wide range of length scales. As a demonstration this methodology is applied to model heat conduction and self heating effects in SOI technology. Compared to the traditional element based numerical method used to solve the Laplace equation, out method greatly reduces the number of nodes and the computing time while maintaining accuracy.
author_names: Kai Xiu

Mark B Ketchen
title: Hierarchical thermal modeling for SOI technology
venue: Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545)
year: 2004

abstract: Semiconducting carbon nanotubes (CNTs) have gained immense popularity as possible successors to silicon as the channel material for ultrahigh performance field effect transistors (FETs) On the other hand, their metallic counterparts have often been regarded as ideal interconnects for future technology generations. Owing to their high current densities and increased reliability, metallic single walled CNTs (SWCNTs) have been subjects of fundamental research, both in theory, as well as experiments. Metallic CNTs have been modeled for radio frequency (RF) applications using a transmission line model. In this paper, we present an efficient circuit compatible RLC model for metallic SWCNTs, and analyze the impact of SWCNTs on the performance of ultrascaled digital very large scale integration (VLSI) design.
author_names: Arijit Raychowdhury

Kaushik Roy
title: Modeling of metallic carbon nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies
venue: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
year: 2006