Query: Heterogeneous 2.5D integration on through  silicon interposer

Candidate papers:

abstract: Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs) In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through Si Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low power/high performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates) and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity <1 mm separation) compared with several centim.
author_names: Xiaowu Zhang

Jong-Kai Lin

Sunil Wickramanayaka

Songbai Zhang

Roshan Weerasekera

Rahul Dutta

Ka Fai Chang

King Jien Chui

Hongyu Li

David Ho

Liang Ding

Guruprasad Katti

Suryanarayana Shivakumar Bhattacharya

Dim Lee Kwong
title: Heterogeneous 2.5D integration on through silicon interposer
year: 2015

abstract: The optimal selection of an interposer substrate is important in 2.5D systems, because its physical, material and electrical characteristics govern the overall system performance, reliability and cost. Several materials have been proposed that offer various tradeoffs including silicon, organic, glass and etc. In this paper, we conduct a quantitative comparison between two 2.5D IC designs based on silicon vs. liquid crystal polymer (LCP) interposer technologies in the overall system level for the first time. We also investigate tradeoffs in power, performance and area (PPA) signal integrity (SI) and power integrity (PI) depending on the interposer technologies. Through our flow, we generate a large scale benchmark architecture with commercial grade GDS layouts of interposer and chiplets using two different interposer substrates. Then, we model transmission lines and power delivery network (PDN) of each 2.5D IC design. Finally, we perform PPA analysis, SI and PI on both 2.5D IC designs to observe the quantitative tradeoffs between two designs. Our experiment shows that silicon interposer based design has 10.46% less power, 0.25x smaller area and 0.57x shorter average wirelength compared to LCP interposer based design. However, LCP based design has 0.59x smaller PDN DC impedance and 0.75x shorter worst delay of interposer wire while maintaining the power delivery efficiency. Lastly, our cost analysis of 2.5D IC design indicates that the overall cost of organic LCP technology, if both the chiplets and their interposer costs are combined, is 2.69x higher than the silicon even the cost of LCP interposer is 1.91% of silicon interposer. This indicates that LCP technology is prohibitive unless the interconnect and bump dimensions are dramatically reduced.
author_names: Jinwoo Kim

Venkata Chaitanya Krishna Chekuri

Nael Mizanur Rahman

Majid Ahadi Dolatsara

Hakki Mert Torun

Madhavan Swaminathan

S Mukhopadhyay

Sung Kyu Lim
title: Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration
venue: 2020 IEEE 38th International Conference on Computer Design (ICCD)
year: 2020

abstract: Silicon interposers are providing interesting alternatives to organic packages for the fabrication of complex system in package (SIP) modules in particular for RF application. Among the advantages of this technology are the capability to fabricate fine pitch redistribution layers and to embed inside the interposer some high quality passive elements very close to the active chips resulting in a highly integrated solution. To keep the technology at a reasonable cost these last add on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. In this work we present the design and the fabrication of a high resistive silicon interposer conceived for hosting a functional RF SIP transceiver including a Front End Module (FEM) a Dual Band Dual Mode Power Amplifier working at 400 and 900 MHz and some embedded planar and 3D inductors. The interposer consists in symmetrical stack with one thick level of copper RDL on each side of the 200 um thin HR silicon substrate and connected with through silicon via last (TSV last) The inductors are built with no additional metallization level. For the inductors development, a dedicated test vehicle was first designed to study different designs including planar spirals and 3D solenoids and torus. Simulation work was first carried out for dimensioning the structures to target inductance values in the range of 0.5 to 10 nH and high quality factor greater than 20. We present the process used for the fabrication, in particular the realization of the thick copper RDL layers on both sides of the interposer and the of the TSV last module. Physical characterization are presented showing the integrity and the good control of the technology. DC and RF electrical measurements assess the performances achieved for the different inductor variants exhibiting low resistance, constant inductance up to 5 GHz and factor of quality higher than 30. The functional RF transceiver SIP module will be then presented. The architecture is an extremely compact multi chip module composed of four actives CMOS chips (VGA, VCO, modulator and the PA) stacked by flip chip with Cu/SnAg ubumps on the HR silicon interposer and surrounded by a hundred of passive SMD components. With this technology the footprint of the module is reduced by a factor of 2 in comparison with the same module made on a uPCB substrate. The signals and ground are fed through the thick copper RDL lines and the TSVs from LGA pads present on the backside of the interposer for assembly on a test board. Different design configurations are made on the same wafer that include some version using only SMD inductors and some using 2.5 and 3D inductors in order to compare the corresponding performances. Other test structures are also present like filters and individual inductors for DC and RF characterization. We will finally present the resulting performances obtained from this SIP integration.
author_names: Gabriel Pares

Michel Jean-Philippe

Deschaseaux Edouard

Ferris Pierre

Serhan Ayssar

Giry Alexandre
title: Highly Compact RF Transceiver Module Using High Resistive Silicon Interposer with Embedded Inductors and Heterogeneous Dies Integration
venue: 2019 IEEE 69th Electronic Components and Technology Conference (ECTC)
year: 2019

abstract: As faster data processing and communication gets more demanded for Data Center/Cloud, HPC (High Performance Computing) AI (Artificial Intelligence) accelerator and Network markets, HBM (High Bandwidth Memory) becomes main memory type to meet the required bandwidth performance. HBM integration with logic dies in a system level has been developed on 2.5D SiP (System in Package) Platform with Si Interposer having TSV (Through Silicon Vias) of which fabrication cost is rather high. Therefore, as the low cost solution, alternative 2.5D SiP Platform approaches such as Organic Interposer using Redistribution Layer (RDL) and Glass Interposer have recently been reported. In this paper, RDL Interposer package with 4 HBM and 1 logic is demonstrated as 2.5D package platform based on RDL First Fan out Wafer Level Package (FOWLP) The effect of RDL design factors on electrical performances is investigated using the eye diagram method and fine pitch multi layer RDL structure (2um L/S RDL, 4 Layers) is designed accordingly. Fine pitch RDL process is established followed by the wafer level and unit level assembly processes and RDL Interposer package is confirmed to meet all the reliability requirements.
author_names: Jae-gwon Jang

Kyoung-Lim Suk

Seok-Hyun Lee

Jin-Woo Park

Gwang-jae Jeon

Jung-ho Park

Jeong-gi Jin

Su-chang Lee

Gyoung-bum Kim

Joo-yeon Choi

Dae-woo Kim

Dan Oh

Won-Kyoung Choi
title: Advanced RDL Interposer PKG Technology for Heterogeneous Integration
venue: 2020 International Wafer Level Packaging Conference (IWLPC)
year: 2020

abstract: As the costs of advanced node silicon have risen sharply with the 7 and 5 nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single die packages will still be around, the high end market is shifting towards multiple die packages to reduce overall costs and improve functionality. This shift is not just to add local memory, such as the addition of high bandwidth memory (HBM) module(s) to an application specific integrated circuit (ASIC) die, but also to separate what would have been a monolithic ASIC in prior generations to its constituent parts, such as the central processing unit (CPU) cores, serializer/deserializer (SerDes) and input/output (I/O) blocks. By splitting the monolithic die into smaller functional blocks, costs can be reduced through improved wafer yield on the smaller CPU cores and re using older, vetted intellectual property (IP) from a prior silicon node for the I/O and SerDes that do not necessarily need the most advanced silicon node.The traditional approach to fine pitch multi die packaging has been silicon interposers with Through Silicon Vias (TSVs) While the TSV approach has ushered in new performance levels never seen before, one of the major limitations is the inability to scale with higher and higher frequencies. The maximum frequency that a silicon interposer can handle between die to die interconnects is approximately 4 GHz due to the parasitics of the silicon. As dieto die interconnects increase their bandwidth to higher and higher levels, the 4 6 GHz limitation can become a major bottleneck. Eliminating the silicon and silicon dioxide dielectrics and using polymers as the dielectric and the interposer itself can solve this problem.This paper will discuss how to use High Density Fan Out (HDFO) technology to replace the TSV bearing silicon interposer with an organic interposer to enable higher bandwidth die to die interconnects for heterogeneous integration.
author_names: George Scott

JaeHun Bae

KiYeul Yang

WonMyoung Ki

Nathan Whitchurch

Mike Kelly

Curtis Zwenger

JongHyun Jeon

Taekyeong Hwang
title: Heterogeneous Integration Using Organic Interposer Technology
venue: 2020 IEEE 70th Electronic Components and Technology Conference (ECTC)
year: 2020

abstract: To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high K (HK) based deep trench capacitors (DTC) have been integrated the first time in the silicon interposer with through silicon via (TSV) and fine pitch interconnects for chip on wafer on substrate (CoWoS) integration. A specific capacitance density (Cs) of up to 340 nF/mm2 is achieved over a large capacitor array, providing a total capacitance (Ct) of up to 68 mF per interposer die. The HK dielectric has intrinsic time dependent dielectric breakdown (TDDB) lifetime of 1,000 years at an operation voltage (Vcc) of 1.35V, and a normalized leakage current (ILK) density 1 fA/mm2 under 1.35V at 105deg C. No discernable process induced damage or performance degradation (capacitance, ILK Vbd tailing) were observed. The high capacitance, low leakage, large area and reliability proven Si interposer integrated DTC, or iCap, provides superior PI performance and therefore greatly enhances the merit of using CoWoS for the next generation heterogeneous wafer level system integration (WLSI)
author_names: S Y Hou

C -H Wu

Douglas Yu

H Hsia

Chung-Hao Tsai

K C Ting

Tsung-Hsin Yu

Y W Lee

F C Chen

W C Chiou

C -T Wang
title: Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration
venue: 2019 IEEE International Electron Devices Meeting (IEDM)
year: 2019

abstract: A new trend in system on chip (SoC) design is chiplet based IP reuse using 2.5 D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off the shelf intellectual properties (IPs) allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5 D designs. Our target design is 64 core architecture based on Reduced Instruction Set Computer (RISC) V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64 core processor into chiplets, which are enhanced with our centralized network on chip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip to chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5 D design. Our design space exploration (DSE) study shows that 2.5 D integration incurs $1.29\times power and $2.19\times area overheads compared with 2 D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5 D integrated chip (IC) designs.
author_names: Jinwoo Kim

Gauthaman Murali

Heechun Park

Eric Qin

Hyoukjun Kwon

Venkata Chaitanya Krishna Chekuri

Nael Mizanur Rahman

Nihar Dasari

Ashutosh Kumar Singh

Minah Lee

Hakki Mert Torun

Kallol Roy

Madhavan Swaminathan

S Mukhopadhyay

Tushar Krishna

Sung Kyu Lim
title: Architecture, Chip, and Package Codesign Flow for Interposer Based 2.5 D Chiplet Integration Enabling Heterogeneous IP Reuse
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2020

abstract: Data intensive applications such as high performance computing (HPC) and artificial intelligence (AI) have recently become major subjects in industry. The heterogeneous integration of a chip and high bandwidth memories (HBMs) using through silicon via (TSV) based interposer has gained attractions to meet their performance requirements. An introduction of micro bump systems of these heterogeneous components (ex, a reticle limited GPU chip and HBMs) can created challenges in chip on wafer (COW) stacking. The impacts of heterogeneous micro bump systems and a giant GPU chip on COW stacking process are investigated in two micro pad systems. Micro bump system with adding a material layer or layers between Cu pillar and SnAg solder is found to be effective in modifying micro bump melting characteristics. It demonstrated the chip warpage dependent micro bump integrity. Micro bump joints formed by both micro pad systems passed reliability requirement without electrical, mechanical, microstructural failures.
author_names: Jaesik Lee

Chun Yang Lee

Chon-Su Kim

Shantanu Kalchuri
title: Micro Bump System for 2nd Generation Silicon Interposer with GPU and High Bandwidth Memory (HBM) Concurrent Integration
venue: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
year: 2018

abstract: In this paper, a high resistivity silicon (HR Si) interposer integrated with through silicon via (TSV) electrically grounded coplanar waveguide (CPW) line is presented for 2.5 D/3 D heterogeneous integration of radio frequency (RF) microelectronics devices. In addition, design of TSV interconnection composed of two coaxial ladder hollow annular Cu (copper) TSVs of different diameters is utilized to maintain a sufficient freedom for strict standard cleaning to avoid Si resistivity degradation. The formation of the coaxial ladder TSV structure is more beneficial to the subsequent plating process because it reduces the aspect ratio of TSV vias. Hollow annular Cu TSV is manufactured in order to reduce the problem of mismatch in coefficient of thermal expansion among TSV's constituent materials. A layer of Au (aurum) film is utilized to passivate the exposed Cu surface of Si interposer. Au is widely used in III V groups' devices because of the good compatibility with photonic integrated circuits, conductivity, and corrosion resistance. HR Si interposer with TSV grounded CPW line and test structure is fabricated and characterized. With the monitoring test results, it can be found that it changes little in the resistivity of Si substrate, though the whole process, which is a basic requirement for RF performance. RF property test results show that the insertion loss is about 0.20 dB/mm at 10 GHz for the presented TSV grounded CPW line and 0.02 dB per TSV. These test results are better than the traditional design. To verify its applicability to 2.5 D/3 D heterogeneous integration, RF microelectronics die is assembled on TSV interposer and tested, and the test results prove that it works properly.
author_names: Jun Yan

Shengli Ma

Yufeng Jin

Weiqi Wang

Jing Chen

Rongfeng Luo

Han Cai

Jiwei Li

Yanming Xia

Lilin Hu

Shuwei He

Zhongjun Tang
title: Fabrication and RF Property Evaluation of High Resistivity Si Interposer for 2.5 D/3 D Heterogeneous Integration of RF Devices
venue: IEEE Transactions on Components, Packaging and Manufacturing Technology
year: 2018

abstract: Recent advances in die stacking and 2.5D chip integration technologies introduce in package network heterogeneities that can complicate the interconnect design. Integrating chiplets over a silicon interposer offers new opportunities of optimizing interposer topologies. However, limited by the capability of existing network on chip (NoC) simulators, the full potential of the interposer based NoCs has not been exploited. In this paper, we address the shortfalls of prior NoC designs and present a new family of chiplet topologies called Kite. Kite topologies better utilize the diverse networking and frequency domains existing in new interposer systems and outperform the prior chiplet topology proposals. Kite decreased synthetic traffic latency by 7% and improved the maximum throughput by 17% on average versus Double Butterfly and Butter Donut, two previous proposals developed using less accurate modeling.
author_names: Srikant Bharadwaj

Jieming Yin

Bradford M Beckmann

Tushar Krishna
title: Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect Modeling
venue: 2020 57th ACM/IEEE Design Automation Conference (DAC)
year: 2020