Query: VLSI Chip Design Market trends

Candidate papers:

abstract: As the move to very deep submicron VLSI devices pushes the threshold of semiconductor technology, conventional test and diagnosis methods become inadequate and costly. The new level of complexity driven by core based system chips demands that designers alter the way they approach chip development in order to keep up with diminishing time to market requirements and stay within budgets. Embedded test enables the production of higher quality devices in less time. The use of embedded test raises margins and significantly reduces the time required for system verification, test and debug. This paper addresses discusses embedded test technology and analyzes its impact on time to market, product quality and cost.
author_names: Yervant Zorian
title: Emerging trends in VLSI test and diagnosis
venue: Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System on Chip Era
year: 2000

abstract: We entered the very large scale inteuration (VLSI) era in 1975. Since that time VLSI technoiugy has been, and continues to be, refined and improved. We have moved from diffusion to ion implantation, from wet etching to dry etching, and from contact printing to scanning projection or step and repeat lithography. By 1990 we will employ larger silicon wafers ~150 mm in diameter) smaller feature lengths ~0.5 um) and lower processing temperatures <900degC) Process simulation and advanced diagnostic techniques will be extensively used for on line process design and for reliability analysis, respectively. Ultra sophisticated chips with millions of components and on chip system organizations will be built in response to the enormous market demand of the Information Age. This paper discusses those advances and future trends in VLSI technology.
author_names: S M Sze
title: Invited) VLSI Technology Overviews and Trends
year: 1983

abstract: The increasing market trends of extremely low power operated handy applications like laptop, electronics gadgets etc requires microelectronic devices with low power consumption. It is obvious that the transistor dimensions continues to shrink and as require for more complex chips increases, power management of such deep sub micron based chip is one of the major challenges in VLSI industry. The manufacturers are always targeting for low power designs for the reason that to provide adequate physical resources to withstand against design hurdles and this lead to increases the cost and restrict the functionality of the device. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression technique, merger of logically equivalent transistors to an eccentric latch structure. Fewer transistors, only three, connected to clock signal which reduces the power drastically, and the smaller total transistor count assures to retain the chip area as conventional FFs. In addition, fully static full swing operation makes the cell lenient of supply voltage and input slew variation. An experimental chip design with 32 nm CMOS technology shows that almost all conventional FFs are expendable with proposed FF while preserving the same system performance and layout area. The performance of this paper is evaluated on the design simulation using Microwind 3.1 simulator
author_names: U Somalatha

S Chandana
title: Design of Low Power Topologically Compressed Static Flip Flop
year: 2018

abstract: Since their introduction in the 1970s, Programmable Logic Devices (PLDs) evolved from implementing small glue logic designs to large, configurable multi processor Systems on Chip (SoC) Today's most prominent PLD technology, known as FPGA (Field Programmable Gate Array) is used in an increasing number of application domains, such as the telecom industry, the automotive electronics sector or automation technology, and recent market studies expect a continuous demand for these sophisticated microelectronic devices in the future. For small and medium enterprises and/or SME dominated countries like Austria, FPGAs can provide access to VLSI (Very Large Scale Integration) technology by avoiding the immense NRE (Non Recurring Engineering) costs of ASICs (Application Specific Integrated Circuits) This work outlines how today's and future electronic based systems can benefit from FPGA technology. Trends, tools and design flows will be explained as well as research challenges that are currently investigated within two public funded R&D projects at the University of Applied Sciences Technikum Wien. Programmierbare Logikbausteine (PLDs) haben sich seit ihrer Markteinfuhrung in den 1970er Jahren von kompakten Implementierungsmoglichkeiten fur simple Glue Logic zu komplexen programmierbaren Multiprozessor Systems on Chip (SoC) entwickelt. Die heutzutage gebrauchlichste PLD Technologie, sogenannte FPGAs (Field Programmable Gate Arrays) werden in einer Vielzahl von Applikationsdomanen, etwa in der Telekommunikation, aber auch in Bereichen wie Fahrzeugelektronik oder der Automatisierungstechnik, verwendet, wobei Marktstudien einen weiterhin steigenden Bedarf dieser hochentwickelten mikroelektronischen Bauelemente in den nachsten Jahren erwarten. Gerade fur KMU dominierte Lander wie Osterreich eroffnet die FPGA Technologie die Moglichkeit zur Realisierung von VLSI (Very Large Scale Integration) Designs unter Vermeidung der in diesem Bereich mittlerweile exorbitanten Einmalkosten bei der Herstellung von ASICs (Application Specific Integrated Circuits) Dieser Artikel beschreibt, wie moderne elektronische Systeme von den Vorteilen der FPGA Technologie profitieren konnen. Trends, Tools und Design Flows werden beschrieben sowie aktuelle Forschungsfragen, die derzeit im Rahmen zweier offentlich geforderter F&E Projekte an der FH Technikum Wien bearbeitet werden.
author_names: Peter Rossler

Roland Holler
title: Programmable logic devices key components for today's and tomorrow's electronic based systems
venue: Elektrotech. Informationstechnik
year: 2020

abstract: Since their introduction in the 1970s, Programmable Logic Devices (PLDs) evolved from implementing small glue logic designs to large, configurable multi processor Systems on Chip (SoC) Today's most prominent PLD technology, known as FPGA (Field Programmable Gate Array) is used in an increasing number of application domains, such as the telecom industry, the automotive electronics sector or automation technology, and recent market studies expect a continuous demand for these sophisticated microelectronic devices in the future. For small and medium enterprises and/or SME dominated countries like Austria, FPGAs can provide access to VLSI (Very Large Scale Integration) technology by avoiding the immense NRE (Non Recurring Engineering) costs of ASICs (Application Specific Integrated Circuits) This work outlines how today's and future electronic based systems can benefit from FPGA technology. Trends, tools and design flows will be explained as well as research challenges that are currently investigated within two public funded R&D projects at the University of Applied Sciences Technikum Wien.
author_names: Peter Rossler

Roland Holler
title: Programmable logic devices key components for today's and tomorrow's electronic based systems
year: 2020

abstract: In the past decade, CMOS technology has played a major role in the rapid ad vancement and the increased integration of VLSI systems. CMOS devices feature high input impedance, extremely low offset switches, high packing density, low switching power consumption, and most importantly, they are easily scaled. With the reduction of the device minimum feature size, in order to prevent the transistor from breakdown because of the higher electrical field across the gate oxide and to ensure its reliability, the power supply voltage is necessary to be reduced. W ith the reduction of the device minimum feature size, more and more transistors can be fabricated into a single chip. Nevertheless, the large amount of circuits inte grated in a chip result in huge power consumption. Decrease of the supply voltage can not only ensure the device reliability, but also reduce power consumption in a sig nificant amount. Furthermore, portable/mobile electronic equipments have become the trends of the present and future market demands. Low power supplies are the requirements of the portable/mobile electronic products. In this dissertation, we focus on the low voltage, low power CMOS circuit de sign. Each circuit either features a rail to rail common mode input voltage and/or consumes very low power. These circuits target applications in mobile telecommuni cations (rail to rail strong inversion circuits) and in (portable) medical applications
author_names: Chung-Chih Hung
title: Low voltage, low power CMOS analog circuit design techniques for mobile, portable VLSI applications
year: 1997

abstract: From the past years, research in reversible logic has done very efficiently. It includes synthesis, optimization, simulation and verification. By the reversible structure excessive garbage inputs are eliminated, which in turn the power and speed of the logic design is efficiently utilized. In this paper we are proposed an Array Multiplier which has high performance factors. From recent years the research has going on multipliers to reduce the partial product number. To eliminate this problem we introduced an array multiplier using reversible full adder and reversible half adders. Because every Very Large Scale Integrated (VLSI) circuit designers wants to their circuits should produce less delay and efficient power utilization, because to keep their designs high demands on the market. For this we proposed an array multiplier with reversible half adder and multiplexer based reversible full adder. By this design the combinational path delay and chip area are decreased. Array multiplier is an important design in VLSI because, Multiplication involves key role in Arithmetic and Logical operations. We developed all these designs using Very high speed Hardware Description Language (VHDL) and results are verified through simulation using Xilinx ISE
author_names: K Yugandhar

V Ganesh Raja

M Tejkumar

Dhandapani Siva
title: High Performance Array Multiplier using Reversible Logic Structure
venue: 2018 International Conference on Current Trends towards Converging Technologies (ICCTCT)
year: 2018

abstract: The growing need of the SoC market and recent trends in embedded systems, force designers to come up with solutions to speed up the chip design and development process. Each embedded system has to be designed in a comparatively short time with minimum bugs and these issues force the designers to adopt new techniques and technologies. In this paper a novel and speedy approach using a comparatively newer language in design, SystemVerilog is introduced. A configurable and reusable Liquid Crystal Display (LCD) Controller is designed and developed using SystemVerilog. The approach presented here is faster and more efficient compared to traditional methods of design. The LCD Controller was successfully designed, developed and validated in FPGA.
author_names: Mithuna Chandran O

T T Libin

S Krishnakumar Rao

Biju C Oommen
title: SystemVerilog based design and implementation of LCD Controller IP Core
venue: 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
year: 2015

abstract: Conventional CMOS memory i.e. Static Random Access Memory (SRAM) has been the popular choice for embedded memory application for last several decades. However, SRAM seems to be approaching a brick wall. On one hand process variability and leakage power is posing severe obstruction towards SRAM scaling to future nodes and on the other hand, emerging energy constrained and bandwidth hungry electronic gadgets demand for larger as well as energy efficient on chip cache which cannot be satisfied with SRAM. To address the changing landscape of consumer market, there is a corresponding need of changing the design paradigm. What is really needed is a memory technology that is at least 50 100X denser, 1000X energy efficient and as fast as SRAM. Several emerging memory technologies are on the horizon but there is no clear universal choice for embedded application. This tutorial will explore the latest trends in the embedded memory segment and discuss the fundamental limitations of SRAM in meeting the new needs of the electronic systems. The complex (and not very well understood) interrelationships between memory density, bandwidth, latency, power and speed will be elaborated in the context of emerging graphics applications. Next the tutorial will discuss few promising emerging memory technologies where storage element is based on charge, spin and resistance. Specifically, the tutorial will focus on the operating principles, design challenges and solutions of volatile memory such as embedded Dynamic Random Access Memory (eDRAM) and non volatile memories (NVM) such as Domain Wall Memory (DWM) and memrister. The eDRAM section of the tutorial will present the trade offs such as low power peripherals (e.g. wordline driver, sense amplifier) and its impact on random access time (tRC) and retention. The relationship between noise sources (e.g. process variations, coupling effects) and retention power will also be described. Design techniques such as pulsed sense amplifier, peripheral sleep etc. will be introduced to control and mitigate the effect of noise in high speed eDRAM arrays for future technology nodes. Next the tutorial will describe DWM which is a spin based memory technology. Various design metrics such as read/write power, speed, reliability and retention will be discussed in detail. The tutorial will address the modeling and simulation methodology for design and analysis of DWM arrays. Various design challenges such as reliable shift circuitry, positioning of read/write head, impact of process variations on sense margin, reliability of nanowire etc. will be described. Design techniques to improve robustness, operating speed and array density will also be presented. The last part of this tutorial will describe memrister where the storage element is resistive in nature. Typically memrister suffer from high access power. Design techniques to lower the power consumption such as data encoding, write pause etc. will be discussed to mitigate the power while maintaining required robustness. The audiences will be able to takeaway following key points from this tutorial (a) changing landscape of emerging electronic systems and inability of SRAM to cater to these new needs in scaled technologies, (b) emerging memory technologies for embedded applications and their relative merits in terms of density, power, speed and reliability, (c) design methodologies, challenges and potential solutions to enable these emerging memories for embedded applications.
author_names: Swaroop Ghosh
title: Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions
venue: VLSI Design
year: 2014

abstract: The increasing complexity of systems on chip (SoCs) has led to the critical "design productivity gap" problem. Several strategies are being employed to cope with this problem, including an IP based design flow, as well as platform based designs for application domains. These approaches have critically increased the amount of on chip communication. Since on chip communication architectures have a significant impact on system performance, power dissipation and time to market, system designers, as well as the research community have focused on the issue of exploring, evaluating, and designing SoC communication architectures to meet the targeted design goals. On the other hand, aggressive scaling of VLSI technology has resulted in nanoscale effects that adversely affect interconnect performance, reliability, power dissipation, and predictability; new approaches to on chip communication architectures (e.g. networks on chip) need to be devised in order to overcome these effects. The tutorial is structured into four parts, covering: i) scaling trends in nanometer interconnects and related methodology challenges; ii) architectural modeling and analysis of communication traffic and synthesis of current on chip bus based communication architectures iii) high performance bus protocols and topologies, including design examples; and iv) emerging network on chip (NoC) paradigms for next generation designs. The tutorial begins by highlighting the key emerging issues in the domain of interconnect modeling and analysis. The implications of various nanoscale effects on VLSI interconnect performance, reliability, power dissipation and parasitic extraction are also presented. Promising new technologies including 3 D ICs and carbon nanotube (CNT) interconnects are outlined which have the potential to meet these interconnect challenges in the nanometer era. The second part of the tutorial will cover modeling abstractions suitable for communication centric designs, analysis techniques for estimating bus communication traffic, and synthesis of current protocols and standards such as OCP IP, VSIA, and AMBA. The third part of the tutorial will cover the use of advanced architectural concepts in bus based communication architecture design, and will include design examples from the industry. Finally, the last part of the tutorial will introduce the basic concepts on networks on chip and the challenges involved in the deployment of this on chip communication paradigm.
author_names: Nikil D Dutt

Kaustav Banerjee

Luca Benini

Kanishka Lahiri

Sudeep Pasricha
title: Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends
venue: 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
year: 2007