Query: An HVD based error detection and correction of soft errors in semiconductor memories used for space application

Candidate papers:

abstract: Exposure to electromagnetic radiations (high speed a ray particles) is a prominent problem in all the semiconductor memories of on board computing unit used for space application. So, in this paper, an error detection and correction method to protect the semiconductor memories against the soft errors is proposed. This method is based on 2 d parities. The parity bits are calculated at the receiver end for each row, column and diagonal in slash and backslash directions in a memory array. The parities are regenerated at the receiver end; the comparison of transmitted and received parity bits detects the error. As soon as the error is detected, the code corrects the detected error. Hamming code is used for error detection and correction. It uses parity codes in each of the four directions (that are horizontal, vertical, forward slash diagonal and backslash diagonal) in a data part. Correction code can correct an error in each row, column, and forward slash diagonal and back slash diagonal. This method is implemented on an FPGA device and it is evaluated for an on chip RAM of a Virtex device. This method is a promising technique to detect and correct errors in semiconductor memories in presence of large electromagnetic interference and hazards with less computational complexity.
author_names: Sudhakar Sharma

Prashanth Vijayakumar
title: An HVD based error detection and correction of soft errors in semiconductor memories used for space applications
venue: 2012 International Conference on Devices, Circuits and Systems (ICDCS)
year: 2012

abstract: With the increase of data transmission and hence sources of noise and interference, engineers have been struggling with the demand for more efficient and reliable techniques for detecting and correcting errors in received data. Although several techniques and approaches have been proposed and applied in the last decade, data reliability in transmission is still a problem. In this report propose a high efficient combined error detection and correction technique based on the horizontal vertical diagonal (HVD) parity check in HDLC. This method has been experimentally implemented and simulated using Field Programmable Gate Array .Simulation results show that the proposed technique detects 99.99% of the errors and corrects as predicted up to three bits of errors in the received impaired n bit code. An independent design platform is utilized for the simulation by Xilinx 8.1 using ModelSim SE EE 5.4a coded in VHDL which shows a significant reduction in uncorrected errors during data transmission. The efficient performance of HVD makes it a more applicable coding technique for communication, data transmission, different protocols and other application.
author_names: Shubham Fadnavis
title: An HVD Based Error Detection and Correction Code in HDLC Protocol Used for Communication
year: 2013

abstract: Data stored in memory or buffer needs Error Detection And Correction (EDAC) Errors occur due to supply voltage fluctuations and/or noise due to electromagnetic interference or external radiation. These errors could be either temporary or permanent. In this paper, a EDAC method is proposed to detect and correct errors based on 3D parity check. In the encoder, the data bits are arranged in a matrix format and then parity bits are calculated for each row, column and diagonal. Errors present in parity bits are detected and corrected using Hamming code. Regeneration of data bits and Syndrome calculation at the decoder helps in detecting and correcting the error bits in the data. The 3D Parity check code can correct up to 3 bits of any combination of errors in the data and the Hamming code can correct up to 3 bits in the parity, if they occur in specific combinations. Thus, this method can detect and correct errors in both data and parity bits. This method achieves higher reliability by having a slight tradeoff in area and power consumption compared to other similar methods.
author_names: Shivani Tambatkar

Siddharth Narayana Menon

Vijayalakshmi S Sudarshan

M Vinodhini

N S Murty
title: Error detection and correction in semiconductor memories using 3D parity check code with hamming code
venue: 2017 International Conference on Communication and Signal Processing (ICCSP)
year: 2017

abstract: Constant shrinkage in the device dimensions by scaling of CMOS technology to nano scale level has resulted in very dense high speed memory cells, also resulting in increase of fault occurrence in the memory. Soft errors and Multiple Cell Upsets (MCUs) are becoming a major reliability issues in memory exposed to extraordinary conditions like radiation and ionization. Thus we need some method for fault tolerant memory cells. Conventional Error Correcting Codes (ECC) cannot correct multiple errors in memories even though many of these are capable of detecting multiple errors. The existing Decimal Matrix Code (DMC) based method for memory protection require more redundant bits to maintain higher reliability of memory. This paper presents a novel Parity Matrix Code (PMC) based encoding and decoding method to assure reliability in presence of multiple bit flip. PMC reduces number of redundant bit and it corrects more errors compared to existing system. The existing DMC and proposed PMC is compared to well known codes such as Hamming Codes, Matrix Code and Punctured Difference Set Code in terms of area used, delay and power resulting in proving minimal overhead for proposed PMC. Keywords Soft Errors, Multiple Cell Upsets (MCUs) Error Correction Codes, Error Detection and Correction (EDAC) Decimal Matrix Code (DMC) Parity Matrix Code (PMC)
author_names: Neha Ibrahim

Sunil Jacob
title: A Novel Methodology for Detection and Correction of Errors in Memory using Parity Matrix Code (PMC)
year: 2015

abstract: Data that is either transmitted over communication channel (e.g. bus) or stored in memory is not completely error free. RAM memory cell contents can change spuriously due to some electromagnetic interference. In magnetic storage devices such as disks, magnetic flux density increases could cause one or more bits to flip (change that value) Exposure to high speed a ray particles is a prominent problem in all the semiconductor memories used for various communication applications. So, in this paper, an error detection and correction method to protect the RAM against the errors is proposed. This method is based on 2 d parities. The parity bits are calculated at the transmitter end for each row, column and diagonal in slash and backslash directions in a memory array. The parities are regenerated at the receiver end. The comparison of transmitted and received parity bits detects the error. As soon as the error is detected, the code corrects the detected error. This method is a promising technique to detect and correct errors in semiconductor memories in presence of large electromagnetic interference with less computational complexity.
author_names: Narinder Singh

Sukhjit Singh

Vikrant Sharma

Amandeep Singh Sehmby
title: RAM ERROR DETECTION CORRECTION USING HVD IMPLEMENTATION
year: 2013

abstract: This paper proposes a novel approach to detect and correct multi bit upsets using horizontal vertical diagonal shift (HVDS) parity. Many of the errors occur when information is transmitted from one node to another node. Detection and correction of these errors is a must for many systems e.g. safety critical systems. Existing work on error detection and correction cover up to three bit errors (as far reviewed) in a data word. The proposed method can detect and correct up to 7 bit errors. Experimental studies show the effectiveness of the proposed method in comparison to existing dominant work.
author_names: Muhammad Sheikh Sadi

Muhammed Saifur Rahman

K M Imrul Kayes Sikdar
title: Error detection correction using horizontal vertical diagonal shift method
venue: 2014 International Conference on Electrical Engineering and Information Communication Technology
year: 2014

abstract: This senate proposes an optimize version of the Hamming codes for Error detection and correction (EDAC) used in the HDLC protocol as HDLC being the most enduring and fundamental standard in communication. When data is either stored in memory or transmitted through a communication channel it is not errorless. With the exposure to electromagnetic radiation the semiconductor memory which are used in various applications get damaged .Because of electromagnetic interference the contents of the RAM memory cells get affected which leads to the bit flip in the magnetic storage devices like floppy disk, magnetic tape and hard disk devices etc. A proposed method has been developed to overcome the existing problems by using Xilinx ISE 13.2 simulator tool through which number of bit errors detection and correction can be increased in 8x8 matrix .It will result into enhancement of code rate and reduction of bit overhead.
author_names: Varinder Pal Singh

Narinder Sharma
title: Improving Performance Parameters of Error Detection and Correction in HDLC Protocol by using Hamming Method
year: 2015

abstract: Soft errors hamper reliability of modern electronic circuits. In critical application areas, demand of safety against soft errors is increasing. Several methods have been developed to provide such error free environment in modern systems. The use of Golay code, and BCH codes are some of the top most widely used techniques. Nonetheless, still no methods have claimed that it has 100% correction rate. In this paper, a new Successive Parity Generation (SPG) based approach is proposed to tolerate such soft errors. After occurrence of bit errors in data, the proposed method corrects all the bit errors completely. It calculates parity at receiver end and successively detects errors and correct the erroneous data by comparing sender and receiver parity bits. The proposed method can detect and correct 100% error for any size of codeword with a moderate overhead. Experimental studies show that it outperforms existing methods with respect to error correction rate, time and information overhead.
author_names: Shaikh Akib Shahriyar

Md Asaf-Uddowla Golap

Muhammad Sheikh Sadi
title: An Efficient Error Correction Approach by using Successive Parity Generation
venue: 2018 4th International Conference on Electrical Engineering and Information Communication Technology (iCEEiCT)
year: 2018

abstract: Soft error tolerance is a matter of concern for system reliability nowadays. The likelihood of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. As the memory bit cell area is condensed, single event upset that would have formerly despoiled only a single bit cell are now proficient of upsetting multiple contiguous memory bit cells per particle strike. While these error types are beyond the error handling capabilities of the frequently used error correction codes (ECCs) for single bit, the overhead associated with moving to more sophisticated codes for multi bit errors is considered to be too costly. To address this issue, this paper presents a new approach to detect and correct multi bit soft error by using Horizontal Vertical Diagonal Blocks (HVDB) parity bits with a higher reliability.
author_names: Md Shamimur Rahman

Sakib Ahammed

Muhammad Sheikh Sadi
title: Soft error tolerance using horizontal vertical diagonal blocks
venue: 2015 2nd International Conference on Electrical Information and Communication Technologies (EICT)
year: 2015

abstract: The likelihood of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. As the memory bit cell area is condensed, single event upset that would have formerly despoiled only a single bit cell are now proficient of upsetting multiple contiguous memory bit cells per particle strike. While these error types are beyond the error handling capabilities of the frequently used error correction codes (ECCs) for single bit, the overhead associated with moving to more sophisticated codes for multi bit errors is considered to be too costly. To address this issue, this paper presents a new approach to detect and correct multi bit soft error by using Horizontal Vertical Double Bit Diagonal (HVDD) parity bits with a comparatively low overhead.
author_names: Md Shamimur Rahman

Muhammad Sheikh Sadi

Sakib Ahammed

Jan Jurjens
title: Soft error tolerance using Horizontal Vertical Double Bit Diagonal parity method
venue: 2015 International Conference on Electrical Engineering and Information Communication Technology (ICEEICT)
year: 2015