Query: Proposal of a spin torque Majority gate logic

Candidate papers:

abstract: A spin based logic device is proposed. It is comprised of a common free ferromagnetic layer and four discrete ferromagnetic nanopillars, each containing an independent fixed layer. It has the functionality of a majority gate and is switched via motion of domain walls by spin transfer torque. Validity of its logic operation and a quantitative performance prediction are demonstrated by micromagnetic simulation. It is entirely compatible with complimentary metal oxide semiconductor technology.
author_names: Dmitri E Nikonov

George Bourianoff

Tahir Ghani
title: Proposal of a Spin Torque Majority Gate Logic
venue: IEEE Electron Device Letters
year: 2011

abstract: A novel scheme for non volatile digital computation is proposed using spin transfer torque (STT) and automotion of magnetic domain walls (DWs) The basic computing element is composed of a lateral spin valve (SV) with two ferromagnetic (FM) wires served as interconnects, where DW automotion is used to propagate the information from one device to another. The non reciprocity of both device and interconnect is realized by sizing different contact areas at the input and the output as well as enhancing the local damping mechanism. The proposed logic is suitable for scaling due to a high energy barrier provided by a long FM wire. Compared to the scheme based on non local spin valves (NLSVs) in the previous proposal, the devices can be operated at lower current density due to utilizing all injected spins for local magnetization reversals, and thus improve both energy efficiency and resistance to electromigration. This device concept is justified by simulating a buffer, an inverter, and a 3 input majority gate with comprehensive numerical simulations, including spin transport through the FM/non magnetic (NM) interfaces as well as the NM channel and stochastic magnetization dynamics inside FM wires. In addition to digital computing, the proposed framework can also be used as a transducer between DWs and spin currents for higher wiring flexibility in the interconnect network.
author_names: Sou-Chi Chang

Sasikanth Manipatruni

Dmitri E Nikonov

Ian A Young

Azad Naeemi
title: Low power Spin Valve Logic using Spin transfer Torque with Automotion of Domain Walls
venue: ArXiv
year: 2016

abstract: devices find their main application in non volatile memories, namely magnetic random access memory (MRAM) Recently, magnetic memory based on switching by injection of spin polarized current, spin transfer torque RAM (STTRAM) [1] proved to be many times more efficient than previous types of MRAM. It is natural to extend the physics of spintronics to logic devices [2] The expected benefits are reconfigurable and non volatile logic, which does not suffer from standby power dissipation and can be turned on instantly. In spite of numerous spintronic logic devices proposed, few of them have been fabricated and none were demonstrated to function in an integrated circuit. A spin logic device, a spin torque majority gate (STMG) has been proposed [3,4] which leverages well developed processes and materials used in STTRAM. In the present work we reveal the character of magnetization dynamics in switching of this device, describe the operation of a practically important circuit, a one bit of a full adder, and obtain performance projections for it. These results support feasibility of experimental implementation of STMG, demonstrate the possibility of creating extended spintronic circuits (e.g. adders) without the need of spin to electrical conversion, and provide an argument that such circuits can have performance comparable with the incumbent CMOS technology. Fig 1. Layout of STMG. Input nanopillars are "A" "B" and "C" output pillar is "Out" in the middle. Minimum width is
author_names: Dmitri E Nikonov

George Bourianoff

Tahir Ghani

Ian A Young
title: Nanomagnetic Logic and Magnetization Switching Dynamics in Spin Torque Majority Gates
year: 2012

abstract: In recent years, spin orbit torques induced by charge current in heavy metal/magnetic structures have attracted wide attention among researchers. Since the experimental demonstration of spin orbit torques due to the spin Hall effect (SHE) being able to manipulate the magnetization direction in an in plane MTJ structure[1] it has been heavily explored for applications in memory and logic. It provides a potential low power alternative to other techniques such as spin transfer torque or electric field control for magnetization reversal. Recently, it has been shown that the spin Hall effect can provide a clocking mechanism for logic applications where the spin Hall effect is used to change the magnetization of a perpendicularly magnetized device along the hard axis (in the plane of the film)[2] In [2] a series of three nanomagets are spaced closely together so they interact through dipole interactions. Each nanomagnet serves as a logic bit. An additional nearby magnet is used as the input. However, due to the dipole interactions, only logic states of 101 or 010 can be obtained. For logic applications, it would be beneficial to be able to individually control the states of the individual bits to obtain a full range of logic functions.
author_names: A K Smith

Mahdi Jamali

Daniel Hickox-Young

Z Zhao

Jing Wang
title: Design and fabrication of nanomagnetic majority logic gate based on spin hall assisted switching
venue: 2015 IEEE Magnetics Conference (INTERMAG)
year: 2015

abstract: Spin torque majority gate (STMG) is one of the promising options for beyond complementary metal oxide semiconductor logic. Improvement of its performance switching speed vs. required current is critical for its competitiveness. In this paper, (a) we identify an optimized layout of the gate comprised of thin magnetic wires with in plane magnetization; (b) we optimize geometries of perpendicular magnetization spin torque majority gates. Micromagnetic simulations demonstrate an improvement in switching current for in plane magnetization (with less than 1 ns switching time) from 6 mA in the original scheme to 1.5 mA in the present one. Additionally, failures of switching caused by vortex formation are eliminated and desired output magnetization is achieved. Various geometries of STMG with perpendicular magnetization are explored. The scheme with a straight cross proves to be the most advantageous. It is predicted to operate with the switching current of 50 mA and less than 4 ns switching time.
author_names: Dmitri E Nikonov

Sasikanth Manipatruni

Ian A Young
title: Switching efficiency improvement in spin torque majority gates
year: 2014

abstract: As scaling CMOS devices is approaching its fundamental limits, a new direction of research has emerged to study beyond CMOS spintronic devices that use electronic spin as their state variable, offering new and enhanced functionalities. Due to low operating voltage, non volatility, and efficient implementation of majority gate, a novel spin based device, all spin logic (ASL) has been widely studied for applications including interconnects [1] pattern recognition systems [2] and Boolean gates [3] However, ASL relies on a non local spin valve (NLSV) structure with the connection to ground being close to the input magnet to ensure non reciprocity. Thus, a large fraction of injected spins is shunted to ground without ever reaching the output magnet. In addition, supply clocking is envisioned to reduce energy dissipation [3] Even then, a 32 bit addition by ASL compared to that by CMOS, requires 5 orders of magnitude more energy. In this paper, we propose a novel device that uses voltage controlled strain mediated magnetization switching [4] and spin transfer torque (STT) to perform the first and second 900 of switching, respectively. The STT is created in a conventional spin valve instead of the NLSV structure used in ASL. Hence, the wasteful shunt path to ground is eliminated. Non reciprocity is ensured through a clocking scheme in which the input and output magnets are oriented along the stable easy axis and the meta stable saddle point of energy profile, respectively. It has been shown that the deterministic switching of a magnet from a saddle point is more efficient in terms of delay and energy and affected less by thermal noise [5] [6] The device can be cascaded in a domino logic scheme, Fig. 1 a, by performing the first 900 switching for all cascaded logic gates simultaneously; therefore, the overall delay of a more complicated circuit like a 32 bit adder significantly improves.
author_names: Rouhollah Mousavi Iraei

Sourav Dutta

Sasikanth Manipatruni

Dmitri E Nikonov

Ian A Young

John T Heron

Azad Naeemi
title: A proposal for a magnetostriction assisted all spin logic device
venue: 2017 75th Annual Device Research Conference (DRC)
year: 2017

abstract: Spin torque majority gate (STMG) is one of the promising options for beyond complementary metal oxide semiconductor non volatile logic circuits for normally off computing. Modeling of prior schemes demonstrated logic completeness using majority operation and nonlinear transfer characteristics. However significant problems arose with cascade ability and input output isolation manifesting as domain walls (DWs) stopping, reflecting off ends of wires or propagating back to the inputs. We introduce a new scheme to enable cascade ability and isolation based on (a) in plane DW automotion in interconnects, (b) exchange coupling of magnetization between two FM layers, and (c) 'round about' topology for the majority gate. We performed micro magnetic simulations that demonstrate switching operation of this STMG scheme. These circuits were verified to enable isolation of inputs from output signals and to be cascade able without limitations.
author_names: Dmitri E Nikonov

Sasikanth Manipatruni

Ian A Young
title: Cascade able spin torque logic gates with input output isolation
year: 2015

abstract: A new digital device scheme based on the magnetoelectric coupling and automotion of the magnetic domain wall is proposed. A single device is composed of a ferromagnetic wire and two ferroelectric capacitors served as the input and the output. It is shown that with the initialization in the magnetic states, a single device and the corresponding majority gate can realize the NOT, NAND, and NOR functions. Furthermore, the device has the cascadability, input output isolation, gain, and nonreciprocity. The device concepts are justified by the numerical calculation, including the Landau Lifshitz Gilbert equation for the magnetization dynamics, the Landau Khalatnikov equation for the electric polarization dynamics, and the electrostatic equations for the open circuit output voltage and the charge sharing process between devices. The energy dissipation is also quantified and shown to be two to three orders of magnitude less than that in spin torque driven devices.
author_names: Sou-Chi Chang

Sasikanth Manipatruni

Dmitri E Nikonov

Ian A Young
title: Clocked Domain Wall Logic Using Magnetoelectric Effects
venue: IEEE Journal on Exploratory Solid State Computational Devices and Circuits
year: 2016

abstract: Spin based devices, in which information is carried via electron spin rather than electron charge, are potential candidates to complement CMOS technology due to the promise of non volatility and compact implementation of logic gates. One class of such devices is all spin logic (ASL) which is based on switching ferromagnets by spin transfer torque and conduction of spin polarized current. Using previously developed physics based circuit models for ASL, we develop a complete logic family for static ASL comprising of majority logic gates. We compare its performance metrics by means of circuit simulations using our Verilog A compact models. We also show the novel implementations of sequencing elements (e.g. latch and D flip flop) to enable clocked ASL. We also refine the models for ferromagnets to include spin relaxation inside ferromagnetic metals (FMs)
author_names: Vehbi Calayir

Dmitri E Nikonov

Sasikanth Manipatruni

Ian A Young
title: Static and Clocked Spintronic Circuit Design and Simulation With Performance Analysis Relative to CMOS
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2014

abstract: We discuss the application of a novel class of device, the magneto electric magnetic tunnel junction (ME MTJ) to realize a variety of computational functions, including majority logic and the XNOR/XOR gate. We also develop a compact model to describe the operation of these devices, which function by utilizing the phenomenon of 'voltage controlled magnetism' to switch the operational state of MTJs. The model breaks down the switching process into three key stages of operation: electrical to magnetic conversion, magnetization transfer, and final state readout. Estimates for the switching energy and delay of these devices, obtained from this compact model, reveal significant improvements in both of these parameters when compared to conventional MTJs switched by spin transfer torque. In fact, the capacity to use the ME MTJ to implement complex logical operations within a single device allows its energy costs to even approach those of low power CMOS. The added benefits of non volatility and compact circuit footprint, combined with their potential for heterogeneous integration with CMOS, make the ME devices of considerable interest for post CMOS technology.
author_names: Nishtha Sharma

Jonathan P Bird

Peter A Dowben

Andrew Marshall
title: Compact device model development for the energy delay analysis of magneto electric magnetic tunnel junction structures
year: 2016