Query: Analysis of on-state losses in pwm inverters

Candidate papers:

abstract: The authors present an analytical technique by which the on state losses in the devices in a PWM inverter may be calculated. The authors take the regular type of symmetrical double edge sinusoidal modulation, assume that the load current is sinusoidal, and show that the inherent Bessel Function solution can be reduced to a simple algebraic form when the frequency ratio is greater than about ten. It is assumed that the on state voltage drop across an active device and a free wheel diode is made up of a constant component plus a component that is linearly dependent upon current. The results are, therefore, applicable to most semiconductor devices. Experimental results are presented and are shown to be in good agreement with predictions.
author_names: Lalit K Mestha

P D Evans
title: Analysis of on state losses in PWM inverters
year: 1989

abstract: In this paper, a near state pulse width modulation (NSPWM) algorithm is proposed and implemented on dual two level voltage source inverters (D2L VSIs) in order to reduce the common mode voltage (CMV) the inverter switching losses, the current total harmonic distortion, and the side effects of bearing currents compared with space vector modulation (SVM) and PWM7. To gain these goals, two conventional two level inverters of the D2L VSI are controlled, separately, with specific switching sequences and an adjusted phase difference between the carriers of two inverters. For evaluating and comparing these PWM techniques mathematically, both CMV root mean square generated and switching losses of the D2L VSI are formulated as a function of the power factor of the D2L VSI, which is driven by the methods detailed in this study. Eventually, theories and analysis, as well as simulations and experimental results which are generated by MATLAB/Simulink environment and a 300 W scaled down D2LVSI prototype, respectively authenticate the superiority of the proposed NSPWM over both SVM and PWM7.
author_names: Amir Aghazadeh

Naser Khodabakhshi-Javinani

Hamed Nafisi

Masoud Davari

Edris Pouresmaeil
title: Adapted near state PWM for dual two level inverters in order to reduce common mode voltage and switching losses
venue: IET Power Electronics
year: 2019

abstract: Common mode voltage (CMV) problem brings severe negative effects in three phase voltage source inverters (VSIs) particularly for high frequency silicon (Si) carbide (SiC) VSIs. However, most traditional CMV reduction strategies, which are studied based on Si VSIs, are hard to be implemented and sacrifice the other performance of the VSIs. To overcome such drawbacks, this paper proposes a novel generalized tri state pulsewidth modulation (GTSPWM) for high frequency SiC VSIs over power factor of 0 1 and whole linear modulation index range. The working principle of conventional space vector based reduced CMV PWM (RCMV PWM) methods are reviewed, and their switching signals and CMV patterns are illustrated. The proposed GTSPWM method is described in a generalized scalar PWM approach for simple application and compared with other RCMV PWM methods. Mathematical analysis, simulations, and experimental results have been used to verify that GTSPWM based high frequency SiC VSIs can achieve minimum switching losses, improved output waveform quality, smaller dc link current ripples, and RCMV characteristics. Moreover, with the usage of GTSPWM method, the switching frequency of SiC VSIs can be further increased, and the performance of high frequency SiC VSIs could be improved appreciably.
author_names: Junzhong Xu

Jingwen Han

Yong Wang

Muhammad Umair Ali

Houjun Tang
title: High Frequency SiC Three Phase VSIs With Common Mode Voltage Reduction and Improved Performance Using Novel Tri State PWM Method
venue: IEEE Transactions on Power Electronics
year: 2019

abstract: Summary In this paper, a single phase quasi Z source (qZS) inverter (qZSI) integrating the pulse width modulation (PWM) control with interleaved and shifted shoot through state (STS) placement modulation technique, is proposed to simultaneously achieve both dc voltage boost and dc ac inversion. Instead of placing the STS in both inverter legs simultaneously, the addressed method inserts the STS only in left/right inverter leg separately during the positive/negative half cycle of the output voltage to reduce switching losses and thermal stresses of the power devices. The STS shift is also studied to decrease the switching numbers of power devices and thus can improve the efficiency further. Theoretical analysis and design guidelines of the studied inverter are included. Improvement in effectiveness and performance of the devised scheme and modulation strategy are proved experimentally and compared with the previous studies on a built laboratory prototype.
author_names: Shun Chung Wang

Yi-Hua Liu

Yu-Shan Cheng

Bo-Ruei Peng
title: A novel modulation technique with interleaved and shifted shoot through state placement for quasi Z source inverters
venue: Int. J. Circuit Theory Appl.
year: 2018

abstract: This paper discusses analysis and reduction of power losses in PV converter systems using conventional Si IGBTs as well as SiC MOSFETs. The PV converter system discussed in this paper consists of a boost converter and two half bridge PWM inverters, considering grid connection to three phase three wire low voltage power systems in Japan. Power losses in Si IGBTs and SiC MOSFETs are measured and theoretically discussed from experimental result in a buck converter benchmark. The power losses in PV converters using Si IGBTs and SiC MOSFETs are also measured and separated into the components in each part. As a result, it is clarified that the dominant power loss occurs in the two half bridge inverters, and their switching power losses are larger than the on state losses. Moreover, application of SiC MOSFETs to both boost converter and half bridge inverters makes it possible to improve the overall power conversion efficiency from 93.5% to 95.5% in the Euro eta definition.
author_names: Ryosuke Amma

Hideaki Fujita
title: Analysis and reduction of power losses in PV converters for grid connection to low voltage three phase three wire systems
venue: 2014 International Power Electronics Conference (IPEC Hiroshima 2014 ECCE ASIA)
year: 2014

abstract: This paper deals with a feasible power loss analysis simulator which can actually estimate the total power losses of three phase voltage source soft switching inverter as well as hard switching inverter. To estimate switching power losses and conduction power losses of switching semiconductor power devices IGBTs incorporated into the inverters and converters, this practical simulator is based on making use of feasible switching power loss data based table and conduction power loss table which are accumulated from the measured transient switching operation and periodic steady state conduction voltage and current operating waveforms of semiconductor switching power devices used in the power converters. The effectiveness of feasible simulation technique and power loss evaluations for power electronic conversion circuits and systems has been confirmed on the basis of simulation and experimental results under the conditions of soft switching and hard switching PWM schemes.
author_names: Eiji Hiraki

Mutsuo Nakaoka
title: Practical simulator development for power loss performance analysis of soft switching and hard switching PWM inverters using IGBTs
venue: IECON'01. 27th Annual Conference of the IEEE Industrial Electronics Society (Cat. No.37243)
year: 2001

abstract: This paper deals with a feasible power loss analysis simulator which can actually estimate the total power losses of three phase voltage source soft switching inverter as well as hard switching inverter. To estimate switching power losses and conduction power losses of switching semiconductor power devices IGBTs, incorporated into the inverters and converters this practical simulator is based on making use of feasible switching power loss data based table and conduction power loss table which are accumulated from the measured transient switching operation and periodic steady state conduction voltage and current operating waveforms of semiconductor switching power devices used in the power converters. The effectiveness of feasible simulation technique and power loss evaluations for power electronic conversion circuits and systems has been confirmed on the basis of simulation and experimental results under the conditions of soft switching and hard switching PWM schemes.
author_names: Eiji Hiraki

Mutsuo Nakaoka
title: Practical power loss analysis simulator of soft switching and hard switching PWM inverters and performance evaluations
venue: IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions
year: 2002

abstract: This paper deals with a feasible power loss analysis simulator which can actually estimate the total power losses of three phase voltage source soft switching inverter as well as hard switching inverter. To estimate switching power losses and conduction power losses of switching semiconductor power devices; IGBTs, incorporated into the inverters and converters, this practical simulator is based on making use of feasible switching power loss data based table and conduction power loss table which are accumulated from the measured transient switching operation and periodic steady state conduction voltage and current operating waveforms of semiconductor switching power devices used in the power converters. The effectiveness of feasible simulation technique and power loss evaluations for power electronic conversion circuits and systems has been confirmed on the basis of simulation and experimental results under the conditions of soft switching and hard switching PWM schemes.
author_names: Eiji Hiraki

Mutsuo Nakaoka

Toshikazu Horiuchi

Yoshitaka Sugawara
title: Practical power loss simulation analysis for soft switching and hard switching PWM inverters
venue: Proceedings of the Power Conversion Conference Osaka 2002 (Cat. No.02TH8579)
year: 2002

abstract: The series Z source network, an expansion of the popular concept of the Z source dc link, was originally proposed for boosting the output voltage of power electronic inverters. In this paper, that idea is extended on a three phase indirect matrix converter. The converter is based on the ultrasparse matrix topology characterized by the minimum number of semiconductor switches. The series Z source network is placed between the three switch input rectifier stage and the six switch output inverter stage in either the positive or the negative rail. A brief shoot through state produces the voltage boost. An optimal pulsewidth modulation (PWM) technique is developed for higher boosting capability of the converter and minimization of switching losses. A comparison is made between the matrix converters employing series and conventional cascade Z source networks. The inrush current and Z source capacitor's voltage are reduced in the series Z source matrix converter. Furthermore, the fast Fourier transform analysis of the output current of the converters suggests superiority of the series Z source matrix converter over the cascaded Z source matrix converter.
author_names: Ekrem Karaman

Mehdi Farasat

Andrzej M Trzynadlowski
title: A Comparative Study of Series and Cascaded Z Source Matrix Converters
venue: IEEE Transactions on Industrial Electronics
year: 2014

abstract: Reactive power handling by distributed power generation systems (DPGS) was prevented in the past in order to avoid additional power losses in the distribution feeders, however several new national grid codes request reactive power generation/absorption by the converters of active users. Actually almost no literature is focused on power losses analysis in case of reactive current circulation from the DPGS converter point of view. In the reactive power management, it has to be considered that the amount of the power losses varies on basis of the converter topology and the related modulation strategy. In this paper an accurate power losses evaluation is provided in case of two levels and three levels single phase PWM inverters in grid connected operation. The H Bridge converter and the Neutral Point Clamped (NPC) half bridge converter are compared. Reactive power handling feasibility is demonstrated up to low power factors (leading and lagging) involving a very limited increase of the power losses.
author_names: Francesco A Gervasio

Rosa Anna Mastromauro

Marco Liserre
title: Power losses analysis of two levels and three levels PWM inverters handling reactive power
venue: 2015 IEEE International Conference on Industrial Technology (ICIT)
year: 2015