Query: Gallium oxide metal oxide semiconductor field effect transistor

Candidate papers:

author_names: Neil A Moser
title: GALLIUM OXIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR ANALYTICAL MODELING AND POWER TRANSISTOR DESIGN TRADES
year: 2017

author_names: Higashiwaki Masataka

Sasaki Kohei

HoiWong Man

Kamimura Takafumi

Krishnamurthy Daivasigamani

Kuramata Akito

Masui Takekazu

Yamakoshi Shigenobu
title: Depletion mode gallium oxide metal oxide semiconductor field effect transistors fabricated by using Si ion implantation
year: 2014

abstract: High temperature performance of Ga2O3 metal oxide semiconductor field effect transistors (MOSFETs) was investigated at temperatures of 25 degC 300 degC. A 30.7% on state current reduction was observed when the temperature increased from 25 degC to 300 degC. On state current and peak intrinsic transconductance decreased when temperature increases and followed a power law, indicating that high temperature electron mobility is limited by phonon scattering. Threshold voltage also shift positively with an increase rate of ~2.3 mV degC 1 when the temperature increased. In terms of off state currents, traps with an activation energy of 0.42 eV were responsible for increased off state current at high temperature and high drain voltage regime.
author_names: Dian Lei

Kaizhen Han

Ying Wu

Zhihong Liu

Xiao Gong
title: Investigation on temperature dependent DC characteristics of gallium oxide metal oxide semiconductor field effect transistors from 25 degC to 300 degC
venue: Applied Physics Express
year: 2019

abstract: Lateral n channel enhancement mode GaN metal oxide semiconductor (MOS) field effect transistors and lateral capacitors have been fabricated on a p type epi GaN substrate semiconductor and electrically characterized at different temperatures. A clear positive behavior of the inversion channel mobility with temperature has been obtained. A physics based model on the inversion charge and charge trapped in interface states characteristics has been used to investigate the temperature dependence of the inversion MOS channel mobility. The field effect mobility increase with temperature is due to an increase in the inversion charge and a reduction in the trapped charge for a given voltage gate. Then, for larger gate bias and/or higher temperatures, surface roughness effects become relevant. The good fitting of the model with the experimental data leads us to consider that the high density of charged acceptor interface traps together with a large interface roughness modulates the channel mobility due to scattering.
author_names: Amador Perez-Tomas

Marcel Placidi

Xavier Perpina

Aurore Constant

Phillippe Godignon

Xavier Jorda

Pierre Brosselard

Jose Millan
title: GaN metal oxide semiconductor field effect transistor inversion channel mobility modeling
year: 2009

abstract: Completely vertical trench gate metal oxide semiconductor field effect transistors (MOSFETs) have been produced using gallium nitride (GaN) for the first time. These MOSFETs exhibited enhancement mode operation with a threshold voltage of 3.7 V and an on resistance of 9.3 mOcm2. The channel mobility was estimated to be 131 cm2/(Vs) when all the resistances except for that of the channel are considered. Such structures, which satisfy the key words "vertical" "trench gate" and "MOSFET" will enable us to fabricate practical GaN based power switching devices.
author_names: Hirotaka Otake

Kentaro Chikamatsu

Atsushi Yamaguchi

Tatsuya Fujishima

Hiroaki Ohta
title: Vertical GaN Based Trench Gate Metal Oxide Semiconductor Field Effect Transistors on GaN Bulk Substrates
year: 2008

abstract: High speed electronic devices rely on short carrier transport times, which are usually achieved by decreasing the channel length and/or increasing the carrier velocity. Ideally, the carriers enter into a ballistic transport regime in which they are not scattered. However, it is difficult to achieve ballistic transport in a solid state medium because the high electric fields used to increase the carrier velocity also increase scattering. Vacuum is an ideal medium for ballistic transport, but vacuum electronic devices commonly suffer from low emission currents and high operating voltages. Here, we report the fabrication of a low voltage field effect transistor with a vertical vacuum channel (channel length of ~20 nm) etched into a metal oxide semiconductor substrate. We measure a transconductance of 20 nS um( 1) an on/off ratio of 500 and a turn on gate voltage of 0.5 V under ambient conditions. Coulombic repulsion in the two dimensional electron system at the interface between the oxide and the metal or the semiconductor reduces the energy barrier to electron emission, leading to a high emission current density ~1 x 10(5) A cm( 2) under a bias of only 1 V. The emission of two dimensional electron systems into vacuum channels could enable a new class of low power, high speed transistors.
author_names: Siwapon Srisonphan

Yun Suk Jung

Hong Koo Kim
title: Metal oxide semiconductor field effect transistor with a vacuum channel.
venue: Nature nanotechnology
year: 2012

abstract: Transparent electronic devices formed on flexible substrates are expected to meet emerging technological demands where silicon based electronics cannot provide a solution. Examples of active flexible applications include paper displays and wearable computers. So far, mainly flexible devices based on hydrogenated amorphous silicon (a Si:H) and organic semiconductors have been investigated. However, the performance of these devices has been insufficient for use as transistors in practical computers and current driven organic light emitting diode displays. Fabricating high performance devices is challenging, owing to a trade off between processing temperature and device performance. Here, we propose to solve this problem by using a novel semiconducting material namely, a transparent amorphous oxide semiconductor from the In Ga Zn O system (a IGZO) for the active channel in transparent thin film transistors (TTFTs) The a IGZO is deposited on polyethylene terephthalate at room temperature and exhibits Hall effect mobilities exceeding 10 cm2 V 1 s 1, which is an order of magnitude larger than for hydrogenated amorphous silicon. TTFTs fabricated on polyethylene terephthalate sheets exhibit saturation mobilities of 6 9 cm2 V 1 s 1, and device characteristics are stable during repetitive bending of the TTFT sheet.
author_names: Kenji Nomura

Hiromichi Ohta

Akihiro Takagi

Toshio Kamiya

Masahiro Hirano

Hideo Hosono
title: Room temperature fabrication of transparent flexible thin film transistors using amorphous oxide semiconductors
venue: Nature
year: 2004

abstract: Research efforts on achieving low interfacial density of states (Dit) as well as low electrical leakage currents on GaAs based III V compound semiconductors are reviewed. Emphasis is placed on ultra high vacuum (UHV) deposited Ga2O3(Gd2O3) and atomic layer deposition (ALD) Al2O3 on GaAs and InGaAs. Ga2O3(Gd2O3) the novel oxide, which was electron beam evaporated from a gallium gadolinium garnet target, has, for the first time, unpinned the Fermi level of the oxide/GaAs heterostructures. Interfacial chemical properties and band parameters of valence band offsets and conduction band offsets in the oxides/III V heterostructures are studied and determined using X ray photoelectron spectroscopy and electrical leakage transport measurements. The mechanism of III V surface passivation is discussed. The mechanism of Fermi level unpinning in ALD Al2O3ex situ deposited on InGaAs were studied and unveiled. Systematic heat treatments under various gases and temperatures were studied to achieve low leakage currents of 10 8 10 9 A/cm2 and low Dit's in the range of (4 9)x1010 cm 2 eV 1 for Ga2O3(Gd2O3) on InGaAs. By removing moisture from the oxide, thermodynamic stability of the Ga2O3(Gd2O3)/GaAs heterostructures was achieved with high temperature annealing, which is needed for fabricating inversion channel metal oxide semiconductor filed effect transistors (MOSFET's) The oxide remains amorphous and the interface remains intact with atomic smoothness and sharpness. Device performances of inversion channel and depletion mode III V MOSFET's are reviewed, again with emphasis on the devices using Ga2O3(Gd2O3) as the gate dielectric.
author_names: Minghwei Hong

Jueinai Kwo

P Tsai

Y C Chang

M L Huang

Chih-Ping Chen

Tsung-Da Lin
title: III V Metal Oxide Semiconductor Field Effect Transistors with High k Dielectrics
year: 2007

abstract: The dc characteristics, such as on resistances (Ron) and threshold voltages (Vth) of gallium nitride based metal oxide semiconductor field effect transistors with vertical trench gates have been theoretically derived. The optimized acceptor density and the thickness of p type layers for n channels (channel length) were estimated to be 3x1017cm 3 and 0.5mm, respectively, in order to realize Ron in the sub mOcm2 range. On the other hand, this resulted in a high Vth of 18V due to the wide bandgap. To achieve low Ron and moderate Vth less than 10V simultaneously, the insertion of an additional p type or n type layer with finite thickness between the gate insulator and the p type layer was suggested.
author_names: Tatsuya Fujishima

Hirotaka Otake

Hiroaki Ohta
title: Reduction in threshold voltages in GaN based metal oxide semiconductor field effect transistors
year: 2008

abstract: Silicon nanowires can be prepared with single crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm2/V*s with peak values of 2000 nS and 1350 cm2/V*s, respectively. The comparison of these results and other key parameters with state of the art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.
author_names: Yi Cui

Zhaohui Zhong

Deli Wang

Wayne U Wang

Charles M Lieber
title: High Performance Silicon Nanowire Field Effect Transistors
year: 2003