Query: Tunnel field-effect transistors as energyefficient electronic switches

Candidate papers:

abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum mechanical band to band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100 fold power reduction over complementary metal oxide semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low power integrated circuits.
author_names: Adrian M Ionescu

Heike E Riel
title: Tunnel field effect transistors as energy efficient electronic switches
venue: Nature
year: 2011

abstract: Conventional field effect transistors (FETs) have long been considered a fundamental electronic component for a diverse range of devices. However, nanoelectronic circuits based on FETs are not energy efficient because they require a large supply voltage for switching applications. To reduce the supply voltage in standard FETs, which is hampered by the 60 mV/decade limit established by the subthreshold swing (SS) a new class of FETs have been designed, tunnel FETs (TFETs) A TFET utilizes charge carrier transportation in device channels using quantum mechanical based band to band tunneling despite of conventional thermal injection. The TFETs fabricated with thin semiconducting film or nanowires can attain a 100 fold power drop compared to complementary metal oxide semiconductor (CMOS) transistors. As a result, the use of TFETs and CMOS technology together could ameliorate integrated circuits for low power devices. The discovery of two dimensional (2D) materials with a diverse range of electronic properties has also opened new gateways for condensed matter physics, nanotechnology, and material science, thus potentially improving TFET based devices in terms of device design and performance. In this review, state of art TFET devices exhibiting different semiconducting channels and geometries are comprehensively reviewed followed by a brief discussion of the challenges that remain for the development of high performance devices. Lastly, future prospects are presented for the improvement of device design and the working efficiency of TFETs.
author_names: Ghazanfar Nazir

Adeela Rehman

Soo-Jin Park
title: Energy efficient tunneling field effect transistors for low power device applications: challenges and opportunities.
venue: ACS applied materials interfaces
year: 2020

abstract: The research field on tunnel FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band to band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non self consistent quantum models, where BTBT is computed with rigorous quantum mechanical models starting from frozen potential profiles and closed boundary Schrodinger equation problems. We will then address models that solve the open boundary Schrodinger equation problem, based either on the non equilibrium Green's function NEGF or on the quantum transmitting boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field.
author_names: David Esseni

Marco G Pala

Pierpaolo Palestri

Cem Alper

Tommaso Rollo
title: A review of selected topics in physics based modeling for tunnel field effect transistors
year: 2017

abstract: Graphene and molybdenum disulfide are two dimensional novel materials considered promising for nanoscale electronic devices. Due to high carrier mobility and in spite of lacking a bandgap, nanoscale graphene transistors have been demonstrated to reach a cut off frequency above 400 GHz. The absence of bandgap in graphene leads to a remarkable band to band tunneling property in electron devices with negative differential resistance. Ultra thin field effect transistors fabricated with graphene as gate conducting channels have been shown experimentally to exhibit negative differential resistance (NDR) with widespread appeal for both digital and analog electronics. NDR devices like the Esaki p n junction have been known to have applications for high frequency oscillators, fast logic switches, memories and low power amplifiers. In this work, a semi analytical model equation for transfer characteristics of graphene transistors is developed to successfully model the NDR. Data from three known experimental devices exhibiting NDR with gate length from 500 nm to 3 mm are shown to match well with theoretical modeled results. Numerical calculations using the model equation show that at a fixed gate bias, NDR can be modulated by tuning the value of contact resistance. The result also shows that separate onset of NDR in purely electron current or hole current can be modeled with this equation and matches experimental data.
author_names: Phuoc X Tran
title: Modulation of Negative Differential Resistance in Graphene Field Effect Transistors by Tuning the Contact Resistances
venue: Journal of Electronic Materials
year: 2018

abstract: Germanane (GeH) a hydrogenated germanium monolayer, is a new family of 2 D semiconductors, exhibiting promising potential for electronic device applications. Here, we investigate GeH Schottky barrier (SB) field effect transistors (FETs) using atomistic quantum transport simulations. Our simulation results reveal that the ohmic contact device with zero SB height <inline formula> <tex math notation="LaTeX"\Phi _{\text {Bn} /tex math>/inline formula> exhibits ~20% lower ON current than the metal oxide semiconductor (MOS) FET counterpart due to the inherent tunnel barrier at the metal semiconductor junction. We also compare 14 nm channel GeH and black phosphorus (BP) SBFETs with a finite SB height of <inline formula> <tex math notation="LaTeX"\Phi _{\text {Bn} 0.22$ /tex math>/inline formula> eV for both devices. Our results show that GeH outperforms BP in the ON state, but it can suffer from larger leakage current in the OFF state. We further investigate the effect of barrier height in GeH SBFET by varying <inline formula> <tex math notation="LaTeX"\Phi _{\text {Bn} /tex math>/inline formula> from 0 eV to a half bandgap (0.78 eV) In general, as barrier height increases, both ON current and the minimum leakage current are reduced. It is also observed that, with increasing SB height, intrinsic delay increases but the required energy per switching decreases, indicating the trade off between the device speed and the energy dissipation. Our benchmarking of GeH SBFET against GeH and BP MOSFETs demonstrates that GeH generally outperforms BP in terms of energy delay product (EDP) By performing careful engineering of SB height along with the device threshold voltage, we show that the minimum EDP of GeH SBFET can be as comparable as that of the MOSFET counterpart, suggesting great potential of GeH SBFETs for future switching device applications.
author_names: Yiju Zhao

Demin Yin

Youngki Yoon
title: Intrinsic Performance of Germanane Schottky Barrier Field Effect Transistors
venue: IEEE Transactions on Electron Devices
year: 2018

abstract: Abstract Reducing supply voltage is a promising way to address the power dissipation in nano electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal oxide semiconductor field effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF ratio in current integrated circuits. Tunnel field effect transistors (TFETs) benefit from steep switching characteristics due to the quantum mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III V compound semiconductor materials further improve the ON state current and reduce SS due to the low band gap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1 xAs/GaAsySb1 y heterostructures allow a wide range of band gap energies and various staggered band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the mixed As/Sb material system. In particular, this review introduces and summarizes the progress in the development and optimization of low power TFETs using mixed As/Sb based heterostructures including basic working principles, design considerations, material growth, interface engineering, material characterization, device fabrication, device performance investigation, band alignment determination, and high temperature reliability. A review of TFETs using mixed As/Sb based heterostructures shows superior structural properties and distinguished device performance, both of which indicate the mixed As/Sb staggered gap TFET as a promising option for high performance, low standby power, and energy efficient logic circuit application.
author_names: Yan Zhu

Mantu K Hudait
title: Low power tunnel field effect transistors using mixed As and Sb based heterostructures
year: 2013

abstract: As a layered, two dimensional material with high charge carrier mobility and photoresponsivity, exfoliated indium selenide (InSe) is being actively studied for a variety of optoelectronic applications. While significant effort has been devoted to characterizing the in plane electronic properties of InSe, charge transport in the out of plane direction has been underreported despite its importance in vertical field effect transistors, photodetectors, and related van der Waals heterostructure devices. Here, we fill this knowledge gap by performing variable temperature and variable thickness charge transport measurements in the out of plane direction for exfoliated InSe crystals. A vertical field effect transistor geometry is utilized with a bulk metal top contact and single layer graphene bottom contact such that electrostatic gating can be performed via the underlying Si substrate. In contrast to lateral InSe transistors, vertical InSe transistors show decreasing conductance at low temperatures, which is explained by the temperature dependence of tunneling and field emission currents. While thinner InSe crystals are dominated by Fowler Nordheim tunneling, thicker InSe crystals show increasing contribution from thermionic emission. In addition, the graphene/InSe barrier height can be modulated by the gate potential, resulting in vertical field effect transistor current switching ratios up to 104. Overall, this study provides fundamental insight into the out of plane electronic properties of exfoliated InSe, which will inform ongoing efforts to realize ultrathin InSe device applications.
author_names: Vinod K Sangwan

Junmo Kang

Mark C Hersam
title: Thickness dependent charge transport in exfoliated indium selenide vertical field effect transistors
year: 2019

abstract: In a recent paper, Biswas et al. demonstrated a onetransistor dynamic random access memory (1T DRAM) based on asymmetrical tunneling field effect transistor (TFET) with an underlapped front gate. The device operates in reverse bias between source and drain, with charge stored in the underlapped LIN region modifying the electric field at the source channel tunnel junction and leading to a modulation of the TFET current that distinguishes the "0" and "1" states. In this comment, we compare the mechanism and performance of the TFET 1T DRAM device of Biswas et al. with a different feedback based operation mode of the same physical device used for the same 1T DRAM application, which we have characterized in recent years. In our version of the device, which we called the Z FET (for zero subthreshold swing and zero impact ionization) the same asymmetrical structure is operated in forward bias, with front and back gates providing controllable injection barriers. The resulting performance appears significantly better in terms of operating current, current sensing margin, and speed. The two structures are compared in Fig. 1. Both the TFET DRAM and the Z FET DRAM (which comes in ptype and n type configurations) originate from the same asymmetrical TFET, in which only a part of the channel is covered by the front gate (LG) and the rest is uncovered (LIN) in order to reduce the ambipolar leakage current. 5 In both devices, the front and back gates are biased to form potential barriers in LG and LIN regions. However, in the TFET DRAM, there is reverse bias (VDS> 0) between drain and source, leading to the potential profile in Fig. 1(c) whereas in the Z FET, the drain source bias is forward (VDS< 0) leading to the potential profile in Fig. 1(d) for the p type Z FET. Other important differences are the charge location and the reading mechanism. In the TFET DRAM, the positive (hole) charge, stored within the potential well formed in the LIN region, is used to differentiate the memory states by modulating the VG controlled tunneling current. However, due to the LG region separating the stored charge and the tunneling junction (Pth body) the stored charge has a weak effect on the tunneling current, leading to the weak hysteresis in the IDVBG curves in Fig. 2(a) and a very small 20 nA) current difference between "1" and "0," as shown in Fig. 2(b) In the Z FET, the source drain junction is forward biased but the device stays in the off state under low jVDj due to the carrier injection barriers formed by the front and back gates. As the jVDj ramps up approaching to jVGj, the barrier on the drain side is lowered and this triggers a feedback process between the hole and electron flows, which turns on the Z FET abruptly. In the on state, the Z FET is essentially a forward biased diode showing high current in the mA range. Figure 2(c) shows the ID VD curves of Z FET with pronounced hysteresis controlled linearly by the front gate VG. For DRAM operation, the Z FET stores the positive charge directly under the front gate in LG region. These charges are read out using a fast VD pulse and the discharge current turns on Z FET abruptly through the feedback process. Figure 2(d) shows the Z FET 1T DRAM operation, in which the readout current of "1" state reaches 90 lA/lm and the device stays in the off state during the readout of "0," leading to a large sensing margin. At the same time, the operating voltages required for the Z FET 1T DRAM are considerably lower, see Fig. 2. The reason for this is the low TFET tunneling current, which requires large gate and drain source voltages of 4 V to achieve the low measured currents of Fig. 2(b) Conversely, in the Z FET, positive feedback collapses the injection barriers in the on state, leading to far higher current at lower operating voltage. The low TFET current is likely responsible for the slow access speeds of the device reported by Biswas et al. <500 Hz) whereas the Z FET 1T DRAM was experimentally measured to work at 500 MHz (limited by the available test equipment) and has <1 ns access speed in simulation. In case of the advent of TFETs replacing MOSFETs in CMOS technology as logic switches, the device of Biswas et al. would be the first TFET based memory concept. We note that if the TFET tunneling current were higher, due to sharper junctions or the use of a lower bandgap material in the channel, the operating voltage of the TFET 1T DRAM could conceivably fall below that of the Z FET DRAM, but for now the operating voltage comparison is clearly in the Z FET's favor (see Fig. 2) Other useful properties of the Z FET DRAM include the non destructive reading, thanks to the regeneration of the stored charge, and the relatively small stored charge needed to distinguish the "0" and "1" states due to amplification of discharge current for short pulses. In conclusion, we agree with Biswas et al. that the underlapped asymmetric TFET structure of Fig. 1 has interesting memory properties, but we believe the previously reported feedback based forward bias operation is superior Author to whom correspondence should be addressed. Electronic mail: jing.wan01@gmail.com
author_names: Jing Wan

Alexander Zaslavsky

Sorin Cristoloveanu
title: Comment on "Investigation of tunnel field effect transistors as a capacitor less memory cell" [Appl. Phys. Lett. 104, 092108 (2014)
year: 2015

abstract: The down scaling of regular MOSFETs has prompted a looming power emergency, in which static power utilization is ending up noticeably too high. Keeping in mind the end goal to enhance the vitality productivity of electronic circuits, little swing switches are intriguing contender to supplant or supplement the MOSFETs utilized today. TFETs, which are gated p i n diodes whose on current rises up out of band to band burrowing, are engaging new devices for low control applications due to their low off current and their potential for a little subthreshold swing. Aside from every one of these points of interest TFET experiences low ON current. So to enhance this low ON current many gate engineering structures have been proposed. This paper clarifies every one of the strategies which are utilized till now and furthermore clarifies device structure and execution assessment. Index Terms TFET (Tunnel Field Effect Transistor) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) ON
author_names: H R Bharathi
title: The Future Device Tunnel Field Effect Transistor A survey
year: 2017

abstract: The down scaling of regular MOSFETs has prompted a looming power emergency, in which static power utilization is ending up noticeably too high. Keeping in mind the end goal to enhance the vitality productivity of electronic circuits, little swing switches are intriguing contender to supplant or supplement the MOSFETs utilized today. TFETs, which are gated p i n diodes whose on current rises up out of band to band burrowing, are engaging new devices for low control applications due to their low off current and their potential for a little subthreshold swing. Aside from every one of these points of interest TFET experiences low ON current. So to enhance this low ON current many gate engineering structures have been proposed. This paper clarifies every one of the strategies which are utilized till now and furthermore clarifies device structure and execution assessment.
author_names: R Helen Ramya Bharathi

T Evangeline Santhia

P S Karthikeyan
title: Ultra low consumption device for future electronics tunnel field effect transistor A survey
venue: 2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)
year: 2017