Query: SiC MOSFET threshold-stability issues

Candidate papers:

abstract: Abstract This work provides additional insight into the threshold voltage instability effect generally observed, to varying degrees, in SiC MOSFETs, and discusses the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold voltage stability is affected primarily by active charge traps in the near interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence of the direct tunneling mechanism in response to changes in gate bias. Bias temperature stressing can induce additional active oxide traps that can then participate in this instability. This time dependence is not properly accounted for in the existing test methods for assessing high temperature gate bias (HTGB) effects.
author_names: Aivars J Lelis

Ronald Green

Daniel B Habersat
title: SiC MOSFET threshold stability issues
year: 2017

abstract: There are a number of potential reliability issues associated with SiC power MOSFETs, including threshold voltage stability, gate oxide reliability, body diode robustness, short circuit current robustness, and radiation effects. This work is primarily focused on threshold voltage stability and the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold voltage stability is affected primarily by active charge traps in the near interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct tunneling mechanism in response to changes in gate bias. This time dependence is not properly accounted for in the existing test methods for assessing high temperature gate bias (HTGB) effects, which allow temporary removal of bias during cool down and significant un biased delay (up to 96 hours) before the post stress measurements are performed. However, this delay, introduced to accommodate the practical constraints of industrial testing, renders this test practically meaningless due to the significant recovery that occurs in the charge states of the near interfacial oxide traps. This difficulty can be overcome by reapplying the gate bias for a brief period of time before measuring. Details of the nature of the near interfacial oxide traps will be discussed, including their activation energy. All this work will be presented within the context of standards development within JEDEC, and a new SiC power devices qualification working group.
author_names: Aivars J Lelis

Ronald Green

Daniel B Habersat
title: SiC MOSFET reliability and implications for qualification testing
venue: 2017 IEEE International Reliability Physics Symposium (IRPS)
year: 2017

abstract: We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 degC. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.
author_names: Kwang-won Lee

Young Ho Seo

Taeseop Lee

Kyeong Seok Park

Martin Domeij

Fredrik Allerstam

T Neyer
title: Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H SiC MOSFET
year: 2019

abstract: Abstract Silicon carbide power MOSFETs are used in numerous studies to improve the efficiency or the performance of power electronic converters. However, the gate oxide technology weakness is a main reliability issue of silicon carbide MOSFET transistors. The threshold voltage shift is a critical phenomenon that addresses the reliability of industrial power applications. It is important to have a better understanding of the phenomena implied in the gate threshold voltage shift. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide stress is studied and discussed in this paper. Complementary testing was performed with dynamic reliability and gate oxide characterizations, such as the charge pumping technique. The results obtained are used to add insight to the current discussion of SiC MOSFET robustness. Additionally test benches and measurement protocols established on 1.7 kV 45 mO are detailed, which will be useful for the next generation of SiC MOSFET.
author_names: Quentin Molin

Mehdi Kanoun

Christophe Raynaud

Herve Morel
title: Measurement and analysis of SiC MOSFET threshold voltage shift
venue: Microelectron. Reliab.
year: 2018

abstract: Despite the recent progress in SiC power MOSFET technology and its commercialization, the defective MOS interface still hampers the exploitation of the full potential of these devices. We present results using our high k gate stack technology that shows significantly reduced density of interface states (Dit) along with superior threshold voltage (VTH) stability for low voltage SiC power MOSFETs. The findings indicate virtually no VTH shift during static characterization as function of the starting gate voltage and its ramp. Furthermore, dynamic switching results show virtually no threshold voltage shift for $V_{GS,start} \gt 12$V.
author_names: Stephan Wirths

Yulieth Arango

Andrei Mihaila

Marco Bellini

Gianpaolo Romano

Giovanni Alfieri

Manuel Belanche

Lars Knoll

E Bianda

Elena Mengotti
title: Vertical Power SiC MOSFETs with High k Gate Dielectrics and Superior Threshold Voltage Stability
venue: 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)
year: 2020

abstract: The new era of power semiconductor devices is exploiting the high potential of wide bandgap device based high frequency power converters. The advanced capabilities of Silicon carbide (SiC) semiconductors allow the power converters to switch at higher switching frequencies with lower switching and conduction losses. Operation under higher switching frequencies can drastically reduce the output filter requirements in grid connected converters. At higher frequencies, an L type filter can sufficiently eliminate the switching frequency harmonics. This will reduce the size and cost of the filter, which eventually results in the optimised system cost. In this paper, the filter requirements of SiC based high frequency converters are investigated. Usage of LCL filters to remove high frequency harmonic will shift the resonance frequency to high frequency region, where these harmonics can create electromagnetic compatibility issues. In industries, passive damping is utilised for mitigating these oscillations. This will result in additional losses and compromise the advantages of SiC devices. Even though active damping can be utilised to eliminate resonance oscillations, the high bandwidth processors and measurement devices may increase the cost further. Simulation study is conducted on PSCAD/MATLAB and the experimental verification using Cree SiC devices verify the filter requirements, stability issues, and possible mitigating solutions for high frequency grid converters.
author_names: Blessy John

Arindam Ghosh

Firuz Zare
title: Investigation on filter requirements and stability effects of SiC MOSFET based high frequency grid connected converters
venue: The Journal of Engineering
year: 2019

abstract: 1,200 V and 1,700 V SiC power MOSFETs from multiple suppliers were subject to dc and pulsed current stress of the body diode. Three of the five suppliers of 1,200 V devices evaluated showed no significant bipolar degradation, but the other two supplier's devices showed varying degrees of degradation due this bipolar phenomenon. Electrical results of newly released 1,700 V devices from two suppliers showed significant degradation in the body diode and MOSFET I V characteristics following both dc and pulsed current stress of their body diodes. The electrical results presented in this work are consistent with basal plane dislocations (BPDs) that form stacking faults during forward conduction of the body diode. Significant drift in the body diode forward voltage and MOSFET on resistance indicates that a much higher BPD density may be present in 1,700 V devices in comparison to the more mature 1,200 V device offerings. The likely presence of BPDs can lead to significant reliability issues in some modern SiC power MOSFETs, and their distribution seems to vary across suppliers and among devices with the same rating and from the same supplier. These differences are likely due to variations in wafer and device processing among suppliers and within a given product line from a single supplier.
author_names: Ronald Green

Aivars J Lelis

Franklin L L Nouketcha
title: Effects of Pulsed and DC Body Diode Current Stress on the Stability of 1200 V SiC MOSFET I V Characteristics
year: 2019

abstract: Due to the breakneck switching speed, SiC mosfet is extremely sensitive to parasitics in the power device, circuit layout, and also measurement probe. It is not clear how the parasitics of measurement probes affect the transient stability of SiC mosfet, and it poses an unsolved challenge for the industrial field. This paper focuses to uncover the transient instability mechanism of SiC mosfet intruded by probes. Mathematical and circuit models of voltage and current probes are created, by considering the parasitics, input impedance, and bandwidth issues. To reveal the stability principles of SiC mosfet associated with probes, impedance oriented and heterogeneity synthesized models combining device with probes are proposed. Furthermore, an assessment methodology and root locus analysis are presented to demonstrate the transient stability schemes and the stable boundaries of SiC mosfet influenced by multiple factors, including probe parasitics, device parameters, gate resistances, and snubber circuits. Comparative experiments are presented to confirm the transient behaviors of SiC mosfet intruded by probe parasitics and regulated by control circuits. It is proven that, because of low bandwidth specifications, the large input capacitance of the voltage probe and coil inductance of the current probe degrade the transient stability of SiC mosfet. Due to the deteriorated stability margin of SiC mosfet intruded by the inserted parasitics of probes, instability may also be activated by using the small gate resistance. The snubber circuit is helpful to enhance the transient stability. Advanced probes with high bandwidth and high impedance are crucially needed for stable measurement of wide bandgap power devices like SiC mosfet.
author_names: Zheng Zeng

Xin Min Zhang

Frede Blaabjerg

Linjing Miao
title: Impedance Oriented Transient Instability Modeling of SiC mosfet Intruded by Measurement Probes
venue: IEEE Transactions on Power Electronics
year: 2020

abstract: Although the body diode of SiC MOSFET has excellent surge capability, the reliability issues about commercial SiC MOSFET under repetitive surge current stress of body diode haven't been studied thoroughly. In this work, repetitive surge current stress is applied to the body diode of commercial SiC trench MOSFET, and the surge tests are conducted under different gate biases and ambient temperatures. It is found that no bipolar degradation occurs in the body diode but degradation phenomena of gate oxide and package are observed in devices under tests (DUTs) At room temperature, the threshold voltage (VTH) related to gate oxide degradation degrades more seriously at a negative gate bias of 5V than at OV. At OV gate bias, gate oxide and package degenerate more severely at $125^\circ}{C} than at $25^\circ}{C} The evolution of on state resistance (R_{DSON} during the tests is influenced by the competitive mechanism between gate oxide degradation and package degradation. As a result, gate oxide degradation causes RDSON to reduce while package degradation makes RDSON rise. Meanwhile, the competitive mechanism is deeply influenced by the gate bias voltage and ambient temperature. The failure analysis shows that all DUTs fail with gate and source terminal shorted, which is mainly attributed to high junction temperature.
author_names: Zhenyu Wang

Yunjia Li

Xiaohua Sun

Ye Liu

Zhengyun Zhu

Na Ren

Qing Guo
title: Reliability Investigation on SiC Trench MOSFET under Repetitive Surge Current Stress of Body Diode
venue: 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)
year: 2020

abstract: An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture emission time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short term threshold variations during application relevant 50 kHz bipolar ac stress. In addition, the impact on circuit operation is discussed.
author_names: Katja Puschkarsky

Tibor Grasser

Thomas Aichinger

Wolfgang Gustin

Hans Reisinger
title: Review on SiC MOSFETs High Voltage Device Reliability Focusing on Threshold Voltage Instability
venue: IEEE Transactions on Electron Devices
year: 2019