Query: machine learning semiconductor polysilicon

Candidate papers:

abstract: As the micro electro mechanical machine (MEMS) industry is maturing, an increased array of product applications and devices are being introduced. As these devices are being developed new processes are required to control and attain the desired levels of polysilicon stress. In this work the relationship between polysilicon blanket residual stress and dopant concentration and anneal conditions are investigated. It was found that as the sheet resistance increased, the magnitude of the stress increased several orders of magnitude. Annealing the wafers for increased durations and multiple cycles lowered the level of stress observed while reducing the response to dopant concentration. The response was reduced by fifty percent for a time increase from 20 to 180 minutes. It is suggested that specific levels of stress are best attained with modifications to the dopant concentration for the required thermal cycles. The characterization performed allows for reduced learning cycles and cost in the development of new MEMS process flows to achieve first pass success for device specific requirements.
author_names: Jerzy Woloszyn
title: A method for controlling residual film stress in LPCVD polysilicon films for surface micromachined MEMS
venue: 2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530)
year: 2004

abstract: While spin qubits based on gate defined quantum dots have demonstrated very favorable properties for quantum computing, one remaining hurdle is the need to tune each of them into a good operating regime by adjusting the voltages applied to electrostatic gates. The automation of these tuning procedures is a necessary requirement for the operation of a quantum processor based on gate defined quantum dots, which is yet to be fully addressed. We present an algorithm for the automated fine tuning of quantum dots, and demonstrate its performance on a semiconductor singlet triplet qubit in GaAs. The algorithm employs a Kalman filter based on Bayesian statistics to estimate the gradients of the target parameters as function of gate voltages, thus learning the system response. The algorithm's design is focused on the reduction of the number of required measurements. We experimentally demonstrate the ability to change the operation regime of the qubit within 3 to 5 iterations, corresponding to 10 to 15 minutes of lab time.
author_names: Julian D Teske

Simon Sebastian Humpohl

Ren'e Otten

Patrick Bethke

Pascal Cerfontaine

Jonas Dedden

Arne Ludwig

Andreas Dirk Wieck

Hendrik Bluhm
title: A machine learning approach for automated fine tuning of semiconductor spin qubits
venue: Applied Physics Letters
year: 2019

abstract: Semiconductor manufacturers aim to fabricate defect free wafers in order to improve product quality, increase yields, and reduce costs. Typically, wafer defects form spatial patterns that provide useful information, helping to identify problems and faults during the fabrication process. Machine learning (ML) methods have been used to classify these defects in order to locate the root causes of failure. This paper proposes a novel deep structured ML approach as an extension of our previous randomized general regression network (RGRN) model, to identify and classify both single defect and mixed defect patterns. The principal motivation for this paper is that a shallow structured RGRN performs well on single pattern defects, achieving an accuracy of 99.8% but performs poorly when a wafer has mixed defect patterns. The proposed approach improves RGRN performance, particularly on mixed pattern defects, by incorporating a novel information gain (IG) based splitter as well as deep structured ML. A spatial filter is applied to remove random noise and reduce model bias during training. During the first detection stage, the splitter generates unique rules that are built using the IG theory and splits the defects data into single defect and mixed defect patterns. Single defect patterns are then classified by RGRN, whereas mixed defect patterns are fed into the deep structured ML model for further classification. This combination improves the ability of the proposed approach to classify diverse defect patterns and achieve a better overall performance. Our experimental results demonstrate that the proposed approach achieves an overall detection accuracy of 86.17% on a dataset that contains real data representing both single defect and mixed defect patterns, as commonly found in real manufacturing scenarios, outperforming existing ML based models.
author_names: Ghalia Tello

Omar Y Al-Jarrah

Paul Yoo

Yousof Al-Hammadi

Sami Hakam Muhaidat

Uihyoung Lee
title: Deep Structured Machine Learning Model for the Recognition of Mixed Defect Patterns in Semiconductor Fabrication Processes
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2018

abstract: Semiconductor cluster equipment adds an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric vacuum atmospheric cycle. Such highly automated tools present a complex scheduling challenge where process specific requirements are balanced against a need to achieve maximum wafer throughput in a fault tolerant manner. Software engineers typically build schedulers using a set of manually configured heuristics but this can be a labor intensive process where small changes to the cluster configuration or process requirements can require large changes to the scheduler. Our motivation for this work was to investigate whether a machine learning approach to complex cluster scheduling could be developed more efficiently and at a lower cost than existing methods.
author_names: Doug Suerich

Terry Young
title: Machine Learning for Optimized Scheduling in Complex Semiconductor Equipment
venue: 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
year: 2019

abstract: In this paper, we show the possibility of using Technology Computer Aided Design (TCAD) to assist machine learning for semiconductor device failure trouble shooting and device reverse engineering. When TCAD simulation models and parameters are properly chosen and calibrated, large number of devices with random defects and structural characteristics can be generated and simulated. The results can then be used to train machine learning algorithms to predict the defect and structural characteristics of a device with given electrical characteristics (such as IV's and CV's) 1D PIN diode with various layer thicknesses and doping concentrations are used in this study. It is showed that with less than 2000 training samples, by using simple linear regression, one can achieve good prediction of layer thickness and doping of a given IV curve.
author_names: Y S Bankapalli

Hiu Yung Wong
title: TCAD Augmented Machine Learning for Semiconductor Device Failure Troubleshooting and Reverse Engineering
venue: 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
year: 2019

abstract: Machine learning and big data analytics are the latest spotlights with all the glare of fame ranging from media coverage to booming start up companies to eye catching merges and acquisitions. On the contrary, the $336 billion industry of semiconductor was seen as an "old fashioned" business, with fading interests from the best and brightest among young graduates and engineers. This chapter argues that this does not have to be that way because many research problems and solutions as studied in the semiconductor industry are in fact closely related to these machine learning and big data problems. To illustrate this point, we discuss a number of practical but challenging problems arising from semiconductor manufacturing process in this chapter. We first show how machine learning techniques, especially those regression related problems, often under the "disguise" of optimization problems, have been used frequently (often with nontrivial modeling skills and mathematical sophistications) to solve the semiconductor problems. We discuss such examples as process variation modeling and VLSI chip testing. For some other types of semiconductor problems, such as manufacturing process monitoring and improvement, we show that some existing machine learning algorithms are not necessarily well positioned to solve them, and novel machine learning techniques involving temporal, structural, and hierarchical properties need to be further developed. In either scenario, we convey the message that machine learning and existing semiconductor industry researches are closely related, and researchers often contribute to and benefit from each other.
author_names: Jinjun Xiong

Yada Zhu

Jingrui He
title: Machine Learning for VLSI Chip Testing and Semiconductor Manufacturing Process Monitoring and Improvement
year: 2019

abstract: Abstract The progress of digitalization enables new potentials to supply chain management by available data as well as by analysis methods like machine learning. This paper focuses on the master production planning matching demand and supply for a midterm time horizon, in a volatile, diverse and capacity constrained environment. Therefore, a framework for measuring instability is outlined, a machine learning approach to predict instability is developed and applied using the CRISP DM methodology on real data of a semiconductor manufacturer. The evaluation and results foster the concept and the field of application, but request the next step of prescriptive instability minimization.
author_names: Tim Lauer

Sarah Legner

Michael Henke
title: Application of machine learning on plan instability in master production planning of a semiconductor supply chain
year: 2019

abstract: In this work, we present a unique approach of combining TCAD modelling and machine learning to detect the defect locations of a bridging defect in a single fin FinFET. The prediction of the defect location is guided by the predictive model consisting of Random Forest algorithm which is trained with the measureable electrical attributes from the I V. High accuracy in predicting the defect location is achieved by the proposed scheme which can further enhance the FA success rate, expediting the cycle of design to product.
author_names: C W Teo

Kain Lu Low

Vinod Narang

Aaron Voon-Yew Thean
title: TCAD Enabled Machine Learning Defect Prediction to Accelerate Advanced Semiconductor Device Failure Analysis
venue: 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
year: 2019

abstract: Reliable and robust process control solutions are pivotal in the era of advanced technology nodes where the stochastic effects dominate the pattern characteristics. The key ingredients ofthe modern process control solutions are huge amount of data and smart data analytics algorithms. The state of the art machine learning methods allow screening large amounts of data for statistically relevant, but so far unknown and unexpected correlations, hence providing new options for process optimizations.
author_names: Eugen Foca
title: Machine Learning Solutions for Process Control in Semiconductor Manufacturing
venue: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI TSA)
year: 2019

abstract: The stock market was affected by different variables, such as the overall economic situation, political events, Sino US relations and corporate operations. Therefore, if you want to get returns in the stock market, predicting the time series of financial markets in advance is the most important thing for analysts and investors. However, predicting the direction of the stock market need to access information from existing markets and past historical data. Under such complicated work and costs, it is always the most difficult and important issue to achieve accurate forecasting and reduce forecasting costs. In this paper, the backpropagation neural network is used as a research tool to analyze the historical data of Taiwan Semiconductor Manufacturing Company (hereinafter referred to as TSMC) during the sample period from 2014 to 2018. In this study, the standardized technical analysis indicators and the related variables of TSMC are taken as input variables, and the closing price of the next day is taken as the output variable to predict the closing price for TSMC of the next day. The empirical results confirm that this method does improve the forecast of stock price of TSMC.
author_names: Po-Chao Lan

Wei-Ling Kung

Yao-Lun Ou

Chun-Yueh Lin

Wen-Cheng Hu

Yi-Hsien Wang
title: Machine learning model with technical analysis for stock price prediction: Empirical study of Semiconductor Company in Taiwan
venue: 2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
year: 2019