Query: Uniformity improvement by integrated electrochemical-plating process for CMOS logic technologies

Candidate papers:

abstract: Abstract Reliability of metal interconnects and the integration of inspection and metrology with process tools are advancing rapidly to overcome obstacles in down stream production. A significant drawback associated with metal interconnects which has resulted from the recent trend is the difficulty in obtaining uniform electroplated layer thicknesses across the maximum lateral dimension of the CMOS logic wafer. The prime objective of this paper is, to root cause uniformity troubleshooting by the adoption of integrated diffuser in electrochemical plating (ECP) system optimizations. These are to quantify the best degree of uniformity and high resistivity to enhance an even current distribution on the wafer. The results show that uniformity of the deposited film has been improved significantly with 1.9% i.e. maximum deviation of the deposited film thickness is at about 1.9% of the average film thickness, while standard electroplating processes typically achieves uniformity at best within 5.5% Furthermore, the origin of "hot spots' that caused poor uniformity was identified and greatly overcome with the improved ECP system comprising an integrated diffuser design and process modifications in real troubleshooting of back end operation line (BEOL) of semiconductor foundry.
author_names: Yasmin Abdul Wahab

Anuar Fadzil

Norhayati Soin

Sharifah Fatmadiana

Zaira Zaman Chowdhury

Nor Aliya Hamizi

Omid Akbarzadeh Pivehzhani

Thennarasan Sabapathy

Y Al-Douri
title: Uniformity improvement by integrated electrochemical plating process for CMOS logic technologies
venue: Journal of Manufacturing Processes
year: 2019

abstract: The recent improvement of VLSI process technologies enables us to integrate a large number of transistors on one chip, and significantly improves the circuit performance. On the other hand, the methodology of VLSI design becomes more and more complex and some new problems, such as Design For Manufacturability (DFM) have arisen. Due to the very high costs associated with the manufacturability of sub micron integrated circuits, even a modest yield improvement can be extremely significant. In order to achieve the high yield, a standard cell layout synthesis considering the DFM is required since standard cells are the most basic elements of the cell based design methodology as described in Chapter 1. This chapter describes a comprehensive CMOS logic cell layout synthesis technique for yield optimization by minimizing the sensitivity to wiring faults due to spot defects. Spot defect is one of the main sources of electrical failure in VLSI integrated circuits. We modeled the sensitivity to wiring faults on intra cell routings with consideration to the spot defects size distribution and the end effect of critical areas. Critical area is defined as the area in which the center of a spot defect must fall to cause a fault. We comprehensively generate the minimumwidth layouts of CMOS logic cells and the exact optimal layouts are selected from all the possible minimum width layouts by using our model of the sensitivity to wiring faults as a cost metric. Although the critical area used for the sensitivity calculation is extracted from the original layout patterns, the feasibility of the proposed sensitivity model to the practical lithography system is discussed. Moreover, the adequacy of the proposed sensitivity to the other cost metrics such as the cell delay and the total intra cell wire length is demonstrated. The impact of the sensitivity reduction on the yield is also discussed in this chapter.
title: Yield Optimal Cell Layout Synthesis for CMOS Logic Cells
year: 2011

abstract: The realization of large area electronics with full integration of 1D thread like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread like fiber electronic devices can be achieved using a simple reel to reel process, which is strongly required for low cost and scalable manufacturing technology. Here, high performance reel processed complementary metal oxide semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical doped single walled carbon nanotube (SWCNT) transistors. With the introduction of selective n type doping and a nonrelief photochemical patterning process, p and n type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high performance and reliable thread like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p and n type SWCNT transistors exhibit field effect mobility of 4.03 and 2.15 cm2 V 1 s 1 respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V.
author_names: Jae Sang Heo

Taehoon Kim

Seok-Gyu Ban

Daesik Kim

Jun Ho Lee

Jesse S Jur

Myung-Gil Kim

Yong-Hoon Kim

Yongtaek Hong

Sung Kyu Park
title: Thread Like CMOS Logic Circuits Enabled by Reel Processed Single Walled Carbon Nanotube Transistors via Selective Doping.
venue: Advanced materials
year: 2017

abstract: This paper presents Common Mode Rejection Ratio's (CMRR) measurement results of a multichannel integrated circuit dedicated to the recording neurobiological signals and shows the design method that allows for CMRR improvement in multichannel architectures. A 64 channel Neuro Stimulation Recording chip named NRS64 is processed in CMOS 180nm technology. The measurements are followed by the detailed analysis of effects that may cause a CMRR deterioration. The simulation results of these effects are also presented and discussed. Additionally, the method improving the CMRR is presented that allows to increase both the CMRR and its uniformity from channel to channel. Furthermore, the design of a prototype multichannel integrated circuit is presented where proposed method was applied. The chip was designed in a 180nm CMOS process.
author_names: Piotr Kmon
title: CMRR improvement for multichannel integrated recording circuits processed in submicron technologies dedicated to neurobiology experiments
venue: 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)
year: 2014

abstract: IMPROVEMENT OF A PROPAGATION DELAY MODEL FOR CMOS DIGITAL LOGIC CIRCUITS by Rodger Lawrence Stamness Propagation delay models, for CMOS Digital Circuits, provide an initial design solution for Integrated Circuits. Resources, both monetary and manpower, constrain the design process, leading to the need for a more accurate entry point further along in the design cycle. By verifying an existing propagation delay method, and its resulting delay model, calibration for any given process technology can be achieved. Literature reviews and detailed analysis of each step in the model development allow for greater understanding of each contributing parameter, and ultimately, adjustments to the model calibration result in a more accurate analytical model. An existing model was verified and improved upon using TSMC 0.18um and IBM 0.13um SPICE decks, and the resulting improvements can be used to further assist individuals needing a method and model for deriving an initial circuit design solution for integrated circuits.
author_names: Rodger Lawrence Stamness
title: Improvement of a propagation delay model for CMOS digital logic circuits
year: 2010

abstract: Single photon avalanche diode (SPAD) detector arrays generally suffer from having a low fill factor, in which the photo sensitive area of each pixel is small compared to the overall area of the pixel. This paper describes the integration of different configurations of high efficiency diffractive optical microlens arrays onto a 32 x 32 SPAD array, fabricated using a 0.35 um CMOS technology process. The characterization of SPAD arrays with integrated microlens arrays is reported over the spectral range of 500 900 nm, and a range of f numbers from f/2 to f/22. We report an average concentration factor of 15 measured for the entire SPAD array with integrated microlens array. The integrated SPAD and microlens array demonstrated a very high uniformity in overall efficiency.
author_names: Giuseppe Intermite

Aongus Mccarthy

Ryan E Warburton

Ximing Ren

Federica A Villa

Rudi Lussana

Andrew J Waddie

Mohammad R Taghizadeh

Alberto Tosi

Franco Zappa

Gerald S Buller
title: Fill factor improvement of Si CMOS single photon avalanche diode detector arrays by integration of diffractive microlens arrays.
venue: Optics express
year: 2015

abstract: This paper presents performance evaluation of high k/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.
author_names: D -G Park

Kenneth J Stein

Klaus Schruefer

Y M Lee

J -P Han

Weicong Li

H X Yin

Christian Pacha

N Kim

M Ostermayr

Manfred Eller

S Kim

K Kim

S Han

Klaus von Arnim

Naim Moumen

Michael S Hatzistergos

T J Tang

Rainer Loesing

Xianfeng Chen

Daniel Jaeger

Haoren Zhuang

J Chen

W Yan

Thomas S Kanarsky

M Chowdhury

Jens Haetty

Dominic Schepis

Michael P Chudzik

V -Y Theon

Srikanth Samavedam

Vijay Narayanan

Melanie Sherony

Richard Lindsay

An Steegen

Rama Divakaruni

Mukesh Khare
title: High k/metal gate low power bulk technology Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
venue: 2009 International Symposium on VLSI Technology, Systems, and Applications
year: 2009

abstract: We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1 3] A full range of Vts is enabled on chip through a unique multi workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6 T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP) However, the technology platform is also designed to leverage EUV insertion for specific multi patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.
author_names: Shreesh Narasimha

Basanth Jagannathan

Atsushi Ogino

Daniel Jaeger

Brian Greene

C D Sheraw

Kai Zhao

Bala Haran

Unoh Kwon

A K M Mahalingam

B Kannan

Bradley Morganfeld

Jessica Dechene

Carl Radens

A Tessier

A Hassan

Haritez Narisetty

I Ahsan

Massud A Aminpur

Chul An

Michael V Aquilino

A S Arya

Rod Augur

N Baliga

Ratnakar D Bhelkar

Glenn A Biery

Alisa Blauberg

Natalia Borjemscaia

Andres Bryant

L Cao

Vinod Chauhan

M Chen

L Cheng

Jae-Ouk Choo

Cathryn Christiansen

T-Y Chu

B Cohen

R Coleman

David Conklin

Stephen W Crown

Adam da Silva

Dan J Dechene

Garo J Derderian

Sadanand Deshpande

G Dilliway

Keith Donegan

Manfred Eller

Y Fan

Qiang Fang

A Gassaria

Robert Gauthier

S Ghosh

George G Gifford

T Gordon

M Gribelyuk

G Han

J -H Han

Kichon Han

M Hasan

Jack M Higman

J Holt

L Hu

L Huang

C Huang

T Hung

Y Jin

J B Johnson

S Johnson

V Joshi

Manoj Joshi

Patrick Justison

Srinivas Kalaga

T J Kim

W V Kim

Rishikesh Krishnan

Bharat Krishnan

K Anil

Mahesh Kumar

Jung-Woo Lee

R Lee

John Lemon

San Leong Liew

P Lindo

M Lingalugari

M Lipinski

P Liu

Jiakai Liu

Stephen Lucarini

W Ma

E Maciejewski

Sudeep Madisetti

Arkadiusz Malinowski

Jash Mehta

Cai Meng

Swarupa Mitra

Christa Montgomery

Hasan Nayfeh

Tanya Nigam

Gregory A Northrop

K Onishi

C Ordonio

Merve Ozbek

Rohit Pal

S R Parihar

Otis Patterson

Eswar Ramanathan

I Ramirez

R Ranjan

Jeric Sarad

V Sardesai

Sangameshwar R Saudari

Carl Schiller

B Senapati

C Serrau

Nilay D Shah

Tian Shen

H Sheng

Joseph F Shepard

Y C Shi

M C Silvestre

D Singh

Z M Song

John R Sporre

Purushothaman Srinivasan

Z Sun

A Sutton

Ryan Sweeney

Keith H Tabakman

M Tan

Xiang-hui Wang

E Woodard

G Xu

D Xu

Truong Luan Xuan

Y Yan

Jingyue Yang

Kong Boon Yeap

M Yu

A Zainuddin

Jia Zeng

K K Zhang

M Zhao

Y Zhong

Rick Carter

C-H Lin

Stephan Grunow

Craig Child

M Lagus

R Fox

E Kaste

Geogina Gomba

Srikanth Samavedam

Paul D Agnello

Dong Kyun Sohn
title: A 7nm CMOS technology platform for mobile and high performance compute application
venue: 2017 IEEE International Electron Devices Meeting (IEDM)
year: 2017

abstract: Magnetometers based on quantum mechanical processes enable high sensitivity and long term stability without the need for re calibration, but their integration into fieldable devices remains challenging. This article presents a CMOS quantum vector field magnetometer that miniaturizes the conventional quantum sensing platforms using nitrogen vacancy (NV) centers in diamond. By integrating key components for spin control and readout, the chip performs magnetometry through optically detected magnetic resonance (ODMR) through a diamond slab attached to a custom CMOS chip. The ODMR control is highly uniform across the NV centers in the diamond, which is enabled by a CMOS generated ~2.87 GHz magnetic field with 5% inhomogeneity across a large area current driven wire array. The magnetometer chip is 1.5 mm<sup>2</sup> in size, prototyped in 65 nm bulk CMOS technology, and attached to a 300 <inline formula> <tex math notation="LaTeX"\times /tex math>/inline formula> 80 <inline formula> <tex math notation="LaTeX"\mu \text{m}{2} /tex math>/inline formula> diamond slab. NV fluorescence is measured by CMOS integrated photodetectors. This ON chip measurement is enabled by efficient rejection of the green pump light from the red fluorescence through a CMOS integrated spectral filter based on a combination of spectrally dependent plasmonic losses and diffractive filtering in the CMOS back end of line (BEOL) This filter achieves a measured ~25 dB of green light rejection. We measure a sensitivity of 245 nT/Hz<sup>1/2</sup> marking a 130<inline formula> <tex math notation="LaTeX"\times /tex math>/inline formula> improvement over a previous CMOS NV sensor prototype, largely thanks to the better spectral filtering and homogeneous microwave generation over larger area.
author_names: Mohamed I Ibrahim

Christopher Foy

Dirk R Englund

Ruonan Han
title: High Scalability CMOS Quantum Magnetometer With Spin State Excitation and Detection of Diamond Color Centers
venue: IEEE Journal of Solid State Circuits
year: 2021

abstract: Schmitt triggers with standard CMOS logic circuits are described, first. Mathematical models for calculating basic parameters and their limits are presented. Most of the chapter is dedicated to different solutions for CMOS and BiCMOS Schmitt logic circuits in monolithic integrated circuits. Two types of inverters with entirely different topologies are described. Also, solutions for Schmitt triggers with voltage controlled thresholds are described. Beside inverters, NAND and NOR Schmitt logic circuits are analyzed. Basic circuit is inverted Schmitt trigger with three pairs of CMOS transistors. Expansion of the number of inputs is reached in a similar way as in standard CMOS and BiCMOS logic circuits. It is shown that voltage transfer characteristics depend, beside voltage supply and parameters of transistors, on the number of logical circuits' inputs. NAND and NOR Schmitt circuits, in which voltage hysteresis in transfer characteristic is generated only through one input, are also described. Analytic models and SPICE simulations are used for analysis of static and dynamic parameters and conditions for work stability and reliability. Areas of reliability, influence of technology and electrical parameters of transistors and their limits are analyzed. Concerning the field of application, in literature there are different solutions of Schmitt triggers (Zou et al, 2008, Al Sarrawi, 2008, Katyal et al, 2008, Lo et al, 2010) In this chapter, solutions with fundamental applications in digital integrated circuits Schmitt logic circuits are described. The author published most of these solutions (Dokic, 1983, Dokic 1984, Dokic 1996, Dokic, 1988) Today, some of them (Dokic, 1984) are treated as conventional. The term regenerative is used because every change of state is followed by a regenerative process positive feedback. Owning to that, transfer characteristic has shape of a hysteresis, like in Schmitt trigger. That is why the term Schmitt logic circuits is most commonly used. Unlike conventional logic circuits, where the output level is uniformly determined for the input voltage value, for Schmitt logic circuits, in certain extent, it is not uniformly determined. In fact, due to hysteresis, in the area of the input voltages between two logic thresholds, logic state at the output depends, beside the input voltage value, also on the previous state. Due to that Schmitt circuits can be used as filters for low frequency interferences. An example of this kind of application is given in Fig.1. Whenever the value of the input signal passes the value of the threshold voltage Ji Zhang of the standard logic circuit, a change of the logic state at the output appears. Therefore, the changes of the input voltage created by noise are transferred to the output as glitches. The change of the logic state at the output of the Schmitt logic circuit can appear only after the noise amplitude of which is greater than the voltage hysteresis.
author_names: Branko Dokic
title: CMOS and BiCMOS Regenerative Logic Circuits
year: 2012