Query: Tunnel field-effect transistors as energy-efficient electronic switches

Candidate papers:

abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum mechanical band to band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100 fold power reduction over complementary metal oxide semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low power integrated circuits.
author_names: Adrian M Ionescu

Heike E Riel
title: Tunnel field effect transistors as energy efficient electronic switches
venue: Nature
year: 2011

abstract: In a continuous search for the energy efficient electronic switches, a great attention is focused on tunnel field effect transistors (TFETs) demonstrating an abrupt dependence of the source drain current on the gate voltage. Among all TFETs, those based on one dimensional (1D) semiconductors exhibit the steepest current switching due to the singular density of states near the band edges, though the current in 1D structures is pretty low. In this paper, we propose a TFET based on 2D graphene bilayer which demonstrates a record steep subthreshold slope enabled by van Hove singularities in the density of states near the edges of conduction and valence bands. Our simulations show the accessibility of 3.5 x 104 ON/OFF current ratio with 150 mV gate voltage swing, and a maximum subthreshold slope of (20 mV/dec) 1 just above the threshold. The high ON state current of 0.8 mA/mm is enabled by a narrow ~0.3 eV) extrinsic band gap, while the smallness of the leakage current is due to an all electrical doping of the source and drain contacts which suppresses the band tailing and trap assisted tunneling.
author_names: Georgy Alymov

Vladimir Vyurkov

Victor Ryzhii

Dmitry Svintsov
title: Abrupt current switching in graphene bilayer tunnel transistors enabled by van Hove singularities
venue: Scientific reports
year: 2016

abstract: Summary form only given. In this talk, I will review some of the recent development of tunnel field effect transistors (TFETs) at Notre Dame [1 8] Tunnel FETs are promising replacements of Si MOSFETs beyond 2020 due to their promise to achieve I<sub>on</sub>/I<sub>off</sub> 10<sup>3</sup> with I<sub>on</sub> 100 uA/um at low supply voltages (up to 0.5 V) To date we have demonstrated I<sub>on</sub>/I<sub>off</sub> 10<sup>6</sup> I<sub>on</sub> 180 uA/um, separately, based on III V heterostructures. Challenges ahead include electrostatic control, defect assisted tunneling and interface state density and parasitics. More recently, we have started to investigate 2D crystal based TFETs for their promises to realize ultrascaled electronic switches.
author_names: Huili Grace Xing

Guangle Zhou

Mingda Li

Yiqing Lu

Rui Li

Mark A Wistey

Patrick J Fay

Debdeep Jena

Alan C Seabaugh
title: Tunnel FETs with tunneling normal to the gate
venue: 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)
year: 2013

abstract: Cooler electrons for transistors The operating power of field effect transistors is constrained in part by the minimum change in voltage needed to change the current output. This subthreshold swing (SS) limit is caused by hotter electrons from a thermal electron source leaking over the potential of the gate electrode. Qiu et al. show that graphene can act as a Dirac source that creates a narrower distribution of electron energies. When coupled to a carbon nanotube channel, the decrease in SS would allow the supply voltage to be decreased from 0.7 to 0.5 volts. Science, this issue p. 387 A graphene source of cold electrons lowers the subthreshold swing and supply voltage in field effect transistors. An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS) 60 millivolts per decade, in field effect transistors (FETs) We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state of the art silicon 14 nanometer node FETs, a similar on state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off state.
author_names: Chenguang Qiu

Fei Liu

Lin Xu

Bing Deng

Mengmeng Xiao

Jia Si

Li Lin

Zhiyong Zhang

Jian Wang

Hong Guo

Hailin Peng

Lian-Mao Peng
title: Dirac source field effect transistors as energy efficient, high performance electronic switches
venue: Science
year: 2018

abstract: Conventional field effect transistors (FETs) have long been considered a fundamental electronic component for a diverse range of devices. However, nanoelectronic circuits based on FETs are not energy efficient because they require a large supply voltage for switching applications. To reduce the supply voltage in standard FETs, which is hampered by the 60 mV/decade limit established by the subthreshold swing (SS) a new class of FETs have been designed, tunnel FETs (TFETs) A TFET utilizes charge carrier transportation in device channels using quantum mechanical based band to band tunneling despite of conventional thermal injection. The TFETs fabricated with thin semiconducting film or nanowires can attain a 100 fold power drop compared to complementary metal oxide semiconductor (CMOS) transistors. As a result, the use of TFETs and CMOS technology together could ameliorate integrated circuits for low power devices. The discovery of two dimensional (2D) materials with a diverse range of electronic properties has also opened new gateways for condensed matter physics, nanotechnology, and material science, thus potentially improving TFET based devices in terms of device design and performance. In this review, state of art TFET devices exhibiting different semiconducting channels and geometries are comprehensively reviewed followed by a brief discussion of the challenges that remain for the development of high performance devices. Lastly, future prospects are presented for the improvement of device design and the working efficiency of TFETs.
author_names: Ghazanfar Nazir

Adeela Rehman

Soo-Jin Park
title: Energy efficient tunneling field effect transistors for low power device applications: challenges and opportunities.
venue: ACS applied materials interfaces
year: 2020

abstract: Ballistic electron conduction offers a new possible approach to the development of low power high speed logic circuits [1 3] Ultra high mobility of graphene allows achieving the ballistic or near ballistic transport regime at room temperature (RT) in devices with relatively long channels [4 5] In this presentation, we show that heterostructure field effect transistors (HFETs) with graphene channel encapsulated between two layers of hexagonal boron nitride (h BN) combine extremely high electron mobility ~36,000 cm2/Vs) with a strongly reduced 1/f noise level (f is the frequency) Low frequency 1/f noise hampers the operation of numerous devices and can be a major impediment to development of practical low power low voltage applications of graphene and other 2D van der Waals materials [6 8] The low noise level is beneficial for the low voltage electronic applications. The prototype h BN graphene h BN HFETs were fabricated using the mechanically exfoliated h BN and graphene flakes on Si/SiO2 wafers. The viscoelastic materials adhered to glass slides were used as transparent stamps for the layer transfer. The stamps were spin coated with poly propylene carbonate (PPC) A micromanipulator was used for careful positioning of h BN flakes on the stamp over graphene flakes. Following this procedure, the h BN layer was added to the stack resulting in a fully encapsulated graphene monolayer. The stack was then released onto target Si/SiO2 substrate by heating the stage to an appropriate temperature. The resulting heterostructure was etched to expose the edges of graphene and create one dimensional Cr/Au (10/100 nm) electrical contacts. Figure 1 shows the schematics and an optical microscopy image of a representative device. Figure 2 (a) shows the current voltage (I V) characteristics of the representative HFET. Both the effective and field effect mobility extractions gave consistent results showing the mobility of ~36,000 cm2/Vs at the carrier concentration of 7x1011 cm2. Figure 2 (b) presents the normalized 1/f noise spectral density of the graphene encapsulated device. The channel area normalized noise spectral density in BN graphene BN HFET is factor of x5 x10 smaller than that in typical reference graphene FETs without the channel encapsulation. The observed strong noise reduction can be explained by screening of the traps in SiO2 by the BN barrier. Other possible physical mechanisms and prospects of further noise suppression will be discussed at the presentation.
author_names: Maxim A Stolyarov

Sergey Rumyantsev

Michael S Shur

Alexander A Balandin
title: Low noise near ballistic BN graphene BN heterostructure field effect transistors for energy efficient electronic applications
venue: 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S)
year: 2015

abstract: Energy efficiency is considered to be the most critical design parameter for ubiquitous and mobile computing systems. With consumers expecting improved functionality and performance from these systems without compromising on battery life, there is urgent need to explore emerging technologies that can overcome the limitations of CMOS and deliver greater energy efficiency. The potential of one such prospective metal oxide semiconductor field effect transistor replacement device, the tunnel FET (TFET) is evaluated in this study. Novel circuit designs are presented to overcome unique design challenges posed by TFETs. Further, the impact of TFETs at different levels of design abstraction is characterised by evaluating a novel sparse prefix tree adder and a field programmable gate array. A considerable improvement in delay and significant reduction in energy is observed because of the combined impact of circuit and technology co exploration.
author_names: Ravindhiran Mukundrajan

Matthew Cotter

Sungmin Bae

Vinay Saripalli

Mary Jane Irwin

Suman Datta

Narayanan Vijaykrishnan
title: Design of energy efficient circuits and systems using tunnel field effect transistors
venue: IET Circuits Devices Syst.
year: 2013

abstract: The technology, a tunnel field effect transistor (TFET) features two advantages over conventional TFET devices. First, the tunnel junction is steeper with high doping concentration, leading to a thinner tunnel barrier, and thus higher tunnelling currents. This was achieved by a new process that provides both silicidation and dopant segregation directly in the source region. Second, the tunnelling area with tunnelling parallel to the electric field of the gate is enlarged by means of selective and self adjusting silicidation. This further increases the tunnelling currents.
title: PRODUCTION OF A TUNNEL FIELD EFFECT TRANSISTOR (TFET) FOR ENERGY EFFICIENT NANOELECTRONICS
year: 2020

abstract: Two dimensional (2D) topological insulators (TIs) are 2D semiconductors/insulators that distinguish themselves from 'conventional' 2D semiconductors/insulators (like monolayer hBN or MoS2) by the presence of electronic states on their edges. These TI edge states traverse the bandgap and exhibit spin momentum locking. The spin momentum locking prohibits intra edge scattering giving rise to efficient electronic transport. Electronic transport will proceed efficiently along the TI edge states as long as the Fermi level is positioned in the bandgap of the 2D TI. If the Fermi level in the 2D TI is close to or lies in the bulk conduction or valence band, scattering is no longer prohibited and can dramatically reduce the conductivity of the 2D TI. Gating a 2D TI enables the modulation of the Fermi level and subsequently the current, realizing a 2D TI field effect transistor (FET) [1]
author_names: William G Vandenberghe
title: Two dimensional topological insulator transistors as energy efficient switches robust against material and device imperfections
venue: 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems Steep Transistors Workshop (E3S)
year: 2017

abstract: A great obstacle for ultralow power MOSFETs functioning at very low voltages is their physical limit of the inverse subthreshold swing of 60 mV/dec at 300K. Quantum mechanical tunneling of carriers from the source into the channel in Tunnel FETs overcomes in principle this hurdle. However, the fabrication of powerful complementary Tunnel FETs with high Ion/Ioff ratios and steep slopes is still a great challenge. Nevertheless, Tunnel FETs are considered as the most promising concept as steep slope devices. In this contribution an overview will be given mainly on Si based Tunnel FETs. Results of planar and nanowire TFETs with Si, strained Si and Silicon Germanium will be shown. Particular emphasis will be placed on the device performance improvement by formation of the steep tunnel junction and the improved device electrostatics defined by the gate stack and the geometry of the device. We have developed a novel process to produce complementary TFETs and first TFET inverters. Strained Si nanowire TFETs show on currents well above 10 ?A/?m at VDS= 0.5 V and n TFETs reach a minimum slope of 30 mV/dec. Inverter voltage transfer curves and their time response will be presented. The TFET inverters show sharp transitions and high gain even at very small voltages, VDD 0.2V, indicating their potential for energy efficient electronics.
author_names: Siegfried Mantl
title: Keynote: Si based tunnel field effect transistors for energy efficient electronics
year: 2014