Query: SiGe Pre epi clean

Candidate papers:

abstract: As electronic devices are evolving to more diversified and specifically function oriented applications, silicon based semiconductors have shown their limitation to unprecedented functionality requirements such as high power, high frequency, and high temperature operation. Growing utilization of IV IV compounds (e.g. SiGe, SiC) III V compounds (e.g. GaAs, GaN) as well as hetero epitaxial structures with Si has become an inevitable trend. Due to cost and size of SiC and GaN wafers, epitaxial deposition on Si is utilized. However, this requires an efficient pre epitaxial wet cleaning of the Si wafer yielding the lowest defects possible. In this study, different HF last processes were tested yielding that an in situ process with dilute chemicals gives the best results.
author_names: Darian Waugh

Gim S Chen

Jennifer Boecker

Ismail I Kashkoush
title: Application of In situ Pre epi Clean Process for Next Generation Semiconductor Devices
venue: 2019 16th China International Forum on Solid State Lighting 2019 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS)
year: 2019

abstract: Epitaxial deposition of strained Si and SiGe to improve electron and hole mobility and Vt shift is becoming more and more part of the standard CMOS processing [1,2] One of the most important restrictions imposed on advanced CMOS processing is that on thermal budget. For epitaxial growth processes this thermal budget is quite high. The main contribution comes however not from the growth itself, but from the in situ H2 bake necessary to remove any oxide traces left prior to epi. Without any pre epi etch, removal of the native oxide requires at least a bake for several minutes at 900 C or higher. When combined with a wet clean which removes the native oxide and passivates the surface (usually H or Cl) this temperature can be reduced to the range of 850 750 C, although this is always at the cost of a remaining C and O peak at the epi substrate interface.
author_names: Ken-ichi Sano

Frederik E Leys

G Dilliway

Roger Loo

Paul W Mertens

Jim Snow

Akira Izumi

Atsuro Eitoku
title: Challenges of Single Wafer Wet Cleaning for Low Temperature Pre Epitaxial Treatment of SiGe
year: 2007

abstract: Locally strained Si technology using embedded SiGe has been used to improve pMOSFET device performance through hole mobility enhancement. Embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si pMOSFET source and drain areas. Prior to selective SiGe epi growth, a thin layer of Si seed was employed to help nucleate following low temperature selective SiGe epitaxial film in recessed source and drain areas. In combination with pre epi wet clean and low temperature chemical bake, use of Si seed resulted in improved SiGe film morphology and micro loading effect, and further improved device performance.
author_names: Po-Lun Cheng

Chin I Liao

Chin Cheng Chien

C L Yang

S F Ting

Li-Shian Jeng

Cheng Tung Huang

Osbert Cheng

S F Tzou

Wensyang Hsu
title: Effectiveness of Si thin buffer layer for selective SiGe epitaxial growth in recessed source and drain for pMOS
year: 2008

abstract: A thin layer (15A) of Si seed was employed to help nucleate low temperature selective SiGe epitaxial film in recessed source and drain. In combination with pre epi wet clean and low temperature chemical bake, use of Si seed resulted in improved SiGe film morphology and micro loading effect, and further improved dislocation on the lateral recess interface. Introduction Locally strained Si technology using embedded SiGe has demonstrated improved pMOSFET device performance through hole mobility enhancement [1 3] Widely used, embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si source and drain in the pMOSFET area. Typical process steps for recessed source and drain SiGe flow is described elsewhere [2] Prior to selective SiGe epi growth, multiple implants and dry etch of source and drain result in surface damage and chemical residues. Surface quality and cleanliness of the etched Si surfaces have great impact on the morphology and SiGe film quality. Typically, wet clean (in diluted HF) or high temperature bake 800 degC) is used as a preepi step to remove surface C and O. Previous study [4] indicated improvement of SiGe film morphology by multiple cycles of wet clean in ozonated DI/SC1/DHF. For most harsh surfaces with severe damage casued by implant and dry etch, use of Si seed layer is employed to nucleate uniform SiGe film with good quality and to minimize micro loading effect. Experiments and Results Prior to SiGe deposition, device wafers were cleaned in ozonated DI, SC1, and dipped in diluted HF (DHF) Wafers were introduced to the reaction chamber for low temperature bake followed by selective deposition of Si seed and SiGe film in recessed source and drain areas in the pMOS area. Control wafer was process with similar pre epi wet clean, bake, and deposition without the seed layer. Wafers with severe surface damage did not yield SiGe film growth of good morphology without the seed layer. However, wafers with surface damage resulted in difference in SiGe film morphology with or without the Si seed as shown in Figure 1 and Figure 2. Improved surface morphology is observed as clear faceting and dislocation free around the lateral recess interface in the case with the Si seed. Also, the surface roughness can be healed well in the different density area of wafer by Si seed, further improve micro loading with the similar incubation time. Micro loading between isolated area and dense area was improved 92% once Si seed layer was applied. Besides, Si seed implement not only decrease micro loading effect but also without SiGe quality degradation. Micro loading was defined as (maximum thickness minimum thickness)/minimum thickness in the same die. (a) (b) Figure 1. Comparison of morphology of selective grown SiGe film (a) with and (b) without Si seed.
author_names: Po-Lun Cheng

Chin I Liao

Houxiao Wu

Yi Cheng Chen

Chin Cheng Chien

Chan Lon Yang

S F Tzou

Jinsong Tang

Yonah Cho

Errol Antonio C Sanchez

Vincent C Chang

T Fu

Wensyang Hsu
title: Effectiveness of Si Seed for Selective SiGe Epitaxial Deposition in Recessed Source and Drain for Locally Strained pMOS Application
year: 2006

abstract: Abstract Motivated by the need to grow fast high quality virtual substrates (VS) for strained Si SiGe channels or for Ge/GaAs applications, Unaxis Semiconductors has developed low energy plasma processes (LEPP) which are running on a new LEPP 300 cluster tool. The system combines the utilisation of plasma for pre epi clean and for epitaxial growth in a production system. It consists of two new processes both applicable for 300 mm wafers: the LEPC (low energy plasma cleaning) process, a dry low temperature (unkeyable??150 degC) process for wafer cleaning before epitaxial growth (pre epi clean) and the LEPECVD (low energy plasma enhanced CVD) a deposition process which allows deposition rates in the range between 0.01 nm/s and several nm /s at 550degC.
author_names: Jurgen Ramm
title: Low energy plasma processing (LEPP) for SiGe applications
year: 2002

author_names: Kurt Wostyn

Dirk Rondas

Roger Loo

Sathish Kumar Dhayalan

Andriy Hikavyy

Wim Elskens

Alex Vyncke

Paul W Mertens

Frank Holsteyns

Stefan De Gendt

Toru Masaoka

Yukifumi Yoshida

Gerhard Bast

Gavin Simpson
title: Enabling GeH4 HCl in situ pre epi clean: impact of water quality on HF last process performance
year: 2015

author_names: V Machkaoutsan

Keith Doran Weeks

Matthias Bauer

J W Maes

John Tolle

Shawn G Thomas

A Alian

Andriy Hikavyy

Roger Loo
title: High Efficiency Low Temperature Pre epi Clean Method for Advanced Group IV epi Processing
year: 2013

abstract: Further improving complementary metal oxide semiconductor (CMOS) performance beyond the 15 nm generation likely requires the use of high mobility materials like Ge for pMOS devices. However, Ge pMOS devices made in relaxed Ge do not outperform current state of the art uni axially strained Si pMOS devices. This explains the current interest in compressively strained Ge like bi axially strained Ge grown on top of SiGe Strain Relaxed Buffers. From a device integration point of view, the surface smoothness of the strained Ge layer is an important parameter which has so far not widely been reported in literature, in contrast to other parameters like the material quality (crystallinity) and the threading dislocation density. In this paper we report the post CMP and pre epi cleans which are required to obtain contamination free SiGe surfaces to enable defect free strained Ge growth without reoccurrence of the surface roughening. We will demonstrate the epitaxial growth of fully strained 20 nm thick Ge epitaxially grown on top of SiGe Strain Relaxed Buffers with 85% Ge with a surface roughness as low as 1.6 A (as measured on areas of 10x10 um2)
author_names: Roger Loo

Laurent Souriau

Patrick Ong

Karine Kenis

Jens Rip
title: Optimized Post CMP and Pre Epi Cleans to Enable Smooth and High Quality Epitaxial Strained Ge Growth on SiGe Strain Relaxed Buffers
year: 2012

author_names: Mireia Bargallo Gonzalez

Nicole K Thomas

Eddy Simoen

Peter Verheyen

Andriy Hikavyy

Frederik E Leys

Yasutoshi Okuno

Bertrand Vissouvanadin Soubaretty

Benny van Daele

Luc Geenen

Roger Loo

Cor Claeys

V Machkaoutsan

Pierre Tomasini

Shawn G Thomas

Jiong Ping Lu

J W Weijtmans

R Wise
title: Analysis of the Pre epi Bake Conditions on the Defect Creation in Recessed SiGe S/D Junctions
year: 2007

abstract: Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex situ wet chemical cleans and in situ pre epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low temperature pre epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.
author_names: Roger Loo

Andriy Hikavyy

Frederik E Leys

Masayuki Wada

Ken-ichi Sano

Brecht De Vos

Antoine Pacco

Mireia Bargallo Gonzalez

Eddy Simoen

Peter Verheyen

W Vanherle

Matty Caymax
title: Low Temperature Pre Epi Treatment: Critical Parameters to Control Interface Contamination
year: 2008