Query: stacked die process

Candidate papers:

abstract: Following the strong demand of high performance and miniaturized electronic devices with reduced process cycle time, the die attach film (DAF) has become a popular option for the die attach process of stacked die packages in the semiconductor assembly industry. The working temperature of a die attach process is crucial to assembly yield and package reliability. However, as the number of die stacks increases, the die attach process with DAF may encounter a technical bottleneck since the working area is gradually away from the heat source. In this study, the thermal effect from bottom heating of plural die stack structures was investigated through transient thermal analysis as well as temperature measurements in an actual stacked die process. It is clear from numerical and experimental results that as the number of dies in the die stack structure increases, the time required to reach a working temperature for DAF increases significantly.
author_names: Tsung-Yueh Tsai

Hsiao-Chuan Chang

Wei-Chung Li

Chi-Ping Teng

Yi-Shao Lai
title: Working Temperature Characterizations for Die Attach Films in Stacked die Process
venue: 2007 32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium
year: 2007

abstract: Three dimensional (3 D) stacked die packaging can reduce cost and improve performance. It utilizes the oldest process, wire bonding, to connect chips with a large bond height difference (BHD) via deep cavity looping. This paper develops 3 D and 2 D finite element models of the process and validate them against experiments. The effects of the height difference between two bond points, reverse motion parameter, kink height parameter, and elliptic capillary traces on the process are studied. The simulations demonstrate that deep cavity looping produces greater deformation on kink II, a lower loop height, and more violent pulling on the wire than traditional looping. Optimized capillary trace parameters for traditional looping are not suitable for deep cavity looping; however, the trends in the effects of the parameters are the same. Elliptic capillary traces can change wire profiles significantly.
author_names: Fuliang Wang

Yun Chen

Lei Han
title: Modeling of Deep Cavity Looping Process on 3 D Stacked Die Package
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2013

abstract: This paper examines the comprehensive effects of vapor pressure, hygroscopic swelling and thermal expansion on the reliability of stacked die package during soldering reflow by the finite element analysis. First, the moisture concentration distributions were obtained for preconditioning at MSL 1 as well as desorption at the reflow process. For the diffusion modeling, existing normalization approaches are only valid under constant temperature/humidity condition and cannot be extended to the reflow process which contains time varying thermal loading. In this study, the internal source approach was adopted to overcome the concentration discontinuity at material interfaces during solder reflow. A micromechanics based vapor pressure model was used to predict the vapor pressure field based on the moisture concentration results from the diffusion analysis. Second, a comprehensive nonlinear finite element model was proposed to integrate the effects of vapor pressure, thermo mechanical stress and hygro mechanical stress with consideration of the non uniform moisture distribution and the viscoelastic behavior of mold compound. The individual and integrated effects of vapor pressure, hygroscopic swelling and thermal expansion on warpage and stress distribution were investigated. Finally, a fracture mechanics based approach was used to study the thermal moisture impact on the delamination of the stacked die package. The transient variations of the strain energy release rate during soldering reflow due to the vapor hygro thermal mechanical stress were evaluated and compared under different crack lengths.
author_names: Jing Wang

Seungbae Park
title: Non linear Finite Element Analysis on Stacked Die Package Subjected to Integrated Vapor Hygro Thermal Mechanical Stress
venue: 2016 IEEE 66th Electronic Components and Technology Conference (ECTC)
year: 2016

abstract: In the present study the direct concentration approach (DCA) and the whole field vapor pressure model developed in Part I of this work (Xie et al. 2009 "Direct Concentration Approach of Moisture Diffusion and Whole Field Vapor Pressure Modeling for Reflow Process: Part I Theory and Numerical Implementation, " ASME J. Electron. Packag. 131, p. 031010) is applied to 3D ultrathin stacked die chip scale packages to investigate wafer level die attach film cohesive failures during the reflow process. Oversaturation, which refers to the film that absorbs more moisture when reflow process begins, is observed using the DCA. The modeling results suggest that the moisture transport and escape through the substrate during the reflow is responsible for the film rupture. A small reduction in substrate thickness could result in a significant decrease in moisture concentration and vapor pressure in bottom layer film and therefore reduce failure rate greatly. A slight improvement in reflow profile while still meeting specification allows a significant amount of moisture loss during the reflow; hence failure rate could also be reduced greatly. The mechanism of soft film rupture at reflow due to moisture is discussed in detail. The simulation results are consistent with the published experimental data.
author_names: Bin Xie

Xuejun Fan

Xunqing Shi

Han Ding
title: Direct Concentration Approach of Moisture Diffusion and Whole Field Vapor Pressure Modeling for Reflow Process Part II: Application to 3D Ultrathin Stacked Die Chip Scale Packages
year: 2009

abstract: As the demand is increasing for memory cards, portable computing systems, multiple chip packages (MCPs) and other applications that require thin integrated circuits (ICs) the wafer thinning for advanced packaging methods become more and more important. This paper gives an overview of the different industrial wafer thinning and dicing techniques, including dicing after grinding (DAG) dicing before grinding (DBG) laser cut after grinding (LAG) and laser stealth dicing before grinding (SDBG) The process capability for each process was compared, and the challenges encountered during thinning and dicing the wafer to be 25 um thickness are analyzed. Potential process issues have been investigated, including die strength and subsurface damage that is associated with these processes and mechanical properties, such as surface conditions and die warpage etc. Die strength test configurations and criteria are also included.
author_names: Renfu Zhang

Hao Liu

Bo Li

Tetsukazu Sugiya
title: Ultra wafer thinning and dicing technology for stacked die packages
venue: 2016 China Semiconductor Technology International Conference (CSTIC)
year: 2016

abstract: In the present study, the direct concentration approach (DCA) and the whole field vapor pressure model developed in Part I of this work (Xie et al. 2009 "Direct Concentration Approach of Moisture Diffusion and Whole Field Vapor Pressure Modeling for Reflow Process: Part I Theory and Numerical Implementation," ASME J. Electron. Packag. 131, p. 031010) is applied to 3D ultrathin stacked die chip scale packages to investigate wafer level die attach film cohesive failures during the reflow process. Oversaturation, which refers to the film that absorbs more moisture when reflow process begins, is observed using the DCA. The modeling results suggest that the moisture transport and escape through the substrate during the reflow is responsible for the film rupture. A small reduction in substrate thickness could result in a significant decrease in moisture concentration and vapor pressure in bottom layer film and therefore reduce failure rate greatly. A slight improvement in reflow profile while still meeting specification allows a significant amount of moisture loss during the reflow; hence failure rate could also be reduced greatly. The mechanism of soft film rupture at reflow due to moisture is discussed in detail. The simulation results are consistent with the published experimental data. DOI: 10.1115/1.3144154
author_names: J Fan
title: Direct Concentration Approach of Moisture Diffusion and Whole Field Vapor Pressure Modeling for Reflow Process Part II Application to 3 D Ultrathin Stacked Die Chip Scale Packages
year: 2009

abstract: Quality control and failure analysis of IC packages require physical access to the die during destructive analysis. Successful analysis depends on the critical preservation of the original state of the die, bond wire, bond pad, and original failure sites during the package decapping process. The currently used acid and conventional plasma decapping techniques have their intrinsic limitations in certain analysis cases, for example 3D stacked die package with complex structures, HAST stressing that causes epoxy hardening, the use of epoxy refill materials and acid resistant epoxy molding compounds, the use of Cu and PdCu bond wires, preservation of original die and bond wire surface features, preservation of original failure sites and contaminants, etc. Such difficult cases with conventional decapping techniques often suffers from low analysis accuracy and low confidence level during root cause failure analysis, and consequently poses major threat to the quality assurance of the IC products. In order to overcome the limitations of conventional decapsulation techniques, a new generation decapsulation technique is developed with an atmospheric pressure Microwave Induced Plasma (MIP) As the MIP system operates at atmospheric pressure and the mean free path of ions at that pressure is extremely low, only isotropic high selectivity etching occurs by long lived oxygen radicals. Recipe and decapping process development is made to solve each of the challenging cases individually. As an ultimate evaluation on the capability of this MIP decapping technique, we deliberately combined multiple decapping difficulties into one single device: a 3D stacked die package that has deliberately introduced contamination and epoxy refill and went through HAST. It appears that the O2 only MIP afterglow decapsulation successfully preserves the deliberately introduced contamination sites in the 3D stacked die package. The unique capability of MIP decapsulation in facilitating accurate failure analysis and quality control is demonstrated.
author_names: J W Tang

M R Curiel

S L Furcone

E G J Reinders

C Th A Revenberg

C I M Beenakker
title: Failure analysis of complex 3D stacked die IC packages using Microwave Induced Plasma afterglow decapsulation
venue: 2015 IEEE 65th Electronic Components and Technology Conference (ECTC)
year: 2015

abstract: Portable consumer electronics have a tremendous demand of miniaturization, high density and high performance. 3D SIP is an efficient solution to meet this requirement. This paper had presented an innovative 3D package product configured with stacked die and cavity embedded substrate. Through hole via in the substrate provides the signal communication at a cost effective way. This structure satisfies the high standards for mobile products packaging by reducing the package size and cost and maintaining functionality. In this paper, some details on the design concepts of the structure are introduced. Then, since the geometric configuration of the bonding wire is unusual, the electrical performance of the wire bonds of the structure is predicted by HFSS. Though the wire bond is long, simulation results shows that it is still suitable for the speed circuits below 3GHz. On the other hand, the two step cavity effectively improves the isolation capability between different die. Moreover, the fabrication process of this structure is presented in detail to access the design. Finally, the functional test of the end products is performed and the end products work well.
author_names: Huiqin Xie

James Li

Jian Song

Fengze Hou

Xueping Guo

Shuling Wang

Yu Daquan

Cao Liqiang

Lixi Wan
title: A 3D package design with cavity substrate and stacked die
venue: 2013 14th International Conference on Electronic Packaging Technology
year: 2013

abstract: The copper based leadframe is practically proven effective in the thermal and reliability of a Quad Flat No Lead (QFN) three dimension (3D) stacked die semiconductor package. Reducing the copper thickness is understood to present various thermal and reliability failure mode and mechanisms, such as die cracking and delamination. However, no in depth study has been pursued to determine the capability of achieving the product requirements in terms of thermal and reliability in a 3D stacked die package. The drive towards a Die Free Package Cost (DFPC) reduction has led the authors to study the used of a thin leadframe in a QFN 3D stacked die. Hence, the work presents basis for the qualification of a thin leadframe design, and also to demonstrate the thermal and reliability performance. Finally, an extensive virtual thermal mechanical prototyping has to be achieved in order to understand the physics of materials during the assembly and reliability testing of a 3D stacked die package with a thin leadframe. This design rule was found to be developed in order to prevent a die crack occurrence between die and leadframe in the semiconductor package.
author_names: Samihah Abdullah

Mohamad Faizal Abdullah

Ahmad Kamal Ariffin

Zalina Abdul Aziz

Mariyam Jameelah Ghazali
title: Thermal Mechanical Analysis of a QFN Stacked Die Leadframe under Reflow Process
year: 2008

abstract: Process variations in integrated circuits have significant impact on their performance, leakage, and stability. This is particularly evident in large, regular, and dense structures such as DRAMs. DRAMs are built using minimized transistors with presumably uniform speed in an organized array structure. Process variation can introduce latency disparity among different memory arrays. With the proliferation of 3D stacking technology, DRAMs become a favorable choice for stacking on top of a multicore processor as a last level cache for large capacity, high bandwidth, and low power. Hence, variations in bank speed create a unique problem of nonuniform cache accesses in 3D space. In this paper, we investigate cache management techniques for tolerating process variation in a 3D DRAM stacked onto a multicore processor. We modeled the process variation in a four layer DRAM memory, including cell transistor, capacitor trench, and peripheral circuit, to characterize the latency and retention time variations among different banks. As a result, the notion of fast and slow banks from the core's standpoint is no longer associated with their physical distances with the banks. They are determined by the different bank latencies due to process variation. We develop cache migration schemes that utilize fast banks while limiting the cost due to migration. Our experiments show that there is a great performance benefit in exploiting fast memory banks through migration. On average, a variation aware management can improve the performance of a workload over the baseline (where one of the slowest bank speed is assumed for all banks) by 16.5 percent. We are also only 0.8 percent away in performance from an ideal memory where no process variation is present.
author_names: Bo Zhao

Yu Du

Jun Yang

Youtao Zhang
title: Process Variation Aware Nonuniform Cache Management in a 3D Die Stacked Multicore Processor
venue: IEEE Transactions on Computers
year: 2013