Query: MOSFET METAL OXIDE

Candidate papers:

abstract: The invention provides a manufacturing method of an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, which is characterized by comprising the steps of forming a mask layer on a substrate; carrying out etching on the substrate by taking the mask layer as a mark, and simultaneously forming a first groove and a second groove; forming a first filling layer in the first groove, and forming a shielding layer on the first filling layer; carrying out etching on the second groove by taking the shielding layer and the mask layer as a mask so as to enable the depth of the second groove to increase to preset depth and form a third groove; and forming a second filling layer in the third groove. According to the manufacturing method of the MOSFET device, the first groove and the second groove are formed simultaneously, then etching is only carried out on the second groove so as to form the third groove, and thus a deep groove and a shallow groove are formed, so that influences imposed on the MOSFET device by photoetching alignment deviation can be avoided when the deep groove and the shallow groove are formed, the manufacturing process of the MOSFET device is optimized, the procedures are simplified, and the cost is reduced.
title: Manufacturing method of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device
year: 2015

abstract: The invention relates to a method for preparing a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) grid oxide layer and belongs to the field of a SiC MOSFET device. The method comprises the following steps: generating a SiO2 grid oxide layer on a SiC epitaxial layer; annealing the grid oxide layer in a C12 environment at a temperature ranging from 500 1000 DEG C, preferably 700 800 DEG C; introducing mixed gas of C12 and inert gas at a preferable rate of 0.5 2 slm, wherein the annealing pressure is 100 1000mbar, and the retention time is 30 180 min. According to the method, C12 is used for annealing a SiO2 grid medium layer, so that oxygen vacancy tapped charges in the grid medium SiO2 layer can be removed, and the critical breakdown electric field and the voltage endurance capability of the SiO2 grid medium layer in the SiC MOSFET device can be improved.
title: Method for preparing SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) grid oxide layer
year: 2015

abstract: The invention relates to the technical field of communication, in particular to an MOSFET (metal oxide semiconductor field effect transistor) bridge circuit. The MOSFET bridge circuit comprises a potential extraction circuit, an MOS (metal oxide semiconductor) tube drive circuit, a first PMOS (P channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N channel metal oxide semiconductor) tube and a second NMOS tube, wherein the potential extraction circuit is connected with the MOS tube drive circuit; the MOS tube drive circuit is respectively connected with the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube. The MOSFET bridge circuit provided by the invention is simple in structure; large scale mass production is easy to achieve; power consumption can be lowered; the calorific value can be reduced.
title: MOSFET (metal oxide semiconductor field effect transistor) bridge circuit
year: 2015

abstract: The invention provides an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided with a GeSn source and drain and a forming method thereof. The forming method comprises the following steps: providing a substrate of which the top is provided with a Ge layer; forming a gate stack or a fake gate on the substrate; forming openings of a source area and a drain area in both sides of the gate stack or the fake gate, and exposing the Ge layer out of the openings; injecting atoms, molecules, ions or plasmas containing Sn elements into the surface layer of the Ge layer, and forming a GeSn layer in the openings. By adopting the forming method of the MOSFET, a field effect transistor provided with the GeSn source and drain can be formed. Since the thicknesses of the GeSn source and drain are small, and the crystal quality is good, the transistor has high electric performance. Moreover, the method has the advantages of easiness, practicability and low cost.
title: MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided with GeSn source and drain and forming method thereof
year: 2014

abstract: The invention discloses a novel trench type MOSFET (metal oxide semiconductor field effect transistor) device and a manufacturing method thereof. A concave interface is formed between a body area and a semiconductor substrate, so that the part under source metal contact, of the body area is thinner than other parts of the body area. The most concave position E of the concave interface is positioned under the source metal contact so as to lead a reversed electric field to be gathered at the most concave position. A heavily doped region positioned under the source metal contact also can be formed in the body area so as to reduce the resistance. When the MOSFET is shut off, a reverse current is generated, flows through the heavily doped region from the most concave position and reaches the source metal contact, so that the influence of an equivalent parasitic transistor B on the shutoff of the MOSFET is reduced and the lower voltage drop is generated. In the novel trench type MOSFET device disclosed by the invention, the parasitic transistor is effectively controlled, and the UIS performance of the trench type MOSFET is improved.
title: Trench type MOSFET (metal oxide semiconductor field effect transistor) device
year: 2011

abstract: The invention provides a manufacturing method of an MOSFET (metal oxide semiconductor field effect transistor) The manufacturing method is characterized in that a sacrificial side wall of amorphous carbon is removed by adopting oxygen or carbon dioxide plasma oxidation method to form a side wall hole; and the dielectric constant of the side wall hole is 1 and is only one seventh of a silicon nitride side wall, so that the capacitance between the grid and a contact plug of a source drain region can be obviously reduced, and the speed and the switching power consumption performance of a short grid length MOSFET device can be effectively improved. The manufacturing method provided by the invention has the advantages that the process is simple, the cost is saved, the formed side wall cavity can exist permanently, and the service life of the device can be prolonged.
title: Manufacturing method of MOSFET (metal oxide semiconductor field effect transistor)
year: 2011

abstract: The invention discloses a semiconductor device comprising a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, and methods of manufacturing a MOSFET device. The MOSFET device comprises: a drain of a first doping type; a body of a second doping type, wherein the body is between the drain and a source; a gate above the body, wherein the source is at one side of the gate and the drain is at another side of the gate; and a recessed Field Oxide (recessed FOX) structure, wherein the recessed FOX structure is between the gate and a drift region vertically and wherein the recessed FOX structure is configured to make the drift region into a U shape. The structure increases the puncture voltage of the MOSFET, increases the electric density and has low cost.
title: Semiconductor device comprising MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device and methods of manufacturing MOSFET device
year: 2012

abstract: Disclosed is a high voltage MOSFET (metal oxide semiconductor field effect transistor) driving circuit which comprises a first high voltage switching circuit PMOSFET (positive metal oxide semiconductor field effect transistor) and a secondary high voltage switching circuit NMOSFET (negative metal oxide semiconductor field effect transistor) of a driving switch component and also comprises a first level displacement circuit, a secondary level displacement circuit, a first voltage distributing circuit, a secondary voltage distributing circuit, a first grid controlling circuit and a secondary grid controlling circuit; on main channels of the high voltage PMOSFET and the high voltage NMOSFET of the driving switch component, a voltage regulator diode is used for replacing an audion in the traditional high voltage MOSFET driving circuit, so that the static power consumption of the whole circuit is greatly reduced; and the voltage is directly distributed by a resistor, so as to ensure that the grid source interelectrode voltage between the high voltage PMOSFET and the high voltage NMOSFET of the driving switch component does not exceed the highest value of the grid source interelectrode voltage, therefore, the limit of the highest grid source interelectrode voltage is guaranteed, and the load regulation of the whole circuit can be effectively reduced.
title: High voltage MOSFET (metal oxide semiconductor field effect transistor) driving circuit
year: 2010

abstract: The invention discloses a method for producing a power MOSFET (metal oxide semiconductor field effect transistor) which comprises the following steps: respectively forming a drain region, a source region and a grid electrode of the power MOSFET; forming a grid contact hole of the grid electrode; and according to the depth of the grid contact hole, dividing the grid contact hole into at least two sections along the direction perpendicular to the drain region, and respectively etching each section so as to form the grid contact hole. The method provided by the invention has the advantage that the operation is simple; and through adjusting the proportional relationship between a first etching length and a second etching length, the balance between the power consumption and the etching effect is realized, which not only saves the energy sources and improves the production efficiency, but also improves yield and the reliability of and gate oxide.
title: Method for producing power MOSFET (metal oxide semiconductor field effect transistor)
year: 2010

abstract: OBJECTIVES The objective of this study was to compare the performance of metal oxide semiconductor field effect transistor (MOSFET) technology dosemeters with thermoluminescent dosemeters (TLDs) (TLD 100; Thermo Fisher Scientific, Waltham, MA) in the maxillofacial area. METHODS Organ and effective dose measurements were performed using 40 TLD and 20 MOSFET dosemeters that were alternately placed in 20 different locations in 1 anthropomorphic RANDO((r) head phantom (the Phantom Laboratory, Salem, NY) The phantom was exposed to four different CBCT default maxillofacial protocols using small (4 x 5 cm) to full face (20 x 17 cm) fields of view (FOVs) RESULTS The TLD effective doses ranged between 7.0 and 158.0 uSv and the MOSFET doses between 6.1 and 175.0 uSv. The MOSFET and TLD effective doses acquired using four different (FOV) protocols were as follows: face maxillofacial (FOV 20 x 17 cm) (MOSFET, 83.4 uSv; TLD, 87.6 uSv; 5% teeth, upper jaw (FOV, 8.5 x 5.0 cm) (MOSFET, 6.1 uSv; TLD, 7.0 uSv; 14% tooth, mandible and left molar (FOV, 4 x 5 cm) (MOSFET, 10.3 uSv; TLD, 12.3 uSv; 16% and teeth, both jaws (FOV, 10 x 10 cm) (MOSFET, 175 uSv; TLD, 158 uSv; +11% The largest variation in organ and effective dose was recorded in the small FOV protocols. CONCLUSIONS Taking into account the uncertainties of both measurement methods and the results of the statistical analysis, the effective doses acquired using MOSFET dosemeters were found to be in good agreement with those obtained using TLD dosemeters. The MOSFET dosemeters constitute a feasible alternative for TLDs for the effective dose assessment of CBCT devices in the maxillofacial region.
author_names: Juha Koivisto

Dirk Schulze

Jan Wolff

Dennis Rottke
title: Effective dose assessment in the maxillofacial region using thermoluminescent (TLD) and metal oxide semiconductor field effect transistor (MOSFET) dosemeters: a comparative study.
venue: Dento maxillo facial radiology
year: 2014