Query: High Gain and  Fully Differential  as Current 

Candidate papers:

abstract: A current sense amplifier (CSA) based on a fully differential difference amplifier (FDDA) is introduced. A prototype was manufactured in a 0.18 <inline formula> <tex math notation="LaTeX"\mu \text{m} /tex math>/inline formula> bipolar, CMOS, DMOS (BCD) technology of Taiwan Semiconductor Manufacturing Company, Limited (TSMC) and characterized. The FDDA architecture offers several benefits regarding gain, bandwidth (BW) and noise performance and is well suited for low side phase current measurement (PCM) in modern electric engines. To achieve a high gain accuracy, an integrated resistive feedback, which offers a low frequency gain of more than 46 dB with a gain error of less than 1% and a 3 dB BW of approximately 2 MHz simulated and confirmed by measurements, is used. Hence, the circuit offers a higher measurement speed and sensitivity than the current state of the art devices. Furthermore, the manual offset reduction allows for an input offset in the low microvolt range, and the input referred noise is reduced to an input noise voltage of less than <inline formula> <tex math notation="LaTeX"$30~\mu \text{V} /tex math>/inline formula> (rms) and a noise floor of <inline formula> <tex math notation="LaTeX"{13}\mathrm {nV} \surd \mathbf {Hz} /tex math>/inline formula> (above 30 kHz) This article describes the design including the top level structure, the distinct gain stages, the common mode feedback (CMFB) and the output buffer amplifier of the CSA in detail. Finally, a measurement with a noisy rectangular 1 mV, 500 kHz signal proves the great potential of the amplifier for low side PCM which is further compared with the state of the art commercial products and research results.
author_names: Christian D Matthus

Simon Buhr

Martin Kreissig

Frank Ellinger
title: High Gain and High Bandwidth Fully Differential Difference Amplifier as Current Sense Amplifier
venue: IEEE Transactions on Instrumentation and Measurement
year: 2021

abstract: Abstract This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low voltage low power applications. Unlike the conventional FB DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple input bulk driven MOS transistor (MI BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail to rail input common mode range (ICMR) high common mode rejection ratio (CMRR) of 100.3 dB DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 um CMOS process from TSMC.
author_names: Fabian Khateb

Tomasz Kulej

Montree Kumngern

Costas Psychalinos
title: A compact power efficient 0.5 V fully differential difference amplifier
venue: AEU International Journal of Electronics and Communications
year: 2019

abstract: A programmable gain amplifier (PGA) is presented, targeting amplifying input signal with high dynamic range and low noise. The proposed PGA adopts fully balanced differential difference amplifier (FBDDA) as main amplifier. A class AB implementation of output stage is advantageous in order to achieve high current driving capability with very low quiescent power consumption. Combining resistor feedback loop controlled by digital signal, the proposed PGA achieves a dB linear gain range from 0 to 15dB with a gain step of 1dB. Compared with previous works, the theoretical analysis and measurement results prove that the proposed structure has lower noise. The circuit was designed and fabricated in SMIC 0.18m 3.3V process, showing a gain error of less than 0.25dB, a third harmonic distortion (HD3) of better than 83dB and a thermal noise of 1.6 nv/Hz. The measurement results indicate that the PGA described here has a 3dB bandwidth of 387.5MHz at maximum gain of 15dB. The PGA occupies a chip area of 0.1mm2.
author_names: Jingyu Wang

Zhangming Zhu

Shubin Liu

Ruixue Ding
title: A low noise programmable gain amplifier with fully balanced differential difference amplifier and class AB output stage
venue: Microelectron. J.
year: 2017

abstract: Abstract A new current mode Wheatstone bridge (CMWB) using a new fully differential operational transresistance amplifier (FDOTRA) is presented in this paper. This proposed FDOTRA is an active element for the proposed CMWB and has the advantages of low input and output impedances, input voltage calibration, high transimpedance (Rm) large input range, and wide bandwidth. The proposed CMWB uses only one active component FDOTRA and four resistors without degrading CMWB performance. The proposed CMWB has a simple structure, high precision, wide range, small volume, and low cost. Therefore, the advantages of the proposed CMWB are twofold. Firstly, it reduces the number of sensing passive and active elements. Secondly, the proposed CMWB circuit offers a significant improvement in accuracy compared to other CMWB integrated circuit (IC) The proposed CMWB has been analyzed, simulated, and implemented. The proposed FDOTRA has been fabricated with TSMC 0.35 mm 2P4M CMOS processes. Its supply voltages are 1.65 V. The open loop gain and 3 dB bandwidth of the proposed FDOTRA are 69.2 dB and 16 MHz, respectively. The open loop gain and 3 dB bandwidth of the FDOTRA based CMWB are 24.6 dB and 16 MHz, respectively. The experimental results show that the precision of the FDOTRA based CMWB is 92.4%
author_names: Yitsen Ku

Yuh-Shyan Hwang

Jiann-Jong Chen

Chun-Chi Shih

D Cheng
title: A new current mode wheatstone bridge based on a new fully differential operational transresistance amplifier
venue: AEU International Journal of Electronics and Communications
year: 2019

abstract: This paper presents a high CMRR and wideband current feedback Instrumentation Amplifier (IA) The proposed IA architecture consists of Fully Balanced Differential Difference Amplifier (FBDDA) and Differential Difference Amplifier (DDA) based on 2 generation current conveyor (CCII) with a buffer. From the simulation results evaluated by HSPICE, the proposed IA exhibits average CMRR was 109.3 dB higher than the conventional one. Furthermore, the proposed IA has higher closed loop gain over a larger bandwidth than corresponding voltage feedback.
author_names: Shota Mago

Hiroki Tamura

Koichi Tanno
title: High CMRR and Wideband Current Feedback Instrumentation Amplifier Using Current Conveyors
year: 2017

abstract: A micropower high gain, low noise differential difference amplifier (DDA) is presented in this paper. The new circuit incorporates the gate bulk driven transistor pairs for input stage transconductance enhancement; the very high gain folded telescopic cascode structure that permits small headroom operation; and the replica tracking bias that sustains the circuit performance against variations of process, supply voltage and temperature. The DDA is designed using Global Foundries 1.8V/3.3V CMOS 0.18um process and simulated using the BSIM3 models. The simulated results for the DDA shows DC gain of 131.4dB and unity gain bandwidth of 1.097 MHz at a load of 30pF//200kO while consuming quiescent current of 10.7uA at a single 1.8V supply. The proposed DDA gives noise reduction of 15.56% with respect to that of the gate driven counterpart. It gives a noise efficiency factor (NEF) [1] of 6.7 when realizing a bio potential sensing circuit. The low noise, very high gain, floating inputs, low power and robust features of the proposed DDA are suitable for front end interface circuit in sensory systems.
author_names: Geok Teng Ong

Pak Kwong Chan
title: A micropower gate bulk driven differential difference amplifier with folded telescopic cascode topology for sensor applications
venue: 2010 53rd IEEE International Midwest Symposium on Circuits and Systems
year: 2010

abstract: An improved operational transconductance amplifier (OTA) is presented in this work. The fully differential OTA adopts the current recycling technique and complementary NMOS and PMOS input branches to enhance the total transconductance. Moreover, in order to achieve higher current efficiency, a data driven biasing circuit was developed to dynamically adjust the power consumption of the amplifier. Two comparators were added to detect the voltage difference at the input nodes, and when the differential input is large enough to activate either comparator, extra biasing current is activated and poured into the amplifier to enhance its slew rate and gain bandwidth product (GBW) The threshold voltage of the complementary recycling folded cascode (CRFC) based comparator is configured to suppress overshoot. Complementary common mode feedback (CMFB) topology with local CMFB structure is built to acquire high common mode gain. The OTA was fabricated in SMIC 0.18 m m CMOS technology. The experimental result based on a capacitive feedback loop shows that the data driven operation improves the average slew rate of the amplifier from 10.2 V/ m s to 55.5 V/ m s while the power only increases by 150% The OTA has good potential to satisfy the fast settling demands for capacitive sensing circuits.
author_names: Xiantao Li

Bo Hou

Chunge Ju

Qi Wei

Bin Zhou

Rong Zhang
title: A Complementary Recycling Operational Transconductance Amplifier with Data Driven Enhancement of Transconductance
year: 2019

abstract: A new modified CMOS buffer amplifier with rail to rail input and output range is proposed by TSMC 0.35mm 2P4M process at 3.3V supply. The technique adds dummy pairs to sense the common mode range of the input differential pair and adjusts the output current accordingly. The amplifier provides high gain for a wider range of output voltages. Design considerations for reducing the impact of the additional circuitry on the core are provided. The technique described can be adapted for use with traditional fully differential rail to rail amplifiers, which performs 86.9dB ~92dB dc gain, 15 MHz unit gain bandwidth, high driving ability with high slew rate under a 100pF capacitance and a 3kO series resistance loading. The simulation results indicate that the settling times of rising and falling edge are within 3.5ms. It is effective for a high resolution and high speed LCD driver.
author_names: Shih-Han Lin

Shu-Jung Chen

Chih-Hsiung Shen
title: A New Architecture of LCD Driver of Rail to Rail Buffer with High Gain Wide Range
year: 2010

abstract: In this article, we propose a novel high performance complementary metal oxide semiconductor (CMOS) current differencing transconductance amplifier (CDTA) with a transconductance gain (GM) that can be linearly tuned by a voltage. By using a high speed, low voltage, cascaded current mirror active resistance compensation technique, the proposed CDTA circuit exhibits wide frequency bandwidths, high current tracking precisions as well as large output impedances. The linear tunable GM of the CDTA is designed with the use of linear composite metal oxide semiconductor field effect transistor as basic cells in the circuit. Combining these two approaches, several design concerns are studied, including: impedance characteristic, tracking errors, offset and linearity and noise. The prototype chip with a 0.25 mm2 area is fabricated in a GlobalFoundries'0.18 mm CMOS process. The simulated results and measured results with 0.8 V DC supply voltages are presented, and show extremely wide bandwidths and wide linear tuning range. In addition, a fully differential band pass filter for a high speed system is also given as an example to confirm the high performance of the proposed circuit.
author_names: Zanming Xia

Chunhua Wang

Jun Kuang

Jie Jin
title: A novel 0.8 V high performance voltage tunable CDTA with enhanced bandwidth
year: 2016

abstract: In this paper we present an optoelectronic architecture based on a current mode photodiode bridge readout circuit that performs differential measurements of the energy variations of nanosecond laser pulses. This operation is achieved by differentially detecting the currents photogenerated by two Si photodiodes one of which is used as the reference signal and the other measures the signal coming from variations of the laser pulse energy. The circuit has been designed for high speed operations (i.e. large bandwidth) and its features can be simply optimised as a function of the laser pulse width (e.g. in the nanosecond and subnanosecond regime) and of its repetition rate from few Hz up to few MHz. Moreover, the electronic circuitry allows to achieve the initial photodiode bridge balancing condition by variable control voltages so zeroing the overall interface offsets due to optical and electronic device mismatches and initial bridge unbalance conditions. The readout circuit has been fully characterised by performing both electrical and optical measurements and by varying its gain, detection sensitivity and energy per pulse changes between the signal and the reference employing 10ns laser pulses at a repetition rate of 20Hz. These measurements have been compared with those ones obtained using a standard commercial lock in amplifier as the conditioning circuit under the same experimental conditions. The proposed optoelectronic architecture is able to reach a maximum detection sensitivity of 7m V/ fJ corresponding to a detection resolution of the laser pulse energy variations equal to 0.14x10 3 fJ. These results prove an increase of 1225 in the detection sensitivity and resolution obtained by employing a lock in amplifier in a differential measurement configuration.
author_names: Andrea De Marcellis

Elia Palange

Simona Leone

Guido Di Patrizio Stanchieri

Marco Faccio
title: Photodiode Bridge Based Differential Readout Circuit for High Sensitivity Measurements of Energy Variations of Laser Pulses for Optoelectronic Sensing Systems
venue: 2018 New Generation of CAS (NGCAS)
year: 2018