Query: analogue memristor

Candidate papers:

abstract: Reinforcement learning algorithms that use deep neural networks are a promising approach for the development of machines that can acquire knowledge and solve problems without human input or supervision. At present, however, these algorithms are implemented in software running on relatively standard complementary metal oxide semiconductor digital platforms, where performance will be constrained by the limits of Moore's law and von Neumann architecture. Here, we report an experimental demonstration of reinforcement learning on a three layer 1 transistor 1 memristor (1T1R) network using a modified learning algorithm tailored for our hybrid analogue digital platform. To illustrate the capabilities of our approach in robust in situ training without the need for a model, we performed two classic control problems: the cart pole and mountain car simulations. We also show that, compared with conventional digital systems in real world reinforcement learning tasks, our hybrid analogue digital computing system has the potential to achieve a significant boost in speed and energy efficiency.A reinforcement learning algorithm can be implemented on a hybrid analogue digital platform based on memristive arrays for parallel and energy efficient in situ training.
author_names: Zhongrui Wang

Can Li

Wenhao Song

Mingyi Rao

Daniel Belkin

Yunning Li

Peng Yan

Hao Jiang

Peng Lin

Miao Hu

John Paul Strachan

Ning Ge

Mark D Barnell

Qing Liang Wu

Andrew G Barto

Qinru Qiu

R Stanley Williams

Qiangfei Xia

J Joshua Yang
title: Reinforcement learning with analogue memristor arrays
venue: Nature Electronics
year: 2019

abstract: A memristor with a bilayer electrolyte structure (Pt/C/NbOx/TiN) is proposed as a self rectification and quasi linear electronic synapse. The device shows self rectifying analogue memristive behavior with 106 rectification ratio, which can solve the sneak current problem in crossbar array without additional hardware burden. Under identical pulses in potentiation process, the device conductance is quasi linearly changed with 9.16% nonlinearity. In addition, the conductance change rate of device is effectively tuned by altering amplitudes and frequencies of spike pulses. Benefiting from the quasi linear conductance change characteristics, excellent classification accuracy (95.7% is achieved for the application of handwritten digit classification with a two layer perceptron based on MINST stimulation.
author_names: Weilong Wang

Rui Wang

Tuo Shi

Jinsong Wei

Rongrong Cao

Xiaolong Zhao

Zuheng Wu

Xumeng Zhang

Jian Lu

Hui Xu

Qingjiang Li

Qi Liu

Ming Liu
title: A Self Rectification and Quasi Linear Analogue Memristor for Artificial Neural Networks
venue: IEEE Electron Device Letters
year: 2019

abstract: A report is presented on the operation of an analogue programming circuit for accurately setting the state of a memristor. The circuit exploits the dynamic modulation of resistance under a constant DC bias while real time measurements of the memristance are performed using an AC signal. The circuit employs feedback for converging the state of a device at any required level within a decade. This allows the memristor to act as an analogue potentiometer, with its resistance corresponding to an input analogue voltage. This implementation was tested with the HP memristor model revealing an accuracy of less than 0.4% (8 bit precision) in relation to the full dynamic range.
author_names: Radu Berdan

Themistoklis Prodromakis

Christofer Toumazou
title: High precision analogue memristor state tuning
year: 2012

abstract: Memristor crossbars offer reconfigurable non volatile resistance states and could remove the speed and energy efficiency bottleneck in vector matrix multiplication, a core computing task in signal and image processing. Using such systems to multiply an analogue voltage amplitude vector by an analogue conductance matrix at a reasonably large scale has, however, proved challenging due to difficulties in device engineering and array integration. Here we show that reconfigurable memristor crossbars composed of hafnium oxide memristors on top of metal oxide semiconductor transistors are capable of analogue vector matrix multiplication with array sizes of up to 128 x 64 cells. Our output precision (5 8 bits, depending on the array size) is the result of high device yield (99.8% and the multilevel, stable states of the memristors, while the linear device current voltage characteristics and low wire resistance between cells leads to high accuracy. With the large memristor crossbars, we demonstrate signal processing, image compression and convolutional filtering, which are expected to be important applications in the development of the Internet of Things (IoT) and edge computing.MainMemristor crossbars with array sizes of up to 128 x 64 cells are capable of analogue vector matrix multiplication and can be used for signal processing, image compression and convolutional filtering.
author_names: Can Li

Miao Hu

Yunning Li

Hao Jiang

Ning Ge

Eric Montgomery

Jiaming Zhang

Wenhao Song

Noraica Davila

Catherine E Graves

Zhiyong Li

John Paul Strachan

Peng Lin

Zhongrui Wang

Mark D Barnell

Qing Wu

R Stanley Williams

Jianhua Joshua Yang

Qiangfei Xia
title: Analogue signal and image processing with large memristor crossbars
year: 2018

abstract: An important cornerstone of data processing is the ability to efficiently capture structure in data and perform data classification. More recently, memristive technologies enabled the incorporation of continuous tuneable resistive elements directly in hardware, thus increasing the efficiency of reconfigurable systems power and area wise. Memristors are a promising candidate for reconfigurable circuits capable of carrying out classification with physical computing, such as dot product vector multiplication and accumulation technique. In this work, we demonstrate a novel proof of concept memristor based Digital In Analogue Out logic circuit and present preliminary results highlighting the effect of non uniform non linear memristor IV characteristics that result in device to device behavioural variation.
author_names: Georgios Papandroulidakis

Loukas Michalas

Alexantrou Serb

Ali Khiat

Geoff V Merrett

Themistoklis Prodromakis
title: A Digital In Analogue Out Logic Gate Based on Metal Oxide Memristor Devices
venue: 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
year: 2019

abstract: An important aspect for implementing neuro inspired circuits and systems is the data pattern recognition and classification circuits. Memristor is one of the most prominent emerging technology to take effectively the place of synaptic weights, in neuro inspired techniques such as Threshold Logic (TL) [1] by showcasing continuously tunable resistance capabilities [2] The design and experimental validation of such circuits, by taking into consideration the practical non linearities of the memristor components, is worth investigating. The introduction of Digital InAnalogue Out (DI AO) memristive TL will enable us to complete the picture of the available circuit modalities that can process information using memristors, by additionally taking into consideration the more conventional digital [3] analogue [4] and Analogue In Digital Out (AI DO) memristor based logic families [1] In this work, a DI AO method of performing reconfigurable memristor based TL is proposed and experimentally validated using real memristor devices and incorporating 1T1R based mixed signal circuit modalities, to compute physically (Kirchhoff's law at the intermediate node) the comparison between two adverse dot products, one pulling towards VDD and the other pulling down to GND (see Fig.1) Hence, the computation is equivalent to a digital in (MOS gate control) analogue out (readout voltage from the intermediate node) TL operation. The circuit performs the TL operation physically in the form of distance of the readout circuit response from VDD/2 voltage level. An example of the experimental validation of the circuit is presented in Fig. 2, where the pull up (PU) pMOS and pull down (PD) nMOS vectors are defined as {Ip11, Ip12, Ip13} and {In21, In22} respectively. The memristor weights [2] used for this configuration are configured as{5.5kO, 10.8kO, 11.5kO} and {7.3kO, 6kO} for the PU and the PD arrays, respectively.
author_names: Georgios Papandroulidakis

Alexantrou Serb

Ali Khiat

Geoff V Merrett

Themistoklis Prodromakis
title: Practical implementation of digital in analogue out memristor based threshold logic circuit
year: 2019

author_names: Takuya Ashida

Tetsuhito Shinohara

Minoru Ohta

Kuniyasu Ito

Shogo Yamada

Shibata Tatsuo

Yukio Terasaki

Tomoyuki Sasaki
title: Domain Wall Type Spin Memristor for Analogue Neuromorphic Devices
year: 2019

abstract: The data processing efficiency of traditional computers is suffering from the intrinsic limitation of physically separated processing and memory units. Logic in memory and brain inspired neuromorphic computing are promising in memory computing paradigms for improving the computing efficiency and avoiding high power consumption caused by extra data movement. However, memristors that can conduct digital memcomputing and neuromorphic computing simultaneously are limited by the difference in the information form between digital data and analogue data. In order to solve this problem, this paper proposes a flexible low dimensional memristor based on boron nitride (BN) which has ultralow power non volatile memory characteristic, reliable digital memcomputing capabilities, and integrated ultrafast neuromorphic computing capabilities in a single in situ computing system. The logic in memory basis, including FALSE, material implication (IMP) and NAND, are implemented successfully. The power consumption of the proposed memristor per synaptic event (198 fJ) can be as low as biology (fJ level) and the response time (1 ms) of the neuromorphic computing is four orders of magnitude shorter than that of the human brain (10 ms) paving the way for wearable ultrahigh efficient next generation in memory computing architectures.
author_names: Jia-Lin Meng

Tian-Yu Wang

He Zhenyu

Lin Chen

Hao Zhu

Li Ji

Qingqing Sun

S J Ding

Wenzhong Bao

Pengcheng Zhou

David-Wei Zhang
title: Flexible boron nitride based memristor for in situ digital and analogue neuromorphic computing applications
year: 2021

author_names: Francesco Marrone
title: Memristor Oscillators for Bio Inspired Analogue Computing
year: 2018

abstract: The theory of memristor was postulated in the year of 1971 by Leon O. Chua. The intensive interest on memristive systems is given by the researchers since after the physical realization of the hysteresis behavior in a nanoscale TiO\(_{\mathrm {2} memristor in 2008 by a group of researchers at HP Labs lead by Stanley Williams. Research on memristive systems has been carried out on various capacities such as understanding the mathematics of memristor, finding new materials which have memristive properties, studying the underlying dynamics of memristive systems and revisiting the existing concepts with memristor as a nonlinear element. As a result, memristors have potential applications in various domains. It ranges from neural networks, memory devices, artificial intelligence, high speed computing, nano batteries and human skin modeling, etc. In the recent times, much attention is given to explore the nonlinear dynamics of memristor based circuits. In this chapter, we consider a smooth continuous cubic memristor as nonlinear element. It is applied to (a) an autonomous and (b) a non autonomous dynamical systems namely, the Chua's circuit and Duffing Oscillator, to study the associated dynamics of these systems. The numerical simulation of the circuit systems as well as its hardware experimental studies are performed in the laboratory. An inductor free realization and volume expanded period doubling scenario in a memristive Chua's circuit is studied. The complex behaviors, like, bifurcations and chaos, three tori, transient chaos and intermittency in a memristive Duffing oscillator are described. In addition, "0 1 test" for the experimental time series data characterizing the regular and chaotic dynamics of the proposed circuits are also discussed.
author_names: R Jothimurugan

S Sabarathinam

K Suresh

Kathamuthu Thamilmaran
title: Experimental Analogue Implementation of Memristor Based Chaotic Oscillators
year: 2017