Query: Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

Candidate papers:

abstract: A post linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive channel metal oxide semiconductor field effect transistor for sinking the third order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18 /spl mu/m technology. The LNA achieved +13.3 dBm IIP3 with 12.8 dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8 V supply.
author_names: Tae-Sung Kim

Byung-Sung Kim
title: Post linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker
year: 2006

abstract: A post linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive channel metal oxide semiconductor field effect transistor for sinking the third order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18 /spl mu/m technology. The LNA achieved +13.3 dBm IIP3 with 12.8 dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8 V supply.
title: Post linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker
venue: IEEE Microwave and Wireless Components Letters
year: 2006

abstract: A highly linear 5.5 GHz low noise amplifier (LNA) has been designed exploiting source inductive degeneration topology by using post distortion linearization techniques in 0.18 m CMOS technology. This technique improves the input third order intercept point (IIP_{3}(IIP3) of a low noise amplifier. For enhancing the linearity, this technique used a diode connected MOSFET as IMD sinker and forward body biased which is done in cadence tool. The proposed low noise amplifier achieves high $IIP_{3}$IIP3 by using two transistors, main and auxiliary transistors. Also source inductive degeneration topology is employed in the proposed LNA to optimize the noise figure (NF) and $S_{11}$S11 at high frequency. In order to reduce power consumption and threshold voltage, Forward Body Biased technique was implemented. In this paper, the first section discusses the most widely used eight linearization techniques and in the second section, the proposed circuit is represented along with its employed topology, techniques and the simulated results. The proposed LNA achieves a simulated third order input intercept (IIP_{3}(IIP3) of 9.20 dBm while consuming 10.8 mW from a power supply of 1.8 V. it also exhibits a measured gain of 11.34 dB and NF, NF of 2.33 dB.
author_names: Ram Kumar

Anandini Devi

Abahan Sarkar

Fazal Ahmed Talukdar
title: Design of 5.5 GHz linear low noise amplifier using post distortion technique with body biasing
year: 2016

abstract: A fully integrated 5.5GHz high linearity low noise amplifler (LNA) using post linearization technique, implemented in a 0.18"m RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise flgure (NF) and power consumption. The LNA achieves an input third order intercept point (IIP3) of +8:33dBm, a power gain of 10.02dB, and a NF of 3.05dB at 5.5GHz biased at 6mA from a 1.8V power supply.
author_names: Chieh-Pin Chang

Wei-Chih Chien

Chun-Chi Su

Yeong-Her Wang

Ja-Hao Chen
title: Linearity improvement of cascode CMOS LNA using a diode connected NMOS transistor with a parallel RC circuit
year: 2010

abstract: A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 mm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF) The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third Order Intercept Point (IIP3) of 3dBm. Keywords 0.18mm CMOS technology, Boosting inductors, Gain, Linearity, Partial source degeneration PSD, Radio frequency identification RFID.
author_names: Zaid Albataineh

Yazan Hamadeh

Jafar Moheidat

Ahmad Dagamseh

Idrees S Al-Kofahi

Mohammed O Alsumady
title: A High Gain Low Noise Amplifier for RFID Front Ends Reader
year: 2017

abstract: In this paper presents a optimization of linearity of low noise amplifier by using post linearization techniques. in this technique we have used diode connected mosfet as IMD sinker also used interstage matching for gain enhancement and reducing the effect of nonlinearity in common gate stage of cascode amplifier, this has done by using UMC .18um CMOS Technology in cadence tool. We got gain 14dB, noise figure 2.1dB, IIP3 3.19dBm with power supply of 1.8v, and power consumption is 10.8mw.
author_names: Ram Kumar

Jitendra Kumar Mishra
title: A low noise amplifier with improved linearity and high gain
year: 2013

abstract: A 5GHz Low Noise Amplifier (LNA) is presented using the folded cascode topology which is suitable for low voltage Radio Frequency Identification (RFID) applications. It employs both NMOS and PMOS devices to reduce the required supply voltage to less than 1V. The circuit is fully integrated on chip, with inductors implemented using stacked spirals to save space. It is experimentally demonstrated in 0.18mm CMOS and performs particularly well at 5GHz, with the noise figure being below 3dB. The gain and input 1dB compression point exceed 12dB and 11.5dBm respectively, while the input return loss is better than 20dB. The LNA has an active footprint of only 575mm by 525mm, and consumes less than 10mW from a 1V supply.
author_names: Ahmed M El-Gabaly

Carlos E Saavedra
title: A Low Voltage Fully Integrated 5 GHz Low Noise Amplifier in 0 18 m m CMOS
year: 2008

abstract: This work describes a 0.5 mm CMOS implementation of a Folded Cascode OTA designed for minimum Input Referred Noise for non implantable EEG SoC arrays. It is also described a small area PID feedback network using a high resistive pMOS pseudo resistor and small integration capacitances for programmable gain control throughout parasitic insensitive nMOS switches. Simulation results show that it achieves about 2.2 mVrms of input referred noise for 6 mA of total current at 1.8 V supply voltage. The circuit provides a NEF of 4.55 within a 1.96 kHz bandwidth and midband gain of 40.22 dB.
author_names: Odilon de Oliveira Dutra

T Pimenta
title: Low Power Low Noise Neural Amplifier with Adjustable Gain
venue: 2012 IEEE Ninth Electronics, Robotics and Automotive Mechanics Conference
year: 2012

abstract: High resolution high speed comparators are one of the main cores in the implementation of the high performance systems, such as ADCs. Two comparators are presented in this paper where both of the structures are suitable for high speed, low noise and accurate applications. The comparators are designed, based on the positive feedback structure of two back to back inverters. An improved rail to rail folded cascode amplifier with an active bias circuit is utilized for the first architecture, in which the structure of the comparator is rearranged appropriate to the running comparison phase. Distinguished by its novel data reception style, a new comparator is proposed in the next circuit. In this structure, the hot n well concept is considered for the PMOS transistors of the positive feedback latch. Applying the inputs to the bulks of the mentioned PMOS devices, isolates the regenerative outputs from the input signals; hence, a sizable attenuation in the kickback noise value is resulted. Merging the reset, evaluation and latch sequences makes it possible to decrease the comparison duration. Both of the proposed comparators of this paper benefits from this excellence, therefore an intensive increase is observed in their comparison speed. In order to confirm the performance accuracy of the circuits in various terms, multiple simulations are performed in all process corners, using HSPICE (level49) with a standard 0.35mm CMOS process and the power supply of 3.3V. VDD noise of 300mVp p and alterations in temperature are also included in the simulation conditions. The simulation results confirm recognition of a differential input with 2mV pick to pick amplitude at as high a clock frequency as 800MHz with power consumption about 2.6mW for the first circuit and a 1mV differential input with update rate of 1GHz and power consumption about 1.6mW for the low noise structure of the second comparator. According to the layout pattern, an active area of 55mm x 13mm and 24mm x 15mm is occupied by the improved folded cascode comparator and the proposed novel structure respectively.
author_names: Ali Baradaran Rezaeii

Obalit Shino

Tohid Moradi
title: Low Kickback Noise Preamplifier Latched Comparators Designed for High Speed Accurate ADCs
year: 2015

abstract: The charge sensitive amplifier (CSA) unit is used in processing signals from capacitive sensors such as photo detectors, pressure sensors, particle and X ray detectors. Next generation front end ASICs will use advanced CMOS and BiCMOS technologies including MOSFETs with minimum channel length (of 45 nm and below) and SiGe Heterojunction Bipolar Transistors (HBTs) The most common CSA architecture employed either in CMOS or BiCMOS implementations is the folded cascode amplifying topology due to its low noise performance, the high gain capability and its gain insensitivity to the detector capacitance variations [1] [4] While noise optimization methodologies have been proposed for both kinds of CSAs (CMOS or BiCMOS) and plenty of CSA designs were so far presented [1] [5] none extended research has been performed about the suitability of each process in relation to the application specifications such as detector capacitance, power consumption, noise performance and speed. In addition, other important issues like the main noise contributors and the radiation hardness capability are also not have been extensively addressed. Particularly, four equivalent folded cascode amplifying topologies were designed. The primary concern was the examination of devices noise contribution, firstly the input transitor and cascoded one and secondary the reset device noise contribution. The four structures were: a) nMOS as the input and pMOS as cascode, b) pMOS as input, nMOS as cascode, c) npn BJT as input, pMOS as cascode and d) pMOS as input and npn BJT as cascode. To further isolate these noise contributors, ideal bias current sources and output buffer were used, in all four designs. Feedback was implemented using a capacitance in parallel with a large reset resistor. The structures were designed using specific noise optimization criteria design methodologies [1] [5] [6] in two respective processes commercially available by Austria Mikro Systeme (AMS) the 0.35mm CMOS process (2P/3M 3.3/5V) and the 0.35mm SiGe BiCMOS process (2P/3M 3.3/5V) All four folded cascode topologies are depicted in figure 1.
author_names: Thomas Noulis

George Fikos

Stylianos Siskos

Gerard Sarrabayrouse
title: Folded Cascode Amplifying Structure Evaluation in terms of the used IC process in Radiation Detection Front End Applications
year: 2009