Query: flash adc 4 bit

Candidate papers:

abstract: This study describes the highly digital 4 bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time to market and is scalable with technology. The comparators used in the ADC consist of complementary metal oxide semiconductor (CMOS) based inverter and NAND NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal to noise and distortion ratio, signal to noise ratio and spurious free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non linearity (DNL) of this ADC is 0.25 LSB and integral non linearity (INL) is 0.6 LSB.
author_names: Ashima Gupta

Anil Singh

Alpana Agarwal
title: Highly digital voltage scalable 4 bit flash ADC
venue: IET Circuits Devices Syst.
year: 2019

abstract: In this work a high speed flash ADC based on threshold invert quantization (TIQ) comparator has been proposed. Unlike conventional ADC resistive ladder and comparator bank has been replaced by TIQ comparator which compares the varying input with in built switching potential, 2n 1 number of TIQ requires with different switching for n bit ADC. 4 bit flash ADC has been implemented with static and dynamic TIQ; Different threshold of static TIQ is obtained by scaling the width of PMOS and NMOS individually while in dynamic TIQ input to each inverting stage acts as body voltage decide threshold voltage dynamically, threshold of TIQ is function of individual MOS width and body potential. Cadence Spectre based simulation result show that static TIQ should preferred for low power and dynamic TIQ for high speed.
author_names: Abhishek Kumar
title: Design of 4 Bit Flash ADC Using Static and Dynamic TIQ Comparator
year: 2019

abstract: Nowadays, there is the highest use of converters in the industries. The degradation of power consumption by these converters has great importance. This paper represents a new method to decrease the power consumption of the flash type analog to digital converter with 250 nm CMOS technology by using frequency which is of 1MHz. Flash type ADC requires 2 1 Comparator and its power supply voltage 2.5V. The proposed design of ADC using the Quantum Voltage Comparator eliminates the resistor ladder circuit and improves linearity of ADC. For the encoding process, the Pseudo logic encoder has been used and it provides higher data conversion rate and maintain low power consumption. The proposed 4 bit flash ADC paper having 876 MSPS speed and optimized power consumption by using the pseudo logic encoder and Quantum Voltage Comparator.
author_names: Sarang S Karale

Dhanashri M Hogale
title: Design of 876 MSPS, 2.5v, 250nm, 4 Bit Flash ADC using Quantum Voltage Comparator and Pseudo Logic Encoder
year: 2019

abstract: In this paper design of low power 4 bit Flash ADC for high frequency applications is presented. The power consumption of the Flash ADC in this work has been reduced in two phase. In the first phase a low power dynamic comparator has been designed which consumes 329.332 uW power. In the second phase a low power Fat tree encoder has been designed. The proposed encoder design uses reduced number of gates than the conventional design. As a result the average power dissipation of the encoder block is 43.6uw. The above mentioned Flash ADC is designed using CMOS 90nm Technology in Cadence tool. The proposed design has a power consumption of 5.1096 mW at IV power supply and at a sampling frequency of 1GHz.
author_names: David Sundararaj Shylu

S Radha

P Sam Paul

Parakati Sarah Sudeepa
title: Design of low power 4 bit Flash ADC in 90nm CMOS Process
venue: 2019 2nd International Conference on Signal Processing and Communication (ICSPC)
year: 2019

abstract: This paper presents the design of 4 bit flash type analog to digital converter implemented in 22 nm FD SOI technology with 0.8 V supply voltage. This block is part of original sub ranging ADC whose working principle is based on the assumption that sub ADC and sub DAC exhibit high linearity while they nominal resolutions remain relatively low. The linearity of the presented flash ADC has to be as high as in case of 8 bit converter. Thus, the most challenging task was to design comparator with resolution of 1.5 mV. This goal was reached owing to ability offered by the FD SOI process to trim transistor's threshold voltage by means of modulating the back gate polarization. The resulting sampling rate is 500 Ms/s.
author_names: Zbigniew Jaworski
title: Highly Linear 4 bit Flash ADC Implemented in 22 nm FD SOI Process
venue: 2019 MIXDES 26th International Conference "Mixed Design of Integrated Circuits and Systems"
year: 2019

abstract: This article describes a design of 4 bit Flash analogue digital converter (ADC) for Ultra Wideband (UWB) sensor systems. The ADC cell structure was designed and fabricated in 0.35 um SiGe BiCMOS technology. Proposed ADC cell achieves up to 1.1 Gs/s with maximum input signal range 1.6 Vpp at 1 MHz. The power consumption of the designed cell is 30 mA from 3.3 V power supply. For basic measurement, the ADC has been directly wires bonded to PCB. The basic measurements are represented by time domain and input output ADC characteristics. The ADC was primarily designed as a test structure for M sequence UWB SoC radar.
author_names: Miroslav Sokol

Pavol Galajda

Stanislav Slovak

Martin Pecovsky
title: Design of 4 bit Flash ADC Cell for UWB Sensor Systems
venue: 2019 29th International Conference Radioelektronika (RADIOELEKTRONIKA)
year: 2019

abstract: A monolithic photon counting receiver consisting of an integrated silicon photomultiplier and a current mode analog to digital converter (ADC) was designed, simulated and fabricated in the AMS 0.35 mm SiGe BiCMOS process. The silicon photomultiplier (SiPM) consists of 64 avalanche photodiodes (APD) arranged in an 8x8 pattern with integrated 236 k quenching resistors. This silicon photomultiplier exhibits peak responsivity at 490 nm and is intended for atmospheric and oceanographic light detection and ranging (LIDAR) applications. The current mode ADC is used to directly convert photocurrent from the silicon photomultiplier into a 4 bit word. The maximum sampling rate achieved in simulation is 100 MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) for the ADC are 0.5 LSB and 0.17 LSB respectively. The dynamic range of the ADC is tunable based on the reference current and varies from 5 mA 80 mA to 30 mA 480 mA. The whole system covers an area of 0.375 mm2. The fill factor of the silicon photomultiplier is 12.6%
author_names: Vikas Vinayaka

Sachin P Namboodiri

Shadden Abdalla

Bryan Kerstetter

Francisco Mata-carlos

Daniel Senda

James Skelly

Angsuman Roy

R Jacob Baker
title: Monolithic 8x8 SiPM with 4 bit Current Mode Flash ADC with Tunable Dynamic Range
venue: ACM Great Lakes Symposium on VLSI
year: 2019

abstract: This Paper introduces 4 bit flash ADC design using Linear Tunable Transconductance Element based comparators for high speed and low power consumption using180nmtech. Thermometer to binary decoder with low power consumption, less area short critical path is selected for the design of low power high speed. Proposed comparator provides improved PSRR (Power Supply Rejection Ratio) compared TIQ (Threshold Inverter Quantizer) comparator NAND based topology is used which improves PSRR as well as linearity; thus eliminates basic limitation of TIQ inverter. Keywords CMOS LTE, CMOS NAND gate, MUX Decoder, ADC, Gain Booster network.
author_names: Leela S Bitla
title: Design and Implementation Of 4 Bit Flash ADC using LTE and NAND Gate Comparator
year: 2018

abstract: A 4 BIT flash ADC is simulated in this work in 90 nm CMOS technology by altering the comparator structure. Two comparators are employed for analysis one is a comparator with cross coupled inverters other is a comparator with regenerative latch. Simulations are executed by varying the supply voltage channel width for different temperatures. Power consumption is then observed recorded ideally at 0.7 V supply voltage 1 um channel length. The minimum power consumption with comparator (cross coupled) is 14.6 uW at 10 degC maximum power consumption of 17.94 uW at 50 degC. Then by altering the comparator to comparator (regenerative latch) the minimum power consumption of 192.1 uW at 10 degC maximum power consumption of 215.5 uW at 50 degC is recorded. Temperature variation leads to the further increment in power consumption. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
author_names: Anil Khatak

Manoj Kumar

Sanjeev Kumar Dhull
title: Design and Analysis of a 4 Bit Flash ADC Architecture with Modified Comparator
venue: ICICI 2018
year: 2018

abstract: This work proposes an efficient 4 bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1 out of 15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1 out of n code. The proposed 4 bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes $292 \mu \mathrm {W} at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.
author_names: Abdullah S Almansouri

Abdullah Alturki

Hossein Fariborzi

Khaled Nabil Salama

Talal Al-Attar
title: A 12.4fJ FoM 4 Bit Flash ADC Based on the StrongARM Architecture
venue: 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
year: 2018