Query: wafer speed

Candidate papers:

abstract: A wafer scale, 2D organic single crystalline semiconductor revolutionizes near field communication. Two dimensional (2D) layered semiconductors are a novel class of functional materials that are an ideal platform for electronic applications, where the whole electronic states are directly modified by external stimuli adjacent to their electronic channels. Scale up of the areal coverage while maintaining homogeneous single crystals has been the relevant challenge. We demonstrate that wafer size single crystals composed of an organic semiconductor bimolecular layer with an excellent mobility of 10 cm2 V 1 s 1 can be successfully formed via a simple one shot solution process. The well controlled process to achieve organic single crystals composed of minimum molecular units realizes unprecedented low contact resistance and results in high speed transistor operation of 20 MHz, which is twice as high as the common frequency used in near field wireless communication. The capability of the solution process for scale up coverage of high mobility organic semiconductors opens up the way for novel 2D nanomaterials to realize products with large scale integrated circuits on film based devices.
author_names: Akifumi Yamamura

Shun Watanabe

Mayumi Uno

Masato Mitani

Chikahiko Mitsui

Junto Tsurumi

Nobuaki Isahaya

Yusuke Kanaoka

Toshihiro Okamoto

Jun Takeya
title: Wafer scale, layer controlled organic single crystals for high speed circuit operation
venue: Science Advances
year: 2018

abstract: This work describes the wafer scale standing growth of (002) plane oriented layers of WS2 and their suitability for use in self biased broad band high speed photodetection. The WS2 layers are grown using large scale sputtering, and the effects of the processing parameters such as the deposition temperature, deposition time, and sputtering power are studied. The structural, physical, chemical, optical, and electrical properties of the WS2 samples are also investigated. On the basis of the broad band light absorption and high speed in plane carrier transport characteristics of the WS2 layers, a self biased broad band high speed photodetector is fabricated by forming a type II heterojunction. This WS2/Si heterojunction is sensitive to ultraviolet, visible, and near infrared photons and shows an ultrafast photoresponse (1.1 ms) along with an excellent responsivity (4 mA/W) and a specific detectivity ~1.5 x 1010 Jones) A comprehensive Mott Schottky analysis is performed to evaluate the parameters of the device, such as the frequency dependent flat band potential and carrier concentration. Further, the photodetection parameters of the device, such as its linear dynamic range, rising time, and falling time, are evaluated to elucidate its spectral and transient characteristics. The device exhibits remarkably improved transient and spectral photodetection performances as compared to those of photodetectors based on atomically thin WS2 and two dimensional materials. These results suggest that the proposed method is feasible for the manipulation of vertically standing WS2 layers that exhibit high in plane carrier mobility and allow for high performance broad band photodetection and energy device applications.
author_names: Hong-Sik Kim

Malkeshkumar Patel

Joondong Kim

Mun Seok Jeong
title: Growth of Wafer Scale Standing Layers of WS2 for Self Biased High Speed UV Visible NIR Optoelectronic Devices.
venue: ACS applied materials interfaces
year: 2018

abstract: In this study, influence of both Si/H2 ratio and C/Si ratio on growth rate uniformity and carrier concentration uniformity of n type 4H SiC epitaxial films grown by high speed wafer rotation vertical CVD tool was investigated. It was found that changes in radial profile of the growth rate and the carrier concentration obtained by varying Si/H2 ratio showed quite similar behavior to those obtained by varying C/Si ratio. Such a similar trend would suggest that the distribution of local C/Si ratio near the wafer surface changes depending on total Si/H2 ratio similarly to total C/Si ratio. Additionally, by using this relationship, both the growth rate uniformity of 49.2 mm/h 1.78% (1.15% s/mean) and carrier concentration uniformity of 1.08 x1016cm 3 6.15% (3.40% s/mean) was achieved.
author_names: Yoshiaki Daigo

Akio Ishiguro

Shigeaki Ishii

Hideki Ito
title: High In Wafer Uniformity of Growth Rate and Carrier Concentration on n Type 4H SiC Epitaxial Films Achieved by High Speed Wafer Rotation Vertical CVD Tool
year: 2018

abstract: 4H SiC homo epitaxial films were grown using a high speed wafer rotation vertical CVD tool, and effects of wafer rotation speed during initial temperature ramping before epitaxial growth were investigated. Also, the effects of conditions during growth of the highly doped buffer layer on both surface and PL defect densities were investigated. It was found that the wafer rotation speed during the temperature ramping has a large influence on the surface defect density of the films. Especially, triangles generated from small pits were considerably reduced in the samples grown at a higher wafer rotation speed during the temperature ramping. The phenomena could be explained as a result of suppressed interfacial reaction between down falls (DFs) and the wafer surface. Additionally, it was found that the density of basal plane dislocations (BPDs) on a drift layer is remarkably reduced by adjusting the C/Si ratio during growth of the buffer layer grown prior to the drift layer. By applying higher wafer rotation speed during the temperature ramping and optimizing the C/Si ratio for the growth of the buffer layer, a total defect density of 0.75 cm 2 on the film, which includes DFs, triangles, DF triangles, stacking faults (SFs) and BPDs, was achieved.
author_names: Yoshiaki Daigo

Akio Ishiguro

Shigeaki Ishii

Hideki Ito
title: Reduction of Surface and PL Defects on n Type 4H SiC Epitaxial Films Grown Using a High Speed Wafer Rotation Vertical CVD Tool
year: 2018

abstract: A 1.2 V 20 nm 307 GB/s high bandwidth memory (HBM) DRAM is presented to satisfy a high bandwidth requirement of high performance computing application. The HBM is composed of buffer die and multiple core dies, and each core die has 8 Gb DRAM cell array with additional 1 Gb ECC array. At speed wafer level, a u bump IO test scheme and an adaptive refresh scheme considering temperature distribution are proposed to guarantee test coverage and stable operation in a power efficient manner.
author_names: Kyomin Sohn

Won-Joo Yun

Reum Oh

Chi Sung Oh

Seong-Young Seo

Min-Sang Park

Dong-Hak Shin

Won-Chang Jung

Sang-Hoon Shin

Je-Min Ryu

Hye-Seung Yu

Jae-Hun Jung

Hyunui Lee

Seok-Yong Kang

Young-Soo Sohn

Jung Hwan Choi

Yong-Cheol Bae

Seong-Jin Jang

G Y Jin
title: A 1.2 V 20 nm 307 GB/s HBM DRAM With At Speed Wafer Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution
venue: IEEE Journal of Solid State Circuits
year: 2017

abstract: In this investigation, we describe a combined low coherence interferometric technique to measure the surface and thickness profiles of wafers at once with high speed. The measurement system consists of a spectrally resolved interferometer to provide and monitor the optical path difference between two incident beams of the optical source part and a low coherence scanning interferometer to measure the dimensions of wafers with significantly shortened scanning length. In the experiments, a silicon wafer and a sapphire wafer, of which both sides are polished, were used as targets of the measurement system for verification of the proposed system. As a result, the scanning length of the low coherence scanning interferometer was reduced from a few millimeters to a few hundreds of micrometers approximately 10 times. In addition, surface profiles of both sides and thickness profiles were simultaneously measured to reconstruct 3D shapes of wafers.
author_names: Hyo Mi Park

Ki-Nam Joo
title: High speed combined NIR low coherence interferometry for wafer metrology.
venue: Applied optics
year: 2017

abstract: This paper presents data on wafer fused 1550 nm vertical cavity surface emitting lasers (VCSELs) based on the active region and distributed Bragg reflectors (DBRs) grown by molecular beam epitaxy. VCSELs with a tunnel junction aperture diameter of <inline formula> <tex math notation="LaTeX"$8~\mu \text{m} /tex math>/inline formula> show lasing at a threshold current density <inline formula> <tex math notation="LaTeX"$j_{\mathrm {th}<3$ /tex math>/inline formula> kA/cm<sup>2</sup> an output optical power of ~4 mW, and a 3 dB bandwidth of approximately 7 GHz at a 10 mA bias current. The devices demonstrate single mode continuous wave operation with the transverse side mode suppression ratio (SMSR) varying in the range of 40 45 dB up to roll over currents. The increase in mirror losses due to the etching of the top DBR makes the output optical power increase to 6 mW and causes the wall plug efficiency value to reach 20% but SMSR remains in the range of 40 45 dB. This also makes it possible to reduce both the photon lifetime and, as a result, the effect of damping and increase the modulation bandwidth to 9 GHz. The observed open and clear eye diagrams indicate that non return to zero operation is possible at bit rates of up to 30 Gbps without equalization or forward error correction. The high output optical power and modulation performance pave the way for the dense wavelength division multiplexing application of wafer fused 1550 nm VCSELs.
author_names: Andrey V Babichev

Leonid Karachinsky

Innokenty Novikov

Andrey Gladyshev

Sergey A Blokhin

S Mikhailov

Vladimir Iakovlev

Alexei Sirbu

Grzegorz Stepniak

Lukasz Chorchos

Jaroslaw Piotr Turkiewicz

K O Voropaev

A S Ionov

Mikel Agustin

Nikolay N Ledentsov

Anton Yu Egorov
title: 6 mW Single Mode High Speed 1550 nm Wafer Fused VCSELs for DWDM Application
venue: IEEE Journal of Quantum Electronics
year: 2017

abstract: Wafer scale defect free planar III V nanowire (NW) arrays with ~100% yield and precisely defined positions are realized via a patterned vapor liquid solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double channel T gated NW array based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs) or graphene channels in plane with the substrate. For a planar GaAs NW array based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF) cutoff frequency (fT) and maximum oscillation frequency (fmax) are 10(4) 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 x 1.5 cm(2) chip, we prove chip level electrical uniformity of the planar NW array based HEMTs and verify the feasibility of using this bottom up planar NW technology for post Si large scale nanoelectronics.
author_names: Xin Miao

Kelson D Chabak

Chen Zhang

Parsian Katal Mohseni

Dennis E Walker

Xiuling Li
title: High Speed Planar GaAs Nanowire Arrays with fmax 75 GHz by Wafer Scale Bottom up Growth.
venue: Nano letters
year: 2015

abstract: A new type of 150 mm vertical 4H SiC epitaxial reactor with high speed wafer rotation has been developed. Multiple resistance heaters ensure uniform radial temperature distribution throughout a 150 mm diameter wafer. Enhancement of the growth rates is realized by high speed wafer rotation under a relatively high system pressure, and growth rates of 40?50 ?m/h are achieved on 4? off 4H SiC substrates, maintaining a low defect density and a smooth surface without macrostep bunching. Excellent thickness and doping uniformities are simultaneously obtained for a 150 mm diameter wafer at a high growth rate of 50 ?m/h.
author_names: Hiroaki Fujibayashi

Masahiko Ito

Hideki Ito

Isaho Kamata

Masami Naito

Kazukuni Hara

Shoichi Yamauchi

Kunihiko Suzuki

Masayoshi Yajima

Shin-ichi Mitani

Suzuki Katsumi

Hirofumi Aoki

Koichi Nishikawa

Takahiro Kozawa

Hidekazu Tsuchida
title: Development of a 150 mm 4H SiC epitaxial reactor with high speed wafer rotation
year: 2014

abstract: Laser trimming is used extensively to ensure accurate values of on chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed loop control and speeding up the process. Predictions are obtained from waferlevel spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of laser trimmed ICs.
author_names: Constantinos Xanthopoulos

Ke Huang

Abbas Poonawala

Amit Nahar

Bob Orr

John M Carulli

Yiorgos Makris
title: IC laser trimming speed up through wafer level spatial correlation modeling
venue: 2014 International Test Conference
year: 2014