Query: develoment technology node

Candidate papers:

abstract: Moore's law, the principle that has powered semiconductor scaling for the past 50 years is nearing its end. However, the industry would like to pursue a dimensional scaling roadmap to reap the full benefit of technology innovation. Results shown on this paper demonstrate traditional dimensional scaling approaches involving multi patterned lithography would skyrocket the manufacturing cost. Design level techniques collectively known as scaling boosters, and innovative Complementary FET (CFET) devices would help to reduce the cost of the technology nodes. To the best of our knowledge, this is the first approach where semiconductor node transitions are benchmarked based on their economic feasibility. To summarize, we have formulated a cost driven approach that can guide the industry to continue semiconductor scaling.
author_names: Arindam Mallik

Julien Ryckaert

Ryan Ryoung han Kim

Peter Debacker

Stefan Decoster

Frederic Lazzarino

Romain Ritzenthaler

Naoto Horiguchi

Diederik Verkest

Anda Mocuta
title: Economics of semiconductor scaling a cost analysis for advanced technology node
venue: 2019 Symposium on VLSI Technology
year: 2019

abstract: This paper signifies the transient analysis of the PLL and is implemented in cadence tool using 180nm technology node. Frequency is expected to be in GHz range for present communication systems to increase the speed and therefore PLL is designed to produce the frequency in GHz range. The designed PLL consists of Phase frequency detector/Charge pump (PFD/CP) second order Low pass filter (LPF) and Schmitt trigger based current starved voltage controlled oscillator (CSVCO) PLL is designed to achieve a stable frequency output. The designed PLL produces 1.084 GHz with 2.382mW of average power consumption.
author_names: Sanjana Hokrani

T C Thanuja

Krishna Kumaraswamy
title: Design and implementation of Phase Locked Loop on 180nm Technology node
venue: 2018 4th International Conference for Convergence in Technology (I2CT)
year: 2018

abstract: For more than a decade, the semiconductor manufacturing industry has anticipated the introduction of Extreme Ultraviolet Lithography (EUVL) into high volume manufacturing (HVM) The readiness of the supporting EUV resists is one of the requirements for HVM. While the industry is planning to introduce EUVL into HVM at 7 nm node, it is important to address the availability of the resists for future generations and in particular for the high NA EUVL which will have the patterning capability down to 8 nm half pitch. In this study we report on the performance of promising EUV resists evaluated by EUV interference lithography (EUV IL) at the Swiss Light Source (SLS) at the Paul Scherrer Institut (PSI) We evaluated EUV resists that are being developed as candidate materials for future technology nodes and we assessed their potential for high NA EUV lithography. Several new chemically amplified resists (CARs) and non CAR resists have been investigated with the aim to resolve patterns down to 10 nm hp. While, up to now, CARs performance reached down to 13 nm half pitch (hp) only, we report about a recent CAR that can partially resolve lines down to 11 nm hp. Moreover, some other non CAR resists have achieved resolutions down to 10 nm. We evaluated essential parameters, such as critical dimension (CD) and line edge roughness as a function of dose and we estimated the exposure latitude (EL) Furthermore, we report on the ultimate extendibility of CAR platform materials in manufacturing, and on novel resist platforms developed to address the challenges in the patterning at hp 10 nm.
author_names: Zuhal Tasdemir

Xiao-long Wang

Iacopo Mochi

Lidia van Lent-Protasova

Marieke Meeuwissen

Rolf Custers

Gijsbert Rispens

Rik Hoefnagels

Yasin Ekinci
title: Evaluation of EUV resists for 5nm technology node and beyond
venue: Photomask Technology
year: 2018

abstract: Crackstops play an important role in protecting the IC prime from moisture ingress as well as impinging cracks. The introduction of thinner BEoL dielectric layers and ULK materials in advanced CMOS technology resulted in more vulnerable crackstop structures. Through Silicon Via (TSV) technology allows the creation of solid copper monolith walls that lack any seams or weak points associated with the conventional layer by layer construction of traditional die seals or crackstops. It was found in previous work [1] that the solid copper crackstop monolith was a superior structure with nearly two times the likelihood to stop the propagation of impinging cracks. However, laboratory experiments demonstrated that cracks were able to bypass the impenetrable solid copper wall through either the underlying silicon interface or unintended thin oxide interface on the upper section of the monolith wall. To address this issue a series of different crackstop architectures that use through silicon via technology have been proposed. These designs incorporate and leverage different architectural elements in an attempt to force the crack's propagation path into the solid copper wall. To assess the various proposed crackstop design's efficiency at stopping a crack, a series of FEM simulations were performed. Simulations were used to study the possibility of crack propagation in a BEoL/Far BEoL stack at the following interfaces: a) copper/copper or copper/aluminum interface; b) the dielectric surrounding the crackstop; and c) the copper/Si interface. Simulations showed in the case of an added bumper extension that cracks are three times less likely to propagate in the Far BEOL at the Al/Cu interface and two times less likely to propagate at the Cu/Si interface. Simulations also showed that the bumper extension with sacrificial dielectric is very efficient in trapping the cracks. Cracks were two times more probable to propagate away from the Cu/Si interface into the sacrificial dielectric and above it.
author_names: Mohamed A Rabie

Nicholas Alexander Polomoff

Md Khaled Hassan

Victoria L Calero-DdelC

Danielle Degraw

Michael Hecker

Michael Thiele

El Mehdi Bazizi
title: Innovative Design of Crackstop Wall for 14nm Technology Node and Beyond
venue: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
year: 2018

abstract: We demonstrate an integration approach to enable 16nm half pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho Etch (LE3) and tone inversion. A silicon verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight pitch metal cut (block) and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.
author_names: B Briggs

C J Wilson

Katia Devriendt

Marleen H van der Veen

Stefan Decoster

Sara Paolillo

Janko Versluijs

Els Kesters

Farid Sebaai

Nicolas Jourdan

Zaid El-Mekki

N Heylen

P Verdonck

D Wan

Olalla Varela Pedreira

Kris Croes

Shibesh Dutta

Julien Ryckaert

Arindam Mallik

Stephane Lariviere

Jurgen Bommels

Zsolt Tokei
title: N5 technology node dual damascene interconnects enabled using multi patterning
venue: 2017 IEEE International Interconnect Technology Conference (IITC)
year: 2017

abstract: In 28nm technology node, developing an enough lithographic process window of PO layer is one of the most basic requirements. Bigger PO DOF means better PO CD uniformity, which is very important to the device performance.
author_names: Bin-Jie Jiang

Shimizu Yu

Zhibiao Mao
title: DOF enhancement of 3bar PO pattern in 28nm technology node
venue: 2017 China Semiconductor Technology International Conference (CSTIC)
year: 2017

abstract: The overlay control is one of the main challenges for advanced lithography in sub 28 nm technology node. There are two kind of overlay metrology in use in semiconductor industry: most conventional image based overlay (IBO) metrology and advanced diffraction based overlay(DBO) metrology. In this paper we will compare these two methods through 3 critical production layers, focusing on the accuracy and the total measurement uncertainty (TMU) for the standard overlay targets of both techniques. The results show that both the accuracy and TMU of DBO method are superior to the traditional IBO method, which makes DBO method applicable at the 28nm and below technology node.
author_names: Jian Xu

Long Qin

Qiaoli Chen

Hui Zhi

Yanyun Wang

Zhengkai Yang

Zhibiao Mao
title: Diffraction based and image based overlay evaluation for advanced technology node
venue: 2017 China Semiconductor Technology International Conference (CSTIC)
year: 2017

abstract: Single PR (photoresist) photo works well in implantation process for planar transistors, however, it suffers severe PR residue issue in FinFET technology node due to the three dimensional fin/gate structure and large wafer surface topography. New integration scheme with BARC (Bottom Anti Reflective Coating) coating/etching was developed to solve this problem. In this work, BARC etching process was compared on two different types of commercial etcher. Key factors which influenced the BARC etching uniformity, remaining PR thickness and BARC profile were discussed. Finally, we delivered a BARC etching process with desired physical profile and improved device performance.
author_names: Long-Juan Tang

Qiu-hua Han

Hai-yang Zhang
title: Barc open in FinFET technology node
venue: 2017 China Semiconductor Technology International Conference (CSTIC)
year: 2017

abstract: The Root Mean Square current (Irms) has been explored on both N doped un silicided poly and silicided poly at 40nm technology node. It is found that poly resistance current (RI) curves show an initially high resistance due to Schottky Rectifying contact. However, poly Irms can be estimated similar to metal Irms. Parameters for poly Irms calculation is provided on the basis of 5degC Joule heating.
author_names: Xiangfu Zhao

Wei-Ting Kary Chien

Kelly Yang
title: Exploration of poly Irms based on 40nm technology node
venue: 2017 China Semiconductor Technology International Conference (CSTIC)
year: 2017

abstract: In this paper, a cylindrical double gate all around technology is merged with junctionless technology to maximize gate control as well as to avoid loss due to the formation of junction in the source channel drain region. This advancement allows downscaling a junctionless cylindrical double gate all around FET (JL CDGAA FET) up to 5nm channel length with acceptable performance in many of its parameters. A comparative study between JL CDGAA FET and GAA FET is also presented in this work.
author_names: N M Mahmud Hossain

Sakib Quader

A Siddik

Md Iqbal Bahar Chowdhury
title: TCAD based performance analysis of junctionless cylindrical double gate all around FET up to 5nm technology node
venue: 2017 20th International Conference of Computer and Information Technology (ICCIT)
year: 2017