Query: A survey of in-spin transfer torque MRAM computing

Candidate papers:

abstract: In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next generation system on a chip. The emerging in memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in magnetic random access memory (MRAM) computing with a low power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal oxide semiconductor node. This study reviews state of the art techniques for managing IMC with an emphasis on spin transfer torque MRAM computing via design schemes at the bit cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co optimization from the IMC perspective.
author_names: Hao Cai

Juntong Chen

Lirida A B Naviner

Zhen Wang
title: A survey of in spin transfer torque MRAM computing
venue: Sci. China Inf. Sci.
year: 2021

abstract: CMOS compatible spin transfer torque magnetic random access memory (STT MRAM) has demonstrated promising developments as the next generation embedded non volatile memory (eNVM) In this survey, we provide the state of the art multi modes reconfigurable techniques for energy efficient STT MRAM implementation. We resort to the bottom up design approach with a twofold aim: 1) summarizing related work from bit cell to circuit and system levels with conventional and emerging memories. 2) analyzing the present research status of multi modes reconfigurable techniques in MRAM, which consist of tunable bit cell configuration, in memory computing and hybrid memory system. Experimental comparisons show that both reconfiguration and in MRAM computing obtain extra design freedom. Nonvolatile data accessing cost can be well alleviated, and thereby improving energy efficiency of MRAM.
author_names: Hao Cai

Juntong Chen
title: Toward Energy Efficient STT MRAM Design With Multi Modes Reconfiguration
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2021

abstract: This work is an effort to introduce advanced logic, their applications and some of their post CMOS technological implementations in "core" conventional logic design classroom. In this short one lecture knowledge module, we aimed at threshold logic and its most popular application, the neural computing. Majority, a special type of threshold function was also discussed and one of its post CMOS implementation was shown. A post CMOS memory called Spin Transfer Torque Magnetoresistive RAM (STT MRAM) was also introduced. The purpose of the module was to encourage research among students and to motivate them towards electives in advanced logic and post CMOS nanotechnologies. Students' feedback were collected through a pre and a post module survey. The feedback suggest that all the participants were satisfied with the module and the module was successful in fulfilling its objectives.
author_names: Jayita Das

Sanjukta Bhanja
title: A novel knowledge module to integrate threshold logic and post CMOS technology into undergraduate logic design classroom
venue: Fourth Interdisciplinary Engineering Design Education Conference
year: 2014

abstract: In memory computing is a promising approach to addressing the processor memory data transfer bottleneck in computing systems. We propose spin transfer torque compute in memory (STT CiM) a design for in memory computing with spin transfer torque magnetic RAM (STT MRAM) The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT MRAM peripheral circuits that leverage this principle to perform logic, arithmetic, and complex vector operations. We address the challenge of reliable in memory computing under process variations by extending error correction code schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT CiM should be integrated within a general purpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on chip buses that enable STT CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT CiM. We evaluate STT CiM using a device to architecture modeling framework, and integrate cycle accurate models of STT CiM with a commercial processor and on chip bus (Nios II and Avalon from Intel) Our system level evaluation shows that STT CiM provides the system level performance improvements of 3.93 times on average (up to 10.4 times) and concurrently reduces memory system energy by 3.83 times on average (up to 12.4 times)
author_names: Shubham Jain

Ashish Ranjan

Kaushik Roy

Anand Raghunathan
title: Computing in Memory With Spin Transfer Torque Magnetic RAM
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2018

abstract: Accurate modeling of magnetic tunnel junction (MTJ) is critical for design of memories such as spin transfer torque magnetoresistive random access memory (STT MRAM) and spin logic circuits such as spin flip flops. This paper reviews several static and dynamic models for the MTJ and compares them for their capabilities and limitations. Furthermore, a Verilog A model is developed to predict dynamic characteristics of the MTJ. These models are used in simulating a prototype circuit to illustrate their strengths and weaknesses.
author_names: Aynaz Vatankhahghadim

Safeen Huda

Ali Sheikholeslami
title: A Survey on Circuit Modeling of Spin Transfer Torque Magnetic Tunnel Junctions
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2014

abstract: Summary form only given. The initial predictions and subsequent definitive demonstrations of the ability of a spin polarized current that impinges onto a thin film nanomagnet to reversibly switch the orientation of its magnetic moment, and/or to excite it into microwave precession, by the torque exerted through the transfer of spin angular momentum from the incident conduction electrons, have catalyzed what is now a quite broad and very active area of spin torque research. Since those initial works, there has been remarkable progress in advancing the fundamental understanding of this new spintronics phenomenon, and in successfully moving it towards technological implementations, particularly spin torque magnetic random access memory (ST MRAM) and spin torque microwave oscillator applications, that have the potential for broad impact. In this presentation I will discuss the basics of the spin torque effect and briefly survey the various approaches that can be employed to demonstrate and study it in both all metallic, spin valve type nanostructures and, most importantly for applications, in nanoscale magnetic tunnel junctions (MTJs) I will discuss some recent work that has sought to contribute to the rapidly advancing spin torque research effort, by helping both to better understand quantitatively the details of the phenomenon and to understand and enhance the efficiency of the effect I will summarize results from studies of spin transfer switching and microwave excitation in magnetic tunnel junctions (MTJs) which include the use of the spin transfer phenomenon to quantitatively determine, through spin torque excited ferromagnetic resonance (ST FMR) both the bias dependent efficiency of the spin torque in high quality MTJs and the magnetic damping of individual free layer nanomagnets. I will also briefly describe some recent work that has been examining spin torque effects in nanoscale structures with distinctly non uniform magnetization which is giving us some new information regarding magnetic dynamics in nanoscale structures and are pointing to ways by which it may be possible to significantly reduce the spin polarized current needed for the short pulse switching of a thermally stable nanomagnet for MRAM applications. I will conclude by briefly discussing some of challenges that remain to be overcome before spin torque based technologies, particularly ST MRAM, can be successfully implemented and of the pathways that might be effectively taken to overcome those challenges.
author_names: Robert A Buhrman
title: Spin Torque Writing for Next Generation MRAM Challenges and Prospects
venue: 2008 Device Research Conference
year: 2008

abstract: Many key electronic technologies (e.g. large scale computing, machine learning, and superconducting electronics) require new memories that are fast, reliable, energy efficient, and of low impedance at the same time, which has remained a challenge. Non volatile magnetoresistive random access memories (MRAMs) driven by spin orbit torques (SOTs) have promise to be faster and more energy efficient than conventional semiconductor and spin transfer torque magnetic memories. This work reports that the spin Hall effect of low resistivity Au0.25Pt0.75 thin films enables ultrafast antidamping torque switching of SOT MRAM devices for current pulse widths as short as 200 ps. If combined with industrial quality lithography and already demonstrated interfacial engineering, our results show that an optimized MRAM cell based on Au0.25Pt0.75 can have energy efficient, ultrafast, and reliable switching, e.g. a write energy of 50 fJ 1 fJ) for write error rate of 50% <10 5) for 1 ns pulses. The antidamping torque switching of the Au0.25Pt0.75 devices is 10 times faster than expected from a rigid macrospin model, most likely because of the fast micromagnetics due to the enhanced non uniformity within the free layer. These results demonstrate the feasibility of Au0.25Pt0.75 based SOT MRAMs as a candidate for ultrafast, reliable, energy efficient, low impedance, and unlimited endurance memory.
author_names: Lijun Zhu

Lujun Zhu

Daniel C Ralph

Robert A Buhrman
title: Energy Efficient Ultrafast SOT MRAMs Based on Low Resistivity Spin Hall Metal Au 0.25 Pt 0.75
year: 2019

abstract: Traditional Von Neumann computing is falling apart in the era of exploding data volumes as the overhead of data transfer becomes forbidding. Instead, it is more energy efficient to fuse compute capability with memory where the data reside. Emerging spintronic technologies show remarkable versatility for the tight integration of logic and memory. In this presentation, we introduce Computational RAM (CRAM) a novel high density, reconfigurable spintronic in memory substrate, and survey several years of progress in developing the CRAM concept across the system stack from the device level all the way to applications. I. FUSING COMPUTATION AND MEMORY Classical computing platforms are not optimized for efficient data transfer, which complicates large scale data analytics in the presence of exponentially growing data volumes. Imbalanced technology scaling further exacerbates this situation by rendering data communication, and not computation, a critical bottleneck [5] Specialization in hardware cannot help in this case unless conducted in a data centric manner. Tight integration of compute capability into the memory, Processing in memory (PIM) is especially promising as the overhead of data transfer becomes forbidding at scale. The rich design space for PIM spans full fledged processors and coprocessors residing in memory [6] Until the emergence of 3Dstacking, however, the incompatibility of the state of the art logic and memory technologies prevented practical prototype designs. Still, 3D stacking can only achieve near memory processing, NMP [1] [2] [8] The main challenge remains to be fusing computation and memory without violating array regularity. Emerging spintronic technologies show remarkable versatility for the tight integration of logic and memory. This talk covers a high density, reconfigurable spintronic in memory compute substrate, Computational RAM (CRAM) [10] The basic idea is to add compute capability to the magnetic tunnel junction (MTJ) based memory cell [7] [12] without breaking the array regularity. Thereby each memory cell can participate in gate level computation as an input or as an output. Computation is not disruptive, i.e. memory cells acting as gate inputs do not loose their stored values. This idea is equally applicable to Spin Torque Transfer (STT) and SpinOrbit Torque (SOT) based technologies. CRAM can implement different types of basic Boolean gates to form a functionally complete set, therefore there is no fundamental limit to the types of computation. If implemented using SOT (STT) each column (row) in an CRAM array can have only one active gate at a time, however, computation in all columns (rows) can proceed in parallel. CRAM provides true in memory computing by reconfiguring cells within the memory array to implement logic functions. As all cells in the array are identical, inputs and outputs to logic gates do not need to be confined to a specific physical location in the array. In other words, CRAM can intiate computation at any location in the memory array on demand. II. OPERATION PRINCIPLE Without loss of generality, we will next use an STT based CRAM as a running example. In its most basic form, a CRAM array is essentially a 2D magneto resistive RAM (MRAM) When compared to the standard 1T(ransistor)1M(TJ) MRAM cell, however, each CRAM cell features an additional transistor TL (Fig.1(a) which acts as a switch between memory and logic configurations. A CRAM cell can operate as a regular MRAM memory cell or serve as an input/output to a logic gate. Each MTJ consists of two layers of ferromagnets, termed as pinned and free layers, separated by a thin insulator. The magnetic spin orientation of the pinned layer is fixed; of the free layer, controllable. Changing the orientation of the free layer entails passing a (polarized) current through the MTJ, where the current direction sets the orientation. The relative orientation of the free layer with respect to the pinned layer, i.e. anti parallel (AP) or parallel (P) gives rise to two distinct MTJ resistance levels, i.e. Rhigh and Rlow, which encode logic 1 and 0, respectively. As resistance levels represent logic states, Fig.1 depicts each MTJ by its resistance. Memory Configuration: The dashed components in Fig.1(a) capture all add ons to the standard MRAM memory cell, in order to support logic functions. When the array is configured as memory, the Logic Bit Line (LBL) is set to 0 to turn the switch TL off, and thereby to disconnect the cells from the Logic Line (LL) In this case, the array becomes equivalent to a standard MRAM array. In the following, we detail the configuration for various memory operations (where LBL is always set to 0) Data retention: The Word Line (WL) is set to 0 to isolate the cells and to prevent current flow through the MTJs. Read: WL is set to 1, to connect each MTJ to its Bit Select Line (BSL) and Memory Bit Line (MBL) A small voltage pulse applied between BSL and MBL induces a current through the MTJ, which is a function of the resistance level (i.e. logic state) and which in turn a sense amplifier attached to BSL captures. Write: WL is set to 1, to connect each MTJ to its BSL and MBL. A large enough voltage pulse (in the order of the supply voltage) is applied between BSL and MBL to induce a large enough current through the MTJ to change the spin orientation of the free layer. Logic Configuration: LL connects all cells participating in computation, on a per row basis. Such cells may act as logic gate inputs or outputs. For each CRAM cell participating in computation, WL is set to 0 to disconnect its MTJ from MBL. Instead, LBL is set to 1 to turn the switch TL on, which in turn connects the MTJ to the LL. As an example, Fig.1(b) demonstrates the formation of a two input logic gate in the array, where cells labeled by "0" "1" and "2" correspond to the inputs In0, In1, and the output Out, respectively. Fig.1(c) depicts the equivalent circuit: BSL of the output, BSL2, is grounded; while BSL of the two inputs,
author_names: Masoud Zabihi

Zhengyang Zhao

Zamshed Iqbal Chowdhury

Salonik Resch

D C Mahendra

Thomas J Peterson

Ulya R Karpuzcu

Jianping Wang

Sachin S Sapatnekar
title: True In memory Computing with the CRAM: From Technology to Applications
venue: ACM Great Lakes Symposium on VLSI
year: 2019

abstract: Hardware implementation of artificial neural networks (ANNs) using conventional binary arithmetic units requires large area and energy, due to the massive multiplication and addition operations in the inference process, limiting their use in edge computing and emerging Internet of Things (IoT) systems. Stochastic computing (SC) where the probability of 1s and 0s in a randomly generated bit stream is used to represent a decimal number, has been devised as an alternative for compact and low energy arithmetic hardware, due to its ability to implement basic arithmetic operations using far fewer logic gates than binary operations. To realize SC in hardware, however, tunable true random number generators (TRNGs) are needed, which cannot be efficiently realized using existing complementary metal oxide semiconductor complementary metal oxide semiconductor (CMOS) technology. In this letter, we address this challenge by using magnetic tunnel junctions (MTJs) as TRNGs, the stochasticity of which can be tuned by an electric current via spin transfer torque. We demonstrate the implementation of ANNs with SC units, using stochastic bit streams experimentally generated by a series of 50 nm perpendicular MTJs. The numerical value (1 to 0 ratio) of the bit streams is tuned by the current through the MTJs via spin transfer torque with an ultralow current of <5 uA 0.25 MAcm 2) The MTJ based SC ANN achieves 95% accuracy for handwritten digit recognition on the MNIST database. MRAM based SC ANNs provide a promising solution for ultra low power machine learning in edge, mobile, and IoT devices.
author_names: Yixin Shao

Sisilia Lamsari Sinaga

Idris O Sunmola

Andrew S Borland

Matthew J Carey

Jordan A Katine

Victor Lopez-Dominguez

Pedram Khalili Amiri
title: Implementation of Artificial Neural Networks Using Magnetoresistive Random Access Memory Based Stochastic Computing Units
venue: IEEE Magnetics Letters
year: 2021

abstract: Spin transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on chip memory in future computing platforms. We present a cross layer (device circuit architecture) approach to energy efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose microarchitectural techniques viz. sequential cache read and partial cache line update, which exploit the non volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.
author_names: Sang Phill Park

Sumeet Kumar Gupta

Niladri Narayan Mojumder

Anand Raghunathan

Kaushik Roy
title: Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture
venue: DAC Design Automation Conference 2012
year: 2012