Query: Design High gain dual stage operational amplifier using CMOS 45nm Technology

Candidate papers:

abstract: Differential amplifier is an analog component. which is used as an amplifier whenever a circuit contains more than one input. A differential amplifier is a basic primitive component in an operational amplifier. Differential amplifier contains three legs. In which two legs for the input signal to be amplified, the third leg used as output. The differential amplifier can be configured by bipolar technology or with Metal oxide semiconductor technology also. When the input non inverted leg which acts as a comparator is applied as input, if any signal applied to invert leg of the differential amplifier it will be used as an amplifier. In this proposed article, the operational amplifier with high gain of 72dB is implemented, the Slew rate of 122 V/us, Gain bandwidth product of 4.60 MHz Dual stage operational amplifier will enhance the amplification in a better way when the single stage amplifier is compared In this article, a dual stage operational amplifier using CMOS 45nm Technology is implemented.
author_names: Srilakshmi Ravali Madabhushanam

Lalitha Malladi

Soumya Reddy Gudepu
title: Design High gain dual stage operational amplifier using CMOS 45nm Technology
venue: 2020 Fourth International Conference on I SMAC (IoT in Social, Mobile, Analytics and Cloud) (I SMAC)
year: 2020

abstract: In this paper, the comparison design of a two stage Bulk CMOS (NMOS) low noise amplifier is implemented using 45 nm technology. These designed amplifiers can operate at a frequency range of 24 30 GHz. The amplifier is implemented using two stage Cascode configuration and shunt series peaking. A comparative study of designed Cascode configuration with feedforward technique, current bleeding technique, and differential configuration. The operation of the circuits in the millimeter wave frequency band and is compared for gain, noise, power consumption and linearity. The different architectures were implemented for high performance with a power supply of 1.1V. The design is implemented by using two NMOS transistors on both stages, producing maximum transconductance with a minimum transistor width, which in turn makes the circuit operate faster. The use of the feed forward technique implemented has helped to reduce noise and power consumption. The circuits were stimulated in the Keysight Agilent Design System software package using a 45nm Predictive technology model (PTM)
author_names: Vishniu Ks

Vaithianathan V
title: Design of CMOS Low Noise Amplifier for 5G Applications Using 45nm Technology
venue: 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184)
year: 2020

abstract: This paper presents the design and implementation of a high gain, low power CMOS operational amplifier with high impedance class AB output stage. By use of cascode based transistor connections the operational amplifier is capable of handling input common mode voltage levels close to operating power supply voltage. The transistors at the input stage are operated in the near subthreshold region. Every transistor size in the op amp is designed, validated and operated at VDD=1.5V. The proposed amplifier circuit employs a class AB output stage consisting of PMOS and NMOS transistors, which accounts for better performance such as higher gain, lower static power dissipation, increased unity gain frequency, higher values of slew rate and reduced input referred noise density than a standard cascode amplifier using emitter follower configuration. The main specifications considered are DC gain, slew rate, power dissipation, phase margin, unity gain bandwidth and CMRR. Circuit level analysis of the proposed amplifier stage is simulated using Cadence Virtuoso schematic editor. The op amp provides a DC gain of 66.4dB and a unity gain bandwidth of 228MHz at 0.5pF. The power dissipation is found to be 74mW, slew rate is 248.2V/ms, CMRR is 116.6dB and area occupied is 0.058mm2.
author_names: Arnav Kumar

K Lokesh Krishna

K Abhinav Viswateja

K Gopi

S Mohan Rao

B Mamatha
title: A High Gain Low Power Operational Amplifier using Class AB Output Stage
venue: 2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)
year: 2019

abstract: This paper presents an ultra low power operational amplifier (opamp) with high gain and high common mode rejection ratio (CMRR) in 45nm CMOS technology. It uses a bulk driven differential pair in the input stage to facilitate low voltage design and to achieve a high input common mode range (ICMR) In addition, the design employs an auxiliary differential pair that utilizes dynamic threshold MOS (DTMOS) technique to enhance the effective transconductance and hence achieves high gain and high unity gain bandwidth (UGB) All the transistors are biased to operate in subthreshold region in order to minimize power consumption. Simulation with Cadence Virtuoso for 350 mV of supply and a load capacitance of 1 pF, yields a DC gain of 77.03 dB, CMRR of 130.8 dB, UGB of 456.9 kHz and a phase margin of 82.47deg for a power consumption of 21.75 nW.
author_names: Fazal Hussain

Partha Ray
title: A 45nm ultra low power operational amplifier with high gain and high CMRR
venue: 2017 IEEE 15th Student Conference on Research and Development (SCOReD)
year: 2017

abstract: In this paper, the CMOS Instrumentation amplifier using a three stage operational Amplifier is presented for low power applications, whose operating power supply is 3 V. The power supply is reduced to decrease the power consumption of the whole circuit. The passive resistive loads are replaced by active load, i.e. by NMOS (in linear region behaves as a resistor) which reduces the overall chip area and contributes to lesser power dissipation. Active load, in turn, produces higher resistance values compared to passive loads thus results in higher values of power gain. Its large gain can amplify even very small signals ranging from 10 6 Vs to 10 3 Vs. In the previous studies of two stage Op amp when operated with resistive load at the output, the overall gain of the circuit is reduced. Also, another problem with two stage Op Amp is the trade off, when we reduce the channel length for increasing speed of Op Amp then the gain is reduced. Thus, the three stage Op amp is presented which can have high gain, high operating speed also when operated at the lesser supply voltage. The proposed Operational amplifier is simulated in H spice at Level 2 (i.e. 180 nm CMOS technology) and AC analysis results of Avanwaves are shown.
author_names: Shubham Saurabh

M A Saifi

Shylaja VinayKumar Karatangi

Amrita Rai
title: Design of CMOS Instrumentation Amplifier Using Three Stage Operational Amplifier for Low Power Signal Processing
year: 2020

abstract: This paper presents the description and analysis of the design and HSPICE based simulation results of very low voltages (LVs) power supplies and high performance specifications CMOS gate driven (GD) operational amplifier (Op Amp) circuit. The very LVs CMOS GD Op Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common mode rejection ratio is dB, the equivalent input referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 the negative slew rate is 11.39 the settling time is 137 the positive power supply rejection ratio is 74.2dB, and the negative power supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies' voltages of the very LVs CMOS GD Op Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op Amp circuits.
author_names: Hayder Khaleel AL-Qaysi

Musaab Mohammed Jasim

Siraj Manhal Hameed
title: Design of very low voltages and high performance CMOS gate driven operational amplifier
year: 2020

abstract: This paper presents the design and simulation of Low Voltage Folded Cascode CMOS Operational Amplifier using gpdk 0.18mM CMOS technology. The proposed op amp consists of pair of NMOS transistors as an input differential gain stage, the NMOS differential pair is chosen for low power consumption and also to maintain good UGF. The design is simulated using cadence spectre simulator, under 1V supply voltage. The proposed design shows 68.6dB gain, Phase margin of 50 0 UGF of 13.1MHz, with power consumption of 30mW. IndexTerms Folded Cascode Operational Amplifier, Op Amp, 180nM CMOS Op Amp.
author_names: K Rajesh Kumar

J Kamal Vijetha

Bhavani Kinnara
title: Design of Folded Cascode Operational Amplifier Using 1.8micron CMOS Technology
year: 2018

abstract: Operational amplifier is consider to be the most imperative electronic device. The procedure inscribed in this paper is to design a two stage CMOS operational amplifier (Opamp) and analyze the effect of various parameters on the characteristics of Opamp design. This paper is mainly concentrating on design of optimized Opamp gain. Keeping this as a main aspect, Opamp specifications are taken into account, i.e. Gain, phase margin, slew rate, power dissipation and others. This work presents a design and implementation of two stage CMOS operational amplifier which operates at 1V supply voltage and Simulation process is carried out by using an EDA tool cadence virtuoso with 90nm technology. The obtained gain is 84db with phase margin of 560 and the power dissipation is of 38.02mW.
author_names: C L Kavyashree

M Hemambika

K G Dharani

Ananth V Naik

M P Sunil
title: Design and implementation of two stage CMOS operational amplifier using 90nm technology
venue: 2017 International Conference on Inventive Systems and Control (ICISC)
year: 2017

abstract: Design of analog circuit is mainly based on simulations that are strongly dependent on EDA tools and competency of the designer. With regard to this, the automatic designs automation for analog architectures is required to solve the simulation time problem. This paper deals with the method for modeling the analog architecture to evaluate the performance parameters; this is for optimizing the transistor size to achieve the desired characteristics. Finally the proposed methodology is applied to design a gate driven Operational Transconductance Amplifier (OTA) using TSMC 0.18 mm CMOS Technology and the design evaluation is done in Cadence Virtuoso. Then, we analyze the performance parameters of the proposed OTA according to the desired specification at 0.18 mm CMOS Technology. This proposed OTA has a supply Voltage of 1.6 V. The multifunction filter is also implemented using OTA of 2.5 V supply.
author_names: Siddesh Gaonkar

P S Sushma
title: Modeling, design and analysis of high CMRR two stage gate driven operational transconductance amplifier using 0.18 mm CMOS technology
venue: 2016 3rd International Conference on Computing for Sustainable Global Development (INDIACom)
year: 2016

abstract: A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low voltage low power VLSI as it requires a dual supply of only 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/ms. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.
author_names: Urvashi Bansal

Pranjal Gupta

Rachit Tayal
title: A high gain and high bandwidth three stage amplifier using FGMOS and 0.5 V dual supply
year: 2020