Query: fpga blind equalization

title: FPGA based high speed design for blind equalization of 8PSK signals
abstract: A high speed structure for blind equalization of 8PSK signals is presented based on FPGA. The filter section is designed with a parallel structure based on time domain convolution. In the case of short delay spread, this structure is superior to the parallel structure based on sub convolution filter bank in literature on computational complexity. Applying this structure to the blind equalization of 800Mbps 8PSK signals, test results show that the speed requirement is met, the hardware resources are furthest saved, and the blind equalizer converges fast.

title: Blind Equalization Algorithm of High order QAM Signal and Its FPGA based Implementation
abstract: Aiming at blind equalization problem of QAM signal,this paper proposes a hybrid blind equalization algorithm named GMMA DD by combining Generalized Multi Modulus Algorithm(GMMA) and Decision Directed(DD) algorithm.It combines the benefits of GMMA and DD algorithm,and utilizes the mean square error to control the proportion of two kind of error signals in total error signals to improve the performance of blind equalization.An improved algorithm with lower computational complexity and less FPGA resources is presented and implemented to simplify FPGA based implementation by using serial and pipelining structures.Experimental results show that the algorithm has good performance for high order QAM signals.

title: Constant Modulus Blind Equalization Analysis for High Speed Implementation
abstract: Constant modulus equalization algorithm (CMA) is widely used for mitigating inter symbol interference (ISI) in various communication systems, for its robustness and low computational complexity. In practice, signed error CMA may be adopted to simplify the implementation. However, the simplification severely degrades its steady state performance. In this paper, a detailed analysis is taken to compare the mentioned two algorithms in Field Programmable Gate Arrays (FPGA) implementation. Furthermore, a novel error function is proposed for the high speed implementation consideration. Numerical simulation demonstrates that the proposed algorithm behaves much better than the reference with similar computational complexity, which makes the proposed algorithm more suitable for the area of high speed applications.

title: Implementation of CMA base blind equalizer on FPGA
abstract: In PCM/FM remote sensing receiving system, when the bit rate is above 1Mbps, the signal suffers frequency select fading, which causes the serious inter symbol interference (ISI) power allowance can no longer guarantee the system quota. Besides signal reflection such as buildings, ground, mountains and atmospheric refraction eventually become the multipath interference signals. Thus an adaptive filter is needed for equalization before the sample decision detector in the receiver  The traditional method is based on training sequence channel equalization. However, considering to these two problems, two issues are discussed in this dissertation: blind equalization based on the adaptive filter theory; the realization of blind equalizer on FPGA.

title: A blind equalization algorithm for FPGA realization
abstract: In this paper, a new separate adjust variable step size blind equalization algorithm is proposed for PAM and QAM modulation, and this new algorithm is realized with Altera's FPGA device. Analysis and comput er simulations show that the convergence performance and symbol error performance of the blind equalization al gorithm are better than those of CMA algorithm. So the separate adjust variable step size equalization algorithm is very useful for practice use.

title: FPGA based implementation of channel blind adaptive equalizers
abstract: Inter Symbol Interference (ISI) is a major obstacle for reliable communication over band limited or multi path channels as it results in overlapped symbols at the receiver, and therefore, elevated bit error rate. This limitation reduces the potential performance gains of high order modulation schemes to be used in modern communication standards. Blind equalization algorithms can solve such problem without the reduction in data rate that is associated with data aided equalizers. In this paper we propose a Field Programmable Gate Array (FPGA) implementation of adaptive fractionally spaced (FSE) blind equalizer, which is both efficient and scalable. The implementation results are provided and its real time performance on a 2 by 2 Multi Input Multi Output (MIMO) channel using 16 QAM modulation is validated by measuring against simulation results.

title: Blind adaptive equalization for QAM signals: New algorithms and FPGA implementation.

title: FPGA implementation of blind adaptive decision feedback equalizer
abstract: This paper considers field programmable gate array (FPGA) implementations for blind adaptive decision feedback equalizer (DFE) based on the IP core reported in  The design can achieve channel equalization for 16 QAM and 64 QAM. Constant modulus algorithm (CMA) and multi modulus algorithm (MMA) are considered for update the coefficients in the blind mode of operation which are followed by decision directed (DD) mode. The system can work at a maximum clock frequency of 22 MHz. The design steps first consider fixed point simulations using MATLAB fixed point toolbox follows by FPGA implementations. The implementations are divided into complex weight update module, output computation module, error adjustment module, and decision device module. Finally, the DFE is implemented using Xilinx Virtex II XC2VP100 FPGA.

title: Study and Realization of High Speed Hybrid 2 Dimensional Blind Equalization for MQAM Signals
abstract: Based on the study of equalization algorithm for Multi Level Quadrature Amplitude Modulation (MQAM)signals,a simplified and high speed hybrid blind equalization algorithm is proposed.The proposed method is realized in an equalizer which is fulfilled with FPGA devices.The performance of the algorithm is verified by the emulation and measured results.The results are of great significant to the design of equalizers which are applied to parallelly process the MQAM signals with high speed.

title: Practical implementation of blind equalization, carrier recovery and timing recovery for QAM cable receiver chip
abstract: This paper is concerned with the system level design of quadrature amplitude modulation (QAM) cable receiver chip for cable HDTV application. We introduce a receiver structure with joint blind decision feedback equalizer (DFE) loop, timing recovery loop, carrier recovery loop and AGC loop. The architecture of blind dual mode DFE, with constant modulus algorithm (CMA) initialization block, dual mode feed forward filter and feedback filter, operates in the passband so that equalizer can be adjusted completely independent of carrier phase. For VLSI realization, the hybrid form, one of pipelined structure without introducing extra latency is applied to the DTE. The all digital synchronization loops such as timing recovery are also described. The timing recovery architecture features with recirculating decimator for variable rate interpolation that allows it operate at any user specified symbol rate from 875kbaud to 7Mbaud. The SPW HDSt simulation and Xilinx VirtexTM II 3000 FPGA verification confirm that proposed scheme is robust against non impulse noise, multi paths and carrier error such as frequency offset, phase offset and phase jitter.