Query: hevc motion estimation fpga code

title: Overview of the High Efficiency Video Coding (HEVC) Standard
abstract: High Efficiency Video Coding (HEVC) is currently being prepared as the newest video coding standard of the ITU T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of the HEVC standardization effort is to enable significantly improved compression performance relative to existing standards in the range of 50% bit rate reduction for equal perceptual video quality. This paper provides an overview of the technical features and characteristics of the HEVC standard.

title: HEVC Complexity and Implementation Analysis
abstract: Advances in video compression technology have been driven by ever increasing processing power available in software and hardware. The emerging High Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate. In this paper, complexity related aspects that were considered in the standardization process are described. Furthermore, profiling of reference software and optimized software gives an indication of where HEVC may be more complex than its predecessors and where it may be simpler. Overall, the complexity of HEVC decoders does not appear to be significantly different from that of H.264/AVC decoders; this makes HEVC decoding in software very practical on current hardware. HEVC encoders are expected to be several times more complex than H.264/AVC encoders and will be a subject of research in years to come.

title: Hexagon based search pattern for fast block motion estimation
abstract: In block motion estimation, a search pattern with a different shape or size has a very important impact on search speed and distortion performance. A square shaped search pattern is adopted in many popular fast algorithms. Recently, a diamond shaped search pattern was introduced in fast block motion estimation and has exhibited a faster search speed. Based on an in depth examination of the influence of the search pattern on speed performance, we propose a novel algorithm using a hexagon based search pattern to achieve further improvement. The hexagon based search pattern is investigated in comparison with diamond search pattern and demonstrates significant speedup gain over the diamond based search. Analysis shows that a speed improvement rate of the hexagon based search (HEXBS) algorithm over the diamond search (DS) algorithm can be over 80% for locating some motion vectors in certain scenarios. In short, the proposed HEXBS algorithm can find the same motion vector with fewer search points than the DS algorithm. Generally speaking, the larger the motion vector, the more search points the. HEXBS algorithm can save, which is further justified by experimental results.

title: A new three step search algorithm for block motion estimation
abstract: The three step search (TSS) algorithm has been widely used as the motion estimation technique in some low bit rate video compression applications, owing to its simplicity and effectiveness. However, TSS uses a uniformly allocated checking point pattern in its first step, which becomes inefficient for the estimation of small motions. A new three step search (NTSS) algorithm is proposed in the paper. The features of NTSS are that it employs a center biased checking point pattern in the first step, which is derived by making the search adaptive to the motion vector distribution, and a halfway stop technique to reduce the computation cost. Simulation results show that, as compared to TSS, NTSS is much more robust, produces smaller motion compensation errors, and has a very compatible computational complexity.

title: A new diamond search algorithm for fast block matching motion estimation
abstract: Based on the study of motion vector distribution from several commonly used test image sequences, a new diamond search (DS) algorithm for fast block matching motion estimation (BMME) is proposed in this paper. Simulation results demonstrate that the proposed DS algorithm greatly outperforms the well known three step search (TSS) algorithm. Compared with the new three step search (NTSS) algorithm, the DS algorithm achieves close performance but requires less computation by up to 22% on average. Experimental results also show that the DS algorithm is better than the four step search (4SS) and block based gradient descent search (BBGDS) in terms of mean square error performance and required number of search points.

title: Efficient Parallel Framework for HEVC Motion Estimation on Many Core Processors
abstract: High Efficiency Video Coding (HEVC) provides superior coding efficiency than previous video coding standards at the cost of increasing encoding complexity. The complexity increase of motion estimation (ME) procedure is rather significant, especially when considering the complicated partitioning structure of HEVC. To fully exploit the coding efficiency brought by HEVC requires a huge amount of computations. In this paper, we analyze the ME structure in HEVC and propose a parallel framework to decouple ME for different partitions on many core processors. Based on local parallel method (LPM) we first use the directed acyclic graph (DAG) based order to parallelize coding tree units (CTUs) and adopt improved LPM (ILPM) within each CTU (DAGILPM) which exploits the CTU level and prediction unit (PU) level parallelism. Then, we find that there exist completely independent PUs (CIPUs) and partially independent PUs (PIPUs) When the degree of parallelism (DP) is smaller than the maximum DP of DAGILPM, we process the CIPUs and PIPUs, which further increases the DP. The data dependencies and coding efficiency stay the same as LPM. Experiments show that on a 64 core system, compared with serial execution, our proposed scheme achieves more than 30 and 40 times speedup for 1920 x 1080 and 2560 x 1600 video sequences, respectively.

title: High Throughput Power Efficient VLSI Architecture of Fractional Motion Estimation for Ultra HD HEVC Video Encoding
abstract: Fractional motion estimation (FME) significantly enhances video compression efficiency, but its high computational complexity also limits the real time processing capability. In this brief, we present a VLSI implementation of FME design in High Efficiency Video Coding for ultrahigh definition video applications. We first propose a bilinear quarter pixel approximation, together with a search pattern based on it to reduce the complexity of interpolation and fractional search process. Furthermore, a data reuse strategy is exploited to reduce the hardware cost of transform. In addition, using the considered pixel parallelism and dedicated access pattern for memory, we fully pipeline the computation and achieve high hardware utilization. This design has been implemented as a 65 nm CMOS chip and verified. The measured throughput reaches 995 Mpixels/s for 7680 x 4320 30 frames/s at 188 MHz, at least 4.7 times faster than prior arts. The corresponding power dissipation is 198.6 mW, with a power efficiency of 0.2 nJ/pixel. Due to the optimization, our work achieves more than 52% improvement on power efficiency, relative to previous works in H.264.

title: High Efficiency Video Coding (HEVC) Algorithms and Architectures
abstract: This book provides developers, engineers, researchers and students with detailed knowledge about the High Efficiency Video Coding (HEVC) standard. HEVC is the successor to the widely successful H.264/AVC video compression standard, and it provides around twice as much compression as H.264/AVC for the same level of quality. The applications for HEVC will not only cover the space of the well known current uses and capabilities of digital video they will also include the deployment of new services and the delivery of enhanced video quality, such as ultra high definition television (UHDTV) and video with higher dynamic range, wider range of representable color, and greater representation precision than what is typically found today. HEVC is the next major generation of video coding design a flexible, reliable and robust solution that will support the next decade of video applications and ease the burden of video on world wide network traffic. This book provides a detailed explanation of the various parts of the standard, insight into how it was developed, and in depth discussion of algorithms and architectures for its implementation.

title: Analysis and architecture design of variable block size motion estimation for H.264/AVC
abstract: Variable block size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter /intra level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs) the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME) Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off chip memory bandwidth and 99.22% on chip memory bandwidth. We demonstrate a 720 p, 30 fps solution at 108 MHz with 330.2k gate count and 208k bits on chip memory

title: Enhanced predictive zonal search for single and multiple frame motion estimation
abstract: Motion Estimation (ME) for video coding has taken an entirely different direction with the emergence of zonal algorithms. These algorithms made it possible to significantly reduce, if not almost eliminate, the tremendous computational overhead of motion estimation that was incurred in a video encoding system, while having little if any loss in quality. In this paper we further improve on these algorithms with the introduction of the Enhanced Predictive Zonal Search Algorithm (EPZS) By considering an additional set of predictors, improving the thresholding process, and simplifying the search pattern employed by these algorithms, we not only manage in achieving better output quality, but also reduce complexity of the motion estimation process even further. Our algorithm was compared with the algorithms accepted in the Optimization Model 1.0 of MPEG 4, and our simulations prove its outright superiority versus the existing algorithms. Furthermore we present a 3 Dimensional implementation of EPZS, which can be easily applied in the case of multiple frame motion estimation (ITU H.263+ and H.26L)