Query: PN code synchronization FPGA

title: A new method for PN code synchronization in the direct sequence spread spectrum communication systems
abstract: Pseudo Noise (PN) code synchronization is of crucial for receiver in direct sequence spread spectrum (DSSS) communication. What's more, acquisition and tracking are two important parts of the synchronization process. To meet the need of a lower power consumption and higher performance, there is a trend to design the digital match filter by using the field programmable gate array (FPGA) or the application specific integrated circuit (ASIC) This paper proposes a new PN code synchronization method based on FPGA and software radio technology. The adaptive threshold detection technology is first used at the acquisition stage to realize the relative judgment. Then the phase demodulation loop based on 1/2 lead lag code is introduced to the tracking stage, which can guarantee the strictly synchronization between the local PN code and the received code. Simulation and actual experiment results validate the performance of the proposed method.

title: Implementation of PN Code Synchronization with FPGA in Burst mode DSSS System
abstract: For the question of PN code acquisition and tracking of spread spectrum signals under large frequency offset circumstance in short term burst mode DSSS system,an algorithm is proposed to achieved PN code synchronization based on sweeping frequency,digital matched filter and DLL.The algorithm is successfully validated based on FPGA hardware platform.The results show that the scheme can meet the system design which achieves PN code acquisition and tracking of spread spectrum signals.

title: Computer simulation of DS/CDMA system pn code synchronization based on FPGA
abstract: The DS/CDMA digital mobile communication system is based on Spread spectrum technique and CDMA technique.PN code synchr onization includes PN code acquidng and tracking.The computer simulation also includes PN code produced,the sender signal simulati on,and the phase discriminator in the receiver.The main function is realized in VHDL language in the system.The simulation of PN code acquiring is carded out in the software quartusll based on FPGA.The simulation conclusion is correct.

title: Detection Technique Of Hybrid PN Code Synchronization For CDMA Personal Wireless Communications
abstract: The hybrid parallel acquisition system described in our previous work  is designed using the Very High Speed ICs Hardware Description Language (VHDL) and is synthesized onto the XC4013 FPGA. It is shown from the results that without recording the delay of each sample collected in the memory, the hybrid acquisition system can be implemented.

title: Detection Technique Of Hybrid PN Code Synchronization For CDMA Personal Wireless Communications
abstract: The hybrid parallel acquisition system described in our previous work  is designed using the Very High Speed ICs Hardware Description Language (VHDL) and is synthesized onto the XC4013 FPGA. It is shown from the results that without recording the delay of each sample collected in the memory, the hybrid acquisition system can be implemented.

title: A Novel Fast Clocking PN Code Acquisition Synchronizer
abstract: Pseudo Noise (PN) code is one of the most well known codes for spreading and secure information in Wireless Communication Systems (WCS) and recently for estimating the carrier and the frame timing information for advanced multipath resistive OFDM systems. Synchronization, with its two steps (acquisition and tracking) is a challenging task for such Multiple Access Systems (MAS) In this paper a Novel Fast Clocking Acquisition Synchronizer (NFCAS) which is based on parallel code phases comparison is designed, modeled, simulated and practically implemented using Field Programmable Gate Array (FPGA) In the proposed synchronizer a fast clock is introduced to speed up the synchronization process. The synchronizer shows a very fast, reliable and direct synchronization in one step rather than two steps. Also the simulation and practical results show a perfect consistency for codes synchronization time which is inversely proportional to the ratio between the introduced fast acquisition clock and the common (transmitter/receiver) traditional slow clock.

title: The Research of Code Synchronization of Spread Spectrum Communication System Based on FPGA
abstract: In direct sequence (DS) spread spectrum communication system, the first condition of receiving correct data is code synchronization. Synchronization is one of the key techniques in spread spectrum communication systems. This paper presents pseudo noise (PN) code acquisition and tracking technology. Spread spectrum communication technology is combined with software radio technology to constitute spread spectrum communication system based on software radio technology. Analog circuit design time can be bypassed. And volume, weight and cost of communication equipment are also greatly reduced. Simulation results are given in this paper.

title: FPGA Implementation of PN Code Acquisition Based on Software Radio
abstract: Spread spectrum technology can effectively solve the problems such as bad channel environment, multi path fading etc between mobile station and subscribers. At present the research on the synchronization of PN code is more concentrated on how to implement fast acquisition. This paper introduces the sliding correlation method of PN code acquisition, gives out a serial and parallel acquisition method which is suitable for the mobile communication, and designs circuit under electronic design software Quartus II using VHDL. At last the accuracy of this method was verified on FPGA.

title: Implementation Architecture of Mached filter for Short PN Code Acquisition
abstract: PN code acquisition is an important part of PN code synchronization in spread spectrum communication system,and the acquisition method based on matched filter is appropriate for short PN code acquisition because of its short acquisition time.In order to solve the problem that digital matched filter occupies too much device resources,the paper introduces an implementation architecture of matched filter based on FPGA,which is suitable for the application in which signal is over sampled.This architecture needs no multiplier unit and reduces the number of adders,meanwhile it doesn't increase the complexity of the system

title: PN Chip Clock Generator for CDMA Code Synchronization
abstract: In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.