Query: WAFER classification

title: Automatic Reclaimed Wafer Classification Using Deep Learning Neural Networks
abstract: Silicon wafer is the most crucial material in the semiconductor manufacturing industry. Owing to limited resources, the reclamation of monitor and dummy wafers for reuse can dramatically lower the cost, and become a competitive edge in this industry. However, defects such as void, scratches, particles, and contamination are found on the surfaces of the reclaimed wafers. Most of the reclaimed wafers with the asymmetric distribution of the defects, known as the "good (G)" reclaimed wafers, can be re polished if their defects are not irreversible and if their thicknesses are sufficient for re polishing. Currently, the "no good (NG)" reclaimed wafers must be first screened by experienced human inspectors to determine their re usability through defect mapping. This screening task is tedious, time consuming, and unreliable. This study presents a deep learning based reclaimed wafers defect classification approach. Three neural networks, multilayer perceptron (MLP) convolutional neural network (CNN) and Residual Network (ResNet) are adopted and compared for classification. These networks analyze the pattern of defect mapping and determine not only the reclaimed wafers are suitable for re polishing but also where the defect categories belong. The open source TensorFlow library was used to train the MLP, CNN, and ResNet networks using collected wafer images as input data. Based on the experimental results, we found that the system applying CNN networks with a proper design of kernels and structures gave fast and superior performance in identifying defective wafers owing to its deep learning capability, and the ResNet averagely exhibited excellent accuracy, while the large scale MLP networks also acquired good results with proper network structures.

title: Functional Logistic Regression based on Constant Splines for Wafer Classification

title: Bin2Vec: A Better Wafer Bin Map Coloring Scheme for Comprehensible Visualization and Effective Bad Wafer Classification
abstract: A wafer bin map (WBM) which is the result of an electrical die sorting test, provides information on which bins failed what tests, and plays an important role in finding defective wafer patterns in semiconductor manufacturing. Current wafer inspection based on WBM has two problems: good/bad WBM classification is performed by engineers and the bin code coloring scheme does not reflect the relationship between bin codes. To solve these problems, we propose a neural network based bin coloring method called Bin2Vec to make similar bin codes are represented by similar colors. We also build a convolutional neural network based WBM classification model to reduce the variations in the decisions made by engineers with different expertise by learning the company wide historical WBM classification results. Based on a real dataset with a total of 27,701 WBMs, our WBM classification model significantly outperformed benchmarked machine learning models. In addition, the visualization results of the proposed Bin2Vec method makes it easier to discover meaningful WBM patterns compared with the random RGB coloring scheme. We expect the proposed framework to improve both efficiencies by automating the bad wafer classification process and effectiveness by assigning similar bin codes and their corresponding colors on the WBM.

title: Joint modeling of classification and regression for improving faulty wafer detection in semiconductor manufacturing
abstract: In the semiconductor manufacturing process, it is important to identify wafers on which faults have occurred or will occur to avoid unnecessary and costly further processing and physical inspections. This issue can be addressed by formulating the faulty wafer detection problem as a predictive modeling task, in which the process parameters/measurements and subsequent inspection results concerning the faults comprise the input and output variables at the wafer level, respectively. To achieve improved predictive performance, this paper presents a joint modeling method that incorporates classification and regression tasks into a single prediction model. Given the output variables in both binary and continuous forms, the prediction model simultaneously considers both the classification and regression tasks to complement each other, where each task predicts the binary and continuous output variables, respectively. The outputs from these two tasks are combined to predict whether a wafer is faulty. The entire model is implemented as a neural network, and is trained by optimizing a single objective function. The effectiveness of the model is demonstrated with a case study using real world data from a semiconductor manufacturer.

title: A Semi Supervised and Incremental Modeling Framework for Wafer Map Classification
abstract: Wafer map analysis provides critical information for quality control and yield improvement tasks in semiconductor manufacturing. In particular, wafer patterns of gross failing areas (GFA) are important clues to identify the causes of relevant failures during the manufacturing process. In this work, a semi supervised classification framework is proposed for wafer map analysis, and its application to wafer bin maps with GFA patterns classification is demonstrated. The Ladder network and the semi supervised variational autoencoder are adopted to classify wafer bin maps in comparison with a standard convolutional neural network (CNN) model on two real world datasets. The results have illustrated that two semi supervised models are consistently and substantially better than the CNN model across various training data percentages by effective utilization of the unlabeled data. Active learning and pseudo labeling are also utilized to accelerate the learning curve.

title: Wafer map defect pattern classification based on convolutional neural network features and error correcting output codes
abstract: Defect clusters on the wafer map can provide important clue to identify the process failures so that it is important to accurately classify the defect patterns into corresponding pattern types. In this research, we present an image based wafer map defect pattern classification method. The presented method consists of two main steps: without any specific preprocessing, high level features are extracted from convolutional neural network and then the extracted features are fed to combination of error correcting output codes and support vector machines for wafer map defect pattern classification. To the best of our knowledge, no prior work has applied the presented method for wafer map defect pattern classification. Experimental results tested on 20,000 wafer maps show the superiority of presented method and the overall classification accuracy is up to 98.43%

title: Convolutional Neural Network for Wafer Surface Defect Classification and the Detection of Unknown Defect Class
abstract: An automatic defect classification (ADC) system identifies and classifies wafer surface defects using scanning electron microscope images. By classifying defects, manufacturers can determine whether the wafer can be repaired and proceed to the next fabrication step. Current ADC systems have high defect detection performance. However, the classification power is poor. In most work sites, defect classification is performed manually using the naked eye, which is unreliable. This paper proposes an ADC method based on deep learning that automatically classifies various types of wafer surface damage. In contrast to conventional ADC methods, which apply a series of image recognition and machine learning techniques to find features for defect classification, the proposed model adopts a single convolutional neural network (CNN) model that can extract effective features for defect classification without using additional feature extraction algorithms. Moreover, the proposed method can identify defect classes not seen during training by comparing the CNN features of the unseen classes with those of the trained classes. Experiments with real datasets verified that the proposed ADC method achieves high defect classification performance.

title: Wafer Classification Using Support Vector Machines
abstract: Increasing yield is a primary concern to integrated circuit manufacturing companies as it dictates the readiness of a new process for high volume manufacturing. In order to expedite the process of discovering yield issues, companies have started looking for ways to perform early prediction for such issues. This paper suggests the use of the support vector machines (SVMs) for early wafer classification. The choice of SVM is motivated by the model's ability to effectively classify multivariate, multimodal, and inseparable data points. This model uses multidimensional hyperplanes to separate and classify wafers into low yield and high yield classes. This paper includes a proposal for how the classification model can be applied for yield classification and how it can be adaptively updated in a manufacturing environment. We show how the values for the SVM parameters can be selected for best yield classification. Furthermore, performance evaluation is conducted on real manufacturing data, comparing the proposed SVM classifier to state of the art. Results show that in all cases, SVM consistently outperforms other methods with and without adaptive model updates. The experiments also show that all classifiers' performances depend on yield thresholds. It is also shown that the classification model can be built and executed using a reduced set without compromising its accuracy.

title: A Light Weight Neural Network for Wafer Map Classification Based on Data Augmentation
abstract: In the semiconductor industry, the testing section has always played an important role. The testing section often requires engineers to judge the defect, which wastes a lot of time and cost. The accurate classification can provide useful information for engineers through neural networks. In this paper, we present a method for wafer map data augmentation and defect classification. Data augmentation is based on CNN encoder decoder and the classification is based on depthwise separable convolutions. There are two datasets used, one is open dataset WM 811K and the other is built with a Taiwan company. We train two models with mobilenetV1 and V2 for the different datasets. The light weight deep convolution can reduce model parameters and calculations, which is very efficient for the testing house with large production volumes. On two different data sets, our proposed method can reduce the number of parameters by 30% and 95% and reduce the amount of calculation by 75% and 25% respectively. The test accuracy of the first dataset is 93.95% The second dataset test accuracy is 87.04% After the data augmentation, accuracy is increased to 97.01% and 95.09% respectively.

title: Active Learning of Convolutional Neural Network for Cost Effective Wafer Map Pattern Classification
abstract: Wafer maps provide important information for engineers for detecting root causes of failure in a semiconductor manufacturing process. Thus, there has been active research into the automation of wafer map pattern classification. With recent advances in deep learning, a convolutional neural network (CNN) has yielded state of the art performance in wafer map pattern classification. Because a large amount of labeled training data is required, experienced engineers need to annotate large quantities of wafer maps manually which is costly. To construct a well performing CNN model with a lower labeling cost, we propose a cost effective wafer map pattern classification system based on the active learning of a CNN. In the system, a CNN model is constructed based on four main steps: uncertainty estimation, query wafer selection, query wafer labeling, and model update. By repetitively performing these steps, the performance of the CNN model is gradually and effectively increased. We compared several methods for uncertainty estimation and query wafer selection in our system. We demonstrated the effectiveness of the proposed system through experiments using real world data from a semiconductor manufacturer.