Point-to-point connectivity between neuromorphic chips using address events

I discuss connectivity between neuromorphic chips, which use the timing of fixed-height, fixed-width, pulses to encode information. Address-events—log2(N)-bit packets that uniquely identify one of N neurons—are used to transmit these pulses in real-time on a random-access, time-multiplexed, communication channel. Activity is assumed to consist of neuronal ensembles—spikes clustered in space and in time. I quantify tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and conclude that an arbitered channel design is the best choice. I implement the arbitered channel with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, I show how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to √ N) by organizing neurons into rows and columns, and reduced in time (from log2(N) to 2) by exploiting locality in the arbiter tree and in the row–column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog–digital systems are described.  Spiking Neurons, Interchip Communication, Asynchronous Logic Synthesis, Virtual Wiring. I. Connectivity in Neuromorphic Systems E are far from matching either the efficacy of neural computation or the efficiency of neural coding. Computers use a million times more energy per operation than brains do . Video cameras uses a thousand times more bandwidth per bit of information than retinas do (see Section II-A). We cannot replace damaged parts of the nervous system because of these shortcomings. To match nature’s computational performance and communication efficiency, we must co-optimize information processing and energy consumption. A small—but growing—community of engineers is attempting to build autonomous sensorimotor systems that match the efficacy and efficiency of their biological counterparts by recreating the function and structure of neural systems in silicon. Taking a structure-to-function approach, these neuromorphic systems go beyond bioinspiration [2], copying biological organization as well as function , , . Neuromorphic engineers are using garden-variety VLSI CMOS technology to achieve their goal [6]. This effort is facilitated by similarities between VLSI hardware and neural wetware. Both technologies: • Provide millions of inexpensive, poorly-matched devices. • Operate in the information-maximizing low-signal-tonoise/high-bandwidth regime. K. A. Boahen morphs brains into silicon at the Bioengineering Dept, University of Pennsylvania, Philadelphia PA 19104-6392.  kwabena@neuroengineering.upenn.edu And challenged by these fundamental differences: • Fan-ins and fan-outs are about ten in VLSI circuits versus several thousand in neural circuits. • Most digital VLSI circuits are synchronized by an external clock, whereas neurons use the degree of coincidence in their firing times to encode information. Neuromorphic engineers have adopted time-division multiplexing to achieve massive connectivity, inspired by its success in telecommunications [7] and computer networks . The number of layers and pins offered by commercial microfabrication and chip-packaging technologies are severely limited. Multiplexing leverages the 5-decade difference in bandwidth between a neuron (hundreds of Hz) and a digital bus (tens of megahertz), enabling us to replace thousands of dedicated point-to-point connections with a handful of high-speed metal wires and thousands of switches (transistors). It pays off because transistors occupy less area than wires, and are becoming relatively more compact in deep submicron processes. In adapting existing networking solutions, neuromorphic architects are challenged by huge differences between the requirements of computer networks and those of neuromorphic systems. Whereas computer networks connect thousands of computers at the buildingor campus-level, neuromorphic systems need to connect millions of neurons at the chipor circuit-board level. Hence, they must improve the efficiency of traditional computer communication architectures, and protocols, by several orders of magnitude. Mahowald and Sivilotti proposed using an address-event representation to transmit pulses, or spikes, from an array of neurons on one chip to the corresponding location in an array on a second chip [9], , . In their scheme, depicted in Figure 1, an address-encoder generates a unique binary address for each neuron whenever it spikes. A bus transmits these addresses to the receiving chip, where an address decoder selects the corresponding location. Eight years after Mahowald and Sivilotti proposed it, the address-event representation (AER) has emerged as the leading candidate for communication between neuromorphic chips. Indeed, at the NSF Neuromorphic Engineering Workshop held in June/July 1997 at Telluride CO, the AER Interchip Communication Workgroup was in the top two—second only to Mindless Robots in popularity [11]! The performance of the original point-to-point protocol has been greatly improved. Efficient hierarchical arbitration circuits have been developed to handle oneand two-dimensional arrays [12], [13], . Sender and receiver interfaces have been combined on a single chip to build a transceiver [15]. Support for multiple senders and receivers [16], , , one-dimensional nearest-neighbor– IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS, VOL. XX, NO. Y, MONTH 1999 101