A flat, timing-driven design system for a high-performance CMOS processor chipset
We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server-Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We show that the density in terms of transistors per mm/sup 2/ is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort.

title: Power-delay product minimization in high-performance 64-bit carry-select adders
abstract: This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.

title: Standard-cell-based design methodology for high-performance support chips
abstract: We describe the methodology used for the design of a set of CMOS support chips used in the IBM S/390® Parallel Enterprise Server Generations 3 and 4. The logic design is based on functional units, and the majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. Custom library elements are used wherever needed for performance reasons. Using this approach, a density has been achieved that is comparable to those of contemporary custom designs, combined with very attractive turnaround times.

title: Performance Evaluation of the PVFS2 Architecture
abstract: As the complexity of parallel file systems' software stacks increases it gets harder to reveal the reasons for performance bottlenecks in these software layers. This paper introduces a method which eliminates the influence of the physical storage on performance analysis in order to find these bottlenecks. Also, the influence of the hardware components on the performance is modeled to estimate the maximum achievable performance of a parallel file system. The paper focuses on the parallel virtual file system 2 (PVFS2) and shows results for the functionality file creation, small contiguous I/O requests and large contiguous I/O requests

title: Bottleneck Detection in Parallel File Systems with Trace-Based Performance Monitoring
abstract: Today we recognize a high demand for powerful storage. In industry this issue is tackled either with large storage area networks, or by deploying parallel file systems on top of RAID systems or on smaller storage networks. The bigger the system gets the more important is the ability to analyze the performance and to identify bottlenecks in the architecture and the applications. 
 
We extended the performance monitor available in the parallel file system PVFS2 by including statistics of the server process and information of the system. Performance monitor data is available during runtime and the server process was modified to store this data in off-line traces suitable for post-mortem analysis. These values can be used to detect bottlenecks in the system. Some measured results demonstrate how these help to identify bottlenecks and may assists to rank the servers depending on their capabilities.

title: Small-file access in parallel file systems
abstract: Today's computational science demands have resulted in ever larger parallel computers, and storage systems have grown to match these demands. Parallel file systems used in this environment are increasingly specialized to extract the highest possible performance for large I/O operations, at the expense of other potential workloads. While some applications have adapted to I/O best practices and can obtain good performance on these systems, the natural I/O patterns of many applications result in generation of many small files. These applications are not well served by current parallel file systems at very large scale. This paper describes five techniques for optimizing small-file access in parallel file systems for very large scale systems. These five techniques are all implemented in a single parallel file system (PVFS) and then systematically assessed on two test platforms. A microbenchmark and the mdtest benchmark are used to evaluate the optimizations at an unprecedented scale. We observe as much as a 905% improvement in small-file create rates, 1,106% improvement in small-file stat rates, and 727% improvement in small-file removal rates, compared to a baseline PVFS configuration on a leadership computing platform using 16,384 cores.

title: Developing Applications for Multicomputer Systems on Workstation Clusters
abstract: Much computational power on state-of-the-art multicomputers like the Paragon is wasted with porting applications. Using networks of workstations is an attempt to withdraw this workload from multicomputer systems. Therefore an environment is needed which provides the programming interface of multicomputers on coupled workstations. The paper describes the design and implementation of the NXLib environment which allows to use Ethernet coupled workstations as a development platform for applications targeted for Intel Paragon systems.

title: A strategy for cost efficient distributed data storage for in-memory OLAP
abstract: With the availability of inexpensive blade servers featuring 32 GB or more of main memory, memory-based engines such as the SAP NetWeaver Business Warehouse Accelerator are coming into widespread use for online analytic processing (OLAP) of terabyte data volumes. Data storage for such engines is often implemented in standard storage technologies like storage area network (SAN) or network attached storage (NAS) with high hardware costs. Given the access pattern, storage costs can be reduced by using a distributed persistence layer based on commodity architecture. We discuss an example of an in-memory OLAP engine with a focus on storage architecture. We then present an implementation of a distributed persistence layer that is optimized for the access pattern of such engines. Finally, we show the cost-saving potential and discuss the performance impact compared to SAN systems.