A circuit level fault model for resistive opens and bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.

title: Longest-path selection for delay test under process variation
abstract: Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay among all paths through that fault site. There are often multiple longest paths for each fault site in the circuit, due to different process conditions. To detect the smallest delay fault, it is necessary to test all longest paths through the fault site. However, previous methods are either inefficient or their results include too many paths that are not longest.This paper presents an efficient method to generate the longest path set for delay test under process variation. To capture both structural and systematic process correlation, we use linear delay functions to express path delays under process variation. A novel path-pruning technique is proposed to discard paths that are not longest, resulting in a significantly reduction in the number of paths compared with the previous best method. The new method can be applied to any process variation as long as its impact on delay is linear.

title: Probabilistic Congestion Prediction with Partial Blockages
abstract: Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing congestion. Using a probabilistic technique instead of a global router has the advantage of speed and easy updating. Previously proposed probabilistic models (Lou, et al., 2001) (Westra et al., 2004) do not account for wiring that may already be fixed in the design, e.g., due to macro blocks or power rails. These "partial wiring blockages" certainly influence the global router, so they should also influence a probabilistic routing prediction algorithm. This work proposes a probabilistic congestion prediction metric that extends the work of (Westra et al., 2004) to model partial wiring blockages. The authors also show a new fast algorithm to efficiently generate the congestion map and demonstrate the effectiveness of our methods on real routing problems

title: Process variation dimension reduction based on SVD.
abstract: We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and timing analysis under process variation can be performed efficiently. Our algorithm reduces the number of process variation variables while preserving the delay function with respect to process variation. Compared with the principal component analysis (PCA) method, our algorithm requires less computation time and guarantees the reduced process variation variables are independent. Experimental results on ISCAS85 circuits show that the algorithm works well. 1 INTROCUTION In modern multi-layer VLSI circuits, the dimension of the process variation is large. For example, in a k-metal technology, there are 2k variables for metal width and thickness, k variables for inter-layer dielectric (ILD) thickness, a gate length variable, and some other variables. With such a large number of process variation variables, timing analysis under process variation is very time consuming, and may not find the worst-case process corner [1][2]. In this paper, we propose the novel concept of variation dimension reduction. The idea is originated from the following observation. For different nets, the underlying process variation variables are the same. Therefore, the delays of the nets are correlated. We model the delay from an input pin of a cell to an input pin of a downstream cell, also known as the buffer-to-buffer delay, as a linear function of process variation variables: d = dnominal(1 + a1x1 + a2x2 + ... + anxn), where x1, x2, ..., xn are process variation variables, a1, a2, ..., an are their corresponding coefficients, and dnominal is the nominal delay. For different nets, the coefficients are different, but the process variation variables are the same. The assumption that the delay is linear with respect to each process variation variable is supported by SPICE simulation of real circuits within reasonable ranges of the process variation . There are many forms of process variation [4][5]. In this paper, we only consider systematic process variation and assume the process variation variables among different nets are fully correlated. We assume the following variation ranges: metal thickness ±20%, metal width ±10%, ILD thickness ±40%, and gate length ±10%. To obtain the delay function with respect to process variation, we first extract interconnect parasitic from the layout and compute the nominal buffer-to-buffer delay for all nets. Then for each process variation variable, we modify the layout or the technology file by varying a specified amount (for example, +10% for metal1 thickness), and perform RC extraction and delay evaluation for the modified layout. The coefficient for this process variation variable is obtained by interpolating the two delays. Recently, the principal component analysis (PCA) method was used to reduce the dimension of process variation . It was shown to be effective for analyzing analog circuits under process variation. However, the PCA method is inefficient for digital circuits, because the PCA method constructs and solves a correlation matrix of size mn×mn, where n is the number of process variation variables and m is the number of nets or devices. For digital circuits, m is easily in hundreds or thousands. In this paper, we propose a new method based on singular value decomposition (SVD) . Our algorithm detects the linear dependence and reduces the number of process variation variables, while minimizing the average error of the delay. Note that although the PCA method also uses SVD, their matrix is size mn×mn while ours is size m×n. To make the reduced process variables linearly/statistically independent, which is desirable for fault simulation and timing analysis, we also propose a sub-matrix SVD method. In Section 2, the SVD method and sub-matrix SVD method for dimension reduction are given. In Section 3, we show the experimental results. It shows that if we simply pick the most important process variation variables and discard the rest, then the average error of net delay is twice as much as the average error produced by our algorithm. 2 ALGORITHM 2.1 Singular Value Decomposition (SVD) The SVD method is based on the following theorems . Theorem 1 If A is an m×n matrix, then there exist orthogonal m×m matrix U=[u1,...,um] and n×n matrix V=[v1,...,vn], such that U·A·V=diag(σ1,...,σp), which is an m×n matrix, p=min{m,n}, and σ1 ≥ σ2 ≥...≥ σp ≥ 0. The σi’s are the singular values of A, and vectors ui and vi are the ith left and right singular vector, respectively. The process to find U and V is called SVD. It can be done by the Golub-Reinsch algorithm of time complexity O(mn+mn+n)  (pp. 254). To compute U(:,1:n) =[u1,...,un], which is an m×n (m>n) matrix, the time complexity is O(mn+n) . Theorem 2 Let the SVD of m×n matrix A be defined in Theorem 1. If r < rank(A) and let ∑ = = r i T i i i v u A 1 * σ , then 1 2 * 2 ) ( min + = = − = − r r B rank A A B A σ . In other words, A is the best 2-norm approximation of A among all rank r matrices.  Application to Dimension Reduction We are given the delay of m nets represented as Ax, where A is an m×n matrix, n is the number of process variation variables, x=[x1,...,xn] is the vector of process variation variables, and xi’s are independent of each other. From Theorem 2, A=U(:,1:r)·S·V(:,1:r), where S=diag(σ1,...,σr), U(:,1:r)=[u1,...,ur], and V(:,1:r) =[v1,...,vr]. Therefore, Ax≈Ax=U(:,1:r)·S·V(:,1:r)x=Bz, where B=U(:,1:r)·S is an m×r matrix and z=V(:,1:r)x is an r×1 vector. Since the dimension of B is much less than the dimension of A, we use Bz to approximate Ax. If we just want to reduce the number of process variation variables, then Bz is the resulting delay function, and z is the vector of new process variation variables. However, we often have an additional requirement from circuit simulation that the new process variation variables z1, ..., zr must be independent. For example, if z1=x1−x2+x3 and z2=x1+x2−x3, then z1 and z2 are not independent although the number of variables is reduced from 3 to 2. 2.3 Sub-Matrix SVD (SMSVD) We propose a sub-matrix SVD method (SMSVD) to ensure the independence between zi’s. The basic idea is to partition columns of A into r sub-matrices, and then use SVD on each sub-matrix. The following is the algorithm: 1) Partition A into sub-matrices A1, A2, ..., Ar, where A=[A1, A2,..., Ar]. Ai is an m×qi matrix, i=1,..., r. 2) For i=1,..., r, compute the approximation matrix Ai of Ai through SVD in which the approximation rank is 1. Define SVD of Ai as Ui·Ai·Vi=diag(σi1,...,σip), then Ai=Ui(:,1)·σi1·Vi(:,1) and ║Ai−Ai║2=σi2. 3) Construct B=[U1(:,1)σ11, U2(:,1)σ21, ..., Ur(:,1)σr1],

title: Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
abstract: As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer insertion algorithms (e.g., [7, 6, 15]) are based on van Ginneken's dynamic programming paradigm [14]. However, van Ginneken's original algorithm does not control buffering resources and tends to over-buffering, thereby wasting area and power. It has been a major open problem whether it is possible to optimize slack and at the same time minimize the buffer usage.This paper settles this open problem by showing that for arbitrary integer cost functions, the problem is NP-complete. We also extend the pre-buffer slack technique [12] to minimize the buffer cost. This technique can significantly reduce the running time and memory in buffer cost minimization problem. The experimental results show that our algorithm can speed up the running time up to 17 times and reduces the memory to 1/30 of traditional best know algorithm. Finally, we show how to efficiently deal with multiway merge in buffer insertion.

title: Longest-path selection for delay test under process variation
abstract: Under manufacturing process variation, a path through a net is called longest if there exists a process condition under which the path has the maximum delay among all paths through the net. There are often multiple longest paths for each net, due to different process conditions. In addition, a local defect, such as resistive open or a resistive bridge, increases the delay of the affected net. To detect delay faults due to local defects and process variation, it is necessary to test all longest paths through each net. Previous approaches to this problem were inefficient because of the large number of paths that are not longest. This paper presents an efficient method to generate the set of longest paths for delay test under process variation. To capture both structural and process correlation between path delays, we use linear delay functions to express path delays under process variation. A novel technique is proposed to prune paths that are not longest, resulting in a significant reduction in the number of paths. In experiments on International Symposium on Circuits and Systems (ISCAS) circuits, our number of longest paths is 1-6% of the previous best approach, with 300/spl times/ less running time.

title: An iterative method for hypothetical reference decoder
abstract: In this paper, we propose a simple iterative method to verify whether a coded bitstream conforms to a hypothetical reference decoder (HRD). A concept of maximum tolerate delay (MTD) is introduced to study the possible low-delay operation such that we can bound the degree of incorrect motion rendition caused by the variation in end to end delay in the neighborhood of big pictures. Our method can be used in the design of a rate control algorithm to improve the possibility for the coded bitstream that conforms to the HRD.

title: Reverse Hashing for High-Speed Network Monitoring: Algorithms, Evaluation, and Applications
abstract: A key function for network traffic monitoring and analysis is the ability to perform aggregate queries over multiple data streams. Change detection is an important primitive which can be extended to construct many aggregate queries. The recently proposed sketches (Krishnamurthy, 2003) are among the very few that can detect heavy changes online for high speed links, and thus support various aggregate queries in both temporal and spatial domains. However, it does not preserve the keys (e.g., source IP address) of flows, making it difficult to reconstruct the desired set of anomalous keys. In an earlier abstract we proposed a framework for a reversible sketch data structure that offers hope for efficient extraction of keys (Schweller, 2004). However, this scheme is only able to detect a single heavy change key and places restrictions on the statistical properties of the key space. To address these challenges, we propose an efficient reverse hashing scheme to infer the keys of culprit flows from reversible sketches. There are two phases. The first operates online, recording the packet stream in a compact representation with negligible extra memory and few extra memory accesses. Our prototype single FPGA board implementation can achieve a throughput of over 16 Gbps for 40-byte-packet streams (the worst case). The second phase identifies heavy changes and their keys from the representation in nearly real time. We evaluate our scheme using traces from large edge routers with OC-12 or higher links. Both the analytical and experimental results show that we are able to achieve online traffic monitoring and accurate change/intrusion detection over massive data streams on high speed links, all in a manner that scales to large key space size. To the best of our knowledge, our system is the first to achieve these properties simultaneously.

title: A Compiler Framework for Tiling Imperfectly-Nested Loops
abstract: This paper presents an integrated compiler framework for tiling a class of nontrivial imperfectly-nested loops such that cache locality is improved. We develop a new memory cost model to analyze data reuse in terms of both the cache and the TLB, based on which we compute the tile size with or without array duplication. We determine whether to duplicate arrays for tiling by comparing the respective exploited reuse factors. The preliminary results with several benchmark programs show that the transformed programs achieve a speedup of 1.09 to 3.82 over the original programs.

title: Chromatic sums of 2-edge-connected maps on the plane
abstract: This paper provides the chromatic sum function equation of rooted 2-edge-connected maps on the plane. The enumerating function equations of rooted biloopless maps, rooted nonseparable maps, rooted 2-edge-connected bipartite maps and rooted loopless Eulerian maps on the plane are derived by the chromatic sum function equation of rooted 2-edge-connected maps on the plane. Moreover, some explicit expressions of enumerating functions are also derived.

title: Haplotype reconstruction from SNP fragments by minimum error correction
abstract: Haplotype reconstruction based on aligned single nucleotide polymorphism (SNP) fragments is to infer a pair of haplotypes from localized polymorphism data gathered through short genome fragment assembly. An important computational model of this problem is the minimum error correction (MEC) model, which has been mentioned in several literatures. The model retrieves a pair of haplotypes by correcting minimum number of SNPs in given genome fragments coming from an individual's DNA.



In the first part of this paper, an exact algorithm for the MEC model is presented. Owing to the NP-hardness of the MEC model, we also design a genetic algorithm (GA). The designed GA is intended to solve large size problems and has very good performance. The strength and weakness of the MEC model are shown using experimental results on real data and simulation data. In the second part of this paper, to improve the MEC model for haplotype reconstruction, a new computational model is proposed, which simultaneously employs genotype information of an individual in the process of SNP correction, and is called MEC with genotype information (shortly, MEC/GI). Computational results on extensive datasets show that the new model has much higher accuracy in haplotype reconstruction than the pure MEC model.