Bounding Worst-Case Response Times of Tasks under PIP
Schedulability theory in real-time systems requires prior knowledge of the worst-case execution time (WCET) of every task in the system. One method to determine the WCET is known as static timing analysis. Determination of the priorities among tasks in such a system requires a scheduling policy, which could be either preemptive or non-preemptive. While static timing analysis and data cache analysis are simplified by using a fully non-preemptive scheduling policy,it results in decreased schedulability. In prior work, a methodology was proposed to bound the data-cache related delay for real-time tasks that, beside having anon-preemptive region (critical section), can otherwise be scheduled preemptively.While the prior approach improves schedulability in comparison to fully non-preemptive methods, it is still conservative in its approach due to its fundamental assumption that a task executing in a critical section may not be preempted by any other task. In this paper, we propose a methodology that incorporates resource sharing policies such as the Priority Inheritance Protocol(PIP) into the calculation of data-cache related delay. In this approach, access to shared resources, which is the primary reason for critical sections within tasks, is controlled by the resource sharing policy. In addition to maintaining correctness of access, such policies strive to limit resource access conflicts,thereby improving the responsiveness of tasks.To the best of our knowledge, this is the first framework that integrates data-cache related delay calculations with resource sharing policies in the context of real-time systems.

title: 2006 WCET Preface - Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time Analysis (WCET'06)
abstract: On the 4th of July, 2006, the 6th International Workshop onWorst-Case Execution Time Analysis (WCET'06) 
was held in Dresden, Germany, co-located with the 18th Euromicro International Conference on Real-Time 
Systems (ECRTS'06), both with support of Euromicro Technical Committee. The goal of the workshop was 
to bring together people from academia, tool vendors and users in industry that are interested in all aspects 
of timing analysis for real-time systems. The workshop provided a relaxed forum to present and discuss 
new ideas, new research directions, and to review current trends in this area. The workshop was based on 
short presentations that should encourage discussion by the attendees.

title: Source-Code-Correlated Cache Coherence Characterization of OpenMP Benchmarks
abstract: Cache coherence in shared-memory multiprocessor systems has been studied mostly from an architecture viewpoint, often by means of aggregating metrics. In many cases, aggregate events provide insufficient information for programmers to understand and optimize the coherence behavior of their applications. A better understanding would be given by source code correlations of not only aggregate events, but also finer granularity metrics directly linked to high-level source code constructs, such as source lines and data structures. In this paper, we explore a novel application-centric approach to studying coherence traffic. We develop a coherence analysis framework based on incremental coherence simulation of actual reference traces. We provide tool support to extract these reference traces and synchronization information from OpenMP threads at runtime using dynamic binary rewriting of the application executable. These traces are fed to ccSIM, our cache-coherence simulator. The novelty of ccSIM lies in its ability to relate low-level cache coherence metrics (such as coherence misses and their causative invalidations) to high-level source code constructs including source code locations and data structures. We explore the degree of freedom in interleaving data traces from different processors and assess simulation accuracy in comparison to metrics obtained from hardware performance counters. Our quantitative results show that: 1) Cache coherence traffic can be simulated with a considerable degree of accuracy for SPMD programs, as the invalidation traffic closely matches the corresponding hardware performance counters. 2) Detailed, high-level coherence statistics are very useful in detecting, isolating, and understanding coherence bottlenecks. We use ccSIM with several well-known benchmarks and find coherence optimization opportunities leading to significant reductions in coherence traffic and savings in wall-clock execution time

title: MOLAR: adaptive runtime support for high-end computing operating and runtime systems
abstract: MOLAR is a multi-institutional research effort that concentrates on adaptive, reliable, and efficient operating and runtime system (OS/R) solutions for ultra-scale high-end scientific computing on the next generation of supercomputers. This research addresses the challenges outlined in FAST-OS (forum to address scalable technology for runtime and operating systems) and HECRTF (high-end computing revitalization task force) activities by exploring the use of advanced monitoring and adaptation to improve application performance and predictability of system interruptions, and by advancing computer reliability, availability and serviceability (RAS) management systems to work cooperatively with the OS/R to identify and preemptively resolve system issues. This paper describes recent research of the MOLAR team in advancing RAS for high-end computing OS/Rs.

title: Proactive process-level live migration in HPC environments
abstract: As the number of nodes in high-performance computing environments keeps increasing, faults are becoming common place. Reactive fault tolerance (FT) often does not scale due to massive I/O requirements and relies on manual job resubmission. This work complements reactive with proactive FT at the process level. Through health monitoring, a subset of node failures can be anticipated when one's health deteriorates. A novel process-level live migration mechanism supports continued execution of applications during much of processes migration. This scheme is integrated into an MPI execution environment to transparently sustain health-inflicted node failures, which eradicates the need to restart and requeue MPI jobs. Experiments indicate that 1-6.5 seconds of prior warning are required to successfully trigger live process migration while similar operating system virtualization mechanisms require 13-24 seconds. This self-healing approach complements reactive FT by nearly cutting the number of checkpoints in half when 70% of the faults are handled proactively.

title: Introduction to the special issue
abstract: This special issue of TECS is dedicated to a digest of the best papers for the ACM Conference on Languages, Compilers, and Tools for Embedded Systems 2003 (LCTES’03) with sponsorship from SIGPLAN and, since 2004, also from SIGBED. The conference has matured to one of the top high-quality academic venues on embedded systems with a competitive acceptance rate of 23% in 2003. The conference attracts papers on topics ranging from hardware enhancements of embedded architectures over compilation, system development, and analysis tools to modeling of embedded systems. The four papers presented in this issue are extensions of the authors’ conference contributions. The first paper, Dynamic Coalescing for 16-bit Instructions by Arvind Krishnaswamy and Rajiv Gupta, proposes a minor architectural extension to the ARM processor architecture to allow the native 32-bit ARM instructions to be interspersed with the smaller 16-bit Thumb instructions supported by the processor. The authors use compilation techniques to fold two Thumb instruction into a single equivalent ARM instruction, thereby reducing the number of cycles required for execution. They demonstrate that their technique can result both in performance improvements and potentially reduced energy consumption. The second paper, The Implementation and Evaluation of Dynamic Code Decompression using DISE by Marc L. Corliss, E. Christopher Lewis, and Amir Roth, promotes code compression techniques combined with programmable hardware support for postfetch time decompression using their so-called dynamic instruction stream editing (DISE) technique. Special instructions in the application code can reprogram the DISE engine by specifying patterns and parameters for patterns. Once programmed, instruction fetches consisting of compressed code are expanded upon a match. Benefits of this technique are in a significant reduction in code size, improved performance and, to some extend, lower energy consumption. The third paper, Memory Safety Without Runtime Checks or Garbage Collection by Dinakar Dhurajti, Sumant Kowshik, Vikram Adve, and Chris Lattner, describes a set of methods to ensure memory safety without requiring run-time support or user annotations. The idea is to restrict the C language such that a combination of compilation techniques and type-sensitive pool-based memory allocation ensures safe program execution. As a result, array bound checks and null pointer checks can also be removed without risking to violate program semantics. Experimental results demonstrate the applicability of these techniques to a number of C benchmarks. The fourth paper, Schedulability-Driven Frame Packing for MultiCluster Distributed Embedded Systems by Paul Pop, Eles Petru, and Peng Zebo, focuses on packet scheduling for distributed real-time systems. The authors consider timing constraints on packet delivery across a gateway connecting two distinct processor clusters, one that is connected by an event-triggered network using CSMA and another that is connected by a time-triggered architecture using

title: Analysis assistant for single-molecule force spectroscopy data on membrane proteins - MPTV
abstract: Force-distance (F-D) curves of single membrane proteins reveal information on inter- and intramolecular interactions occurring within a protein and between proteins. However, the analysis of single-molecule force spectroscopy data is a time consuming and complex process requiring objective criteria. In most cases the user requires additional information to interpret F-D curves. Therefore we developed a software assistant representing the force or molecular interaction pattern and the topology or the 3D structure of the membrane protein. This representation establishes a basis for detailed interpretation of the protein structure and its underlying molecular interactions. Various integrated bioinformatic features further assist in the interpretation of measured and assigned molecular interactions that determine membrane protein folding, structure, stability and function. Web queries and programs about the topology are directly linked. Motifs, helix types, representation of Venn diagrams and the complete functionality of the program Jmol belong to it.


AVAILABILITY
The program MPTV is freely available from the website at