Bipartite graphs containing every possible pair of cycles
Let G=(V 1 ,V 2 ;E) be a bipartite graph with |V 1 |=|V 2 |=n⩾4 . Suppose that d(x)+d(y)⩾n+2 for all x∈V 1 and y∈V 2 . Then G contains two vertex-disjoint cycles of lengths 2s and 2t , respectively, for any two positive integers s and t with s⩾2 , t⩾2 and s+t⩽n . We also propose a conjecture.

title: Vertex-Disjoint Triangles in Claw-Free Graphs with Minimum Degree at Least Three
abstract: . Our main result is as follows: For any integer , if G is a claw-free graph of order at least and with minimum degree at least 3, then G contains k vertex-disjoint triangles unless G is of order and G belongs to a known class of graphs. We also construct a claw-free graph with minimum degree 3 on n vertices for each such that it does not contain k vertex-disjoint triangles. We put forward a conjecture on vertex-disjoint triangles in -free graphs.

title: On Independent Cycles in a Bipartite Graph
abstract: Let G=(V1,V2;E) be a bipartite graph with 2k≤m=|V1|≤|V2|=n, where k is a positive integer. We show that if the number of edges of G is at least (2k−1)(n−1)+m, then G contains k vertex-disjoint cycles, unless e(G)=(2k−1)(n−1)+m and G belongs to a known class of graphs.

title: Packing Three Copies of a Tree into a Complete Graph
abstract: A three T of order n is said to be 3-placeable if there are three edge-disjoint copies of T in Kn. In this paper we characterize all the trees T such that T is 3-placeable.

title: On Quadrilaterals and Cycle Covers in a Bipartite Graph

title: On Covering a Bipartite Graph with Cycles
abstract: We conjectured in [H. Wang,  (1999), pp. 115--121] that, for each integer $k\geq 2$, there exists N(k) such that if G=(V1,V2;E) is a bipartite graph with $|V_1|=|V_2|=n\geq N(k)$ and d(x)+d(y)\geq n+k$ for each pair of nonadjacent vertices x and y of G with $x\in V_1$ and $y\in V_2$, then for any k independent edges e1, . . ., ek of G, there exist k vertex-disjoint cycles C1, . . . ,Ck in G such that $e_i\in E(C_i)$ for all $i\in\{1,\ldots ,k\}$ and $V(C_1\cup\cdots \cup C_k)=V(G)$. This conjecture is also verified for k=2 in [H. Wang,  (1999), pp. 115--121]. We prove this conjecture for k=3 in this paper.

title: EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system
abstract: Future mainstream microprocessors will likely integrate specialized accelerators, such as GPUs, onto a single die to achieve better performance and power efficiency. However, it remains a keen challenge to program such a heterogeneous multicore platform, since these specialized accelerators feature ISAs and functionality that are significantly different from the general purpose CPU cores. In this paper, we present EXOCHI: (1) Exoskeleton Sequencer(EXO), an architecture to represent heterogeneous acceleratorsas ISA-based MIMD architecture resources, and a shared virtual memory heterogeneous multithreaded program execution model that tightly couples specialized accelerator cores with generalpurpose CPU cores, and (2) C for Heterogeneous Integration(CHI), an integrated C/C++ programming environment that supports accelerator-specific inline assembly and domain-specific languages. The CHI compiler extends the OpenMP pragma for heterogeneous multithreading programming, and produces a single fat binary with code sections corresponding to different instruction sets. The runtime can judiciously spread parallel computation across the heterogeneous cores to optimize performance and power.
 We have prototyped the EXO architecture on a physical heterogeneous platform consisting of an Intel® Core™ 2 Duo processor and an 8-core 32-thread Intel® Graphics Media Accelerator X3000. In addition, we have implemented the CHI integrated programming environment with the Intel® C++ Compiler, runtime toolset, and debugger. On the EXO prototype system, we have enhanced a suite of production-quality media kernels for video and image processing to utilize the accelerator through the CHI programming interface, achieving significant speedup (1.41X to10.97X) over execution on the IA32 CPU alone.

title: Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors

title: Generalized discrete-time PI control of output PDFs using square root B-spline expansion
abstract: A new control approach is proposed for the probability density function (PDF) control of non-Gaussian stochastic systems using PI controllers. Using the square root output PDF model and the weight dynamics, the PDF tracking is transformed to a constrained dynamical tracking control problem for weight dynamics, where LMI techniques are used to design a generalized PI controller such that stability, state constraints and tracking performances can be guaranteed simultaneously.

title: A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors
abstract: The authors propose a new approach for subcube and noncubic processor allocations for hypercube multiprocessors. The main idea is to represent available processors in the system by means of a prime cube graph (PC-graph). The PC-graph maintains the inter-relationships between free subcubes and hence reduces both internal and external processor fragmentations. Their simulation results show that the PC-graph approach outperforms the existing allocation strategies by 25% to 50% under certain load conditions.

title: Minimum entropy control of nonlinear ARMA systems over a communication network
abstract: In this paper, the entropy concept has been utilized to characterize the uncertainty of the tracking error for nonlinear ARMA stochastic systems over a communication network, where time delays in the communication channels are of random nature. A recursive optimization solution has been developed. In addition, an alternative algorithm is also proposed based on the probability density function of the tracking error, which is estimated by a neural network. Finally, a simulation example is given to illustrate the efficiency and feasibility of the proposed approach.