On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers

title: CPR: Composable performance regression for scalable multiprocessor models
abstract: Uniprocessor simulators track resource utilization cycle by cycle to estimate performance. Multiprocessor simulators, however, must account for synchronization events that increase the cost of every cycle simulated and shared resource contention that increases the total number of cycles simulated. These effects cause multiprocessor simulation times to scale superlinearly with the number of cores. Composable performance regression (CPR) fundamentally addresses these intractable multiprocessor simulation times, estimating multiprocessor performance with a combination of uniprocessor, contention, and penalty models. The uniprocessor model predicts baseline performance of each core while the contention models predict interfering accesses from other cores. Uniprocessor and contention model outputs are composed by a penalty model to produce the final multiprocessor performance estimate. Trained with a production quality simulator, CPR is accurate with median errors of 6.63, 4.83 percent for dual-, quad-core multiprocessors. Furthermore, composable regression is scalable, requiring 0.33x the simulations required by prior regression strategies.

title: Register renaming and scheduling for dynamic execution of predicated code
abstract: To achieve higher processor performance requires greater synergy between advanced hardware features and innovative compiler techniques. Recent advancement in compilation techniques for predicated execution has provided significant opportunity in exploiting instruction level parallelism. However, little research has been done on how to efficiently execute predicated code in a dynamic microarchitecture. In this paper, we evaluate hardware optimizations for executing predicated code on a dynamically scheduled microarchitecture. We provide two novel ideas to improve the efficiency of executing predicated code. On a generic Intel Itanium processor pipeline model, we demonstrate that, with some microarchitecture enhancements, a dynamic execution processor can achieve about 16% performance improvement over an equivalent static execution processor.

title: BLoG: Post-Silicon bug localization in processors using bug localization graphs
abstract: Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

title: Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations
abstract: This paper presents key insights and design rationales behind Inferno, a functional simulation construction framework developed at Intel to support execution-driven cycle-accurate performance modeling and simulation of advanced microarchitectural data speculation techniques for future processor designs and explorations. Inferno divides the task of functional simulation into three essential components, namely: (1) context manager of in-flight speculatively executed instructions, (2) stateless emulator of instruction semantics, and (3) a high speed functional simulator capable of booting OS and running large-scale system workloads. These building block components work together in concert via a set of well-architected functional model convergence APIs. With a novel abstraction called speculative domain, the context manager serves effectively as a relational database about the in-flight instructions and on-going speculations. Through a set of functional model usage APIs, the context manager enables performance models to express arbitrary microarchitectural data speculation scenarios. The contribution of this paper is to demonstrate the importance of providing a functional model with modular construction, proper abstraction and expressive APIs for speculative state management. Inferno is such a functional model construction framework and has significantly improved productivity in modeling a variety of sophisticated data speculation microarchitecture techniques.

title: Real-time pose estimation for outdoor mobile robots using range data
abstract: Pose estimation is a key issue in mobile robots and important to moving object tracking. In this paper, we present a tangent based hybrid pose estimation algorithm with real-time performance using range data from laser radar, which consists of Iterative Tangent weighted Closest Point (ITCP) and Hough transform based Tangent Angle Histogram (HTAH) algorithms to overcome problems with past methods, such as local minimum, aperture-like, and high computation problems. The algorithm has been tested on both synthetic and real range data in outdoor environments. Experimental results demonstrate its high accuracy, low computation, wide applicability and high robustness to aperture-like problems, occlusion and noise.

title: Distribution function tracking filter design using hybrid characteristic functions
abstract: A new tracking filtering algorithm for a class of multivariate dynamic stochastic systems is presented. The system is expressed by a set of time-varying discrete systems with non-Gaussian stochastic input and nonlinear output. A new concept, such as hybrid characteristic function, is introduced to describe the stochastic nature of the dynamic conditional estimation errors, where the key idea is to ensure the distribution of the conditional estimation error to follow a target distribution. For this purpose, the relationships between the hybrid characteristic functions of the multivariate stochastic input and the outputs, and the properties of the hybrid characteristic function, are established. A new performance index of the tracking filter is then constructed based on the form of the hybrid characteristic function of the conditional estimation error. An analytical solution, which guarantees the filter gain matrix to be an optimal one, is then obtained. A simulation case study is included to show the effectiveness of the proposed algorithm, and encouraging results have been obtained.

title: Sensor fault estimator and its application for linear multi-variable dynamic systems with delayed state and input
abstract: For systems with multiple time delays, a novel state and sensor noise observer is designed to estimate system states and sensor noises at the same time. In this design, descriptor system approach and linear matrix inequality technique are adopted. Unbounded sensor faults will make the system fail unavoidably, it is indispensable to derive a reliable control scheme against sensor failures. Using the estimated state and sensor fault, a fault-tolerant observer-based controller is proposed, which makes the system work well not matter whether sensor faults occur or not.

title: How to fool an unbounded adversary with a short key
abstract: The symmetric encryption problem which manifests itself when two parties must securely transmit a message m with a short shared secret key is considered in conjunction with a computationally unbounded adversary. As the adversary is unbounded, any encryption scheme must leak information about m; in particular, the mutual information between m and its ciphertext cannot be zero. Despite this, a family of encryption schemes is presented that guarantee that for any message space in {0,1}n with minimum entropy n-lscr and for any Boolean function h:{0,1}n rarr {0,1}, no adversary can predict h(m) from the ciphertext of m with more than 1/nomega(1)  advantage; this is achieved with keys of length lscr+omega(logn). In general, keys of length lscr+s yield a bound of 2-Theta(s) on the advantage. These encryption schemes rely on no unproven assumptions and can be implemented efficiently. Applications of this to cryptosystems based on complexity-theoretic assumptions are discussed and, in addition, a simplified proof of a fundamental "elision lemma" of Goldwasser and Micali is provided

title: A scalable associative processor with applications in database and image processing
abstract: This paper describes the implementation and use of a dedicated associative SIMD coprocessor ideally suited for many applications such as database processing, image processing, genome matching, or molecular similarity analysis. The concept of associative SIMD processing is introduced, and differentiated from other associative and SIMD techniques. Then our ASC (associative computing) processor is briefly described, along with its implementation of associative SIMD processing. Finally, we demonstrate the use of our ASC processor on relational database processing and on the image processing operation of edge detection.