An XML-Based Implementation of Multimodal Affective Annotation
In simple cases, affective computing is a computational device recognizing and acting upon the emotions of its user or having (or simulating having) emotions of its own in complex cases. Multimodal technology is currently one of the hottest focuses in affective computing research. However, the lack of a large-scale multimodal database limits the research to some respective and scattered fields, such as affective recognition by video or by audio. This paper describes the development and implementation of an XML-based multimodal affective annotation system which is called MAAS (Multimodal Affective Annotation System). MAAS contains a hierarchical affective annotation model based on the 3-dimensional affect space derived from Mehrabian’s PAD temperament scale. The final annotation file is formed in XML format in order to interchange the resources with other research groups conveniently.

title: Deception Detection Via Blob Motion Pattern Analysis
abstract: Deception dectection is one of the most difficult problems in affect recognition and expression research area. Recently, non-verbal methods of detecting deception have appeared to be promising.  presented a proof-of-concept study based on the blob analysis of some suspects' interviews and mock experiments video clips. In this paper, we present our recent research work in the direction of developing an automated deception detection system. We propose a blob motion pattern analysis approach to solve this problem.

title: Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags
abstract: This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique is Caching Address Tags, or CAT cache, for short. The CAT cache exploits locality property that exists among addresses of memory references. By keeping only a limited number of distinct tags of cached data, rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache, with only a few tag entries, performs as well as ordinary caches, while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip-area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.

title: A dependable Peer-to-Peer computing platform
abstract: This paper discusses a dependable and widely applicable Peer-to-Peer (P2P) computing platform. As the existing P2P computing platforms are limited due to the lack of support for various computational models, this paper proposes a workflow management mechanism to support task dependency in parallel programs while increasing computing efficiency. In general, task dependency leads to a serious performance degradation for failed task re-execution because of volatile peers. Therefore, it results in low dependability. Here, dependability is defined as a comparison of the actual performance with task failures to the theoretical one without failure on a P2P computing platform. Redundant task dispatch and a runtime optimization method are proposed to guarantee high dependability even with highly volatile peers. Large-scale simulation results indicate that the computing platform efficiently solves the problem of P2P computing due to volatile peers.

title: A Workflow Management Mechanism for Peer-to-Peer Computing Platforms
abstract: This paper proposes a workflow management mechanism to address a neglected aspect of existing P2P computing platforms – the lack of support for various computational models. In the workflow management mechanism, a workflow description file is used to define the workflow diagram of the target application. We develop a prototype system, and evaluate it using a test program to demonstrate how the workflow management mechanism effectively works.

title: CAT—caching address tags: a technique for reducing area cost of on-chip caches
abstract: This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique Caching Address Tags, or CAT cache for short. The CAT cache exploits locality property that exists among addresses of memory references for the purpose of minimizing chip area-cost of address tags. By keeping only a limited number of distinct tags of cached data rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache with only a few tag entries performs as well as ordinary caches while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.

title: Estimation delay compensation in high-gain observer-based parameter identification
abstract: In this paper, the properties of the disturbance estimation in a high gain observer are analyzed, and a time delay calculation method is proposed to improve the performance of parameter identification. This paper shows that the estimation delay depends on the observer gain, but has nothing to do with the parameter variation. Then, a novel algorithm is proposed to calculate the delay according to the phase response of disturbance estimation transfer function. Hence, in terms of system identification, this delay is compensated by lagging the state estimate by the same amount of delay. This technique, on one side, improves the performance of parameter identification accuracy, and, on the other side, gives a new insight into the high-gain observer design.