A Comparison of Different Machine Transliteration Models
Machine transliteration is a method for automatically converting words in one language into phonetically equivalent ones in another language. Machine transliteration plays an important role in natural language applications such as information retrieval and machine translation, especially for handling proper nouns and technical terms. Four machine transliteration models - grapheme-based transliteration model, phoneme-based transliteration model, hybrid transliteration model, and correspondence-based transliteration model - have been proposed by several researchers. To date, however, there has been little research on a framework in which multiple transliteration models can operate simultaneously. Furthermore, there has been no comparison of the four models within the same framework and using the same data. We addressed these problems by 1) modeling the four models within the same framework, 2) comparing them under the same conditions, and 3) developing a way to improve machine transliteration through this comparison. Our comparison showed that the hybrid and correspondence-based models were the most effective and that the four models can be used in a complementary manner to improve machine transliteration performance.

title: Knowledge Seeking Activities for Content Intelligence
abstract: This paper proposes a problem on the knowledge seeking activities compared with information seeking and knowledge discovery from text. A knowledge seeking activity is accomplished by a dynamic linkage of contents that is called “content intelligence.” An algorithm called “crossover” of knowledge units is proposed.

title: Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player
abstract: This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption while maintaining a quality of service (QoS) constraint. The computational workload for an incoming frame is predicted by using a frame-based history so that the processor voltage and frequency can be scaled to provide the exact amount of computing power needed to decode the frame. More precisely, the required decoding time for each frame is separated into two parts: a frame-dependent (FD) part and a frame-independent (FI) part. The FD part varies greatly according to the type of the incoming frame whereas the FI part remains constant regardless of the frame type. Separation of the FI part from the overall decoding sequence provides two key benefits depending on the hardware platform: better compensation of the error due to workload prediction and higher level of energy saving when given a QoS degradation level. The proposed DVFS scheme has been implemented on two platforms, a low performance StrongArm-1110-based evaluation board from Intel and a high performance XScale-based testbed designed at USC. In the StrongArm-1110-based system, the FI part is used to compensate for the prediction error that may occur during the FD part, whereas in the XScale-based system, the FI part is used to reduce energy consumption by employing the lowest CPU frequency during the corresponding time intervals. Detailed current measurements in these two platforms demonstrate larger than 87 % and 80 % CPU energy saving while maintaining a user-provided frame rate, respectively. Index Terms — Dynamic voltage and frequency scaling, MPEG decoding, workload decomposition.

title: Dynamic voltage and frequency scaling based on workload decomposition
abstract: This paper presents a technique called "workload decomposition" in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the CPU clock cycles that are required to execute instructions in the CPU whereas the off-chip workload captures the number of external memory access clock cycles that are required to perform external memory transactions. When combined with a dynamic voltage and frequency scaling (DVFS) technique to minimize the energy consumption, this workload decomposition method results in higher energy savings. The workload decomposition itself is performed at run time based on statistics reported by a performance monitoring unit (PMU) without a need for application profiling or compiler support. We have implemented the proposed DVFS with workload decomposition technique on the BitsyX platform, an Intel PXA255-based platform manufactured by ADS Inc., and performed detailed energy measurements. These measurements show that, for a number of widely used software applications, a CPU energy saving of 80% can be achieved for memory-bound programs while satisfying the user-specified timing constraints.

title: PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI
abstract: This paper describes a slack budget distribution algorithm for ultra-low power CMOS logic circuits in a VLSI design environment. We introduce Power-Aware Zero-Slack Algorithm (PA-ZSA), which distributes the surplus time slacks into the most power-hungry modules. The PA-ZSA ensures that the total slack budget is near-maximal and the total power is minimal as a power-aware version of the well-known zero-slack algorithm (ZSA). Based on these time slacks, we have conducted the low-power optimization at gate level by using technology scaling technique. The experimental results show that our strategy reduces average 36% of the total (static and dynamic) power over the conventional slack budget distribution algorithms.

title: Nonrandom Clusters of Palindromes in Herpesvirus Genomes
abstract: Palindromes are symmetrical words of DNA in the sense that they read exactly the same as their reverse complementary sequences. Representing the occurrences of palindromes in a DNA molecule as points on the unit interval, the scan statistics can be used to identify regions of unusually high concentration of palindromes. These regions have been associated with the replication origins on a few herpesviruses in previous studies. However, the use of scan statistics requires the assumption that the points representing the palindromes are independently and uniformly distributed on the unit interval. In this paper, we provide a mathematical basis for this assumption by showing that in randomly generated DNA sequences, the occurrences of palindromes can be approximated by a Poisson process. An easily computable upper bound on the Wasserstein distance between the palindrome process and the Poisson process is obtained. This bound is then used as a guide to choose an optimal palindrome length in the analysis of a collection of 16 herpesvirus genomes. Regions harboring significant palindrome clusters are identified and compared to known locations of replication origins. This analysis brings out a few interesting extensions of the scan statistics that can help formulate an algorithm for more accurate prediction of replication origins.

title: Research problems in clothing simulation
abstract: Clothing simulation and animation are of great importance in computer animation. If cloth simulations could be improved to the point that they could generate realistic cloth motion in real-time, they would find uses in many aspects of daily life such as in fashion design and manufacturing. The area of cloth simulation and animation is full of technical challenges: creating more realistic results, achieving faster run-times, and developing methods capable of constructing and simulating more complex garments. This paper provides an overview of the key procedures involved in the creation of clothed characters, describes the current state-of-the-art techniques, and proposes the research problems that most require further study. Three technical aspects of cloth simulation are considered in this paper: garment construction, physically based simulation, and collision resolution.