Processor Performance Modeling using Symbolic Simulation
We propose a method of analytically characterizing processor performance as a function of circuit latencies. In our approach, we modify traditional simulation to use variables instead of fixed latencies for the internal functional units. The simulation engine then algebraically computes execution times, and the result is a mathematical equation which characterizes the performance space across numerous processor configurations. We discuss the computational complexity issues of this approach and show that instruction chunking and simple equation redundancy checking can make this approach feasible-we can model a large multi-dimensional design space with thousands to millions of design parameter combinations for about 10times the simulation time of a single conventional simulation run. We demonstrate our approach by exploring two different machines: a traditional MlPS-style in-order pipeline and the Intel Graphics

title: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

title: Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
abstract: This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

title: Helper threads via virtual multithreading
abstract: Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
abstract: Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

title: Minimum entropy control of nonlinear ARMA systems over a communication network
abstract: In this paper, the entropy concept has been utilized to characterize the uncertainty of the tracking error for nonlinear ARMA stochastic systems over a communication network, where time delays in the communication channels are of random nature. A recursive optimization solution has been developed. In addition, an alternative algorithm is also proposed based on the probability density function of the tracking error, which is estimated by a neural network. Finally, a simulation example is given to illustrate the efficiency and feasibility of the proposed approach.

title: A Reliability Model for Result Checking in Volunteer Computing
abstract: Large scale volunteer computing has been proved to be an efficient mechanism to solve the complicated problems. Specifically, in such a system, thousands of idle computers on the network are organized to finish a series of tasks dispatched by a central server. However, this computing model is vulnerable to attack from malicious peers returning incorrect results, since it is impossible to check each of thousands of the results. To address this problem, we propose a scheme to evaluate the reliability of each peer, and hence to distinguish whether the peer is honest or malicious. Specifically, the task dispatching pattern is changed so that the results returned from a peer can reflect the type of this peer. We focus on a typical dispatching pattern, and analyze its performance both theoretically and experimentally. The results indicate that the proposed scheme can effectively differentiate the malicious peers for most of the reasonable situations.

title: Delay-dependent fault detection and diagnosis using B-spline neural networks and nonlinear filters for time-delay stochastic systems
abstract: A new fault detection and diagnosis (FDD) scheme is studied in this paper for the continuous-time stochastic dynamic systems with time delays, where the available information for the FDD is the input and the measured output probability density functions (PDFs) of the system. The square-root B-spline neural networks is used to formulate the output PDFs with the dynamic weightings. As a result, the concerned FDD problem can be transformed into a robust FDD problem subjected to a continuous time uncertain nonlinear system with time delays. Delay-dependent criteria to detect and diagnose the system fault are provided by using linear matrix inequality (LMI) techniques. It is shown that this new criterion can provide higher sensitivity performance than the existing result. Simulations are given to demonstrate the efficiency of the proposed approach.

title: Existence of two disjoint long cycles in graphs
abstract: Let n,h be integers with n>=6 and h>=7. We prove that if G is a graph of order n with @s"2(G)>=h, then G contains two disjoint cycles C"1 and C"2 such that |V(C"1)|+|V(C"2)|>=min{h,n}.

title: MIMO Probability Density Function Control Using Simple LOG-MLP Neural Networks
abstract: This paper presents a new model for the control of multivariable output probability density function (PDF). Firstly, a Multi-Layer Perceptron (MLP) neural network is adopted to approximate the static output PDF of the MIMO systems. Nonlinear principal component analysis (NLPCA) is then used to reduce the order of the obtained static neural network model and the dynamics of the system is considered based on the lower-order model. After this, an integrated solution is provided to set up the system with lower-order dynamics for the purpose of stochastic distribution control. The controller design is then presented in detail. Finally, a simulation example is given to demonstrate the effectiveness of the method and encouraging results have been obtained.