Preserving survivability during logical topology reconfiguration in WDM ring networks
We consider the design of reconfiguring logical topologies over physical WDM ring networks. The logical topology consists of the same set of nodes as the physical topology, and the links of the logical topology are lightpaths established (or embedded) over the physical topology. The logical topology is said survivable if the failure of any single physical link does not disconnect the logical topology. In this paper, we consider the following problem: Given a logical topology with its survivable embedding over a physical ring network and a new logical topology to be reconfigured, find a sequence of lightpaths additions and deletions satisfying the given wavelengths and ports constraints such that the logical topology remains survivable throughout the reconfiguration.

title: Double-Link Failure Recovery in WDM Optical Torus Networks
abstract: Most existing link protection methods have been focused on single-link failures. Recently, the double-link failure model has also been considered. In this model, any two links may fail in an arbitrary order. However, an existing model for protecting the entire network against double-link failures does not always provide a 100% recovery when the link identification is not required for pre-computing backup paths. In this paper, we consider double-link failure models that provide 100% recovery in WDM torus optical networks. Three link protection methods are presented. The first method requires failed link identification, whereas the last two methods do not. Other performance measures such as hop-length and backup capacity are also discussed. Finally, we briefly address how our method is possibly extended to mesh optical networks.

title: On double-link failure recovery in WDM optical networks
abstract: Network survivability is a crucial requirement in high-speed optical networks. Typical approaches of providing survivability have considered the failure of a single component such as a link or a node. We consider a failure model in which any two links in the network may fail in an arbitrary order. Three loopback methods of recovering from double-link failures are presented. The first two methods require the identification of the failed links, while the third one does not. However, precomputing the backup paths for the third method is more difficult than for the first two. A heuristic algorithm that pre-computes backup paths for links is presented. Numerical results comparing the performance of our algorithm with other approaches suggests that it is possible to achieve 100% recovery from double-link failures with a modest increase in backup capacity.

title: Packet filtering for congestion control under DoS attacks
abstract: Congestion control in IP networks is typically done at each router through queue management, and the network is entirely dependent on the end hosts to react congestion. However, when misbehaving flows exist and continue to send their packets in very high rates, the queue management schemes implemented in current IP routers reveal a significant shortcoming in protecting legitimate flows. Here, we propose a novel scheme for congestion control in IP networks. Our approach is a time-window based filtering mechanism implemented in a router and processed before a queue management policy is applied. Setting the window size properly and dropping packets reaching in the next window can catch the nonresponsive nature of misbehaving flows. The performance of our proposed scheme is demonstrated through extensive simulations using the NS2, simulator using a set of simulated traffic generated based on IP traces reported in http://www.nlnar.org.

title: Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design
abstract: The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the very deep sub micron technologies that arise from non-scalable global wire delay, failure to achieve global synchronization, errors due to the signal integrity, non-scalable bus based functional interconnection, etc. This paper introduces interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm , etc. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS-2.

title: Design and control of a novel 4-DOFs parallel robot H4
abstract: This paper deals with the design and dynamic control simulation of a new type and dynamic control simulation of a new type of 4-DOFs parallel mechanism providing 3 translations and 1 rotation for high-speed handling and machining. This parallel mechanism is named as H4. A model-based dynamic control scheme is developed to improve the accuracy of the trajectory tracking. A simplified dynamic model is used for the H4 robot to decrease the cost of computation. A dynamic simulation is performed using ADAMS/sup TM/. In addition, the adept motion is used as a benchmark test to evaluate the effect of the dynamic control. The simulation results show that the dynamic control dramatically improves the trajectory tracking accuracy.

title: The Optimum Network on Chip Architectures for Video Object Plane Decoder Design
abstract: On Chip Network (OCN) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, three differently heterogenous Tree-based network topologies are proposed as the OCN architectures for Video Object Plane Decoder (VOPD). The topologies are designed in order to maximize the system throughput. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic energies of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and power consumptions.

title: Throughput Aware Mapping for Network on Chip Design of H.264 Decoder
abstract: Network-on-Chip (NoC) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, we present the queuing theory based model for router to evaluate the performance of NoC in terms of drop probability, throughput and energy consumption. Then we apply the linear programming to optimize the allocation of the heterogeneously functional blocks (IPs) onto the given heterogeneous NoC architecture so as to obtain the maximum throughput as well as to optimize the energy dissipation of whole system. Finally, the three differently heterogenous Tree-based network topologies are proposed as the NoC architectures for the study case of H.264 Decoder. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic powers of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and energy consumptions.

title: Realization of Video Object Plane Decoder on On-Chip Network Architecture
abstract: System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired bus-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. In this paper, we present interconnected network topologies and analyze their performances with a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Fat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.