Dynamic speculative precomputation
A large number of memory accesses in memory-bound applications are irregular, such as pointer dereferences, and can be effectively targeted by thread-based prefetching techniques like Speculative Precomputation. These techniques execute instructions, for example on an available SMT thread context, that have been extracted directly from the program they are trying to accelerate. Proposed techniques typically require manual user intervention to extract and optimize instruction sequences. This paper proposes Dynamic Speculative Precomputation, which performs all necessary instruction analysis, extraction, and optimization through the use of back-end instruction analysis hardware, located off the processor's critical path. For a set of memory limited benchmarks an average speedup of 14% is achieved when constructing simple p-slices, and this gain grows to 33% when making use of aggressive optimizations.

title: Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
abstract: Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

title: Helper threads via virtual multithreading
abstract: Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers

title: Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
abstract: This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

title: On Reduced Structure Control and the 1-norm regularisation
abstract: This paper studies the controller structure selection problem for large multivariable systems. Current approaches to this problem either rely on the control engineer's experience and intuition, or solutions of very difficult and non-convex combinatorial optimisation problems. In this paper new computationally inexpensive analysis tools are presented which provide the control engineer with a complete set of optimal controller structures for a given system. Furthermore, the proposed tools can be used directly to assess the local structural sensitivity of the problem and identify key and important connections within the controller. These tools are applied here to the model of a real-life gas-turbine engine.

title: MIMO Probability Density Function Control Using Simple LOG-MLP Neural Networks
abstract: This paper presents a new model for the control of multivariable output probability density function (PDF). Firstly, a Multi-Layer Perceptron (MLP) neural network is adopted to approximate the static output PDF of the MIMO systems. Nonlinear principal component analysis (NLPCA) is then used to reduce the order of the obtained static neural network model and the dynamics of the system is considered based on the lower-order model. After this, an integrated solution is provided to set up the system with lower-order dynamics for the purpose of stochastic distribution control. The controller design is then presented in detail. Finally, a simulation example is given to demonstrate the effectiveness of the method and encouraging results have been obtained.

title: Maximal Total Length Of k Disjoint Cycles In Bipartite Graphs
abstract: Let k, s and n be three integers with s≥k≥2, n≥2k+1. Let G=(V1,V2;E) be a bipartite graph with |V1|=|V2|=n. If the minimum degree of G is at least s+1, then G contains k vertex-disjoint cycles covering at least min(2n,4s) vertices of G.

title: A simple self-adaptive Differential Evolution algorithm with application on the ALSTOM gasifier
abstract: Differential Evolution (DE) has gathered a reputation for being a powerful yet simple global optimiser with continually outperforming many of the already existing stochastic and direct search global optimisation techniques. It is however well established that DE is particularly sensitive to its control parameters, most notably the mutation weighting factor F. This sensitivity is further studied here and a simple randomised self-adaptive scheme is proposed for the DE mutation weighting factor F. The performance of this algorithm is studied with the use of several benchmark problems and applied to a difficult control systems design case study.

title: How to fool an unbounded adversary with a short key
abstract: The symmetric encryption problem which manifests itself when two parties must securely transmit a message m with a short shared secret key is considered in conjunction with a computationally unbounded adversary. As the adversary is unbounded, any encryption scheme must leak information about m; in particular, the mutual information between m and its ciphertext cannot be zero. Despite this, a family of encryption schemes is presented that guarantee that for any message space in {0,1}n with minimum entropy n-lscr and for any Boolean function h:{0,1}n rarr {0,1}, no adversary can predict h(m) from the ciphertext of m with more than 1/nomega(1) advantage; this is achieved with keys of length lscr+omega(logn). In general, keys of length lscr+s yield a bound of 2-Theta(s) on the advantage. These encryption schemes rely on no unproven assumptions and can be implemented efficiently. Applications of this to cryptosystems based on complexity-theoretic assumptions are discussed and, in addition, a simplified proof of a fundamental "elision lemma" of Goldwasser and Micali is provided