Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

title: Helper threads via virtual multithreading
abstract: Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers

title: Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
abstract: This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

title: BLoG: Post-Silicon bug localization in processors using bug localization graphs
abstract: Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

title: Minimum Entropy Control Algorithm for General Dynamic Stochastic Systems
abstract: In order to measure the uncertainty of the stochastic systems subjected to arbitrary noise disturbance instead of Gaussian white noise, the minimum entropy control of tracking errors for dynamic stochastic systems is presented in this paper. Different from conventional hypothesis, it is assumed that the system output and noise obey multi-to-one mapping, which is more general in the practical application. A controller design was described based on minimizing system output error entropy and a recursive optimization algorithm was set up for dynamic, non-Gaussian and nonlinear system. This approach only used the formula of the probability density function of the tracking error to calculate the controller and it did not need to know the style of the system model and the probability density function of noise, which often is difficult to measure in fact. An illustrative example is utilized to demonstrate the efficiency of the minimum entropy control algorithm and the approving simulation results have been gained

title: Delay-dependent fault detection and diagnosis using B-spline neural networks and nonlinear filters for time-delay stochastic systems
abstract: A new fault detection and diagnosis (FDD) scheme is studied in this paper for the continuous-time stochastic dynamic systems with time delays, where the available information for the FDD is the input and the measured output probability density functions (PDFs) of the system. The square-root B-spline neural networks is used to formulate the output PDFs with the dynamic weightings. As a result, the concerned FDD problem can be transformed into a robust FDD problem subjected to a continuous time uncertain nonlinear system with time delays. Delay-dependent criteria to detect and diagnose the system fault are provided by using linear matrix inequality (LMI) techniques. It is shown that this new criterion can provide higher sensitivity performance than the existing result. Simulations are given to demonstrate the efficiency of the proposed approach.

title: Output PDF Shaping of Singular Weights System: Monotonical Performance Design
abstract: For a group of stochastic systems whose output probability density function (PDF) is modelled by the B-spline neural networks with singular weights dynamics, the output PDF is controlled towards the desired PDF by an innovative optimization design with monotonically decreasing performance. The controller is developed based on the transformed equivalent non-singular system with sufficient conditions given for the monotonic performance.

title: A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded Applications
abstract: This paper describes the FPGA implementation of a specialized SIMD processor array for embedded applications. An alternative to traditional SoC or MPSoC architectures, this array combines the massive parallelism inherent in SIMD architectures with the search capabilities of associative computing, producing a SIMD Processor Array System on a Chip (PASoC) well suited for applications such as data mining and bioinformatics. This paper first describes the architecture of the system, and then the pipelining of the processing elements and the addition of a reconfigurable interconnection network. Finally, the paper concludes with a brief description of a string-matching algorithm that can be used for the applications cited above.

title: How to fool an unbounded adversary with a short key
abstract: The symmetric encryption problem which manifests itself when two parties must securely transmit a message m with a short shared secret key is considered in conjunction with a computationally unbounded adversary. As the adversary is unbounded, any encryption scheme must leak information about m; in particular, the mutual information between m and its ciphertext cannot be zero. Despite this, a family of encryption schemes is presented that guarantee that for any message space in {0,1}n with minimum entropy n-lscr and for any Boolean function h:{0,1}n rarr {0,1}, no adversary can predict h(m) from the ciphertext of m with more than 1/nomega(1) advantage; this is achieved with keys of length lscr+omega(logn). In general, keys of length lscr+s yield a bound of 2-Theta(s) on the advantage. These encryption schemes rely on no unproven assumptions and can be implemented efficiently. Applications of this to cryptosystems based on complexity-theoretic assumptions are discussed and, in addition, a simplified proof of a fundamental "elision lemma" of Goldwasser and Micali is provided