Almost rotation-minimizing rational parametrization of canal surfaces
Almost rotation minimizing parametrization of the canal surface is given. The basic building block of our approach is the curve approximation scheme that enables us to construct a curve, called the parameter curve, on the canal surface that produces, when projected and rescaled, an almost parallel normal vector field on the spine curve. Its construction relies on our earlier methods and results on relating the geometry of the canal surface to the Lorentzian geometry of the Minkowski geometry via the Clifford algebra formalism. We then iteratively construct patches out of the parameter curves via suitable interpolation procedure. Furthermore, its rotational deviation, i.e., the angle deviation from the parallel (no rotation) frame along the spine curve, can be controlled with the use of the rotation deviation estimate of the parameter curves. Our numerical experiment shows that the rotation deviation is minuscule. When compared with other earlier results including our earlier one, our result fares extremely favorably. To facilitate the implement, a practitioners' summary is given in the appendix.

title: Clifford algebra, Lorentzian geometry, and rational parametrization of canal surfaces
abstract: We present a new approach toward the rational parametrization of canal surfaces. According to our previous work, every canal surface with rational (respectively polynomial) spine curve and rational (respectively polynomial) radius function is a rational (respectively polynomial) Pythagorean hodograph curve in R3,1. Drawing upon this formalism and utilizing the underlying Lorentzian geometry, the problem is reduced to simple algebraic manipulations.We also illustrate how our work related to the previous work of pottmann and Peternell. Finally, we give an outline of an approach toward the rotation minimizing parametrization of canal surfaces.

title: Realization of Video Object Plane Decoder on On-Chip Network Architecture
abstract: System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired bus-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. In this paper, we present interconnected network topologies and analyze their performances with a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Fat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.

title: The Optimum Network on Chip Architectures for Video Object Plane Decoder Design
abstract: On Chip Network (OCN) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, three differently heterogenous Tree-based network topologies are proposed as the OCN architectures for Video Object Plane Decoder (VOPD). The topologies are designed in order to maximize the system throughput. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic energies of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and power consumptions.

title: Designing On-Chip Network Based on Optimal Latency Criteria
abstract: A new chip design paradigm, so called Network on Chip, has been introduced based on the demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks. The Network on Chip design not only requires the good performance but also the minimization of several physical constraints such as the network latency, the used area as well as the power consumption of design. This paper analyzes the average latency of heterogeneous Network on Chip architectures in which the shortest path routing algorithm is applied. This average latency includes the queuing latency and the wire latency, and is calculated for general cases of allocating IPs onto the fixed generic switching architectures such as 2-D Mesh and Fat-Tree. With different allocation schemes of IPs, the network has different average latencies. Hence, this article presents an optimal search that adopts the Branch and Bound algorithm to find out the optimal mapping scheme to achieve the minimal network latency. This algorithm automatically map the desired IPs onto the target Network on Chip architecture with the criteria of lowest network latency. Some experiments of On Chip Multiprocessor Network application are simulated. The results show that the network latency is significantly saved with the optimized allocation scheme for the several cases of generic architectures of On Chip Multiprocessor Network application.

title: Throughput Aware Mapping for Network on Chip Design of H.264 Decoder
abstract: Network-on-Chip (NoC) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, we present the queuing theory based model for router to evaluate the performance of NoC in terms of drop probability, throughput and energy consumption. Then we apply the linear programming to optimize the allocation of the heterogeneously functional blocks (IPs) onto the given heterogeneous NoC architecture so as to obtain the maximum throughput as well as to optimize the energy dissipation of whole system. Finally, the three differently heterogenous Tree-based network topologies are proposed as the NoC architectures for the study case of H.264 Decoder. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic powers of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and energy consumptions.

title: Efficient scheduling of transmissions in optical broadcast networks
abstract: All-optical networks (AONs) with a broadcast-star based physical topology offer the possibility of transmission scheduling to resolve channel and receiver conflicts. This paper considers the problem of scheduling packet transmissions in a wavelength-division multiplexed (WDM) optical network with tunable transmitters and fixed-tuned receivers. The scheduling problem is complicated by tuning latency, a limited number of channels, and arbitrary traffic demands. We first analyze scheduling all-to-all packet transmissions and obtain a new lower bound for the schedule length. The lower bound is achieved by an algorithm proposed by Pieris and Sasaki (1994). We then extend the analysis to the case of arbitrary traffic demands and obtain lower bounds for the schedule length. Two constructions for scheduling algorithms are provided through list scheduling and multigraphs. The upper bounds so obtained not only provide performance guarantees with arbitrary demands, but also nearly meet the lower bound in simulations.