Existence of two disjoint long cycles in graphs
Let n,h be integers with n>=6 and h>=7. We prove that if G is a graph of order n with @s"2(G)>=h, then G contains two disjoint cycles C"1 and C"2 such that |V(C"1)|+|V(C"2)|>=min{h,n}.

title: Packing Three Copies of a Tree into a Complete Graph
abstract: A three T of order n is said to be 3-placeable if there are three edge-disjoint copies of T in Kn. In this paper we characterize all the trees T such that T is 3-placeable.

title: On Covering a Bipartite Graph with Cycles
abstract: We conjectured in [H. Wang,  (1999), pp. 115--121] that, for each integer $k\geq 2$, there exists N(k) such that if G=(V1,V2;E) is a bipartite graph with $|V_1|=|V_2|=n\geq N(k)$ and d(x)+d(y)\geq n+k$ for each pair of nonadjacent vertices x and y of G with $x\in V_1$ and $y\in V_2$, then for any k independent edges e1, . . ., ek of G, there exist k vertex-disjoint cycles C1, . . . ,Ck in G such that $e_i\in E(C_i)$ for all $i\in\{1,\ldots ,k\}$ and $V(C_1\cup\cdots \cup C_k)=V(G)$. This conjecture is also verified for k=2 in [H. Wang,  (1999), pp. 115--121]. We prove this conjecture for k=3 in this paper.

title: Vertex-Disjoint Triangles in Claw-Free Graphs with Minimum Degree at Least Three
abstract: . Our main result is as follows: For any integer , if G is a claw-free graph of order at least and with minimum degree at least 3, then G contains k vertex-disjoint triangles unless G is of order and G belongs to a known class of graphs. We also construct a claw-free graph with minimum degree 3 on n vertices for each such that it does not contain k vertex-disjoint triangles. We put forward a conjecture on vertex-disjoint triangles in -free graphs.

title: On Quadrilaterals and Cycle Covers in a Bipartite Graph

title: An extension of a theorem on cycles containing specified independent edges
abstract: We give an alternative proof of a conjecture due to Wang ( (1997) 105) in a stronger form. The main theorem states that for any integer k ≥ 2 if G is a graph of order n ≥ 4k - 1 and d(u) + d(υ) ≥ n + 2k - 2 for each pair of non-adjacent vertices u and υ of G, then, for any k independent edges e1,... ,ek of G, there exist k vertex-disjoint cycles C1,..., Ck in G such that (i) ei ∈ E(Ci) for all 1 ≤ i ≤ k, (ii) V(C1)∪ ... ∪V(Ck) = V(G), and (iii) #{i ≤ k||Ci| a > n - 4k + 2). It strengthens the conjecture of Wang, which was first proven by Egawa et al. ( (2000) 81).

title: Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors

title: Optimal Actuator Fault Detection via MLP Neural Network for PDFs
abstract: In this paper a new type of fault detection (FD) problem is considered where the measured information is the stochastic distribution of the system output rather than its value. A multi-layer perceptron (MLP) neural network is adopted to approximate the probability density function (PDF) of the system outputs and nonlinear principal component analysis (NLPCA) is applied to reduce the model order for a lower-order model. For such a dynamic model in discrete-time context, where nonlinearities, uncertainties and time delays are included, the concerned FD problem is investigated. The measure of estimation errors, which is represented by the distances between two output PDFs, will be optimized to find the detection filter gain. Guaranteed cost detection filter are designed based on LMI formulations.

title: Novel Parameter Identification by Using a High-Gain Observer With Application to a Gas Turbine Engine
abstract: In this study, a novel identification technique, that is high-gain observer-based identification approach, is proposed for systems with bounded process and measurement noises. For system parameters with abnormal changes, an adaptive change detection and parameter identification algorithm is next presented. The presented technique and algorithm are finally applied to the parameter identification of the gas turbine engine by using the recorded input data from the engine test-bed. The identified parameters and the response curves are desirable. The simulations have proved the effectiveness of the proposed procedure compared with the previous identification approach.

title: Register renaming and scheduling for dynamic execution of predicated code
abstract: To achieve higher processor performance requires greater synergy between advanced hardware features and innovative compiler techniques. Recent advancement in compilation techniques for predicated execution has provided significant opportunity in exploiting instruction level parallelism. However, little research has been done on how to efficiently execute predicated code in a dynamic microarchitecture. In this paper, we evaluate hardware optimizations for executing predicated code on a dynamically scheduled microarchitecture. We provide two novel ideas to improve the efficiency of executing predicated code. On a generic Intel Itanium processor pipeline model, we demonstrate that, with some microarchitecture enhancements, a dynamic execution processor can achieve about 16% performance improvement over an equivalent static execution processor.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.