Packing Three Copies of a Tree into a Complete Graph
A three T of order n is said to be 3-placeable if there are three edge-disjoint copies of T in Kn. In this paper we characterize all the trees T such that T is 3-placeable.

title: An extension of a theorem on cycles containing specified independent edges
abstract: We give an alternative proof of a conjecture due to Wang ( (1997) 105) in a stronger form. The main theorem states that for any integer k ≥ 2 if G is a graph of order n ≥ 4k - 1 and d(u) + d(υ) ≥ n + 2k - 2 for each pair of non-adjacent vertices u and υ of G, then, for any k independent edges e1,... ,ek of G, there exist k vertex-disjoint cycles C1,..., Ck in G such that (i) ei ∈ E(Ci) for all 1 ≤ i ≤ k, (ii) V(C1)∪ ... ∪V(Ck) = V(G), and (iii) #{i ≤ k||Ci| a > n - 4k + 2). It strengthens the conjecture of Wang, which was first proven by Egawa et al. ( (2000) 81).

title: On Covering a Bipartite Graph with Cycles
abstract: We conjectured in [H. Wang,  (1999), pp. 115--121] that, for each integer $k\geq 2$, there exists N(k) such that if G=(V1,V2;E) is a bipartite graph with $|V_1|=|V_2|=n\geq N(k)$ and d(x)+d(y)\geq n+k$ for each pair of nonadjacent vertices x and y of G with $x\in V_1$ and $y\in V_2$, then for any k independent edges e1, . . ., ek of G, there exist k vertex-disjoint cycles C1, . . . ,Ck in G such that $e_i\in E(C_i)$ for all $i\in\{1,\ldots ,k\}$ and $V(C_1\cup\cdots \cup C_k)=V(G)$. This conjecture is also verified for k=2 in [H. Wang,  (1999), pp. 115--121]. We prove this conjecture for k=3 in this paper.

title: On Independent Cycles in a Bipartite Graph
abstract: Let G=(V1,V2;E) be a bipartite graph with 2k≤m=|V1|≤|V2|=n, where k is a positive integer. We show that if the number of edges of G is at least (2k−1)(n−1)+m, then G contains k vertex-disjoint cycles, unless e(G)=(2k−1)(n−1)+m and G belongs to a known class of graphs.

title: On Quadrilaterals and Cycle Covers in a Bipartite Graph

title: Vertex-Disjoint Triangles in Claw-Free Graphs with Minimum Degree at Least Three
abstract: . Our main result is as follows: For any integer , if G is a claw-free graph of order at least and with minimum degree at least 3, then G contains k vertex-disjoint triangles unless G is of order and G belongs to a known class of graphs. We also construct a claw-free graph with minimum degree 3 on n vertices for each such that it does not contain k vertex-disjoint triangles. We put forward a conjecture on vertex-disjoint triangles in -free graphs.

title: Hardware Support for Prescient Instruction Prefetch
abstract: This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch — an approach to improving single-threaded application performance by using helper threads to perform instruction prefetch. We demonstrate the need for enabling store-to-load communication and selective instruction execution when directly pre-executing future regions of an application that suffer I-cache misses. Two novel hardware mechanisms, safe-store and YAT-bits, are introduced that help satisfy these requirements. This paper also proposes and evaluates .nite state machine recall, a technique for limiting pre-execution to branches that are hard to predict by leveraging a counted I-prefetch mechanism. On a research Itanium®SMT processor with next line and streaming I-prefetch mechanisms that incurs latencies representative of next generation processors, prescient instruction prefetch can improve performance by an average of 10.0% to 22% on a set of SPEC 2000 benchmarks that suffer significant I-cache misses. Prescient instruction prefetch is found to be competitive against even the most aggressive research hardware instruction prefetch technique: fetch directed instruction prefetch.

title: An ILC-Based Adaptive Control for General Stochastic Systems With Strictly Decreasing Entropy
abstract: In this paper, a new method for adaptive control of general nonlinear and non-Gaussian unknown stochastic systems has been proposed. The method applies the minimum entropy control scheme to decrease the closed-loop randomness of the output under an iterative learning control (ILC) basis. Both modeling and control of the plant are performed using dynamic neural networks. For this purpose, the whole control horizon is divided into a certain number of time domain subintervals called batches and a pseudo-D-type ILC law is employed to train the plant model and controller parameters so that the entropy of the closed-loop tracking error is made to decrease batch by batch. The method has the advantage of decreasing the output uncertainty versus the advances of batches along the time horizon. The analysis on the proposed ILC convergence is made and a set of demonstrable experiment results is also provided to show the effectiveness of the obtained control algorithm, where encouraging results have been obtained.

title: Implementing a scalable ASC processor
abstract: Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism.

title: Novel Parameter Identification by Using a High-Gain Observer With Application to a Gas Turbine Engine
abstract: In this study, a novel identification technique, that is high-gain observer-based identification approach, is proposed for systems with bounded process and measurement noises. For system parameters with abnormal changes, an adaptive change detection and parameter identification algorithm is next presented. The presented technique and algorithm are finally applied to the parameter identification of the gas turbine engine by using the recorded input data from the engine test-bed. The identified parameters and the response curves are desirable. The simulations have proved the effectiveness of the proposed procedure compared with the previous identification approach.

title: Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors