A dependable Peer-to-Peer computing platform
This paper discusses a dependable and widely applicable Peer-to-Peer (P2P) computing platform. As the existing P2P computing platforms are limited due to the lack of support for various computational models, this paper proposes a workflow management mechanism to support task dependency in parallel programs while increasing computing efficiency. In general, task dependency leads to a serious performance degradation for failed task re-execution because of volatile peers. Therefore, it results in low dependability. Here, dependability is defined as a comparison of the actual performance with task failures to the theoretical one without failure on a P2P computing platform. Redundant task dispatch and a runtime optimization method are proposed to guarantee high dependability even with highly volatile peers. Large-scale simulation results indicate that the computing platform efficiently solves the problem of P2P computing due to volatile peers.

title: A Workflow Management Mechanism for Peer-to-Peer Computing Platforms
abstract: This paper proposes a workflow management mechanism to address a neglected aspect of existing P2P computing platforms – the lack of support for various computational models. In the workflow management mechanism, a workflow description file is used to define the workflow diagram of the target application. We develop a prototype system, and evaluate it using a test program to demonstrate how the workflow management mechanism effectively works.

title: A Performance Study of Secure Data Mining on the Cell Processor
abstract: This paper examines the potential of the Cell processor as a platform for secure data mining on the future volunteer computing systems. Volunteer computing platforms have the potential to provide massive computing power. However, privacy and security concerns prevent using volunteer computing for data mining of sensitive data. The Cell processor comes with a hardware security feature. The secure volunteer data mining can be achieved by using this hardware security feature. In this paper, we present a general security scheme for the volunteer computing, and a secure parallelized K-Means clustering algorithm for the Cell processor. We also evaluate the performance of the algorithm on the Cell secure system simulator. Evaluation results indicate that the proposed secure data clustering outperforms a non-secure clustering algorithm on the general purpose CPU, but incurs a huge performance overhead introduced by the decryption process of the Cell security features.

title: A Reliability Model for Result Checking in Volunteer Computing
abstract: Large scale volunteer computing has been proved to be an efficient mechanism to solve the complicated problems. Specifically, in such a system, thousands of idle computers on the network are organized to finish a series of tasks dispatched by a central server. However, this computing model is vulnerable to attack from malicious peers returning incorrect results, since it is impossible to check each of thousands of the results. To address this problem, we propose a scheme to evaluate the reliability of each peer, and hence to distinguish whether the peer is honest or malicious. Specifically, the task dispatching pattern is changed so that the results returned from a peer can reflect the type of this peer. We focus on a typical dispatching pattern, and analyze its performance both theoretically and experimentally. The results indicate that the proposed scheme can effectively differentiate the malicious peers for most of the reasonable situations.

title: CAT—caching address tags: a technique for reducing area cost of on-chip caches
abstract: This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique Caching Address Tags, or CAT cache for short. The CAT cache exploits locality property that exists among addresses of memory references for the purpose of minimizing chip area-cost of address tags. By keeping only a limited number of distinct tags of cached data rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache with only a few tag entries performs as well as ordinary caches while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.

title: Dynamic speculative precomputation
abstract: A large number of memory accesses in memory-bound applications are irregular, such as pointer dereferences, and can be effectively targeted by thread-based prefetching techniques like Speculative Precomputation. These techniques execute instructions, for example on an available SMT thread context, that have been extracted directly from the program they are trying to accelerate. Proposed techniques typically require manual user intervention to extract and optimize instruction sequences. This paper proposes Dynamic Speculative Precomputation, which performs all necessary instruction analysis, extraction, and optimization through the use of back-end instruction analysis hardware, located off the processor's critical path. For a set of memory limited benchmarks an average speedup of 14% is achieved when constructing simple p-slices, and this gain grows to 33% when making use of aggressive optimizations.

title: Sensor fault estimator and its application for linear multi-variable dynamic systems with delayed state and input
abstract: For systems with multiple time delays, a novel state and sensor noise observer is designed to estimate system states and sensor noises at the same time. In this design, descriptor system approach and linear matrix inequality technique are adopted. Unbounded sensor faults will make the system fail unavoidably, it is indispensable to derive a reliable control scheme against sensor failures. Using the estimated state and sensor fault, a fault-tolerant observer-based controller is proposed, which makes the system work well not matter whether sensor faults occur or not.

title: Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags
abstract: This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique is Caching Address Tags, or CAT cache, for short. The CAT cache exploits locality property that exists among addresses of memory references. By keeping only a limited number of distinct tags of cached data, rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache, with only a few tag entries, performs as well as ordinary caches, while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip-area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.

title: Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
abstract: Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.