Production asymmetry of Ds from 600 GeV//c Sigma- and pi- beam

title: Nuclear dependence of charm production
abstract: Using data taken by SELEX during the 1996–1997 fixed target run at Fermilab, we study the production of charmed hadrons on copper and carbon targets with Σ−, p, π−, and π+ beams. Parametrizing the dependence of the inclusive production cross section on the atomic number A as Aα, we determine α for D+, D0, Ds+, D+(2010), Λc+, and their respective anti-particles, as a function of their transverse momentum pt and scaled longitudinal momentum xF. Within our statistics there is no dependence of α on xF for any charm species for the interval 0.1<xF<1.0. The average value of α for charm production by pion beams is αmeson=0.850±0.028. This is somewhat larger than the corresponding average αbaryon=0.755±0.016 for charm production by baryon beams (Σ−, p).

title: Multiplicity separation with the reciprocal effect counter in the SELEX experiment

title: Investigation of elastic hadron electron scattering at 540 GeV/c in order to measure the electromagnetic charge radius of the proton

title: Precision measurements of the lambda(+)(c) and D0 lifetimes.
abstract: We report new precision measurements of the lifetimes of the Lambda(+)(c) and D0 from SELEX, the charm hadroproduction experiment at Fermilab. Based upon 1630 Lambda(+)(c) and 10 210 D0 decays we observe lifetimes of tau[Lambda(+)(c)] = 198.1+/-7.0+/-5.6 fs and tau[D0] = 407.9+/-6.0+/-4.3 fs.

title: Arrangement Channel Quantum Mechanics: A General Time Dependent Formalism for Multiparticle Scattering

title: DEPFET Active Pixel Sensors
abstract: DEPFET pixels offer a unique possibility for a high resolution pixel vertex detector at a future linear collider (ILC) experiment. The key idea of DEPFET sensors is the integration of amplifying transistors into a fully depleted bulk. The excellent noise performance obtained through the low input capacitance in combination with the full signal from the depleted bulk leads to a large S/N ratio. The sensor itself can therefore be made very thin (50μm) without loss of efficiency. In this article the progress of the DEPFET development towards an ILC vertex detector is presented. Properties of prototype matrices and dedicated ASIC electronics have been characterized in various laboratory and test beam measurements. In particular a point resolution of less than 2 μm has been demonstrated (using 450 μm thick sensors). Based on these results larger matrices, improved readout and control electronics have been designed which are presently in production. In parallel software was developed to simulate the performance of a DEPFET based vertex detector in an ILC experiment.

title: Progress towards a large area, thin DEPFET detector module
abstract: Large arrays of depleted field effect transistor (DEPFET) detector elements are one possible technology for the vertex detector of the planned International Linear Collider. The main challenges are the production of large ( 10 cm 2 ) devices with an average thickness of around 100 μ m (silicon) and their fast column parallel readout. This paper describes in some detail how a DEPFET based sensor module could be built and presents the design of the latest generation of ‘Switcher’ steering chips.

title: First test beam results on DEPFET pixels for the ILC
abstract: By incorporating a field effect transistor into a fully depleted sensor substrate the DEPFET sensor combines radiation detection and amplification in each pixel, resulting in very low noise and high spatial resolution. This makes DEPFET sensors a favorable technology for the vertex detector at the planned International Linear Collider (ILC). A prototype system with fast steering chips, a current-based readout chip and a 64 × 128 pixels DEPFET matrix has been built and was operated successfully in the DESY test beam. First results of the studies on two different DEPFET design options are presented in this paper.

title: SEU tolerant memory design for the ATLAS pixel readout chip
abstract: The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.