CAT—caching address tags: a technique for reducing area cost of on-chip caches
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique Caching Address Tags, or CAT cache for short. The CAT cache exploits locality property that exists among addresses of memory references for the purpose of minimizing chip area-cost of address tags. By keeping only a limited number of distinct tags of cached data rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache with only a few tag entries performs as well as ordinary caches while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.

title: Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
abstract: Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

title: Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
abstract: This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

title: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers

title: Helper threads via virtual multithreading
abstract: Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: An Algorithm for Identification of Reduced-Order Dynamic Models of Gas Turbines
abstract: Model based approaches show a lot of advantages for fault detection and condition monitoring. Particularly, it is true in employing reduced order models for real-time parameter identification and output prediction of gas turbines. Many algorithms have been developed, but most of them focus on one-step-ahead prediction models and involve complex computation. These algorithms are not acceptable for long-term prediction and real-time condition monitoring. In this paper, an improved gradient method (dynamic gradient descent) is proposed. The idea is to take account of the dependency of prediction errors and calculate the gradient information recursively. Not only low computation expense is achieved, but the non-Gaussian errors can also be overcome when this approach is applied to estimate parameters of a reduced order gas turbine model and to improve long-term prediction

title: A Performance Study of Secure Data Mining on the Cell Processor
abstract: This paper examines the potential of the Cell processor as a platform for secure data mining on the future volunteer computing systems. Volunteer computing platforms have the potential to provide massive computing power. However, privacy and security concerns prevent using volunteer computing for data mining of sensitive data. The Cell processor comes with a hardware security feature. The secure volunteer data mining can be achieved by using this hardware security feature. In this paper, we present a general security scheme for the volunteer computing, and a secure parallelized K-Means clustering algorithm for the Cell processor. We also evaluate the performance of the algorithm on the Cell secure system simulator. Evaluation results indicate that the proposed secure data clustering outperforms a non-secure clustering algorithm on the general purpose CPU, but incurs a huge performance overhead introduced by the decryption process of the Cell security features.

title: MIMO Probability Density Function Control Using Simple LOG-MLP Neural Networks
abstract: This paper presents a new model for the control of multivariable output probability density function (PDF). Firstly, a Multi-Layer Perceptron (MLP) neural network is adopted to approximate the static output PDF of the MIMO systems. Nonlinear principal component analysis (NLPCA) is then used to reduce the order of the obtained static neural network model and the dynamics of the system is considered based on the lower-order model. After this, an integrated solution is provided to set up the system with lower-order dynamics for the purpose of stochastic distribution control. The controller design is then presented in detail. Finally, a simulation example is given to demonstrate the effectiveness of the method and encouraging results have been obtained.

title: A Polygon Detection Algorithm for Robot Visual Servoing
abstract: The problem of detecting polygon structures in images arises in many applications, from building extraction to cryo-electron microscopy. In this paper, A polygon detection algorithm (PDA) based on line detection is proposed. First of all, we introduce a parallel thinning algorithm to eliminate useless feature points. Then the feature points are organized as disjoint feature contours. For each independent contour, we detect line segment candidates based on RANSAC algorithm. With these candidates, a polygon (triangle, rectangle or other polygons) is composed. Compared to the state-of-the-art shape detection algorithms, PDA is much faster and it can detect any polygons such as triangles, rectangles, etc. We introduce PDA to a 6DOFs robot visual servoing platform and the experimental results show that significant improvements in time efficiency and performance robustness of the proposed algorithm have been achieved.

title: Color-based road detection in urban traffic scenes
abstract: Road detection is a key issue for autonomous driving in urban traffic. In this paper, after a brief overview of existing methods, we present a road-area detection algorithm based on color images. This algorithm is composed of two modules: boundaries are first estimated based on the intensity image and road areas are subsequently detected based on the full color image. In the first module, an edge image of the scene is analyzed to obtain the candidates for the left and right road borders and to delimit the area that will subsequently be used to compute the mean and variance of the Gaussian distribution, assumed to be obeyed by the color components of road surfaces. The second module effectively extracts the road area and reinforces boundaries that most appropriately fit the road-extraction result. The combination of these modules can overcome basic problems due to inaccuracies in edge detection based on the intensity image alone and due to the computational complexity of segmentation algorithms based on color images. Experimental results on real road scenes have substantiated the effectiveness of the proposed method.