Partition of a bipartite graph into cycles
(1984) conjectured that if G is a graph on n 1 + n 2 +⋯+ n k vertices with n i ⩾3 for 1⩽ i ⩽ k a minimum degree δ ( G )⩾⌈ n 1 /2⌉+⌈ n 2 /2⌉+⋯+⌈ n k /2⌉, then G contains k vertex-disjoint cycles of lengths n 1 , n 2 ,⋯, n k respectively. He proved this conjecture for k =2. In this note we consider a similar problem in bipartite graphs and prove: If G is a bipartite graph with partites V 1 and V 2 where | V 1 |=| V 2 |= n , n = n 1 + n 2 +⋯+ n k for n 1 ⩾ n 2 ⩾⋯⩾ n k ⩾2, k ⩾2 and δ ( G )⩾ n 1 + n 2 + ⋯+ n k −1 + n k /2, then G contains k vertex-disjoint cycles of lengths 2 n 1 ,2 n 2 ,…,2 n k , respectively. We demonstrate by producing examples that the above result is best possible when k =2.

title: Packing Three Copies of a Tree into a Complete Graph
abstract: A three T of order n is said to be 3-placeable if there are three edge-disjoint copies of T in Kn. In this paper we characterize all the trees T such that T is 3-placeable.

title: On Covering a Bipartite Graph with Cycles
abstract: We conjectured in [H. Wang,  (1999), pp. 115--121] that, for each integer $k\geq 2$, there exists N(k) such that if G=(V1,V2;E) is a bipartite graph with $|V_1|=|V_2|=n\geq N(k)$ and d(x)+d(y)\geq n+k$ for each pair of nonadjacent vertices x and y of G with $x\in V_1$ and $y\in V_2$, then for any k independent edges e1, . . ., ek of G, there exist k vertex-disjoint cycles C1, . . . ,Ck in G such that $e_i\in E(C_i)$ for all $i\in\{1,\ldots ,k\}$ and $V(C_1\cup\cdots \cup C_k)=V(G)$. This conjecture is also verified for k=2 in [H. Wang,  (1999), pp. 115--121]. We prove this conjecture for k=3 in this paper.

title: Vertex-Disjoint Triangles in Claw-Free Graphs with Minimum Degree at Least Three
abstract: . Our main result is as follows: For any integer , if G is a claw-free graph of order at least and with minimum degree at least 3, then G contains k vertex-disjoint triangles unless G is of order and G belongs to a known class of graphs. We also construct a claw-free graph with minimum degree 3 on n vertices for each such that it does not contain k vertex-disjoint triangles. We put forward a conjecture on vertex-disjoint triangles in -free graphs.

title: On Independent Cycles in a Bipartite Graph
abstract: Let G=(V1,V2;E) be a bipartite graph with 2k≤m=|V1|≤|V2|=n, where k is a positive integer. We show that if the number of edges of G is at least (2k−1)(n−1)+m, then G contains k vertex-disjoint cycles, unless e(G)=(2k−1)(n−1)+m and G belongs to a known class of graphs.

title: On Quadrilaterals and Cycle Covers in a Bipartite Graph

title: Temperature dependence of DC characteristics of NpN InP/GaAsSb/InP double heterojunction bipolar transistors: an analytical study
abstract: An analytic study of DC characteristics based on the drift-diffusion approach has been performed for the InP/GaAsSb DHBTs. The current transport of InP/GaAsSb/InP DHBTs has been investigated focusing the device temperature dependence. Our simulation results show that, at room temperature, the DC characteristics of the InP/GaAsSb/InP DHBTs similar to the conventional InP-based HBT using InGaAs as the base layer although a type-II energy band alignment is presented in the InP/GaAsSb HBT. However, due to different mechanisms for the electron injection from the emitter induced by the different conduction band alignments, the InP/GaAsSb HBTs may present a different temperature dependent behavior in term of device current gain as compared to the conventional InP/InGaAs HBTs. Higher current gain could be achieved by the InP/GaAsSb HBTs at elevated temperature.

title: BLoG: Post-Silicon bug localization in processors using bug localization graphs
abstract: Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.

title: Zero Assignment for Robust  $H_{2}/H_{\infty}$ Fault Detection Filter Design
abstract: In practical engineering, it is inevitable that a system is perturbed by noise signals. Unfortunately, H infin /H infin filtering may fail to detect some faults when the noise distribution matrix are the same as the fault distribution matrix. In this paper, it is shown that the dynamic feedback gain of a dynamic filter introduces additional zeros to the filter, and both the filter poles and the additional zeros can be assigned arbitrarily. In order to attenuate band-limited noises, the zero assignment technique is used, and an optimal dynamic fault detection filtering approach is proposed by locating the zeros to the noise frequencies and optimizing the poles. Compared to other dynamic filter design approaches, the zero assignment technique gives a better tradeoff between more design freedom and computation costs. As shown in the simulation, a better noise attenuation and fault detection performance have been obtained. The zero assignment in multivariable fault detection filter design would be the main contribution of this paper.

title: Dynamic speculative precomputation
abstract: A large number of memory accesses in memory-bound applications are irregular, such as pointer dereferences, and can be effectively targeted by thread-based prefetching techniques like Speculative Precomputation. These techniques execute instructions, for example on an available SMT thread context, that have been extracted directly from the program they are trying to accelerate. Proposed techniques typically require manual user intervention to extract and optimize instruction sequences. This paper proposes Dynamic Speculative Precomputation, which performs all necessary instruction analysis, extraction, and optimization through the use of back-end instruction analysis hardware, located off the processor's critical path. For a set of memory limited benchmarks an average speedup of 14% is achieved when constructing simple p-slices, and this gain grows to 33% when making use of aggressive optimizations.

title: Robust minimum entropy tracking control with guaranteed stability for nonlinear stochastic systems under modeling errors
abstract: In this paper, robust minimum entropy tracking control problem is considered for nonlinear stochastic systems. The controlled systems are described by nonlinear non-Gaussian difference equations with the un-modeled uncertainty and modeling error, as well as time delays. Entropy is adopted to characterize the uncertainty of the tracking error. The nonlinear multi-step-ahead predictive cost function is used and the relationship between the probability density functions of the input and the tracking error via the uncertain mapping is established. With these formulations, the cost function can be bounded as a nonlinear functional of the control input and the known bounds of the errors. Explicit design algorithms are presented for the robust suboptimal controller and further for the stabilization controllers. The Renyi's entropy has also been used to simplify the cost function. Simulations are given to demonstrate the effectiveness of the proposed control algorithm.