A Reliability Model for Result Checking in Volunteer Computing
Large scale volunteer computing has been proved to be an efficient mechanism to solve the complicated problems. Specifically, in such a system, thousands of idle computers on the network are organized to finish a series of tasks dispatched by a central server. However, this computing model is vulnerable to attack from malicious peers returning incorrect results, since it is impossible to check each of thousands of the results. To address this problem, we propose a scheme to evaluate the reliability of each peer, and hence to distinguish whether the peer is honest or malicious. Specifically, the task dispatching pattern is changed so that the results returned from a peer can reflect the type of this peer. We focus on a typical dispatching pattern, and analyze its performance both theoretically and experimentally. The results indicate that the proposed scheme can effectively differentiate the malicious peers for most of the reasonable situations.

title: A Workflow Management Mechanism for Peer-to-Peer Computing Platforms
abstract: This paper proposes a workflow management mechanism to address a neglected aspect of existing P2P computing platforms – the lack of support for various computational models. In the workflow management mechanism, a workflow description file is used to define the workflow diagram of the target application. We develop a prototype system, and evaluate it using a test program to demonstrate how the workflow management mechanism effectively works.

title: Criticality-based optimizations for efficient load processing
abstract: Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Previous work has shown that the criticality of instructions can be dynamically predicted with high accuracy, and that this information can be leveraged to optimize the performance of load value prediction and instruction steering for clustered architectures. In this work, we revisit the idea of criticality, but we propose several processor enhancements that can exploit criticality information and can be directly applied to modern x86 microarchitectures. For the investment of a small (less than 1KB) criticality predictor, we can make a conventional single-read-port data cache achieve the performance of an ideal dual-read-port cache, yielding an average 10% performance improvement. Our remaining techniques can reuse the predictor (i.e., no additional overhead) to further optimize other aspects of load processing (e.g., caching decisions, store-to-load forwarding, etc.), yielding an overall performance improvement of 16% over a conventional processor. Some of these techniques also allow us to decrease power and area costs for several related hardware structures.

title: An ILC-Based Adaptive Control for General Stochastic Systems With Strictly Decreasing Entropy
abstract: In this paper, a new method for adaptive control of general nonlinear and non-Gaussian unknown stochastic systems has been proposed. The method applies the minimum entropy control scheme to decrease the closed-loop randomness of the output under an iterative learning control (ILC) basis. Both modeling and control of the plant are performed using dynamic neural networks. For this purpose, the whole control horizon is divided into a certain number of time domain subintervals called batches and a pseudo-D-type ILC law is employed to train the plant model and controller parameters so that the entropy of the closed-loop tracking error is made to decrease batch by batch. The method has the advantage of decreasing the output uncertainty versus the advances of batches along the time horizon. The analysis on the proposed ILC convergence is made and a set of demonstrable experiment results is also provided to show the effectiveness of the obtained control algorithm, where encouraging results have been obtained.

title: An Optimal Iterative Learning Scheme for Dynamic Neural Network Modelling
abstract: In this paper, iterative learning control is presented to a dynamic neural network modelling process for nonlinear (stochastic) dynamical systems. When (B-spline) neural networks are used to model a nonlinear dynamical functional such as the output stochastic distributions in the repetitive processes or the batch processes, the parameters in the basis functions will be tuned using the generalized iterative learning control (GILC) scheme. The GILC scheme differs from the classical model-based ILC laws, with no dynamical input-output differential or difference equations given a prior. For the “model free” GILC problem, we propose an optimal design algorithm for the learning operators by introducing an augmented difference model in state space. A sufficient and necessary solvable condition can be given where a robust optimization solution with an LMI-based design algorithm can be provided.

title: Best of both latency and throughput
abstract: This paper describes the tradeoff between latency performance and throughput performance in a power-constrained environment. We show that the key to achieving both excellent latency performance as well as excellent throughput performance is to dynamically vary the amount of energy expended to process instructions according to the amount of parallelism available in the software. We survey four techniques for achieving variable energy per instruction: voltage/frequency scaling, asymmetric cores, variable-size cores, and speculation control. We estimate the potential range of energies obtainable by each technique and conclude that a combination of asymmetric cores and voltage/frequency scaling offers the most promising approach to design a chip-level multiprocessor that can achieve both excellent latency performance and excellent throughput performance.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.