Redundant Arithmetic Optimizations (Research Note)
Redundant arithmetic can be implemented on general-purpose processors to gain significant speedup. Redundant arithmetic speeds up the execution of certain dependent instructions by removing extra work and enabling higher frequencies. However, the issues of worst case delay, scheduling and power must be resolved. We will present the ECS representation format along with initial data and analysis on these critical issues.

title: Helper threads via virtual multithreading
abstract: Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
abstract: Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

title: Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
abstract: This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

title: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers

title: Temperature dependence of DC characteristics of NpN InP/GaAsSb/InP double heterojunction bipolar transistors: an analytical study
abstract: An analytic study of DC characteristics based on the drift-diffusion approach has been performed for the InP/GaAsSb DHBTs. The current transport of InP/GaAsSb/InP DHBTs has been investigated focusing the device temperature dependence. Our simulation results show that, at room temperature, the DC characteristics of the InP/GaAsSb/InP DHBTs similar to the conventional InP-based HBT using InGaAs as the base layer although a type-II energy band alignment is presented in the InP/GaAsSb HBT. However, due to different mechanisms for the electron injection from the emitter induced by the different conduction band alignments, the InP/GaAsSb HBTs may present a different temperature dependent behavior in term of device current gain as compared to the conventional InP/InGaAs HBTs. Higher current gain could be achieved by the InP/GaAsSb HBTs at elevated temperature.

title: Delay-dependent fault detection and diagnosis using B-spline neural networks and nonlinear filters for time-delay stochastic systems
abstract: A new fault detection and diagnosis (FDD) scheme is studied in this paper for the continuous-time stochastic dynamic systems with time delays, where the available information for the FDD is the input and the measured output probability density functions (PDFs) of the system. The square-root B-spline neural networks is used to formulate the output PDFs with the dynamic weightings. As a result, the concerned FDD problem can be transformed into a robust FDD problem subjected to a continuous time uncertain nonlinear system with time delays. Delay-dependent criteria to detect and diagnose the system fault are provided by using linear matrix inequality (LMI) techniques. It is shown that this new criterion can provide higher sensitivity performance than the existing result. Simulations are given to demonstrate the efficiency of the proposed approach.

title: Pentagons and cycle coverings
abstract: Let G be a graph of order n ≥ 5k + 2, where k is a positive integer. Suppose that the minimum degree of G is at least (n + k)/2 . We show that G contains k pentagons and a path such that they are vertexdisjoint and cover all the vertices of G. Moreover, if n ≥ 5k + 7, then G contains k + 1 vertex-disjoint cycles covering all the vertices of G such that k of them are pentagons.

title: Deception Detection Via Blob Motion Pattern Analysis
abstract: Deception dectection is one of the most difficult problems in affect recognition and expression research area. Recently, non-verbal methods of detecting deception have appeared to be promising.  presented a proof-of-concept study based on the blob analysis of some suspects' interviews and mock experiments video clips. In this paper, we present our recent research work in the direction of developing an automated deception detection system. We propose a blob motion pattern analysis approach to solve this problem.

title: Triangles in claw-free graphs
abstract: A graph is said to be claw-free if it does not contain an induced subgraph isomorphic to K 1,3 . Let k be a positive integer. Our main result is as follows: If G is a claw-free graph of order at least 3 k and d(x) + d ( y )⩾3 k + 1 for every pair of non-adjacent vertices x and y of G , then G contains k vertex-disjoint triangles unless either k is odd and G is one exceptional graph of order 3 k + 1, or k is 1 and G is the union of vertex-disjoint cycles of length at least 4.