Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CMP, applications must expose their thread-level parallelism to the hardware. One common approach to doing this is to decompose a program into parallel "tasks" and allow an underlying software layer to schedule these tasks to different threads. Software task scheduling can provide good parallel performance as long as tasks are large compared to the software overheads.
 We examine a set of applications from an important emerging domain: Recognition, Mining, and Synthesis (RMS). Many RMS applications are compute-intensive and have abundant thread-level parallelism, and are therefore good targets for running on a CMP. However, a significant number have small tasks for which software task schedulers achieve only limited parallel speedups.
 We propose Carbon, a hardware technique to accelerate dynamic task scheduling on scalable CMPs. Carbon has relatively simple hardware, most of which can be placed far from the cores. We compare Carbon to some highly tuned software task schedulers for a set of RMS benchmarks with small tasks. Carbon delivers significant performance improvements over the best software scheduler: on average for 64 cores, 68% faster on a set of loop-parallel benchmarks, and 109% faster on aset of task-parallel benchmarks.

title: Fast Paths in Concurrent Programs

title: Threads Yield Continuations
abstract: Just as a traditional continuation represents the rest of acomputation from a given point in the computation, a subcontinuationrepresents the rest of a subcomputation from agiven point in the subcomputation. Subcontinuationsare more expressive than traditional continuations and have been shown to beuseful for controlling tree-structured concurrency, yet they havepreviously been implemented only on uniprocessors. This article describes aconcurrent implementation of one-shot subcontinuations. Like one-shotcontinuations, one-shot subcontinuations are first-class but may be invokedat most once, a restriction obeyed by nearly all programs that usecontinuations. The techniques used to implement one-shot subcontinuationsmay be applied directly to other one-shot continuation mechanisms and may begeneralized to support multi-shot continuations as well. A novel feature ofthe implementation is that continuations are implemented in terms ofthreads. Because the implementation model does not rely upon any speciallanguage features or compilation techniques, the model is applicable toany language or language implementation that supports a small set of threadprimitives.

title: Using model checking to debug device firmware
abstract: Device firmware is a piece of concurrent software that achieves high performance at the cost of software complexity. They contain subtle race conditions that make them difficult to debug using traditional debugging techniques. The problem is further compounded by the lack of debugging support on the devices. This is a serious problem because the device firmware is trusted by the operating system.Model checkers are designed to systematically verify properties of concurrent systems. Therefore, model checking is a promising approach to debugging device firmware. However, model checking involves an exponential search. Consequently, the models have to be small to allow effective model checking.This paper describes the abstraction techniques used by the ESP compiler to extract abstract models from device firmware written in ESP. The abstract models are small because they discard some of the details in the firmware that is irrelevant to the particular property being verified. The programmer is required to specify the abstractions to be performed. The ESP compiler uses the abstraction specification to extract models conservatively. Therefore, every bug in the original program will be present in the extracted model.This paper also presents our experience with using Spin model checker to develop and debug VMMC firmware for the Myrinet network interfaces.

title: Dynamic memory management for programmable devices

title: Hybrid transactional memory
abstract: High performance parallel programs are currently difficult to write and debug. One major source of difficulty is protecting concurrent accesses to shared data with an appropriate synchronization mechanism. Locks are the most common mechanism but they have a number of disadvantages, including possibly unnecessary serialization, and possible deadlock. Transactional memory is an alternative mechanism that makes parallel programming easier. With transactional memory, a transaction provides atomic and serializable operations on an arbitrary set of memory locations. When a transaction commits, all operations within the transaction become visible to other threads. When it aborts, all operations in the transaction are rolled back.Transactional memory can be implemented in either hardware or software. A straightforward hardware approach can have high performance, but imposes strict limits on the amount of data updated in each transaction. A software approach removes these limits, but incurs high overhead. We propose a novel hybrid hardware-software transactional memory scheme that approaches the performance of a hardware scheme when resources are not exhausted and gracefully falls back to a software scheme otherwise.

title: Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
abstract: Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is often an important requirement in pervasive applications. However, it has been the hardest to implement on constraint platforms due to its very high computational requirements. This contribution describes a proof-of-concept implementation for an extremely low-cost instruction set extension using reconfigurable logic, which enables an 8-bit micro-controller to provide full size elliptic curve cryptography (ECC) capabilities. Introducing full size public-key security mechanisms on such small embedded devices will allow new pervasive applications. We show that a standard compliant 163-bit point multiplication can be computed in 0.113 sec on an 8-bit AVR micro-controller running at 4 Mhz with minimal extra hardware, a typical representative for a low-cost pervasive processor. Our design not only accelerates the computation by a factor of more than 30 compared to a software-only solution, it also reduces the code-size, data-RAM and power requirements.

title: Asynchronous Genetic Algorithms for Heterogeneous Networks Using Coarse-Grained Dataflow
abstract: Genetic algorithms (GAs) are an attractive class of techniques for solving a variety of complex search and optimization problems. Their implementation on a distributed platform can provide the necessary computing power to address large-scale problems of practical importance. On heterogeneous networks, however, the performance of a global parallel GA can be limited by synchronization points during the computation, particularly those between generations. We present a new approach for implementing asynchronous GAs based on the dataflow model of computation -- an approach that retains the functional properties of a global parallel GA. Experiments conducted with an air quality optimization problem and others show that the performance of GAs can be substantially improved through dataflow-based asynchrony.

title: Digital tapestry [automatic image synthesis]
abstract: This paper addresses the novel problem of automatically synthesizing an output image from a large collection of different input images. The synthesized image, called a digital tapestry, can be viewed as a visual summary or a virtual 'thumbnail' of all the images in the input collection. The problem of creating the tapestry is cast as a multi-class labeling problem such that each region in the tapestry is constructed from input image blocks that are salient and such that neighboring blocks satisfy spatial compatibility. This is formulated using a Markov random field and optimized via the graph cut based expansion move algorithm. The standard expansion move algorithm can only handle energies with metric terms, while our energy contains non-metric (soft and hard) constraints. Therefore we propose two novel contributions. First, we extend the expansion move algorithm for energy functions with non-metric hard constraints. Secondly, we modify it for functions with "almost" metric soft terms, and show that it gives good results in practice. The proposed framework was tested on several consumer photograph collections, and the results are presented.

title: Increased watermark-to-host correlation of uniform random phase watermarks in audio signals
abstract: We analyze the watermark-to-host correlation (WHC) of random phase watermarks, in the context of additive embedding and blind correlation-detection of the watermark in audio signals. Interestingly, we find that WHC is higher when a legitimate watermark is present in the audio signal. Instead of trying to minimize the WHC, one could also attempt to harness this increased correlation in order to result in better detection performance. The analysis shows that uniformly distributed phase difference (between the host signal and the watermark) provides maximum advantage. It is also verified that, a uniformly distributed watermark phase provides the most advantage, experimented over a variety of audio signals.

title: Semantics of Agent Communication Languages for Group Interaction
abstract: Group communication is the core of societal interactions. Therefore, artificial agents should be able to communicate with groups as well as individuals. However, most contemporary agent communication languages, notably FIPA and KQML, have either no provision or no well-defined semantics for group communication. We give semantics for group communication that we believe can profitably enrich the agent communication languages. In our semantics, individual communication is a special case of group communication wherein each communicating group consists of a single agent.