Development of a counting strip detector readout chip for precision compton polarimetry
A strip detector readout chip used in an individual photon counting detection system for precision Compton polarimetry has been chosen as a platform for the implementation, comparison and the in-silicon test of several alternative architectural analog and digital circuit concepts. For this application first an analytic result for the noise optimization has been derived based on the EKV model which gives the optimum width of the input transistor of the charge sensitive amplifier as a function of the inversion factor. Apart from the input transistor, the noise contribution from the biasing for a folded and a telescopic cascode preamplifier topology has also been analyzed. The limitations of conventional shaping circuits using MOS transistors operating in linear region as feedback elements are emphasized and alternative shaping topologies based on linearized transconductance amplifier are introduced. A potential hazard of synchronous counters reacting on very short clock pulses is described which becomes much less severe when the implementation is changed to asynchronous ripple counters. All digital circuitry has been implemented in Differential Current Logic to reduce crosstalk between the digital and the analog circuitry. The trade-offs which are related to the presented architectural options are extracted from measurements and simulations.

title: Search for nonpointing and delayed photons in the diphoton and missing transverse momentum final state in 8 TeV pp collisions at the LHC using the ATLAS detector
abstract: A search has been performed, using the full 20.3 fb(-1) data sample of 8 TeV proton-proton collisions collected in 2012 with the ATLAS detector at the LHC, for photons originating from a displaced vertex due to the decay of a neutral long-lived particle into a photon and an invisible particle. The analysis investigates the diphoton plus missing transverse momentum final state, and is therefore most sensitive to pair production of long-lived particles. The analysis technique exploits the capabilities of the ATLAS electromagnetic calorimeter to make precise measurements of the flight direction, as well as the time of flight, of photons. No excess is observed over the Standard Model predictions for background. Exclusion limits are set within the context of gauge mediated supersymmetry breaking models, with the lightest neutralino being the next-to-lightest supersymmetric particle and decaying into a photon and gravitino with a lifetime in the range from 250 ps to about 100 ns.

title: Performance of a DEPFET prototype module for the ILC vertex detector
abstract: For the detection of secondary vertices of long lived bottom and charm quarks at the proposed International Linear Collider (ILC) a DEPFET pixel detector is one of the favored technology options. DEPFET pixel sensors, in which the amplifying transistor structure is contained in the pixel cell itself on a fully depleted bulk, are unique devices in terms of their large signal and low noise capability and their obtainable spatial resolution with very thin detectors. DEPFET pixel prototype modules with close to ILC specifications have been tested in the laboratory and, for the first time, in a 6 GeV electron test beam. The different noise sources have been calculated and compared with the measured value of ENC/spl ap/225 e/sup -/ for the entire readout chain.

title: DMAPS: a fully depleted monolithic active pixel sensor—analog performance characterization
abstract: Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s based on silicon substrates with a thin epitaxial layer (thickness of 10–15 μm) in which charge is collected on an electrode, albeit by disordered and slow diffusion rather than by drift in a directed electric field. As a consequence, the signal of these conventional MAPS is small (≈1000 e−) and the radiation tolerance is limited. In this paper, the development of a fully Depleted Monolithic Active Pixel Sensors (DMAPS) based on a high resistivity substrate allowing the creation of a fully depleted detection volume is presented. This concept overcomes the inherent limitations of charge collection by diffusion in the standard MAPS designs. We present results from a prototype chip EPCB01 designed in a commercial 150 nm CMOS technology. The technology provides a thin (≈50 μm) high resistivity n-type silicon substrate as well as an additional deep p-well which allows to integrate full CMOS circuitry inside the pixel. Different matrix types with several variants of collection electrodes and pixel electronics have been implemented. Measurements of the analog performance of this first implementation of DMAPS pixels are presented.

title: A serial powering scheme for the ATLAS pixel detector at sLHC
abstract: Powering concepts, such as serial powering and DC-DC conversion, are in development for the silicon trackers at sLHC to achieve an efficient power distribution with a minimum volume of cables. This paper will describe the serial powering scheme developed for the upgraded ATLAS pixel detector, with focus on the scheme architecture and on the main components involved: the Shunt-LDO regulator and the protection scheme. Issues connected to system aspects will be discussed, and the advantages in terms of material reduction provided by the proposed serial powering scheme will be presented.

title: Test results of the Data Handling Processor for the DEPFET Pixel Vertex Detector
abstract: In the new Belle II detector, which is currently under construction at the SuperKEKB accelerator, a two layer pixel detector will be introduced to improve the vertex reconstruction in a ultra high luminosity environment. The pixel detector will be produced using the DEPFET technology. A new ASIC (Data Handling Processor or DHP) designed to steer the readout process, pre-process and compress the raw data has been developed. The DHP will be directly bump bonded to the balcony of the all-silicon DEPFET module. The current chip prototype has been produced in CMOS 90 nm. Its test results, including the data processing quality, the signal integrity of the gigabit transmission lines will be presented here. For the final chip, which will be produced using CMOS 65 nm, single event upset (SEU) cross sections were measured. An additional chip, containing memory blocks to be tested, was submitted and produced using this technology.

title: Production asymmetry of Ds from 600 GeV//c Sigma- and pi- beam

title: Polarization of Σ+ hyperons produced by 800 GeV/c protons on Cu and Be
abstract: We show that  hyperons produced by 800 GeV/c protons on targets of Be and Cu have significant polarizations (15-20%). These polarizations persist at values of p{sub t}{approx_equal}2 GeV/c and a wide range of x{sub F}. The polarizations from the Cu target are consistently less than from Be. The average ratio of the {sigma}{sup +} polarization from Cu to that from Be is 0.68{+-}0.08.

title: Nuclear dependence of charm production
abstract: Using data taken by SELEX during the 1996–1997 fixed target run at Fermilab, we study the production of charmed hadrons on copper and carbon targets with Σ−, p, π−, and π+ beams. Parametrizing the dependence of the inclusive production cross section on the atomic number A as Aα, we determine α for D+, D0, Ds+, D+(2010), Λc+, and their respective anti-particles, as a function of their transverse momentum pt and scaled longitudinal momentum xF. Within our statistics there is no dependence of α on xF for any charm species for the interval 0.1<xF<1.0. The average value of α for charm production by pion beams is αmeson=0.850±0.028. This is somewhat larger than the corresponding average αbaryon=0.755±0.016 for charm production by baryon beams (Σ−, p).