Helper threads via virtual multithreading
Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: BLoG: Post-Silicon bug localization in processors using bug localization graphs
abstract: Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.

title: Register renaming and scheduling for dynamic execution of predicated code
abstract: To achieve higher processor performance requires greater synergy between advanced hardware features and innovative compiler techniques. Recent advancement in compilation techniques for predicated execution has provided significant opportunity in exploiting instruction level parallelism. However, little research has been done on how to efficiently execute predicated code in a dynamic microarchitecture. In this paper, we evaluate hardware optimizations for executing predicated code on a dynamically scheduled microarchitecture. We provide two novel ideas to improve the efficiency of executing predicated code. On a generic Intel Itanium processor pipeline model, we demonstrate that, with some microarchitecture enhancements, a dynamic execution processor can achieve about 16% performance improvement over an equivalent static execution processor.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

title: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers

title: Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
abstract: This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

title: PAD Model Based Facial Expression Analysis
abstract: The validity of PAD (Pleasure-Arousal-Dominance) theory in vision area and the feasibilityT on PAD based models for facial expression analysis are discussed in this paper. Three new models based on PAD theory are proposed and their feasibility is verified by experiments on Cohn-Kanade dataset and PAD dataset which is collected from well-designed psychological experiments. After combining Gabor feature and SVM (Support Vector Machine), the result can be further improved. Compared with the basic expression models, our experiments show that the predominance of PAD based model is that it can represent almost any states of expression. Finally, our preliminary experiments show that distinguishing different grades of the same expression is promising by our models.

title: Estimation delay compensation in high-gain observer-based parameter identification
abstract: In this paper, the properties of the disturbance estimation in a high gain observer are analyzed, and a time delay calculation method is proposed to improve the performance of parameter identification. This paper shows that the estimation delay depends on the observer gain, but has nothing to do with the parameter variation. Then, a novel algorithm is proposed to calculate the delay according to the phase response of disturbance estimation transfer function. Hence, in terms of system identification, this delay is compensated by lagging the state estimate by the same amount of delay. This technique, on one side, improves the performance of parameter identification accuracy, and, on the other side, gives a new insight into the high-gain observer design.

title: Reliable Observer-Based Control Against Sensor Failures for Systems With Time Delays in Both State and Input
abstract: For systems with both state and input time delays, a novel state and sensor fault observer is proposed in this paper to estimate system states and sensor faults simultaneously. In this design, a descriptor system approach and a linear matrix inequality technique are adopted, where the considered sensor fault may be in any form, even unbounded. Unbounded sensor faults will make the system fail unavoidably; it is indispensable to derive a reliable control scheme against sensor failures. Using the estimated state and sensor fault, a reliable observer-based controller is proposed, which makes the system work well no matter whether sensor faults occur or not. The present approaches are next extended to the case for systems with multiple time delays. Finally, a simulation example of the network of three cascaded reactors is used to illustrate the design procedure and demonstrate the efficiency of the present techniques.

title: Temperature dependence of DC characteristics of NpN InP/GaAsSb/InP double heterojunction bipolar transistors: an analytical study
abstract: An analytic study of DC characteristics based on the drift-diffusion approach has been performed for the InP/GaAsSb DHBTs. The current transport of InP/GaAsSb/InP DHBTs has been investigated focusing the device temperature dependence. Our simulation results show that, at room temperature, the DC characteristics of the InP/GaAsSb/InP DHBTs similar to the conventional InP-based HBT using InGaAs as the base layer although a type-II energy band alignment is presented in the InP/GaAsSb HBT. However, due to different mechanisms for the electron injection from the emitter induced by the different conduction band alignments, the InP/GaAsSb HBTs may present a different temperature dependent behavior in term of device current gain as compared to the conventional InP/InGaAs HBTs. Higher current gain could be achieved by the InP/GaAsSb HBTs at elevated temperature.

title: A scalable associative processor with applications in database and image processing
abstract: This paper describes the implementation and use of a dedicated associative SIMD coprocessor ideally suited for many applications such as database processing, image processing, genome matching, or molecular similarity analysis. The concept of associative SIMD processing is introduced, and differentiated from other associative and SIMD techniques. Then our ASC (associative computing) processor is briefly described, along with its implementation of associative SIMD processing. Finally, we demonstrate the use of our ASC processor on relational database processing and on the image processing operation of edge detection.