Buffering databse operations for enhanced instruction cache performance
As more and more query processing work can be done in main memory access is becoming a significant cost component of database operations. Recent database research has shown that most of the memory stalls are due to second-level cache data misses and first-level instruction cache misses. While a lot of research has focused on reducing the data cache misses, relatively little research has been done on improving the instruction cache performance of database systems.We first answer the question "Why does a database system incur so many instruction cache misses?" We demonstrate that current demand-pull pipelined query execution engines suffer from significant instruction cache thrashing between different operators. We propose techniques to buffer database operations during query execution to avoid instruction cache thrashing. We implement a new light-weight "buffer" operator and study various factors which may affect the cache performance. We also introduce a plan refinement algorithm that considers the query plan and decides whether it is beneficial to add additional "buffer" operators and where to put them. The benefit is mainly from better instruction locality and better hardware branch prediction. Our techniques can be easily integrated into current database systems without significant changes. Our experiments in a memory-resident PostgreSQL database system show that buffering techniques can reduce the number of instruction cache misses by up to 80% and improve query performance by up to 15%.

title: Architecture Sensitive Database Design: Examples from the Columbia Group
abstract: In this article, we discuss how different aspects of modern CPU architecture can be effectively used by database systems. While we shall try to cover most important aspects of modern architectures, we shall not aim to provide an exhaustive survey of the literature. Rather, we will use examples from our own recent work to illustrate the principles involved. While there is related work on using other components of modern machines such as graphics cards and intelligent disk controllers for database work, we limit our discussion here to just a single CPU and the memory hierarchy (excluding disks). In recent years the primary focus of database performance research has fundamentally shifted from disks to main memory. Systems with a very large main memory allow a database’s working set to fit in RAM. At the same time processors have continued to double in performance roughly every eighteen months in line with “Moore’s Law,” while memory speed improvements have been marginal. The CPU now spends many hundreds of cycles waiting for data to arrive from main memory, and database workloads are often memory-bound. Because of this bottleneck, database research at Columbia and elsewhere has focused on effectively using the cache hierarchy to improve database performance. Changes in processor technology have also influenced database research. Modern processors feature a very long pipeline, which helps to provide better performance. It also results in a higher branch misprediction penalty, because the pipeline must be flushed and restarted when a branch is mispredicted. Modern CPUs provide the database programmer with a rich instruction set. Using specialized instructions, such as SIMD instructions, database performance can be improved by allowing a degree of parallelism and eliminating some conditional branch instructions, thus reducing the impact of branch mispredictions.

title: Implementing database operations using SIMD instructions
abstract: Modern CPUs have instructions that allow basic operations to be performed on several data elements in parallel. These instructions are called SIMD instructions, since they apply a single instruction to multiple data elements. SIMD technology was initially built into commodity processors in order to accelerate the performance of multimedia applications. SIMD instructions provide new opportunities for database engine design and implementation. We study various kinds of operations in a database context, and show how the inner loop of the operations can be accelerated using SIMD instructions. The use of SIMD instructions has two immediate performance benefits: It allows a degree of parallelism, so that many operands can be processed at once. It also often leads to the elimination of conditional branch instructions, reducing branch mispredictions.We consider the most important database operations, including sequential scans, aggregation, index operations, and joins. We present techniques for implementing these using SIMD instructions. We show that there are significant benefits in redesigning traditional query processing algorithms so that they can make better use of SIMD technology. Our study shows that using a SIMD parallelism of four, the CPU time for the new algorithms is from 10% to more than four times less than for the traditional algorithms. Superlinear speedups are obtained as a result of the elimination of branch misprediction effects.

title: Scalable simulation of large-scale wireless networks with bounded inaccuracies
abstract: Discrete event network simulators have emerged as popular tools for verification and performance evaluation for various wireless networks. Nevertheless, the desire to model such networks at high fidelity implies high computational costs, prohibiting most researchers from simulating wireless networks with thousands of nodes. There have been attempts on performance optimizations for large-scale wireless network simulation, but they have not appropriately modeled accumulation of weak interference, thereby suffering inaccuracies which may be magnified by upper layer protocols. This paper presents analysis of the effects of common optimization techniques for large-scale wireless network simulation on the overall network performance and also proposes modifications and novel techniques that introduce only limited inaccuracies or no additional inaccuracy at all. The study quantifies the effects of those optimizations on the simulation results for given thresholds and network parameters, and also identifies thresholds tolerable to most network studies. The experimental results show that these optimizations can improve the runtime performance of an already efficient wireless network simulator substantially, by a factor of up to 55 for wireless networks with 3200 nodes without compromising accuracy of the simulation results.

title: Undeniable Mobile Billing Schemes
abstract: An undeniable mobile billing system allows a mobile network service provider to bill its subscribers with trustworthy evidences. Chen, Jan and Chen proposed such a billing system by introducing a trusted third party - Observer and exploiting a hash chain mechanism. In their system, the Observer provides call time evidence to both cellular carriers and subscribers for billing. In this paper, we first identify some vulnerabilities in their mobile billing system. Then, we propose an undeniable billing scheme based on a proper combination of digital signature and hash chain mechanism. The proposed scheme can achieve authentication, non-repudiation, and fairness, which are desirable security requirements for an undeniable mobile billing system.

title: Security Analysis of Some Proxy Signatures
abstract: A proxy signature scheme allows an entity to delegate his/her signing capability to another entity in such a way that the latter can sign messages on behalf of the former. Such schemes have been suggested for use in a number of applications, particularly in distributed computing where delegation of rights is quite common. Followed by the first schemes introduced by Mambo, Usuda and Okamoto in 1996, a number of new schemes and improvements have been proposed. In this paper, we present a security analysis of four such schemes newly proposed in [14, 15]. By successfully identifying several interesting forgery attacks, we show that these four schemes all are insecure. Consequently, the fully distributed proxy scheme in [11] is also insecure since it is based on the (insecure) LKK scheme [13, 14]. In addition, we point out the reasons why the security proofs provided in  are invalid.

title: Verification - a method of enhancing the recognizers of isolated and touching handwritten numerals
abstract: This paper investigates verification schemes and their applications to the recognition of both isolated and touching handwritten numerals. Definitions and functionality analyses of the verifiers are given. The measurement of precision rate is used to assess the system reliability in a class-specific manner. Verification-enhanced systems are proposed with extensive experiments conducted on both isolated and touching numerals. Two databases for touching numerals are built/organized to serve as standard data sets. Experimental results indicate a substantial improvement in system precision rates by the verification scheme, which proves the effectiveness of the proposed systems and justifies the important role of verifiers in OCR systems.

title: Code Parameterization for Satisfaction of QoS Requirements in Embedded Software
abstract: The rapid growth of embedded systems urgently requires methods of improving the development process for these systems. Component-based development (CBD) techniques have been widely studied to enhance the productivity of developing complex applications. These techniques can benefit the software development process for embedded systems as well as other application domains. However, applying CBD techniques to embedded software development faces additional challenges. For embedded systems, it is crucial to consider the QoS attributes, such as timeliness, memory limitations, output precision, battery constraints, etc. However, it is often difficult to adjust the QoS properties of a system integrated from components that do not consider QoS properties in the first place. In this paper, we present an overview of a repository-based embedded software development methodology and then focus on component parameterization techniques. The basic concept of the parameterization process is to identify configurable parameters in a component that can be parameterized to achieve QoS tradeoffs. The component is then modified to a reconfigurable one such that its configurable parameters can be adjusted to satisfy different QoS requirements for various applications or for dynamical changing execution environment. A rule base is used to assist the parameter identification process. We also develop delta file technique to facilitate component adaptation and testing tools for QoS data collection. Keywords-embedded system, component parameterization, QoS, Repository system