CPR: Composable performance regression for scalable multiprocessor models
Uniprocessor simulators track resource utilization cycle by cycle to estimate performance. Multiprocessor simulators, however, must account for synchronization events that increase the cost of every cycle simulated and shared resource contention that increases the total number of cycles simulated. These effects cause multiprocessor simulation times to scale superlinearly with the number of cores. Composable performance regression (CPR) fundamentally addresses these intractable multiprocessor simulation times, estimating multiprocessor performance with a combination of uniprocessor, contention, and penalty models. The uniprocessor model predicts baseline performance of each core while the contention models predict interfering accesses from other cores. Uniprocessor and contention model outputs are composed by a penalty model to produce the final multiprocessor performance estimate. Trained with a production quality simulator, CPR is accurate with median errors of 6.63, 4.83 percent for dual-, quad-core multiprocessors. Furthermore, composable regression is scalable, requiring 0.33x the simulations required by prior regression strategies.

title: Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
abstract: This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

title: Helper threads via virtual multithreading
abstract: Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: BLoG: Post-Silicon bug localization in processors using bug localization graphs
abstract: Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.

title: Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
abstract: Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

title: Dynamic speculative precomputation
abstract: A large number of memory accesses in memory-bound applications are irregular, such as pointer dereferences, and can be effectively targeted by thread-based prefetching techniques like Speculative Precomputation. These techniques execute instructions, for example on an available SMT thread context, that have been extracted directly from the program they are trying to accelerate. Proposed techniques typically require manual user intervention to extract and optimize instruction sequences. This paper proposes Dynamic Speculative Precomputation, which performs all necessary instruction analysis, extraction, and optimization through the use of back-end instruction analysis hardware, located off the processor's critical path. For a set of memory limited benchmarks an average speedup of 14% is achieved when constructing simple p-slices, and this gain grows to 33% when making use of aggressive optimizations.

title: Model reference adaptive control of the output stochastic distributions for unknown linear stochastic systems
abstract: This paper presents a model reference based adaptive control approach for the control of the output probability density function for unknown linear time-invariant stochastic systems. Different from most existing models used in stochastic control, it is assumed here that the measured control input directly affects the distribution of the system output in probability sense. As such, the purpose of control is to make the shape of the probability density function of the system output as close as possible to a prespecified one. Using the weighted integration of the measurable output probability density functions, two adaptive on-line updating rules are developed which guarantee the global stability for theclosed loop adaptive control system under certain conditions. Ithas been shown, when there is no external disturbance, that the so-formed closed loop system also realizes the perfect tracking (i.e., the probability density function of the system output approaches a class of given distributions asymptotically)...

title: Deception Detection Via Blob Motion Pattern Analysis
abstract: Deception dectection is one of the most difficult problems in affect recognition and expression research area. Recently, non-verbal methods of detecting deception have appeared to be promising.  presented a proof-of-concept study based on the blob analysis of some suspects' interviews and mock experiments video clips. In this paper, we present our recent research work in the direction of developing an automated deception detection system. We propose a blob motion pattern analysis approach to solve this problem.

title: Analysis of DC characteristics of GaAs double heterojunction bipolar transistors (DHBTs) with a pseudomorphic GaAsSb base
abstract: In this paper, DC characteristics in GaAs DHBTs with pseudomorphic GaAsSb base layer are investigated using an analytical approach. Devices using different GaAs 1− x Sb x base thickness with different Sb compositions were simulated to gain an in-depth understanding on the effect of base layer design on the device DC performance. Our calculated results show that, in the GaAsSb base with high Sb composition, the strain plays a non-negligible role in determining the overall device performance. The reduction of B–E turn-on voltage using a large Sb composition of GaAs 1− x Sb x could be partially compensated by strain in the base. Furthermore, for the devices using high Sb composition, a thin base layer has to be used to ensure elastic strain. In order to maintain reasonable base conductivity that is critical for device microwave performance, high base doping is required. However, our simulation reveals a drastic reduction of DC gain with the increase in base doping, while a high emitter doping may be helpful for the compensation of the degradation of β. A proper design of the device structure by taking the aforementioned issues into account is important for improving device DC and microwave performance.

title: Delay-dependent fault detection and diagnosis using B-spline neural networks and nonlinear filters for time-delay stochastic systems
abstract: A new fault detection and diagnosis (FDD) scheme is studied in this paper for the continuous-time stochastic dynamic systems with time delays, where the available information for the FDD is the input and the measured output probability density functions (PDFs) of the system. The square-root B-spline neural networks is used to formulate the output PDFs with the dynamic weightings. As a result, the concerned FDD problem can be transformed into a robust FDD problem subjected to a continuous time uncertain nonlinear system with time delays. Delay-dependent criteria to detect and diagnose the system fault are provided by using linear matrix inequality (LMI) techniques. It is shown that this new criterion can provide higher sensitivity performance than the existing result. Simulations are given to demonstrate the efficiency of the proposed approach.

title: An Algorithm for Identification of Reduced-Order Dynamic Models of Gas Turbines
abstract: Model based approaches show a lot of advantages for fault detection and condition monitoring. Particularly, it is true in employing reduced order models for real-time parameter identification and output prediction of gas turbines. Many algorithms have been developed, but most of them focus on one-step-ahead prediction models and involve complex computation. These algorithms are not acceptable for long-term prediction and real-time condition monitoring. In this paper, an improved gradient method (dynamic gradient descent) is proposed. The idea is to take account of the dependency of prediction errors and calculate the gradient information recursively. Not only low computation expense is achieved, but the non-Gaussian errors can also be overcome when this approach is applied to estimate parameters of a reduced order gas turbine model and to improve long-term prediction