Threads Yield Continuations
Just as a traditional continuation represents the rest of acomputation from a given point in the computation, a subcontinuationrepresents the rest of a subcomputation from agiven point in the subcomputation. Subcontinuationsare more expressive than traditional continuations and have been shown to beuseful for controlling tree-structured concurrency, yet they havepreviously been implemented only on uniprocessors. This article describes aconcurrent implementation of one-shot subcontinuations. Like one-shotcontinuations, one-shot subcontinuations are first-class but may be invokedat most once, a restriction obeyed by nearly all programs that usecontinuations. The techniques used to implement one-shot subcontinuationsmay be applied directly to other one-shot continuation mechanisms and may begeneralized to support multi-shot continuations as well. A novel feature ofthe implementation is that continuations are implemented in terms ofthreads. Because the implementation model does not rely upon any speciallanguage features or compilation techniques, the model is applicable toany language or language implementation that supports a small set of threadprimitives.

title: Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
abstract: We explore the emerging application area of physics-based simulation for computer animation and visual special effects. In particular, we examine its parallelization potential and characterize its behavior on a chip multiprocessor (CMP). Applications in this domain model and simulate natural phenomena, and often direct visual components of motion pictures. We study a set of three workloads that exemplify the span and complexity of physical simulation applications used in a production environment: fluid dynamics, facial animation, and cloth simulation. They are computationally demanding, requiring from a few seconds to several minutes to simulate a single frame; therefore, they can benefit greatly from the acceleration possible with large scale CMPs.
 Starting with serial versions of these applications, we parallelize code accounting for at least 96% of the serial execution time, targeting a large number of threads.We then study the most expensive modules using a simulated 64-core CMP.
 For the code representing key modules, we achieve parallel scaling of 45x, 50x, and 30x for fluid, face, and cloth simulations, respectively. The modules have a spectrum of parallel task granularity and locking behavior, and all but one are dominated by loop-level parallelism. Many modules operate on streams of data. In some cases, modules iterate over their data, leading to significant temporal locality. This streaming behavior leads to very high on-die and main memory bandwidth requirements. Finally, most modules have little inter-thread communication since they are data-parallel, but a few require heavy communication between data-parallel operations.

title: Hybrid transactional memory
abstract: High performance parallel programs are currently difficult to write and debug. One major source of difficulty is protecting concurrent accesses to shared data with an appropriate synchronization mechanism. Locks are the most common mechanism but they have a number of disadvantages, including possibly unnecessary serialization, and possible deadlock. Transactional memory is an alternative mechanism that makes parallel programming easier. With transactional memory, a transaction provides atomic and serializable operations on an arbitrary set of memory locations. When a transaction commits, all operations within the transaction become visible to other threads. When it aborts, all operations in the transaction are rolled back.Transactional memory can be implemented in either hardware or software. A straightforward hardware approach can have high performance, but imposes strict limits on the amount of data updated in each transaction. A software approach removes these limits, but incurs high overhead. We propose a novel hybrid hardware-software transactional memory scheme that approaches the performance of a hardware scheme when resources are not exhausted and gracefully falls back to a software scheme otherwise.

title: Evaluating synchronization on shared address space multiprocessors: methodology and performance
abstract: Synchronization is an area that exhibits rich hardware-software interactions in multiprocessors. It was studied extensively using microbenchmarks a decade ago. However, its performance implications are not well understood on modern systems or on real applications. We study the impact of synchronization primitives and algorithms on a modern, 64processor, hardware-coherent shared address space multiprocessor: the SGI Origin 2000. In addition to the actual results on a modern system, we examine the key methodological issues in studying synchronization, for both microbenchmarks and applications. We find that although the efficient hardware support (Fetch&Op) for synchronization provided on our machine usually helps lock and barrier microbenchmarks, it does not help in improving application performance when compared to good software algorithms that use the processor-provided LL-SC instructions. This is true even in applications that spend a significant amount of time in synchronization operations. More elaborate hardware support is unlikely to have a significant benefit either. From the applications’ perspective, it is usually the waiting time due to load imbalance or serialization that dominates synchronization time, not the overhead of the synchronization operations themselves, even in apparently balanced cases where the overhead may be expected to be substantial.

title: Dynamic memory management for programmable devices

title: Compilation, architectural support, and evaluation of SIMD graphics pipeline programs on a general-purpose CPU
abstract: Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a small program for each fragment in the graphics pipeline. We investigate low-cost mechanisms to obtain good performance for modern graphics programs on a general purpose CPU. We present a compiler that compiles SIMD graphics program and generates efficient code on a general purpose CPU. The generated code can process between 25-0.3 million vertices per second on a 2.2 GHz Intel Pentium/spl reg/ 4 processor for a group of typical graphics programs. We also evaluate the impact of three changes in the architecture and compiler. Adding support for new specialized instructions improves the performance of the programs by 27.4% on average. A novel compiler optimization called mask analysis improves the performance of the programs by 19.5% on average. Increasing the number of architectural SIMD registers from 8 to 16 registers significantly reduces the number of memory accesses due to register spills.

title: Discriminative Fields for Modeling Spatial Dependencies in Natural Images
abstract: In this paper we present Discriminative Random Fields (DRF), a discriminative framework for the classification of natural image regions by incorporating neighborhood spatial dependencies in the labels as well as the observed data. The proposed model exploits local discriminative models and allows to relax the assumption of conditional independence of the observed data given the labels, commonly used in the Markov Random Field (MRF) framework. The parameters of the DRF model are learned using penalized maximum pseudo-likelihood method. Furthermore, the form of the DRF model allows the MAP inference for binary classification problems using the graph min-cut algorithms. The performance of the model was verified on the synthetic as well as the real-world images. The DRF model outperforms the MRF model in the experiments.

title: Wavelet directional histograms for classification of human gestures represented by spatio-temporal templates
abstract: This paper evaluates the efficacy of directional information of wavelet multi-resolution decomposition for histogram-based classification of human gestures represented by spatio-temporal templates. This template collapses temporal component into gesture representation in a way that no explicit sequence matching or temporal analysis is needed, and characterizes the motion from a very high dimensional space to a low dimensional space. These templates are modified to be invariant to translation, rotation and scale. Two dimensional, 3 level dyadic wavelet transform applied on these templates results in one low pass subimage and nine highpass directional subimages. Histograms of wavelet coefficients at different scales are compared to establish significance of available information for classification. The preliminary experiments show that while the statistical properties of the template provide high level of classification accuracy, the available information in high pass or low pass decompositions by itself is not sufficient to provide significant efficiency of accuracy.

title: Error-resilient coding of 3-D graphic models via adaptive mesh segmentation
abstract: Current coding techniques for 3-D graphic models mainly focus on coding efficiency, which makes them extremely sensitive to channel errors due to the irregular mesh structure. We introduce a new approach for error-resilient coding of arbitrary 3-D graphic models by extending the error-free constructive traversal compression scheme proposed by Li and Kuo (see MPEG-4 Tokyo Meeting, 1998, , and Proc.  vol.86, p.1052-63, 1998). A 3-D mesh of an arbitrary structure is partitioned into pieces of a smaller uniform size with joint boundaries. The size of a piece is determined adaptively based on the channel error rate. The topology and geometry information of each joint boundary and each piece of a connected component is coded independently. The coded topology and first several important bit-planes of the joint-boundary data are protected against channel errors by using the Bose-Chaudhuri-Hocquenghem error-correcting code. At the decoder, each piece is decoded and checked for channel errors. The decoded joint-boundary information is used to perform data recovery and error concealment on the corrupted piece data. All decoded pieces are combined together according to their configuration to reconstruct all connected components of the complete 3-D model. Our experiments demonstrate that the proposed approach has excellent error resiliency at a reasonable bit-rate overhead. The techniques is also capable of incrementally rendering one connected component of the 3-D model at a time.

title: STAPLE: An agent programming language based on the joint intention theory
abstract: Joint intention theory has been used for rule based creation of teams and to provide a formal semantics for communicative acts but there were no agent programming languages linked to this theory. We proposed a declarative agent programming language called STAPLE whose logical semantics is given by the joint intention theory. This paper illustrates the STAPLE support for communication and teamwork in a unified framework.

title: A Weighted Finite State Transducer Implementation of the Alignment Template Model for Statistical Machine Translation
abstract: We present a derivation of the alignment template model for statistical machine translation and an implementation of the model using weighted finite state transducers. The approach we describe allows us to implement each constituent distribution of the model as a weighted finite state transducer or acceptor. We show that bitext word alignment and translation under the model can be performed with standard FSM operations involving these transducers. One of the benefits of using this framework is that it obviates the need to develop specialized search procedures, even for the generation of lattices or N-Best lists of bitext word alignments and translation hypotheses. We evaluate the implementation of the model on the French-to-English Hansards task and report alignment and translation performance.