On Reduced Structure Control and the 1-norm regularisation
This paper studies the controller structure selection problem for large multivariable systems. Current approaches to this problem either rely on the control engineer's experience and intuition, or solutions of very difficult and non-convex combinatorial optimisation problems. In this paper new computationally inexpensive analysis tools are presented which provide the control engineer with a complete set of optimal controller structures for a given system. Furthermore, the proposed tools can be used directly to assess the local structural sensitivity of the problem and identify key and important connections within the controller. These tools are applied here to the model of a real-life gas-turbine engine.

title: An Intelligent Mill Load Switching Control of the Pulverizing System for an Alumina Sintering Process
abstract: This paper proposes an intelligent switching control strategy for the pulverizing system for an alumina sintering process. The control strategy consists of a coordinating controller, a proportional-integral (PI) controller, a rule-based reasoning controller and a switching mechanism. The practical application to a pulverizing system in an alumina sintering process has shown that when the hot air temperature is low and varies frequently, this control strategy ensures that the mill load and the temperature of the mill outlet are both within their required ranges, and also controls the mill load at the level corresponding to the maximum mill output. Moreover, it has been observed that the proposed control strategy can avoid the fault operating condition and effectively reduce the unit energy consumption.

title: Advances in stochastic distribution control
abstract: Stochastic distribution control systems aims at the controller design so as to realize a shape control of the distributions of certain random variables in the process. Once the probability density functions (PDFs) of these variables are used to describe their distributions, the control task is to obtain control signals so that the output PFDs of the system are made to follow their target PDFs. In this paper, a survey of the recent developments on the research of stochastic distribution control systems will be made.

title: Novel Parameter Identification by Using a High-Gain Observer With Application to a Gas Turbine Engine
abstract: In this study, a novel identification technique, that is high-gain observer-based identification approach, is proposed for systems with bounded process and measurement noises. For system parameters with abnormal changes, an adaptive change detection and parameter identification algorithm is next presented. The presented technique and algorithm are finally applied to the parameter identification of the gas turbine engine by using the recorded input data from the engine test-bed. The identified parameters and the response curves are desirable. The simulations have proved the effectiveness of the proposed procedure compared with the previous identification approach.

title: Minimum entropy control of nonlinear ARMA systems over a communication network
abstract: In this paper, the entropy concept has been utilized to characterize the uncertainty of the tracking error for nonlinear ARMA stochastic systems over a communication network, where time delays in the communication channels are of random nature. A recursive optimization solution has been developed. In addition, an alternative algorithm is also proposed based on the probability density function of the tracking error, which is estimated by a neural network. Finally, a simulation example is given to illustrate the efficiency and feasibility of the proposed approach.

title: Descriptor observer approaches for multivariable systems with measurement noises and application in fault detection and diagnosis
abstract: In this paper, new descriptor observer design approaches are presented for multivariable systems with measurement noises. If the system matrix is stable, the proposed modified proportional and derivative observer technique allows us not only to decouple the measurement noise in any forms completely, but also obtain accurate estimations of both system states and measurement noises. If the system is detectable and the noise is bounded, it has been shown that two design parameters can provide more degrees of freedom. In this context, the derivative gain parameter is chosen to reduce the amplification of the noise, and the proportional gain is then selected to guarantee the stability of the error dynamics. For systems with both measurement output noises and input disturbances, a modified proportional, derivative and integral observer is constructed to asymptotically estimate states, input disturbances, and output noises at the same time. The applications of the proposed observers for systems with actuator and sensor faults are also discussed. Numerical examples are given to illustrate the design procedures, and the simulation results show the satisfactory tracking performance.

title: Control Flow Optimization Via Dynamic Reconvergence Prediction
abstract: This paper presents a novel microarchitecture technique for accurately predicting control flow reconvergence dynamically. A reconvergence point is the earliest dynamic instruction in the program where we can expect program paths to reconverge regardless of the outcome or target of the current branch. Thus, even if the immediate control flow after a branch is uncertain, execution following the reconvergence point is certain. This paper proposes a novel hardware re-convergence predictor which is both implementable and accurate, with a 4KB predictor achieving more than 95% accuracy for SPEC INT, and larger implementations achieving greater than 99% accuracy. The information provided from reconvergence prediction can increase the effectiveness of a range of previously proposed performance optimizations, including speculative multithreading, control independence, and squash reuse. This paper also demonstrates a new technique that takes advantage of the dynamic reconvergence prediction information in order to predict a wrong path excursion ahead of branch resolution. On average, 34% of wrong path fetches are eliminated.

title: Helper threads via virtual multithreading
abstract: Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent

title: Implementing a scalable ASC processor
abstract: Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism.

title: A dependency chain clustered micro architecture
abstract: In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved by heavily clustering the pipeline from decode to commit stage without the need for any direct bypass between clusters. This is made possible by assuming support for executing compiler-constructed traces. One trace is executed at a time by executing its coarse-grained dependency chains (DCs) in different in-order clusters. Since the DCs of a trace are mutually data independent of each other they can be executed in different clusters without any direct communication between them. To execute DCs in narrower clusters without compromising ILP, a compiler algorithm that splits large DCs by duplicating instructions is proposed. Through cycle accurate simulations we show that a DC processor with one 3-wide, one 2-wide and one 1-wide in-order pipeline, could achieve performance equivalent to a 6-wide in-order superscalar processor. Since a clustered DC microarchitecture is complexity efficient, it is amenable to higher clock frequencies and will also be easier to design and validate than a 6-wide monolithic design.

title: Intel nehalem processor core made FPGA synthesizable
abstract: We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.