Longest-path selection for delay test under process variation
Under manufacturing process variation, a path through a net is called longest if there exists a process condition under which the path has the maximum delay among all paths through the net. There are often multiple longest paths for each net, due to different process conditions. In addition, a local defect, such as resistive open or a resistive bridge, increases the delay of the affected net. To detect delay faults due to local defects and process variation, it is necessary to test all longest paths through each net. Previous approaches to this problem were inefficient because of the large number of paths that are not longest. This paper presents an efficient method to generate the set of longest paths for delay test under process variation. To capture both structural and process correlation between path delays, we use linear delay functions to express path delays under process variation. A novel technique is proposed to prune paths that are not longest, resulting in a significant reduction in the number of paths. In experiments on International Symposium on Circuits and Systems (ISCAS) circuits, our number of longest paths is 1-6% of the previous best approach, with 300/spl times/ less running time.

title: Process variation dimension reduction based on SVD.
abstract: We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and timing analysis under process variation can be performed efficiently. Our algorithm reduces the number of process variation variables while preserving the delay function with respect to process variation. Compared with the principal component analysis (PCA) method, our algorithm requires less computation time and guarantees the reduced process variation variables are independent. Experimental results on ISCAS85 circuits show that the algorithm works well. 1 INTROCUTION In modern multi-layer VLSI circuits, the dimension of the process variation is large. For example, in a k-metal technology, there are 2k variables for metal width and thickness, k variables for inter-layer dielectric (ILD) thickness, a gate length variable, and some other variables. With such a large number of process variation variables, timing analysis under process variation is very time consuming, and may not find the worst-case process corner [1][2]. In this paper, we propose the novel concept of variation dimension reduction. The idea is originated from the following observation. For different nets, the underlying process variation variables are the same. Therefore, the delays of the nets are correlated. We model the delay from an input pin of a cell to an input pin of a downstream cell, also known as the buffer-to-buffer delay, as a linear function of process variation variables: d = dnominal(1 + a1x1 + a2x2 + ... + anxn), where x1, x2, ..., xn are process variation variables, a1, a2, ..., an are their corresponding coefficients, and dnominal is the nominal delay. For different nets, the coefficients are different, but the process variation variables are the same. The assumption that the delay is linear with respect to each process variation variable is supported by SPICE simulation of real circuits within reasonable ranges of the process variation . There are many forms of process variation [4][5]. In this paper, we only consider systematic process variation and assume the process variation variables among different nets are fully correlated. We assume the following variation ranges: metal thickness ±20%, metal width ±10%, ILD thickness ±40%, and gate length ±10%. To obtain the delay function with respect to process variation, we first extract interconnect parasitic from the layout and compute the nominal buffer-to-buffer delay for all nets. Then for each process variation variable, we modify the layout or the technology file by varying a specified amount (for example, +10% for metal1 thickness), and perform RC extraction and delay evaluation for the modified layout. The coefficient for this process variation variable is obtained by interpolating the two delays. Recently, the principal component analysis (PCA) method was used to reduce the dimension of process variation . It was shown to be effective for analyzing analog circuits under process variation. However, the PCA method is inefficient for digital circuits, because the PCA method constructs and solves a correlation matrix of size mn×mn, where n is the number of process variation variables and m is the number of nets or devices. For digital circuits, m is easily in hundreds or thousands. In this paper, we propose a new method based on singular value decomposition (SVD) . Our algorithm detects the linear dependence and reduces the number of process variation variables, while minimizing the average error of the delay. Note that although the PCA method also uses SVD, their matrix is size mn×mn while ours is size m×n. To make the reduced process variables linearly/statistically independent, which is desirable for fault simulation and timing analysis, we also propose a sub-matrix SVD method. In Section 2, the SVD method and sub-matrix SVD method for dimension reduction are given. In Section 3, we show the experimental results. It shows that if we simply pick the most important process variation variables and discard the rest, then the average error of net delay is twice as much as the average error produced by our algorithm. 2 ALGORITHM 2.1 Singular Value Decomposition (SVD) The SVD method is based on the following theorems . Theorem 1 If A is an m×n matrix, then there exist orthogonal m×m matrix U=[u1,...,um] and n×n matrix V=[v1,...,vn], such that U·A·V=diag(σ1,...,σp), which is an m×n matrix, p=min{m,n}, and σ1 ≥ σ2 ≥...≥ σp ≥ 0. The σi’s are the singular values of A, and vectors ui and vi are the ith left and right singular vector, respectively. The process to find U and V is called SVD. It can be done by the Golub-Reinsch algorithm of time complexity O(mn+mn+n)  (pp. 254). To compute U(:,1:n) =[u1,...,un], which is an m×n (m>n) matrix, the time complexity is O(mn+n) . Theorem 2 Let the SVD of m×n matrix A be defined in Theorem 1. If r < rank(A) and let ∑ = = r i T i i i v u A 1 * σ , then 1 2 * 2 ) ( min + = = − = − r r B rank A A B A σ . In other words, A is the best 2-norm approximation of A among all rank r matrices.  Application to Dimension Reduction We are given the delay of m nets represented as Ax, where A is an m×n matrix, n is the number of process variation variables, x=[x1,...,xn] is the vector of process variation variables, and xi’s are independent of each other. From Theorem 2, A=U(:,1:r)·S·V(:,1:r), where S=diag(σ1,...,σr), U(:,1:r)=[u1,...,ur], and V(:,1:r) =[v1,...,vr]. Therefore, Ax≈Ax=U(:,1:r)·S·V(:,1:r)x=Bz, where B=U(:,1:r)·S is an m×r matrix and z=V(:,1:r)x is an r×1 vector. Since the dimension of B is much less than the dimension of A, we use Bz to approximate Ax. If we just want to reduce the number of process variation variables, then Bz is the resulting delay function, and z is the vector of new process variation variables. However, we often have an additional requirement from circuit simulation that the new process variation variables z1, ..., zr must be independent. For example, if z1=x1−x2+x3 and z2=x1+x2−x3, then z1 and z2 are not independent although the number of variables is reduced from 3 to 2. 2.3 Sub-Matrix SVD (SMSVD) We propose a sub-matrix SVD method (SMSVD) to ensure the independence between zi’s. The basic idea is to partition columns of A into r sub-matrices, and then use SVD on each sub-matrix. The following is the algorithm: 1) Partition A into sub-matrices A1, A2, ..., Ar, where A=[A1, A2,..., Ar]. Ai is an m×qi matrix, i=1,..., r. 2) For i=1,..., r, compute the approximation matrix Ai of Ai through SVD in which the approximation rank is 1. Define SVD of Ai as Ui·Ai·Vi=diag(σi1,...,σip), then Ai=Ui(:,1)·σi1·Vi(:,1) and ║Ai−Ai║2=σi2. 3) Construct B=[U1(:,1)σ11, U2(:,1)σ21, ..., Ur(:,1)σr1],

title: Longest-path selection for delay test under process variation
abstract: Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay among all paths through that fault site. There are often multiple longest paths for each fault site in the circuit, due to different process conditions. To detect the smallest delay fault, it is necessary to test all longest paths through the fault site. However, previous methods are either inefficient or their results include too many paths that are not longest.This paper presents an efficient method to generate the longest path set for delay test under process variation. To capture both structural and systematic process correlation, we use linear delay functions to express path delays under process variation. A novel path-pruning technique is proposed to discard paths that are not longest, resulting in a significantly reduction in the number of paths compared with the previous best method. The new method can be applied to any process variation as long as its impact on delay is linear.

title: Probabilistic Congestion Prediction with Partial Blockages
abstract: Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing congestion. Using a probabilistic technique instead of a global router has the advantage of speed and easy updating. Previously proposed probabilistic models (Lou, et al., 2001) (Westra et al., 2004) do not account for wiring that may already be fixed in the design, e.g., due to macro blocks or power rails. These "partial wiring blockages" certainly influence the global router, so they should also influence a probabilistic routing prediction algorithm. This work proposes a probabilistic congestion prediction metric that extends the work of (Westra et al., 2004) to model partial wiring blockages. The authors also show a new fast algorithm to efficiently generate the congestion map and demonstrate the effectiveness of our methods on real routing problems

title: Making fast buffer insertion even faster via approximation techniques

title: Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
abstract: As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer insertion algorithms (e.g., [7, 6, 15]) are based on van Ginneken's dynamic programming paradigm [14]. However, van Ginneken's original algorithm does not control buffering resources and tends to over-buffering, thereby wasting area and power. It has been a major open problem whether it is possible to optimize slack and at the same time minimize the buffer usage.This paper settles this open problem by showing that for arbitrary integer cost functions, the problem is NP-complete. We also extend the pre-buffer slack technique [12] to minimize the buffer cost. This technique can significantly reduce the running time and memory in buffer cost minimization problem. The experimental results show that our algorithm can speed up the running time up to 17 times and reduces the memory to 1/30 of traditional best know algorithm. Finally, we show how to efficiently deal with multiway merge in buffer insertion.

title: Reducing cache conflicts by partitioning and privatizing shared arrays
abstract: Parallelizing compilers for shared-memory multiprocessors typically generate fork-join programs in which multiple threads may access different sections of shared arrays. Each thread tends to access discontiguous addresses due to the gap between sections which belong to different arrays. Such interarray discontiguity often causes cache-set conflicts even when the private cache is large enough to hold the working set. A compiler technique, called array partition and privatization (or APP), is proposed to correct this problem. The APP technique partitions a shared array into sections, one for each computing thread, and then maps each section to the private stack of the corresponding thread. Interarray discontiguity is thus removed and the cache performance improved. This paper presents a compiler algorithm for APP and preliminary experimental results based on four benchmark programs running on an SGI Origin 2000 multiprocessor.

title: QMBF: a QoS-aware multicast routing protocol
abstract: Many multicast applications, such as video-on-demand and tele-education, desire quality of service (QoS) support from the underlying network. Recently, many QoS-based multicast protocols have been proposed to meet this requirement. However, few of them can achieve high success ratios while maintaining good scalability. In this paper, we propose a new QoS-aware multicast protocol based on a bounded flooding technique (QMBF). In this protocol, every network node maintains the knowledge of a local network cell (LNC) topology as well as QoS state information (collected from the bounded flooding messages). QMBF utilizes this knowledge to increase the probability and accuracy of finding a feasible branch which connects a new member to an existing multicast tree. The protocol exploits two approaches to find feasible branches: repeatedly computing partial feasible branches using the LNC information and searching multiple paths. The design of QMBF allows it to operate on top of any unicast routing protocol or cooperate with a QoS-based unicast routing protocol. Results obtained using NS-2 simulator demonstrate high success ratio for locating feasible branches for multicast paths.

title: An Object-Oriented Approach Using a Top-Down and Bottom-Up Process for Manipulative Action Recognition
abstract: Different from many gesture-based human-robot interaction applications, which focused on the recognition of the interactional or the pointing gestures, this paper proposes a vision-based method for manipulative gesture recognition aiming to achieve natural, proactive, and non-intrusive interaction between humans and robots. The main contributions of the paper are an object-centered scheme for the segmentation and characterization of hand trajectory information, the use of particle filtering methods for an action primitive spotting, and the tight coupling of bottom-up and top-down processing that realizes a task-driven attention filter for low-level recognition steps. In contrast to purely trajectory based techniques, the presented approach is called object-oriented w.r.t. two different aspects: it is object-centered in terms of trajectory features that are defined relative to an object, and it uses object-specific models for action primitives. The system has a two-layer structure recognizing both the HMM-modeled manipulative primitives and the underlying task characterized by the manipulative primitive sequence. The proposed top-down and bottom-up mechanism between the two layers decreases the image processing load and improves the recognition rate.

title: Automatic tiling of iterative stencil loops
abstract: Iterative stencil loops are used in scientific programs to implement relaxation methods for numerical simulation and signal processing. Such loops iteratively modify the same array elements over different time steps, which presents opportunities for the compiler to improve the temporal data locality through loop tiling. This article presents a compiler framework for automatic tiling of iterative stencil loops, with the objective of improving the cache performance. The article first presents a technique which allows loop tiling to satisfy data dependences in spite of the difficulty created by imperfectly nested inner loops. It does so by skewing the inner loops over the time steps and by applying a uniform skew factor to all loops at the same nesting level. Based on a memory cost analysis, the article shows that the skew factor must be minimized at every loop level in order to minimize cache misses. A graph-theoretical algorithm, which takes polynomial time, is presented to determine the minimum skew factor. Furthermore, the memory-cost analysis derives the tile size which minimizes capacity misses. Given the tile size, an efficient and general <i>array-padding</i> scheme is applied to remove conflict misses. Experiments were conducted on 16 test programs and preliminary results showed an average speedup of 1.58 and a maximum speedup of 5.06 across those test programs.

title: WICCAP: from semi-structured data to structured data
abstract: Web data extraction is a technique for extracting and integrating data from Web based semistructured data. Wrappers function like the kernel of Web data extraction systems providing information mediator between users and a large number of heterogeneous data sources. Typically, they process semistructured documents generated from structured databases based on rules that are usually hidden to users. Much research has been done to use various methods to represent the knowledge of hidden rules and exploit techniques such as grammar induction, inductive logic programming, etc., to discover these rules that can be used by wrappers to extract data. An important property of semistructured data is its hierarchical structure. Intuitively, we can devise a method that can use this structure information to generate wrappers. We describe a Web data extraction system - WICCAP and its internal Web Data Extraction Language (WDEL) that provides unified view of Web data resources and extracted data. We describe some rule generation features of WICCAP and provide detailed description of the internal language and its implementation. We have conducted experiments to show the ease on generating wrappers with this approach.