DAxML: A Program for Distributed Computation of Phylogenetic Trees Based on Load Managed CORBA
High performance computing in bioinformatics has led to important progress in the field of genome analysis. Due to the huge amount of data and the complexity of the underlying algorithms many problems can only be solved by using supercomputers. In this paper we present DAxML, a program for the distributed computation of evolutionary trees. In contrast to prior approaches DAxML runs on a cluster of workstations instead of an expensive supercomputer. For this purpose we transformed PAxML, a fast parallel phylogeny program incorporating novel algorithmic optimizations, into a distributed application. DAxML uses modern object-oriented middleware instead of message-passing communication in order to reduce the development and maintenance costs. Our goal is to provide DAxML to a broad range of users, in particular those who do not have supercomputers at their disposal. We ensure high performance and scalability by applying a high-level load management service called LMC (Load Managed CORBA). LMC provides transparent system level load management by integrating the load management functionality directly into the ORB. In this paper we demonstrate the simplicity of integrating LMC into a real-world application and how it enhances the performance and scalability of DAxML.

title: RAxML-OMP: An Efficient Program for Phylogenetic Inference on SMPs
abstract: Inference of phylogenetic trees comprising hundreds or even thousands of organisms based on the Maximum Likelihood (ML) method is computationally extremely intensive. In order to accelerate computations we implemented RAxML-OMP, an efficient OpenMP-parallelization for Symmetric Multi-Processing machines (SMPs) based on the sequential program RAxML-V (Randomized Axelerated Maximum Likelihood). RAxML-V is a program for inference of evolutionary trees based upon the ML method and incorporates several advanced search algorithms like fast hill-climbing and simulated annealing. We assess performance of RAxML-OMP on the widely used Intel Xeon, Intel Itanium, and AMD Opteron architectures. RAxML-OMP scales particularly well on the AMD Opteron architecture and achieves even super-linear speedups for large datasets (with a length ≥ 5.000 base pairs) due to improved cache-efficiency and data locality. RAxML-OMP is freely available as open source code.

title: Interoperability Support in Distributed On-Line Monitoring Systems
abstract: Sophisticated on-line tools play an important role in the software life-cycle, by decreasing software development and maintenance effort without sacrificing software quality. Using multiple tools simultaneously would be very beneficial; however, with most contemporary tools, this is impossible since they are often based on incompatible methods of data acquisition and control. This is due largely to their relative independence, and could be overcome by an appropriately designed common on-line monitoring system. We consider three possible platforms that might be potentially capable of addressing this issue, and discuss the relative merits and demerits of each.

title: Efficiently building on-line tools for distributed heterogeneous environments
abstract: Software development is getting more and more complex, especially within distributed middleware-based environments. A major drawback during the overall software development process is the lack of on-line tools, i.e. tools applied as soon as there is a running prototype of an application. The MIMO MIddleware MOnitor provides a solution to this problem by implementing a framework for an efficient development of on-line tools. 
 
This paper presents a methodology for developing on-line tools with MIMO. As an example scenario, we choose a distributed medical image reconstruction application, which represents a test case with high performance requirements. Our distributed, CORBA-based application is instrumented for being observed with MIMO and related tools. Additionally, load balancing mechanisms are integrated for further performance improvements. 
 
As a result, we obtain an integrated tool environment for observing and steering the image reconstruction application. By using our rapid tool development process, the integration of on-line tools shows to be very convenient and enables an efficient tool deployment.

title: An Open Monitoring System for Parallel and Distributed Programs
abstract: The on-line monitoring interface specification OMIS provides means for developing more powerful tool environments for parallel and distributed systems. It specifies the interaction between any tool and a monitoring system which is responsible for observing and manipulating the programs' execution. By having this well defined interface it is now possible to concurrently use several tools of possibly different developers with the same program run. The research group at LRR-TUM currently designs an OMIS compliant monitoring system for PVM running on workstation clusters. Tool developers can use this implementation to attach their own on-line tools to the system.

title: Tracing the MPI-IO Calls' Disk Accesses
abstract: With parallel file I/O we are faced with the situation that we do not have appropriate tools to get an insight into the I/O server behavior depending on the I/O calls in the corresponding parallel MPI program. We present an approach that allows us to also get event traces from the I/O server environment and to merge them with the client trace. Corresponding events will be matched and visualized. We integrate this functionality into the parallel file system PVFS2 and the MPICH2 tool Jumpshot.

title: Power-delay product minimization in high-performance 64-bit carry-select adders
abstract: This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.

title: Editorial for the ISC’10 Scientific Sessions Proceedings
abstract: The International Supercomputing Conference started in 1986 as the “Supercomputer Seminar” organized by Prof. Hans Meuer, then director of the computer center and professor for computer science at the Universitat Mannheim (Germany). Since these early days the annual conference became a major international event in the HPC community. As the conference grew bigger, it moved from Mannheim over Heidelberg and Dresden to Hamburg. In 2010 the conference will celebrate its 25th birthday! About 2,000 attendees and more than 140 exhibitors from over 45 countries are expected to attend, turning ISC’10 into a powerful and memorable event. Over the years we decided to strengthen the scientific part of the conference and present selected talks on relevant research results in the field of HPC. These scientific sessions started in 2007 as a separate day preceding the conference. Slides and accompanying papers were made available via the conference web site. Now, the scientific sessions evolved into an integral part of the conference, being scheduled in the afternoon of the first day. The call for participation was issued in winter 2009 inviting researchers and developers to submit latest results of their work as full research papers to the program committee of the scientific sessions. Altogether we received 25 submissions from authors all over the world. In a peer-reviewing process with an international committee we selected the best 13 papers for publication in this journal and for presentation during the scientific sessions of the conference.

title: A flat, timing-driven design system for a high-performance CMOS processor chipset
abstract: We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server-Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We show that the density in terms of transistors per mm/sup 2/ is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort.