Topic 2: Performance Evaluation
Besides excellent performance results for quite some applications for large scale systems, measurements very often reveal performance limitations for parallel programs. They result either from the architecture of the parallel systems (memory organization, communication hardware), from system software (parallel compilers, message passing implementations, operating systems), or sometimes even from implementation aspects of the given application. However, one of the main observations still is that on a single PE, many, if not most applications which are relevant to the technical field do not benefit adequately from clock rate improvement. The reason for this is memory accesses: most data read and write operations have to access memory which is relatively slow compared to processor speed. With several levels of caches we now have architectures which, in principal, provide plenty of options to keep the data as close as possible to the processor. Nevertheless, the resulting chip architectures are quite complex, and the compiler development progresses more slowly than anticipated.

title: DAxML: A Program for Distributed Computation of Phylogenetic Trees Based on Load Managed CORBA
abstract: High performance computing in bioinformatics has led to important progress in the field of genome analysis. Due to the huge amount of data and the complexity of the underlying algorithms many problems can only be solved by using supercomputers. In this paper we present DAxML, a program for the distributed computation of evolutionary trees. In contrast to prior approaches DAxML runs on a cluster of workstations instead of an expensive supercomputer. For this purpose we transformed PAxML, a fast parallel phylogeny program incorporating novel algorithmic optimizations, into a distributed application. DAxML uses modern object-oriented middleware instead of message-passing communication in order to reduce the development and maintenance costs. Our goal is to provide DAxML to a broad range of users, in particular those who do not have supercomputers at their disposal. We ensure high performance and scalability by applying a high-level load management service called LMC (Load Managed CORBA). LMC provides transparent system level load management by integrating the load management functionality directly into the ORB. In this paper we demonstrate the simplicity of integrating LMC into a real-world application and how it enhances the performance and scalability of DAxML.

title: Developing Applications for Multicomputer Systems on Workstation Clusters
abstract: Much computational power on state-of-the-art multicomputers like the Paragon is wasted with porting applications. Using networks of workstations is an attempt to withdraw this workload from multicomputer systems. Therefore an environment is needed which provides the programming interface of multicomputers on coupled workstations. The paper describes the design and implementation of the NXLib environment which allows to use Ethernet coupled workstations as a development platform for applications targeted for Intel Paragon systems.

title: NXLib - A Parallel Programming Environment for Workstation Clusters
abstract: Workstations provide an attractive platform to develop software. This paper describes the NXLib environment which enables users to use this platform to develop parallel applications. The source code compatibility of NXLib applications with Intel's Paragon multicomputer system easily allows to migrate these applications to a supercomputer. The performance which can be achieved with either platform is compared using two applications. In addition performance results of NXLib communication calls and comparisons with other widespread messagepassing libraries for workstation clusters are presented.

title: Performance Assessment of Parallel Spectral Analysis: Towards a Practical Performance Model for Parallel Medical Applications
abstract: To determine the need for a parallel computer on campus a committee of the Graduate Program in Computer Science surveyed selected Dartmouth College faculty and students in December and January We hope that the information in this report can be used by many groups on campus including the Computer Science graduate program and DAGS summer institute Kiewit s NH Supercomputer Initiative and by numerous researchers hoping to collaborate with people in other disciplines We found signi cant interest in parallel supercomputing on campus An on campus par allel supercomputing facility would not only support numerous courses and research projects but would provide a locus for intellectual activity in parallel computing encouraging interdisci plinary collaboration We believe that this report is a rst step in that direction All of the committee members can be reached by email at fullname Dartmouth edu where dots replace spaces in the name e g David Kotz Dartmouth edu Dartmouth Parallel Computer Needs January

title: Efficiently building on-line tools for distributed heterogeneous environments
abstract: Software development is getting more and more complex, especially within distributed middleware-based environments. A major drawback during the overall software development process is the lack of on-line tools, i.e. tools applied as soon as there is a running prototype of an application. The MIMO MIddleware MOnitor provides a solution to this problem by implementing a framework for an efficient development of on-line tools. 
 
This paper presents a methodology for developing on-line tools with MIMO. As an example scenario, we choose a distributed medical image reconstruction application, which represents a test case with high performance requirements. Our distributed, CORBA-based application is instrumented for being observed with MIMO and related tools. Additionally, load balancing mechanisms are integrated for further performance improvements. 
 
As a result, we obtain an integrated tool environment for observing and steering the image reconstruction application. By using our rapid tool development process, the integration of on-line tools shows to be very convenient and enables an efficient tool deployment.

title: Editorial for the ISC’10 Scientific Sessions Proceedings
abstract: The International Supercomputing Conference started in 1986 as the “Supercomputer Seminar” organized by Prof. Hans Meuer, then director of the computer center and professor for computer science at the Universitat Mannheim (Germany). Since these early days the annual conference became a major international event in the HPC community. As the conference grew bigger, it moved from Mannheim over Heidelberg and Dresden to Hamburg. In 2010 the conference will celebrate its 25th birthday! About 2,000 attendees and more than 140 exhibitors from over 45 countries are expected to attend, turning ISC’10 into a powerful and memorable event. Over the years we decided to strengthen the scientific part of the conference and present selected talks on relevant research results in the field of HPC. These scientific sessions started in 2007 as a separate day preceding the conference. Slides and accompanying papers were made available via the conference web site. Now, the scientific sessions evolved into an integral part of the conference, being scheduled in the afternoon of the first day. The call for participation was issued in winter 2009 inviting researchers and developers to submit latest results of their work as full research papers to the program committee of the scientific sessions. Altogether we received 25 submissions from authors all over the world. In a peer-reviewing process with an international committee we selected the best 13 papers for publication in this journal and for presentation during the scientific sessions of the conference.

title: Standard-cell-based design methodology for high-performance support chips
abstract: We describe the methodology used for the design of a set of CMOS support chips used in the IBM S/390® Parallel Enterprise Server Generations 3 and 4. The logic design is based on functional units, and the majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. Custom library elements are used wherever needed for performance reasons. Using this approach, a density has been achieved that is comparable to those of contemporary custom designs, combined with very attractive turnaround times.

title: Power-delay product minimization in high-performance 64-bit carry-select adders
abstract: This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.

title: Analyzing Metadata Performance in Distributed File Systems
abstract: The performance of metadata processing in large distributed file systems currently presents larger challenges than scaling of data throughput. The paper presents a novel, distributed benchmark called DMetabench for measuring the performance of metadata operations (e.g. file creation). DMetabench runs in environments with potentially thousands of nodes and allows an assessment of the scalability of metadata operations. Additionally, precise run-time performance data is preserved which allows for a better understanding of performance artifacts. Validation results from production file systems at the Leibniz Supercomputing Centre (LRZ) are provided and discussed. Possible applications of knowledge about metadata performance scaling include the choice of an optimal parallelization strategy for metadata-itensive workload in a specific runtime environment.

title: A flat, timing-driven design system for a high-performance CMOS processor chipset
abstract: We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server-Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We show that the density in terms of transistors per mm/sup 2/ is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort.