Early EDA Innovations in Europe driven by Lynn Conway s Lambda Notation
Year: 2012

This paper summarizes the history of introducing the Mead Conway VLSI design revolution in Europe. Although the academic scene in Europe was watching the DARPA supported break through in the U.S. all national governments declined support by pointing toward the missing funding in all neighbor countries a classical deadlock. This paper reports how later the E.I.S. project completely removed this Europe wide deadlock by stimulating national multi university programs and spearheading the EURCHIP action still running to day, supported by the EU commission. The paper details the impact of these programs on various areas in structured VLSI design and computer structures. Working at Karlsruhe on hardware description languages  and microprogramming  and teaching digital system design and computer architecture (from 1969 to 1977) I was highly impressed by the colleagues from semiconductor technology with their expensive equipment. I did not expect, that I ever would design the layout of a microchip. Popularized by Bob Rosin's article microprogramming looked interesting at first glance  But I became more and more sceptic: it's also a method to keep the masses of CS people away from the technology scene. Exponentiating the von Neumann syndrome [4] based on nesting several von Neumann machines turned out not to be a desirable VLSI system perspective, so that the German computer society dissolved its special interest group on microprogramming. Going 1977 to Kaiserslautern I started a chair on EDA and computer structures. Meeting Carver Mead (Professor at Caltech) and Lynn Conway (head, VLSI Lab at Xerox PARC) during a trip to the Design Automation Conference at San Diego in 1979 I learned fascinating details about their VLSI design methodology efforts and received a copy of Lynn Conway's notes from her visiting professorship at MIT and prepublication color copies of the first 4 chapters of their book [6] Back home to Kaiserslautern I started in summer semester 1979 the first regularly scheduled Mead Conway style university course with exercises: the first one "on the entire continent" (Asia and Europe except UK) My students became tremendously excited and seized the opportunity of learning by doing. My article about this rapidly spread the news of disruptive developments from the U.S. [7, 8] I went on to lobby for innovative curricula and protoyping infrastructures as known from MPC79 or MOSIS. At the annual "Schlosstag" reception at Schloss Birlinghoven on October 1 in 1981 Prof. Dr. Norbert Szypersky celebrated his debut as the new CEO of the GMD. In front of the buffet he had a long talk with me and the queue of guests waiting for shake hands with the new CEO was growing longer and longer. Just back home as visiting professor at UC Berkeley I was a legendary animal to him, since he just started founding the ,International Computer Science Institute (ICSI)" at Berkeley. VLSI became a very important matter of the boss and Dr. Woelcken, head of Prof. Szypersky's staff, was put into charge at very high priority. Soon a 3 day tutorial (more than 30 professors ,back to the school bench" has been organized with me as the only speaker coming with boxes full of transparencies (PowerPoint did not yet exist) Because of the strong demand a second run has been organized a few weeks later. During the evening social activities a pressure group has been formed, since ,the industry" combatted us. ,Lobbyism prevents a balanced industry policy and efficient research funding"  Such a pressure group has been urgently needed, also throughout Europe (except UK and Scandinavia) where for years the professors Carlos Lopez Barrio (Spain) Francois Anceau (France) Heetmann (The Netherlands) Roger Van Overstraeten and Hugo De Man (Belgium) Mariagiovanna Sami and Luigi Dadda (Italy) etc. could not convince their governments. This formed a classical deadlock by the argument, that all neighbor countries do not do anything. Let me illustrate our hostile environment. My first proposal to the BMFT (Ministry of Research and Technology) failed because of the industry lobby and the favorite reviewer of the responsible department, a semiconductor technology professor, who characterized Carver Mead as a charlatan. He claimed, that, instead of going to Coyote Hill Drive (where MPC79 had been organized) he went to Deer Creek Road (the fabrication site) to find out the real truth. For me this first attempt ended with an embarrassing first class throw out. The Europe wide deadlock finally has been broken by Germany via my successful second proposal. Promising a political change Helmut Kohl became Bundeskanzler in 1983. But for me the turning point has been the new Technology Minister Dr. Heinz Riesenhuber, almost a kind of old friend of mine. Another turning point has been, that another person became the head of his responsible BMFT department who finally signed a document providing for us a grant of 35 million Deutschmark for 3 years to run the German multi university project. Didn't he know, that he should have asked for permission by ,the industry" Or, did he sign Figure 1. Speed up factors obtained by von Neumann to Reconfigurable Computing (vN to RC) migration. with a wink In 1987 this ,E.I.S. Projekt"  has been extended by another 18 months with a second grant (E.I.S. stands for ,Entwurf Integrierter Schaltungen" The "E.I.S. Projekt" headed by me and massively supported by Dr. Klaus Woelcken from GMD was very productive, and became the incubator of the EUROCHIP service, also, since in 1988 Dr. Woelcken became an officer of the Commission of the European Union. In 1988, the CEC launched a call for tenders to select a consortium to serve European universities for several services including multi project chip fabrication. As a result, the EUROCHIP organization was set up including CMP from France, the German E.I.S project, the Inter University Center for Microelectronics (IMEC) in Belgium, NORCHIP from Scandinavia, and the Rutherford Appleton Laboratory (RAL) in the UK. Finally 417 academic institutions participated, training about 15,000 students per year; about 16,000 copies of 20 different CAD packages were distributed and about 200 multi project wafer batches have been fabricated, containing some 2700 circuits [11] EUROCHIP also supported activities in Latin America (IBERCHIP) and Eastern Europe (EUROEAST) Of course, bootstrapping the learning process in these countries has the positive side effect of encouraging the development of potential future markets for European industry. In 1995 EUROCHIP launched EUROPRACTICE, designed to cover a broad range of systems orientated technologies and its services targeted to academia and to all types of industrial users by including training, design packages and access to prototype manufacturing and packaging. During my stay as a visiting professor at UC Berkeley in 1981 I could learn lot, like experiencing ARPANET access to the MOSIS service housed in Marina del Rey. I collected valuable experience in using many tools providing direct support for ,Mead Conway design" like a design rule checker, a circuit extractor, the MOSSII switch level simulator, a silicon compiler, and the IC layout tools CAESAR and MAGIC. The availability of all these Mead &Conway based tools made UC Berkeley an incubator of the later EDA software industry, including Cadence, Mentor Graphics, Viewlogic and many others. Carlo Sequin, also my sponsor at UCB, consulted Lynn Conway and took me with him for a ride to PARC at several Wednesdays. Having me as a medium UCB and PARC also was at least partially an incubator of the E.I.S. CVT and CVS projects. Circuit extraction became mandatory for most IC design processes. EDA tools to generate and check layouts were massively simplified and speeded up by Lambda based methods. With this scalable design rule methodology we at Kaiserslautern implemented in the early 80ies a design rule check called PISA [13, 14] on our MoM architecture  by adapting image preprocessing methods for interpreting a Lambda grid based circuit design file as a pixel array. A 4 by 4 pixel scan window scanned this array pixel by pixel and line by line (a video scan) For each scan window position the 4 by 4 pixel design pattern is compared in parallel with several hundred rule violation reference patterns. Because of this parallelism only a single clock cycle is needed for each scan window position. Since first FPGAs appearing on the market in 1984 have been tiny, we designed our own PLA like chip called ,DPLA" (Dynamically Programmable Logic Array) manufactured via E.I.S. project Multi Project Chip organization. This extremely area efficient solution was possible by using sum of product Boolean expressions for all reference patterns, so that a we did not need the less area efficient FPGAs. Compared to a software only version on a Motorola 68020 we obtained a speed up factor of more than 15.000 (fifteenthousand) 20 years before similar factors have been reported from the FPGA scene  This massively outstanding competitive edge in vN to RC migration would have been impossible without Lynn Conway's scalable design rule methodology. During my time at UC Berkeley I learnt PLA design and the M C EDA infrastructures created and organized by Carlo Sequin and his people. PISA is also an early application of our Anti Machine paradigm (counterpart of the von Neumann machine by using data counters instead of a program counter [15, 16] Based on this methodology we also implemented multi level extractor supporting automatic test pattern generation efforts [17, 18]  The worldwide first VLSI CAD framework: for the acronyms and for their meanings see figure 3.  CVS Acronyms, mostly also used within Fig. 2. Immediately after my talks on KARL during a summer school at Schuola Reiss Romoli (L'Aquila, Italy) I have been asked to join the CVT proposal ,CAD for