Voltage Regulator Dc_Dc Converter Based On Filter for Low Power Analysis
Year: 2014

An active filter based on chip DC DC voltage converter for application to distributed on chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point of load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2 and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area.  Hybrid regulator, low dropout regulator, on chip voltage regulation, point of load voltage egulation.  The power supply voltage aggressively scales with each technology generation, making the delivery of a high quality supply voltage to noise sensitive circuit blocks highly challenging .The number of voltage domains within an integrated circuit is increasing to satisfy stringent power budgets. The increase in the number of voltage domains requires new techniques to generate these voltages close to the load circuitry while occupying a small area. The power savings is greater when the voltage regulators are close to the load devices (point of load voltage delivery) and size is therefore the primary issue for point of load voltage regulation. Classical power supplies occupy large on chip area and are therefore not appropriate for point of load power delivery. Several topologies are commonly used to generate on chip dc voltages. These DC DC voltage converters are generally used as on chip power supplies in high performance integrated circuits. Conventional DC DC converters can be grouped into three primary categories: switching, switched capacitor (SC) and linear DC DC converters Buck converters, which are step down switching DC DC converters, are popular because of their high power efficiency. A second order inductor capacitor (LC) passive filter is commonly used in a buck converter. The passive LC components require significant on chip area, therefore, the passive components have generally been implemented offchip. As a consequence of placing these components off chip, significant voltage drop and bounce are produced at the package level due to the parasitic resistance and inductance between the off chip components of the voltage converter and the integrated circuit. Additionally, the parasitic interconnect impedance between the discrete components of the voltage converter can produce significant power loss. Furthermore, with power supply scaling, analog and digital circuits are less tolerant to fluctuations in the supply voltage The parasitic impedance of the interconnect between the discrete components degrades the speed and accuracy of the load regulation, causing slow response times and changing output voltage levels. A more area efficient voltage converter structure is a lowdropout voltage regulator (LDO) These regulators are implemented on chip close to the load circuitry for fast and accurate load regulation. These regulators require a large output capacitance to achieve fast load regulation. This capacitor occupies significant on chip area and is therefore generally implemented off chip The off chip implementation of the output capacitor requires dedicated I/Os and produces higher parasitic losses. Alternatively, when the output capacitor is placed on chip, the output capacitor dominates the total LDO regulator area A high bias current of 6 mA is used in to deliver 100 mA current with a 600 pF output capacitor. This approach is not appropriate for low power applications and the output capacitor occupies a significant die area. Many techniques have been proposed to eliminate the need for the large off chip capacitor without sacrificing the stability and performance