nils-herrmann/clean_scirepeval huggingface dataset:
A Distributed Index Based Multi-Resolution Data Storage Architecture in Wireless Sensor Networks

We propose a distributed index based multi-resolution storage architecture (DIMSA) for data storage and retrieval at multiple levels of detail in wireless sensor networks. The proposed scheme could automatically retrieve subsets of the data in correspondence to the user defined level of detail to save energy. In addition, DIMSA deploys attribute allocation scheme to further reduce energy consumption in the condition that some attributes are included in many events. In this condition, traditional data-centric storage schemes consumes more energy because the values for these attributes have to be replicated and stored at different places in the network for each individual event. A distributed index scheme is also proposed to avoid query flooding and extra data transmission. Analysis and simulations are conducted to evaluate the performance of the proposed scheme. The results show that DIMSA outperforms the traditional data-centric storage scheme like GHT.
A Nonisolated ZVS Asymmetrical Buck Voltage Regulator Module With Direct Energy Transfer

This paper presents a new nonisolated asymmetrical buck voltage regulator module. A transformer is used to extend the extremely low duty cycle of a conventional buck converter. Turn-off losses can be significantly reduced due to the extension of duty cycle, and there are no turn-on losses owing to the zero-voltage turn-on condition. At the same time, the voltage stress over the synchronous rectifier MOSFETs is also reduced. Therefore, the reverse-recovery losses of the body diode can be reduced. Furthermore, the MOSFETs with lower voltage rating and lower RDS(on) can be used to reduce the conduction losses. In order to reduce the turn-off losses above the switching frequency of 1 MHz further, a new current-source driver is also proposed, which is suitable to this new topology. A 12-V input prototype with the switching frequency of 1 MHz was implemented. Simulation and experimental results verify the functionality and benefits of the proposed topology.
A Context-Aware Policy Model to Support Autonomic Networking

Autonomic networking requires that the services and resources offered by the network at any specific time adapt to evolving changes in user needs, business goals and environmental conditions. This paper describes a rich and extensible context-aware policy model as part of the FOCALE autonomic network architecture. This context-aware policy model is built explicitly to support context-awareness that in turn enables the control loops in FOCALE to be adaptive.
Combined imaging matching method of side scan sonar images with prior position knowledge

Side scan sonar (SSS) image matching plays an important role in underwater applications, such as combining images to form wide range relief images, underwater simultaneous location and mapping, and construction of images of underwater terrain and objects. Because there are differences between the imaging mechanisms of SSS images and optical images, current matching algorithms for optical images do not always work well for SSS images. This study proposes a combined image matching approach for SSS images. First, the images are preprocessed to remove some environmental effects. Second, feature points that are stable for affine transformations are extracted from the SSS matching images based on speeded-up robust features with prior position knowledge. Third, geometric correction is made by the random sample consensus. After that, a similarity calculation is performed. The proposed approach speeds up the matching process and improves its accuracy by combining feature points matching and similarity calculation. It reduces the mismatching rate and the computation requirement by estimating the location uncertainty with prior knowledge and reducing the searching regions for image matching. Experiments show that the matching algorithm takes less time and has greater reliability and accuracy than traditional algorithms.
A new R-tree node splitting algorithm using MBR partition policy

In this paper we introduced a new R-tree node splitting algorithm. As an indexing technique for multi-dimensional data, R-tree is widely used in geographical information systems, CAD systems and spatial databases. An R-tree consists of nodes which in turn consist of records. Each node in R-tree must contain limited number of records in order that it can be stored within one disk block, thus a node splitting algorithm is used while inserting a new record into a full node. A node splitting algorithm is one of the crucial factors of the query performance of an R-tree since bad splits would result in an inefficient R-tree structure. At first we gave an efficient, linear node splitting algorithm that could construct an R-tree fast, by partitioning the minimum bounding rectangle of the node according to the shape of the node's MBR and the shapes of the MBRs of the node's records. Then we found that this node splitting algorithm would generate uneven nodes sometimes, that is the node to be split might be split into two nodes with one of them containing less records than the minimum number of records required. We then developed an algorithm to balance those uneven splitting results to meet the demands of the R-tree definition. At Last we improved our node splitting algorithm by considering the siblings of the splitting node. The siblings of the splitting node were picked up during the phase of choosing node to insert record and were put together with the splitting node to generate a better result. We performed several experiments to compare our node splitting algorithms with some other node splitting algorithms on both synthetic and real world data. These experiments tested the tree-construction costs and the query performance of the resulting R-trees. The results showed that the tree-constructing cost of our algorithm was lower than others and although the balancing procedure degraded the performance, our algorithm outperformed other node splitting algorithms in queries of the resulting R-trees.
A TDC based ISFET readout for large-scale chemical sensing systems

This paper presents a novel ISFET based readout system by minimizing the analogue instrumentation. Quantization of sensed pH is realized by means of a novel ISFET pH-to-Time sensor integrated with a time to digital converter (TDC). By using this scheme, interference usually introduced in the analogue front end can be minimized, and time based signal processing can be used to simplify the sensor interface. This system is implemented in a typical 0.18um standard CMOS technology. It includes a 3×3 sensor array of pH-to-Time sensors, and a TDC dedicated to this sensing scheme. ISFET pixels are fabricated with chemical sensing area of 10μm × 10μm. The TDC is delay line based flash converter with resolution of 781.25ps, when a reference clock 160MHz is used for both sensors and TDC. The occupied silicon area is 0.036mm2, and the total power consumption of this time-to-digital converter including the delay-locked loop is equal to 230μW.
Effect of surface roughness on quasi-ballistic transport in nano-scale Ge and Si double-gate MOSFETs

Effect of surface roughness on quasi-ballistic transport in nano-scale Ge and Si double-gate (DG) MOSFETs are investigated using 2D full-band self-consistent ensemble Monte Carlo (MC) method based on solving quantum Boltzmann equation (QBE). Results show that the effect of the surface roughness on carrier quasi-ballistic transport in DG nMOSFETs is still significant even when the gate length scales down to 10 nm. Moreover, the influence of surface roughness can be suppressed by the non-local transport since the on-current of the Ge DG nMOSFETs decreasing less than that of Si DG nMOSFETs with increasing of surface roughness
A forensic analysis solution of the email network based on email contents

Forensics analyses of an email network were more based on the email communication structure, while the email content was seldom considered. In this paper, we propose a forensics analysis method for an email network based on the Latent Dirichlet Allocation topic model and the Centrality algorithm. The method takes into full consideration the email content and the email communication structure. In order to calculate the email communication correlation with the topic of the criminal case, we get the similarity of the email content based on the Latent Dirichlet Allocation model. Combined with the Centrality algorithm, we can obtain the mail accounts that have the greater influence on the email network. Experimental results show that this method can more effectively analyze an email network and find the specific email accounts.
Decentralized voltage optimization and coordinated method in smart distribution grid

In order to meet requirements of distributed generator (DG) integration with distribution system and real-time simulation, a novel voltage optimization algorithm which is used to solve the active power output of DG units in distributed environment is presented in this paper. Firstly, an automatic partitioning method based on hierarchical agglomerative clustering (HAC) is proposed to decompose the distribution network. Next, according to the decoupling model, the distributed sequential quadratic programming for distributed generation (DSQP-DG) algorithm is adopted to solve the optimal outputs of DG units in a parallel way through alternating of internal and external iterations. The IEEE 33-bus and PG&E 69-bus system with DG units are considered and evaluated. Compared with auxiliary problem principle (APP) algorithm, the proposed algorithm shows that the DSQP-DG algorithm has better performance in distributed parallel voltage optimization of distribution system.
Design of DBA Algorithm in EPON Uplike

Ethernet Passive Optical Network (EPON) has combined the advantages of Ethernet and Passive Optical Network (PON). High speed accessing at lower price has been realized in this way. In this paper, based on CBR (Constant Bit Rate), design issues of Dynamic Bandwidth Allocation (DBA) are studied and the improved DBA algorithm is proposed. Ensure effectively Quality of Service (QoS) of the entire EPON and fairness of bandwidth allocation, and meet the request of the current network with multi-service, multi-level priorities. Provide reference for the standard of multi-service QoS in EPON uplink bandwidth allocation.
A Method of Network Traffic Analysis Based on Multiple-Combination Model

The traditional stationary network traffic model (ARIMA) is incapable of describing non-stationary characteristics. In the process of predicting, the accuracy will weaken with the increase of step. As a non-stationary network traffic model, NN (neural network) could make up for the defect of stationary model, which can not describe the non-stationary qualities of the network traffic. However, the parameters choice of NN doesn’t have a specific theoretical foundation. According to the problems above, the paper proposes a method of multiple combinations. First, we compared the errors of ARIMA with those of Elman model, and then designed a multiple-combination model which applied to network traffic analysis. The result shows that the method is superior to a single model.
An interleaving and load sharing method for multiphase LLC converters

Interleaving frequency-controlled LLC resonant converters will encounter load-sharing problem due to the tolerance of the resonant components. In this paper, full-wave and half-wave switch-controlled capacitors (SCCs) are used in LLC stages to solve this problem. By using resonant capacitance as a control variable, the output current can be modulated even when all the LLC stages are synchronized at the same switching frequency. A design procedure is developed. A 600W prototype is built to verify the feasibility.
A DC bus voltage reduction technique for single-stage AC-DC forward converters

There are several key criteria to consider when designing single-stage ac-dc converters, such as primary-side dc bus voltage level, input current harmonics, and output power. Satisfying these criteria for higher power converters, such as a two-switch single-stage forward converter is challenging because of the wide line and load range that these converters operate with. A technique that can reduce the dc bus voltage and be used in higher power single-stage converters is proposed in this paper. The reduction in voltage allows for greater flexibility in the design of the converter. In this paper, a design procedure based on the use of steady-state characteristic curves is developed. The procedure can be used to select the values of key converter parameters, and is demonstrated with the design of an example converter. Experimental results obtained on a laboratory prototype are presented to confirm the concepts discussed in the paper.
A low-power 8-read 4-write register file design

This paper gives a study of leakage in 90nm logic CMOS technology, and by analyzing the power constitutions in multi-ported register files and the leakage in different nMOS transistors with different power supply, a low-swing strategy for bit lines is used in saving power. In this paper an 8 read / 4 write ports write-through register file is designed and it dissipates 10.04mW at 500MHz, which save 33.36% power in read operation and 24.8% energy in average. The leakage power on the bit lines also reduces 1.7% by using high threshold voltage transistors in low-swing scheme.
Accurate thermoplasmonics modelling of complex metallic nanostructures

In this paper, a numerical scheme is presented to accurately model thermoplasmonics for arbitrarily shaped nanostructures. The volume integral equation (VIE) is utilized to calculate the light absorption, then the temperature profile is obtained by the moment of method (MoM) solution of the steady-state thermal equation. The accuracy and capability of proposed scheme are demonstrated by numerical simulations including gold rods with hemi-spherical caps and a chain of 15 gold spheres.
Biomechanical evaluation of FDS (flexor digitorum superficialis), 1/2FDS, and palmar fascia in the correction of claw fingers and the clinical exploration of 5 cases with 1/2FDS as tendon stiffness

FDS (flexor digitorum superficialis), 1/2FDS, and palmar fascia are 3 surgical procedures commonly used to correct the deformities of claw fingers after ulnar nerve injury. FDS and palmar fascia traditionally are the more common procedures. The fomer requires the whole FDS, while the latter sometimes causes the recurrence of deformity because of its transfiguration. The of 1/2FDS spare the motor tendon and the recurernce rate is expected to be lower. A biomechanical study was performed to determine whether the biomechanical character of the three tissues is suit for surgery procedure; Another follow-up study was performed to determine the clinical outcome with the 1/2FDS loop tenodesis operation in treatment of patients with ulnar claw fingers.  Ten fresh symmetrical arms in adults were tested, whose palmar fascias and FDSs of each finger were cut down respectively. And then 5 of the 10 FDSs were split into two tails equally. All samples were tested by an Instron Universal Test Instrument (model AG-10TA; made in Japan), which would control the stress and strain exerted on the test sample automatically, and print out the data of each load, elongation, stress and strain, then the curve of stress compared with elongation. 5 patients presented 5 affected 5 hands with ulnar claw fingers, had the 1/2FDS loop tenodesis procedure from May 1990 to March 2010. Each hand was assessed before surgery and at follow-up evaluation by predetermined angle measurements, power grip, motion, mechanical function, and patients'satisfaction.  Biomechanical study showed that FDS and that in half could endure large amount of stress exerted on it with less elongation in size. The difference between half FDS with palmar fascia group was statistically significant (P&#60;0.05) in maximum stress and in maximum elongation in size. The maximum stress of half FDS was ten times larger than that of palmar fascia, while the maximum elongation in size of palmar fascia was two times bigger than that of half FDS. In the aspect of modulus of elasticity, there was no significant difference between the two groups of FDS integrated and that in half (P>0.05)f, but it was significant weaker in half FDS than palmar fascia(P&#60;0.05). After an average follow-up period of 34 months, Corrections of deformity with the 1/2FDS loop tenodesis procedure was satisfactory in all patients without recurrence. Power grip remained static in most cases. Motion and function of the fingers were satisfactory.  The 1/2FDS provided us a better procedure for tenodesis than palmar fascia by biomechanical testing. It avoids the disadvantage to sacrifice large amount of FDSs that would result in new disorders of hand.
Design and experimental verification of on-board charger for electric vehicle

In this paper, an on-board charger for electric vehicle, with two-stage power converter, is designed. Firstly, a single-phase Boost-APFC (Active Power Factor Correction) circuit controlled by a one-cycle controller is designed as the front state converter. Compared to the traditional APFC circuit, the One-cycle controller is constructed without considering the multiplier and AC line voltage sensing circuits, which is suitable for APFC system. Moreover, the one cycle controlled Boost-APFC converter has strong ability to reject the input voltage disturbance. After that, the second stage converter is an improved phase-shifted full-bridge ZVZCS (Zero Voltage Zero Current Switching) power converter, wherein the secondary side of the auxiliary circuit is consisted of two diodes and a clamp capacitor. The clamp capacitor is charged on transfer mode and discharged on free-wheeling mode. By achieving the ZCS on the lagging leg, the voltage stress on the secondary side of the rectifier bridge is reduced. Based on the effective duty cycle approach of small signal model on Buck converter, a new small signal model has been built, which provides a theoretical basis for closed-loop control circuit analysis and design. Finally, a 1Kw prototype, with 120V (AC) input and 200V output, is built. IR1153S and UCC3895 were used as the control chips, and the switching frequency is 22 kHz. Moreover, the prototype has been achieved a peak efficiency of 92% at a full load.
A Modifed Approach on MMSE MIMO Interference Cancellation Detection

In this paper, an novel MMSE MIMO detector is proposed with respect to MMSE MIMO channel estimation. We will show how a two-step MMSE MIMO estimator can be used to facilitate packet detection as well as to provide superior bit error rate performance. This proposed detector takes channel estimation errors into account by the statistical characteristics of MMSE MIMO channel estimation. When compared with existing soft-output MMSE MIMO detector, simulation results show that the proposed novel detector can remarkably reduce the residual error floor due to the channel estimation errors, while achieving significant performance gain at the cost of negligible increase of complexity. We will show how this approach significantly improves packet detection and how the overall solution approaches the performance of the classical MMSE estimator.
A spark-based parallel simulation approach for repairable system

Fault-tree analysis is a useful analytic tool for the reliability and safety of complex system. However, fault tree is not suitable for repairable system. In this paper, we will propose a new method called TTF (time to failure) and TTM (time to maintenance) to analyze repairable system. Nevertheless, Monte Carlo simulation may be time consuming. In order to reduce simulation time, a parallel algorithm based on Spark will be used in this paper. Spark-MapReduce is the latest parallel computation framework. In situations where the amount of data is prohibitively large, we will propose a parallel algorithm for repairable system analysis to quickly get the simulation result. In this article, we propose a parallel algorithm to speed up through the experiment, we prove that the parallel algorithm has a superior performance on large scale models, and under Spark-MapReduce framework, researchers can concentrate on algorithm itself. It has significant benefits on reliability or availability assessment issues because it can free researchers, who are non-computer professional researchers, from parallelization and computational frame.
A Computational Study of Dopant-Segregated Schottky Barrier MOSFETs

A dopant-segregated Schottky barrier MOSFET is simulated by Monte Carlo method in this paper. The feature that dopant-segregated structure can improve on-current is revealed. The influence of dopant-segregated structure parameters on device performance is investigated, and the guideline for device design optimization is that the dopant-segregated region should overlay the whole Schottky barrier region. Some carrier transport details are also demonstrated here. The maximal velocities at source and drain sides all decrease with the increase of dopant-segregated region length. The maximal velocity at source side shows saturation with the existence of dopant-segregated structure when drain voltage increases while the maximal velocity at drain side shows no saturation.
Analysis on mismatch loss caused by poor contact of BNC connector components

As a main coaxial cable connector, BNC connector, internal connections of which often take the form of a clamping structure, is widely used in communication industry. Due to different manufactures' different production processes and standards, inadequate compaction or out-of-tolerance component size in BNC connector production may cause poor contact, which may lead to mismatch loss of coaxial cable and influence the quality of signal transmission. Based on an actual BNC connector fault in satellite communication, this paper analyzes mismatch loss caused by poor contact of BNC connector components. Quantitative analysis is given on the cause and sizes of mismatch loss, which provides reference for coaxial cable production and troubleshooting.
A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication

This paper describes a novel system for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μm CMOS technology, occupying 1.4 mm2 silicon area, and requiring a 62.2 μA average current consumption.