nils-herrmann/clean_scirepeval huggingface dataset:
Error-propagation analysis and concealment strategy for MPEG-4 video bitstream with data partitioning

Data partitioning, one of the MPEG-4 video error resilience tools, enables better error robustness. However, it suffers from serious error propagation problem. In this paper, we use an experimental approach to model the error propagation with several commonly used error detection conditions. It is shown that errors detected in forward section of texture data may be propagated from motion data, while those in DCT coefficients mostly result from themselves. Furthermore, the motion marker is the major error source for several error conditions detected in motion part. According to these characteristics, motion marker assumption and backtracking-based concealment strategies are proposed to achieve more accurate error localization in bitstream domain.
Effective hardware-oriented technique for the rate control of JPEG2000 encoding

A great deal of computation for JPEG2000 encoding is a redundancy when the compression rate is high. That is because many coded bit-streams will be truncated after the rate control of JPEG2000. In this paper, an effective scheme for JPEG2000 rate control is proposed. Through this scheme, the computation complexity for JPEG2000 entropy coding, that is, EBCOT Tier-1, can be greatly reduced almost without paying any penalty on the image quality, especially at lower bit-rate. Moreover, the proposed method is considered to be suitable for the hardware implementation since the existing techniques for the rate control of JPEG2000 are all software-oriented. By the proposed rate control method, a dedicated hardware of JPEG2000 with high-speed processing and effective rate control ability can be achieved.
Error concealment algorithm using interested direction for JPEG 2000 image transmission

The newly defined JPEG 2000 delivers scalable and region-of-interest images with lower bit rates in Internet and wireless communications. However, any data loss in the JPEG 2000 bitstream affects the consequent bitplanes and even possibly destroys the whole picture. We propose a new algorithm to recover the damaged bitplane data according to the interested directional pattern in the subband. Simulation results show that the proposed concealment algorithm can achieve much smoother edges on the reconstructed image.
System analysis of VLSI architecture for motion-compensated temporal filtering

The motion-compensated temporal filtering (MCTF) is an innovative prediction scheme for video coding and has become the core technology of the coming video coding standard, MPEG-21 part 13 - scalable video coding (SVC). This paper provides the system analysis of MCTF for VLSI implementation, which includes computational complexity, external memory access, external storage size, and coding delay. The one-level MCTF is analyzed first, and a modified double current frames scheme is introduced to address the external memory access penalty that results from fractional-pel motion compensation (MC). Then the analysis is extended to multi-level MCTF, in which many important system issues will be explored. Finally, a real-life test case was given to compare the system requirements of many different MCTF schemes and the prediction scheme of H.264/AVC.
Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000

Embedded block coding with optimized truncation (EBCOT) is the entropy coding algorithm adopted by the new still image compression standard JPEG 2000. It is composed of a multi-pass fractional bit-plane context scanning along with an arithmetic coding procedure. GPP (general purpose processor) or DSP fails to accelerate this kind of bit-level operation, which is proven to occupy most of the computational time of the JPEG 2000 system. In this paper, two new accelerating schemes are proposed and applied to our prototyping design which turns out to be powerful enough to fulfill the demand of computational requirement of the most advanced digital still camera.
A Novel Architecture for Lempel-Ziv-Based Data Compression

In this paper, a novel VLSI architecture for Lempel-Ziv-based data compressioddecompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, Parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application.
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System

In a typical portable multimedia system, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 62%, 66%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With TSMC 0.18 mum 1P6M CMOS logic process, the proposed EC codec engine can encode or decode CIF 30 frame per second video data and achieve power saving of more than 109 mW. The EC codec engine itself consumes only 2 mW power.
Real-Time Depth Image based Rendering Hardware Accelerator for Advanced Three Dimensional Television System

3D TV will become a prominent technology in the next generation. In this paper, a depth image based rendering system is proposed from algorithm level to hardware architecture level. We propose a novel depth image based rendering algorithm with edge-dependent Gaussian filter and interpolation to improve the rendered stereo image quality. Based on our proposed algorithm, a fully-pipelined depth image based rendering hardware accelerator is proposed to support real-time rendering. The proposed hardware accelerator is optimized in three steps. First, we analyze the effect of fixed point operation and choose the optimal wordlength to keep the stereo image quality. Second, a three-parallel edge-dependent Gaussian filter architecture is proposed to solve the critical problem of memory bandwidth. Finally, we optimize the hardware cost by the proposed hardware architecture. Only 1/21 amounts of vertical PEs and 1/11 amounts of horizontal PEs is needed by the proposed folded edge-dependent Gaussian filter architecture. Furthermore, by the proposed check mode, the whole Z-buffer can be eliminated during 3D image warping. In additions, the on-chip SRAMs can be reduced to 66.7 percent compared with direct implementation by global and local disparity separation scheme. A prototype chip can achieve real-time requirement under the operating frequency of 80 MHz for 25 SDTV frames per second (fps) in left and right channel simultaneously. The simulation result also shows the hardware cost is quite small compared with the conventional rendering architecture
Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME

Motion-compensated temporal filtering (MCTF) is an innovative prediction scheme for video coding and the core technology of scalable extension of H.264/AVC. The first MCTF and ME hardware work is in this paper. The proposed hardware not only can support the various coding schemes in JSVM and H.264 but also can adapt itself to provide rate-distortion-computation scalability. With the frame-level searching range data reuse and frame-interleaved MB pipelining scheme, external memory bandwidth are reduced 33%, and 10 Kbits buffer are saved. The proposed MCTF/ME hardware is of 350K gate counts and 30 KB internal buffer, which can perform four-level MCTF or H.264 P-/B-frames at CIF format
A bit-level pipelined VLSI architecture for the running order algorithm

A bit-level pipelined VLSI architecture for the running order algorithm is presented. Based on the proposed modified algorithm, the deletion and the insertion is successfully pipelined in the bit-level operation. A block processing architecture of this modified algorithm is also constructed. The pipelined cycle of the proposed architecture is merely equivalent to the delay time of a pair of 1-bit comparisons that is independent on the window size and the signal resolution.
Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition

Image pipeline processing is crucial to generating high quality images in applications using complementary metaloxide-semiconductor (CMOS)/charge-coupled device sensors. The on-chip line buffer normally dominates the total area and power dissipation due to the needed filter window buffering. As image resolution and filter support increase, the area and power requirement increase accordingly. This paper presents a novel pyramid architecture to efficiently process a system that the image pipeline is between an image sensor and video coding engine. By utilizing the features of the pyramid structure and block-based video/image encoders, the proposed architecture is scalable from low to high image resolution and filter size. The input image is first partitioned into floors of tiles to reduce the frame line buffer. Two computing schemes, immediate result reuse and vertical snack scan, are utilized to reduce the overlapping redundant computations. A 90 nm CMOS chip design with 7 × 5 filter support for 3840 × 2160 quad full high definition video at 30 frames/s is designed to demonstrate the performance of power and area efficiency. Compared with traditional architectures with frame line buffers, the proposed design has shown that the power consumption is reduced by 25% to 108 mW from 145 mW. The chip area is reduced by 65% to 309 K from 888 K logic gates. The external memory bandwidth increases to 8286 Mbit/s from 5972 Mbit/s for YUV4:2:0, from 7963 Mbit/s for YUV4:2:2, and is reduced by 30% from 11944 Mbit/s for YUV4:4:4.
Real-time deblocking filter for MPEG-4 systems

This paper presents a deblocking filter architecture in the MPEG-4 standard. This architecture performs as a 1D nonlinear filter across the block boundary to efficiently suppress blocking artifacts. Two shift register banks are used in the design; their use greatly reduces the control complexity of data flow. Due to efficient scheduling, the size of storage and the total clock cycles are minimized. The maximum processing rate of this architecture mapped in 0.35 /spl mu/m technology is 30 Mpixels/sec, which can support NTSC resolution at 30 frames per second. The power consumption of the design is 46.6 mW while operating frequency is 81 MHz.
Tree-structure architecture and VLSI implementation for vector quantization algorithms

A tree-structure based architecture for vector quantization (VQ) is proposed and implemented by VLSI in this paper, The proposed folded-tree architecture is designed by 0.8 /spl mu/m CMOS VLSI technology. The die size is 4.65/spl times/5.21 mm/sup 2/ and estimated clock rate is about 34 MHz, which satisfies most real-time applications. Since it is basically a mean squared error computation circuit, various kinds of VQ algorithms can apply on the proposed architecture.<<ETX>>
Architecture design of high performance embedded compression for high definition video coding

External memory bandwidth is an important issue in system-on-chip (SoC) systems. Especially in high definition (HD) video coding, the bandwidth requirement of off-chip memory is critical in video processing. In recent researches, embedded compression shows high potential on off-chip memory bandwidth reduction. Works about embedded compression have been done for low power applications. However, there is no suitable efficient embedded compression with good rate-distortion performance for high throughput applications. In this paper, an algorithm and hardware architecture of high performance lossy embedded compression is proposed to ease the bus congestion problem while keeping the latency low. Using the proposed algorithm, not only the high throughput requirement of HD video encoder is met, but also the hardware cost is relatively low. From our simulation, about 70% memory bandwidth is reduced with only 0.1 dB PSNR degradation in 1080p HD video.
Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process

Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90 nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.
An efficient architecture for two-dimensional discrete wavelet transform

This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform-module, we employ the polyphase decomposition technique to the decimation filters of stage 1, and the coefficient folding technique to the decimation filters of stage 2. The RAM size is N/2/spl times/N/2. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are the near 100% hardware utilization, fast computation time, regular data flow, and low complexity control circuit, making this architecture suitable for next generation image compression systems.
Platform architecture design for MPEG-4 video coding

This paper presents a cost-effective platform architecture design for MPEG-4 video coding. A fast motion estimator architecture supporting predictive diamond search and spiral full search with halfway termination is implemented to make good compromise between compression performance and design cost. An efficient block-level scheduling for texture coding engine is employed to reduce the hardware cost. Both these key modules are integrated into an efficient platform in hardware/software co-design fashion. With high degree of optimization in both algorithm and architecture levels, a cost-efficient video encoder is implemented. It consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352/spl times/288) frames per second.
A novel hybrid motion estimator supporting diamond search and fast full search

We present a novel hardware architecture supporting diamond search and fast full search for block matching motion estimation. It can handle irregular data flow of these fast algorithms without pipeline bubbles, and reduce computation of duplicated search positions. The proposed architecture needs preprocessing with a small amount of computational power while performing fast full search and is suitable for the platform-based video coding system. While the diamond search mode can be applied for real-time requirements, we can choose the fast full search mode, which adapts the processing cycles to picture contents and preserves the same quality of full search block matching (FSBM), for applications of high picture quality or compression ratio. It needs only 9K gates and one additional memory of search range size and is more cost-effective than the conventional systolic array architecture.
VLSI Implementation of a Selective Median Filter

0001 0 0 1 0 0011 0111 1001 In this paper, the VLSI implementation of a selective median filter for the real-time applications is presented. T h e proposed design is based on a novel bit-level running algorithm with a modular and parallel in structure. A chip designed by the cell-based style is demonstrated to show the hardware realization. The performance of the proposed design is also presented.
A new design and implementation of 8/spl times/8 2-D DCT/IDCT

Among various transform techniques for image compression, the discrete cosine transform (DCT) is the most popular and effective one in practical applications because it gives an almost optimal performance and can be implemented at an acceptable cost. We describe a novel 8/spl times/8 2-D DCT/IDCT architecture based on the direct 2-D approach and the rotation technique. The computational complexity is reduced by taking advantage of the special attribute of complex numbers. Unlike other direct approach, the proposed architecture is regular, hence, it is suitable for VLSI implementation.
On-line empirical mode decomposition biomedical microprocessor for Hilbert Huang transform

On-chip implementation of Hilbert-Huang transform (HHT) has great impact to analyze the non-linear and non-stationary biomedical signals on wearable or implantable sensors for the real-time applications. Empirical mode decomposition (EMD) is the key component for the HHT processor. In tradition, EMD is usually performed after the collection of a large window of signals, and the long latency may not be feasible for the real-time applications. In this work, the architecture of on-line EMD for biomedical signals is proposed. The on-line interpolation method with data reuse as well as component and iteration loop decomposition is applied to obtain low latency and low hardware cost. The first chip of EMD processor is fabricated in UMC 90nm LL process and consumes 57.3µW.
A low power 2D DCT chip design using direct 2D algorithm

In this paper, a low power 8/spl times/8 2D DCT architecture based on direct 2D approach is proposed. The direct 2D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, a hybrid-architecture adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.
Design and implementation of low-power DCT chip for portable multimedia terminals

This paper describes the design and implementation of a low power 2D DCT chip for portable multimedia terminals. The chip architecture based on direct 2D approach reduces computational complexity and the power dissipation can be reduced accordingly. In the implementation of the direct 2D algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is adopted. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low-voltage two-port SRAM with sequential access. The resultant 2D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz. The measured chip speed is around 100 MHz.
Architecture of global motion compensation for MPEG-4 advanced simple profile

Global motion compensation (GMC) is an important coding tool in MPEG-4 advanced simple profile (ASP). In this paper, we propose an efficient GMC hardware architecture for MPEG-4 ASP@L5. Based on analysis of the affine model, the proposed memory arrangement and cascaded scheduling reduce the impact of irregular memory access and improve processing ability. It can process 30 fps at only 25 MHz. The implementation result shows that the total gate count is 19.3 K and internal memory size is 1.28 Kb. It is suitable to be integrated into MPEG-4 ASP encoders and decoders.
Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices

Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.
Reconfigurable discrete wavelet transform architecture for advanced multimedia systems

A novel reconfigurable discrete wavelet transform architecture is proposed to meet the diverse computing requirements of advanced multimedia systems. The proposed architecture mainly consists of a reconfigurable processing element array and a reconfigurable address generator, featuring a dynamically reconfigurable capability where the wavelet filter kernels and wavelet decomposition structures can be reconfigured at run-time with little overhead. The lifting-based reconfigurable processing element array possesses better computational efficiency than a convolution-based architecture, and a systematic design method is provided to generate the hardware configurations of different wavelet filter kernels for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by the TSMC 0.35 /spl mu/m 1P4M CMOS process, and, at 50 MHz, it can achieve at most 100 Mpixel/sec transform throughput, proving it to be a universal and extremely flexible computing engine for advanced multimedia systems.
Design and implementation of a bitstream parsing coprocessor for MPEG-4 video system-on-chip solution

In this paper, the hardware-oriented bitstream structure analysis and an efficient and flexible bitstream parsing processor are presented. The analysis of MPEG-4 video bitstream structure based on RISC model explores requirement and design constraint for bitstream-level processing. It shows that conventional RISC is not efficient enough for bitstream parsing. An efficient instruction set optimized for bitstream processing is designed and the hardware architecture can be reconfigured for various applications. Compared with 160 MOPS required by a RISC, the proposed architecture needs only about 27 MOPS to parse an MPEG-4 video bitstream at high bit-rate as about 40 Mbit/s, which is about 6 times speedup. The impact of the proposed architecture on video applications is to enhance and extend the processing for bit domain translation and related real time applications.