nils-herrmann/clean_scirepeval huggingface dataset:
An energy efficient protocol exploiting cache data for sensor networks

Minimizing energy consumption is important for prolonging the life of battery powered sensor nodes. A major portion of the power consumption is spent in communication with other nodes. If any communication fails, the message needs to be re-transmitted, resulting in added energy consumption. In this paper we suggest having a Failed Communication table, which keeps track of number of failed communications with each node in the group, while the nodes are updated with duplicate values for better resistance against loss of data. Consulting this table while selecting a path would help in detecting local interference and avoiding it while routing.
Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates

The high switching activity of wide fan-in dynamic domino gates introduces significant power overhead that poses a limitation on using these compact high-speed circuits. This paper presents a new limited-switching clock-delayed dynamic circuit technique, called SP-Domino, which achieves static-like switching behavior, while maintaining the low-area and high-performance characteristics of wide fan-in dynamic gates. SP-Domino is a single-phase footless domino that can be freely mixed with static gates and can provide inverting and non-inverting functions. Simulations on 8 and 16 inputs or gates show that SP-Domino reduces dynamic power by up to 63% compared to same-UNG and same-delay standard footless domino, and up to 56.9% compared to low-contention high-speed standard footless domino.
A low power VLSI prototype for low bit rate video applications

This paper presents a low power architecture for video application. The architecture is divided into two parts: motion estimation and motion compensation. In the motion estimation part, the modified three step search (TSS) algorithm is used to reduce the computational cost and the memory access. Also, the mesh is coded as a tree and a sequence of motion vectors to ensure low bit rate. In the motion compensation part, using a modified affine transform that reduces the complexity of the motion compensation reduces the computational cost. The performance of this architecture is also presented.
Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100nm technology. In this paper, we present a highly stable 2-port 7T SRAM cell for ultra-low power in 90nm technology. The dynamic read noise margin is improved by 7X over conventional dual port SRAM. Finally, a 4Kb bit-interleaved SRAM architecture is presented using proposed cell. Experimental results show that memory consumes 1.26pJ/bit at 0.22V supply voltage with 2MHz performance. The dynamic read noise margin is improved by 7X over conventional dual port SRAM. The successful write and read operations can be performed at supply voltage as low as 0.17V. Two level write decoder architecture is used to eliminate the pseudo read problem in unselected columns.
Defect clustering viewed through generalized Poisson distribution

It is shown that generalized double Poisson distributions provide a good basis for yield models when moderate spatial heterogeneity exists between chips of larger sizes, or when defects are almost randomly distributed. The model includes the average number and size of clusters as its parameters. On being tested with simulated as well as actual wafer particle maps, the model gave a significance level >0.95 in most of the cases. This model is simple and facilitates direct implementation of multilevel or hierarchical redundancy in regular VLSI/WSI designs. The strength of the proposed model lies in its simplicity and its ability to provide a physical explanation of the clustering process through its parameters. The model reflects the effects of the competition which can occur among defects in a cluster during wafer processing. Comparisons of yield predictions by various models for wafer maps with different spatial properties are reported.
High-performance asic architecture for hysteresis thresholding and component feature extraction in limited-resource applications

Hysteresis thresholding offers enhanced object detection but is time-consuming. Hence, it is often avoided in real-time, constrained streaming processors. We propose a high-performance solution for limited-resource applications. This features two memory-efficient and fast architectures for hysteresis thresholding followed by object feature extraction: a lower-area uniform implementation and a faster pipelined one with slight area increase. Both designs couple thresholding with candidate pixel handling, component analysis, and feature extraction on the fly. This avoids multiple scans of the image, additional label resolving, and large image buffers; thus offering an average speedup up to 37x with about 99% memory reduction compared to state of the art schemes for VGA images. Moreover, the ASIC implementation allows this process to be done at 460fps, making the integration of this part into real-time detection systems very feasible.
A low power adaptive transmitter architecture for low band UWB applications

An adaptive CMOS UWB transmitter architecture based on programmable pulse position modulation (PPPM) is proposed. It can operate in high-speed mode and power-saving mode depending on various QoS constrains. When the data rate is the primary concern, the transmitter operates at high-speed mode. When the power consumption becomes the major constrain, the transmitter can switch to power-saving mode. The high frequency 80 MHz clock is generated from a 10 MHz low frequency reference by a DLL-based frequency multiplier. The proposed adaptive UWB transmitter has been designed and simulated by using TSMC 0.18mum CMOS process. Simulation results shows proposed transmitter can provide a flexible knob for cross-layer QoS optimization with low power consumption
Memory-Efficient Architecture for Hysteresis Thresholding and Object Feature Extraction

Hysteresis thresholding is a method that offers enhanced object detection. Due to its recursive nature, it is time consuming and requires a lot of memory resources. This makes it avoided in streaming processors with limited memory. We propose two versions of a memory-efficient and fast architecture for hysteresis thresholding: a high-accuracy pixel-based architecture and a faster block-based one at the expense of some loss in the accuracy. Both designs couple thresholding with connected component analysis and feature extraction in a single pass over the image. Unlike queue-based techniques, the proposed scheme treats candidate pixels almost as foreground until objects complete; a decision is then made to keep or discard these pixels. This allows processing on the fly, thus avoiding additional passes for handling candidate pixels and extracting object features. Moreover, labels are reused so only one row of compact labels is buffered. Both architectures are implemented in MATLAB and VHDL. Simulation results on a set of real and synthetic images show that the execution speed can attain an average increase up to for the pixel-based and for the block-based when compared to state-of-the-art techniques. The memory requirements are also drastically reduced by about 99%.
A VLSI array for computing the DFT based on RNS

The Discrete Fourier Transform (DFT) has been adopted in a wide spectrum of Digital Signal Processing (DSP) applications due to the advances in VLSI technology, One dimensional systolic arrays are employed to implement the DFT algorithms where N DFT points can be computed in O(N) time using O(N) area. Residue Number System (RNS) is used to achieve parallelism on the mathematical level, as the arithmetic operations are performed independently for each modulus. Modularity has been realized on both functional and layout levels. Two types of arrays are described. The first array offers higher speed performance, while the second requires less area and is more general. The proposed structures are based on bit parallel processing and lend themselves to pipelining.
MRI data compression using a 3-D discrete wavelet transform.

A low-power system that can be used to compress MRI data and for other medical applications is described. The system uses a low power 3-D DWT processor based on a centralized control unit architecture. The simulation results show the efficiency of the wavelet processor. The prototype processor consumes 0.5 W with total delay of 91.65 ns. The processor operates at a maximum frequency of 272 MHz. The prototype processor uses 16-bit adder, 16-bit Booth multiplier, and 1 kB cache with a maximum of 64-bit data bandwidth. Lower power has been achieved by using low-power building blocks and the minimal number of computational units with high throughput.
An Adaptive Block Size Phase Correlation Motion Estimation Using Adaptive Early Search Termination Technique

An adaptive block size phase correlation motion estimation (ABSPC-ME) with a smart adaptive early termination technique is proposed and implemented in this paper. With its performance, efficiency and complexity ABSPC-ME is compared to that of the original phase correlation (PC) and full search block matching (FSBM) techniques. Since the phase correlation method measures the motion directly from the phase correlation map, it gives a more accurate and robust estimate of the motion vector. Besides increasing the encoding quality, the complexity of the encoder and computational cost are also decreased. Results show that there is approximately 78% reduction in computations compared with the original PC technique and 96% compared with FSBM without a significant loss in the visual quality.
Performance evaluation of 1-bit CMOS adder cells

Evaluating the performance measures of a full adder cell, like other circuits, is input pattern dependent. The issue gets more complicated when evaluating several parameters such as time delay, area, power dissipation, and correct functionality at the same time. The proposed input test pattern is based on full coverage of all possible transitions from one input pattern to another. It is composed of two parts: the first is a 56 transitions input pattern for speed measurement, followed by 9 different input patterns concatenated together for power consumption measurement. The proposed input test pattern proves the correct functionality, and produces correct time delay and power dissipation. Using this input test pattern guarantees correct and fair comparison among different full adder cells.
A new block-matching motion estimation algorithm based on successive elimination

This paper presents an exhaustive search algorithm for block matching motion estimation. The proposed algorithm reduces the computational load with successive elimination of non-candidate blocks in the search window. The proposed algorithm locates the global optima as located by the full search block-matching algorithm. This computational reduction leads to low-power VLSI implementation of the algorithm. Also, it leads to a faster efficient motion estimation procedure. The correctness of this algorithm and its complexity are presented. Simulation results on benchmark video clips are also presented.
Reducing misprediction penalty in the Branch Target Buffer

Ideal speedup in pipelined processors is seldom achieved due to stalls and breaks in the execution stream. These interrupts are caused by data and control hazards, the latter, however, can be the most detrimental to pipeline performance. Branch Target Buffer (BTB) can reduce performance penalty of branches in pipelined processors by predicting the path of the branch and caching information used by the branch. No stalls will be encountered if the branch entry is found in BTB and the prediction is correct; otherwise, the penalty will be at least two cycles. This paper proposes a novel algorithm based on changing the BTB structure to eliminate the branch misprediction penalty. It also highlights a problem in the previous BTB algorithms (nested branches problem) and proposes a solution to it.
A generalized fast motion estimation algorithm using external and internal stop search techniques for H.264 video coding standard

In this paper, a set of computationally efficient accurate skipping techniques are proposed for motion estimation. First, a partial internal stop search (ISS) technique which utilizes an accurate adaptive threshold model is exploited to skip the internal SAD (sum of absolute difference) operations between the current and reference blocks. Second, an external stop search (ESS) technique greatly reduces the unnecessary operations by skipping all the irrelevant blocks in the search area. The proposed techniques can be incorporated in any block matching motion estimation algorithm. Computational complexity reduction is reflected on the amount of saving in motion estimation encoding time. Simulation results using H.264 reference software (JM 12.4) show up to 71.26% saving in motion estimation time using the proposed techniques compared to the fast full search algorithm adopted in JM 12.4 with a negligible degradation in the PSNR by approximately 0.03 dB and a small increase in the required bits per frame by only 2%.
The Extended Cube Connected Cycles: An Efficient Interconnection for Massively Parallel Systems

The hypercube structure is a very widely used interconnection topology because of its appealing topological properties. For massively parallel systems with thousands of processors, the hypercube suffers from a high node fanout which makes such systems impractical and infeasible. In this paper, we introduce an interconnection network called The Extended Cube Connected Cycles (ECCC) which is suitable for massively parallel systems. In this topology the processor fanout is fixed to four. Other attractive properties of the ECCC include a diameter of logarithmic order and a small average interprocessor communication distance which imply fast data transfer. The paper presents two algorithms for data communication in the ECCC. The first algorithm is for node-to-node communication and the second is for node-to-all broadcasting. Both algorithms take O(log N) time units, where N is the total number of processors in the system. In addition, the paper shows that a wide class of problems, the divide and conquer class, is easily and efficiently solvable on the ECCC topology. The solution of a divide and conquer problem of size N requires O(log N) time units.
A hybrid adaptive scheme based on selective Gaussian modeling for real-time object detection

Object detection is receiving a growing attention with the emergence of surveillance systems. This paper presents a hybrid adaptive scheme based on selective Gaussian modeling for detecting objects in complex outdoor scenes with gradual illumination changes and dense, moving background objects like swinging tree branches. The proposed technique combines simple frame difference (FD), simple adaptive background subtraction (BS), and accurate Gaussian modeling to benefit from the high detection accuracy of Mixture of Gaussian solution (MoG) in outdoor scenes while reducing the computations required, thus, making it faster and more suitable for real time surveillance applications. Moreover, by applying selective component matching and updating and hysteresis thresholding, the probability of detecting a background pixel as foreground decreases leading to better detection accuracy than MoG as demonstrated in the quantitative and qualitative comparison.
theta (logN) architectures for RNS arithmetic decoding

Decoding in residue-number-system (RNS)-based architectures can be a bottleneck. A high-speed, flexible modulo decoder is an essential computational element to maintain the advantages of RNS. A fast and flexible modulo decoder, based on the Chinese remainder theorem (CRT), is presented. It decodes a set of residues into its equivalent representation in either unsigned magnitude or two's-complement binary number system. Two different architectures are analyzed: the first one uses carry-save adders, and the other uses modified structure carry-save adders. Both architectures are modular and are based on simple cells, which leads to efficient VLSI implementation. The decoder has a time complexity of theta (log N).<<ETX>>
Low complexity decimation filter for multi-standard digital receivers

This paper proposes a reduction in complexity of decimation filter architectures used in multi-standard digital receivers, using IIR filters implemented as a sum of two all-pass filters. The decimation filter is an important block in devices which want to establish communication using different standards. IIR filters are implemented on specific stages of multistage pipeline/interleaving structures, where high order filters are power consuming and area demanding. Therefore, a major reduction in complexity is obtained. Regularity is an important property of all-pass filters, which can be decomposed on first or second order all-pass transfer functions achieving more efficient implementation. The results presented are implemented in pipeline/interleaving architectures using specific decimation decomposition proposed previously. Reductions of 36%, 77%, and 80% are obtained compared with previous works, where basically these implementations are based on linear phase filters. The decimation filter architecture is simulated using Matlab.
An Efficient Data Reuse Motion Estimation Engine

We present a novel motion estimation engine (MEE) architecture that efficiently reuses search area data while fully utilizing the hardware resources. A 2-D processing element (PE) core is central to the architecture. Search area data flows both horizontally as well as vertically while the current block data is stationary. A clever PE design ensures simple but highly regular dataflow through the core avoiding long interconnect delays. For a search range of [-16,+15] and block size of 16, our architecture can perform motion estimation for 60 fps of 4CIF video at 100 MHz
Modeling and performance simulation of PULSE and MCMAC protocols in RFID-based IoT network using OMNeT++

A key challenge in applying radio-frequency identification (RFID) in internet of thing (IoT) is the need to minimize signal interference. In an effort to reduce RFID signal interference (including tag-tag, reader-tag and reader-reader signal collisions), towards IoT application, researchers have used both theoretical and experimental approaches to study, optimize and compare the performance of standard RFID anti-collision protocols, especially Aloha-based and tree-based protocols. Various protocols have also been proposed and evaluated. In the various studies, the simulation platforms, models (e.g., channel, tag, physical layer) and underlying assumptions, and performance metrics considered often vary significantly among the plethora of RFID performance evaluation studies. The goal of this work is to develop a standardized simulation framework, including related models, that can be used to evaluate proposed interference mitigation protocols under similar conditions, allowing for a more accurate and robust comparison. In this research work, we focus on the application of RFID to IoT networks. We develop an RFID-based IoT network model using MiXiM OMNeT network simulator and compared the performance of two distributed protocols — Multi-Channel Medium Access Control (MCMAC) and PULSE protocol — based on average tag reading time. We observed that, the PULSE protocol performs better only after adding 9 readers to a 81-tags grid topology. Hence, while the MCMAC protocol is better, judging by throughput, the PULSE protocol gives a higher positive spectrum utilization index after an infinite period of time.
ASIC implementation of a computationally efficient compressive sensing detection method using least squares optimization in 45 nm CMOS technology

This paper presents a high speed architecture of a recently proposed compressive sensing detection method for wideband cognitive radios using least squares. Using least squares instead of the orthogonal matching pursuit for signal recovery reduces the computational complexity where, the index search and matrix inverse stages are avoided. The proposed architecture is fully pipelined where, 14 clock cycles are required to detect 1024-length signal occupying 8 channels from 16 measurements. The design is implemented in 45 nm CMOS operating at 165 MHz. Since, the sensing time for 1024-length signal is roughly 84.8 ns, the proposed design offers high speed signal detection compared with state of art orthogonal matching pursuit architecture.
Tunable level-shifter/buffer for dual supply systems and low-power clock-tree design in deep-submicron application

A new architecture for analog tunable level-shifter is introduced in the 130 nm CMOS process. As the transistor keeps on shrinking, low power design becomes more challenging. Dual supplies are used for many low-power applications and needs level-shifter between the low Vdd and high Vdd critical path. Similarly, although the die sizes are shrinking but the high speed I/Os are relatively larger and hence use higher Vdd supply, and hence needs level-shifters in between the core and the I/O circuits. Also the clock trees are major source for power dissipation in present day high-speed design. Reducing the clock swings within the tree and the branches can help reduce the overall power dissipation for the chip. The new tunable-level shifter takes in different input voltages and shifts it to 1.2 V-1.5 V outputs. The input voltage can range from 0.45 V to Vdd, while the threshold for the shifter is tuned using a reference-voltage, thus controlling the current through the level-shifter/buffer. Modification has been done to the circuit for low-power application with minimal degradation to the performance.
MAC-SCC: a medium access control protocol with separate control channel for reconfigurable multi-hop wireless networks

In this paper, we propose a novel medium access control protocol with a separate control channel (MAC-SCC) to increase the channel efficiency and address the unfairness and instability problems of IEEE 802.11 MAC protocol. In MAC-SCC, the available bandwidth is partitioned into two channels: a data channel and a control channel, each associated with a network allocation vector (NAV). To reduce hardware complexity, the station transmits or receives on one channel only at any given time. In the network employing MAC-SCC, the next data frame can be pre-scheduled during the current data transmission via the separate control channel, and thus reducing the frame collision probability and the bandwidth wasted during backoff. Moreover the use of the separate control channel helps to achieve fair medium access and solve the instability problem resulted from frequent link failures. The optimal bandwidth partitioning between the two channels is analyzed via a statistical model, which shows 10% bandwidth for the control channel and 90% bandwidth for the data channel. The performance of MAC-SCC is quantified via extensive simulations in both a stand-alone simulator developed by using PARSEC and a comprehensive network simulator called QualNet with whole protocol stack. Our results show that MAC-SCC can effectively reduce the link failure probability, achieve fair medium access when running multiple TCP sessions, and yield a throughput gain up to 60% under high traffic load
A double-edge implicit-pulsed level convert flip-flop

Clustered voltage scaling (CVS) systems is a technique to decrease power dissipation. One of the design challenges in CVS is the efficient level converter with fewer overheads in power and delay. In this paper, we propose a novel implicit-pulsed level convert flip-flop that uses circuit techniques such as conditional discharge to reduce the overhead incurred with level conversion flip-flops (LCFF). Double-edge triggering is also used to further decrease the power consumption. In view of power, the new LCFF outperform previous published designs about 18%-56% and exhibit smaller delay and PDP.