nils-herrmann/clean_scirepeval huggingface dataset:
A self-testing systolic module for VLSI DSP applications

The authors propose a novel concurrent error-detection scheme for error detection in VLSI arrays. The proposed scheme is called LOED (logarithm-based online error detection) and is based on the use of logarithmic coding. This scheme is analyzed and its implementation details are described. Fault coverage and hardware overhead of the scheme are also discussed. The application of LOED to the convolution problem is described, and the advantages of LOED are enumerated.<<ETX>>
Hybrid multiplierless FIR filter architecture based on NEDA

This paper presents new hybrid multiplierless finite impulse response (FIR) architecture based on New Distributed Arithmetic (NEDA). The hybrid structure is a trade off between direct form and transposed direct form that results in a reduction of the critical path and the size of the delays elements as well as the fan-out. While the multiplications involved in the hybrid structure are replaced by a butterfly adder tree. Compared with previous methods, our proposed architecture achieves an average of 20% less additions. Moreover, the design method is simple and achieves better results than previous methods.
An efficient mapping of multilayer perceptron with backpropagation ANNs on hypercubes

This paper proposes a parallel structure, the mesh-of-appendixed-trees (MAT), for efficient implementation of artificial neural networks (ANNs). Algorithms to implement both the recall and the training phases of the multilayer perceptron and backpropagation ANN model are provided. A recursive procedure for embedding the MAT structure into the hypercube topology is used as the basis for an efficient mapping technique to map ANN computations on general purpose massively parallel hypercube systems. In addition, based on the mapping scheme, a fast special purpose parallel architecture for ANNs is developed. The major advantage of our technique is high performance. Unlike the other techniques presented in the literature which require O(N) time, where N is the size of the largest layer, our implementation requires only O(log N) time. Moreover, it allows the pipelining of more than one input pattern and thus further improves the performance.<<ETX>>
Traffic-aware power-gating scheme for Network-on-Chip routers

Network-on-Chip technology has become very popular in the recent decade to address the scalability issue in multi-core processors. Developing the inter-connection network improves the performance of multi-core systems at the cost of additional power and design complexity. Power-gating of router buffers as the most power consuming part of Network-on-Chip has been proposed recently to reduce the static power consumption. However, power-gating has its own shortcomings in terms of delay and power overhead that can diminish the overall performance if it is not used in sync with the traffic flow. In this paper, a power management technique has been introduced to optimize the power-gating of router input buffers by utilizing an adaptive learning scheme to estimate the future traffic arrival. The proposed design intelligently invokes the power-gating signals to the router buffers based on the statistical estimation of the traffic inter-arrival times. Syncing the power-gating signals with the traffic arrival significantly reduces the power-gating overhead caused by: mandatory wake-up delay to route immediate traffic arrival and static power consumption due to prolonging idle state in anticipation of future arrival. The simulation results indicate that the proposed scheme has average 25% improvement in the static power consumption compared to previous works while it reduces the average packet latency by 35% in comparison to naive power-gating. It is worth mentioning that the overhead of power-gating has significantly decreased by 41% compared to the proposed scheme in .
Automatic epileptic seizure detection based on empirical mode decomposition and deep neural network

Electroencephalogram (EEG) used to record the electrical activity of the brain is a standout amongst the most helpful tools which are utilized in the diagnosis of neurological disorders. In this paper, we propose two classification methods for automatic epileptic seizure detection based on EEG recordings. The proposed methods use Empirical Mode Decomposition (EMD) for feature extraction and Deep Neural Networks (DNNs) for classification. Multilayer perceptron is used in the first classification method to classify between normal and seizure cases by reducing features' dimension which speeds up the task. The classification accuracy achieved using this method is 100%. Deep Convolutional Neural Network (DCNN) is utilized in the second classification method to accomplish a high accuracy in multiclass classification task. The classification accuracy obtained using DCNN for classifying between the normal, interictal and ictal cases is 98.6%. The evaluation of the proposed methods is conducted using the 10-fold cross-validation methodology to ensure the robustness of the system.
An energy-efficient 32-bit RISC processor for sensor platform in 90nm technology

Due to limited life-time of battery, the energy constrained system for sensor platform has drawn a strong interest for ultra-low power research in recent years. In this paper, an energy efficient 32-bit RISC processor is discussed. The design is targeted for branch and data intensive computations. The design includes both architectural and circuit techniques to optimize energy consumption. An advance branch technique is introduced to reduce stalls in branch intensive application, which in turn decreases energy wastage due to incorrect branch decision. Architectural innovation also includes low power data memory access policy. On the circuit front, energy consumption is minimized by scaling down the supply voltage near to threshold. The 24Kb memory incorporates subthreshold 6T SRAM cell to ensure read stability at subthreshold voltage down to 0.18V. The design consumes 562pJ/instruction at optimal core and memory supply 0.5V and 0.33V respectively, for operating frequency 650KHz in 90nm technology.
Noise-constrained interconnect optimization for nanometer technologies

Wide, thick wiring, clock frequency in the GHz range will require interconnection analysis to consider inductance and inductive coupling effects on interconnect delay and noise. Analytical expressions are preferred because simulation is always expensive and ineffective in use with modem designs containing millions of transistors and wires. However, analytical expressions are not sufficiently accurate and do not consider all of interconnect and driver parameters. In this paper, we try to merge between analytical models and a table lookup approach to easily get the crosstalk peak noise, as well as impact of coupling on aggressor delay. The pulse width of the crosstalk noise, which is of similar importance for circuit performance as the peak amplitude, is also measured. We consider parameters like spacing, length, coupling length, place of overlap (near driver or receiver side), frequency, direction of the signals, load capacitance, rise time of the inputs, wire width for both the aggressors and the victim wires. Also, we consider parameters like shields and shield width to decrease the inductive coupling.
A multiplication-free parallel architecture for affine transformation

This paper presents a novel low power parallel architecture for computing affine transformation (AT). It is based on a new multiplication-free algorithm that employs the inherent algebraic properties of the AT. Low power has been achieved at the algorithmic level by replacing the multiplication with shifting operation, at the architecture level by using parallel computational units, and at the circuit level by using low power cells. The proposed architecture can be used as a computational kernel in object-based video processing. It is compatible with MPEG-4 and VRML standards. The architecture has been prototyped in 0.6 /spl mu/m CMOS technology with three layers of metal.
An application specific architecture for rate-distortion optimized motion compensation

The authors present the implementation details of the application specific architecture for rate-distortion optimized motion compensation. It is based on quadtree architecture which consists of two types of processors, P/sub 1/ and P/sub 2/. P/sub 1/ processors are used at the leaf level and P/sub 2/ processors are used at non-leaf levels. The proposed architecture supports pipelined operations both at the system level as well as at the processor level. The application specific prototype was designed for a block size of 4 /spl times/ 4.
An overview of IEEE standardization efforts for cognitive radio networks

The Cognitive Radio (CR) technology is envisioned as a primary solution for the spectrum scarcity problem in wireless communication networks. Cognitive radio networking allows the exploitation of the unutilized spectrum bands in an opportunistic manner, and thereby, improves the efficiency of the spectrum utilization. Cognitive radio Networks (CRNs) provide wireless connectivity via heterogeneous wireless architectures and dynamic spectrum access techniques. In this paper, we present an overview of the state-of-the-art of the IEEE standardization efforts for CR and CRNs.
Low-Power Cache Design Using 7T SRAM Cell

On-chip cache consumes a large percentage of the whole chip area and expected to increase in advanced technologies. Charging/discharging large bit lines capacitance represents a large portion of power consumption during a write operation. We propose a novel write mechanism which depends only on one of the two bit lines to perform a write operation. Therefore, the proposed 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a write operation. Experimental results using HSPICE simulation shows that the write power saving is at least 49%. Both read delay and static noise margin are maintained after carefully sizing the cell transistors
Efficient Mutliplierless Polyphase FIR Filter based on New Distributed Arithmetic Architecture

This paper present an efficient polyphase multiplierless finite impulse response (FIR) architecture based on new distributed arithmetic (NEDA). The polyphase structure is based on the decomposition of the transfer function in subfilters connected in parallel. The multiplications involved on each subfilter are replaced by an adder array implemented by NEDA. These subblocks presents a different distribution of Is and Os on the NEDA matrix compared with the implementation of the filter in a direct form or transposed form. NEDA presents a bottleneck that is reduced by a balance between a larger filter order and a reduced coefficient wordlength size impacting the whole structure with this tradeoff. This new architecture involves a reduced number of adders in their implementation without significant overhead. The results presented are compared with previous approaches showing superior result around of 34% average reduction on the total number of adders. Additionally, the proposed design method for FIR filter is simple.
Framework for generating and designing spectrum awareness modules for opportunistic networking

For improved spectrum utilization in opportunistic network (OppN), spectrum awareness (SA) metrics can be generated from the synthesis and analysis of both static and dynamic network parameters. However, there are several techniques and algorithms for evaluating network parameters. Hence, a standardized framework is needed for generating SA towards improved spectrum consumption. To the best of our knowledge, no such framework currently exist in literature. In this work, therefore, we propose a novel approach for constructing, justifying and improving SA modules for OppN. Our approach maps different SA metrics to network parameters, which we define as SA integrals. We derive the constant of proportionality (SA constant) between the metrics and the integrals as a function of reliability, computational complexity and latency. The derived SA constants can be used to justify and compare SA techniques and algorithms. Based on the results obtained from the modeling and simulation of an adhoc cognitive radio network, using QualNet, we illustrate the applicability of SA constant as an index (0.0 < SA constant < 1.0) for quantifying the level of SA derivable from any specified SA module.
An efficient approach for reducing inductive noise using shield insertion [IC layout]

An efficient technique to reduce the inductive noise is to insert shields among signal wires. These shields are quiet wires that are either connected to the ground or to the power supply. An efficient approach to determine the locations and number of shields needed to satisfy certain noise constraints is provided. We use an already existing noise model, which is flexible and fast, to be included in the core of our algorithm. Experimental results and SPICE simulations show that our approach is fast compared to the best-known approach and needs few number of shields to satisfy the noise constraints.
Optimal mapping of feedforward neural networks onto multiple bus architectures

This paper addresses the problem of mapping a feedforward ANN onto a multiple bus system, MBS, with p processors and b buses so as to minimize the total execution time. We model the computational requirements of ANN by an m-partite graph called FFCG and show that the mapping problem can be reduced to that of optimally mapping a single (arbitrary) computational layer (c-layer) to the MBS. We present an algorithm which assigns the nodes of a given c-layer to processors such that the computation lower bound [N/sup l//p]t/sub  l/ and the communication lower bound [N/sup l//b]t/sub c/, are achieved simultaneously, where N/sup l/ is the number of nodes in the mapped c-layer, and t/sub  l/ and t/sub c/, are the computation and communication times, respectively, associated with a node in the layer. When computation and communication are not overlapped, we show that the optimal number of processors needed is either 1 or p, depending on the ratio t/sub  l//t/sub c/. We show how the total execution time can be reduced by overlapping computation and communication. In that case, we show that the optimal number of processors needed is either 1 or (t/sub  l//t/sub c/)b. We show that there is a unique arrangement of interfaces such that the total number of interfaces is minimum and the optimal time is reached. Finally, we compare the relative merits of the hypercube and the MBS and show the superiority of the latter in simulating an ANN.
Design and analysis of energy reference metric in a cluster based wireless sensor network

Wireless sensor nodes are expected to make economical, energy efficient decisions in routing of data with the limited amount of battery-voltage that they have. To make overall energy-efficient decisions, an approximation of the system energy levels can be made available to the sensor nodes. The aim of this work is to propose an algorithm to get the cluster-wise global energy status of sensors' residual energies. The study and implementation is done in a cluster-based network and the computed energy status is provided to the sensors within a cluster. An energy message is proposed to assess the sub-system energy status for each cluster. Two aggregates are explored for the energy status assessment within the energy message. The first aggregate has measurement of number of sensors with defined intervals of voltage ranges. The second aggregate considers that the cluster is divided into sectors and calculates the average of residual energies of each sector. Pre-defined bits in the energy message are used to indicate the comparison results. It is seen that as the number of sensors increased, more energy-rich sensors were chosen (45.87% higher for a 9times9 sensors sized network) in the routing process, with the proposed energy message considerations than without.
A power-efficient architecture for EBCOT tier-1 in JPEG 2000

Power reduction has become a serious issue in recent years. In this paper, a power-efficient architecture for EBCOT tier-1 is proposed. EBCOT tier-1 architecture is divided into BC (bit-plane coding), AE (arithmetic encoding), and FIFO that connects BC with AE and balances the different throughput between them. In BC, simple control logics are added to reduce computation in bit-plane coding; in FIFO, memory access is reduced since AE is fed with fixed values instead of reading from FIFO; in AE, simple control logics are added to reduce computation in AE and forwarding technique combined with clock gating is adopted to reduce switching activities in the last two pipeline stages. Experimental results, with standard test image benchmarks, show that the proposed power reduction techniques keep the same system throughput and achieve about 48%, 16%, and 20% improvement for BC, FIFO, and AE, respectively, in the power consumption by comparison with the original architecture
A 90 nm low-power successive approximation register for A/D conversions

A novel low-power successive approximation register is proposed. The new register is based on gating the clock when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 14 bits has been designed up to the layout level with 1V power supply in 90nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption and 18% of transistor count.
A scalable affine core for mesh-based video object motion compensation

This paper presents a scalable affine core (SAG) that can be used for video object motion compensation. MPEG standardization committee recommends affine transformation for 2D mesh-based video object motion tracking, where the object is modeled as 2D mesh with triangular patches. The motion tracking is a texture warping for the deformed patches from a frame-to-frame. A mesh-based video motion compensation architecture is presented. The motion compensation architecture uses the proposed SAC to track the deformation of a 2D mesh-based video object. Performance study is conducted and it shows that the proposed SAC can be used in online MPEG-4 mobile applications.
A scalable affine core for video object motion compensation

This paper presents a scalable affine core (SAC) that can be used for video object motion-compensation. MPEG standardization committee recommends affine transformation for 2D mesh-based video object motion tracking, where the object is modeled as 2D mesh with triangular patches. The motion tracking is a texture warping for the deformed patches from frame-to-frame. A mesh-based video motion compensation architecture is presented. The motion compensation architecture uses the proposed SAC to track the deformation of a 2D mesh-based video object. A performance study is conducted and it shows that the proposed SAC can be used in online MPEG-4 mobile applications.
A multi-modal automatic image registration technique based on complex wavelets

Image registration is considered one of the most fundamental and crucial pre-processing tasks in digital imaging. This paper describes a fast multimodal automatic image registration algorithm that handles the alignment of IR and visible images. A multiresolution approach based on Dual Tree-complex wavelet transform is employed to speed up the process. At the coarsest level, an accurate registration estimate for higher levels is achieved, using edge detection and cross correlation. Mutual Information, on the other hand, is applied at higher levels as a matching criterion applied to the six orientation bands of the complex wavelet. The process is completely automatic, and was tested on several sets of synthetic and real data. Experimental results show that the proposed technique exhibits better accuracy than DWT-based algorithms for uni and multi-modal cases.
On-chip learning for a scalable hybrid neural architecture

A new class of neural architecture with on-chip learning has been developed. Learning has been implemented in analog while the control is performed in digital. An efficient analog technique has been developed to refresh the capacitors that store the synaptic weights. The graded update signals are also generated in analog, it is added to the weights via simple local analog adders. This localization of weight update makes the complexity of the learning procedure independent of the overall network size. The new ar chitecture is based on a computational kernel composed of two chips; the SynChip and NeuChip. The SynChip consists of an array of 32/spl times/32 analog synapse modules (SynMod), a digital control block (SynLogic), a voltage reference of 16 levels, and 32 refreshing blocks (RefMod). The NeuChip consists of a 32 analog neurons modules (NeuMod) and a digital control black (NeuLogic). This two-chip set can be cascaded on a regular grid to build large size neural networks.
A novel scheduling-based CAD methodology for exploring the design space for low power

This paper describes a novel approach to scheduling with multiple supply voltages in the high-level synthesis. The proposed approach considers, identifies, and exploits the maximal parallelism available in an initial schedule, and applies a modified stochastic evolution mechanism to iteratively improve, or re-schedule, the previously obtained best-schedule to reduce the maximal power consumption of function-units. Based on simulation and evaluation of the proposed approach (using standard benchmarks), it is observed that a power saving of upto 80% is possible when three supply voltage levels, 5 V, 3.3 V, and 2.4 V are considered. In addition to scheduling for low power, the proposed methodology can serve as a vital guiding tool to a designer for studying the efficacy of different design choices before a final design option is selected.
A PUF-based paradigm for IoT security

Physically Unclonable Functions or PUFs have emerged as a promising lightweight authentication alternative to traditional cryptography. This made them a promising candidate for constrained IoT devices. These PUFs however have been found to be vulnerable to modeling attacks to varying degrees. The security of different PUFs designs against these modeling attacks have been evaluated in multiple research efforts. However, a more accurate evaluation that incorporates the area footprints of the different PUFs is missing from the literature. Such evaluation is rather essential in order to determine the most suitable PUF design for the different constrained IoT devices. To perform this evaluation, we implemented several strong delay-based PUFs. The results showed that when factoring in the PUFs implementation area costs, these PUFs compare differently as some enhanced PUF designs turned out to have inferior efficiency compared to their simpler counterpart. We recognized the most effective design elements in the implemented PUFs. Based on the efficiency figures obtained, we recommended the optimal PUF design for the different security schemes used in constrained IoT devices.