nils-herrmann/clean_scirepeval huggingface dataset:
“Voodoo” error prediction for bit-depth scalable video coding

A new prediction method for bit-depth scalable video coding is proposed in this paper. Correlation between the dropped bits during linear scaling tone mapping is used as the basis for using the error as an additional aid in predicting the high bit-depth enhancement layer. The residual to be transmitted in the enhancement layer is reduced by this technique. The effectiveness of this technique is increased when using a small quantization parameter. We show up to a 20% reduction in bit rate of the CAVLC output in our simulation test frames. Bit-depth scalability may be needed in future systems that will support legacy display applications as well as future high dynamic range displays.
An efficient implementation of multi-layer perceptron on mesh architecture

This paper presents a new efficient parallel implementation of multi-layer perceptron on mesh-connected SIMD machines. A new algorithm to implement the recall and training phases of the multi-layer perceptron network with back-error propagation is devised. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architecture such as hypercube without the added cost; it requires O(1) multiplications and O(log N ) additions, whereas most others require O(N) multiplications and O(N) additions. The proposed algorithm maximizes parallelism by unfolding the ANN computation to its smallest computational primitives and processes these primitives in parallel.
Interconnect noise analysis and optimization in deep submicron technology

The migration to using ultra deep submicron (UDSM) process, 0.25 /spl mu/m or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.
A 10-transistor low-power high-speed full adder cell

In this paper, we introduce a high-speed low-power 10-transistor 1-bit full adder cell. The critical path consists of an XOR gate; an inverter and one pass transistor. A prototype of the proposed adder cell in 0.6 /spl mu/m CMOS technology has an average delay time of 0.084 ns. It also exhibits low average power dissipation of 0.891/spl times/10/sup -4/ watt at frequency equal to one GHz. In an n-bit adder circuit, the new adder cell will give alternate polarity for the carryout in the odd and even positions. The inverters in the structure of the proposed FA cell act as drivers. Therefore, each stage will not suffer a degradation in its deriving capabilities. This saves power, area, and time. The new cell is used to build a prototype for a 32-bit ripple carry adder. This prototype has 384 transistors and it operates at 2.8 V with an average delay of 4.1 ns, and a low power dissipation of 2.6 mW at frequency equal to 250 MHz.
A post-processing algorithm for short-circuit defect sensitivity reduction in VLSI layouts

Yield enhancement may well be regarded as the quintessential objective in microelectronic manufacturing. With diminishing feature size and increasing die area the amount of functional silicon on a die is too expensive to discard in the event of short-circuit and open-circuit faults. Designing chips with high tolerance against faults, therefore, holds a great promise for profitable manufacturing in the semiconductor industry. In this paper we propose a post-processing defect-tolerant routing algorithm that reduces or eliminates short-circuit sensitive area, and minimizes vias in a two-layer channel routing solution. The algorithm is built to be sensitive to manufacturer's defect pareto figures. This feature gives the designer the flexibility of customizing the routing algorithm to the desired defect-tolerant features without increasing the die area or interconnect length.
A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits

Outsourcing the chip for fabrication is an efficient way to save money and reduce time to market. However, it raises numerous security challenges for chip designers, as some of the foundries try to identify the functionality of the chip to take its ownership. Furthermore, some foundries may insert a Trojan circuit to affect the functionality of the chip or steal valuable information about the design such as encryption key. Each Trojan may utilize low toggle (LT) nets to trigger its activation . Hence, it is tough to detect a Trojan circuit during the testing step as it lies dormant for ages and waits until its rare activation conditions are met. Consequently, some mechanisms are required to neutralize the attacker's plans for inserting a Trojan circuit. 3D Integrated circuit (3D-IC) can be a practical solution to the challenges that threaten the security of the chip. One of the famous features of 3D-IC is its capability of split manufacturing of the chip, as the whole design can be distributed among different tiers in the 3D stack. Tiers containing critical logic blocks are sent to a trusted local foundry to be fabricated while the less significant tiers are sent to the less reliable foundries to save money. In this work, we propose a method to sabotage the trigger criteria for a hardware Trojan. To do so we obscure root LT nets by replacing each of them with a vertical interconnect known as Through Silicon Via (TSV) in a 3D-IC structure. A root (earliest ancestor) LT net is defined as a net that is the origin of other LT nets. As we will discuss in section IV, obscuring a root LT net will result in hiding the toggle characteristics of its offspring LT nets. Therefore, untrusted foundries will not be able to exploit LT nets for activating their Trojan circuits. They may even use the high toggle nets for enabling the Trojan circuit. Thus, the chance of Trojan circuit getting compromised during the testing process will be high. In the end, list of root LT nets obtained from our algorithm will be used in upcoming partitioning stage to boost the security of the design.
High-performance and low-power conditional discharge flip-flop

In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.
A new cell for low power adders

Reducing power dissipation at the circuit level is considered one of the main factors in developing low power systems. Also, minimizing power of the most commonly used circuit module, will lead to a global power reduction. Following these two design philosophies, a low power speed adder has been developed based on a new cell. This cell is a combination of an XOR gate and transmission gate. It offers both low power and high speed performance. The proposed cell has been compared with two other basic common cells. An extensive analysis of three types of adders, namely carry lookahead, carry select and carry skip has proved the superiority of the proposed cell.
A novel low-power building block CMOS cell for adders

A new low-power, high-speed CMOS 1-bit full adder cell is presented. It is based on recent designs of XOR and XNOR gates, and pass-transistors, it has 16 transistors. This cell has been compared to two widely used efficient adder cells; the transmission function full adder cell (16 transistors), and the low power adder cell (14 transistors). The new cell has no short circuit power and lower dynamic power, because of less number and magnitude of circuit capacitances. It consumes up to 21% less power than the other two cells, while it is 12% to 20% faster. A comparative analysis (using Magic and Hspice) for 8-bit ripple-carry and carry-select adders shows that the adders based on the new cell can save up to 29% of power consumption.
High speed intra mode and direction prediction for MPEG-2 to H.264/AVC realtime transcoder

The paper presents a significantly fast INTRA mode and direction prediction algorithm for MPEG-2 to H.264/AVC time sensitive transcoders for mobile applications. The mode and direction prediction in H.264/AVC encoder is responsible for a huge portion of the delay in the transcoder. An efficient transcoder would take advantage of the information stored in MPEG-2 bitstream (i.e. DCT coefficients) to simplify the IN-TRA prediction in H.264/AVC. Based on the spatial activity analysis using a smoothness determining factor and an edge orientation detector, an early mode decision technique and an INTRA direction prediction for each mode are proposed. The proposed algorithm utilizes the DCT coefficients of the MPEG-2 to eliminate redundant operations in the H.264/AVC encoder part of the transcoder. The Experimental results; using frames with different resolution; show 92% transcoding time elimination at slight PSNR degradation (less than 3.5%) compared with the conventional transcoder.
Empirical model-based adaptive control of MANETs

The performance of mobile ad hoc networks (MANETs) depends upon a number of dynamic factors that ultimately influence protocol and overall system performance. Adaptive protocols have been proposed that adjust their operation based on the values of factors, such as traffic load, node mobility, and link quality. In this work, however, we are investigating the feasibility of an adaptive model-based self-controller that can manage the values of controllable factors in MANETs. In general, the proposed self-controller should determine a set of factor values that will maximize system performance or satisfy specific performance requirements. The model-based controller adapts or reconfigures system-wide parameters or protocol operation as a function of the dynamically changing network state. In this paper, we describe the proposed self-controller, its design issues, and provide a preliminary case study to demonstrate the effectiveness and tradeoffs of two potential empirical-modeling techniques: regression and artificial neural networks.
A novel scheduling-based CAD methodology for exploring the design space of ASICs for low power

This paper describes a novel approach to scheduling with multiple supply voltages in the high-level synthesis of ASICs. In a significant shift from the existing scheduling algorithms for multiple voltages, the proposed approach considers, identifies, and exploits the maximal parallelism available in an initial schedule, and applies a modified stochastic evolution mechanism to iteratively improve, or re-schedule, the previously obtained best-schedule to reduce the maximal power consumption of function-units. Based on simulation and evaluation of the proposed approach (using standard benchmarks), it is observed that a power savings of up to 80% is possible when three supply voltage levels, 5 V, 3.3 V, and 2.4 V are considered. In addition to scheduling for low power, the proposed methodology can serve as a vital guiding tool to a designer for studying the efficacy of different design choices before a final design option is selected.
Self-healing router architecture for reliable network-on-chips

NoCs are a well established research topic and several Implementations have been proposed for Self-healing. Self-healing refers to the ability of a system to detect faults or failures and fix them through healing or repairing. The main problems in current self-healing approaches are area overhead and scalability for complex structure since they are based on redundancy and spare blocks. Also, faulty router can isolate PE from other router nodes which can reduce the overall performance of the system. This paper presents a self-healing for a router to avoid denied fault PE function and isolation PE from other nodes. In the proposed design, the neighbor routers receive signal from a faulty router which keeps them to send the data packet which has only faulted router destination to a faulty router. Control unite turns on switches to connect four input ports to local ports successively to send coming packets to PE. The reliability of the proposed technique is studied and compared to conventional system with different failure rates. This approach is capable of healing 50% of the router. The area overhead is 14% for the proposed approach which is much lower compared to other approaches using redundancy.
Wireless sensors networks infrastructure for Oil Industry

Computers, communication, and sensing technologies are converging to change the way we live, interact, and conduct business. Wireless sensor networks reflect such convergence. These networks are based on collaborative efforts of a large number of sensor nodes. They should be low-cost, low-power, and multifunction. These nodes have the capabilities of sensing, data processing, and communicating. Sensor networks have a wide range of applications, from monitoring sensors in industrial facilities to control and management of energy applications to military and security fields. Because of the special features of these networks, new network technologies are needed for cost effective, low power, and reliable communication. These network protocols and architectures should take into consideration the special features of sensor networks such as: the large number of nodes, their failure rate, limited power, high density, etc. In this talk the impact of wireless sensor networks will be addressed, several of the design and communication issues will be discussed, and a case study of a current project of using such networks in Oil Industry; seismic analysis and drilling, management of off-shore oil and natural gas platforms in the gulf region, Instrumentation, and security will be given.
Towards real-time DPM object detector for driver assistance

Automatic object detection is a rapidly evolving area in surveillance and autonomous vehicles. Deformable part model (DPM) is a well-known object detector for its high precision and speed bottleneck. This paper proposes a very fast object detection pipeline based on complementary techniques to accelerate DPM. A recent fast feature pyramid technique is employed with look-up table HOG features, Fast Fourier Transform and early classification technique to speed up DPM and maintain its accuracy. We exploit SIMD optimization and multiple cores to achieve a real time detector. Our results shows that we achieve a speed-up of 50x and 6x on a single core over DPM and cascade DPM respectively. Our optimized version processes a 640×480 pixel image at 38 fps.
Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach

Different applications require different communication performance between subnets in a global hybrid network-on-chip (NOC) of a heterogeneous CPU-GPU architecture (HSA). It is impractical to deploy (at design time) or switch-on (at runtime) all the hybrid routers in the network for a certain application that needs several hybrid routers for communication. Reconfiguring the customized global hybrid NOC is important because the cost of deploying/powering these hybrid routers will be reduced significantly when the network scales up. Hence, applying optimization is feasible on this problem.We consider the problem of optimizing the quantity of the utilized hybrid routers in the global hybrid NOC, when the applications and network configurations are known. This problem can be cast as a mixed-integer linear programming which is known to be NP-Hard in general.We propose a prediction model of estimating the near-optimal amount of the utilized hybrid routers with a quick time. Our evaluation shows that the solution time of the prediction model outperforms that of the conventional model by 99 percent on average. The models also saved up to 84 percent on average in terms of the router utilization, compared to without using the models. We validated our estimated results by simulating them in HSA to prove the efficient performance.
VLSC: Video Live Streaming Using Cloud Services

Live streaming of video contents over the Internet generally requires conversion (i.e.,transcoding) of the video contents based on the characteristics of viewers' devices (e.g.,spatial resolution, network bandwidth, and supported codec). Due to the complexity of video transcoding process, live streaming service providers are becoming reliant on cloud services (e.g.,Amazon AWS1). With the scalable and reliable processing capability that clouds offer, live streaming service providers are able to transcode the live streams in a timely manner and fulfill viewers' Quality of Service (QoS) demands. For that purpose, cloud services must be utilized efficiently. In this paper, we present a cloud-based architecture that facilitates transcoding for live video streaming. Then, we propose a scheduling method for the architecture that is cost-efficient and satisfies viewers' QoS demands. We also propose a method -- utilized by the scheduler -- to predict the execution time of transcoding tasks before their executions. Experiment results demonstrate the feasibility of cloud-based transcoding for live video streams and the efficacy of the proposed scheduling method in satisfying viewers' QoS demands without imposing extra cost to the stream provider.
Fast region-based DPM object detection for autonomous vehicles

Real-time object detection is essential for self-driving cars and traffic monitoring. Deformable part model (DPM) is a popular competitive detector for its burden of intensive computations. We present a fast category independent object detector based on integrated modules to speedup DPM steps. An Edge Boxes region proposal technique is integrated with a feature pyramid approximation and neighborhood aware cascade to accelerate DPM with a comparable precision. Moreover, we employ assembly and SSE optimization with multi-threading to perform detection in real-time. Our experiments on different benchmark datasets show that our proposed framework is 59 times faster than original DPM using a single core. Meanwhile, our optimized implementation can process Pascal VOC at 47Hz and a VGA image at 40HZ with about 2% loss in accuracy.
Real-time Parallelized Hybrid Median Filter for speckle removal in ultrasound images

Medical Imaging has historically been very successful to expose the patient's anatomy beyond external visibility; thus, allowing more efficient and accurate treatments. The field of medicine continues to search for new techniques in order to increase accuracy, reduce complications, enable real-time feedback, allow early detection and reduce human errors. Various medical imaging techniques exist but suffer from multiple correlated noise or performance that hinders real-time application; ie, ultrasounds. Our contribution attempts to solve both of these problems efficiently to be enable real-time procedures Our work is based on the hybrid median filter. We implemented Parallelized Hybrid Median Filter on FPGA Virtex6 in order to be able to exploit parallelism and real-time capabilities. We were able to get the desirable visual results for experts at 382MHz frequency with 150μs completion time for full 512×512 ultrasound image to complete despeckle.
A stochastic evolution based register allocation using multiport memories

In data path synthesis, intermediate outputs of functional blocks are stored in registers. Allocation of physical resources (register files) to registers is done by the designer. In some high level synthesis systems (CMU-DA), memory ports are allocated to registers with disjoint access times. In this paper, we present a stochastic evolution based approach to register allocation using multiport memories. In this approach allocation of registers to multiport memories proceeds in a way as to minimize the interconnection between memory ports and the functional units, while placing constraints on access time requirements of registers. This approach could be used in design space exploration to determine how many read/write ports per bank would best suit the application. We have implemented the algorithm and tested in on standard benchmarks. The approach yields good results.<<ETX>>
A prototype chipset for a large scaleable ATM switching node

This paper presents a chipset for a 16/spl times/16 switching node for the distributed banyan network. This chipset enables the use of a larger and much more efficient switching node than was previously available. Very high performance is required of the chips and thus a number of special circuits have been designed to achieve this performance. The chipset resulting from this design consumes low power. The chips have been designed in 1.0 micron CMOS using a mixture of static and dynamic logic. To achieve the speed needed for a larger node, a register file has been employed to store the packet headers on the control chip. It has an area of 3,150/spl times/3,750 micron, and uses 130,000 transistors. The SRAM blocks on the switch chip, which store a bit-slice of the packets, uses 228,600 transistors.
An enhanced low-power computational kernel for a pipelined multiplier-accumulator unit

A novel low power Computational Kernel (CK) for pipelined multiplier-accumulator unit is proposed. It is composed on of 1-bit full adder cell and a C/sup 2/MOS latch. This new CK offers efficient solutions to several problems experienced by existing cells such as large driving load, delay-time in the sum signal, unwanted transitions and the increase in the short circuit power component. Simulations of several prototypes have shown that the new CK consumes 18% less power than most of the other cells at several voltages. The MAC unit based on the new CK consumes 35% less power than the standard MAC units and can also operate efficiently at lower voltage.
An efficient polynomial-modulus based technique for multiplication of large integers

This paper proposes a computational method for polynomial-modulus residue number system (PMRNS), a system in which residue is calculated after decomposing the numbers into polynomial of desired radix. This residue can be used to find product, sum, and difference so that different steps (e.g. finding the residue, addition/subtraction etc. of residues, conversion of result into an integer) can be performed in parallel to enhance the speed of operation. The advantages of the proposed method are: i) it does not need to calculate multiplicative inverse for conversion from the residue product to the number; and ii) it does not need to increase the number of modulus as the number gets larger, instead radix can be increased to meet the computational need.