nils-herrmann/clean_scirepeval huggingface dataset:
A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic

Domino Logic's excessive power consumption limits its use to ICs with lax power budgets. A dynamic clock gating scheme for Domino that takes advantage of inactive portions of functional unit operands is proposed. Through efficient switching activity detection, activity-domain partitioning, and a specific multi-phase configuration, significant power saving is achieved in a 32-bit Kogge Stone Adder at the cost of increased setup time in the preceding pipeline stage.
A thinning algorithm for Arabic characters using ART2 neural network

The authors propose a thinning algorithm based on clustering the image data. They employ the ART2 network which is a self-organizing neural network for the clustering of Arabic characters. The skeleton is generated by plotting the cluster centers and connecting adjacent clusters by straight lines. This algorithm produces skeletons which are superior to the outputs of the conventional algorithms. It achieves a higher data-reduction efficiency and much simpler skeletons with less noise spurs. Moreover, to make the algorithm appropriate for real-time applications, an optimization technique is developed to reduce the time complexity of the algorithm. The developed algorithm is not limited to Arabic characters, and it can also be used to skeletonize characters of other languages.
VLSI architecture for an object change detector for visual sensors

Object detection is a crucial step in visual surveillance. Traditionally, object detection has been performed purely in software in surveillance systems. The problem of object detection, however, becomes critical in the upcoming wireless visual sensors because of size and power constraints. The need for low-power, small size, hardware implementations is greatly felt. This paper introduces a VLSI architecture for Wronskian change detector (WCD). Object detection is done through background subtraction. WCD offers regularity, low complexity and accuracy as well as global illumination changes independency. WCD can be employed in automated visual surveillance on buildings and adjacent parking lots. WCD replaces each pixel by a vector containing luminance value of the pixel and its surrounding area. A linear dependency test is applied to each vector to determine if a change has occurred. WCD is mapped into a 12-processing element array with a fixed window value of 3/spl times/3. Design of each processing element is discussed in detail. Based on extensive search, no VLSI implementation of WCD has been reported previously.
RSSI range estimation for indoor anchor based localization for wireless sensor networks

Range estimation using RSSI (received signal strength indicator) for localization application for wireless sensor networks is a challenging task. Interference from the shared 2.4GHz channel and fading due to multipath propagation and shadowing deteriorate the process of range estimation. In this work an estimation of these noise levels that are present in the environment is being carried out by anchor nodes which are placed throughout the sensing field. These anchor nodes will compare the actual distance between them with distance computed from the measured RSSI. Four different techniques have been devised that applies a smoothing coefficient on the measured RSSI taking into consideration information about the environment from the anchor nodes. Simulation shows that even when the error introduced is equivalent to 100% of the transmission range, the error in range estimation was around 25%.
A mesh based motion tracking architecture

This paper presents a video object motion tracking architecture that can be used for very low bit rate online video applications. The architecture prototypes a 2D mesh-based video object motion tracking algorithm. It can be used as a building block for 2D mesh-based video object systems such as MPEG-4 and MPEG-7 systems. Moreover, the power consumption and the delay show that the prototype can be used in mobile online video applications.
Three-level parallel high speed architecture for EBCOT in JPEG2000

A multi-level parallel high speed architecture for embedded block coding with optimized truncation (EBCOT) tier-1 in JPEG2000 is proposed. To increase the system throughput, this architecture adopts three levels of parallelism: 1) parallelism among bit-planes - all the bit-planes can be processed simultaneously; 2) parallelism among three pass scannings - three passes scan one bit-plane in parallel; 3) parallelism among coding bits - bits that are coded in different passes can be coded simultaneously without any conflict. Experimental results show that the proposed architecture can encode one code block with size N/spl times/N in only 0.6/spl times/N/spl times/N clock cycles, and is twice as fast as the fastest architecture in the literature so far.
CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits

Power gating can be a source of disturbances detrimental to IC robustness and response time. This work introduces Current-Equalized Multi-Stage Power Gating (CEMS-PG), a parameterized algorithm for finding an efficient wakeup approach given a maximum tolerable fluctuation in the power distribution network. Applying both partitioning and scheduling, CEMS-PG efficiently divides a power gated circuit into partitions with near-equal surge currents, making them suitable for an improved form of Staggered-Phase Damping. Our simulations show up to 44% improvement in wakeup time and 78% in peak noise, offering minimal compromise between the two.
A fast heuristic for leakage-aware synthesis

With decreasing device sizes, and especially in the nanometer realm, the leakage power is growing and is in excess of 40% of the total power consumption. Therefore, methods are needed that reduce the leakage power. This work considers power minimization during high-level synthesis through a fast heuristic scheduling algorithm to reduce the leakage power. The proposed synthesis system constructs a library of functional units with subunits operating either at a high threshold voltage or a low threshold voltage. Consequently, the library is populated with several design choices with respect to the leakage power dissipation and speed offered. The input to the system is a behavioral description of the circuit to be synthesized. The proposed scheduling algorithm tames the complexity of the optimal scheduling (a well known NP-Complete problem) through a low-complexity heuristic scheduling. The details of the algorithm, complexity analysis, illustration on simple test cases, as well as the results obtained on the standard benchmarks are presented. The results (i.e., synthesized, time-scheduled structure) show significant reduction in the leakage power without sacrificing the original speed
Low power and high speed explicit-pulsed flip-flops

Flip-flops play an important role in building digital CMOS designs. Their design and optimization is critical for high-performance and low power systems. In this paper, we propose high-performance and low power flip-flops based on the explicit-pulsed flip-flop (EPFF). These new flip-flops eliminate the hazardous glitches associated with the original EPFF output. The Static-EPFF (SEPFF) is developed for low-power dissipation purposes; it reduces the power dissipation by 13.9%-15.7%, and it enhances the speed by 4.86%-7.87%. For high-speed objectives, the dual path single-transistor-clocked EPFF (STC-EPFF) achieves 21% enhancement in speed over EPFF at the expense of increased power dissipation (12%).
Multiple voltage-based scheduling methodology for low power in the high level synthesis

A methodology for resource-constrained scheduling, in the scenario of function units operating at variable voltages, is presented. Reducing the power consumption while maximizing the hardware sharing is accomplished through a novel formulation. Available parallelism is identified in an initial schedule, and different "zones" with individual weights are created and used for maximally reducing power consumption of the function units whenever a low power schedule is desired for an increased latency. The reduction in throughput due to increased latency is assumed to be compensated through pipelining. There are two main contributions of this work: providing a low complexity algorithm for scheduling with multiple voltages, and providing a mechanism to generate low-power schedules which are realistic, and for which the design of a controller is feasible. The proposed algorithm is applied to standard high-level synthesis benchmarks, and the results indicate significant power savings.
A low power 3-D discrete wavelet transform processor for medical applications

This paper presents a low power 3-D discrete wavelet transform processor for medical applications. The main target of this work is the compression of Magnetic Resonance Imaging (MRI) data using a wavelet based scheme. A prototype has been developed to realize a 3-D wavelet compressor. The processor is based on an architecture that uses a centrally controlled unit to coordinate sub-systems which carry out the operations necessary for the data compression. The subsystems include a small cache memory used for block data storage, parallel high and low pass filters used for data calculation, and two coefficient units used to retrieve off-chip wavelet coefficients. The processor has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype processor is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype, area, time delay, power and utilization has been evaluated. The prototype operates at an estimated frequency of 272 MHz and dissipating 0.5 W of power.
Ultra low power 1-bit adder cells

Supply voltage scaling is considered to be an effective technique for reducing power consumption of digital CMOS circuits. But such approach has a detrimental effect on system performance, which renders it impractical for many applications. However, in some applications, where power consumption is of critical importance, supply voltage scaling can be reasonably effective. In this paper power critical applications are considered and a set of adders is presented. The supply voltage scaling technique is applied and different adders are analyzed for a range of supply voltage levels (1.8-0.15 Volts). It is found that at very low supply voltage levels, the performance experiences immense deterioration. Moreover, for a fixed frequency of operation, the lowest supply voltage level attainable depends on circuit structure.
Contention reduced/conditional discharge flip-flops for level conversion in CVS systems

Clustered Voltage Scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the efficient level converter with fewer overheads in power and delay. Several novel level conversion flip-flops (LCFF) are proposed: a single-ended contention reduced LCFF (CR-LCFF) and double-ended conditional discharge LCFFs (CD-LCFF). Novel circuit techniques are employed for reducing the LCFF overhead, including conditional discharge technique which effectively suppresses dynamic power, contention reduce technique which suppresses short circuit power in DCVSL circuits during transition. A new pulse generator with 10 transistors is used in the proposed LCFFs. In view of PDP, the new LCFFs outperform previous published designs by about 37.7%-41%.
Introducing a Novel Smart Design Framework for a Reconfigurable Multi-Processor Systems-on-Chip (MPSoC) Architecture

In this work, a smart designing framework for a Systems- on-Chip has been proposed. We examined a reconfigurable MPSoC architecture which incorporates one Processor-FPGA core to ensure flexibility and better design parameters. The objective of this work is to propose and develop a smart framework which initiates this philosophy: the system would build a better system by itself. The system would learn about usage statistics by using an android application. Then the system would form a decision function and classify the user with the help of support vector machine-based machine learning algorithm. According to user's preference, it would re-design the reconfigurable MPSoC to ensure customized and superior user experience. The machine learning algorithm runs on cloud for saving computing power and resources. An image processing task has been performed as a case-study on a FPGA-SoC platform and on GPU as a proof of concept to ensure current standards. As of our knowledge, this is a novel and competent approach of designing system for hand-held devices which enables customization of the device after the manufacturer's end.
A Novel 90nm 8T SRAM Cell With Enhanced Stability

As the MOSFETs channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to dopant fluctuation in the channel region. In this paper , a novel highly stable 8T SRAM cell is proposed which eliminates any noise induction during read operation and keeps the Read SNM as high as 415 mV at VDD = 1.2 V in 90 nm technology. The cell also supports low power operation at Cell VDD as low as 0.41 V. This new asymmetric cell structure is capable of using differential sense technique for high speed read operation.
Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.
A 6-bit 130-MS/s low-power tracking ADC in 90 nm CMOS

In this paper, a new design for a low power CMOS current-mode Tracking Analog-to-Digital Converter (ADC) is proposed. A 6-bit ADC, with a maximum acquisition speed of 130 MHz, is implemented in a 1 V analog supply voltage. HSpice simulation results for the proposed tracking ADC verifying the analytical results are also given. It shows that the circuit consumes a static power of 0.63 mW and a dynamic power of 0.49 mW in a commercial 90 nm CMOS process.
A low power 10-transistor full adder cell for embedded architectures

A high performance Full adder cell has been designed using 10 transistors. The proposed cell has the advantage of low power consumption and high operating speed. Moreover, it occupies small area due to the small transistor count. The low power objective is achieved at the circuit level by reducing the number of internal node capacitances, by eliminating direct paths between the supply voltage and the ground, and by maintaining low switching activity in the circuit. The circuit is prototyped using 0.35 /spl mu/m CMOS technology using Cadence development tools and simulated using Hspice. The circuit consumes 0.752*10/sup -4/ Watt at a frequency of 500 MHz. The proposed cell is compared with both the standard Transmission Gate adder cell and a 16-transistor adder cell that was recently developed and characterized by its low power consumption compared to other adder cells. A 4-bit multiplier is constructed using the proposed adder cell and used as a test vehicle to check the performance of the new proposed design in embedded architectures.
Simultaneous partitioning, scheduling and allocation for synthesis of multi-chip module architectures

We present a simultaneous partitioning, scheduling and allocation technique for the synthesis of multi-chip module architectures. It is based on the Stochastic Evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. Before the actual partitioning is performed, Supernodes are created based on the scheduling/allocation constraints which in turn reduces the search space for the partitioner. We formulate the partitioning problem as an extension to the Network-Bisectioning problem for which the Stochastic Evolution heuristic has been shown to provide better results than the Simulated Annealing technique. Scheduling/Allocation and Pin Sharing are also performed simultaneously with partitioning to estimate the area and pincount requirements for each of the partitions. Efficient partitions are obtained for some of the digital signal processing applications in reasonable CPU time.
A scalable systolic array architecture for the 2D discrete wavelet transform

A systematic synthesis approach has been applied to the 2D discrete wavelet transform (DWT), and a scalable systolic array architecture has been derived based on the data dependence analysis and linear index space transformation. The architecture has regular topology, local routing, simple controller and high throughput rate, and it can be easily extended to different parameters of various levels, macroblocks and filters. The architecture has been implemented on Cadence Edge Framework.
An efficient VLSI adder for DSP architectures based on RNS

The implementation of Residue Number System (RNS) architectures using the VLSI technology is discussed. An example of implementing an RNS adder is presented in this paper. Two approaches; the look-up table and the binary adder, have been analyzed in the scope of VLSI criteria where the performance measures are area and time. Two models have been developed, they are flexible, support any modulus, and they provide custom design capabilities. Within the context of this paper, it has been found that the look-up table approach is superior in both area and time up to 5 bits, while the binary adder approach offers better performance for larger moduli.
Motion estimation algorithm for real-time systems

The paper presents an algorithmic enhancement of the full-search block-matching algorithm for motion estimation for real-time systems. The multi-stage interval based motion estimation (MIME) algorithm reduces the computational load by successively eliminating candidate blocks from the search window. The elimination process uses low bit-resolution and it is applied in multiple stages for motion vector computation. On average, MIME eliminates more than 88% of the candidate blocks in the search window after the first and second stage. Based on these results, in a real-time environment, the algorithm can be stopped at any stage without incurring significant loss in motion estimation accuracy. Simulation results show that, in the worst case scenario when the algorithm stops after first stage, there is an average loss of only 3 dB in PSNR as compared to the full-search block-matching algorithm and an average loss of 1.2 dB if the algorithm is stopped after the second step.
Real-time streaming challenges in Internet of Video Things (IoVT)

The limited capabilities of Internet of Things (IoT) devices make real-time video streaming a major challenge. Video encoding and transmission are computationally intensive processes. Applications; like urban surveillance and health care monitoring, require real-time high definition video streams. Current video encoders are not designed to meet these requirements, thus alternative architectures, algorithms and compression techniques are needed to meet these goals. In this paper, real-time video streaming challenges for IoT applications are presented.
Efficient multistage decimation filter using pipeline/interleaving architectures for digital IF receiver

This paper presents an efficient multistage decimation filter using a specific decomposition multistage and pipeline/interleaving technique to reduce the amount of multiplications. The multistage decimator filter is an important block on digital IF receivers for advanced dedicated mobile data technology called Mobitex and Ardis networks. The results are presented and compared with current results in the literature. The frequency response shows that the requirements are reached and the amount of multiplications is highly reduced. In each case, we get results with an improvement of 55% and 45% just in the multistage decimation filter. Additionally, using PI techniques we just need a single filter to process the components I, and Q in the IF digital receiver.
MAP decoder architecture: soft IP for SOC applications

A soft IP for MAP decoder is presented. The Soft IP supports different design objectives, such as high performance and area efficiency. System parameters and required performance configure the IP yielding the architecture. The IP is realized using VHDL and scripts that accept design specification from the designer and automatically generate a synthesizable HDL. FPGA platform is used for rapidly prototyping the IP core. Prototyping adhering the third generation standard yields architectures range from 56 Kbps up to 20 Mbps.
Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design

In this paper, we propose a low-power SRAM design by reducing the accessed bit line capacitance. Each column is divided into divisions. Each division consists of equal number of cells connected together with a local bit line and one local sense amplifier. The divisions are connected together with a global bit line that is also connected to the write, precharge, and reading sense amplifier circuits. During write operation, the global bit lines is slightly discharged to develop a small voltage difference on the accessed local bit lines enough for the local sense amplifier to amplify it to full swing on the local bit lines pair only. The experimental results show reduction in the power consumption that can reach more than 88% with no performance degradation. The architecture is flexible to be used according to the power, and area budget.
Enhanced efficient Diamond Search algorithm for fast block motion estimation

In this paper, a Modified Diamond Search (MDS) algorithm is proposed for fast motion estimation based on the well known Diamond Search (DS) algorithm. A set of computationally efficient algorithms that can be applied to any block matching algorithm and is applied to the DS as a study case achieves higher complexity reduction than DS algorithm without further relative PSNR (peak signal to noise ratio) degradation compared to Full Search (FS). First, Dynamic Internal Stop Search (DISS) algorithm is used to reduce the internal redundant SAD (Sum of Absolute Difference) operations between the current and the candidate blocks using an accurate dynamic threshold. Second, a Dynamic External Stop Search (DESS) greatly reduces the unnecessary operations by skipping all the irrelevant blocks in the search area. In addition, early search termination and adaptive pattern selections techniques are applied to the proposed MDS as initialization steps to achieve even higher complexity reduction. The accuracy of the proposed model threshold equations guarantee not to fall into a local minima. Experiments show that the proposed MDS algorithm reduces the computations greatly up to 99% and 20% compared with the conventional FS algorithm and DS respectively with no significant degradation in both the PSNR and the bit-rate.