nils-herrmann/clean_scirepeval huggingface dataset:
Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile

Direct VLSI implementation of context-based adaptive variable length coding (CAVLC) for residues, as a modification from conventional run-length coding, will lead to low throughput and utilization. In this paper, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4/spl times/4-blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bitstream. The dual-block-pipelined architecture doubles the throughput and utilization of CAVLC at high bitrates. Moreover, a zero skipping technique is adopted to reduce up to 90% of cycles at low bitrates. Last but not least, exponential-Golomb coding for other general symbols and bitstream encapsulation for network abstraction layer are integrated with CAVLC engine as a complete entropy coder for H.264/AVC baseline profile. Simulation results show that our design is capable of real-time processing for 1920 /spl times/ 1088 30fps videos with 23.6K logic gates at 100MHz.
Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder

is very challenging through the high memory bandwidth and low hardware utilization caused by the new functionalities of variable block size and 6-tap interpolation filter. In this paper, the vertically integrated double Z (VIDZ) schedule, and interpolation window reuse (IWR) and interpolation window classification (IWC) bandwidth reduction schemes are proposed to keep the MC highly utilized and save 60-80% memory bandwidth. The hardware of proposed MC is implemented at 120MHz with 47K logic gates and can support 2048 times 1024 30fps H.264/AVC HDTV decoder with less than 200MB/s memory bandwidth
Evolving technology integration for consumer electronics

Traditionally, the industries are separated into individual segments of consumer electronics, displays, touch panels, lighting, semiconductors, packaging, and so on. In recent years, the consumers' behaviors have changed from the demands of functional commands to intelligent interactions. As a result, industrial research activities have also evolved to the integration of multiple disciplines. In this presentation, we will give overviews of the key technologies in the areas of electronics and optoeletronics in the industries. The topics include advanced roll-to-roll technologies on ultra-thin substrates, touch panels, optical object human interface, OLED lighting, LED lighting, advanced semiconductor technologies, advanced packaging technologies, interface technologies beyond 60 GHz, and technology integration for bio-medical devices. For example, the roll-to-roll technologies on ultra-thin substrates will change the product “design concepts” of consumer electronics. In addition, it is also a revolution of manufacturing technology. It will replace the conventional stationary chamber process with a continuous rolling process. The former requires an environment of high-voltage, high-temperature, and high-vacuum, while the later can be completed in low-voltage, atmosphere pressure, and room temperatures. Another example is the applications of lighting technologies in our daily life with smart phones and digital camera.
A single chip CMOS APS camera with direct frame difference output

A CMOS active pixel sensor with direct frame difference output is reported in this paper. The proposed pixel circuit includes a photodiode and nine transistors and is optimized for low voltage operation. A 128/spl times/96 pixel prototype camera chip with an on-chip 8-bit pipeline ADC was fabricated in a 0.5 /spl mu/m double poly double metal CMOS process. At 3.3 V, the power dissipation is 56 mW.
VLSI architecture design and implementation for TWOFISH block cipher

A novel VLSI architecture of the TWOFISH block cipher is presented. Based on the loop-folding technique combined with efficient hardware mapping, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 /spl mu/m CMOS technology. The chip can achieve an encryption rate of 200 Mb/s and consume 44 mW while operating at a 66 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.
A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications

To provide more vivid perception, TV resolution is increasing dramatically. In addition, 3D video is emerging because it can present immersive and complete scenes. Therefore, multiview video coding (MVC) is currently being developed as an extension of H.264/AVC . Disparity estimation (DE), which effectively exploits the inter-view redundancy and reduces bit rates 20% to 30%, is the most significant feature. However, DE and motion estimation (ME) require ultra-high computation and memory access. To encode a 3-view 1080p video, 82.4TOPS computing power and 54.6TB/s memory access are required with a full search algorithm. Moreover, view scalability is a critical functionality to deal with various MVC structures.
Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor

On-chip implementation of Hilbert-Huang transform (HHT) has great impact to analyze the non-linear and non-stationary biomedical signals on wearable or implantable sensors for the real-time applications. Cubic spline interpolation (CSI) consumes the most computation in HHT, and is the key component for the HHT processor. In tradition, CSI in HHT is usually performed after the collection of a large window of signals, and the long latency violates the realtime requirement of the applications. In this work, we propose to keep processing the incoming signals on-line with small and overlapped data windows without sacrificing the interpolation accuracy. 58% multiplication and 73% division of CSI are saved after the data reuse between the data windows.
H.26L intra mode encoder architecture for digital camera application

In this paper, a still image encoder based on the H.26L intra mode algorithm is proposed and implemented in a FPGA prototype board. H.26L was proposed by ITU-T to provide high compression efficiency for very low bit rate communication. The intra mode in H.26L (H.26Li) uses high level spatial prediction and provides 2 db PSNR gain more than the JPEG standard. It is suitable for still image camera application and can be further extended into video camera application.
Learning-Based Vehicle Detection Using Up-Scaling Schemes and Predictive Frame Pipeline Structures

This paper aims at detecting preceding vehicles in a variety of distance. A sub-region up-scaling scheme significantly raises far distance detection capability. Three frame pipeline structures involving object predictors are explored to further enhance accuracy and efficiency. It claims a 140-meter detecting distance along proposed methodology. 97.1% detection rate with 4.2% false alarm rate is achieved. At last, the benchmark of several learning-based vehicle detection approaches is provided.
An intelligent depth-based obstacle detection system for visually-impaired aid applications

In this paper, we present a robust depth-based obstacle detection system in computer vision. The system aims to assist the visually-impaired in detecting obstacles with distance information for safety. With analysis of the depth map, segmentation and noise elimination are adopted to distinguish different objects according to the related depth information. Obstacle extraction mechanism is proposed to capture obstacles by various object proprieties revealing in the depth map. The proposed system can also be applied to emerging vision-based mobile applications, such as robots, intelligent vehicle navigation, and dynamic surveillance systems. Experimental results demonstrate the proposed system achieves high accuracy. In the indoor environment, the average detection rate is above 96.1%. Even in the outdoor environment or in complete darkness, 93.7% detection rate is achieved on average.
Fast realistic refocusing for sparse light fields

Digital refocusing for sparsely sampled light fields results in aliasing effect. For realistic quality, previous works performed anti-aliasing by applying time-consuming view interpolation for a heuristic number of novel views. In this paper, we study this problem by first performing a spectral analysis to give an analytical rule for the novel view number, which saves 34% of views compared to the intuitional choice. Then we propose a fast refocusing algorithm using a view interpolation method which is about 30x faster than VSRS-1D-Fast. Experimental results show the effectiveness of our approach in terms of speed and quality. For showing realistic refocusing, a light-field wafer-level-optics array is implemented, and its refocused images are compared to pictures captured by a real camera.
Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control

For H.264/AVC decoder system, the motion compensation bandwidth comes from two parts, the reference data loading bandwidth and the equivalent bandwidth from DRAM access overhead latency. In this paper, a bandwidth-efficient cache-based MC architecture is proposed. It exploits both intra-MB and inter-MB data reuse and reduce up to 46% MC bandwidth compared to conventional scheme. To reduce the equivalent bandwidth from DRAM access overhead latency, the DRAM-friendly data mapping and access control scheme are proposed. They can reduce averagely 89.8% of equivalent DRAM access overhead bandwidth. The average MC burst length can be improved to 9.59 words/burst. The total bandwidth reduction can be up to 32∼71% compared to previous works.
Interactive sticker system with Intel RealSense

We present an interactive sticker system, which can detect user's face expression and gesture to stitch the corresponding image to the face or replace the background picture with Intel RealSense depth camera. The proposed system combines both facial expression detection and finger count detection in the same time to realize the respond for expression change and the command that the user gives the camera simultaneously. The proposed system also provides drawing and image saving function, so users can paint directly on the picture by hand and then save the image using a different gesture.
Frame-level data reuse for motion-compensated temporal filtering

Motion-compensated temporal filtering (MCTF) is an open-loop prediction scheme, so the frame-level data reuse for MCTF is possible. In this paper, we propose two general frame-level data reuse schemes which can minimize the memory bandwidth of current and reference frames, respectively. And their relationships between the required memory bandwidth and the number of searching range buffers are also formulated under the constraint of the data dependency in joint scalable video model. Finally, we extend our analysis to pyramid MCTF and the impact of the inter-layer prediction scheme is also considered
iSense3D: A real-time viewpoint-aware 3D video synthesis system

In this paper, a real-time 3D video synthesis system is proposed. The system achieves more real 3D effect by dynamically adapts the synthesized view to user's viewpoint. There are two major parts: 6D viewpoint parameter extraction, and real-time Free-Viewpoint View Synthesis(FVVS). 6D viewpoint parameter extraction is done by 3D object tracking over image and depth. Various techniques for FVVS are proposed and implemented on GPU to achieve real-time. The system is demonstrated on multi-core system with programmable GPU. Real-time performance up to 1280×720p with 30fps is achieved.
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264

Motion estimation can reduce temporal redundancy and achieve high compression capability in video coding standards. In H.264, the coding gain is further improved by variable block-size motion estimation (VBSME). In order to reduce the complexity, many fast algorithms have been proposed. Though previous works can reduce a large amount of computation, most of them are not suitable for hardware implementation and not robust for complex motion videos. A content-adaptive fast algorithm for variable block-size integer motion estimation (VBSIME) is proposed in this paper. Motion activity is exploited to improve the coding efficiency. Because of the good data reuse scheme and simple control flow, the proposed algorithm is applicable to hardware implementation. According to the simulation results, about 98% searching candidates and 86% encoding time are reduced with at most 0.05 dB quality drop in average compared with full search even for complex motion videos.
Reconfigurable platform for content science research

The College of Electrical Engineering and Computer Science at the National Taiwan University has identified the area of content science for media-rich life, broadly construed, as one of core areas for the college's future directions. One major aspect of this project is to develop the enabling technology for reconfigurable platforms for multimedia applications. Specifically, the goal is to develop reconfigurable platforms of system-on-a-chip (SoC) components for the applications to support the needs of multi-modal multimedia contents and to provide rapid system prototyping. The faculties in the College of Electrical Engineering and Computer Science have formed a multi-discipline team to develop such technology. Our team includes seven faculties and more than thirty students from the college. This short report describes the reconfigurable platform for content science research activities currently underway by our team. Our current activities include to develop the technology to analyze the critical path for avoiding hardware contention, to minimize the use of logic components, to design the multimedia IPs, to optimally route the bus and place the logic units, to design energy efficient cache, to evaluate the performance and power consumption, to design the algorithm for temporal floor-planning/placement.
Analysis and reduction of reference frames for motion estimation in MPEG-4 AVC/JVT/H.264

In the new video coding standard, MPEG-4 AVC/JVT/H.264, motion estimation is allowed to use multiple reference frames. The reference software adopts full search scheme, and the increased computation is in proportion to the number of searched reference frames. However, the reduction of prediction residues is highly dependent on the nature of sequences, not on the number of searched frames. In this paper, we present a method to speed up the matching process for multiple reference frames. For each macroblock, we analyze the available information after intra prediction and motion estimation from previous one frame to determine whether it is necessary to search more frames. The information we use includes selected mode, inter prediction residues, intra prediction residues, and motion vectors. Simulation results show that the proposed algorithm can save up to 90% of unnecessary frames while keeping the average miss rate of optimal frames less than 4%.
A Low-power Low-voltage Direct Digital Frequency Synthesizer

A low-power low-voltage direct digital frequency synthesizer is presented in this paper. With the proposed efficient ROM compression method and other ROM reduction techniques, a compression ratio of 236 is achieved. Through low-power techniques at various design levels: low-voltage (2-V) operation, ROM reduction, the proposed parallel architecture, static conventional CMOS gates, and true single phase clocking scheme, an unparalleled power performance is obtained. The final chip is successfully fabricated and guaranteed to function 100% correctly at 62.5 MHz.
An efficient embedded bitstream parsing processor for MPEG-4 video decoding system

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bit-stream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.
A novel video signal processor with reconfigurable pipelined architecture

A programmable 133 MOPS (mega operations per second) processor is designed for video signal processing. It consists of Data-path Processing Part (DPP) and Address Generating Part (AGP). Through a flexible network, the DPP can be efficiently reconfigured as any types of pipelined architecture in terms of video coding algorithms. It is especially suitable to implement irregular algorithms, such as the fast discrete cosine transform (FDCT) and the three-step hierarchical search (3SHS) algorithm for motion estimation. The AGP can generate addresses to perform desired memory access operations for various irregular video coding algorithms. By using this video signal processor (VSP), video processing systems can be easily implemented, and video data can also be smoothly processed in single or multiple VSP configurations. The realization of MPEG-2 is evaluated, and its performance is also presented.
An efficient pipelined VLSI implementation of rank order filter

An efficient pipelined VLSI implementation of rank order filter based on the ordering property is proposed. In the previous works, this filter required many iterations in the bit-serial implementation of the positive Boolean function (PBF) and used a large number of counters, comparators and many AND-OR logic array inputs in a parallel architecture to output an M-th order sample. This limited the real-time applications for large window size. Based on the ordering property of the values of the elements in the m-array, we proposed a pipeline architecture to fold the parallel data flow in order to reduce the hardware complexity without loss of performance. The proposed design can also realize the concurrent search method for the PBF to output an M-th order sample. Compared with previous works, the hardware complexity is reduced from O(2/sup r/) to O(2/sup r/2/) area-time complexity and the latency approaches that of a parallel implementation.<<ETX>>
Analysis of scalable architecture for the embedded block coding in JPEG 2000

In this paper, the scalable architecture of the embedded block coding (EBC) in JPEG 2000, the bit-plane parallel EBC, is proposed. We provided the analysis and an unified design methodology for the bit-plane parallel EBC architecture. To design the bit-plane parallel EBC, there exists three critical difficulties. To overcome the difficulties, three algorithms are proposed. By use of the proposed algorithms, the external bandwidth of the EBC is reduced by 55% averagely, and the throughput of a 4 bit-planes parallel EBC is higher than a word-level EBC with 10 bit-plans parallel by 1.5 times at the bitrate of 1 bits per pixel
Bio-inspired unified model of visual segmentation system for CAPTCHA character recognition

In this paper, we present a bio-inspired unified model to improve the recognition accuracy of character recognition problems for CAPTCHA (completely automated public turing test to tell computers and humans apart). Our study focused on segmenting different CAPTCHA characters to show the importance of visual preprocessing in recognition. Traditional character recognition systems show a low recognition rate for CAPTCHA characters due to their noisy backgrounds and distorted characters. We imitated the human visual attention system to let a recognition system know where to focus on despite the noise. The preprocessed characters were then recognized by an OCR system. For the CAPTHA characters we tested, the overall recognition rate increased from 16.63% to 70.74% after preprocessing. From our experimental results, we found out the importance of preprocessing for character recognition. Also, by imitating the human visual system, a more unified model can be built. The model presented is an instance for a certain type of visual recognition problem and can be generalized to cope with broader domains.
Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC

Weighted prediction (WP) is a tool to compensate the brightness difference in video sequences with brightness variations. In this paper, some weight parameter determination methods are surveyed, and a weighted prediction algorithm together with the hardware architecture design is proposed. The main idea of the algorithm is to limit the number of weight parameters transmitted by quantizing the parameter into levels and using only offset as the parameter. As a result, the extra parameters sent in each slice header is thus limited by the number of levels, and the parameter determination process requires much less computations. By further utilizing sub-sampling of brightness levels and estimated offset sum, a simplified architecture is also proposed. Simulation result shows that the later architecture achieves a coding gain of about 0.5 dB over weighted prediction method in JM9.6 and has a minimum overhead to hardware implementation
128-channel spike sorting processor with a parallel-folding structure in 90nm process

An emerging class of neural prostheses aims to provide more aggressive performance by realizing advanced realtime signal processing algorithms in particular the spike sorting on chips. To support realtime spike sorting for 128 channels, the traditional fully parallel approach duplicating 128 processing units results in a large burden on chip area. The fully folding approach sharing one processor over 128 channels consumes large dynamic power in data caching. We propose to use the parallel-folding structure to optimally tradeoff the area and power. Our 128-channel spike sorting processor consumes 1.36 mm2 area and 1.87 mW power in 90 nm process. 91.1% and 63.4% of the hardware resources (area×power) are reduced compared to the fully parallel and the fully folding approaches respectively.
Low power 2D DCT chip design for wireless multimedia terminals

In this paper, a low power 2-D DCT architecture based on direct 2-D approach is proposed. The direct 2-D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2-D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.