nils-herrmann/clean_scirepeval huggingface dataset:
3D discrete wavelet transform architectures

Compression is a significant operation in many 3D data applications, such as magnetic resonance imaging (MRI), medical diagnosis, television, and seismic data. Employing standard 2D compression techniques do not offer efficient solutions in these applications. In this paper, a 3D discrete wavelet transform (DWT) approach is proposed for performing 3D compression. Two architectures are presented. The first architecture, called 3D-I, is a straight-forward implementation of the 3D DWT. It allows even distribution of the processing load onto 3 sets of filters, with each set doing the calculations for one dimension. The filters are easily scalable to a larger size. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. The design is cascadable. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The second proposed architecture, 3D-II, uses block inputs to reduce the amount of on-chip memory. It has a control unit to select which coefficients to pass on to the low and high pass filters. The RAM on the chip is small compared to the input size, since it depends solely on the filter sizes. The filters are parallel, since systolic filters assume that the data is fed in a non-block form such that partial calculations are done.
A slice of a brain: a hybrid neural chip set

This paper proposes a complete self-contained chip set for ANN systems based on a back-propagation model with full-connectivity topology and on-chip learning and refreshing. We believe that our proposal is the first to offer fully hardware-supported on-board learning in continuous analog mode. Another unique novel feature of our 2-chip set design is that it does not require any other supporting chips of any kind and is capable of growing to any arbitrarily large size. Interface and communications with host and/or real-world systems is done via the direct analog and digital I/O ports which allow real-time computations. A representative system of 1 layer with 100 K analog synapses would require 100 SynChips and 20 NeuChips and expected to fill the entire surface of a whole wafer. Such a system which acquires an I/O port of up to 12800 digital bits or 3200 analog channels runs in absolute parallelism and would sustain a performance of 940x10/sup 12/ CPS. Larger systems may be constructed with several wafers.
On the design of low-energy hybrid CMOS 1-bit full adder cells

We present several designs for 1-bit full adder cell featuring hybrid CMOS logic style. These designs are based on a novel XOR-XNOR circuit that simultaneously produces XOR and XNOR full-swing outputs and outperforms its best counterpart showing 39% improvement in PDP. The new full-adder designs are also categorized in three main categories depending upon the implementation of the logic expression for sum and carry outputs. The results show that all the proposed designs prove to be energy-efficient and outperform several standard full-adder designs. All the designs are able to operate at low voltages without significant loss in signal integrity. The improvement in terms of PDP obtained by the best full-adder cell as compared the best standard design amounts to 24%.
A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio

This paper presents a low power 4-bit ADC for sub-GHz ultra wideband (UWB) receivers. The power efficiency is achieved by taking advantage of the low duty cycle feature of UWB impulse. After the synchronization is achieved, the burst-mode sampling approach is employed to avoid unnecessary operations. So, the ADC only samples at the time when a pulse is expected and stays in standby during the rest of the time. The proposed burst sampling ADC employs five interleaved pipeline flash ADCs controlled by a low duty cycle 25 MHz sampling clock with five different phases. The resistor ladder reference circuit is eliminated by using a modified quantum voltage comparator, which can generate the reference voltages internally. The proposed ADC has been designed and simulated by using TSMC 0.0mum CMOS process. Simulation results show that the proposed 4-bit ADC can operate at 1G sample/s for UWB impulse with power consumption of 7.6 mW.
NEDA: a low-power high-performance DCT architecture

Conventional distributed arithmetic (DA) is popular in application-specific integrated circuit (ASIC) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed, aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in digital signal processing (DSP) applications. Mathematical analysis proves that DA can implement inner product of vectors in the form of two's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative studies show that NEDA outperforms widely used approaches such as multiply/accumulate (MAC) and DA in many aspects. Being a high-speed architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architectures for 8 /spl times/ 8 discrete cosine transform (DCT) core are presented as an example. Savings exceeding 88% are achieved, when the compression scheme is applied along with NEDA. Finite word-length simulations demonstrate the viability and excellent performance of NEDA.
A novel high-performance CMOS 1-bit full-adder cell

A novel 16-transistor CMOS 1-bit full-adder cell is proposed. It uses the low-power designs of the XOR and XNOR gates, pass transistors, and transmission gates. The cell offers higher speed and lower power consumption than standard implementations of the 1-bit full-adder cell. Eliminating an inverter from the critical path accounts for its high speed, while reducing the number and magnitude of the cell capacitances, in addition to eliminating the short circuit power component, account for its low power consumption. Simulation results comparing the proposed cell to the standard implementations show its superiority. Different circuit structures and input patterns are used for simulation. Energy savings up to 30% are achieved.
A scalable analog architecture for neural networks with on-chip learning and refreshing

This paper discusses various techniques for analog storage and handling and proposes a new class of architecture suitable for modular and scalable analog neural networks with on-chip learning and refreshing. The new architecture is based on analog functional blocks and analog pass switches which enhance the system versatility. Supporting algorithms are also developed. A novel characteristic is the full-analog on-chip learning methodology which substantially increases the learning speed. The speedup is evidenced by the utilization of local analog synaptic updating scheme which utterly eliminates time-sharing components. Moreover, this localization scheme conceives unbounded scalability in this neural architecture.
Low Power Lookup Tables for Huffman Decoding

Mobile video devices are energy constrained and therefore need to contain circuits that consume a minimum amount of energy. In this paper, different architectures of lookup tables for Huffman decoding are studied. The PLA type structure is common in these Huffman lookup tables because of their speed and simplicity advantage. However, we determine that the tree structure for table lookup can be a lower power alternative than a PLA structure in certain situations. These situations accounted for 56% of our total simulations runs, and of these runs, the average power savings of the tree in those situations was 78%. Another goal of this paper is to show the effects of varying the table size and varying the probability distributions of a table on power, area, and delay.
Toward fast low power adaptive spike sorting VLSI chip design for wireless BCI implants

Recently, controlling the surrounding world by just the power of our thoughts has become a reality using Brain Computer/Machine Interface (BCI/BMI). Enabling handicap people to control artificial limbs is one of the most important goals of BCI. There are challenges in providing the usability of BCI implants because most of the BCI sensors are non-practical or increases the infection hazard to the patients. Some research proposed wireless implants that do not require chronic wound in the skull. However, in such cases, the communications consume much power via a slow and complex arithmetic unit, high power and bandwidth that exceeds the allowed limits . This study proposes and implements a neural based real-time spike sorting technique for wireless BCI that is faster and simpler than the existing designs, which was achieved by simplifying the computational units, restricting fixed point architecture and involving an adaptive immune system structure based behavior; which makes the design also power and area efficient. The system was implemented, and simulated using Modalism and Cadence.
A novel ultra-low-energy bulk dynamic threshold PMOS scheme

In this paper we introduce a new dynamic threshold MOSFET scheme for PMOS transistors in bulk-CMOS technology. The proposed scheme can be applied to subthreshold dynamic and static circuits. The proposed scheme is shown to have 54% saving in energy if compared to the regular subthreshold DTPMOS scheme, which makes it attractive for ultra-low-energy moderate-performance devices. The proposed scheme is also shown to be more robust against temperature variations.
Minimum-area shield insertion for explicit inductive noise reduction

With high clock frequencies, faster transistor rise/fall time, long signal wires, and the use of wider wires and Cu material interconnects, the interconnect inductance, and the noise generated because of this inductance, is becoming an important design metric in digital circuits. For a risk-free layout solution of a chip, capacitive and inductive noises should be considered at various routing process stages. A formulation and efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The noise model used can handle different wire widths, different spacing among wires, and different wire lengths. The model also is aware of the skin effect in high frequency ranges. Experimental results show that the proposed approach gives minimum number of shields to satisfy the noise constraints and uses less runtime than the best alternative approach.
A scalable architecture for 2-D discrete wavelet transform

We propose an efficient and simple systolic-like architecture for VLSI implementation of a 2-D discrete wavelet transform (DWT). The "approximation" and "detailed" components of a signal are computed simultaneously in the first octave and alternately in the other octave(s). Each processing element has its own local memory for storing intermediate data and minimum routing requirement limited only to its neighbors. The proposed architecture uses the same clock frequency for every octave level and has a 100% utilization for j=2 architecture, and N/sup 2/+N period cycle. The architecture is scalable for different filter lengths (divisible by 2) and different octave levels.
MAC-SCC: medium access control with a separate control channel for multihop wireless networks

The recent research has shown that the basic RTS/CTS approach is not efficient in multihop wireless networks. In this paper, we propose a novel medium access control protocol with a separate control channel (MAC-SCC). A distinct feature of MAC-SCC (compared with other multichannel MAC protocols) is to use two Network Allocation Vectors (NAVs) for the data channel and the control channel, respectively. The transmission of the next data frame can be pre-determined during the current transmission via the separate control channel, and thus the frame collision probability and bandwidth wasted during backoff can be reduced. The system throughput is quantified via simulation. The results show that MAC-SCC yields a throughput gain up to 60% under high traffic load and has a significant lower link failure probability.
Power analysis of the Huffman decoding tree

A power analysis of the Huffman decoding tree for variable length decoding is presented. Leakage power is shown to be the primary component for large table sizes, while dynamic power has a role in smaller table sizes. Area increases nearly linearly with increasing table size, regardless of the probabilities of the symbols for a given table size, while the delay depends more on the probabilities. Although delay of the tree can be larger than other table lookup types, it is acceptable for mobile devices in order to reduce power.
A low power VLSI architecture for mesh-based video motion tracking

This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the video object. The architecture consists of motion estimation and motion compensation units. The motion estimation architecture generates a progressive mesh code and the motion vectors of the mesh nodes. It reduces the power consumption, uses a simpler approach for mesh construction, approximates the mesh nodes motion vector by using the three step search algorithm and uses a parallel motion estimation core to evaluate the mesh nodes motion vectors. Moreover, it maximizes the lifetime of the internal buffers. The motion compensation architecture uses a multiplication-free algorithm for affine transformation, which significantly reduces the complexity of the motion compensation architecture. Moreover, using pipelined affine units contributes to the power savings. The video motion compensation architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. The performance analysis shows that this processor can be used in online object-based video applications such as in MPEG and VRML.
Fault tolerant techniques for TSV-based interconnects in 3-D ICs

TSV-based 3-D IC is one of the most promising approach in modern integrated circuit design. As TSV enables the integration of different dies with different technologies, it is considered as one of the key elements in IC design. Reliability of TSV is an important issue which needs to be addressed very carefully since a faulty TSV can result in the failure of the whole stack. TSV open defect alongside TSV short are the most prevalent faults in 3-D ICs. They can happen during TSV filling, bonding process or as a result of aging due to Electromigration. In this paper, we present two methods for reducing the amount of delay caused by a partially open TSV and TSV short defect in 3D-ICs. Simulation results demonstrate the effectiveness of the proposed method in improving the performance of 3-D ICs in presence of partially open and short TSV defects.
VLSI Architectures for JPEG 2000 EBCOT

EBCOT tier-1, as entropy encoder of JPEG 2000, is a huge time-consuming part (typically more than 50%) and is considered a bottleneck for the entire system. In this paper, EBCOT tier-1 algorithm, including serial coding mode and parallel coding mode, is introduced. The VLSI architectures for EBCOT tier-1 can be divided into two categories: parallel bit-plane coding scheme (ParaBCS), where all bit-planes in a code block are coded in parallel, and serial bit-plane coding scheme (SeriBCS), where all bit-planes in a code-block are coded in serial. These two schemes are compared in terms of system throughput, PSNR performance, power consumption, and memory size. Finally, two case studies (one is based on SeriBCS and the other is based on ParaBCS) are presented.
Efficient high speed lattice-CORDIC IFFT architecture for DMT transmitter

The Discrete MultiTone (DMT) modulation/demodulation technique plays an important role in data transmission. The main bottleneck of the DMT scheme is its high computational complexity due to the large block size of the IFFT/FFT. In this paper an efficient fast IFFT architecture is proposed to accelerate the operation of the DMT technique. The proposed architecture achieves approximately 58%, 39%, and 50% reductions in gate count, power consumption, and area compared to the conventional state of the art pipelined IFFT generators. Implementation and Simulation results project that the proposed IFFT architecture can perform data transmission at 118 MHz.
Multi-Path Search Algorithm for Block-Based Motion Estimation

Block-based motion estimation algorithms are widely adopted by video coding standards due to their simplicity and good distortion performance. Amongst these, pattern based search algorithms are very popular. The basic assumption made by these algorithms is that there exists a unimodal error surface within the search window. As seen in real world video sequences, this is far from reality and the algorithms often get stuck in local minimums yielding sub-optimal results. We propose a multi-path search (MPS) algorithm that utilizes more than one path to find the absolute minima. Wrong search paths are avoided early resulting in faster search. Better motion vectors are estimated increasing the video quality, consequently reducing the bitrate requirement. MPS algorithm offers flexibility and robustness with better speed and quality. Results show that a speedup of upto 34% is achieved with slight increase in PSNR as compared to its best competitor. When compared to full search, the proposed algorithm looses only 0.1%~2% in PSNR while saving 92%~95% computations.
Algorithm-based low-power VLSI architecture for 2D mesh video-object motion tracking

The new VLSI architecture for video object (VO) motion tracking uses a novel hierarchical adaptive structured mesh topology. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the VO. Motion compensation is performed using a multiplication-free algorithm for affine transformation, significantly reducing the decoder architecture complexity. Pipelining the affine unit contributes a considerable power saving. The VO motion-tracking architecture is based on a new algorithm. It consists of two main parts: a video object motion-estimation unit (VOME) and a video object motion-compensation unit (VOMC). The VOME processes two consequent frames to generate a hierarchical adaptive structured mesh and the motion vectors of the mesh nodes. It implements parallel block matching motion-estimation units to optimize the latency. The VOMC processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion-compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. Performance analysis shows that this processor can be used in online object-based video applications such as MPEG-4 and VRML.
Green energy solution for femtocell power control in massive deployments

Mobile data traffic has skyrocketed in recent years and will continue to grow and demand more capacity. Continued heterogeneous networks' evolution and the utilization of massive Femtocell deployments will facilitate the meeting of capacity demands as expected towards 5G and telecom 2020-vision. The CO2 footprint of power usage is becoming spotlighted and energy-aware solutions are required.  Femtocell downlink power control frameworks and proposes a novel comprehensive one taking into consideration issues like intra-interference (Femto-Femto), dense-deployments and environmental impact. Simulation results show up to 68% user throughput improvement and up to 20.69kg/year CO2-emission reduction for one Femtocell.
Application of compressed sensing in wideband cognitive radios when sparsity is unknown

We present a novel solution for wideband spectrum sensing when the sparsity of the sensed signal or the occupation rate of the frequency band of interest is unknown. Moreover, the proposed method offers the first solution to sense the frequency band of interest when almost fully occupied. Generally, our method employs compressed sensing to acquire the received signal at sub-Nyquist rates. Then, the sum (or the average) of the frequency spectra per each frequency subband is estimated using least squares optimization where the sparsity is assumed as the total number of frequency subbands. Moreover, a detection criterion is formulated. A reduction in the design complexity of the sampling stage as well as the computational complexity of the recovery stage is achieved compared to compressive wideband spectrum sensing methods including the sequential compressed sensing method.
Router-level performance driven dynamic management in hierarchical networks-on-chip

When on-chip interconnection network scales to integrate more processing elements, the average end-to-end latency is highly increased due to long average hop distance. Though it has been discovered that, almost of the communication in large scale networks is between nodes in a short range, it revealed that the small portion of data delivery between distant nodes consumes or occupies most of the network bandwidth. Hierarchical NoCs caters an attractive solution to resolve the distant data transmission problem by taking advantage of the network hierarchy. However, it brings about new sever congestion challenge because of uneven traffic distribution among hierarchy. In previous work, we performed a detouring scheme on a layered hierarchical NoC. When congestion is formed on the access link to adjacent hierarchical layer, the detouring scheme seeks and reroutes the packets to an nearby node to access the next adjacent network layer. It revealed that the links, which bridges the packets up to higher layers, are more essential for distributing the traffic and avoiding congestion between hierarchy levels. In this paper, we proposed dynamic schemes to solve the congestion problem introduced by region-based hierarchical routing on a hierarchical NoC. The results exposed that the dynamic approaches are efficient to manage the congestion under heavier long range traffic load, yielding significant average network latency reduction and throughput increment under mixed synthetic traffic patterns.