nils-herrmann/clean_scirepeval huggingface dataset:
Efficient message reduction algorithm for stereo matching using belief propagation

Belief propagation (BP) is a popular global optimization technique in computer vision. However, it requires huge bandwidth and memory in hardware implementation because it iteratively processes messages between the neighboring nodes. In this paper, we propose an efficient message reduction algorithm that greatly reduces the bandwidth and memory consumption. Compared with the original message passing operation, we successfully reduce the memory and bandwidth with similar quality. For stereo matching of a VGA input where the disparity range is 64, the proposed algorithm can achieve 93.75% message memory reduction with about only 0.2–2.2% bad pixels quality degradation. The proposed algorithm greatly reduces the memory requirement and is suitable both for hardware and software realization.
A programmable VLSI architecture for 2-D discrete wavelet transform

Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy to extend. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform and the mirror-extension is realized via the routing network. This design has been implemented and fabricated in a 0.35 /spl mu/m 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 /spl mu/m/spl  /spl mu/m. For a 256/spl times/256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. Hence the proposed architecture is suitable for real-time applications such as JPEG 2000.
Multichannel evoked neural signal compression using advanced video compression algorithm

Multichannel neural recording is one of the most important topics in the field of biomedical engineering. This is because there is a need to considerably reduce large amounts of data without degrading the data quality for easy transfer through wireless transmission. Video compression technology is of considerable importance in the field of signal processing. There are many similarities between multichannel neural signals and video signals. In this study, we propose a signal compression method that employs motion vectors (MVs) to reduce the redundancy between successive video frames and between successive channels. The method shows a signal-to-noise (error) ratio (SNR) of 25 db and data are compressed to 5% of their original size.
Efficient hybrid tree/linear array architectures for block-matching motion estimation algorithms

Execution latency and I/O bandwidth play essential roles in determining the effectiveness and the cost of a parallel hardware implementation for block-matching motion estimation algorithms. Unfortunately, almost all traditional architecture designs, e.g. the two-dimensional mesh-connected systolic array architecture (2DMCSA), and the tree-type structure (TTS), fail to take these two factors into account simultaneously. As a result, they suffer from either large execution latency or huge input bandwidth requirements. The authors propose a family of tree/linear architectures, which efficiently optimise the total implementation cost by combining the merits of the 2DMCSA and the TTS. Moreover, to facilitate hardware designs, the authors present the tree-cut techniques and the on-chip buffer design method to meet computational demands of various video compression applications. Since the proposed architectures are capable of executing the exhaustive search and the fast search block-matching algorithms, they offer relatively flexible and cost-effective hardware solutions for a wide range of video coding systems, including CD-ROM, portable visual communications systems and high-definition TV.
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding

This paper presents a hardware-efficient architecture of tree-depth scanning (TDS) and multiple-quantization (MQ) scheme for MPEC-4 still texture coding. By means of the novel architecture, the TDS can achieve its maximal throughput to area ratio and minimal external memory access with only one wavelet-tree size on-chip memory. Besides, MQ adopts the proposed POT (power of 2) quantization, which is proved to have very similar performance to generic (user-defined coefficients) scalar quantization, to achieve the most cost-effective hardware implementation. The prototyping chip has been implemented in a TSMC 0.35 /spl mu/m CMOS technology. This architecture can handle 30 4-CIF frames per second with 5 spatial layers and 3 SNR layers scalability at 100 MHz clock frequency.
Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors

This paper describes an efficient motion estimation algorithm, the predictive line search (PLS), for real-time implementations of MPEG-4 encoder on multimedia processors. The motion-vector predictor is used as the starting point in the search process because the correlation between neighboring motion vectors is strong. The line search pattern is used in the proposed algorithm to reduce the memory access as well as to exploit the special multimedia processor instructions for sum of absolute difference calculations. Experimental results show that the performance of the PLS is very close to that of the full-search (FS) algorithm. Compared with the well-known diamond search and one-dimensional FS, the PLS shows better performance and robustness, especially for high motion sequences. A prototype MPEG-4 encoding system is implemented on a 216-MHz multimedia processor with very long instruction word architecture to verify the effectiveness of the PLS. Real-time encoding of MPEG-4 Simple Profile Level 3 (CIF, 30 fps) can be achieved with only 57% of the processor load.
Simple online and realtime tracking with spherical panoramic camera

In this paper, a simple yet effective method for online and real-time multi-object tracking (MOT) in 360-degree equi-rectangular panoramic videos is proposed. Based on the current state-of-the-art tracking-by-detection paradigm, several improvements have been made to overcome the challenges of full field-of-view (FOV) of Spherical Panoramic Camera (SPC). In addition, two datasets are presented for evaluation. It is shown that the proposed method outperforms the baseline by 28.6% and 27.8% in terms of average Multiple Object Tracking Accuracy (MOTA) on each dataset.
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications

3DTV promises to become the mainstream of next-generation TV systems. Highresolution 3DTV provides users with a vivid watching experience. Moreover, free-viewpoint view synthesis (FVVS) extends the common two-view stereo 3D vision into virtual reality by generating unlimited views from any desired viewpoint. In the next-generation 3DTV systems, the set-top box (STB) SoC requires both a high-definition (HD) multiview video-coding (MVC) decoder to reconstruct the real camera-captured scenes and a free-viewpoint view synthesizer to generate the virtual scenes [1–2].
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method

In this paper, by using line-based methods, a generic RAM-based architecture is proposed to construct the corresponding two-dimensional architectures efficiently for any given hardware architecture of one-dimensional wavelet filters, including conventional convolution-based and advanced lifting-based architectures. The categories of line buffer and the strategy to optimize the size of internal memory are also described. For multi-level two-dimensional discrete wavelet transforms, the recursive pyramid algorithm is adopted to turn our proposed architecture into another efficient architecture. According to the comparison results, the proposed architecture outperforms previous arts in the aspects of memory size, control complexity, and flexibility.
A real-time video signal processing chip

A real-time video signal processing chip for video data compression which combines block truncation coding (BTC) and a conventional motion compensation (MC) algorithm is presented. The regularity and simplicity of the BTC algorithm strongly suggest that it is quite suitable for an efficient VLSI implementation. It is shown that the proposed BTC-based system is much better than the conventional system in terms of implementation, complexity, and accuracy. Two benchmark sequences are used as test examples. The clock rate of the designed chip is about 47 MHz, which is suitable for most video applications.
Graphical block-diagram based programming environment for a DSP silicon compiler

The paper presents a graphical blockdiagram based programming tool, which is a new software development system for digital signal processing (DSP). This system provides a blockdiagram editor; therefore, the DSP system can be easily built by connecting functional blocks as described in the signal-flow graph. A block library is set up, which includes basic signal processing functions and some frequently used high level signal processing functions like FIR, IIR, FFT, etc. A friendly graphic user interface (GUI) based on the ‘X-Window’ system is developed to support each design step. Users can then improve their design easily according to the GUI's response. To guarantee the correctness of the circuits designed, the debugging and verifying capabilities are embedded in our system. The full system is combined with a structural silicon compiler, which we developed previously. Several designs will be illustrated as examples. It has been shown that this tool will be suitable for DSP system design by using a silicon compiler
Hardware-Efficient Belief Propagation

Loopy belief propagation (BP) is an effective solution for assigning labels to the nodes of a graphical model such as the Markov random field (MRF), but it requires high memory, bandwidth, and computational costs. Furthermore, the iterative, pixel-wise, and sequential operations of BP make it difficult to parallelize the computation. In this paper, we propose two techniques to address these issues. The first technique is a new message passing scheme named tile-based BP that reduces the memory and bandwidth to a fraction of the ordinary BP algorithms without performance degradation by splitting the MRF into many tiles and only storing the messages across the neighboring tiles. The tile-wise processing also enables data reuse and pipeline, resulting in efficient hardware implementation. The second technique is an O(L) fast message construction algorithm that exploits the properties of robust functions for parallelization. We apply these two techniques to a very large-scale integration circuit for stereo matching that generates high-resolution disparity maps in near real-time. We also implement the proposed schemes on graphics processing unit (GPU) which is four-time faster than standard BP on GPU.
Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysis

A new SoC architecture for multimedia content analysis is implemented with 16mm2 area in 90nm CMOS technology. It focuses on the co-acceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements are integrated to achieve tera-scale performance. In the dual processor architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. The power efficiency of the proposed machine learning SoC is 1.7 TOPS/W, and the area efficiency is 81.3 GOPS/mm2.
A pseudo-object-oriented very low bit-rate video coding system with cache VQ for detail compensation

A pseudo object-oriented video coding system is proposed and implemented. In order to increase the coding efficiency, a cache VQ algorithm is suggested to further compress those areas where motion estimation fails. According to our primary simulation results, the visual quality of long-timed sequences is still acceptable even for bit-rates below 10 kbps. In addition to the high compression ratio for very low bit-rates, content-based applications are also expected since the proposed system utilizes the segmented motion field; furthermore, the occurrences of prediction errors generally locate at emotionally important parts, e.g. eyes and mouth, etc. All the coded components are not only useful for compression but also meaningful for video recognition.
A novel 2Dd-to-3D conversion system using edge information

Although three-dimensional (3D) displays enhance visual quality more than two-dimensional (2D) displays do, the depth information required for 3D displays is unavailable in the conventional 2D content. Therefore, converting 2D videos into 3D ones has become an important issue in emerging 3D applications. This work presents a novel algorithm that automatically converts 2D videos into 3D ones. The proposed algorithm utilizes the edge information to segment the image into object groups. A depth map is then assigned based on a hypothesized depth gradient model. Next, the depth map is block-based assigned by cooperating with a cross bilateral filter to generate visually comfortable depth maps efficiently and also diminish the block artifacts. A multiview video can be readily generated by using a depth image-based rendering method.
Application layer error correction scheme for video header protection on wireless network

In wireless video streaming application, video information may be corrupted by a noisy channel. By introducing error resilience and error concealment techniques, many researchers have tried to eliminate quality degradation of reconstructed picture in decoding a corrupted data. On the contrary, there are relatively fewer works discussing the ways to diminish the corruption. Hence, system designers need to use different methods to restrict the error cause by channel within a tolerable extent. In other words, the system will be difficult to be implemented in practical design. In this paper, we propose a way to protect the video header information in application layer without modifying standardized syntax. Beside, we also consider channel condition of wireless transmission and propose a way to reduce redundant bits used in channel coding. By doing this, the bitstream can be simply transmitted over practical wireless network and the reconstructed picture quality outperforms the original one.
Fast belief propagation process element for high-quality stereo estimation

Belief propagation is a popular global optimization technique for many computer vision problems. However, it requires extensive computation due to the iterative message passing operations. In this paper, we present a new process element (PE) for efficient message construction. The efficiency is gained by exploiting the unique characteristics of the generalized Potts model (truncated linear mode) of the smoothness term in the Markov random field. For stereo estimation with L disparity values, the algorithm successfully reduces the computation from O(L2) to O(L) and retains the high throughput and low latency. Compared with the direct message construction PE, our method achieves 87.14% computation saving and a 94.38% PE area reduction.
Accurate and Bandwidth Efficient Architecture for CNN-based Full-HD Super-Resolution

CNN-based super-resolution methods achieve great performance but come with high bandwidth requirements. This paper proposes a bandwidth efficient CNN-based architecture for super resolution supporting up to Full HD images at 60 fps. The bandwidth efficiency is achieved by layer fusion with data reuse scheduling and dynamic quantization. To maintain a high utilization of processing elements, the deconvolution operation is decomposed into a several convolution operations. The proposed architecture provides a 94.8 % bandwidth reduction. Compared to the software implementation, less than 1 % performance drop is induced in this VLSI implementation. The enables the proposed architecture to obtain state-of-the-art accuracy compared to existing super-resolution hardware implementations.
Error recovery for MPEG-4 shape and texture information

In this paper, a new error concealment algorithm is proposed to repair damaged portions of the shape information and texture information. Based on the least squares estimation method, the proposed algorithm can find the most similar block to replace the damaged block without worrying about the rotation, movement, or some luminance change between two sequential images. From the experimental results, the proposed algorithm achieves better performance than previous works, especially in the case where the damaged portion includes the object edge.
Smart display: A mobile self-adaptive projector-camera system

Owing to the diversity of projection surfaces, an effective mobile display system must be adaptive to the surface to avoid introducing a clipped scene. In this paper, we propose a smart mobile display system which automatically adapts to the location and motion of a surface. Firstly, an imperceptible structured light technique is adopted and continuous adaptation is accomplished. Secondly, a specifically designed code image with high distortion tolerance is proposed. Thirdly, we present a priority-based correction method to revise previous decoding results. Finally, a matching procedure resisting noise interruption is introduced. The system achieves 95% correct rate under the common indoor illuminance. In addition, the system performance is independent of the projected content and the surface shapes.
The arbitrarily shaped transform of segmented motion field for a pseudo object-oriented very low bit-rate video coding system

The arbitrarily shaped transform (AST) of the segmented motion field generated by modified optical flow algorithm (MOFA) is suggested in this paper. Because the transform kernels are dependent on the shape of the coded region, information about the contours of the objects must be transmitted. To achieve data compression, a coefficient selection function (CSF) is defined for AST coefficients reduction. Since shape information data intensive, a rectangle approximation method is also developed. According to the simulation results, the proposed coding method is efficient and its performance is much better than the traditional block matching algorithm in terms of PSNR and bit-rate. In addition, the proposed algorithms are integrated together to build a very low bit-rate video coding system. From some primary simulations of the system, the proposed method can guarantee 34 dB PSNR for most cases at around 10 kbps; furthermore, the segmentation of objects has potential for object scalability.
Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation

Digital refocusing has a tradeoff between complexity and quality when using sparsely sampled light fields for lowstorage applications. In this paper, we propose a fast physically correct refocusing algorithm to address this issue in a twofold way. First, view interpolation is adopted to provide photorealistic quality at infocus-defocus hybrid boundaries. Regarding its conventional high complexity, we devised a fast line-scan method specifically for refocusing, and its 1D kernel can be 30× faster than the benchmark View Synthesis Reference Software (VSRS)1D-Fast. Second, we propose a block-based multi-rate processing flow for accelerating purely infocused or defocused regions, and a further 3-34× speedup can be achieved for high-resolution images. All candidate blocks of variable sizes can interpolate different numbers of rendered views and perform refocusing in different subsampled layers. To avoid visible aliasing and block artifacts, we determine these parameters and the simulated aperture filter through a localized filter response analysis using defocus blur statistics. The final quadtree block partitions are then optimized in terms of computation time. Extensive experimental results are provided to show superior refocusing quality and fast computation speed. In particular, the run time is comparable with the conventional single-image blurring, which causes serious boundary artifacts.
A new error concealment algorithm for H.264 video transmission

In this paper, a new error concealment algorithm for the new coding standard H.264 is presented. The algorithm consists of a block size determination step to determine the size type of the lost block and a motion vector recovery step to find the lost motion vector from multiple reference frames. The main feature of this algorithm are as follows. In the block size determination step, we propose a criterion to determine the size type of the lost block from the current frame. In the motion vector recovery step, the optimal motion vector for the lost block chosen from multiple previous reference frames with the minimum value of the side match distortion. The proposed algorithm not only can determine the most correct mode for the lost block, but also can save much more computation time for motion vector recovery. Experimental results show that the proposed algorithm achieves 0.4/spl sim/7 dB improvement over the conventional VM method.
Design and implementation of cubic spline interpolation for spike sorting microsystems

Accurate spike sorting is important for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend. The compromise on sorting accuracy is usually made for the low power consumption with a lower SR. In this paper, the VLSI architecture of cubic spline interpolation is proposed to improve the power-accuracy tradeoff for the spike sorting microsystems. The window-based interpolation schedule, event-triggered processing, and two-step interpolation scheme are applied to save the memory and computation. 0.04 µW/channel is finally achieved after the implementation in 90nm process.
A VLSI architecture for radix-2/sup k/ Viterbi decoding with transpose algorithm

The paper presents a novel transpose path metric (TPM) algorithm to reduce the interconnection routing complexity for a radix-2/sup k/ Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rearrangement in a transpose strategy. With features of modulation and regularity, this algorithm is very suitable for VLSI implementation; consequently, a larger memory length VA decoder can be constructed with several smaller memory length modules. Finally, a VLSI architecture for a 16-states radix-4 VA decoder using TPM has been developed.
A real-time augmented view synthesis system for transparent car pillars

In this paper, a real-time augmented view synthesis system is proposed. With real-time consideration and augmented reality property, the proposed system provides a novel application for making car pillars transparent to enlarge the eyesight of the drivers. Thanks to the proposed trinocular depth estimation, online depth generation becomes possible through trinocular fast dense disparity estimation. With the proposed texture mapping free viewpoint depth image based rendering on the GPU, the processing speed for view interpolation achieves real-time. The computational power doesn't cost much so that this real-time system is achievable on common computers. The experimental results show that the proposed system is able to project view synthesized video which is integrated with the background to make the user perceive seamless outside scene inside their car.