nils-herrmann/clean_scirepeval huggingface dataset:
Six-dimensional free-viewpoint synthesis flow for QFHD free-viewpoint/multiview 3DTV applications

Multiview video (MVV) can provide viewers a complete 3D perception by its multiple-viewpoint feature. In order to support smooth viewpoint switching, virtual view synthesis is required. However the ultra high computational complexity and the system memory bandwidth requirement make the real-time multiview applications difficult. For the quad full-HD (QFHD) specification, 31.5GByte/Sec is needed for every virtual view. Furthermore, the conventional line buffer based or block based data scheduling cannot support the various geometries required in the virtual view synthesis. In the paper, a six-dimensional free-viewpoint view synthesis flow is proposed. By the proposed texture reorder and inverse reorder data interface, the on-chip data scheduling can be done under the conventional block pipelining even with different geometries. After integrating the proposed bandwidth reduction schemes, including the dynamic warping reference frame selection and on-chip texture buffer optimization, 95.7% system memory bandwidth is saved. Comparing with the previous 1D-horizontal-shifting-based 3DTV chips, the proposed scheduling provides full geometries including translations and rotations in the 3D space.
VLSI architecture of leading eigenvector generation for on-chip principal component analysis spike sorting system.

On-chip spike detection and principal component analysis (PCA) sorting hardware in an integrated multi-channel neural recording system is highly desired to ease the bandwidth bottleneck from high-density microelectrode array implanted in the cortex. In this paper, we propose the first leading eigenvector generator, the key hardware module of PCA, to enable the whole framework. Based on the iterative eigenvector distilling algorithm, the proposed flipped structure enables the low cost and low power implementation by discarding the division and square root hardware units. Further, the proposed adaptive level shifting scheme optimizes the accuracy and area trade off by dynamically increasing the quantization parameter according to the signal level.With the specification of four principal components/channel, 32 samples/spike, and nine bits/sample, the proposed hardware can train 312 channels per minute with 1MHz operation frequency. 0.13 mm(2) silicon area and 282microW power consumption are required in 90 nm 1P9M CMOS process.
Single iteration view interpolation for multiview video applications

Multiview video can bring the 3D and virtual reality perceptual experience to users by its multiple view point characteristic. To support the smooth and free view point switching, both matrix-based depth image based rendering and the complex virtual view interpolation schemes are required. In order to reduce the high computation complexity and avoid the iterative processing scheduling in conventional view interpolation flows, a single iteration view interpolation algorithm is proposed. By use of the proposed algorithm, the redundant warping operations are reduced by 86%. In addition, based on the proposed artifact detecting and removing algorithm, artifacts due to imperfect depth maps can be detected and eliminated at the same time. Therefore, no additional post-processing or iteration is required and the single iteration processing is achieved.
Channel selection for epilepsy seizure prediction method based on machine learning

The studies on seizure prediction problem have shown great improvement these years. Machine learning based seizure prediction method shows great performance by doing pattern recognition on high-dimensional bivariate synchronization features. However, the computation loading of the machine learning based method may be too high to meet wearable or implantable devices with the power and area constraints. In this work, channel selection is proposed to reduce the channel number from 22 to less than 6 channels and therefore more than 93.73% of the computation loading is saved through the method. The best result shows successful rate of 60.6% in 3-channel cases of ECoG database and successful rate of 70% in 3-channel cases of EEG database.
Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264

Transform coding has been widely used in video coding standards. In this paper, a hardware architecture for accelerating transform coding operations in MPEG-4 AVC/H.264 is presented. This architecture calculates 4 inputs in parallel by fast algorithms described previously. The transpose operations are implemented by a register array with directional transfers. This architecture has been mapped into a 4 /spl times/ 4 multiple transforms unit and synthesized in TSMC 0.35um technology. The multiple transform processor can process 320M pixels/sec at 80Mhz for all 4 /spl times/ 4 transforms used in MPEG-4 AVC/ H.264.
Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces

Brain computer interface based on Electroencephalogram can be used to control the external devices through the motor imagery, and may be the next-generation user computer interface. However, this system requires a significant amount of data for the supervised algorithm training. The collection of training data is time-consuming, which may impede the usage in the daily life. In this paper, the trade-off between the training data size and algorithm accuracy is first analyzed. Then the reusing of the generalized pre-recorded training data set is explored to further improve this trade off. According to the simulation results, 63.8% training data collection time can first be saved with only 3% accuracy degradation.
Memory and computationally efficient psychoacoustic model for MPEG AAC on 16-bit fixed-point processors

When MPEG AAC encoders are implemented on 16-bit fixed-point processors, the constraints of low complexity and limited data word length become challenges, especially on the critical algorithm, the psychoacoustic model (PAM). This paper proposes a very efficient PAM design, concerning the reduction of memory requirement and computational complexity while maintaining the audio quality.
Hardware oriented rate control algorithm and implementation for realtime video coding

In this paper, a novel rate control algorithm suitable for realtime video encoding is proposed. The proposed algorithm uses mean absolute error (MAE) results of motion estimation (ME) to achieve bitrate control. Neither pre-analysis nor multi-pass encoding is required in our algorithm, which makes realtime hardware implementation possible. A new hardware oriented scene change detection method is also included in this rate control framework to achieve better video quality. Experiment shows our rate control algorithm behaves well in all situations. Hardware architecture for this algorithm is also described. Implementation shows our proposed algorithm can be efficiently integrated into low cost, high efficiency video encoder.
High speed memory efficient EBCOT architecture for JPEG2000

This paper presents a high speed, memory efficient architecture of embedded block coding with optimized truncation (EBCOT) tier-1 in JPEG2000. By parallel coding all the bitplanes, the state variable memory can be eliminated. The proposed architecture can process 50 M coefficients per second at 100 MHz, which can realtime encode 720p resolution of HDTV picture format at 30 fps.
A motion estimator for low bit-rate video codec

A novel component performing motion estimation is presented. This chip is designed based on the three-step hierarchical search block-matching algorithm and can be applied to image communication on ISDN (integrated services digital network) (H.261 standard), MPEG, TV transmission, HDTV (high-definition television), etc. The practical architectural design techniques and the chip features are discussed. This component has the following features: unified execution steps, low latency delay, low I/O bandwidth, regular hardware structure, and single-chip or cascaded configurations.
Lifting based discrete wavelet transform architecture for JPEG2000

A lifting based 1-D discrete wavelet transform (DWT) core is proposed. It is re-configurable for 5/3 and 9/7 filters in JPEG2000. Folded architecture is adopted to reduce the hardware cost and achieve the higher hardware utilization. Multiplication is realized in hardwired multiplier with coefficients represented in canonic signed-digit (CSD) form. It is a compact and efficient DWT core for the hardware implementation of JPEG2000 encoder.
Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology

This paper introduces a power estimation scheme and generated results of SoC (System-on-Chip) fabricated with different process nodes extending to very deep submicron technology. Different power modeling strategies are used to estimate power for analog and digital circuits. According to the analysis results, ultra low power analog components are key to successful biomedical SoC design if more advanced fabrication technology is utilized. Meanwhile, the digital part should be designed barely enough to serve the target application. Integrating more dedicated digital hardware accelerators can further reduce the total power consumption by lowering the working frequency of system processor. The goal of this paper is to provide a quantitative scheme to estimate the power consumption when SoC is fabricated with different process technologies. Then a suitable technology could be selected to manufacture the SoC for biomedical usage.
Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC

High Definition (HD) video compression enables vivid reproduction of scenes. However, Motion Estimation (ME) requires large memory capacity and huge memory bandwidth, which are undesirable in many platforms including ASIC and SoC. In this paper, an algorithm and architecture design of cache system and fast ME in HD H.264/AVC are proposed. With the proposed cache system and hardware-oriented fast ME algorithm, the rate-distortion performance is maintained within 0.03dB difference, the size of on-chip memory reduced to only 10% to 21% of original size, while the external memory bandwidth from cache refill is also 18% to 56% less than that of level C data reuse scheme with vertical +64 search range.
Performance analysis of hardware oriented algorithm modification in H.264

H.264 [Committee Draft of Joint Video Specification, July 2002] is initiated by ITU-T as H.26L and will become a joint standard of ITU-T and MPEG. The coding complexity of H.264 is much higher than MPEG-4 simple profile and advance simple profile algorithms. In order to achieve real-time encoding, hardware implementation is required. The original test model of H.264 (JM) [Joint Video Team, August 2002] is designed to achieve high coding performance. Some algorithms of the test model require lots of operations with little coding efficiency improvement. And some algorithms create data dependencies that prevent parallel hardware accelerations. This paper presents analysis of H.264 video coding algorithm in a hardware-oriented viewpoint. Intra prediction, Hadamard transform and motion estimation algorithms are reviewed and modified to a hardware friendly configuration. The rate distortion penalties of these modifications are simulated and shown in this paper.
A Novel MPEG-2 Audio Decoder With Efficient Data Arrangement And Memory Configuration

The paper describes a novel MPEG-2 audio decoder with a new modified scheme. In the techniques of intelligent data arrangement, the complexity of the multichannel decoding can be largely reduced. In the modified decoding scheme, the bottleneck computation module can be reduced to a quarter of the size of the original. Also, the major memory storage only requires half the size of the standard synthesis subband filterbank.
A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine

3GPP LTE requires a 100 Mbps of peak bandwidth, and the instantaneous throughput demand changes with different applications. Fixed sub-block parallel turbo decoding scheme introduces bit-error rate (BER) performance drop when the block length is short. In this paper, an LTE turbo decoder implemented on a 0.66 mm2 die in a 65 nm CMOS technology is presented. An adaptive sub-block parallel (ASP) decoding scheme that improves the BER performance by up to 2.7 dB while maintaining the same parallelism is developed. A DVFS engine combining with an early-termination scheme is also developed. It generates the supply voltage and the clock rate that lead to the lowest energy consumption given the output bandwidth requirement. The measured energy consumption is 0.077∼0.168 nJ per bit per iteration and 0.39∼0.85 nJ per bit.
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile

Global motion estimation and compensation (GME/GMC) is a new and important coding tool in MPEG-4 Advanced Simple Profile (ASP). The coding gain of GME/GMC is 1-1.6 dB compared to that without GMC. However, because of the irregular memory access and huge memory bandwidth of GME/GMC, few hardware architectures have been proposed. In this paper, we proposed an algorithm which can save 87.27% memory bandwidth compared to that of the original algorithm. By the proposed arrangement of memory, the impact of the irregular memory access is reduced, and four neighboring pixels, which are used for the interpolation of GMC, can be accessed in one cycle. Finally, we also proposed a hardware architecture for GME in MPEG-4 ASP@L5. The total gate count is 131 K, at 100 MHz and the internal memory size is about 10.8 Kb. It is reasonable to be integrated into MPEG-4 ASP encoders.
An efficient hardware implementation of HON4D feature extraction for real-time action recognition

Human activity recognition has been an important area of computer vision research. In this paper, we present real-time hardware implementation for action recognition with HON4D features, which outperform the methods relying on skeleton detectors. Our proposed circuit adopts sliding histogram, and several approximate techniques to reduce computation and speed up feature extraction. Furthermore, using sliding histogram allows continuous classification without video segmentation in advance.
Low-power multi-processor system architecture design for universal biomedical signal processing

As the study of the wireless body area sensor network (BASN) keeps growing, corresponding applications such as bio-signal processing for personal healthcare are gaining more attention. To realize a miniature and multi-functional system for biomedical applications, the design of on-sensor mircoprocessor is considered to be a solution. However, how to balance the power consumption and system scalability remains a challenge. In this work, we try to involve the concept of multi-core computing systems into biomedical applications. A fully programmable system architecture based on the proposed two-way pipeline processing unit (two-way PPU) is introduced and evaluated. The proposed two-way PPU is a computing unit that adopts the general purpose processor (GPP) to provide high system programmability, and is easy to be cascaded for system extension. According to the implementation results, the proposed architecture can save up to 91% of energy compared with conventional multi-core architecture in a four-core biomedical processing microsystem.
Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator

Neuromodulation of the brain is an emerging therapy to control the epileptic seizure. The therapy can be improved with a closed-loop mechanism in which the electrical stimuli is activated in accordance with the seizure onset. In this paper, a correlation integral (CI) processor in a form of application specific integrated circuit is designed to estimate the brain complexity, chaoticity, after the EEG/ECoG sensors. Since the neural firing becomes more organized prior to the seizure, the intent is to drive the neuromodulator after the early detection of the seizure onset. With the simplified CI algorithm and channel-folded architecture, 0.14µW/channel power consumption is achieved in 90nm CMOS process to simultaneously extract chaoticity for 16 channels in a real time. The simulation results demonstrate a 98.23% and 97.81% of sensitivity and specificity for the classification of normal and epileptic brain rhythms.
Computation-Free Motion Estimation with Inter-View Mode Decision for Multiview Video Coding

Multiview video coding (MVC) plays a critical role in 3D-TV systems. However, MVC require much more memory bandwidth and computational complexity relative to mono-view video coding. Therefore, an efficient prediction scheme is necessary for computation reduction. In this paper, a new fast prediction algorithm, computation-free motion estimation (ME) with inter-view mode decision, is proposed. By utilizing disparity estimation to find corresponding blocks between different views, the coding information, such as modes and motion vectors, can be effectively reused from the coded view channel. Therefore, the computation for ME can be almost totally neglected in most view channels. Besides, the proposed algorithm also provides the computation scalability. Experimental results show that compared with the full search block matching algorithm (FSBMA), the proposed algorithm not only save 61-72% computation with near-FSBMA quality, but save almost 100% computation with a little quality drop of 0.23-0.36 dB. Thus, computation-free ME is achieved.
A 130.3mW 16-core mobile GPU with power-aware approximation techniques

In this work, a 130mW 16-core mobile GPU is fabricated with TSMC 45nm technology. With three approximation techniques, this proposed architecture can trade-off between power consumption and visual quality to provide power-aware ability. Implementation results show that, with satisfactory visual quality, 53% of the power consumption can be reduced with the proposed Approximated Precision Shader architecture and Screen-space Approximated Lighting technique. Moreover, the Approximated Texturing technique reduces 24.57% L1 cache requests in our evaluation.
An efficient parallel motion estimation algorithm for digital image processing

The authors present an efficient parallel block matching algorithm called the parallel hierarchical one-dimensional search for motion estimation. This algorithm is based on the assumptions made by the one-at-a-time search and 2-D logarithmic search. Instead of finding the two-dimensional motion vector directly, it finds two one-dimensional displacements in parallel on the two axes independently within the search area. The major feature of this algorithm is that its search speed for the motion vector is faster than that of the other search algorithms because of its simpler computations and parallelism.<<ETX>>
A Novel MPEG-2 Audio Decoder With Efficient Data Arrangement And Memory Configuration

The paper describe a novel MPEG-2 audio decoder with a new modified scheme. In the techniques of intelligent data arrangement, the complexity of the multichannel decoding can be largely reduced. In the modified decoding scheme, the bottleneck computation module can be reduced into oneforths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank.
Reconfigurable architecture for video applications

In this paper, the design concept of reconfigurable architecture for video applications is introduced. By introducing well-designed reconfigurability into application specific circuits, an application specific design can provide not only good performance in terms of area, speed and power, but also flexibility for different modes, parameters, and algorithms. Power-aware concept can therefore also be realized based on the reconfigurable architecture. Several design cases are discussed: reconfigurable architecture for MPEG-4 and AVC/H.264, scalable architecture for JPEG 20000, and a video processing unit (VPU) with reconfigurable memory.
124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory

A 124 MSamples/s JPEG 2000 codec is implemented on a 20.1 mm2  die with 0.18 mum CMOS technology dissipating 385 mW at 1.8 V and 42 MHz. This chip is capable of processing 1920times1080 HD video at 30 fps. For previous works, the tile-level pipeline scheduling is used between the discrete wavelet transform (DWT) and embedded block coding (EBC). For a tile with size 256times256, it costs 175 kB on-chip SRAM for the architectures using on-chip tile memory or costs 310 MB/s SDRAM bandwidth for the architectures using off-chip tile memory. In this design, a level-switched scheduling is developed to eliminate tile memory and the DWT and the EBC are pipelined at pixel-level. This scheduling eliminates 175 kB on-chip SRAM and 310 MB/s off-chip SDRAM bandwidth. The level-switched DWT (LS-DWT) and the code-block switched EBC (CS-EBC) are developed to enable this scheduling. The codec functions are realized on an unified hardware, and hardware sharing between encoder and decoder reduces silicon area by 40%
Architecture of MPEG-7 color structure description generator for realtime video applications

Color structure descriptor (CSD) provides satisfactory image indexing and retrieval results among all color-based descriptors in MPEG-7. The superiority comes from the consideration of space distribution of colors. Hardware accelerator is a must because its good performance is at the expense of high computational complexity. In this paper, a design approach of specific hardware accelerators for descriptors is explored. The characteristics of CSD algorithm are also analyzed and an efficient architecture is proposed. The proposed architecture can generate CSD description of 256 256 image at 30 frames per second (fps). The architecture provides about 4.5 giga instructions per second (GIPS) to achieve real-time applications like assisting rate control in video coding system and circumstance change detection in surveillance system.
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder

High Definition (HD) H.264/AVC video compression is the emerging necessity on nowadays home entertainment environment and so on. However, Although B-frame coding scheme provides better quality, only P-frame encoders are presented due to too high complexity and memory requirement. In this paper, a frame-parallel encoding scheme based on B-frame's data independency is proposed. It can largely reduce the system memory bandwidth and improve the processing capability. Then, the proposed IME and FME scheduling can further enhance the hardware utilization for frame-parallel scheme. Finally, a case study is given to show that the proposed scheme can largely reduce 66% system bandwidth compared to direct implementation from previous P-frame encoder.