nils-herrmann/clean_scirepeval huggingface dataset:
An Accurate Lithium-Ion Battery Gas Gauge Using Two-Phase STC Modeling

The lithium-ion (Li-ion) battery is a time-varying, nonlinear component. Its discharge characteristic is dependent on discharge current, loading change scheme, ambient temperature, and initial state-of-charge (SoC), and hence its remaining time can vary with the discharge operating conditions in a manner of nonlinear relationship. The non-linearity behavior makes the accurate gas-gauge of Li-ion battery very difficult. This paper presents an efficient scheme to simplify the estimation of battery service time with high-degree of accuracy. According to the typical discharge characteristic of Li-ion batteries, we applied a two-phase single-time-constant (STC) model for the gas-gauging strategy and parameterize the discharge operating conditions in terms of the first-phase gradient, the knee voltage, and the second-phase gradient, instead of using complex curve-fitting equations. As shown in the experimental results, the accuracy of predicted remaining time is less than 1% for constant current cases, and 10% for loading change cases.
High-Quality Image Compression for Gastrointestinal Endoscope

This paper proposes an efficient framework of high-quality image compression method for upper Gastrointestinal tract endoscopy images. The proposed DEWC coding method saves traditional image preprocessing computations, such as demosaicking and color-space transformation, and directly utilizes raw image data acquired from CMOS sensor. R, G and B band image are then separately encoded by wavelet-based SPECK coding. In a cardinal GI tract environment, the spatial frequency distribution of red component is lower than green or blue, and green component is relatively high while compared to blue and red components. DEWC coding saves more bits on red band while allocating more bits on green and blue bands. Therefore, under a fixed compression ratio, such non-uniform bit-rate allocation may earn a better image quality. To measure quality-loss in non-uniform bit-rate allocation, a quality quantified measurement called color-distortion based on CIE94 color-difference formula is also proposed. By using analytical result of color-distortion in bit-rate and bit-rate-difference analysis, an optimal/suboptimal bit-rate allocation scheme can be found by solving linear equations derived from the relationship of color-distortion and bit-rate-difference. When comparing to general JPEG2000 compression standard, the experimental result shows that proposed DEWC coding has a better image quality in color-distortion measurement and more efficient performance in execution time.
Model-based architectural design and verification of scalable embedded DSP systems-a RASSP approach

The paper describes how rapid model-year architectural synthesis (e.g., HW/SW codesign) of embedded signal processors can be performed to optimize various cost objective functions using a reuse library of model, followed by simulation based optimization. Sponsored as part of DARPA's RASSP program, this approach has developed and released a number of interoperable and verified architectural component libraries at the system level (processors, communication protocols, and topologies). While these libraries have been used in actual demonstrations of avionics and military systems, such as the MIT Lincoln Laboratory's SAR Benchmark, the F-14 legacy Infrared Search and Track System (IRST), and as part of NASA/JPL's Remote Exploration/Experimentation (REE) program studies, the authors introduce the methodology of conceptual prototyping and establish the requirements and features of the proposed environment. They also illustrate its use on some common applications with relatively sophisticated architectural building blocks, such as IEEE SCI protocol and Analog Devices' SHARC processor family.
An anti-racing PWM-based battery pack equalization

Following the trend of eco-conscious, the automakers tend to use high-voltage packs in the electric vehicle or hybrid electric vehicle. The packs are formed by battery cells in series and parallel connections. Because of the variation of battery production, their capacity, impedance, lifetime and chemistry characteristic vary with ambient temperature. When the batteries are charged or discharged as a pack, the differences result in the imbalance of the battery voltage. The imbalance turns out over-charged and over-discharged and shortens the capacity and lifetime of batteries. Among the equalization methods, resistively switching approach is widely used for its low complexity and low cost. The controller gauges the battery voltage no matter the equalization is on or off. The comparison of two battery voltages must be based on the charging current. If not, the racing phenomenon happens and the equalization circuit would be turned on and off frequently. PWM-based equalization can solve this problem. Detecting the voltages of the batteries when the duty is off ensures the battery voltages are both based on the charging current. The PWM-based equalization successfully eliminates the racing phenomenon and shortens charging time by 48%; from 6200 seconds of switching shunt resistor equalization to 3200 seconds.
A hybrid fuel cell-battery power system

This paper presents a new hybrid power system with battery depth-of-discharge (DOD) management for extending battery cycle life and system service time. The proposed power system consists of a power management system, a dual-battery unit, a fuel cell (FC) stack, and two dc/dc unidirectional power converters. The dual-battery unit serves as the primary power source, while the FC stack serves as the secondary power source. The proposed power management is based on a state-machine-based mechanism, using a battery interchanging strategy to limit batteries operating within a given DOD range. The state-machine-based mechanism is employed for reducing the effects of battery overcharging or overdischarging; thus, it can significantly improve the battery life time. In addition, this algorithm has the ability to distribute the power flow efficiently between the dual batteries and the FC stack, and also to keep providing a stable and continuous energy output for the load. A current-mode control dc/dc boost converter is designed to regulate the FC current and try to maximize the FC power for battery charging time reduction. The proposed hybrid system introduced in this paper is designed and implemented with a 20W proton exchange membrane fuel cell (PEMFC) stack and two 12Ah lithium iron phosphate (LiFePO4) batteries. The experimental results of capacity fades on various DOD tests verify the usefulness of the proposed fuel cell/dual batteries hybrid power system. The comparison of life improvement is also shown in test results.
Design of power-aware multiplier with graceful quality-power trade-offs

A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions with regard to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for this purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency, subject to user-defined quality constraints, than full precision multiplication.
On improving dynamic range of wideband multistage /spl Sigma//spl Delta/ modulator using nonlinear oscillation

This paper presents an improved architecture of the multistage (MASH) multibit sigma-delta modulators (/spl Sigma//spl Delta/Ms). The architecture can be immune to circuit nonidealities over a large portion of input range when oversampling ratio (OSR) is low, and hence the dynamic range (DR) can be improved. The approach presented is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feed forward (LQCIFF). The key to improving DR is to use HQCRFF-based single-bit structure in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. In addition, because of the in-band zeros introduced by the resonators, the proposed architecture enhances the suppression of the in-band quantization noise for wideband applications. As the results of simulation, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.
A robust, intelligent CC-CV fast charger for aging lithium batteries

This paper proposes a robust, intelligent constant current-constant voltage (CC-CV) charger for fast charging an aging Lithium-ion battery. Increasing the charging current in the CC regime cannot guarantee the short charging time, so an optimal charging current exists in the CC-CV method. The optimal charging current changes with battery degradation, so this paper figures out a way to find the optimal charging current by applying direct current internal resistance (DCIR) tests before the CC-CV charging method. The experiment results show that the proposed charger can adjust the optimal current based on battery state-of-health (SOH). The charging time has a 6.5% improvement when it is compared to a standard CC-CV fast charger.
An automated IP synthesizer for limited-resource DWT processor

This paper presents a systematic design methodology for 1-D/2-D DWT processor based on a novel limited-resource scheduling algorithm. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Based on the limited-resource scheduling algorithm an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.
A modified H.264 intra-frame video encoder for capsule endoscope

The objective of this paper is to develop an ultra-low-power video compression processor for capsule endoscope to lower the RF transmitter bandwidth. In applications of capsule endoscope, it is imperative to consider battery life and performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much power from battery. There are also many fast video compression algorithms for reducing computation load; however, they may result in distortion of original image. A new video compression algorithm for gastrointestinal image based on H.264 Intra-frame encoder and its corresponding VLSI architecture are both proposed for low-power, high bite-rate wireless capsule endoscope. The algorithm exploits the characteristic of gastrointestinal image and H.264 intra-frame prediction technique to reduce computing complexity and save battery power consumption. As the result of implementation, the developed video compressor for 512-by-512 image sensor and 2 Mbits/sec RF transmitter costs 60 k gates and consumes 0.9161 mW power at 2 frames/sec while the average compression rate can be as low as 82%.
A Wireless Narrowband Imaging Chip for Capsule Endoscope

This paper presents a dual-mode capsule gastrointestinal endoscope device. An endoscope combined with a narrowband image (NBI), has been shown to be a superior diagnostic tool for early stage tissue neoplasms detection. Nevertheless, a wireless capsule endoscope with the narrowband imaging technology has not been presented in the market up to now. The narrowband image acquisition and power dissipation reduction are the main challenges of NBI capsule endoscope. In this paper, we present the first narrowband imaging capsule endoscope that can assist clinical doctors to effectively diagnose early gastrointestinal cancers, profited from our dedicated dual-mode complementary metal-oxide semiconductor (CMOS) sensor. The dedicated dual-mode CMOS sensor can offer white-light and narrowband images. Implementation results show that the proposed 512 × 512 CMOS sensor consumes only 2 mA at a 3-V power supply. The average current of the NBI capsule with an 8-Mb/s RF transmitter is nearly 7 ~ 8 mA that can continuously work for 6 ~ 8 h with two 1.5-V 80-mAh button batteries while the frame rate is 2 fps. Experimental results on backside mucosa of a human tongue and pig's small intestine showed that the wireless NBI capsule endoscope can significantly improve the image quality, compared with a commercial-of-the-shelf capsule endoscope for gastrointestinal tract diagnosis.
A 2.5 14-bit 180-mW Cascaded ΣΔ ADC for ADSL2+ Applications

This paper presents a sigma-delta (ΣΔ) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 ΣΔ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4-mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.
On reducing leakage quantization noise of multistage /spl Sigma//spl Delta/ modulator using nonlinear oscillation

The paper presents an improved architecture of multistage (MASH) multibit sigma-delta modulators (/spl Sigma//spl Delta/Ms). The architecture can be immune to circuit nonidealities over a large portion of input range when the oversampling ratio (OSR) is low, and hence the dynamic range (DR) can be improved. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCIFF). The key to improving DR is to use an HQCRFF-based single-bit structure in the first stage and have the first stage oscillate. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problems. In addition, because of the in-band zeros introduced by the resonators, the proposed architecture enhances the suppression of the in-band quantization noise for wideband applications. As the results of simulation, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.
Effect of external resistance on SOH measurement of LFP cells

Due to the small ohmic resistance, such as the LFP battery, off-line state-of-health (SOH) estimation based on ohmic techniques faces a great challenge on measurement difficulty. The inaccurate measurement result of the ohmic resistance can cause a severe SOH error. This paper studies the influences of battery external resistance on the off-line SOH estimations using different model parameters in a first-order equivalent battery model. The sensitivity function is introduced here to assess performances of these model parameters. The several test results show that the transient resistance has the good ability against the external resistance effect. The sensitivity results of the transient resistance are all less 0.05 in different test cases. In addition, the SOHs estimated by the transient resistance and full charge capacity (FCC) in 600 cycling tests have the smallest average error (6.9%).
A Digital Boost Converter for Fuel Cell Current Regulation in Hybrid Power Systems

Fuel cell (FC)/lithium-ion battery hybrid power system (HPS) gradually becomes a powerful energy source in the future. This paper presents a digital boost converter for FC current regulation in the HPS with a dual-battery energy storage unit (ESU). The digital boost converter regulates the FC current in order to control the FC power generation. Simulations have been conducted in PSIM environment, and the digital controller is implemented with a Microchip dsPIC33FJ06GS202 16- bit microcontroller. Experimental results show that the efficiency of power conversion can reach to 85%.
A Subsample-based Motion Estimation for Quality-Stationary Video Coding

The block-matching motion estimation has been aggressively developed for years. Many papers have presented fast block-matching algorithms (FBMAs) for the reduction of computation complexity. Nevertheless, their results, in terms of video quality and bitrate, are rather content-varying. Very few FBMAs can result in stationary or quasi-stationary video quality or bitrate for different types of video content. This paper presents a content-motion-aware motion estimation for quality-stationary video coding. By adaptively specifying the subsample ratio, the proposed algorithm can adjust the computational load for acceptable quality loss under the rate control mechanism. As the simulation result, the proposed algorithm can produce stationary quality at the PSNR of 0.36 dB for a given bitrate while saving about 69.6% power consumption
On the reduction of reorder buffer size for discrete Fourier transform processor design

Double RAM buffer technique is widely used in row-column method to decompose the multidimensional transformation. In this paper, we propose a new approach, named single RAM technique. Base on the accurate arrangement of the location and timing of the input and output data, only a single RAM is used as the reorder buffer. Therefore, approximately half of the memory size is reduced. In addition, a long length DFT processor which can handle 1008-point real-valued DFT with nonstop input sequence is presented to demonstrate the benefits of the single RAM buffer technique. Goertzel Algorithm and CORDIC technique are adopted to realize a two level pipeline linear array for attaining higher speed. Besides, based on the symmetric property of real value DFT, we can compute N-point real-valued DFT with a length-N/2 complex-valued DFT.<<ETX>>
A power-aware ME architecture using subsample algorithm

This paper presents a power-aware architecture driven by a content-based subsample algorithm which allows the architecture to work at different power consumption modes with acceptable and smooth quality degradation. The proposed algorithm first performs the edge extraction to generate a turn-off mask which is used to reduce the switch activities of processing elements (PEs) in the semi-systolic array. Since we introduce an adaptive control mechanism to set the threshold value of edge determination, based on the video content and the remaining capacity of battery pack, the reduction of switch activities is rather stationary at a certain power consumption mode. As shown in simulation results, the architecture can dynamically operate at different power consumption modes with little quality degradation while the power overhead of edge extraction is under 0.8% comparing with the general subsample algorithm.
Spatio-temporal segmentation using 3D morphological tools

In this paper, we present a novel morphological approach to image simplification by flat zones which, applied to a temporal image sequence, leads to a method for spatio-temporal segmentation. Our approach considers a sequence as a single 3D image, rather than as a succession of 2D images. An extension of recent tools of 2D mathematical morphology, to the spatio-temporal (2D+t) volume, allows a fast detection of moving objects, a tracking of moving regions across time as well as a classification of motion.
Automatic parameterization of grey-level hit-or-miss operators for brain vessel segmentation

Reliable segmentation of 3D magnetic resonance angiography (MRA) is fundamental for planning and performing neurosurgical procedures, but also for detecting vascular pathologies. We propose here a method for brain vessel segmentation based on mathematical morphology tools. This method, devoted to phase-contrast MRA (PC-MRA) performs vessel segmentation by applying an adaptive set of grey-level hit-or-miss operators on each point of the MR data. High level anatomical knowledge modeled by a vascular atlas is used in order to adapt the parameters of these operators (number, size, and orientation) to the current position. The method has been performed on 30 PC-MRA cases composed of both phase and magnitude images. The results have been validated and compared to segmented data obtained by applying a region-growing algorithm on the same database. They tend to prove that the method is reliable for brain vessel detection and additionally provides information on vessel size and orientation without requiring any post-processing step.
Cerebral vascular atlas generation for anatomical knowledge modeling and segmentation purpose

Magnetic resonance angiography (MRA) is currently used for cerebral flowing blood visualization. Many segmentation methods have been proposed for brain vessel segmentation, in order to help analyzing the huge data (generally more than 10/sup 7/ voxels) provided by MRA acquisitions. Recently, a new family of segmentation algorithms, involving high level anatomical knowledge, has been studied. These new algorithms require a way to model and store this knowledge. An efficient and general approach to reach that goal consists in using atlases. In this paper a method is proposed to create vascular atlases of the brain, containing information useful for vessel segmentation purpose. This atlas creation process, designed for phase-contrast MRA (PC-MRA), is composed of four steps: segmentation, quantification, registration and data fusion. It uses a region-growing algorithm for vessel segmentation, a skeleton and vessel size determination algorithm, based on discrete geometry, for determination of quantitative properties, and a topology preserving non-rigid registration method to fuse the information. This method, which has been applied to a 18 PC-MRA database, enables to create vascular atlases containing information on brain vessels position, density, size and orientation. The generated atlases are essentially devoted to segmentation purpose but can also be used for anatomical description or pathology detection.
Fully automatic 3D segmentation of coronary arteries based on mathematical morphology

In this paper we propose a fully automatic algorithm for coronary artery extraction from X-ray data (3D-CT scan, 64 detectors) based on the mathematical morphology techniques and guided by anatomical knowledge. Growing and thresholding methods, in their most general form, are not sufficient to extract only the whole coronary arteries, because of the properties of these images. Finding appropriate methods is known to be a challenging problem because of the data imperfections such as noise, heterogeneous intensity and contrasts of similar tissues. We deal with these challenges by employing discrete geometric tools to fit on the arteries form independently from any perturbation of the data.