nils-herrmann/clean_scirepeval huggingface dataset:
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

In this paper, a detailed analysis of very large scale integration (VLSI) architectures for the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is presented in many aspects, and three related architectures are proposed as well. The 1-D DWT and inverse DWT (IDWT) architectures are classified into three categories: convolution-based, lifting-based, and B-spline-based. They are discussed in terms of hardware complexity, critical path, and registers. As for the 2-D DWT, the large amount of the frame memory access and the die area occupied by the embedded internal buffer become the most critical issues. The 2-D DWT architectures are categorized and analyzed by different external memory scan methods. The implementation issues of the internal buffer are also discussed, and some real-life experiments are given to show that the area and power for the internal buffer are highly related to memory technology and working frequency, instead of the required memory size only. Besides the analysis, the B-spline-based IDWT architecture and the overlapped stripe-based scan method are also proposed. Last, we propose a flexible and efficient architecture for a one-level 2-D DWT that exploits many advantages of the presented analysis.
124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory

A JPEG2000 codec capable of processing 1920times1080 HD video at 30frames/s is implemented on a 20.1mm2 die with 0.18mum CMOS technology dissipating 345mW at 1.8V and 42MHz. The level-switched schedule eliminates the 192kB tile memory. Hardware sharing between encoder and decoder reduces silicon area by 40%
Algorithm and architecture optimization for full-mode encoding of H.264/AVC intra prediction

In this paper, we designed a four-parallel intra prediction architecture applied with four optimization schemes. Category-level interleaved scheme (CLIS) eliminates the bubble cycles of 14MB reconstruction. Mode-level scheduling (MLS) and early data preparation scheme (EDPS) rearrange the processing sequence of intra modes. The hardware resource of earlier low-complexity modes is used to deal with the computation of later high-load modes. Not only the hardware utilization is increased but the processing cycles is reduced. Furthermore, stage-level partial distortion elimination (SLPDE) is induced to skip the calculation of unnecessary intra modes. The architecture has been integrated into an H.264/AVC baseline encoder for HDTV applications and has been verified to be feasible under system consideration.
Robust heart rate measurement with phonocardiogram by on-line template extraction and matching

As health care becomes popular, daily monitoring of health-status related parameters, including the heart rate (HR), is getting more and more valued. An easy, comfortable and robust solution is therefore an important issue. Phonocardiogram (PCG) is a physiological signal reflecting the cardiovascular status. It could be recorded by microphone-equipped on-hand devices, like the smartphone, even without direct skin contact. However, high inter- and intra-variance of PCG make its processing challenging. For PCG-based HR measurement, a robust method is still strongly required. In this paper, we propose a HR measurement algorithm on the processing of PCG that uses on-line template extraction and matching. Through several experiments where traditional methods cannot effectively handle, the robustness of our method is verified by its accurate HR measurement results.
Low power programmable shader with efficient graphics and video acceleration capabilities for mobile multimedia applications

In this paper, a low power programmable vertex shader with video coding acceleration instructions is proposed. For mobile multimedia applications, supporting both video and graphics is a promising trend. The proposed programmable graphics engine features a unified architecture that can efficiently execute not only vertex shader operations for graphics but also the motion estimation of video coding algorithms. It can achieve the processing speed of 8.3M vertex geometry transformations per second and 6.25M polygons per second with the working frequency of 50 MHz and the power consumption of 20 mW. Furthermore, the floating/fixed-point data path, the reconfigurable memory, and special instructions are designed to be able to accelerate the key operation, motion estimation, in video coding. The execution of motion estimation on the proposed graphics engine is shown to be 80 times faster than RISC type processors and can achieve real-time video coding requirements with diamond search algorithm for 30 CIF (352/spl times/288) frames per second with [-16, 15] search range. This powerful graphics and video dual-function programmable engine is shown to be a good solution for multimedia consumer products.
On-the-fly fashion photograph recommendation system with robust face shape features

In this paper, we demonstrate a novel method for retrieving fashion photographs with robust face shape features, a challenging problem due to the different face orientations, variant face size, and variation in lighting environment. In addition, we provide a novel dataset for labeling eight face shape categories, to enable future research on face shape classification. We also present experimental results through the proposed face shape features to reach 94% accuracy of face shape classification. Finally, we demonstrate an on-the-fly prototype application for the face-shape-dependent fashion photo recommendation system.
Algorithm and architecture design of a knowledge-based vehicle tracking for intelligent cruise control

The paper exploits a vision-based intelligent vehicle cruise control system from the application level to the architecture level. Firstly, design considerations of the system are addressed in both computing power and accuracy aspects. Secondly, we present an efficient knowledge-based front-vehicle tracking algorithm. The algorithm yields below 5% error rate that outperforms the state-of-the-arts. Thirdly, a run-length-based algorithm optimization flow is introduced. Finally, specific hardware architecture is developed. It achieves 1280×960/80FPS and 4096×2160/10FPS requirements for multi-vehicle tracking tasks.
Embedded JPEG encoder IP core and memory efficient preprocessing architecture for scanner

In this paper a baseline JPEG encoder soft intellectual property (IP) is proposed together with a memory efficient preprocessing architecture for scanner to solve the bandwidth problem between PC and scanner. This JPEG IP features quantization tables that are reconfigurable at run time and compile time. It is a modularized and fully pipelined design with friendly interface, which makes it easier to be integrated into various application systems. It is silicon proven to run up to 40 MHz at 3.3 V. With the optimized preprocessing unit feeding data smoothly into JPEG core, it is a low cost and competitive solution for a scanner to have a compression function embedded.
Hardware verification using symbolic state transition graphs

A new approach for hardware verification using symbolic state transition graphs (implemented in BDDs) is presented. We propose a novel idea, a symbolic state transition graph (STG), which can represent finite state machines FSM in terms of the relations between symbolic input variables, state variables, and output results, rather than the exact input-output bit patterns. Compared to conventional STG methods, the symbolic STG is more concise, higher-level, has fewer states and is easier to specify. Based on the transition relation method and an event-driven scheduling technique to compute the symbolic states, we propose two algorithms to verify the circuit implementation with respect to its symbolic STGs. The algorithms can be used to find out a necessary condition for the implementation to satisfy the specification, which can be used for the allocation of design errors.<<ETX>>
The radix-2/sup k/ Viterbi decoding with transpose path metric processor

In this paper, we present a radix-2/sup k/ Viterbi decoding with Transpose Path Metric (TPM) processor. The TPM processor can provide a permutation function for state rearrangement with simple local interconnection. For interconnection realization, the routing complexity is less than that of the delay-commutator reported previously. In addition, a higher memory length Viterbi processor can be constructed with lower radix-2/sup k/ modules. With features of modulation and cell regularity, the radix-2/sup k/ Viterbi decoding with TPM processor is very suitable for VLSI implementation.
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture

This paper presents a new macroblock (MB) pipelining scheme for H.264/AVC encoder. Conventional video encoders adopt two-stage MB pipelines, which are not suitable for H.264/AVC due to the long encoding path, sequential procedure, and large bandwidth requirement. According to our analysis of encoding process, an H.264/AVC accelerator is divided into five major functional blocks with four-stage MB pipelines to highly increase the processing capability and hardware utilization. By adopting shared memories between adjacent pipelines with sophisticated task scheduling, 55% of the bus bandwidth can be further reduced. Besides, hardware-oriented algorithms are proposed without loss of video quality to remove data dependencies that prevent parallel processing and MB pipelining. The H.264/AVC Baseline Profile Level Three encoder, which requires computational complexity of 1.8 tera-instructions per second (TIPS), is successfully mapped into hardware with our MB pipeline scheme at 100 MHz.
Algorithm and architecture for object tracking using particle filter

Particle filtering is a popular algorithm for vision-based target tracking. Despite its effectiveness in many fields of tracking, however, the computation requirement of particle filters is high. In this paper we propose an algorithm and architecture for vision-based particle filters. The proposed algorithm can estimate objects' positions, sizes, and angles by using color histogram as the feature. We propose two hardware parallelization schemes — one makes use of particle-level parallel operation and the other utilizes particle-level plus pixel-level parallel operation. The experimental result shows the tracking accuracy of our test sequences is over 85%, and the proposed hardware architecture can run the particle filtering in real-time, with 31.35 frames per second in average.
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC

We contributed a new VLSI architecture for fractional motion estimation of the H.264/AVC video compression standard. Seven inter-related loops extracted from the complex procedure are analyzed and two decomposing techniques are proposed to parallelize the algorithm for hardware with a regular schedule and full utilization. The proposed architecture, also characterized by a reusable feature, can support situations in different specifications, multiple standards, fast algorithms and some cost considerations. H.264/AVC baseline profile level 3 with complete Lagrangian mode decision can be realized with 290K gates at operating frequency of 100 MHz. It is a useful intellectual property (IP) design for platform based multimedia systems.
Low power full-search block-matching motion estimation chip for H.263+

In this paper, a low power full-search block matching (FSBM) motion estimation design for the H.263+ low bit rate video coding was proposed. The features of H.263+ such as half-pixel precision and some advanced modes (advance prediction mode, PB-frame mode and reduced resolution update mode) are taken into consideration. This architecture can deal with different block size and searching range in a single chip without any latency. We use a 1-D and 2-D mixed architecture to fulfill this goal. To achieve the purpose of low power and reduce the design period, we use dual supply voltage levels in this chip. This chip is realized by TSMC 0.6 /spl mu/m single-poly triple-metal CMOS technology. The operation frequency is set at 60 MHz to meet the requirement of the real time processing in the reduced resolution update mode in H.263+. The power consumption is 424 mW at 60 MHz and the throughput is 36 frames per second with CIF format at 60 MHz.
An efficient and simple VLSI tree architecture for motion estimation algorithms

A low-latency, high-throughput tree architecture is proposed. This architecture implements both the full-search block-matching algorithm and the three-step hierarchical search algorithm in motion estimation. Owing to the simple and modular properties, the proposed architecture is suitable for VLSI implementation. Furthermore, it can be decomposed into subtrees to reduce hardware cost and pin count. The memory interleaving and the pipeline interleaving are also employed to enhance memory bandwidth and to use the pipeline 100%. Theoretical calculations and simulation results are presented to show the attractive performance.
Error resilience for block loss with overlapped motion compensation

A new error resilience algorithm for recovering the lost blocks or motion vectors is presented. It combines the overlapped motion compensation and the side match criterion to make the effect of lost blocks subjectively imperceptible. The side match criterion takes advantage of the spatial contiguity and interpixel correlation of image to select the best-fit replacement among the motion vectors of spatially contiguous candidate blocks. Particularly, to mask the blocking artifacts, we incorporate an overlapping technique to create a subjectively closer approximation to the true error-free image.
Pipelined arithmetic encoder design for lossless JPEG XR encoder

With rapid progress of sensors, display devices, and computing engines, image application exists everywhere. High quality, high compression rates of digital image and low computational cost are important factors of consumer electronics. In this paper, we proposed a 4:4:4 lossless JPEG XR encoder design. In JPEG XR encoder, entropy coding is a critical module of encoder. We proposed a well-defined timing schedule of pipeline architecture to speed up the entropy encoding, which is the most computationally intensive part in JPEG XR encoder. This design can be used for the digital photography applications to achieve the low complexity of computation, low storage, and high dynamic range.
Area Efficient Architecture for the Embedded Block Coding in JPEG 2000

An area efficient architecture for the embedded block coding in JPEG 2000 is implemented on a 1.23 mm2 die using 0.18 mum CMOS technology. This chip can support 16.7 MS/s lossless encoding. The area of the proposed architecture is only 1/6 of the conventional architectures while the throughput is the same as others. The proposed architecture has the highest performance comparing with other existing architectures according to the experimental results
Analysis and architecture design of JPEG2000

Analysis and architecture design of the key modules in JPEG2000 are presented in this paper. For Discrete Wavelet Transform (DWT), a lifting based DWT core for the default 5-3 and 9-7 filters in part I of JPEG2000 is proposed. Folded architecture is adopted in DWT to reduce the hardware cost and to achieve the higher hardware utilization. For Embedded Block Coding with Optimized Truncation (EBCOT), column-based coding architecture of Tier-1 block coding engine is proposed. The context formation efficiency is increased by adopting two speedup methods. The computation cycle of the block coding engine is reduced to about 40% of previous work.
A Quality-of-Experience Video Adaptor for Serving Scalable Video Applications

When transmitting video over a heterogeneous network, it is required to satisfy the different constraints due to the preferences and equipment selections of different users. Scalable video coding is one of the solutions to serve this problem. More than one video parameters include spatial frame size, temporal frame rate, and visual quality resolution are utilized to provide better scalability in scalable video coding scheme. It is difficult to find the relationship between the various video parameter settings and user preferences. In this paper, we propose a quality-of-experience video adaptor applied on scalable video applications. This adaptor adjusts video parameters for each user appropriately and achieves a better visual quality by using negligible computation. The simulated results show the accuracy of adaptation points can match the user's preference from 78% to 93% by using proposed scheme. This solution provides not only a practical way in video adaptor design, but also an efficient scheme to achieve better subjective view.
Analysis of belief propagation for hardware realization

Belief propagation has become a popular technique for solving computer vision problems, such as stereo estimation and image denoising. However, it requires large memory and bandwidth, and hence naive hardware implementation is prohibitive. In this paper, we first analyze the memory and bandwidth requirements of the technique from the hardware perspective. Then, we propose a tile-based belief propagation algorithm that works with existing data reuse schemes and achieves bandwidth reduction by a factor of 10 to 400. We apply the proposed algorithm to stereo estimation and show that its performance is comparable to the original algorithm.
System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering

Motion-compensated temporal filtering (MCTF) is an innovative prediction scheme for video coding and it has become the core technology of the coming video coding standard, Scalable Video Coding. Since MCTF is important, this paper provides the system analysis of MCTF for hardware architecture design, including computational complexity, external memory bandwidth, and external memory size. The one-level MCTF is analyzed first, in which several frame-level data reuse schemes are proposed and the tradeoffs between external memory usages and on-chip memory size in these frame-level data reuse schemes are also discussed. Next, the analysis is extended to multilevel MCTF. The computational complexity of multilevel MCTF is close to that of traditional MC prediction with two reference frames. The memory bandwidth of multilevel MCTF depends on the frame-level data reuse scheme and performing the update stage or not. The external memory size is linearly proportional to the number of decomposition levels. Finally, a real-life test case is given to compare the system requirements between MCTF with various frame-level data reuse schemes and the prediction scheme of H.264/AVC
A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor for mobile multimedia applications

A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor is designed and implemented for mobile multimedia applications. It is fabricated in 65nm CMOS technology with core size of 7.56mm2. The buffer bridged scheduler, energy efficient transaction technique and approximated rendering scheme are proposed to efficiently utilize energy to deliver excessive graphics rendering performance of 1.2Gvertices/s and 2.4Gpixels/s for 3D graphics applications. Moreover, configurable filtering unit (CFU) is also employed for accelerating image processing. Compared with state-of-the-art image signal processors (ISPs), 1.1 times to 7.2 times performance can be achieved by the proposed mobile graphics processor with CFU.
Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder

Low power hardware design for entropy coding of H.264/AVC baseline profile encoder is urgent for the increasing mobile applications. However, previous works are poor in the power performance. In this paper, the first low power context-based adaptive variable length coding (CAVLC) scheme named the side information aided (SIA) symbol look ahead (SLA) one-pass CAVLC is proposed, with the non-zero and abs-one SIA flags. A reconfigurable architecture for the SLA module is also proposed to support the low power CAVLC scheme efficiently. The resultant hardware power is reduced by 69% to only 3.7 mW at 27 MHz and 1.8 V for CIF-sized video coding. The total logic gate count is 27 K gates
Hardware architecture design of video compression for multimedia communication systems

VLSI realization of video compression is the key to many real-time multimedia communications systems. Among the video compression algorithms, the newly established MPEG-4 and, in particular, H.264 standards have become increasingly popular. However, the high coding efficiency of such video coding algorithms comes at the cost of a dramatic increase in complexity. Effective and efficient hardware solutions to this problem are necessary. In this article we present an overview of the hardware design issues of MPEG-4 and H.264. Both module and system architectures of these two coding standards are discussed. Based on these architectures, the design of a single-chip encoder complying with the H.264 baseline profile and capable of encoding the D1 resolution (720 x 480) video at 30 Hz is presented as an example. In addition, the system integration issues of video compression engines with multimedia communication systems and a general hardware platform for various applications are discussed.
Low delay, error robust wireless video transmission architecture for video communication

In this paper, a novel video transmission architecture is proposed to meet the low-delay and error robust requirement of wireless video communications. This architecture uses FEC coding and ARQ protocol to provide efficient bandwidth access from wireless link. In order to reduce ARQ delay, a video proxy server is implemented at the base station. This video proxy not only reduces the ARQ response time but also provides error tracking functionality. We use H.263 as the experimental platform for our architecture. Experiments show that average luminance PSNR decreases only 0.35db for the "Foreman" sequence under a random error condition of 10/sup -3/ error probability.
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications]

To the best of authors' knowledge, this paper presents the first work on memory analysis of VLSI architectures for motion-compensated temporal filtering (MCTF). The open-loop MCTF prediction scheme has led the revolution for hybrid video coding methods that are mainly based on the close-loop MC prediction (MCP) scheme, and it also becomes the core technology of the coming video coding standard, MPEG-21 part 13-scalable video coding (SVC). In this paper, the macroblock (MB)-level and frame-level data reuse schemes are analyzed for the MCTF. The MB-level data reuse is especially for the motion estimation (ME), and the level C+ scheme is proposed, which can further reduce the memory bandwidth of the conventional level C scheme. Frame-level data reuse schemes for MCTF are proposed according to the open-loop prediction nature.
MPEG-4 video bitstream structure analysis and its parsing architecture design

In this paper, the hardware-oriented structure analysis and an efficient and flexible bitstream parser for MPEG-4 video are presented. The analysis of bitstream structure explores processing requirement and design constraint for bitstream-level processing. The proposed architecture is basically RAM-based that can be reconfigured for various applications. For high bitrate as about 40 Mbit/s, it needs only about 19 MIPS to parse the bitstream. The impact of the proposed architecture on MPEG-4 video is to enhance and extend the processing for bit domain translation and related real time applications.