nils-herrmann/clean_scirepeval huggingface dataset:
System Architecture Design Methodology for H.264/AVC Encoder

MPEG-4 H.264/AVC has become a joint standard for ITU-T and MPEG and has been implemented in a wide spectrum of applications, from digital video broadcasting for handsets (DVB-H) to Hi-Definition DVD Storage (HD DVD). However, the resolution and system clock rate requirements vary greatly. Therefore, developing a system that is optimal for all applications is impossible. Among all aspects of the H.264 encoding system architecture design, inter-prediction occupies 99% total computation complexity and the search-range buffer occupies 76% of total on-chip memory. Our design methodology fully explores the design spaces of parallelism of inter-prediction, macro-block (MB) pipelining, and search-range buffer architecture. This paper combined with presents a complete methodology to help H.264/AVC systems designers obtain the most area efficient design under user defined timing requirements.
Memory efficient JPEG2000 architecture with stripe pipeline scheme

The memory issue is the most critical problem for a high performance JPEG2000 architecture. The tile memory occupies more than 50% of the area in conventional JPEG2000 architectures. To solve this problem, we propose a stripe pipeline scheme. For this scheme, a level switch discrete wavelet transform (LS-DWT) and a code-block switch embedded block coding (CS-EBC) are proposed. With small additional memory, the LS-DWT and the CS-EBC can process multiple levels and code-blocks in parallel by an interleaved scheme. As a result, the overall memory requirements of the proposed architecture can be reduced to only 8.5% compared with conventional architectures.
Optimal module set and clock cycle selection for DSP synthesis

The authors present a program to determine the optimal module set and clock cycle time of an application specific digital signal processor at the beginning of synthesis. This method systematically performs design space exploration in actual time and space domain. The module set can include single-cycle, multicycle or pipelined operators. The optimal clock cycle selection is done by scanning all suboptimal clock cycle values in an efficient way. The cost of hardware considers both the cost of the data path and that of the controller. Several examples are given to show the advantages of the approach.<<ETX>>
Novel systolic array design for the discrete Hartley transform with high throughput rate

Three features for the discrete Hartley transform (DHT) transform are derived, including (1) the single/double data folding; (2) the constructive feature and (3) the data reusage. By using the CORDIC (coordinate rotations digital computer) algorithm, the DHT transform kernel h/sub n//spl times/[cos/spl theta/+ sin/spl theta/] and conjugate kernel h/sub n//spl times/[cos/spl theta/-sin/spl theta/] can be simultaneously determined. With these favorable properties, a novel systolic array design for the discrete Hartley transform is designed.<<ETX>>
A multimedia semantic analysis SoC (SASoC) with machine-learning engine

Advances in semiconductors and developments in machine learning  have led to versatile multimedia applications with semantic processing abilities. Real-time applications, such as face detection, facial-expression recognition, scene analysis  and object recognition , have become indispensable functionality for Consumer Electronic (CE) products. To deal with complicated video-processing algorithms for multimedia content analysis, many powerful processors have been reported [2–5]. Although these processors can speed up video-processing tasks with massively parallel processing elements, they only focus on the feature-extraction parts, and there is no specialized hardware to support different kinds of advanced machine-learning algorithms, which require extensive computations. In this paper, a Semantic Analysis SoC (SASoC) that accelerates video processing and machine learning simultaneously, is developed to meet the demands of the near future.
Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling

Memory issues pose the most critical problem in designing a high-performance JPEG 2000 architecture. The tile memory occupies more than 50% area in conventional JPEG 2000 designs. To solve this problem, we propose a stripe pipeline scheduling. It well matches the throughputs and dataflows of the discrete wavelet transform and the embedded block coding to minimize the data lifetime between the two modules. As a result of the scheduling, the overall memory requirements of the proposed architecture can be reduced to only 8.5% compared with conventional architectures. This effectively reduces the hardware cost of the entire system by more than 45%. Besides reducing the cost, we also propose a two-symbol arithmetic encoder architecture to increase the throughput. By use of this technique, the proposed architecture can achieve 124 MS/s at 124 MHz, which is the highest specification in the literature. Therefore, the proposed architecture is not only low cost but also high speed
A real-time multi-user face unlock system via fast sparse coding approximation

We propose a multi-user face unlock system based on fast sparse coding approximation. Different approximation techniques of sparse coding are compared for real-time processing and recognition rate. The system is capable of online new user registration without specific training, and it is designed for continuously processing video sequences as on-the-fly face classification. The system is tested with a public face dataset for real-world applications, which is able to recognize 100 different face identities in 0.0028s on a regular PC, with 93.8% recognition rate.
NEUSORT2.0: A multiple-channel neural signal processor with systolic array buffer and channel-interleaving processing schedule

An emerging class of neuroprosthetic devices aims to provide aggressive performance by integrating more complicated signal processing hardware into the neural recording system with a large amount of electrodes. However, the traditional parallel structure duplicating one neural signal processor (NSP) multiple times for multiple channels takes a heavy burden on chip area. The serial structure sequentially switching the processing task between channels requires a bulky memory to store neural data and may has a long processing delay. In this paper, a memory hierarchy of systolic array buffer is proposed to support signal processing interleavingly channel by channel in cycle basis to match up with the data flow of the optimized multiple-channel frontend interface circuitry. The NSP can thus be tightly coupled to the analog frontend interface circuitry and perform signal processing for multiple channels in real time without any bulky memory. Based on our previous one-channel NSP of NEUSORT1.0 [1], the proposed memory hierarchy is realized on NEUSORT2.0 for a 16-channel neural recording system. Compared to 16 of NEUSORT1.0, NEUSORT2.0 demonstrates a 81.50% saving in terms of area×power factor.
A modified MPEG-2 audio decoding scheme based on its low-cost fast algorithm and efficient data scheduling

Degrouping is the key component in MPEG Layer II audio decoding. It mainly contains the arithmetic operations of division and modulo, which requires a great deal of hardware and computation time. In this paper, we propose a novel degrouping algorithm with a low complexity design concept. By using mode selection and iterative decomposition, only the addition and subtraction are needed. The elimination of the multiplier, divider and ROM table can therefore save a lot of chip area, but still retains the high efficiency without loss of any accuracy.
Algorithm and implementation of multi-channel spike sorting using GPU in a home-care surveillance system

Intensive home-care surveillance programs are associated with a marked decrease in the need for hospitalization. They can improve the functional statuses of elderly patients with severe congestive diseases. The GPU-based home-care surveillance system is effective and has a major impact on health expenditure than traditional surveillance equipments. In this work, we propose a spike sorting technique as a specific case for the GPU-based home surveillance system. Spike sorting is the procedure of classifying spikes corresponding to the firing neurons. In neuroscience research, spike sorting is adopted to analyze neural activities, brain functions and sensation. It is also a key component in cortically-controlled neuro-prosthetics for patients. In order to efficiently distinguish different neural spike activities, a robust spike sorting algorithm is required for above applications. To improve accuracy, multi-channel spike sorting is necessary. In addition, real-time monitoring for a home-care system is required. Therefore, we exploit a CUDA implementation using GPU for acceleration.
Error concealment of lost motion vectors with overlapped motion compensation

Most video sequence coding systems use block motion compensation to remove temporal redundancy for video compression due to the regularity and simplicity. A new error concealment algorithm for recovering the lost or erroneously received motion vectors is presented. It combines the overlapped motion compensation and the side match criterion to make the effect of lost motion vectors subjectively imperceptible. The side match criterion takes advantage of the spatial contiguity and interpixel correlation of image to select the best-fit replacement among the motion vectors of spatially contiguous candidate blocks. Particularly, to mask the blocking artifacts, we incorporate an overlapping technique to create a subjectively closer approximation to the true error-free image.
A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition

In this paper, an NC processor for power-efficient real-time universal visual recognition is proposed with following features: 1) A grey matter-like homogeneous many-core architecture with event-driven hybrid MIMD execution provides 1.0TOPS/W efficient acceleration for NC operations; 2) A white matter-like Kautz NoC provides 2.3Tb/s throughput, fault/congestion avoidance and redundancy-free multicast with 151Tb/s/W NoC power efficiency, which is 2.7-3.9x higher than previous NoC-based visual recognition processors.
Platform-based MPEG-4 video encoder SOC design

An MPEG-4 video coding SOC design is presented. We adopt a platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented to provide a compromise between compression performance and design cost. The proposed data reuse scheme reduces the required memory access bandwidth. Several key modules are integrated into an efficient platform in a hardware/software codesign fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352/spl times/288) frames per second.
An intelligent vision-based vehicle detection and tracking system for automotive applications

In this paper, we present an intelligent vision-based on-road preceding vehicle detection and tracking system based on computer vision techniques. Pre-processing video stabilization is adopted to improve system reliability and stability. High performance detection is achieved via the machine learning-based method. Our framework is favored for various automotive applications, which yields above 90% detection rate in long range and 99.1% tracking successful rate in middle range.
B-spline factorization-based architecture for inverse discrete wavelet transform

In this paper, the VLSI architecture for the inverse discrete wavelet transform (IDWT) is proposed on the basis of B-spline factorization that is the intrinsic property of DWT and comprises two parts: B-spline part and distributed part. After the polyphase decomposition, the former can be constructed by Pascal or direct implementation. And the latter one can be implemented by serial or parallel filter architecture. The B-spline-based architectures can reduce multipliers but would introduce additional adders compared with convolution-based architectures. Because the hardware complexity of adders is much less than that of multipliers, B-spline-based architectures could provide smaller hardware complexity for DWT and IDWT. The case study of the (10,18) filter will also be given to demonstrate the efficiency.
Area efficient architecture for the embedded block coding in JPEG 2000

An area efficient architecture for the embedded block coding is presented in this paper. A new algorithm is proposed to compute the state variables on-the-fly. Thus, the memory for the state variables are eliminated, which occupies more than 60% area in a conventional embedded block coding architecture. The area of the proposed architecture is only 1/6 of conventional architectures while the throughput is the same as others. The proposed architecture has the highest performance comparing with other existing architectures according to the experimental results.
GPU-accelerated high-resolution image stitching with better initial guess

High-resolution image processing is crucial for emerging applications in virtual reality. The trade-off between robustness/accuracy and speed pose a challenge to high-resolution image stitching. This paper accelerates the state-of-the-art image stitching algorithm by using the CUDA toolkit. We also use the mesh coordinates as an initial guess for solving warping function for an additional increase in speed. Experimental results show that our implementation achieves comparable quality to the state-of-the-art work, while our implementation is almost 2x faster on high-resolution images (3264×2448).
Architecture and analysis of color structure and scalable color descriptor for real-time video indexing and retrieval

Color stnictiire descriptor (CSD) arid scalable colrir descriptor (SCD) provide .sati.s/actoiy and scalable inluge inde,~ing and rebieval resiiIts among other color-based descriptors in MPEG-7. The sfiperiori<v of' CSD comes .from the con.sk/eration oJ space disti-ihiition of' pirel colors and SCD pravides .scalability on histogram by a Haar-,filter. I n this paper, LW proposed the first hardware architecttire that conibines CSD and SCD /I? ~~esoiirce sharing, and it can generate descriptions withframe size 256x256 and 30 frames per second fps). This architecture pinides ahoirt 12 times speed-iip than rimning on a 2.54 GHz n~icropruce.s.sor plat/urm to achieve real-time applications like assisting fast algmoritlmi of' motion estimation in video coding system and circiimstance change detectioii in srirveillancr system. I Index Terms Hardware architecture, indexing and retrieval, MPEG-7 application, MPEG-7 descriptor.
A 65 fps Full-HD Hardware Implementation of HOG, HOF, MBHx, and MBHy for Real-Time Action Recognition

In this paper, we propose a compact hardware architecture which can support HOG, HOF, MBHx and MBHy feature extraction in real-time. To achieve low-cost hardware, we first design a hardware-oriented algorithm. In addition to simplification of complicated numeric computation, we also modify the computation of the gradient at boundary to reduce on-chip buffers. The architecture is highly parallel in order to fully reuse input data and to achieve high throughput. Other features of our architecture include a four-bank memory composed of four SRAMs, a 2-cycle weighted binning, and a 2-port memory for histogram collection. The final specification can support HOG, HOF, MBHx, and MBHy feature extraction with a throughput of 65 fps in full-HD videos operating at 215 MHz, consuming only 57.6 kB on-chip memory and a gate count of 411k.
Motion adaptive interpolation with horizontal motion detection for deinterlacing

A motion adaptive deinterlacing algorithm is presented in this paper. It consists of the ELA-median directional interpolation, same-parity 4-field horizontal motion detection, morphological operation for noise reduction and adaptive threshold adjusting. The edges can be sharper when the ELA-median directional interpolation is adopted. The same-parity 4-field horizontal motion detection detects faster motion and makes more accurate determinations about where objects are going to move. The morphological operation for noise reduction and adaptive threshold adjusting preserve the actual texture of the original objects. The proposed method achieves cost-efficient hardware implementation with low complexity, low memory usage, and high-speed processing capability. In addition, it consumes less time in producing high-quality images and allows the audience to enjoy a high-quality TV sequence on their progressive devices. The experimental results show that the proposed algorithm is more cost-effective than previous systems.
A concurrent error-detectable module design for FFT processing

Most data in digital signal processing belong to the complex number system. Some characteristics of complex number computations can be utilized to reduce hardware overhead for concurrent error detection (CED) scheme. This paper presents a novel design of CED technique based on realization of direct complex computation approach. It is a time-redundant method and the recomputation step is performed through exchanging strategy on both the real part and imaginary part circuits in a complex function. The hardware overhead then can be eliminated and the capability of error detection is still robust as duplicated module technique. Since pipelined processing can be introduced to kill the recomputation cycle, the fast Fourier transform (FFT) processor based on pipelined butterfly module with the proposed CED technique is able to achieve real-time fault diagnosis. This technique can be applied to other complex number computing systems, and is more attractive especially in high-speed and high-reliability system.<<ETX>>
A hybrid morphology processing units architecture for real-time video segmentation systems

In this paper, we propose a hybrid morphology processing units architecture for real-time video segmentation systems. It contains two parts: a gray-level part and a binary part. A partial-result-reuse technique is applied to reduce the hardware cost of gray-level part. For the target of high throughput and flexibility, the binary part is implemented with a programmable PE array. Simulation shows the proposed hardware architecture is efficient in both hardware complexity and memory organization.
Unsupervised object-based sprite coding system for tennis sport

Sprite coding is a new objected-based coding technology proposed by MPEG-4 video standard. In this paper, we propose an unsupervised sprite coding system for sport videos, for example, tennis sequences. Our system can provide several important functions. First, the sprite of the background can be generated without any pre-processing masks in our system. Second, it can automatically segment the foreground and background in a video sequence. Third, it can provide the masks of the foreground objects and the tennis ball. The experimental results show that our system has a very good performance and the coding gain of our system compared with MPEG-4 advanced simple profile is 2.5 dB at the low bit rate (270 Kbps) and is 2 dB at the ultra low bit rate (70 Kbps). It can be used in the sport video coding at low bit rate and provides a object-based sport video sequence.
System scheduling analysis for high definition multiview video encoder

In recent years, 3D related applications, including 3D movie and 3DTV, are getting more and more attentions. In order to make the real-time 3D applications feasible, efficient multview video coding (MVC) scheme is desired. However, the system throughput requirement on a high definition (HD) MVC encoder is at least two times higher than the current highest throughput H.264/AVC encoder design. In order to meet the target HD MVC specifications, the system scheduling analysis for the HD MVC encoder is performed in this paper. By the 8-stage MB pipeline system architecture with view-parallel MB-interleaved system scheduling and other in-core computation optimizations, the proposed HD MVC encoder design provides about 339% to 1536% higher system throughput than the previous HD H.264/AVC encoder chips[4][5][6] and therefore the real-time HD MVC encoding can be achieved.
Novel word-level algorithm of embedded block coding in JPEG 2000

In this work, a novel word-level algorithm of the embedded block coding in JPEG 2000 is proposed. Unlike conventional approaches, all bitplanes of coefficients are processed in parallel in the proposed algorithm. The algorithm is based on the observations and the analysis of the significant state of a coefficient and its contribution to neighbors. As a result of the analysis, there is only the coding pass of the MSB of a coefficient is the required information for the word-level processing. An algorithm for finding the coding pass of the MSB of a coefficient is also proposed. The number of scans of the entire code block is reduced to two scans and is independent of the number of bit planes.
Stereo video coding system with hybrid coding based on joint prediction scheme

Stereo video systems require double bandwidth and more than twice the computational complexity relative to mono-video systems. Thus, an efficient coding scheme is necessary for transmitting stereo video. We propose a novel stereo video coding system by exploiting a joint prediction scheme which combines three prediction schemes to achieve high coding efficiency and low computational complexity. Joint block compensation improves the visual quality. Motion vector prediction and mode pre-decision utilize the features of stereo video to reduce the computational complexity with up to 8-9 times acceleration. Experiments show that the proposed joint prediction scheme is 2 dB better than MPEG-4 TS and 3 dB better than MPEG-4 SP.
Fast motion estimation with inter-view motion vector prediction for stereo and multiview video coding

3-D video will become one of the most important video technologies in the next generation of television. Due to ultra high data bandwidth requirement for 3-D video, effective compression technology becomes an essential part in the infrastructure. Thus stereo and multiview video coding (MVC) plays a critical role. However, MVC systems require much more computational complexity relative to mono-view video coding systems. Therefore, an efficient prediction scheme is necessary for encoding. In this paper, a new fast motion estimation (ME) algorithm is proposed. By utilizing disparity estimation (DE) to find corresponding blocks between different views, the coding information such as motion vectors can be effectively shared and reused from the coded view channel. Therefore, the computation for ME in most view channels can be greatly reduced. Experimental results show that compared with the full search block matching algorithm applied to both ME and DE, the proposed algorithm saves 95% computation with near-FSBMA quality.