nils-herrmann/clean_scirepeval huggingface dataset:
An efficient VLSI implementation of real-time Kalman filter

An efficient systolic implementation for a real-time Kalman filter is presented. The filter is implemented by propagating the error information matrix. The whole computation for each estimate is done in five processing steps instead of eight by exploiting inherent parallelism in the algorithm. This is achieved by dividing the eight steps into two groups, each of which can be computed simultaneously on a systolic array, thereby reducing the total computation time by 40%. Each processing step follows a modified Faddeev's algorithm which is implemented on a bitrapezoidal array. Using a bitrapezoidal array doubles the throughput obtained by a single trapezoidal array. Techniques used for data skewing and storage organization are efficient, thus reducing the silicon area and complexity of control, and increasing the speed of computation.<<ETX>>
Novel systolic array architecture for the decorrelator using conjugate gradient for least squares algorithm

The decorrelator is a linear transform that can be used in multi-user detection receivers in cellular networks to increase the capacity of the base-station receiver. It has been shown that the decorrelation operation can be performed using iterative methods that do not require computation-intensive inverse matrix computation. We propose a high throughput systolic array architecture for the decorrelator receiver, which meets the throughput demands of 3G mobile communications systems.
B-DTNMOS: a novel bulk dynamic threshold NMOS scheme

Dynamic threshold MOS circuits offer speed and energy saving advantages over the conventional subthreshold MOS circuits; they are faster and consume less energy. In this paper a new Bulk Dynamic Threshold MOS scheme for NMOS transistors (B-DTNMOS) in Domino-like dynamic circuits is introduced. Up to the author's knowledge, this is the first dynamic threshold scheme for NMOS transistors in Bulk-CMOS technology without altering the process technology. In this scheme the common substrate of all the NMOS transistors is connected to the clock signal in dynamic circuits. The proposed scheme is shown to be 63% faster and has 37.2% energy savings compared to the regular subthreshold dynamic MOS circuits. The scheme is shown also to be more robust against temperature and process parameters variations.
An efficient low-bit rate adaptive mesh-based motion compensation technique

This paper proposes a two-stage global motion estimation method using a novel quadtree block-based motion estimation technique and an active mesh model. In the first stage, motion parameters are estimated by fitting block-based motion vectors computed using a new efficient quadtree technique, that divides a frame into equilateral triangle blocks using the quadtree structure. Arbitrary partition shapes are achieved by allowing 4-to-1, 3-to-1 and 2-1 merge/combine of sibling blocks having the same motion vector. In the second stage, the mesh is constructed using an adaptive triangulation procedure that places more triangles over areas with high motion content, these areas are estimated during the first stage. Finally the motion compensation is achieved by using a novel algorithm that is carried by both the encoder and the decoder to determine the optimal triangulation of the resultant partitions followed by affine mapping at the encoder. Computer simulation results show that the proposed method gives better performance that the conventional ones in terms of the peak signal-to-noise ratio (PSNR) and the compression ratio (CR).
Distributed Kalman Filter using fast polynomial filter

Distributed estimation algorithms have received a lot of attention in the past few years, particularly in the fusion framework of Wireless Sensor Network (WSN). Distributed Kalman Filter (DKF) for WSN is one of the most fundamental distributed estimation algorithms for scalable wireless sensor fusion. In the literature, most of DKF methods rely on consensus filter algorithms. The convergence rate of such distributed consensus algorithms is slow and typically depends on the network topology and the weights given to the edges between neighboring sensors. In this paper, we propose a DKF based on polynomial filter to accelerate the distributed average consensus in the static network topologies. The main contribution of the proposed methodology is to apply a polynomial filter on the network matrix that will shape its spectrum in order to increase the convergence rate by minimizing its second largest eigenvalue. The simulation results show that the proposed algorithm increases the convergence rate of DKF by 4 times compared to the standard iteration. The proposed methodology can contribute in the real time WSN's applications.
Low power VLSI architecture for 2D-mesh video object motion tracking

This paper presents a low power VLSI architecture for video object motion tracking. Power has been reduced at both algorithmic and arithmetic levels. The video object is modeled as a 2D hierarchical structured mesh, where the deformation of the mesh represents the dynamics of the object across the video sequence. The algorithm benefits from the small number of bits that describe the mesh topology. Low power has been achieved in the algorithm level by: (1) modeling the mesh into independent triangular patches that can be processed in parallel, (2) each patch is hierarchical triangulated using structured technique, which can be pipelined using simple unit, and (3) using the three steps motion estimation algorithm to simplify the motion estimation of the mesh nodes. On the arithmetic level, low power has been achieved by using multiplication-free affine transformation because of the followed triangle topology. A VLSI architecture is developed based on the proposed algorithm. The architecture consists of two main parts, a mesh-based motion estimation unit and a mesh-based motion compensation unit. The first unit is based on parallel block matching motion estimation to optimize the latency. The second uses parallel threads. Each thread implements a pipelined chain of scalable multiplication-free affine units. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications such as in MPEG-4, and VRML.
Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.
Parallel implementation of a cut and paste maze routing algorithm

Wire routing is a compute bound phase in the design of VLSI circuits. Some of the software solutions to this problem entail divide and conquer methods, such as hierarchical routing, in order to reduce its time complexity. Hardware accelerators have been employed to achieve further increase in the speed of this process. Implementation aspects of a reduced array architecture (RAA) for hardware acceleration of the cut and paste hierarchical routing algorithm are detailed. Several macros are defined to implement the algorithm in hardware. The architecture is implemented in double-metal 2-/spl mu/ CMOS technology.<<ETX>>
Low power video object motion-tracking architecture for very low bit rate online video applications

This paper presents a low power VLSI architecture for video object motion-tracking that can be used in very low bit rate online video applications. Power has been reduced at both algorithmic and arithmetic levels. The video object motion-tracking architecture consists of two main parts, a mesh-based motion estimation unit and a mesh-based motion compensation unit. The mesh-based motion estimation unit implements parallel block matching motion estimation units to optimize the latency. The mesh-based motion compensation unit uses parallel multiplication-free affine core. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications.
Adaptive Techniques for a Fast Frequency Domain Motion Estimation

Dynamic Block Size Motion Estimation (DBS-ME) and smart Dynamic Early Search Termination (DEST) techniques are proposed and implemented in this paper. Both of the proposed techniques are combined and applied to the conventional phase correlation technique. The performance, visual quality and complexity of the proposed techniques are compared to that of the original phase correlation motion estimation (PC-ME) and Full Search Block Matching (FSBM) techniques. The proposed techniques provide an increase in the encoding quality besides a decrease in the computational complexity of ME process. Results show that there is approximately 100% of the stationary blocks decided by the FSBM algorithm are discovered correctly which consequently reduce the computations compared with the original FS and PC techniques. Also it is noted that, DBS-ME technique greatly decreases the computations required for ME process by decreasing the required padding to one or two pixels for both the current and the reference blocks. In addition, the motion field of the proposed algorithm gives much lower entropy than PC-ME which means more reduction in the transmitted bit rate.
Fault tolerant Hopfield associative memory on torus

The associative Hopfield memory, is a very useful artificial neural network (ANN) that can be utilized in numerous applications. Examples include, pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an efficient and fault tolerant algorithm for implementing the Hopfield ANN on a torus parallel architecture. The main advantage of this algorithm is fault tolerance, high performance, and cost effectiveness. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architectures such as the hypercube without the added cost. It requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. Moreover, the developed algorithm has an added advantage over other known algorithms due to its fault tolerance feature, which is based on ABFT techniques. The main advantage of our ABFT (algorithm-based fault tolerance) method over other existing ABFT methods is its ability to detect and correct several faults without any additional hardware overhead (i.e. no extra row or column is needed).
A Lightweight Collaborative Fault Tolerant Target Localization System for Wireless Sensor Networks

Efficient target localization in wireless sensor networks is a complex and challenging task. Many past assumptions for target localization are not valid for wireless sensor networks. Limited hardware resources, energy conservation, and noise disruption due to wireless channel contention and instrumentation noise pose new constraints on designers nowadays. In this work, a lightweight acoustic target localization system for wireless sensor networks based on time difference of arrival (TDOA) is presented. When an event is detected, each sensor belonging to a group calculates an estimate of the target's location. A fuzzyART data fusion center detects errors and fuses estimates according to a decision tree based on spatial correlation and consensus vote. Moreover, a MAC protocol for wireless sensor networks (EB-MAC) is developed which is tailored for event-based systems that characterizes acoustic target localization systems. The system was implemented on MicaZ motes with TinyOS and a PIC 18F8720 microcontroller board as a coprocessor. Errors were detected and eliminated hence acquiring a fault tolerant operation. Furthermore, EB-MAC provided a reliable communication platform where high channel contention was lowered while maintaining high throughput.
Precharged SRAM cell for ultra low-power on-chip cache

This paper proposes an ultra low-power technique to reduce dynamic and leakage power in SRAM. At write mode, the technique reduces the voltage swing required on the bit lines and depends on the cell itself to amplify the small swing to full swing. HSPICE simulation shows 94.2% write power saving in 0.18nm technology. On the sleep mode, the proposed cell reduces the leakage current by 60% for 70nm technology.
Storage allocation strategies for data path synthesis of ASICs

In this paper, we concentrate on the storage allocation problem in datapath synthesis. Datapath allocation techniques can be classified into two main categories: iterative/constructive; and global. Storage allocation deals with determining the number of registers that are needed. Registers are used in datapaths to store values that are generated in one control step and used in an other. When lifetimes of such values do not overlap, they can then be mapped on to the same registers. Just as in the case of functional unit allocation, storage allocation also affects the steering and interconnection logic. Therefore storage allocation must take into consideration minimization of such logic. Storage allocation does not necessarily deal with register allocation. In lieu of registers, register files or memory units can be used to decrease overall area.<<ETX>>
Investigating the feasibility of LEAP+ in ZigBee specification

The ZigBee specification is an emerging wireless technology designed to address the specific needs of low-cost, low-power wireless sensor networks and is built upon the physical and medium access control layers defined in IEEE 802.15.4 standard for wireless personal area networks (WPANs). A key component for the wide-spread success and applicability of ZigBee-based networking solutions will be its ability to provide enhanced security mechanisms that can scale to hundreds of nodes. Currently, however, an area of concern is the ZigBee key management scheme, which uses a centralized approach that introduces well-known issues of limited scalability and a single point of vulnerability. Moreover, ZigBee key management uses a public key infrastructure. Due to these limitations, we suggest replacing ZigBee key management with a better candidate scheme that is decentralized, symmetric, and scalable while addressing security requirements. In this work, we investigate the feasibility of implementing Localized Encryption and Authentication Protocol (LEAP+), a distributed symmetric based key management. LEAP+ is designed to support multiple types of keys based on the message type that is being exchanged. In this paper, we first conduct a qualitative security analysis of LEAP+ and the current ZigBee key management scheme. Using the QualNet 5.0.2 simulator, we implement LEAP+ on the ZigBee platform for the very first time. Experimental results show that a distributed key management scheme such as LEAP+ provides improved security and offers good scalability.
A novel approach towards less area overhead self-healing hardware systems

Self-healing digital systems has been a key approach towards reliable systems. It has been challenging for researchers to find an optimal scalable solution for it. Self-healing is based on redundancy by adding spare cells to replace faulty cells when needed for recovery which makes an area overhead. One of main problem in current self-healing approaches is area overhead because they are based on redundancy (spare blocks). This paper presents an idea for self-healing without using redundancy through embryonic hardware where each cell is a universal cell. Therefore, the area overhead will be lower compared to previous works. The idea is based on using every active block as a spare cell for its neighbor through time multiplexing. In case of faulty cell, the neighbor cell will run its task as well as the task of the faulty cell successively in one clock cycle. The area overhead of the proposed technique is shown to be much lower than compared other approaches relying on spare cells. The proposed solution provides 50% chance of repairing.
A systolic architecture for modulo multiplication

With the current advances in VLSI technology, traditional algorithms for Residue Number System (RNS) based architectures should be reevaluated to explore the new technology dimensions. In this brief, we introduce A /spl theta/(log n) algorithm for large moduli multiplication for RNS based architectures. A systolic array has been designed to perform the modulo multiplication algorithm. The proposed modulo multiplier is much faster than previously proposed multipliers and more area efficient. The implementation of this multiplier is modular and is based on using simple cells which leads to efficient VLSI realization. A VLSI implementation using 3 micron CMOS technology shows that a pipelined n-bit module multiplication scheme can operate with a throughput of 30 M operation per second.
Low-power binding of function units in high-level synthesis

This work considers binding of function units, operating at multiple voltages, in a post-scheduling scenario. The main aim is to minimize the power consumption due to switching activities on the physical adders and multipliers etc. To achieve this, switching activities on the function units are gathered through profiling the data-flow graph of the design by employing random input patterns. The problem of binding is then transformed into a graph-theory problem and solved for optimization of power consumption. Two approaches are considered in this work: a greedy approach, and an optimal approach. Cases are considered when all the resources are operating at the same voltage, as well as, when resources are operating at possibly different voltages.
On reconfigurable fabrics for intelligent hardware systems

Intelligent hardware is an important framework for optimizing hardware based on the operations running, the competing goals and the surrounding changes. The framework relies on three elements to build the system with different granularities in mind and different target applications. In this paper the focus will be on analyzing a reconfigurable fabric which gives the system its flexibility in being adjusted dynamically. Typical performance metrics like area, speed, power are important but another set of proper metrics have to be imposed to analyze and compare different fabric solutions. FPGAs, VRCs and brain-inspired organization were the main systems considered for the reconfigurable fabric in this paper and the analysis shows the advantage of each of them.
An efficient low-bit rate adaptive mesh-based motion compensation technique

This paper proposes a two-stage global motion estimation method using a novel quadtree block-based motion estimation technique and an active mesh model. In the first stage, motion parameters are estimated by fitting block-based motion vectors computed using a new efficient quadtree technique, that divides a frame into equilateral triangle blocks using the quad-tree structure. Arbitrary partition shapes are achieved by allowing 4-to-1, 3-to-1 and 2-1 merge/combine of sibling blocks having the same motion vector. In the second stage, the mesh is constructed using an adaptive triangulation procedure that places more triangles over areas with high motion content, these areas are estimated during the first stage. Finally the motion compensation is achieved by using a novel algorithm that is carried by both the encoder and the decoder to determine the optimal triangulation of the resultant partitions followed by affine mapping at the encoder. Computer simulation results show that the proposed method gives better performance that the conventional ones in terms of the peak signal-to-noise ration (PSNR) and the compression ratio (CR).
A VLSI architecture for 2D mesh-based video object motion estimation

This paper proposes a novel 2D mesh-based object motion estimation architecture that generates a content-based video object. The video object is represented using an alpha plane and a texture. The alpha plane consists of two layers (1) a mesh layer and (2) a binary layer that defines the object boundary. The texture defines the object's colors. The mesh layer is represented by a new adaptive hierarchical mesh. The proposed mesh is formed by recursive triangulation of the initial coarse mesh geometry, which reduces the mesh code. The proposed architecture generates a progressive mesh code. The proposed architecture offers low power performance at the algorithm level as follows: (1) decomposing the mesh into independent triangular patches that can be processed in parallel, (2) using a hierarchical structured triangulation technique, that simplify the processing unit, and (3) using the three steps motion estimation algorithm to simplify the motion estimation of the mesh nodes. The proposed architecture is suitable for very low bit rate online applications and it can be used as a building block for an MPEG-4 codec.
A VLSI architecture for hierarchical mesh based motion compensation using scalable affine transformation core

This paper presents a VLSI architecture for hierarchical mesh based motion compensation. It uses a hierarchical adaptive structured mesh, which minimizes the number of bits describing the mesh. The mesh is constructed as triangular patches that describe the motion at different resolutions. Image warping is used to reconstruct the frame, whereas an affine transformation is used to texture map the triangular patches. The architecture implements a scalable affine transformation core, which can be used with any level of hierarchical mesh. The architecture has been prototyped and performance measures have been conducted. The prototype can be used as building block for MPEG-4 codec.
Energy scavenging and storage using through silicon vias to reduce power consumption in 3D ICs

Through silicon vias (TSV) are an enabler for high performance Three Dimensional Integrated Circuits (3DIC). TSVs are used for signal, power and ground lines in 3DICs. TSVs used to carry signals can induce noise in nearby circuitry and in those instances shielding is required. Traditional shielding is composed of guard rings surrounding the signal TSVs or if the signal is differential in nature, a careful arrangement of TSVs carrying the differential signals can aid in noise reduction. In the guard ring scenario, the guard rings are typically tied to ground. This paper proposes a technique for energy scavenging utilizing the guard rings for shielding TSVs. Energy absorbed by the guard rings can be stored for later use by the system. This paper examines the feasibility of configuring the guard rings to charge a decoupling capacitor instead of shunting energy to ground. It is shown that the decoupling capacitor can be charged using this method and that under certain conditions, the overall power of the system can be reduced by 4% to 15%.