nils-herrmann/clean_scirepeval huggingface dataset:
Pixel-Level Image Fusion Scheme based on Linear Algebra

Image fusion refers to the process of integrating complementary image sources from multiple imaging sensor such that the resulting fused image improves the performance of computational analysis tasks such as segmentation, feature extraction and object recognition. The paper introduces a pixel-level image fusion scheme based on linear algebra. The image fusion process begins by computing the discrete wavelet transform of the source images. Then, the wavelet transform of the images are fused using a feature-based rule. A salient feature may extend to several pixels; therefore, a rule that can include a region of pixels containing it results in a more efficient integration. The fusion rule is based on a measurement of the linear dependency of a small window centered on the pixel under consideration. The linear dependency measurement is the Wronskian determinant that is a simple and rigorous test. The performance assessment of the proposed method is established by using mutual information measurement as well as root mean square error and peak signal to noise ratio. The simulation results show that the proposed method is an efficient approach to image fusion.
Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays

A systolic temporal arithmetic (STA) formalism suitable for describing arithmetic operations in dynamic environments is introduced. It can be used for formal specification and verification of systolic arrays at the array architecture level. Besides providing value and operation abstraction from the lower level, it also exploits several features of systolic arrays, such as synchrony, regularity, repeatability, modularity, pipelinability, parallel processing ability, and spatial and temporal locality. STA provides constructs and verification techniques for simple, efficient, and effective systolic-array specification and verification. Verification techniques such as mathematical induction are suggested to exploit these systolic array features so as to speed up the process. STA overcomes several limitations of other existing specification and verification techniques and can be used with lower-level formalism for multilevel reasoning of systolic arrays. A brief description of this formalism and examples of how the formalism can be applied for formal specification and verification of two systolic arrays are discussed. Other applications of STA, such as simulations, fault diagnoses, and test generation for systolic arrays, are also suggested.
An efficient frequency domain intra prediction for H.264/AVC

This paper presents an efficient intra prediction implementation for H.264/AVC in the frequency domain. Intra prediction in the frequency domain is vital for transform domain heterogeneous video transcoding in wireless and mobile networks. A limited computation capabilities constraint constitutes a burden over such networks. New distributed intra prediction arithmetic is proposed with only addition and shift operations for transform domain intra prediction modes computations. Compared to previous attempts the proposed method reduces the computations extensively by eliminating the expensive matrix multiplications and omits the need for excessive memory storage.
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family

We present a new dynamic-like static circuit family called feedback-switch logic (FSL) that is suitable for high-speed low-power applications. FSL is a derivative of cascode voltage switch logic (CVSL) family. However, it does not suffer from the contention problems of clockless CVSL, and it consumes much less power than clocked CVSL (dual-rail domino). FSL gates offer fast switching, reduced capacitance, and input-switching dependent activity factor without the need of clock connection. An 18-bit majority voting circuit is simulated in a 90-nm technology, in order to compare static, clockless CVSL, dual-rail domino and FSL. Simulation results show that FSL reduces delay by 21% compared to static logic, and offers at least 46% power reduction compared to dynamic dual-rail domino logic with two-phase skew-tolerant clocking.
Hardware architecture for fast Intra mode and direction prediction in real-time MPEG-2 to H.264/AVC transcoder

In this article, we propose a hardware architecture for our fast Intra mode and direction prediction algorithm to accelerate the MPEG-2 to H.264/AVC transcoding devices. In order to eliminate the redundant operations in the transcoder, our implemented algorithm uses the DCT coefficients from the MPEG-2 decoder to predict the Intra mode and reconstruction direction for the H.264/AVC encoder. In addition, the Intra prediction process in the H.264/AVC part of the transcoder has been dramatically accelerated by using our full-search elimination technique. The empirical results show 92% reduction in the transcoding time while reducing the PSNR for less than 3.5%. The proposed architecture has achieved an operating frequency of 323MHz at a power consumption of 112 mW when implemented on Virtex-5 FPGA Development Board.
A new low power building block cell for adders

One of the main factors in developing low power systems is reducing power consumption at the circuit design level and the module building block levels in the design. Following this strategy a low power and high speed full adder cell with the minimum number of transistors has been developed. The proposed cell is a combination of a 3-input XOR gate and transmission gates. The proposed cell has been compared to the other three basic common cells. An extensive analysis of the four architectures of adders, namely carry ripple, carry skip, carry select and carry lookahead has proved the superiority of the proposed cell.
Novel formulations for low-power binding of function units in high-level synthesis

This paper considers minimizing the switchings of the function units through new binding formulations. Switching activities on the function units are gathered through profiling the data-flow graph of the design at hand. Several thousand random input streams are generated and used for such profiling. The switching activities are obtained and stored in a matrix. The problem of binding the function units for low power is then formulated and solved by using the proposed methods.
Structure generation and design of tracking ADCs

In this paper, a new model for a low power CMOS current-mode Tracking Analog-to-Digital Converter (ADC) is proposed. The model generates several designs that differ in power consumption and signal bandwidth specifications. As an example, A 6-bit ADC, with a maximum acquisition speed of 130 MHz, is implemented in a 1 V analog supply voltage. Spectre simulation results for the proposed tracking ADC verifying the analytical results are also given. It shows that the circuit consumes a static power of 0.63 mW and a dynamic power of 0.49 mW in a commercial 90 nm CMOS process.
A memory efficient architecture for compressed-domain texture feature extraction

Texture is a useful feature for representing the content of many real-world images. In order to reduce the time and memory overhead of traditional decode-process texture feature extraction systems, a compressed-domain approach is needed. This paper presents a new technique and hardware solution for obtaining accurate texture features from the compressed domain while using less memory and computational time. The architecture achieves these savings by reducing and simplifying the calculations performed. The design uses simple modules and can easily be extended to include a wide variety of image sizes and bit rates.
Enhanced Parallel Interference Cancellation using Decorrelator for the base-station receiver

Multi-user detection is a paradigm that is used to enhance the performance of the receivers in cellular networks in terms of Bit Error Rate (BER), capacity and near-far effect. Parallel Interference Cancellation is the choice for most current multi-user detection receivers because of its simplicity in implementation and good qualitative parameters. Decorrelator-based Parallel Interference Cancellation (PIC) has been proposed to improve the performance of the PIC receiver. In this paper, we make an important observation about the determination of the Decorrelator that makes it feasible for it to be used in conjunction with PIC in the base-station receiver.
Crosstalk noise analysis in ultra deep submicrometer technologies

In ultra deep submicron (UDSM) circuit design, the interconnect delay and noise have become the dominant factors in determining circuit performance. Analytical expressions are preferred because simulation is always expensive and ineffective in use with modern designs containing millions of transistors and wires. However, analytical expressions are not sufficiently accurate and do not consider all of interconnect and driver parameters. In this paper, we analyze the effects of all known interconnect and driver parameters on the crosstalk peak noise, crosstalk noise pulse width, and the impact of coupling on aggressor delay. We consider parameters like spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, direction of the signals, wire width for both the aggressors and the victim wires. Also, we consider parameters like driver strength as several recent studies considered the simultaneous device and interconnect sizing.
Compressed-domain classification of texture images

Traditional decompress-process methods for texture feature extraction consume valuable time and memory resources. This paper proposes a method for calculating wavelet energy texture features directly from a wavelet-compressed symbol stream. The proposed method requires little decompression and results in a technique that is efficient and requires less memory than traditional approaches. This reduction is accomplished through the elimination of both multiplication operations and the storage of zero-valued coefficients, which have no effect on these features. The developed algorithm has been implemented at various compression ratios, and in each case, the classification results are nearly identical to those obtained with the traditional method.
ULSI design-for-manufacturability: a yield enhancement approach

Yield enhancement is a quintessential objective of the
semiconductor industry. With diminishing feature size and increasing
chip area, the amount of “functional” silicon on a chip is
too expensive to discard in the event of short- and open-circuit faults.
Designing chips with high tolerance against faults, therefore, holds
great promise for profitable manufacturing in the semiconductor
industry. In this paper, we present an algorithm for integrated circuit
yield enhancement in the routing phase of layout synthesis. The focus is
on detailed routing. The proposed algorithm reduces layout critical area
for short circuits due to two-dimensional spot defects. Critical area
reduction is achieved in both horizontal and vertical layers without any
penalties on net length or channel density. Results show yield
improvement of 15-25% from the application of the proposed algorithms
Fast Motion Estimation System Using Dynamic Models for H.264/AVC Video Coding

H.264/AVC offers many coding tools for achieving high compression gains of up to 50% more than other standards. These tools dramatically increase the computational complexity of the block based motion estimation (BB-ME) which consumes up to 80% of the entire encoder's computations. In this paper, computationally efficient accurate skipping models are proposed to speed up any BB-ME algorithm. First, an accurate initial search center (ISC) is decided using a smart prediction technique. Thereafter, a dynamic early stop search termination (DESST) is used to decide if the block at the ISC position can be considered as a best match candidate block or not. If the DESST algorithm fails, a less complex style of the motion estimation algorithm which incorporates dynamic padding window size technique will be used. Further reductions in computations are achieved by combining the following two techniques. First, a dynamic partial internal stop search technique which utilizes an accurate adaptive threshold model is exploited to skip the internal sum of absolute difference operations between the current and the candidate blocks. Second, a dynamic external stop search technique greatly reduces the unnecessary operations by skipping all the irrelevant blocks in the search area. The proposed techniques can be incorporated in any block matching motion estimation algorithm. Computational complexity reduction is reflected in the amount of savings in the motion estimation encoding time. The novelty of the proposed techniques comes from their superior saving in computations with an acceptable degradation in both peak signal-to-noise ratio (PSNR) and bit-rate compared to the state of the art and the recent motion estimation techniques. Simulation results using H.264/AVC reference software (JM 12.4) show up to 98% saving in motion estimation time using the proposed techniques compared to the conventional full search algorithm with a negligible degradation in the PSNR by approximately 0.05 dB and a small increase in the required bits per frame by only 2%. Experimental results also prove the effectiveness of the proposed techniques if they are incorporated with any fast BB-ME technique such as fast extended diamond enhanced predictive zonal search and predictive motion vector field adaptive search technique.
Transition Skew Coding for Global On-Chip Interconnect

This paper presents new simulation results of the previously proposed transition skew coding (TSC) for global on-chip interconnects. Considering 2-GHz global clock frequency at the 90-nm node, we show that TSC can be applied to broad range of wire length on both semiglobal and global metal layers, while maintaining its energy efficiency and its advantages in terms of crosstalk reduction and signal integrity, and wiring and repeater area minimization.
A scalable architecture for discrete wavelet transform

We present the design and prototyping of an efficient systolic architecture which performs both forward and inverse discrete wavelet transform. The proposed architecture consists of a linear array of processing elements, each of which has an adder and a multiplier and fixed number of I/O channels. The wavelet transform is computed by convolution and by mapping the computation on to a linear array of systolic processing elements. The design of the architecture has been shown to be simple, scalable and has the advantage of low I/O bandwidth. The number of processing elements is independent of the size of the input. The architecture has been prototyped using 2/spl mu/m p-well CMOS technology and has been developed in the CADENCE Edge Design Framework environment.
Implementable Spike Sorting techniques for VLSI wireless BCI/BMI implants: A survey

Brain Computer/Machine Interface (BCI/BMI) has a great potential in solving many handicapped people's problems (e.g. restoring missing limb functionality) via neural controlled implants. However, the main problems with BCI implants are: the open wound problems, the implant size and the needed power. This limits the usability of BCI implants for patients. Therefore, a wireless VLSI approach can provide a feasible solution for medically safe and usable implants. Spike Sorting play a major role in power consumption and area within the BCI signal processing stages. Thus, this study provides a survey and an analysis of the Signal Processing and Spike Sorting methods being used or proposed for VLSL wireless BCI Implants, along with a suggested design and a set of recommendations as a step closer to real-life BCI implants.
A low power and reduced area carry select adder

A carry select adder (CSA) can be implemented by using a single adder block and an add-one circuit instead of using dual adder blocks. The add-one circuit is based on "first" zero detection logic and a few multiplexers. In the modified CSA, one of the n-bit adder blocks is replaced by an add-one circuit consisting of fewer transistors. This scheme considerably reduces the power and area, with negligible speed penalty. For 8-bit length, n=8, this modified CSA requires 38% fewer transistors and consumes only 73% of the power, compared to the conventional design, using a 0.5 /spl mu/m CMOS technology.
The challenges towards energy-efficient cognitive radio networking

The Cognitive Radio (CR) technology is envisioned as a primary solution to the spectrum scarcity problem in future wireless communication networks. Cognitive radio networking allows the exploitation of unutilized spectrum in an opportunistic manner, and thereby, improves the efficiency of the spectrum utilization. Cognitive radio Networks (CRNs) provide wireless connectivity via heterogeneous wireless architectures and dynamic spectrum access techniques. The enabling technologies and the benefits of CR and CRNs have received significant research and industry interest. However, the energy efficiency of such technologies has received far less interest. In this paper, we shed the light on the move towards energy-efficient CRN that fits the global vision of green communication networks.
A systematic framework for high throughput MAP decoder VLSI architectures

The paper presents a systematic method for the development of high throughput MAP decoder architectures. High throughput is achieved by exploiting more algorithmic parallelism. The paper proposes the use of the trellis-time graph to study the parallel MAP decoder architectures analytically. A parameterized windowing approach is developed to construct the trellis-time graph of the decoding operation. Next, an exhaustive search is used to explore the parallelism vs. hardware resources systematically. This method is applied towards the design of a MAP decoder that has a frame of size 320 bits. A tradeoff among the decoding delay, number of kernels, number of BMM banks, and number of SMM banks is presented.
Reliable modulo systolic arrays for DSP algorithms

The algebraic and structural properties of a residue number system (RNS) to optimize the design of DSP (digital signal processing) systolic arrays is discussed. RNS establishes parallelism on the algorithmic level by decomposing the original computational field into a set of finite fields, in which arithmetic operations are performed independently for each field. The impact of the moduli size on the structural choices is analyzed. Three different structures, namely, word-parallel, bit-parallel, and bit-serial, are presented. Redundant RNS has fault tolerance capabilities. An efficient fault-detection technique is developed as an alternative to the standard procedure based on a mixed radix algorithm. A finite-impulse-response (FIR) filter algorithm is used as a case study.<<ETX>>
Fast deep pyramid DPM object detection with region proposal networks

Object detection is fundamental for realization of self-driving cars and smart traffic management. Various vision based techniques are based on Deformable part models (DPMs) and recently convolutional neural network (CNN) for its anticipated high precision. The DeepPyramid DPM model maps DPM into multiple CNN layers as an assembly of the two concepts with intensive computations. While the recent Region Proposal Network (RPN) allows convolutional layers sharing with further detection steps to accelerate Fast R-CNN. Our framework employs these cost-free RPN proposals and DenseNet with Fast Fourier Transform (FFT) to introduce a faster and more accurate class independent and region based DeepPyramid DPM detector. Our evaluation on four different benchmarks shows that our technique processes PASCAL VOC at 20 fps and VGA images at 14 fps on a GPU (about 12x faster than DeepPyramid DPM with better precision).
High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications

A high speed and area-efficient merged multiply accumulate (MAC) units is proposed in this work. To realize the area-efficient and high speed MAC unit proposed in this work, first we examine the critical delays and hardware complexities of conventional MAC architectures to derive at a unit with low critical delay and low hardware complexity. The new architecture is based on binary trees constructed using a modified 4:2 compressor circuits. Reducing the overall area is achieved by the full utilization of the compressors instead of putting zeros in free inputs. Increasing the speed of operation is achieved by avoid using the modified compressor in the critical path. Feeding the bits of the accumulated operand into the summation tree before the final adder helps to increase the speed too. The proposed MAC unit and the previous merged MAC unit are mapped on a field programmable gate array (FPGA) chip, in order to compare between them. The simulation result shows that the proposed system for 8-bit, 16-bit, and 32-bit MAC unit reduces area by 6.25%, 3.2 %, and 2.5% and increases the speed by 14%, 16%, and 19% respectively. The experimental test for the proposed 8-bit MAC is done using XESS demo board (XSA-100, Spartan-X2S100tq144).
Synthesizing DSP architectures from behavioral specifications: a formal approach

A formal behavioral synthesis framework is introduced for specification, simulation, and synthesis of digital signal processing (DSP) algorithms. The given algorithm is represented using a newly developed language called the algorithm specification language (ASL). The components and connectivity of the synthesized architecture can be represented in three different forms: a language called the realization specification language (RSL), schematic captures, and PROLOG. PROLOG is used as a user interface language between the user subsystem and the synthesis subsystem. Algorithms of linear time complexity are introduced for transferring between different representations.<<ETX>>
A Survey on the power and robustness of FinFET SRAM

For the last decade, SRAM has been used for high density, high performance, and ultra-low power consumption system-on-chip (SoC) and mobile applications. That has been achieved by an aggressive feature size scaling, which resulted in severe and non-tolerant degradation in the device physical characteristics represented by the Short Channel Effect (SCE), high leakage current and robustness problems. Moreover, SRAM stability became a critical design parameter under deep-scaled feature technology. Since planar CMOS reached the limits in shrinking the device, a new promising candidate for extreme scaled CMOS devices has emerged to overcome the previous mentioned problems and enhance the device performance. Thus, FinFET SRAM comes as the alternative to substitute Si-bulk SRAM. In this survey paper, different FinFET schemes based on both device level and SRAM circuit level are addressed and compared. Also, design challenges issues for FinFET SRAM are addressed.
Variable-way set associative cache design for embedded system applications

Variable-way set associative cache is proposed as a new technique to maximize the cache performance especially for embedded applications or to reduce the power consumption with the same performance. Static profiling is used to determine the sets' behavior of the set-associative cache. Variable-way set-associative can be used in high-performance or low-power operation modes. Each set in the proposed design basically has different associativity to maximize the total performance for the cache size or reduce the power consumption. The proposed architecture is simulated on SimpleScalar simulator and tested on several Spec2000 Benchmarks. The results show on average 2% reduction in the miss rate at the high-performance mode and up to 43% reduction of the power consumption at low-power mode.