nils-herrmann/clean_scirepeval huggingface dataset:
Energy-balancing task allocation on wireless sensor networks for extending the lifetime

Extending the wireless sensor network's lifetime has been the aim of several research efforts. Distributed in-network processing arises as a viable solution to extend the network's lifetime. It avoids assigning heavy computations to a single node which might otherwise lead to its significant energy depletion. Task scheduling and allocation play a major role in the efficiency of the distribution. This work proposes EBSEL, an e̲nergy-b̲alancing task s̲cheduling and allocation heuristic whose main purpose is to e̲xtend the network's l̲ifetime, through energy balancing. Balancing the energy consumption among the nodes can help avoid the disintegration of the network where some nodes die unnecessarily, while others still have high energy reserve. EBSEL was extensively simulated on random task graphs and on a task graph of a real-world application. Compared to related work, EBSEL achieved more than 50% increase in lifetime and up to 5% energy savings per iteration.
Area-Efficient NEDA Architecture for The 1-D DCT/IDCT

A new distributed arithmetic has been applied to the 1-D DCT to produce a low power, high throughput architecture. In this paper, we apply NEDA to the even-odd decomposition matrices of the 8times8 forward and inverse DCT. We show that, with the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8times8 DCT and IDCT matrices. This reduction results in power savings, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding
Three-dimensional discrete wavelet transform architectures

The three-dimensional (3-D) discrete wavelet transform (DWT) suits compression applications well, allowing for better compression on 3-D data as compared with two-dimensional (2-D) methods. This paper describes two architectures for the 3-D DWT, called the 3DW-I and the 3DW-II. The first architecture (3DW-I) is based on folding, whereas the 3DW-II architecture is block-based. Potential applications for these architectures include high definition television (HDTV) and medical data compression, such as magnetic resonance imaging (MRI). The 3DW-I architecture is an implementation of the 3-D DWT similar to folded 1-D and 2-D designs. It allows even distribution of the processing load onto 3 sets of filters, with each set performing the calculations for one dimension. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The 3DW-II architecture uses block inputs to reduce the requirement of on-chip memory. It has a central control unit to select which coefficients to pass on to the lowpass and highpass filters. The memory on the chip will be small compared with the input size since it depends solely on the filter sizes. The 3DW-I and 3DW-II architectures are compared according to memory requirements, number of clock cycles, and processing of frames per second. The two architectures described are the first 3-D DWT architectures.
Low power SOVA architecture using bi-directional scheme

The soft output Viterbi algorithm (SOVA) is the main building block in the turbo coding receiver. A major problem in implementing SOVA is the high complexity and hence high power consumption. In this paper we present a low power SOVA architecture. Low power optimization is performed on the system level using a bi-directional scheme to increase the throughput of SOVA then trading throughput by reducing the power supply voltage. The prototype adheres to the third generation wireless standard. Evaluated results shows that power consumption could be reduced by 50% with about twice the increase in area.
A low power prototype for a 3D discrete wavelet transform processor

This paper presents a low power prototype of a 3-D discrete wavelet transform processor. It illustrates the design flow used in developing the prototype, and the mapping and verification starting from the high level modeling of the chip design and concluding with the low level implementation details at the transistor level. The main application of this architecture is toward 3-D MRI data, but other applications will benefit from the 3-D DWT as well, such as digital broadcast. The processor has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype processor is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype, area, time delay, power and utilization have been evaluated. The prototype operates at an estimated frequency of 272 MHz and dissipates 0.5 W of power. The prototype processor uses a 16-bit adder, 16-bit Booth multiplier and 1 KB cache with a maximum of 64-bit data bandwidth. Lower power has been achieved by using low power building blocks and the minimal number of computational units with high throughput.
An application-specific array architecture for feedforward with backpropagation ANNs

An application-specific array architecture for Artificial Neural Networks (ANNs) computation is proposed. This array is configured as a mesh-of-appendixed-trees (MAT). Algorithms to implement both the recall and the training phases of the multilayer feedforward with backpropagation ANN model are developed on MAT. The proposed MAT architecture requires only O(log N) time, while other reported techniques offer O(N) time, where N is the size of the largest layer. Beside the high speed performance, pipelining of more than one input pattern can be achieved which further improves the performance.<<ETX>>
General chairs' welcome

In Cajun slang, Lagniappe means something extra, and ICASSP 2017 is really a Lagniappe. On behalf of ICASSP 2017 and IEEE Signal Processing Society, I welcome you to the beautiful and historic city of New Orleans. New Orleans is the heart of great bayous; the melting pot of Cajun, Zydeco, and Creole cultures; the capital of Jazz music; and the home of Mardi Gras.
A controller chip for a scaleable ATM switch node

This paper presents the architecture of the control chip for an Asynchronous Transfer Mode (ATM) chipset, used in a distributing banyan network. This chip, with 4 switch chips, forms a scaleable 16/spl times/16 switching element that runs at 155 MHz. It is larger and much more efficient than previous switching nodes. The architecture uses shared multibuffering, since it is less bandwidth limited than a shared buffering switch. Such criteria make the switch more scaleable, although the control logic increases in complexity. Very high performance is required of the chip and thus a number of special circuits have been created to achieve this performance. The chip has been prototyped in 1.0 micron CMOS using a mixture of static and dynamic logic.
De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips

Multi-level caches are used in multiprocessor systems to exploit locality of data and decrease the bandwidth demands on the network. Apart from exploiting locality in large-scale networks, we must also amortize the cost of distant communication so as to reduce memory request latency which is a critical determinant of multiprocessor performance. Our proposed architecture called the De-Cache ($De) architecture exploits the nature of the network-on-chip (NoC) structure by introducing what we called detour caches to store data from the most distant physical memory locations closer to the requesting node. Our experiments show that by using our proposed $De architecture we can decrease the memory request latency up to approximately 29.0% with very little degradation to the network performance.
EB-MAC: An event based medium access control for wireless sensor networks

Efficiency in any wireless sensor based application relies significantly on the medium access control it implements. It is not likely that we will see in the near future a unified MAC protocol for wireless sensor networks that is suitable for all wireless sensor applications. In this context, we propose an event based medium access control (EB-MAC) that is tailored for event based systems. Typically, event based systems are characterized by having long periods of inactivity and short abrupt periods of high data contention when an event is detected. High data traffic is generated simultaneously from all sensors detecting the event to deliver captured data. EB-MAC arranges data transfer dynamically using an election based scheduling technique. When data transfer begins, each sensor at a time starts sending data packets in a contention free environment. The protocol is implemented on MicaZ sensor motes where it showed efficiency in reliability, throughput and energy conservation. The algorithm is compared with an implementation of B-MAC with RTS/CTS on MicaZ where it showed its superiority in throughput and latency.
A fast block-based motion estimation using early stop search techniques for H.264/AVC standard

H.264/AVC is a new video coding standard of the ITU-T video coding expert group which has a significant improvement in the rate distortion efficiency compared with the previous standards. However, there is an exhaustive motion search across multiple block sizes and multiple reference frames leading to a linear increase in processing time. Although, the encoding quality is improved, the complexity of the encoder and computational cost are also increased at the same time. In this paper, we reduce the computational cost by reducing the number of candidate pixels required for the sum of absolute difference for each block (SAD) using two early stop search techniques. These techniques are applied on two scan search patterns (raster and spiral search patterns) and compared with the conventional full search (FS), three step search (TSS), and diamond search (DS) algorithms. Results show that there is at least 98% reduction in computations with a maximum loss of 0.1 dB compared with the conventional FS algorithm.
A compact single-pass architecture for hysteresis thresholding and component labeling

Hysteresis thresholding offers enhanced edge/object detection in the presence of noise. However, due to its recursive nature, it requires a lot of memory and execution time. Thus, it is restricted and sometimes totally avoided in streaming processors with limited memory. We propose an efficient architecture coupling hysteresis thresholding with component labeling and feature extraction in a single pass over the image pixels. The operations are performed on the fly while recycling labels to avoid additional passes for handling candidate pixels and extracting object features. Moreover, only one row of compact labels is buffered. Hence, the execution speed of the algorithm is increased and the memory requirements are drastically reduced when compared to state of the art techniques. When implemented on FPGA, this technique promises to offer even more speed up and efficient resource utilization.
An efficient two's complement systolic multiplier for real-time digital signal processing

The authors propose a fast, area-efficient, bit-parallel systolic architecture for two's complement multiplication, which can be implemented on a single VLSI chip. This architecture is more efficient than other reported bit-parallel architectures in terms of performance and utilization of silicon area. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are employed on the cell level instead of a basic full adder, which increases the throughput rate by a factor of three over the other reported pipeline structures. The structure is highly regular and programmable, and it can be adapted to the requirements of different digital signal processing applications without significant loss in throughput and efficiency.
Optimal Probabilistic Encryption for Secure Detection in Wireless Sensor Networks

We consider the problem of secure detection in wireless sensor networks operating over insecure links. It is assumed that an eavesdropping fusion center (EFC) attempts to intercept the transmissions of the sensors and to detect the state of nature. The sensor nodes quantize their observations using a multilevel quantizer. Before transmission to the ally fusion center (AFC), the senor nodes encrypt their data using a probabilistic encryption scheme, which randomly maps the sensor's data to another quantizer output level using a stochastic cipher matrix (key). The communication between the sensors and each fusion center is assumed to be over a parallel access channel with identical and independent branches, and with each branch being a discrete memoryless channel. We employ J-divergence as the performance criterion for both the AFC and EFC. The optimal solution for the cipher matrices is obtained in order to maximize J-divergence for AFC, whereas ensuring that it is zero for the EFC. With the proposed method, as long as the EFC is not aware of the specific cipher matrix employed by each sensor, its detection performance will be very poor. The cost of this method is a small degradation in the detection performance of the AFC. The proposed scheme has no communication overhead and minimal processing requirements making it suitable for sensors with limited resources. Numerical results showing the detection performance of the AFC and EFC verify the efficacy of the proposed method.
Robust object tracking using correspondence voting for smart surveillance visual sensing nodes

This paper presents a bottom-up tracking algorithm for surveillance applications where speed and reliability in the case of multiple matches and occlusions are major concerns. The algorithm is divided into four steps. First, moving objects are detected using an accurate hybrid scheme with selective Gaussian modeling. Simple object features balancing speed, reliability, and complexity are then extracted. Objects are matched based on their spatial proximity and feature similarity. Finally, correspondence voting solves multiple match conflicts, segmentation errors, and occlusion cases. This approach is very simple, which makes it suitable for implementation at smart surveillance visual sensing nodes. Moreover, the simulation results demonstrate its robustness in detecting occlusions and correcting segmentation errors without any prior knowledge about the objects models or constraints on the direction of their motion.
Multi-dimensional systolic networks for DSP algorithms

The authors present a novel technique for transforming a class of digital signal processing (DSP) algorithms, and some arithmetic algorithms, to specific forms that can be directly mapped onto higher-dimensional systolic networks. The latency, as well as the order of complexity of computation time, can be significantly improved through implementing these algorithms on higher-dimensional systolic networks. At the same time, the order of area complexity is kept constant. The technique can be applied to problems such as 1-D convolution, k-point discrete Fourier transform (DFT), finite-impulse response (FIR) filters, and matrix-vector multiplication. The k-point DFT algorithm example is illustrated along with other examples. Implementation issues of high-dimensional systolic networks on 2-D or 3-D VLSI are discussed.<<ETX>>
A systolic array for image segmentation using split and merge procedure

A systolic array architecture for image segmentation by a split and merge procedure is proposed. This architecture enhances the I/O and memory bandwidth requirements, which leads to speeding up the computation time of the segmentation of an image. The system structure is defined in terms of its interconnections and host computer interface along with other structural and behavioral considerations. Image segmentation through the proposed approach can be achieved in linear time.<<ETX>>
The Hierarchical Hypercube: A New Interconnection Topology for Massively Parallel Systems

Interconnection networks play a crucial role in the performance of parallel systems. This paper introduces a new interconnection topology that is called the hierarchical hypercube (HHC). This topology is suitable for massively parallel systems with thousands of processors. An appealing property of this network is the low number of connections per processor, which enhances the VLSI design and fabrication of the system. Other alluring features include symmetry and logarithmic diameter, which imply easy and fast algorithms for communication. Moreover, the HHC is scalable; that is it can embed HHC's of lower dimensions. The paper presents two algorithms for data communication in the HHC. The first algorithm is for one-to-one transfer, and the second is for one-to-all broadcasting. Both algorithms take O(log/sub 2/ k), where k is the total number of processors in the system. A wide class of problems, the divide & conquer class (D&Q), is shown to be easily and efficiently solvable on the HHC topology. Parallel algorithms are provided to describe how a D&Q problem can be solved efficiently on an HHC structure. The solution of a D&Q problem instance having up to k inputs requires a time complexity of O(log/sub 2/ k).
Parallel arithmetic: from algebra to architecture

A demonstration of how to use the mathematical properties of available algebraic theory for developing optimized computations on efficient architectures is presented. A systematic description of the theoretical concepts of the algebra of surrogate fields that constitute the foundations of quadratic residue arithmetic is presented. Using the properties of the quadratic residue number system for developing complex digital signal-processing architectures is explained through the design of a fast Fourier transform processor.<<ETX>>
A Low Complexity Inter Mode Decision for MPEG-2 to H.264/AVC Video Transcoding in Mobile Environments

This paper presents a fast variable block size Inter mode decision algorithm suitable for low complexity MPEG-2 to H.264/AVC heterogeneous video transcoding in mobile environments. Macroblock Inter coding mode prediction in H.264/AVC represents almost 70% of its computational complexity. An efficient transcoder would take advantage of the information stored in MPEG-2 bitstream (ex. motion vectors, DCT coefficients, etc.) to simplify macroblock mode decision in H.264/AVC. The proposed Fast Variable Block Size Inter Mode Decision (FVBSMD) algorithm conditionally reuse MPEG-2 motion vectors along with only few DCT coefficients to eliminate unnecessarily complexity from H.264/AVC variable block size motion re-estimation process. Simulations results; using video sequences with different motion complexities, resolutions and frame rates; show about 80% computational complexity elimination with only a 0.2dB and 2.5% degradation in PSNR and bit-rate respectively.
Adaptive search window size algorithm for fast motion estimation in H.264/AVC standard

H.264/AVC is a new recommendation for moving picture coding, in which a lot of new techniques are used for improving encoding efficiency and reducing the bit-rate. However, it involves an exhaustive motion search across multiple block sizes and multiple reference frames leading to a linear increase in processing time. Although, the encoding quality is improved, the complexity of the encoder and computational cost are increased at the same time. We reduce the computational cost by reducing the search space without significant loss in quality. Results show that there is at least 90% reduction in computation with a maximum loss of
A cluster-based key management framework for resource constraint networks

In this work, we propose a Cluster-based framework to be used for a resource constraint network. The proposed framework includes any pre-distribution key establishment schemes. It allows mobility and provides efficiency and security. We provide two instantiations to support our claim that the proposed framework improves security and scalability of the used keying establishment schemes. We develop analytical models and conduct extensive simulations to evaluate the security and performance of the proposed framework under different scenarios.
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively
Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation]

The paper describes the design and implementation of an 8 /spl times/8 2D DCT chip for use in low-power applications. The design exploits a coefficient distributed arithmetic (CoDA) scheme as opposed to the prevalent data distributed arithmetic (DDA) schemes to achieve low power consumption. The architecture uses no ROMs and uses minimum number of additions by exploiting the redundancy in the adder arrays. The described architecture for the CoDA scheme is implemented on FPGA and has been fabricated on silicon. The fabricated chip computes 8 /spl times/8 2D DCT @ 50 MHz consuming around 137mW of power.
New Wireless Sensors Networks: The Art of Integration

Integrating Computers, Communication, Sensing, and Microelectronics technologies in an orchestrated systems have opened new frontiers in our life; in entertainment, business, handling disasters and emergencies, health care, warfare, etc. Wireless Sensor Networks (WSNs) reflects such integration, it is a prototype of these new systems. WSNs are based on collaborative efforts of a large number of sensor nodes. They should be low-cost, low-power, and multifunction. These nodes have the capabilities of sensing, data processing, and communicating. High performance sensor node is another example of integration of various technologies; CMOS, MEMS, synchronous, asynchronous, static, dynamic,..etc, on the same chip. Wireless Sensor Networks have a wide range of applications; from monitoring sensors in industrial facilities for controlling and management energy applications to military and security fields. Because of the special features of these networks, new network technologies are needed that focused on low power, reliable communication, and low cost. The new network protocols and architectures should take into consideration the special features of WSNs such as: the large number of nodes, their failure rate, limited power, high density,.. etc. In this talk the impact of wireless sensor networks is addressed, examples of the design, communication, and technological issues are given. A case study of an SoC sensor node processor, designed at our lab., is demonstrated.
On on-chip intelligence paradigms

Hardware Intelligence is an attractive concept that has the potential to make electronic, industrial and reliability-oriented applications efficiently optimized. This work investigates different frameworks and analyzes their challenges. Hardware automation faces different challenges like scalability, overhead, testability as well as goal definition. For better classification, hardware systems are mapped to different layers with different granularities of reconfiguration, monitoring and decision making. An Intelligent Hardware Stack (IHW) is proposed to differentiate these layers showing which techniques can be mapped to which layer. IHW stack presented in this paper showcase different substrates essential for the process like monitoring, reconfiguration and decision making.