nils-herrmann/clean_scirepeval huggingface dataset:
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition

This paper presents a power-gating structure that employs a staggered-phase damping technique for suppressing power and ground rails fluctuation and stabilization time during mode-transition. Two same type sleep devices coupled to two clusters in a single power domain are switched-on at different time instants such that the turn-on time of one of these is delayed by half the resonant oscillation period relative to the turn-on time of the other. The same can be generalized to plurality of clusters where one set of sleep devices switch at the first time instant and the other set switch at the said second time instant. This technique was evaluated in a 1-V 90-nm CMOS technology in the context of a 3-stage 16-bit Carry-Select-Adder (CSA) component, and compared with the parallel sleep transistor technique that is based on reducing the instantaneous excitation current. Results show that the present technique reduces peak noise by 33.2% compared to standard power-gating structure, and achieves a settling time reduction of 4.03× and 3.21× compared to standard and parallel sleep transistor power-gating structures, respectively.
A framework for fair performance evaluation of 1-bit full adder cells

Evaluating the performance measures of a full adder (FA) cell depends on the input test pattern, and on the circuit structure used for simulation. The issue gets more complicated when evaluating several parameters such as time delay, area, power dissipation, and driving capability at the same time. In this paper a framework for evaluating and comparing 1-bit FA cells is proposed. The framework consists of an input test pattern which can give accurate speed, and power consumption figures, plus two circuit simulation structures that test the performance of adder cells in a proper context. 25 different full adder cells, collected from the literature, are evaluated and ranked using the proposed framework, which ensures fair comparison basis.
An efficient mapping algorithm of multilayer perceptron on mesh-connected architectures

This paper presents a new efficient parallel implementation of neural networks on mesh-connected SRMD machines. A new algorithm to implement the recall and training phases of the multilayer feedforward network with back-error propagation is devised. The developed algorithm is much faster than other known algorithms; it requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. The proposed algorithm maximizes parallelism by unfolding the ANN computation to its smallest computational primitives and processes these primitives in parallel.
An efficient low-bit rate adaptive mesh-based motion compensation technique

This paper proposes a two-stage global motion estimation method using a novel quadtree block-based motion estimation technique and an active mesh model. In the first stage, motion parameters are estimated by fitting block-based motion vectors computed using a new efficient quadtree technique, that divides a frame into equilateral triangle blocks using the quad-tree structure. Arbitrary partition shapes are achieved by allowing 4-to-1, 3-to-1 and 2-1 merge/combine of sibling blocks having the same motion vector. In the second stage, the mesh is constructed using an adaptive triangulation procedure that places more triangles over areas with high motion content; these areas are estimated during the first stage. Finally the motion compensation is achieved by using a novel algorithm that is carried by both the encoder and the decoder to determine the optimal triangulation of the resultant partitions followed by affine mapping at the encoder. Computer simulation results show that the proposed method gives better performance that the conventional ones in terms of the peak signal-to-noise ratio (PSNR) and the compression ratio (CR).
Parameterized modeling of open-circuit critical volume for three-dimensional defects in VLSI processing

In this paper, we study the impact of three-dimensional (3-D) physical defects on the functionality of integrated circuit (IC) structures. A practical extension to Pineda de Gyvez and Dani's (1992) method of IC critical volume modeling for open-circuits due to 3-D defects is presented. According to their approach, an open-circuit may result only when any two of the three dimensions of the defect are greater than the corresponding dimensions of the conducting pattern. In this way, their treatment can be considered more of a physical than electrical in nature. We analyze the increase in the resistance of a conductor due to the presence of a defect. The maximum tolerable increase in the resistance of a conductor is considered as the criterion for an open-circuit. Based on this analysis, new analytical expressions for critical volume are obtained. Some suggestions are made regarding yield modeling in presence of 3-D defects in integrated circuits.<<ETX>>
Performance analysis for a new automatic error control system for overcoming turbulent fading errors for wireless ATM networks

This paper suggests and analyzes the performance of a new wireless ATM adaptive error control system, which can be used in wireless ATM networks to improve quality of service in keeping the cell loss under a certain predefined limit and reducing the average delay of cell encoding. The new system is based on multi-level forward error correction (FEC), and specifically the Bose-Chaudhuri-Hocqenghem (BCH) code, which has multiple error correcting capability and a wide class of block codes, to overcome random errors. Realistic error patterns caused by multipath turbulent fading are analytically approximated and applied to the suggested system. Performance analysis for the new system showed that it improves cell loss rate to a value of less than 10/sup -9/ in case of non-fading and it keeps the average cell loss close to a reasonable value (approximately 10/sup -7/) in case of fading, while maintaining an average encoding delay considerably less than the delay of a system using a fixed BCH correction capability.
Efficient Mapping Algorithm of Multilayer Neural Network on Torus Architecture

This paper presents a new efficient parallel implementation of neural networks on mesh-connected SIMD machines. A new algorithm to implement the recall and training phases of the multilayer perceptron network with back-error propagation is devised. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architecture such as hypercube, without the added cost; it requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. The proposed algorithm maximizes parallelism by unfolding the ANN computation to its smallest computational primitives and processes these primitives in parallel.
A motion-estimation architecture based on band-matching

An algorithmic specific architecture has been developed based on the newly introduced band-matching algorithm (BDMA) for computing motion vectors. The BDMA offers better performance than both the fixed size and variable size block matching algorithms as it uses less vectors and only processes the relevant parts of the image instead of the whole image. The main modules of the BDMA architecture are the encoder and decoder. The memory in the encoder is classified into three types: storing images, storing the image of difference, storing the bands. The first memory is arranged in parallel banks which will enhance the performance considerably. In the second memory, registers are used for temporary storage during filtering. The third memory is used for storing the bands. A single code book is employed to identify the type of edges.
The land of pixels hosts ICIP 2009 [Conference Spotlight]

Cairo, Egypt, will host the 2009  Con ference on Image Processing (ICIP) 7?11 November 2009. This is the first time that ICIP will be held in the Middle East and only the second time that any major IEEE Signal Processing Society conference, ICASSP or ICIP, is taking place in this region (the first conference was ICASSP, which took place in Istanbul). ICIP 2009 is one of the main Society initiatives to reach out and have a signal processing global impact.
Real-time VLSI architecture for detection of moving object using Wronskian determinant

Several computer vision applications require reliable object detection. Traditionally detection algorithms have been implemented solely in software. Object detection in upcoming wireless visual sensors has a need of hardware implementation with requirements of low power and small area. This paper introduces a hardware implementation of a real-time change detector based on Wronskian Determinant. This detection algorithm offers regularity, low complexity and accuracy as well as robustness against global illumination changes. The proposed architecture is able to process incoming frames on-the-fly, therefore requiring a small amount of memory. The maximum frame rate is 15 fps, however the implementation is flexible enough to allow analysis of less frames if required. Processing unit consist of a basic processing element implemented in pipeline fashion and adder tree to produce final results. The architecture was implemented using a XCV800 FPGA. The power consumption of the whole system is 121 mW
Models for VLSI implementation of residue number system arithmetic modules

This paper discusses the implementation of RNS arithmetic modules using VLSI technology. The modules are based on the interconnection of read-only memory look-up tables. The paper first outlines a memory model for a single look-up table which allows the selection of the most efficient layout for memories which do not have power of 2 dimensions. The paper then discusses various examples of interconnected memory modules with associated optimizing layout algorithms. Finally, an example is given of the application of one of the modules to a large prime modulus multiplier.
Fault-current limiter with thyristor-controlled impedance

A new fault current limiter with thyristor-controlled impedance (FCL-TCI) is proposed. The FCL-TCI helps in improving the steady-state stability limit, while providing an effective reduction of short circuit current during the fault. Analytical, experimental and computer simulation studies on a working model are conducted. The effects on improvement of stability limits and reduction of the short-circuit current are shown using the experimental model. The economical benefits of the FCL-TCI are due to the extension of the useful life of the existing circuit breakers and power transformers, and to the improvement in the performance of the transmission line.
A merged multiplier-accumulator for high speed signal processing applications

In an attempt to improve the speed of signal processing VLSI systems, a new architecture for high speed Multiply Accumulate Units is proposed. The architecture is based on Binary trees constructed using 4-2 compressor circuits. Increasing the speed of operation is achieved by taking advantage of the available free input lines of the 4-2 compressors, which result from the parallelogram shape of the generated partial products, and using the bits of the accumulated value to fill in these gaps. This results in merging the accumulation operation within the multiplication process. An 8-bit Multiplier Accumulator prototype circuit using the proposed architecture is prototyped in 0.35 micron double metal CMOS technology and simulated using hspice. Simulation results at 3.3 V show that the proposed architecture has a delay of 4.26 ns with a 16.8 delay savings. At 150 MHz operating frequency, the power consumption is 324 mWatts with a 23.04% power saving compared to other architectures not using the merging technique.
Cost-Efficient and Robust On-Demand Video Transcoding Using Heterogeneous Cloud Services

Video streams, either in the form of Video On-Demand (VOD) or live streaming, usually have to be converted (i.e., transcoded) to match the characteristics of viewers’ devices (e.g., in terms of spatial resolution or supported formats). Transcoding is a computationally expensive and time-consuming operation. Therefore, streaming service providers have to store numerous transcoded versions of a given video to serve various display devices. With the sharp increase in video streaming, however, this approach is becoming cost-prohibitive. Given the fact that viewers’ access pattern to video streams follows a long tail distribution, for the video streams with low access rate, we propose to transcode them in an on-demand (i.e., lazy) manner using cloud computing services. The challenge in utilizing cloud services for on-demand video transcoding, however, is to maintain a robust QoS for viewers and cost-efficiency for streaming service providers. To address this challenge, in this paper, we present the Cloud-based Video Streaming Services (CVS2) architecture. It includes a QoS-aware scheduling component that maps transcoding tasks to the Virtual Machines (VMs) by considering the affinity of the transcoding tasks with the allocated heterogeneous VMs. To maintain robustness in the presence of varying streaming requests, the architecture includes a cost-efficient VM Provisioner component. The component provides a self-configurable cluster of heterogeneous VMs. The cluster is reconfigured dynamically to maintain the maximum affinity with the arriving workload. Simulation results obtained under diverse workload conditions demonstrate that CVS2 architecture can maintain a robust QoS for viewers while reducing the incurred cost of the streaming service provider by up to 85 percent.
Novel high-throughput EBCOT architecture for JPEG2000

Embedded block coding with optimized truncation (EBCOT) consumes more than 50% of the processing time in JPEG200 encoding system. Hardware implementation with careful handling for the control nature of tier-1 is essential. Although, some architectures have been developed to speed up the coding operations, they still require a tedious checking mechanism to decide if each sample is eligible or not for coding. We propose a novel checking scheme for the three coding passes for EBCOT that works in parallel with the encoding process to achieve the required high throughput. The simulation results show that the proposed architecture increases the throughput by 19% on average compared, to other well known architectures.
A building block chip for a scaleable ATM architecture

In this paper, a building block chip for a scaleable ATM switch architecture is developed. The architecture is based on a modified banyan interconnection network of this chip. Crossbar technology is employed for the switch chip. A prototype of the switch chip is implemented in Dynamic/Static/C/sup 2/MOS 2.0 micron technology using the Cadence tools environment. The performance of the chip has been optimized using a full custom design approach and a mix of technologies. The developed prototype supports a data rate of 155.52 Mb/s with a high speed of 155.52 MHz using serial inputs and outputs, and a lower speed of 38.88 MHz using four bit wide parallel inputs and outputs. The developed system and chip are fully scaleable up to a size of 256 by 256 channels, which could easily be extended in future versions.
Enhanced low power motion estimation VLSI architectures for video compression

Power consumption is very critical for portable video applications. During compression, the largest portion of power is consumed in the Motion Estimation part, which requires a huge amount of computation. This paper presents an architectural enhancement to reduce the power consumption during full-search block-matching (FSBM) motion estimation without sacrificing throughput or optimality. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between our enhancement and others is presented based on simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements.
Novel clock gating techniques for low power flip-flops and its applications

Two new clock gated flip-flops are presented. The designs are based on new clock gating approaches to reduce the consumption of clock signal's switching power. They operate with no redundant clock cycles and have reduced number of transistors to minimize the overhead and to make it suitable for data signals with higher switching activity. The proposed flip-flops are used to design 8-bit successive approximation register. This application has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using Spectre. Simulations with the inclusion of parasitics have shown the effectiveness of the new approaches on power consumption and transistor count.
Towards Autonomic Network Performance Management in mobile ad hoc networks

The performance of mobile ad hoc network is influenced by a number of factors, such as protocol selections, parameter settings, wireless channel conditions, network size, transmission ranges, and traffic loads. In this work, we present an Autonomic Network Performance Management (ANPM) framework for ad hoc networks. The proposed framework follows a control-theoretic approach and is designed to monitor, model, optimize, and configure the controllable node and systemlevel factors to satisfy global performance goals. The functional components of the ANPM framework are presented along with a case study of establishing a call center in a disaster recovery operation using MANET. In the case study, tuning the performance of the overall network performance is shown through: (1) changing whole network protocols, and (2) changing settings within the network protocols.
A 108 Gbps, 1.5 GHz 1D-DCT architecture

A high-performance ID-DCT architecture is proposed. It is based on the New Distributed Arithmetic Architecture algorithm (NEDA). Enhancements to NEDA are proposed to reduce the number of computations. Only addition operations are used, with 42 additions to compute the outputs for a 8/spl times/1 DCT. No subtractions, multiplications, or ROM are needed. High-throughput is achieved by pipelining the architecture. In every clock cycle, it receives eight pixels (each is 9-bits) as inputs, and produces eight DCT coefficients (each is 14-bits). The delay of one pipeline stage is the delay of a 3-level 4:2 compressor tree. The architecture is implemented in 0.35 /spl mu/m technology; it runs at 1.5 GHz, and processes 108 Gbps of image/video sequence data.
Energy-efficient XOR gate with embedded level conversion for serial-link encoding

The insatiable demand for increased energy-efficient communication bandwidth has led to the widespread adoption of serial-links. Serializer/Deserializer (SerDes) architectures have seen considerable use in both inter — and intra-chip communication of high-performance computing platforms and embedded systems. Serializers translate m-bit parallel data into a serial stream of increased data rate. Bus encoding can lower the activity factor of the link to mitigate energy consumption. Additional savings can be gained by partitioning the supply voltage at the serializer boundary to capitalize on the difference in parallelism. However, the required voltage level conversion increases complexity and delay. In this work, a new method of gate-embedded level conversion is demonstrated within a XOR gate for the purpose of constructing a serializer-encoder. We explore existing level converters, as well as, the ramifications of level conversion before and after serial bus encoding. Results show the complementary pass-transistor logic (CPL)-based level converters have the best energy delay product (EDP) of those compared yielding 0.8fJ/bit at 4Gb/s.
Novel design methodology for high-performance XOR-XNOR circuit design

As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are some of the characteristics for DSM circuits. A novel design methodology for the design of energy-efficient noise-tolerant XOR-XNOR circuits that can operate at low voltages is proposed. The proposed circuits are characterized and compared with previously published circuits for reliability and energy efficiency. To test their driving capability, the proposed gates are implanted in an existing 5-2 compressor design and are shown to provide superior performance. The average noise threshold energy is used for quantifying the noise immunity. Simulation results show that the proposed circuits are more noise-immune and displays better power consumption results as well as power-delay product characteristics. Also, the circuits prove to be faster and successfully work at all ranges of supply voltage starting from 0.6 V to 3.3 V.
New bulk dynamic threshold NMOS schemes for low-energy subthreshold domino-like circuits

Dynamic threshold MOS circuits offer speed and energy saving advantages over the conventional subthreshold CMOS circuits; they are faster and consume less energy. In this paper a new bulk dynamic threshold MOS scheme for NMOS transistors (B-DTNMOS) in domino-like dynamic circuits is introduced. In this scheme the substrate of all the NMOS transistors is connected to the clock signal in dynamic circuits. The proposed scheme is shown to be 63% faster and has 37.2% energy savings compared to the regular subthreshold CMOS circuits.
Smart-flooding: A novel scheme for fault-tolerant NoCs

The shrinking in device sizes brings about an increase in effects of noise sources and process variations, thus leading to increased faults and decreased chip yields in deep submicron systems. We propose a new fault-tolerant scheme called smart-flooding to fight both transient and permanent faults in networks-on-chips (NoCs). Smart-flooding tries to flood messages in cases where permanent faults have occurred, while end-to-end retransmission is used in cases of transient errors. Our experiments show that the proposed scheme exhibits a high performance while maintaining the level of fault-tolerance seen in regular flooding algorithm.
Implementation of NEDA-based DCT architecture using even-odd decomposition of the 8 × 8 DCT matrix

New Distributed Arithmetic has been been applied to the 1-D DCT to produce a low power, high throughput architecture. In previous work, we applied NEDA to the even-odd decomposition matrices of the 8 × 8 forward and inverse DCT. With the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8 × 8 DCT and IDCT matrices. This reduction results in few adders needed, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding. In this paper, we present the results of the implementation for the forward DCT using 4:2 compressor trees where needed to decrease the delay and show the results obtained from synthesizing the design in 0.18¿ technology using Cadence BuildGates.