nils-herrmann/clean_scirepeval huggingface dataset:
An efficient and low power architecture design for motion estimation using global elimination algorithm

This paper presents a new algorithm and architecture for motion estimation. The proposed global elimination algorithm (GEA) is derived from successive elimination algorithm (SEA). The main idea is to remove the branches of SEA to make data flow more regular and suitable for hardware. Besides, the processing time per motion vector for GEA is fixed, no initial guess is required, and the skipping ratio of search positions can be fixed within frames and is even higher than 99%. The average PSNR of compensated frames is almost the same (within 0.1 dB) as that of full-search block matching algorithm (FBMA). An architecture composed of a systolic part, an adder tree, and a comparator tree is also developed for GEA. Simulation results show our design outperforms many FBMA architectures in normalized processing capability per gate and normalized power at gate level.
2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications

A 2.8 to 67.2 mW H.264 encoder is implemented on a 12.8 mm2 die with 0.18 mum CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock.
IC design of an adaptive Viterbi decoder

We implement an integrated circuit (IC) design for a decoder of a 64-state binary convolutional code. The decoder is based on a reduced-state adaptive Viterbi algorithm (VA) for which the decoding speed is faster than the standard VA while the error performance remains almost the same. With the adaptive VA, less bits are needed to store and to calculate the metrics of the decoding trellis and less power dissipation is needed, as compared to the standard VA. The IC design is based on a 0.8 /spl mu/m CMOS technology. The number of quantization levels in the decoding is Q=8.
Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques

Automatic video segmentation plays an important role in real-time MPEG-4 encoding systems. Several video segmentation algorithms have been proposed; however, most of them are not suitable for real-time applications because of high computation load and many parameters needed to be set in advance. This paper presents a fast video segmentation algorithm for MPEG-4 camera systems. With change detection and background registration techniques, this algorithm can give satisfying segmentation results with low computation load. The processing speed of 40 QCIF frames per second can be achieved on a personal computer with an 800 MHz Pentium-III processor. Besides, it has shadow cancellation mode, which can deal with light changing effect and shadow effect. A fast global motion compensation algorithm is also included in this algorithm to make it applicable in slight moving camera situations. Furthermore, the required parameters can be decided automatically, which can enhance the proposed algorithm to have adaptive threshold ability. It can be integrated into MPEG-4 videophone systems and digital cameras.
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

Using the lifting scheme to construct VLSI architectures for discrete wavelet transforms outperforms using convolution in many aspects, such as computation complexity and boundary extension. Nevertheless, the critical path of the lifting scheme is potentially longer than that of convolution. Although pipelining can reduce the critical path, it will prolong the latency and require more registers for a 1D architecture as well as larger memory size for a 2D line-based architecture. In this paper, an efficient VLSI architecture is proposed to provide a variety of hardware implementations for improving and possibly minimizing the critical path and memory requirements of lifting-based discrete wavelet transforms by flipping conventional lifting structures. By case studies of a JPEG2000 defaulted filter and an integer filter, the efficiency of the proposed flipping structure is shown.
A cortex-like model for rapid object recognition using feature-selective hashing

Building models by mimicking the structures and functions of visual cortex has always been a major approach to implement a human-like intelligent visual system. Several feed-forward hierarchical models have been proposed and perform well on invariant feature extraction. However, less attention has been given to the biologically plausible feature matching model which mimics higher levels of the ventral stream. In this work, with the inspirations from both neuroscience and computer science, we propose a framework for rapid object recognition and present the feature-selective hashing scheme to model the memory association in inferior temporal cortex. The experimental results on 1000-class ALOI dataset demonstrate its efficiency and scalability of learning on feature matching. We also discuss the biological plausibility of our framework and present a bio-plausible network mapping of the feature-selective hashing scheme.
ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor

A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor is implemented in 90nm CMOS technology. A reconfigurable hardware architecture with heterogeneous stream processing and subword-level parallelism is implemented to accelerate the vision processing for smart-camera applications. The area efficiency reaches 111.329 GOPS/mm2. The power efficiency and area efficiency are 4.5x to 33.0x and 3.8x to 74.2x better than the state-of-the-art works, respectively.
Robust moving object tracking and trajectory prediction for visual navigation in dynamic environments

We propose a robust and efficient moving object detection system with trajectory prediction mechanism for mobile visual applications in dynamic environments. The navigation system not only supports intelligent moving object detection and collision avoidance, but also provides automatic trajectory prediction mechanism to create a safe environment for the user. To take into account recognition challenges in practice, the system addresses problems of camera shake and image blurs caused by mobile camera and fast moving objects, respectively. Experimental results show our system supports 97.1% detection rate for fast moving objects and achieves high accuracy of trajectory prediction with error estimation less than 16.5 cm.
Block-based Vanishing Line and Vanishing Point Detection for 3D Scene Reconstruction

This paper presents a robust and reliable block-based method for vanishing line and vanishing point detection. The proposed method provides assistance in construction of a depth map, which is a necessity of 3D scenes. Moreover, the method focuses on the fundamental image structural element analysis, and divides them into six successive steps. Furthermore, complicated mathematic calculation and approximation are replaced by six block-based estimation algorithms. Also, the method is a regular algorithm design which is suitable for VLSI design on future 3D applications.
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264

Variable block size motion estimation is adopted in the new video coding standard, MPEG-4 AVC/JVT/ITU-T H.264, due to its superior performance compared to the advanced prediction mode in MPEG-4 and H.263+. In this paper, we modified the reference software in a hardware-friendly way. Our main idea is to convert the sequential processing of each 8/spl times/8 sub-partition of a macro-block into parallel processing without sacrifice of video quality. Based on our algorithm, we proposed a new hardware architecture for variable block size motion estimation with full search at integer-pixel accuracy. The features of our design are 2-D processing element array with 1-D data broadcasting and 1-D partial result reuse, parallel adder tree, memory interleaving scheme, and high utilization. Simulation shows that our chip can achieve real-time applications under the operating frequency of 64.11 MHz for 720/spl times/480 frame at 30 Hz with search range of [-24, ] in horizontal direction and [-16, +15] in vertical direction, which requires the computation power of more than 50 GOPS.
Parallel global elimination algorithm and architecture design for fast block matching motion estimation

The critical path of the hardware for the global elimination algorithm (GEA) is too long to meet the real-time constraints for high-end applications. In this paper, we propose a new parallel GEA and its corresponding architecture. By dividing candidate blocks into independent groups and finding the most probable candidates of each group in parallel, instead of sequentially searching within the whole search range, parallel design can be developed as an array of GEA processing elements with much shorter critical path. Besides, the GEA processing element is optimized to reduce 30% of the gates, and the 2D data reuse is organized to save 80% of the SRAM bandwidth, which also reduces a lot of power. Simulation results show that our implementation can achieve real time processing of D1 30 Hz video with search range as H[-64, +63.5] V[-32, ] while the operating frequency is 70 MHz, and the gate count is 113 K. Compared with full search, our gate count is six times smaller under the same frequency, and the PSNR loss is at most 0.1-0.2 dB.
Density-based hardware-oriented classification for spike sorting microsystems

Successful proof-of-concept laboratory experiments on cortically-controlled brain computer interface motivate continued development for neural prosthetic microsystems (NPMs). One of the research directions is to realize realtime spike sorting processors (SSPs) on the NPM. The SSP detects the spikes, extracts the features, and then performs the classification algorithm in realtime in order to differentiate the spikes for the different firing neurons. Several architectures have been designed for the spike detection and feature extraction. However, the classification hardware is missing. To complete the SSP, a density-based hardware-oriented classification algorithm is proposed for hardware implementation. The traditional classification algorithms require a considerable memory space to store all the training features during the processing iteration, which results in a considerable power and area for the hardware. The proposed one is designed based on the density map of the spike features. The density map can be accumulated on-line with the coming of the spike features. Therefore the algorithm can save significant memory space, and is good for efficient hardware implementation.
Simple and effective algorithm for automatic tracking of a single object using a pan-tilt-zoom camera

This paper presents a simple but effective algorithm for a pan-tilt-zoom camera to automatically track a single moving object. The proposed tracking algorithm is suitable for but not limited to stationary background, and it can tolerate reasonable noise and light change. The main idea is to initially capture the background information and to calculate the difference between incoming frame and background buffer. Block-based processing is adopted to reduce computation and to alleviate noise effects. Skin-color detection is combined with spatial and temporal information to let the camera more likely to focus on human faces. Even more, the tracking algorithm can be integrated with region-of-interest video coding, which allocates more bits for human faces to produce better subject views. Many practical situations have been tested and the simulation results show that the proposed tracking algorithm is useful for surveillance systems.
IP design of a reconfigurable baseline JPEG coding

IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly.
A Chip Architecture for Compressive Sensing Based Detection of IC Trojans

We present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a circuit under test (CUT). We describe our designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Our architecture achieves approximately a 10X speedup and 1000X reduction in output bandwidth while incurring a small area overhead.
A predictive parallel motion estimation algorithm for digital image processing

An efficient block matching algorithm (BMA) for motion estimation is presented. This BMA exploits motion correlation of neighbor blocks in the temporal direction to reduce the search area. Instead of finding the 2D motion vector directly, this BMA finds two 1D displacements in parallel on two axes independently within the reduced search area. Simulation results show that this algorithm can rival conventional BMAs for performance. The hardware-oriented features of this BMA guarantee that it is more suitable for the hardware realization of a VLSI motion estimator.<<ETX>>
Error concealment algorithm using interested direction for JPEG 2000 image transmission

Digital image transmission is widely used in consumer products, e.g., digital camera and cellular phone, etc. The newly defined JPEG 2000 delivers image with lower bit rate in the Internet and wireless communications. However, JPEG 2000 decoding is processed bitplane by bitplane. Any data loss in bitstream affects the consequent bitplanes and even possible destroy the whole picture. We propose a new algorithm to recover the damaged bitplanes data according to the interested directional sets (IDS) of in-subband. The proposed algorithm is quite simple, but is very efficient in concealing the loss data of any subband in streaming real-time video data in the Internet and wireless communications. The simulation results show that the proposed algorithm has 1.5-3dB improvements than previously presented error resilient mechanism. In a subjective view, the proposed concealment algorithm can achieve much smoother edges on the reconstructed images.
A VLSI architecture design of VLC encoder for high data rate video/image coding

An efficient architecture of variable length coding (VLC) is developed for recent multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.
Low power strategy about correlator array for CDMA baseband processor

This paper discusses the design, implementation, and performance evaluation of a low powered correlator architecture for multi-code CDMA systems. In CDMA systems, correlators are used to de-spread the received signals and are important blocks for RAKE receivers. We proposed a low powered correlator architecture to de-spread input with several PN sequence concurrently, According to our preliminary simulation results, the suggested architecture can de-spread the input signal with two PN codes simultaneously and save 41% power consumption compared with traditional correlator architecture.
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder

MPEG-4 Fine Granularity Scalability (FGS) provides bandwidth adaptation and error resilience features for streaming applications. In this paper, by estimating the required computational power for FGS in a video encoding system, an efficient FGS implementation method is exploited. With the proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to provide a cost-effective solution to FGS implementation. The proposed hardware core can support profile level 5, frame size 720/spl times/576, 30Hz, for real-time streaming applications at 54 MHz.
Memory efficient architecture for belief propagation based disparity estimation

This paper introduces a memory efficient architecture for belief propagation based disparity estimation. To find the bottleneck of the memory, a lifetime analysis of the exchanged message is presented. The analysis leads to architecture which can take advantage of the data characteristics resulting in memory reduction, computing resource and memory access. In the experimental result, the proposed architecture gains 20% speed up in software simulation compared to non-optimized counterpart. In hardware implementation, more than 42% area is reduced by this architecture design without affecting the performance. With further design effort 61.8% area reduction is achieved.
Word-Level Parallel Architecture of JPEG 2000 Embedded Block Coding Decoder

This paper presents a word-level decoding architecture of embedded block coding in JPEG 2000. This architecture decodes one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column- switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show that the proposed architecture is capable of decoding 54 MSamples/s at 54 MHz, which can support HDTV 720p (1280 times 720, 4:2:2) decoding at 30 frames/s.
Fast decomposition of filterbanks for the state-of-the-art audio coding

This letter derives fast decomposition for the quadrature mirror filterbanks (QMFs) of the low power spectral band replication (SBR) tools in the MPEG high efficiency advanced audio coding (HE AAC) decoder. In contrast with the standard method where computation-intensive matrix operations are employed in the QMF, the proposed method decomposes the matrix operations into conventional discrete cosine transform of type II and III (DCT-II and DCT-III) and simple permutations for easy implementation. The computational complexity can be also reduced effectively by using fast algorithms for DCT.
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications

A 5mW MPEG4 SP encoder is implemented on a 7.7mm2 die in 0.18mum CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption
An efficient linear-phase FIR filter architecture design for wireless embedded system

This paper presents a novel approach for implementing power-efficient finite impulse response (FIR) filters that require less power consumption than traditional FIR filter implementations in wireless embedded systems. The proposed schemes impose to the direct form and achieve a certain reduction in the power consumption. A novel retimed structure and balanced modularized techniques are introduced and used to reduce the critical path to achieve hardware efficiency. A novel separated signed processing data flow scheme with modifying CSD (canonical signed digit) representation is also introduced and used to reduce the transition, which is the main source of power consumption. The combination of the proposed methods gives up to 71% reduction in power consumption with a slight area overhead.
Predictive watershed: a fast watershed algorithm for video segmentation

The watershed transform is a key operator in video segmentation algorithms. However, the computation load of watershed transform is too large for real-time applications. In this paper, a new fast watershed algorithm, named P-watershed, for image sequence segmentation is proposed. By utilizing the temporal coherence property of the video signal, this algorithm updates watersheds instead of searching watersheds in every frame, which can avoid a lot of redundant computation. The watershed process can be accelerated, and the segmentation results are almost the same as those of conventional algorithms. Moreover, an intra-inter watershed scheme (IP-watershed) is also proposed to further improve the results. Experimental results show that this algorithm can save 20%-50% computation without degrading the segmentation results. This algorithm can be combined with any video segmentation algorithm to give more precise segmentation results. An example is also shown by combining a background registration and change-detection-based segmentation algorithm with P-Watershed. This new video segmentation algorithm can give accurate object masks with acceptable computation complexity.
Scalable implementation scheme for multirate FIR filters and its application in efficient design of subband filter banks

A scalable implementation scheme for multirate FIR filters in consideration of both the processing time and the silicon area is presented in this paper. According to our various requirements, the flexible and efficient implementation scheme can simultaneously reduce both the time cost T to 1/kT and the area cost A to k/MA (M is the decimation or interpolation rate, k is any factor of M). Furthermore, by employing the scalable implementation scheme, we also propose an efficient design technique for subband filter banks.
Optimal Transform of Multichannel Evoked Neural Signals Using a Video Compression Algorithm

One of the most important problems in the field of biomedical engineering is how to record a multichannel neural signal. This problem arises because recording produces a large amount of data that must be reduced to transfer it through wireless transmission, and data reduction must be made without compromising data quality. Video compression technology is very important in the field of signal processing, and there are many similarities between multichannel neural signals and video signals. Therefore, we use motion vectors (MVs) to reduce the redundancy between successive video frames and successive channels. We also test what transform for neural signal compression is best. Our novel signal compression method gives a signal-to-noise ratio (SNR) of 25 db and compresses data to 5% of the original signal.
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform

The on-chip line buffer dominates the total area and power of line-based 2-D discrete wavelet transform (DWT). In this paper, a memory-efficient VLSI implementation scheme for line-based 2-D DWT is proposed, which consists of two parts, the wordlength analysis methodology and the multiple-lifting scheme. The required wordlength of on-chip memory is determined firstly by use of the proposed wordlength analysis methodology, and a memory-efficient VLSI implementation scheme for line-based 2-D DWT, named multiple-lifting scheme, is then proposed. The proposed wordlength analysis methodology can guarantee to avoid overflow of coefficients, and the average difference between predicted and experimental quality level is only 0.1 dB in terms of PSNR. The proposed multiple-lifting scheme can reduce not only at least 50% on-chip memory bandwidth but also about 50% area of line buffer in 2-D DWT module.