nils-herrmann/clean_scirepeval huggingface dataset:
One-Pass Computation-Aware Motion Estimation With Adaptive Search Strategy

A computation-aware motion estimation algorithm is proposed in this paper. Its goal is to find the best block-matching results in a computation-limited and computation-variant environment. Our algorithm is characterized by a one-pass flow with adaptive search strategy. In the prior scheme, Tsai et al. propose that all macroblocks are processed simultaneously, and more computation is allocated to the macroblock with the largest distortion among the entire frame in a step-by-step fashion. This implies that random access of macroblocks is required, and the related information of neighboring macroblocks cannot be used to be prediction. The random access flow requires a huge memory size for all macroblocks to store the up-to-date minimum distortions, best motion vectors, and searching steps. On the contrary, our one-pass flow processes the macroblocks one by one, which can not only significantly reduce the memory size but also effectively utilize the context information of neighboring macroblocks to achieve faster speed and better quality. Moreover, in order to improve the video quality when the computation resource is still sufficient, the search pattern is allowed to adaptively change from diamond search to three step search, and then to full search. Last but not least, traditional block matching speed-up methods are also combined to provide much better computation-distortion curves
An efficient architecture for two-dimensional inverse discrete wavelet transform

This paper proposes an efficient architecture for the two-dimensional inverse discrete wavelet transform (2D IDWT). The proposed architecture includes an inverse transform module, a RAM module, and a multiplexer. In the inverse transform module, we employ the coefficient folding technique and the polyphase decomposition technique to the interpolation filters of stages 1 and 2, respectively. The RAM size is N/2/spl times/N/2. The advantages of the proposed architecture are the 100% hardware utilization, fast computing time, regular data flow, and low control complexity, making this architecture suitable for next generation image coding/decoding systems.
Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC

In the new video coding standard H.264/AVC, motion estimation (ME) is allowed to search multiple reference frames. Therefore, the required computation is highly increased, and it is in proportion to the number of searched reference frames. However, the reduction in prediction residues is mostly dependent on the nature of sequences, not on the number of searched frames. Sometimes the prediction residues can be greatly reduced, but frequently a lot of computation is wasted without achieving any better coding performance. In this paper, we propose a context-based adaptive method to speed up the multiple reference frames ME. Statistical analysis is first applied to the available information for each macroblock (MB) after intra-prediction and inter-prediction from the previous frame. Context-based adaptive criteria are then derived to determine whether it is necessary to search more reference frames. The reference frame selection criteria are related to selected MB modes, inter-prediction residues, intra-prediction residues, motion vectors of subpartitioned blocks, and quantization parameters. Many available standard video sequences are tested as examples. The simulation results show that the proposed algorithm can maintain competitively the same video quality as exhaustive search of multiple reference frames. Meanwhile, 76 %-96 % of computation for searching unnecessary reference frames can be avoided. Moreover, our fast reference frame selection is orthogonal to conventional fast block matching algorithms, and they can be easily combined to achieve further efficient implementations.
Motion compensated de-interlacing with adaptive global motion estimation and compensation

A motion compensated de-interlacing method with adaptive global motion estimation and compensation is proposed to recover the defects of interlaced video sequence with camera panning, rotating or zooming. GME and GMC are used to recover the change of the whole picture due to camera motions. Two local motion compensated de-interlacing methods are proposed and applied to de-interlace the interlaced video sequences with or without global motion respectively. SAD checking and global/local motion comparator can be used as a block based mode decision system for intra/MC/GMC modes. The proposed algorithm could achieve higher image quality of interlaced video sequences than any other usual de-interlacing algorithm on progressive devices.
Efficient algorithms and architectures for MPEG-4 object-based video coding

This paper presents efficient algorithms and architectures for the MPEG-4 object-based video coding. The novel coding tools supporting for object-based coding will much increase the computational burden, in comparison with conventional frame-based video coding system. In order to process these extra computational tasks effectively design techniques both on algorithms and architectures have to be addressed. By the careful examination of computational behavior of algorithms, the best-matched computation models can be derived, and the target architectures can be determined. Based on this design strategy, the computational behavior of the MPEG-4 video coding tools at simple/core profiles and level 2 is explored first. Then, by considering the analysis results, efficient algorithms and architectures are developed to meet the design specifications. The shape coding tool, which is the most computation-extensive task supporting for object-based functionality is selected as our study case. The real-time performance of shape coding can be easily achieved by the proposed architecture approximately running at 7.8 MHz while the optimized software running on a full-speed RISC (Ultra Sparc, 300 MHz) can only have about 1/10 performance.
iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor

Visual sensors combined with video analysis algorithms can enhance applications in surveillance, healthcare, intelligent vehicle control, human-machine interfaces, etc. Hardware solutions exist for video analysis. Analog on-sensor processing solutions feature image sensor integration. However, the precision loss of analog signal processing prevents those solutions from realizing complex algorithms, and they lack flexibility. Vision processors realize high GOPS numbers by combining a processor array for parallel operations and a decision processor for other ones. Converting from parallel data in the processor array to scalar in the decision processor creates a throughput bottleneck. Parallel memory accesses also lead to high power consumption. Privacy is a critical issue in setting up visual sensors because of the danger of revealing video data from image sensors or processors. These issues exist with the above solutions because inputting or outputting video data is inevitable.
A novel hybrid pipeline design methodology on a multi-cores streaming system for multimedia applications

With the rapid growth of media-processing technologies and the advancement of semiconductor process, more and more multimedia applications are integrated into consumer electronics. However, in such highly complex system, the design time for the circuit designers does not reduce much as the process advances. We propose a novel hybrid pipeline design methodology for multi-core streaming system from C-level to RTL design. Our methodology can optimize data communication for media-processing applications to achieve both flexibility and efficiency.
Accelerated local feature extraction in a reuse scheme for efficient action recognition

In this paper, we propose an accelerated local feature extraction in a reuse scheme for action recognition. Most local features of the previous frame could be reused due to the high correlation between successive frames. Feature extraction is only needed to be applied partially in the current frame. The full-frame features of the current frame are combined by features extracted at different times. Experimental results show that the proposed reuse scheme can achieve comparable performance to full-frame feature extraction while computational effort is reduced significantly.
Low-cost hardware architecture design for 3D warping engine in multiview video applications

As the history of television industry goes, multiview video (MW) and its applications draw more and more attentions by the realistic 3D scene it can bring. In these applications, virtual view synthesis is required for providing free view point sequences so as to fulfill a real-time display system. In this paper, a low-area architecture is proposed. By employing the linear-interpolated approximation algorithm, the large area requirement due to the synthesis parameters is resolved. In addition, redundant information for fraction bits of parameters is further reduced by precision fitting analysis. As a result, 95.9% of area for matrix parameter rendering stage and 69.5% for vector transform stage are reduced with only 0.0059 dB overhead of PSNR performance.
Single chip video segmentation system with a programmable PE array

Video segmentation is a very important unit in content-based video encoding systems, such as MPEG-4. In this paper, a single chip video segmentation system is proposed. First, a hardware-oriented video segmentation algorithm is developed, which contains only local pixel operations and morphological operations. Simulation results show that the segmentation results of the proposed algorithm are satisfied. To achieve both high throughput and flexibility, the system is then mapped to a hardware architecture with a programmable PE array. This chip is designed with cell-based design flow and is currently under fabrication by TSMC using 0.35/spl mu/m 1P4M technology. Simulation shows that the prototyping chip can achieve the processing speed of 30 QCIF frames per second and 7,680 binary morphological operations per second at 26MHz with small chip size. This chip can be integrated into any camera or real-time encoding system to support content-based coding capability.
A flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC

Due to the multi-frame motion estimation (ME), H.264/AVC requires ultra high memory bandwidth. The conventional multiple reference frames single current macroblock (MRSC) scheme only considers the data reuse within one frame, requiring on-chip memory size and off-chip memory bandwidth in proportion to the number of reference frames. In this paper, a single reference frame multiple current macroblocks (SRMC) scheme is presented to further exploit the data reuse between multiple frames. With rescheduling of the macroblock (MB) procedures at frame level, one loaded search window can be utilized by multiple current MBs in different frames. The demanded memory size and bandwidth for multi-frame ME can thus be reduced to those of the MRSC scheme with only one reference frame. Moreover, based on SRMC, a system architecture for H.264/AVC encoding is proposed. For HDTV specifications, 62.21 Kb (74.8%) of SRAM and 364.3 MB/s (62.6%) of system bandwidth are saved in comparison with the MRSC scheme.
Architecture design of stereo matching using belief propagation

We propose a new architecture for stereo matching using belief propagation. The architecture combines our fast, fully-parallel processing element (PE) and memory-efficient tile-based BP (TBP) algorithm. On the architectural level, we develop several novel techniques, including a three stage pipeline, a message forwarding scheme, and a boundary message reuse scheme, which greatly reduce the required bandwidth and power consumption without sacrificing performance. The simulation shows that the architecture can generate HDTV720p results at 30 fps when operating at 227MHz. The high-quality depth maps enable real-time depth image based rendering and many other important applications in the 3D TV industry.
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications

In this paper, the low power design techniques from algorithm to architecture levels are proposed for fractional motion estimation in H.264/AVC. The proposed AMPD algorithm can reduce 50.8% power with up to 0.1 dB quality drop. The proposed parallel architecture with efficient memory hierarchy can efficiently reuse data and save 61.6% power. Furthermore, the power aware functionality is included. Our design can gracefully vary the quality degradation of 0.1-3.9 dB in response to the 22.58-1.64 mW power consumption. This power-oriented design is very efficient for different mobile applications in various power situations
The system implementation of I-phone hardware by using low bit rate speech coding

This paper presents a system implementation for Internet-phone communication with real-time speech coding schemes. A low-cost speech processing coprocessor is embedded. A CPLD device is used to implement the interface between the host processor and the coprocessor via conventional parallel port. At the headphone interface, there are a 16-bits PCM CODEC and an audio amplifier with acoustic echo cancellation features employed. The system consists of a mixed implementation of software and hardware. The experimental coding rate is 8.5 kbps. In such rate, a 14.4 kbps or higher speed modem can conform to offer full-duplex speech for the applications such as digital simultaneous voice data (DSVD).
A single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm

By using an adaptive algorithm, we design a single-chip Viterbi decoder for a rate 1/2 binary convolutional code. The adaptive algorithm is realized by threshold checking at each stage. The survivor paths that are less likely are ignored and hence the number of states at each decoding stage to be computed is reduced significantly in comparison with the conventional Viterbi decoder. Therefore, the decoding speed can be increased. A single-chip hard-decision decoder for a rate 1/2 convolutional code with constraint length K=6 (64 states) has been fabricated in 1.2 /spl mu/m CMOS technology. Experimental results show that this improved algorithm can achieve a data throughput rate about 3 times faster than that using a conventional algorithm without sacrificing the decoding reliability.
High throughput CORDIC-based systolic array design for the discrete cosine transform

In this paper, we propose a modified Malvar algorithm that can transfer the Discrete Hartley Transform (DHT) results to the Discrete Cosine Transform (DCT) by using a one additional CORDIC computing stage. A fast CORDIC-based systolic array is designed with four attractive features the single/double data folding feature; the constructive feature; the co-computing feature; and redundant path computation. Due to the existence of the redundant path, the proposed design also has the capability of error detection.<<ETX>>
Hardware architecture design for visual processing: present and future

This paper presents the present and future trends of hardware architecture design for image and video coding. Fundamental design issues are discussed with particular emphasis on efficient dedicated implementation. Hardware architectures for MPEG-4 video coding and JPEG 2000 still image coding are reviewed as examples, and special approaches exploited to improve efficiency are identified. Further perspectives are also presented to address the challenges of hardware architecture design for future image and video coding.
Perspectives of multimedia SoC

Multimedia technology is one of the driving forces for the digital convergence of computers, communications, and consumer electronics. With digital technology being applied to human daily life, multimedia has been brought to office, home, and even the outdoors, from large devices to portable devices, and from specific people to everybody. Diverse multimedia applications have been realized and are emerging around various multimedia terminals, making human life more convenient and more interesting. One of the key factors allowing multimedia systems to become so popular is the advance in SoC technology, which enables the integration of large-scale complex system into a single chip and results in the low-cost and low-power features desired by multimedia terminals. The recent advances in signal processing and video codec implementations for multimedia applications are presented. The technology issues and directions of the multimedia design approaches based on the latest research results, e.g. MPEG-4, H.264, are introduced. Key challenges of multimedia SoC design, e.g. complexity, low power, flexibility, are addressed. Finally, the future trend of multimedia SoC are discussed.
Hardware architecture design for H.264/AVC intra frame coder

In this paper, we contributed a VLSI architecture design for H.264/AVC intra frame coder. First, analysis of coding algorithm is provided by using a RISC model to obtain the proper degrees of parallelism under SDTV specification. Second, a two-stage macroblock pipelining is proposed to double the processing capability and hardware utilization. Third, Hadamard-based mode decision is modified as DCT-based version to reduce the 40% of memory access. To sum up, our system architecture achieves 215 times of speed compared with RISC-based software implementation in terms of processing cycles. In addition, we also made a lot of efforts on developing area-speed efficient modules. Reconfigurable intra predictor generator can support all kinds of prediction modes. Parallel multi-transform has four times throughput of the serial one with little area overhead. CAVLC engine can efficiently provide coding information for the bitstream packer. A prototype chip was fabricated with TSMC 0.25 /spl mu/m CMOS technology and is capable of encoding 720/spl times/480 4:2:0 30 Hz video in real time at the working frequency of 54 MHz. The transistor count is 429 K, and the core size is only 1.855/spl times/1.885 mm/sup 2/.
Analysis and architecture design of EBCOT for JPEG-2000

This paper presents detailed analysis and efficient architecture design of Embedded Block Coding with Optimized Truncation (EBCOT) for JPEG-2000. Detailed profile of the context formation process in EBCOT is analyzed to get an insight into the characteristics of the operation. Column-based operation is adopted to enable higher process speed. Two speed-up methods, referred to as Pixel Skipping (PS), and Group-Of-Column Skipping (GOCS), are proposed. It is shown that over 60% of processing time can be reduced by exploiting the two methods. A column-based architecture using these combined speed-up ideas is then proposed.
An I-phone system design and implementation with a portable speech coding coprocessor

This paper presents a high quality, low bit rate, and portable Internet-phone system. The system consists of a mixed implementation of software and hardware. The hardware includes a portable box that can be plugged into the conventional parallel port. Three major parts are considered in this box: the speech compression unit, the host interface, and the speakerphone module. A low-cost non-delicate speech coprocessor is embedded to process the heavy job of speech coding, a CPLD device is employed to control the host access timing, a 16-bit PCM codec and an audio amplifier with acoustic echo cancellation features are introduced to optimize the speakerphone module. The experimental coding rate is 8.5 kbps. At such a rate, the popular modems can conform to offer full-duplex speech in real time. Modern applications of this system include digital simultaneous voice data (DSVD) transmission, such as net-game's talking and video-conferencing.
Modifications and performance improvements of 3-step search block-matching algorithm for video coding

The paper proposes three modifications to the 3-step hierarchical search block-matching algorithm for video coding: a multiple-winner search that improves the estimation accuracy, a method of subsampling that reduces computation and input data amount, and an overlapping strategy that improves the accuracy of large-area search. Experimental results show that combining these techniques provides high-speed and high-precision motion estimators with reduced on-chip buffers and lowered input bandwidth requirements.<<ETX>>
Multiview video hybrid coding system with texture-depth synthesis

Multiview video coding (MVC) is getting more and more attention in recent years because of the realistic perception it can bring. However, the current H.264-based coding scheme cannot get enough coding gain in the rate-distortion (R-D) performance. Furthermore, the view synthesis and random access between views are also design challenges. In this paper, a multiview hybrid coding system with texture-depth synthesis is proposed. By sharing the prediction information between texture and depth maps, the depth map can be reconstructed with reduced bitrate overhead. Then, after using matrix-based warping and adaptive disparity compensation, the R-D performance of the proposed system can be about 2 to 4 dB higher than the current MVC coding scheme at low bitrate range.
Design and Implementation Of Word-Level Embedded Block Coding Architecture in JPEG 2000 Decoder

This paper presents a word-level decoding architecture of embedded block coding (EBC) in JPEG 2000. This architecture decodes one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column-switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show the proposed architecture can decode 54 MSamples/s at 54 MHz, which can support HDTV 720 p (1280times720, 4:2:2) decoding at 30 frames/sec in real time
System design consideration for digital wheelchair controller

The design and implementation of a digital wheelchair controller system is presented in this paper. This novel model depicts an information flow between the driving commands and wheel speed. A command interpreter and two speed processing datapaths are proposed as functionally independent blocks for the controller. The control process consists of the following steps: command decoding, speed estimation, and speed serving. Through proper partitioning to concurrent blocks, the design complexity is reduced significantly. Block reconfiguration for field-programmable gate array rapid prototyping is also employed in this paper, and system fidelity and development efficiency are revealed through the experimental results.