nils-herrmann/clean_scirepeval huggingface dataset:
A microscopic interpretation of the RF noise performance of fabricated FDSOI MOSFETs

In this paper, a detailed research of the high-frequency noise sources and figures of merit (FOMs) of fabricated deep-submicrometer n-channel fully depleted silicon-on-insulator MOSFETs is carried out. Special care is given to reproduce the main topology parameters, together with the most relevant parasitic elements of real devices in order to accomplish an accurate and reliable simulation. The information provided by the Monte Carlo (MC) tool allows getting a physical insight of the relationship between internal quantities and the main noise sources inside the device; moreover, the spectral density of velocity fluctuations has been analyzed spatially in order to determine the local current noise source in the gradual channel and velocity overshoot sections of the effective channel. Together with the calculation of intrinsic noise sources, the MC simulator is able to reproduce the measurements for the main noise FOMs in the RF and microwave frequency ranges. Moreover, the whole simulation framework allows addressing the importance of parasitic elements in the final value of these FOMs.
Time-dependent physics of double-tunnel junctions

In this work, we investigate and explain the time-dependent behavior of shot noise in Silicon quantum dot-based double-tunnel junctions by means of a three-dimensional self-consistent simulation and a Monte-Carlo algorithm following the time evolution of the system. We demonstrate the strong link between autocorrelation functions and electron waiting time distributions, i.e, the time between two consecutive tunnel events through a given junction. Moreover, we separate and analyze the contribution of each different path - evolution of the number of electrons in the quantum dot between two consecutive tunnel events through the same junction - to understand clearly the behavior of auto-correlations and waiting time distributions in the case of a 3-state system.
Isolated-gate InAs/AlSb HEMTs: A Monte Carlo study

In this work we present a Monte Carlo study of the influence of the presence of a native oxide which isolates the gate in InAs/AlSb high electron mobility transistors (HEMTs) on their dc and ac performance. A good agreement between simulations and experimental results of I-V curves and small signal equivalent circuit parameters has been found for low VDS, where impact ionization is not of importance. The comparison between intrinsic MC simulation results for isolated-gate and Schottky-gate HEMTs reveals a strong influence of the native oxide on the dynamic behavior of the devices, mainly on Cgs, gm and fc.
Surface Charge Effects in Ballistic T-Branch Nanojunctions

We analyze the influence of the surface charge on the operation of ballistic T-branch junctions based on InAlAs/InGaAs layers by means of a semi-classical 2-D Monte Carlo simulator. For this sake we propose a new self-consistent model in which the local value of the surface charge is dynamically adjusted depending on the surrounding carrier density. We will show that the TBJ rectifying behavior, that is the down-bending shape of the output voltage VC as a function of the applied voltage, VR= -VL=V, is found to be much influenced by the surface charge. A satisfactory agreement is achieved between simulated results and experimental measurements.
Monte Carlo Study of 2-D Capacitance Fringing Effects in GaAs Planar Schottky Diodes

Nanometer scale planar Schottky barrier diodes (SBDs) with realistic geometries have been studied by means of a 2-D ensemble Monte Carlo simulator. The topology of the devices studied in this paper is based in real planar GaAs SBDs used in terahertz applications, such as passive frequency mixing and multiplication, in which accurate models for the diode capacitance are required. The intrinsic capacitance of such small devices, which due to edge effects strongly deviates from the ideal value, has been calculated. In good agreement with the classical models, we have found that the edge capacitance is independent of the properties of the semiconductor beneath the contact and, as novel result, that the presence of surface charges at the semiconductor dielectric interface can reduce it almost 15%. We have finally provided a compact model for the total capacitance of diodes with arbitrary shape that could be easily implemented in design automation software such as Advance Design System (ADS).
An Embedded System Design of Selective Window Speckle Noise Suppression Filter for Ultrasound Images

This paper presents a novel approach for speckle reduction of ultrasound image and its implementation using EDK 7.1i (Embedded Development Kit) on ML310 embedded development platform wherein the image is read from an image data file to a set of slave registers in the filter core through the On-Chip Peripheral Bus (OPB) and thereby processed in the filter core. Speckle is a phenomenon in ultrasonic pulse-echo measurements, caused by the coherent nature of the imaging source. When an acoustic wave propagates through a scattering medium, all the wavelets generated by the reflection of the incident wave on randomly distributed scatterers, interfere on the surface of the receiving transducer in a constructive or destructive way, depending on their relative phase forming speckle noise
Multirate scan conversion of ultrasound images using warped distance based adaptive bilinear interpolation

Ultrasound imaging systems use a scan conversion process to display data acquired with polar coordinate in Cartesian coordinate system. To avoid artifacts interpolation is needed for unsampled pixels. The resultant image quality is dependent on the interpolation algorithm. Majority of the interpolation mechanisms enhance both smooth and detailed regions which degrades the image quality. In this paper, a warped distance based adaptive bilinear interpolation technique with selective sampling is proposed. This algorithm enhances the detail regions and preserves the smooth regions. Simulation results prove that proposed interpolation algorithm yields better image quality with less computational complexity.
A wavelet based low complexity embedded block coding algorithm

Along with compression efficiency, other factors, like complexity, are significant issues for image coding. The measure of complexity varies from application to application. To overcome the problems of large database maintenance and the high computational burden of EZT and SPIHT, a new algorithm, WEBLOC (Wavelet-based Embedded BLOck Coding), is proposed for low complexity, near lossless compression. The most significant characteristics of this algorithm involve (a) sign-bit arrangement (b) subband intensity distribution statistics. Results were obtained with monochrome 8 bpp, 256/spl times/256 images. The salient features of the coding algorithm can be summarized as follows. Entropy coding is replaced by fixed RLC (runlength coding), considerably reducing the computational overhead and also the time overhead. For near lossless image compression, the reduction of complexity highly reduces the hardware circuitry. The running memory overhead for any list is reduced as compared to the EZT and SPIHT. However, the memory requirement for storing the wavelet coefficients is not reduced.
Design of a new log-domain differentiator based universal analog biquadratic filter

A novel implementation of a continuous-time universal analog biquadratic filter is presented. Using two log-domain differentiators along with a few current mirrors and current copiers, the low-pass, high-pass, band-pass, band-elimination (notch) and all-pass filter transfer functions are realized. The filter, has been designed using a purely current-mode approach and is electronically tunable over several decades of frequency by altering the magnitude of the current sources. Both the differentiators used here have been designed using bipolar junction transistors. The design can be extended and realized with MOSFETs operating in the weak inversion region. The concept has been demonstrated at circuit simulation level using the Saber simulator
Real time dynamic receive apodization for an ultrasound imaging system

This paper proposes an algorithm and its VLSI implementation to generate the aperture weighting coefficients for an ultrasound imaging system in real time. The side lobe reduction capability of the proposed scheme has been compared with existing methods and satisfactory results have been obtained. The design has been implemented using XCV2000EBG560 Xilinx FPGA and for a typical 64 channel beamformer (100 scan lines, 512 scan points on each line) found to operate at 40 frames/s. Further speed enhancement in the existing design, if necessary, can easily be made by just using identical blocks in parallel and very small change in the control structure.
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25μ BiCMOS Technology

A fully differential low power 10-bit 200MSPS sample and hold has been designed for the front-end of a pipelined analog-to-digital converter using 0.25μm BiCMOS technology. Switched capacitor differential topology has been used with special care taken in linearization of switches. The key issues of the design are optimization of speed, accuracy and power minimization. An op-amp (OTA) having very fast settling time of 1.67ns is designed to meet the speed requirement of the sample and hold. The sample and hold consumes 11mW power while occupying an area of 0.07 mm2 including clock driver circuitry. Analog and digital power-supplies used are 3V and 2.5V respectively
Finite element analysis of SiGe npn HBT

A two dimensional general purpose device simulator (BISOF), based on finite element method, has been developed. The various material parameters, such as dielectric constant, energy bandgap, intrinsic carrier concentration, mobilities and life time etc., which vary with position due to the spatial variation of the composition of the have been taken into account. An npn heterojunction bipolar transistor has been analysed and the dependence of the device characteristics on the various Ge mole-fraction material parameters has also been studied using the program.<<ETX>>
Design of low-voltage low-power continuous-time filter for hearing aid application using CMOS current conveyor based translinear loop

In this paper, we discuss the design of a continuous-time biquadratic filter for hearing aid application using CMOS current conveyors based translinear loop. It has the capability of amplifying as well as attenuating the signals of any desired frequency band in the audio range. The proposed circuit has been realized using purely current-mode approach. Electronic tuning of the filter parameters is being done by the bias current sources. This filter in the log-domain operates at low voltage and consumes very low power.
Comparative Analysis of Golay Code Based Excitation and Coherent Averaging for Non-invasive Glucose Monitoring System

This paper presents a method for improvement in SNR and resolution of photo acoustic (PA) signal using Golay coded excitation for a non-invasive and continuous glucose monitoring. The simulation results with a Golay code of length 4 has been shown, which gives a coding gain of 9.03 dB in comparison to regular pulse triggering. Furthermore, Golay coded excitation results in better resolution of PA signal as compared to coherent averaging technique, which can help in improving calibration accuracy.
Area efficient, high-speed VLSI design for EBCOT block coder in JPEG 2000

With the growth in multimedia technology, demand for highspeed real time image compression system has also increased. JPEG 2000 standard is developed to cater such application requirements. However, the sequential execution of the bit plane coder (BPC) used in this standard consumes more clock cycles. To improve the performance of the BPC, a new concurrent context modeling technique is proposed in this paper. To study number of context generated in each clock cycle, analysis is carried out on five ISO grayscale images with size 512 × 512. The study revealed that about 58% of time more than 4 contexts are generated in one clock. Therefore, a new concurrent context coding architecture is proposed in this paper. It is implemented on Startix FPGA and the hardware requirement is reduced significantly, compared to similar architectures. Moreover, number of clock cycles required to encode a bit plane is reduced by 10% and it is minimum 2.5 times faster than the similar designs in existence. This design operates at 164.47 MHz, which makes it compatible for encoding HDTV 1920 × 1080 4:2:2 at 39 frames per second.
Data-folded architecture for running 3-D DWT using 4-tap Daubechies filters

A real-time 3-D sub-band coding (SBC) technique using a discrete wavelet transform is proposed. The main advantages of the proposed scheme lie in the reduction of wait time and diminution of buffer size in 3-D SBC. The major delay which is due to the group of frames (GOF) generation in the temporal direction is decreased by dynamic updating of the transform coefficients. The dynamic updating handles much a lower dimension of data compared to 3-D SBC, and thus facilitates better hardware utilisation with lower overhead. A data-folding architecture is used in unison with the CORDIC-based QMF lattice filters for realisation of 2-D DWTs using a 4-tap Daubechies filter. The data scanning pattern for the spatial domain signal results in a low-complexity control circuit. The multiplierless DWT architecture operating at 100 MHz is implemented on 0.25 μm BiCMOS technology and found to have much lower power dissipation compared to the multiplier-based structures for FIR realisation. The optimised design of the DWT filter using data-folding architecture resulted in an appreciable low memory budget of N2/4+2N for 2-D DWT and O(N2/M) time required for temporal direction decomposition. Hardware utilisation in the proposed architecture is 100%.
Development of SPICE Compatible Thermal Model of Silicon MEMS Piezoresistive Pressure Sensor for CMOS-MEMS Integration

In this paper, the effects of electrical heating in a silicon MEMS piezoresistive pressure sensor have been analyzed analytically and verified experimentally with a view to design energy efficient sensor node network where the sensors are operated for a prolonged time. For the integration of the MEMS sensor with the CMOS circuits, a SPICE compatible thermal equivalent circuit has been developed for the purpose, which imports the values of thermal resistance, time constant, and thermal capacitance by a dynamically linked library from the external user defined model.
Virtually Scaling-Free Adaptive CORDIC Rotator

In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2.
Smartphone based blood flow feature extraction and classification from Doppler spectrum images

Ultrasound (US) Doppler spectrograms have been widely used for diagnosing vascular obstructions. This paper presents an Android smartphone based new approach for detecting the blood flow condition based on the US Doppler spectrogram images. A set of 59 spectrograms acquired from a US Doppler system is processed to extract features, and these non-redundant features are fed into a supervised classifier to determine the normal and abnormal blood flow. The classification is performed using the k-nearest neighbors (k-NN), Support vector machine (SVM), Naive Bayes (NB) and Multilayer perception (MLP) based classifiers. The SVM based classifier has shown superior performance, having an accuracy of 86.4 %, with a sensitivity and specificity of 96.4 % and 77.4 % respectively. The complete technique is implemented as an Android application and the results show the efficacy of the presented approach for the automated diagnosis of arterial diseases.
Inertial snake for contour detection in ultrasonography images

Snakes, or active contour models are used extensively for image segmentation in varied fields. However, some major challenges restrict their use in many fields. The authors propose a new inertial snake model, that introduces an inertial effect of the control points into the snake framework. The proposed inertial force along with the first- and second-order continuity forces controls the spline motion through the concavities and also against weak edge forces. This smart force field, added to the inertial energy framework, posses the ability to adaptively reduce its effect near the true edges, so that the energy minimising spline converges into the edges. A greedy snake has been used for computation of the energy minimising spline. The algorithm has been tested on phantoms and ultrasound images as well. It is shown in the results that the proposed algorithm classifies the object from the background class in most of the images perfectly. Ultrasound images of a lower limb artery of an adult woman have been tested with this algorithm, and also extended for motion tracking.
A Real Time Speckle Noise Cleaning Filter for Ultrasound Images

Ultrasound images are masked by multiplicative speckle noise caused by random interference between coherent backscattered waves. This paper presents an efficient algorithm for real-time speckle cleaning filter of ultrasound images and its VLSI implementation in FPGA. The algorithm presented here implements a regular, tunable filter with an optimized architecture having proper parallelism and pipelining to achieve high speed. The performance of the proposed filter is compared to that of the aggressive region growing filter (ARGF). The processed images obtained from the proposed filter are speckle removed and the edge details are also restored effectively. Also, the PSNR performance is better than the ARGF filter while noise variance is lower indicating a cleaner image as more speckle is reduced
A smart diagnostic system for Doppler ultrasonography

This paper proposes an automated diagnostic approach for a Doppler ultrasonography system (DUS) using the spectrogram features and image information. Various boundary and moment features of the spectrogram are fed to a supervised ANN to diagonise the localized arterial condition. This local data is given to a Bayesian probabilistic inferencing engine for end diagnosis. Simultaneously, arterial contour variation in the image is tracked for motion estimation and diagnosis of the arterial condition. Though the exact correlation remain unexplored, but the two findings amply help in medical diagnosis of arterial ailments.
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation

This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standard's filter while designing a root-raised-cosine finite-impulse response filter for multistandard DUC for three different standards. In the next step, a 2-bit binary common subexpression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with 36% improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and can be considered more appropriate for designing the multistandard DUC.
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm

This paper introduces a computationally efficient hardware architecture for reconfigurable multiple constant multiplication block, which functions according to the canonical signed digit (CSD)-based vertical and horizontal common sub-expression elimination (VHCSE) algorithm. In the proposed architecture, the CSD decoded coefficient along with 4-b common sub-expressions (CSs) in the vertical direction and 4- and 8-b CSs in the horizontal direction reduces the required number of full adder cells and the adder depths. This technique helps in reducing area consumption by decreasing the number of coefficient multiplier adders by 59% than that of the binary VHCSE (VHBCSE) algorithm. This technique helps in reducing the average switching activity of the adder blocks used in each coefficient multiplier block by 26.1%, 25.6%, and 21.3%, while compared with those of the 2- and 3-b binary CS elimination (BCSE) and VHBCSE algorithms, respectively. For different orders of filter, the proposed one delivers 57.5% and 61.9% improvement in area-power product (APP) on an average compared with the VHBCSE and mixed integer programming algorithms, respectively. Experimental results of differently specified finite impulse response (FIR) filters ranging from 10 to 100 taps and the coefficients of 8, 12, and 16 b show the improvements of 42.8%, 53.6%, and 37%, respectively, in the average gate count and 51.8%, 43.5%, and 36.7% less propagation delay than those of earlier canonical double-based number representation method. Moreover, in the metric made of APP divided by throughput, the proposed technique experiences 63.7% improvement on an average over that of faithfully rounded truncated multiple constant multiplication/accumulation technique of designing constant multiplier and demonstrates its suitability for implementing efficient reconfigurable FIR filter.
An 8-bit, 3.8GHz dynamic BiCMOS comparator for high-performance ADC

This paper deals with a monolithic dynamic voltage comparator with sampling speed up to 3.8GHz and a resolution of 8-bit. To improve the power-speed tradeoff, the front-end pre-amplifier is being designed with high f/sub T/ (80GHz) Si-SiGe heterojunction bipolar transistor (HBT) for higher speed while the dynamic latch along with the output buffer is implemented in 0.25/spl mu/m standard CMOS process to keep the power level low. To operate the CMOS latch at 3.8GHz sampling rate, a tailor made 3-/spl Phi/ clocking scheme is employed where the reset time of the latch falls up to 45ps in the reset mode. In the tracking mode, controlled decision transferring is done from pre-amplifier to the latch. At the latch output, a buffer with hysteresis is used to overcome the switching noise of latch and produce sharp, well defined digital data. The active power consumption by the core comparator is /spl sim/9mW and it takes a core area of /spl sim/0.017 mm/sup 2/.