nils-herrmann/clean_scirepeval huggingface dataset:
Performance & reliability characterization of eWLB (embedded wafer level BGA) packaging

The drive for small form factor and foot print area packages is being fueled by consumer electronic applications that today constitute 50% of semiconductor revenue. Mobile phones are experiencing explosive growth both in terms of unit shipments and increased complexity at the same time. In just one decade mobile phone has transformed from a simple communication device into more complex system integrating features that allow customers to use it as a multipurpose gadget. Small form factor, foot print areas and cost effective technology are mandatory characteristics for packages in hand held electronic applications. Demand for WLP is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. However there are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. This paper will highlight some of the recent characterization works of electrical, thermal and mechanical performance of eWLB packaging. The performance is compared with fcFBGA packaging format. Thermal characterization activity is carried out to investigate the effect on eWLB configuration with power loading. Thin film based integrated passives on the fan-out area (mold material) of the eWLB is also analyzed during electrical characterization. Due to the low-loss property of the mold material, plated Cu inductors showed high quality-factor (Q) performance. The mold material in fan-out area is not only used as a supporting substrate, but also serves as the package substrate, which allows the high-Q inductors to be implemented with other RF chips in one single package. Parasitic electrical performance and characterization works will be presented in this paper. eWLB package warpage behavior with temperature profile observed with Thermo-Moire method, package and board level reliability results will be presented in this paper too.
Per-channel color barcodes for displays

We present a per-channel framework for extending monochrome barcodes to color for display applications, offering increased data rates and capacity. Data is independently encoded into barcodes, incorporated within a color image as the red (R), green (G), and blue (B) channels and decoded from the corresponding R, G, and B channels in the image of the displayed barcode captured with a smartphone. Using a physical model for the display and capture processes, we show that the cross-channel interference in this situation is appropriately modeled by a linear mixing relation. Via experiments done over multiple smartphones and displays, we demonstrate that the impact of the interference is small and can be further mitigated through the use of interference cancellation. Two methods are presented for estimating and canceling the interference: either using pilot blocks in coherent designs where the synchronization marker patterns align between the codes or using expectation maximization. Results are presented for both QR and Aztec color codes in this framework, highlighting its versatility. Overall bit error rates are shown to be below 1.23% and are further reduced by interference cancellation. These low error rates are well within the correction capacity of the error correction codes used for typical color barcodes.
Toward Turbo Decoding of RNA Secondary Structure

We propose an iterative probabilistic algorithm for estimation of RNA secondary structure using sequence data from two homologous sequences. The method is intended to exploit intersequence correlations "encoded" in the form of probabilistic models for alignment and for common secondary structure. In analogy with turbo-decoding in digital communications, we formulate a maximum a posteriori probability objective function for joint structural prediction and sequence alignment using iterations over individual structural and sequential alignment models with soft-input soft-output estimators. As a preliminary step toward realizing this methodology, we present results obtained from incorporating (hard) constraints based on posterior sequence alignment probabilities in joint secondary structure prediction. Through experimental evaluations over available databases of known secondary structure, we demonstrate that this results in a significant decrease in computation time while simultaneously providing a marginal increase in structural prediction accuracy.
Cancellation of show-through in duplex scanning

When scanning a page with printing on both sides, the printing on the back-side often shows through in the scan of the front-side because the page is not completely opaque. This phenomenon of show-through is analyzed and an image processing method for removal of this commonly encountered degradation is developed. A simplified mathematical model is obtained from first physical principles. The model is linearized using suitable transformations and simplifying approximations. Based on the linearized model, an adaptive linear-filtering scheme is developed for the electronic removal of show-through using scans of both sides of the document. Experimental results demonstrating the effectiveness of the method developed are presented.
Insertion, Deletion Codes With Feature-Based Embedding: A New Paradigm for Watermark Synchronization With Applications to Speech Watermarking

A framework is proposed for synchronization in feature-based data embedding systems that is tolerant of errors in estimated features. The method combines feature-based embedding with codes capable of simultaneous synchronization and error correction, thereby allowing recovery from both desynchronization caused by feature estimation discrepancies between the embedder and receiver; and alterations in estimated symbols arising from other channel perturbations. A speech watermark is presented that constitutes a realization of the framework for 1-D signals. The speech watermark employs pitch modification for data embedding and Davey and Mackay's insertion, deletion, and substitution (IDS) codes for synchronization and error recovery. Experimental results demonstrate that the system indeed allows watermark data recovery, despite feature desynchronization. The performance of the speech watermark is optimized by estimating the channel parameters required for the IDS decoding at the receiver via the expectation-maximization algorithm. In addition, acceptable watermark power levels (i.e., the range of pitch modification that is perceptually tolerable) are determined from psychophysical tests. The proposed watermark demonstrates robustness to low-bit-rate speech coding channels (Global System for Mobile Communications at 13 kb/s and AMR at 5.1 kb/s), which have posed a serious challenge for prior speech watermarks. Thus, the watermark presented in this paper not only highlights the utility of the proposed framework but also represents a significant advance in speech watermarking. Issues in extending the proposed framework to 2-D and 3-D signals and different application scenarios are identified.
On Side-Informed Coding of Noisy Sensor Observations

In this paper, we consider the problem of side-informed coding in applications where the data available at the encoder consists of indirect noisy observations of the signal desired at the decoder. In these scenarios, under Gaussian statistics we show that for a mean-squared distortion metric, the side-informed encoding problem can be decomposed into a "side-informed" minimum mean-squared error (MMSE) estimation followed by side-informed coding of the MMSE estimate, without incurring any rate-distortion penally. By recursively exploiting this decomposition, we develop a sequential framework for side-informed coding in multi-sensor networks, where each sensor observes linear noise-corrupted measurements. We construct a practical realization of this encoder using a Karhunen-Loeve transform with 1 -D scalar coset codes. Simulations demonstrate that simple code constructions based on the estimate-then-code partitioned structure provide improvements over their counterparts that perform the encoding directly without a pre-processing estimation step.
Solar-supercapacitor harvesting system design for energy-aware applications

Supercapacitors are an emerging choice for energy buffering in field systems and their use in solar-powered field systems has been the focus of recent research. Supercapacitors offer advantages compared to rechargeable batteries for energy buffering due to their energy charge/discharge efficiency as well as environmental friendliness. Additionally, a supercapacitor-based system permits an energy-aware operation due to its superior energy-predictability. This paper describes a circuit for solar/supercapacitor energy harvesting, which includes power and voltage measurements, voltage regulation circuit and RS232 communication capability with the host embedded processor. A complete system is prototyped and its operation is discussed in terms of design parameters.
Reliability and failure analysis study of multi-die embedded micro wafer level packages

Main objective of this study is to design and development of multi-die embedded micro wafer level packages (EMWLP) reliability test vehicles. Such as, the laterally placed die EMWLP and the vertically stacked thin die EMWLP. For reliability evaluation, EMWLPs have been subjected to both environmental and mechanical reliability tests as per JEDEC standards. These reliability tests include highly accelerated stress testing (HAST), thermal Cycling (TC), moisture sensitivity testing level 3 (MSL3), board level TC and drop tests. In case of drop tests evaluation, two types of pad finishes, ENIG & OSP have been used. During reliability tests both test vehicles have exhibited better performance without any electrical failures. But in case of HAST reliability test, delamination issue in two packages have been observed. Detailed failure analysis has been carried out on delaminated packages to find out the root cause for the different modes of delamination failures. Non-destructive and destructive techniques have been employed to investigate the failures in EMWLP's and this includes electrical testing, Scanning Acoustic Microscopy (SAM), micro-sectioning and Scanning Electron Microscopy (SEM). Delamination interface has been identified as passivation-RDL interface. Thermo-mechanical simulation study has been carried out over both test vehicles to locate higher stress concentration regions in the packages and finally to correlate with experimental reliability and failure analysis results.
Design and development of a multi-die embedded micro wafer level package

The primary trend in electronics industry is product miniaturization. Both design and manufacturing engineers are looking for ways to make products lighter, smaller, less expensive, and at the same time faster, more powerful, reliable, user-friendly, and functional. A partial list of today's "shrinking" products would include cellular phones, personal and sub-notebook computers, pagers, PCMCIA cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components. With silicon chips continue integrating more functionality as per Moore's law, the packaging is challenged to integrate and shrink. Chips first or embedded chip packaging is a revolutionary way to overcome these recent packaging integration challenges. Packaging researchers have worked on embedded packaging and developed newer way of embedding the chip. The PBGA replaced the lead frame based peripheral array packages, in which the die is electrically connected to circuit board (PCB) substrate by wire bonding or flip chip technology, before covering with molding compound. Embedded Wafer level packaging takes the next step, eliminating the PCB, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection. This paper deals with the development embedding multiple dies at wafer level. A detailed mechanical and structural analysis of the package in terms of the die thickness, wafer size and warpage is presented. The package format is suitable for stacking multiple die in 3D format and 2D format. The paper also deals with characterization of the materials and the process integration of the multidie wafer level packaging. Initial reliability results of the package are also presented.
A hierarchical image authentication watermark with improved localization and security

Several fragile watermarking schemes presented in the literature are either vulnerable to vector quantization (VQ) counterfeiting attacks or sacrifice localization accuracy to improve security. Using a hierarchical structure, we propose a method that thwarts the VQ attack while sustaining the superior localization properties of blockwise independent watermarking methods. In particular, we propose dividing the image into blocks in a multi-level hierarchy and calculating block signatures in this hierarchy. While signatures of small blocks on the lowest level of the hierarchy ensure superior accuracy of tamper localization, higher level block signatures provide increasing resistance to VQ attacks. At the top level, a signature calculated using the whole image completely thwarts the counterfeiting attack. Moreover, "sliding window" searches through the hierarchy enable the verification of untampered regions after an image has been cropped.
Biological Force Measurement in a Protein-Based Nanoactuator

The mechanical force exerted by a nanoactuator due to pH actuation is discussed from a statistical mechanics and free energy of conformational change viewpoint. We use molecular dynamics to show that the nanoactuator, based on the coiled-coil leucine zipper portion of a yeast transcriptional activator protein, can generate mechanical forces of the order of 20-40 pN upon pH modulation. The forces are generated due to the electrostatic repulsions at low pH between His-tag handles and other charged residues engineered into the protein sequence. The biological force output of the nanoactuator is comparable to that generated by adenosine triphosphate (ATP)-based molecular motors such as myosin and kinesin even though the nanoactuator is smaller in size to these molecular motors. The force calculation technique can readily be applied to other biomolecular systems and has implications in the area of bionanotechnology and in particular to study and characterize the properties of novel protein and DNA-based nanodevices.
Mid- air collision prevention in aircraft using GLARE algorithm

(TCAS) Traffic collision avoidance system) is a technique used to reduce mid -air collision. 12It was developed by the Federal aviation administration (FAA), civil aviation authorities (CAA) and the aviation industry. However past analysis shows that there are late reactions or human errors such as over reactions from pilot's which may lead to flight crash or injuries to passengers. There may also be a lack of communication between (ATC) and crew when a resolution advisories (RA) occurs. In this paper, we propose a autopilot configured TCAS that would help to reduce mid air collisions. This can be done using a MSP-430(DSP Microcontroller) that takes coordinates from transponders, and judge any critical scenario based on the GLARE algorithm and shift to autopilot mode until the aircraft reaches a safe zone. Whenever a (TA) occurs the control shifts to longitudinal autopilot mode until the aircraft reaches a safe position; then shifts back to pilot mode. This prevents the pilot from taking control whenever a TA occurs, thus preventing human effort.
Solutions Strategies for Die Shift Problem in Wafer Level Compression Molding

Die shift problem that arises during the wafer molding process in embedded micro wafer level package fabrication was systematically analyzed and solution strategies were developed. A methodology to measure die shift was developed and applied to create maps of die shift on an 8 inch wafer. A total of 256 dies were embedded in an 8 inch mold compound wafer using compression molding. Thermal and cure shrinkages of mold compound are determined to be the primary reasons for die shift in wafer molding. Die shift value increases as the distance from the center of the wafer increases. Pre-compensation of die shift during pick and place is demonstrated as an effective method to control die shift. Applying pre-compensation method 99% of dies can be achieved to have die shift values of less than 40 μm. Usage of carrier wafer during wafer molding reduces the maximum die shift in a wafer from 633 μm to 79 μm. Die area/package area ratio has a strong influence on the die shift values. Die area/package area ratios of 0.81, 0.49, and 0.25 lead to maximum die shift values of 26, 76, and 97 μ.m, respectively. Wafer molding using low coefficient of thermal expansion (7 × 10-6/°C) and low cure shrinkage (0.094%) mold compounds is demonstrated to yield maximum die shift value of 28 μm over the whole 8 inch wafer area.
On the optimality of de-synchronized demand response with stochastic renewables and inertial thermal loads

We consider the problem of optimally supporting a collection of thermostatically controlled inertial loads in a smart microgrid environment. One key consideration is to reduce the need for costly nonrenewable reserves, while also meeting the consumer requirements specific to inertial thermal loads at the same time. Several models studied for optimal demand response leads to a response that is synchronized over the collection of loads, which is undesirable since synchronized response entails high demand fluctuations. We propose a model with an additional feature of stochastic variations in end user requirements. We show that employing a cost function that additionally penalizes the error in adhering to end user requirements leads to an optimal demand response that is de-synchronized over the collection of homogeneous loads. That is, identical thermal loads are intentionally staggered so as to hedge against future uncertainty of consumer preferences. We show that such desynchronization is related to the concavity of the cost-to-go function in the Hamilton-Jacobi-Bellman equation. We provide a simple heuristic to approximate the optimal policy. We also illustrate the results on a simple numerical example.
Geometric distortion signatures for printer identification

We present a forensic technique for analyzing a printed image in order to trace the originating printer. Our method, which is applicable for commonly used electrophotographic (EP) printers, operates by exploiting the geometric distortion that these devices inevitably introduce in the printing process. In the proposed method, first a geometric distortion signature is estimated for an EP printer. This estimate is obtained using only the images printed on the printer and without access to the internal printer controls. Once a database of printer signatures is available, the printer utilized to print a test image is identified by computing the geometric distortion signature from test image and correlating the computes signatures against the printer signatures in the database. Experiments conducted over a corpus of EP printers demonstrate that the geometric distortion signatures of test documents exhibit high correlation with the corresponding printer signatures and a low correlation with other printer signatures. The method is therefore quite promising for forensic printer identification applications. We highlight several of the capabilities and challenges for the method.
Optimized energy allocation in battery powered image sensor networks

We investigate energy allocation strategies in image sensor networks for the purpose of maximizing the network operational lifetime. For the application scenarios that we consider, visual coverage over a monitored region is obtained by deploying wireless, battery-powered image sensors. Each sensor camera provides coverage over a part of the monitored region and a central processor coordinates the sensors in order to gather required visual data. We characterize the network lifetime as a stochastic random variable that depends upon the coverage geometry for the sensors and the distribution of data requests over the monitored region. Using this characterization we consider optimized strategies for energy allocation among the sensors that maximize the expected network lifetime. The formulation naturally leads to a max-min optimization problem that aims to maximize the duration of coverage for the most critical region for which the available energy is the least. We transform this problem into an equivalent linear programming problem, leading to a computationally efficient solution. The effectiveness of the proposed energy allocation strategy is validated by simulations.
Cryptanalysis of a certificateless aggregate signature scheme

Certificateless aggregate signature allows mapping n signatures on n distinct messages from n distinct users into a single length signature. Recently Deng et al proposed CLAS Scheme which is an improvement of Hou et al scheme and claims that their scheme is secure against type II adversary but unfortunately it is found unsecure by applying the Honest but Curious attack by adversary II. In this we show that Deng et al proposed scheme is insecure against type II adversary.
Joint Congestion Control and Distributed Scheduling for Throughput Guarantees in Wireless Networks

We consider the problem of throughput-optimal cross-layer design of wireless networks. We propose a joint congestion control and scheduling algorithm that achieves a fraction 1/dI(G) of the capacity region, where dI(G) depends on certain structural properties of the underlying connectivity graph G of the wireless network and also on the type of interference constraints. For a wide range of wireless networks, dI(G) can be upper bounded by a constant, independent of the number of nodes in the network. The scheduling element of our algorithm is the maximal scheduling policy. Although maximal scheduling policy has been considered in many of the previous works, the difficulties that arise in implementing it in a distributed fashion in the presence of interference have not been dealt with previously. In this paper, we propose two novel randomized distributed algorithms for implementing the maximal scheduling policy under the 1-hop and 2-hop interference models.
Power efficient SAR ADC designed in 90 nm CMOS technology

A 8-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is designed using non redundant SAR structure and sequencer/code Register structure for low power operation. The designed ADC structures provide optimum results for all three circuit design challenges: speed, area and power. Among the two designed SAR ADCs, non-redundant SAR structure ADC and sequence/code register SAR structure ADC is power efficient than SAR ADC designed for the same feature size. Design and simulation of various SAR ADCs has been done in 90 nm CMOS Technology.