nils-herrmann/clean_scirepeval huggingface dataset:
Optimizing the heterogeneous network on-chip design in manycore architectures

Current hybrid network-on-chip designs in manycore systems are agnostic to the application requirements and thus are provided for general cases. This results in high cost in the manycore systems design, wasted energy and performance. We observe that the cost of network-on-chip designs can be reduced by optimizing the application-specific traffic onto the system. This paper presents mincostflow-based heuristic algorithm (LINCA) that minimizes the quantification of hybrid routers corresponding to the application-specific traffic for manycore systems. LINCA guarantees the performance of hybrid networks on chip. Its results are validated against the manycore system architecture. Our evaluations show that LINCA can reduce significant cost of using hybrid routers in the manycore systems. It reduces cost by 84 percent on average across a variety of applications, compared with all of hybrid routers being deployed in the network without using optimization model.
OAPM: Fine-grained operand-aware power management with fast reaction time

Power management is a crucial aspect of modern low power SoCs, but kernel-based approaches suffer from slow DVFS and power state adaptation. We propose OAPM, a power management scheme based on circuit-level operand activity that complements existing OS-based solutions with better system visibility. Operating at the cycle granularity, OAPM has very fast response time in requesting the appropriate power state via a two-stage algorithm. Simulations show potential savings of up to 70% when used with clock-gated Domino, depending on the activity profile.
A VLSI implementation of an FFT/NTT computational unit

The coupling of Residue Number System (RNS) with the recent advances in VLSI technology leads to an efficient implementation of many digital signal processing algorithms. This paper discusses modularity in implementing RNS systems, as modularity is considered an important criterion for VLSI design. An NTT/FFT computational unit is implemented using two multi-look-up table modules as building block units. The layout can be optimized using a look-up table layout procedure which supports the custom design approach. The modularity has been achieved on both functional and layout levels where the interconnection area is minimum.
A low power based partitioning and binding technique for single chip application specific DSP architectures

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for partitioning the given data flow graph describing the DSP algorithm. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.
An efficient compressive wideband spectrum sensing architecture for cognitive radios

Cognitive Radios (CRs) are expected to enhance spectrum efficiency by enabling dynamic or opportunistic access to underutilized licensed frequency bands. To fully maximize capacity gains, CRs must be able to detect spectral opportunities across a wide spectral band. Realizing a wideband spectrum sensing architecture will require analog-to-digital converters (ADC) with extremely high sampling rates. Currently, however, it is infeasible to achieve such rates using the state of art ADC technologies. On the other hand, compressed sensing (also known as compressive sampling) theory has been introduced as a technique for efficiently acquiring and reconstructing a signal using sub-Nyquist sampling rates. In this paper, we propose a wideband spectrum sensing architecture which employs a recently-proposed compressed sensing technique, “channel multiplexer” with a single low switching rate analog to digital converter and low chipping rate pseudorandom generation circuit. Our proposed architecture offers a simple low-power design with enhanced performance over state-of-art wideband spectrum sensing architectures.
Cost Efficient Repository Management for Cloud-Based On-demand Video Streaming

Video transcoding is the process of converting a video to the format supported by the viewer's device. Video transcoding requires a huge storage and computational resources, thus, many video stream providers choose to carry it out on the cloud. Video streaming providers generally need to prepare several formats of the same video (termed pre-transcoding) and stream the appropriate format to the viewer. However, pre-transcoding requires enormous storage space and imposes a significant cost to the stream provider. More importantly, pre-transcoding proven to be inefficient due to long-tail access pattern to video streams in a repository. To reduce the incurred cost, in this research, we propose a method to partially pre-transcode video streams and re-transcode the rest of it in an on-demand manner. We will develop a method to strike a trade-off between pre-transcoding and on-demand transcoding of video streams to reduce the overall cost. Experimental results show the efficiency of our approach, particularly, when a high percentage of videos are accessed frequently. In such repositories, the proposed approach reduces the incurred cost by up to 70%.
An efficient low-bit rate motion compensation technique based on quadtree

The quad-tree structured motion-compensation technique effectively utilizes the motion content of a frame as opposed to the fixed size block motion compensation technique. The authors propose a novel quad-tree structured region-wise motion compensation technique that divides a frame into equilateral triangle blocks using the quad-tree structure. Arbitrary partition shapes are achieved by allowing 4-to-1, 3-to-1 and 2-1 merge/combine of sibling blocks having the same motion vector. We propose an optimal code scheme and a temporal predictive coding for the quad-tree. Simulation results show that our techniques reduce the bit rate by 40% as compared to other methods.
Adaptive neural matching online spike sorting VLSI chip design for wireless BCI implants

Controlling the surrounding world by just the power of our thoughts has always seemed to be just a fictional dream. With recent advancements in technology and research, this dream has become a reality for some through the use of a Brain Computer/Machine Interface (BCI/BMI). One of the most important goals of BCI is to enable handicap people to control artificial limbs. Some research proposed wireless implants that do not require chronic wound in the skull. However, the communications consume a high bandwidth and power that exceeds the allowed limits, 8-10mW. This study proposes and implements a modified version of real-time spike sorting for wireless BCI [4] that simplifies and uses less computation via an adaptive neural-structure; which makes it simpler, faster and power and area efficient. The system was implemented, and simulated using Modalism and Cadence, with ideal case and worst case accuracy of 100% and 91.7%, respectively. Also, the chip layout of 0.704mm2, with power consumption of 4.7mW and was synthesized on 45nm technology using Synopsys.
A general purpose VLSI chip for robot axis motion controller

A VLSI-based realization and implementation of an entire robot axis controller is proposed as a single-chip joint controller. This chip requires a 68000-bus family microprocessor (MP) and a power transistor module. It forms a three-component complete robot servo-level controller which correlates all joint electromechanical activities with the supervisor level (main robot CPU). The proposed chip is equipped with an on-chip RS485 port for communication with the CPU. It is also provided with a pin-to-pin interface to its accompanied MP. All joint digital and analog feedback signals connect directly to the chip.<<ETX>>
Self-Sleep Buffer for Distributed MTCMOS Design

Leakage power is considered as major concern in deep sub-micrometer VLSI designs. MTCMOS technology was introduced to provide considerable power reduction in standby mode, while maintaining high performance in active mode. However, MTCMOS presents new challenges that require extra design effort. This paper targets the challenges and complexities related to sleep signal distribution in a distributed MTCMOS design. We propose synchronized dual-V,h self-sleep buffer method that eliminates the need for sleep signal distribution and allows easy implementation of MTCMOS wakeup scheduling. Guidelines for designing and sizing the self-sleep buffer circuit are provided. In a 90-nm technology and 2-GHz clock frequency, the self-sleep buffer consumes only 1.46- uWin active mode, while eliminating the sleep distribution network overheads and providing fast, low-energy active- to-standby-to-active transitions.
Apology [Plagiarism]

The lead author (Abu Baker) of the paper entitled, "LDPC Decoder: A Cognitive Radio Perspective for NeXt Generation (XG) Communication," which appeared in the 3rd quarter issue of the IEEE Circuits and Systems Magazine, admits to having plagiarized his work from "Energy/Power Estimation for LDPC Decoders in Software Radio Systems" authored by Chia-han Lee and Wayne Wolf of Princeton University, which appeared in the IEEE-SiPS 2005 conference and in order to obfuscate the plagiarism, he made minor modifications to the original work, which he thought would make it harder to trace the material back to the source. He also inappropriately plagiarized some paragraphs from another work by Professors Ian Akyildiz, Won-Yeol Lee, Mehmet Vuran and Shantidev Mohanty, entitled "NeXt generation/dynamic spectrum access/cognitive radio wireless networks: A survey," published in Computer Networks, Vol. 50, Issue 13, September 2006,  He acknowledges that his co-authors, Soumik Ghosh, Ashok Kumar, and Magdy Bayoumi were totally unaware of any plagiarism. Throughout the process, the VLSI research team believed that Baker's write-up showed his own work.
A generalized Poisson based model for defect spatial distribution in WSI

Discusses the use of the modified generalized Poisson binomial limit in modeling defect spatial distribution in WSI (wafer scale integration) and large-area VLSI chips. This model demonstrates the usefulness of generalized Poisson distributions for effectively taking into account the issues of the distribution of clusters and cluster sizes. The strength of the proposed model lies in its simplicity and its close adherence to the forms of defect patterns on a wafer. The model shows excellent fits to the data from simulated wafer maps with high clustering of defects. It also exhibits good fits to data from wafers with small-area, highly dispersed clusters.<<ETX>>
Hybrid mesh-based/block-based motion compensation architecture

The mesh-based model offers a lot of functionalities that the block-based model does not offer. While the mesh-based modes are suitable for spatially continuous representation of in-plane rotations, zooms, and other motions that can be represented by parametric mappings, the block-based models perform better around motion boundaries. Therefore, a hybrid codec with block-based and mesh-based modes, which nicely complement each other, yields the best results over a wide range of video at low bitrates. This paper presents a low-power motion compensation architecture for video applications. It extends the traditional block-based video coders to incorporate the mesh-based model. Using a modified affine transform that reduces the complexity of the motion compensation also reduces the computational cost.
Energy aware distributed arithmetic DCT architectures

An energy aware DCT (discrete cosine transform) architecture based on the distributed arithmetic concept is proposed. Architectures based on the distributed arithmetic concept are inherently low power as they are multiplication free algorithms. One characteristic of the DCT is that signal energies are concentrated in only a few coefficients (less than 25%) upon transformation, with the rest (or 75%) of the coefficients being insignificant and negligible. One can skip the computation of these terms without seriously affecting the output signal quality. Exploiting this idea, we propose an energy aware DCT architecture which adaptively trades off image quality with power dissipation. Our simulation results show that the new proposed architecture achieves 60% in power savings with a small degradation in signal quality.
A theta (1) algorithm for modulo addition

A theta (1) algorithm for large modulo addition for architectures based on the residue number (RNS) is proposed. The addition is done in a fixed number of stages which does not depend on the size of the modulus. The proposed modulo adder is much faster than previous adders and more area efficient. The implementation of the adder is modular and is based on simple cells, which leads to efficient VLSI realization.
A novel 8T SRAM cell with improved read-SNM

As the MOSFET's channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to dopant fluctuation in the channel region. In this paper, a novel highly stable 8T SRAM cell is proposed which eliminate any noise induction during read operation and keep the read SNM as high as 468 mV at VDD = 1.2 V in 120 nm technology. The cell also supports low power operation at cell VDD as low as 0.34 V.This new asymmetric cell structure is capable of using differential sense technique for high speed read operation.
A high-throughput ECC architecture

In this paper, we propose a high-throughput parallel crypto architecture that performs the low level operations for scalar point multiplication over GF(2m) operands. The design performs several different operations in parallel. In the absence of parallel operations or when there are not enough free modules to handle new request, the remaining modules will be deactivated for the sake of power consumption. The experimental results show significant improvement in timing, throughput, and energy performances with a slight overhead in the circuit area.
Multisensor data fusion methods for petroleum engineering applications

Small amount of sand in oil pipelines can result in significant erosion in a very short time period. This Produced sand is a serious problem in many production situations. Installation of a system to monitor and quantify sand production from a well would be valuable to assist in optimizing well productivity and to detect sand as early as possible. We present a multi-sensor framework for sand detection. Wireless acoustic sensors are applied in networked data fusion systems for sand detection. The framework is designed to collect real time data from oil pipeline using acoustic sensors and flow analyzer. Fusion was implemented using two methods; Fuzzy Art (FA) and Moving Average Filter (MAF). A test bed was established from ten acoustic sensors. The flow rate was monitored as well in order to collect the data with the same flow rate. For each acoustic sensor the average percentage error between the observed sand rate and the actual sand rate is very high and inconsistence. However, using the fusion methods, the result shows that the average percentage error of the fusion methods is decreased.
Reducing the switching activity of modified SAFF flip-flop for low power applications

The design and analysis of flip-flops is a critical issue in the design of high-performance and low power systems. In this paper, we propose a low power and a high-speed flip-flop (LP-SAFF) based on the Sense Amplifier Flip-Flop (SAFF). The saving in power consumption was achieved by reducing the switching activity at major internal nodes of the original SAFF. Our simulations show that this new flip-flop achieves major reduction in power consumption (25%-80%) and increases its performance by 5%-16%.
Editorial: Low-Power, Intelligent, and Secure Solutions for Realization of Internet of Things

This special issue aims to provide a timely discussion on the technical trends and challenges of circuits and systems on Internet of Things (IoT). Rapid advancement of networking technologies together with extreme miniaturization of computing and communication devices enable emerging and exciting applications and services that connect the cyber and physical worlds. In the future, digital sensing, communication, and processing capabilities will be ubiquitously embedded into everyday objects, turning them into the IoT. In this new paradigm, smart devices will collect data, relay the information or context to each other, and process the information collaboratively in a machine-to-machine (M2M) manner.
A gradient-based hybrid image fusion scheme using object extraction

This paper presents a new hybrid image fusion scheme that combines features of pixel and region based fusion, to be integrated in a surveillance system. In such systems, objects can be extracted from the different set of images due to background availability, and transferred to the new composite image with no additional processing usually imposed by other fusion approaches. The background information is then fused in a multi-resolution pixel-based fashion using gradient-based rules to yield a more reliable feature selection. According to Piella and Petrovic quantitative evaluation metrics, the proposed scheme exhibits a superior performance compared to existing fusion algorithms.
A low power based system partitioning and binding technique for multi-chip module architectures

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.
SDS: a framework for the design of DSP ASICs

A brief overview is given of the Sphinx Design System (SDS), a high-level synthesis system consisting of an integrated and interacting set of tools for the synthesis of digital circuits. The system is specifically tuned to the synthesis of digital signal processor (DSP) application specific integrated circuits (ASICs) from behavioral specifications written in Verilog. SDS consists of tools for behavioral, structural and logical synthesis, technology mapping and for simulation. C and SKILL have been used as the implementation and extension languages and the system will be integrated into the Cadence Edge Framework. SPS, the scheduling and allocation subsystem of SDS, is discussed in some detail.<<ETX>>
New error control enhancing technique for wireless ATM networks

In this paper we introduce a new technique to enhance the performance and cost of wireless asynchronous transfer mode (WATM) error control systems. The new technique is based on using a new scheme to reduce the ATM cell header size before applying the multiple error correcting code Bose-Chaudhuri-Hocqenghem (BCH) instead of the usual header error control (HEC) for the wireless portion of the transmission. This new scheme implies dividing the ATM cell header into segments, then comparing all segments with the first one to generate reduced-length codes to represent the compared segments. The result of applying the new technique for the wireless portion of the network is a reduced header length which is an advantage in reducing delay and cost while maintaining the required cell loss probability limit. The new technique was analyzed in terms of performance and cost and was compared to a fixed BCH system performance and found to achieve better delay values while reducing the hardware required and maintaining a cell loss probability close to the limit 10/sup -9/ at bit error rate (BER)=10/sup -3/.
A Cost-Effective Self-Healing Approach for Reliable Hardware Systems

In this paper, self-healing concept for hardware systems is investigated and a new approach is proposed. Hardware systems have been proposing imitations to biological organisms in the way they offer healing and recovery abilities. Digital systems with inspired homogeneous architecture have improved capabilities to compensate for any faults. Self-healing is defined by the ability of a system to detect faults or failures and fix them. One of the main problems in current self-healing approaches is area overhead and scalability for complex structures considering they are based on redundancy and spare blocks. This paper proposes a different approach for self-healing based on embryonic structures without a need for spare cells. The area overhead is lower compared to other approaches relying on spare cells. The proposed approach relies on time multiplexing two functions in one cell within one clock cycle. The reliability of the proposed technique is studied and compared to conventional system with different failure rates. This approach is capable of healing up to 50% of the cells where each cell can cover another neighbor failed cell at most. The area overhead is 9% for the proposed approach which is much lower compared to other approaches using spare cell. The proposed approach is applied to investigate two case studies; ALU array, and neural network.
A co-design based high-performance real-time GIS

This paper presents a co-design approach for implementing the map overlaying operation for a high-performance real-time geographical information system (GIS). The map overlaying is the most important but also the most computation-intensive operation in GIS systems. Development of an embedded environment for attaining high performance is achieved by implementing a certain computational core in hardware which is efficiently used by software. The methodology partitions the hardware/software parts based on evaluation of a cost function. The hardware core is simulated using VerilogXL and prototyped in VLSI using Synopsys and Cadence, while the software part is implemented using C++. The performance studies show that the average response time using the proposed co-design is 70 times faster than an all-software solution. The proposed co-design approach results in impressive throughput improvement without sacrificing any flexibility.
A Data Fusion Scheme for Tenet Architecture

Tenet architecture is a two-tier sensor network architecture that provides a model to implement more complex algorithms due to incorporation of less resource-restricted nodes. Stargate-class nodes called masters form the upper tier while resource-restricted nodes named motes compose the lower tier. This paper introduces a data fusion scheme for a tenet architecture based on the correlation coefficients between data set extracted from the motes. Each master selects four sentinels to calculate the direction in which an event has been detected, and then uses this data as a base data to calculate the correlation coefficient for the incoming data. The aggregate output is a result of a weighted sum of the data collected from the N sensors. The weights are calculated based on the correlation coefficients. The aggregated output is compared with a linear means square (LMS) estimator based on variance. The proposed scheme achieves good performance.