nils-herrmann/clean_scirepeval huggingface dataset:
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine

Since motion-compensated temporal filtering (MCTF) becomes an important temporal prediction scheme in video coding algorithms, this paper presents an efficient temporal prediction engine which not only is the first MCTF hardware work but also supports traditional motion-compensated prediction (MCP) scheme to provide computation scalability. For the prediction stage of MCTF and MCP schemes, modified extended double current Frames is adopted to reduce the system memory bandwidth, and a frame-interleaved macroblock pipelining scheme is proposed to eliminate the induced data buffer overhead. In addition, the proposed update stage architecture with pipelined scheduling and motion estimation (ME)-like motion compensation (MC) with level C+ scheme can also save about half external memory bandwidth and eliminate irregular memory access for MC. Moreover, 76.4% hardware area of the update stage is saved by reusing the hardware resources of the prediction stage. This MCTF chip can process CIF 30 fps in real-time, and the searching range is [-32, 32) for 5/3 MCTF with four-decomposition level and also support 1/3 MCTF, hierarchical B-frames, and MCP coding schemes in JSVM and H.264/AVC. The gate count is 352-K gates with 16.8 KBytes internal memory, and the maximum operating frequency is 60 MHz.
Low bandwidth decoder framework for H.264/AVC scalable extension

In the process of scalable video coding (SVC) decoding, large external memory bandwidth is required for SVC inter-layer prediction. In this paper, a low bandwidth decoder framework is proposed for SVC. Two main decoding schemes are developed to reduce the external memory bandwidth. Macroblock-level on-the-fly padding and on-line upsampling is proposed for SVC spatial scalability decoding. This scheme reduces 36% of decoding bandwidth and 34% of processing cycles. For SVC quality scalability, a layer-interleaving decoding scheme is proposed to eliminate all inter-layer prediction bandwidth which is 41–51% of decoding bandwidth. The corresponding hardware architectures of these two decoding schemes are also provided. This low bandwidth framework can save 33–52% of DRAM access power for SVC decoding.
Scalable module-based architecture for MPEG-4 BMA motion estimation

In this paper, we present a scalable module-based architecture for block matching motion estimation algorithm of MPEG-4. The basic module comprises one set of processing elements based on one-dimensional systolic array architecture. To support various applications, modules of processing elements can be configured to form the processing element array to meet the requirements, such as variable block size, search range and computation power. And this proposed architecture has the advantage of few I/O port counts. Based on eliminating unnecessary signal transitions in the processing element, power dissipation of datapath can be reduced to about half without decreasing the picture quality.
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC

Due to the multiple reference frame motion estimation (MRF-ME), an H.264/AVC encoder requires ultrahigh memory bandwidth. Conventional multiple reference frames single current macroblock (MRSC) scheme only considers the data reuse within one frame, and requires on-chip memory size and off-chip memory bandwidth in proportional to the reference frame number. In this paper, a single reference frame multiple current macroblocks (SRMC) scheme is presented to further exploit the data reuse at frame level. With frame-level rescheduling of the motion estimation ME procedures in different reference frames, one loaded search window can be utilized by multiple current MBs in different original frames. The demanded on-chip memory size and off-chip memory bandwidth for MRF-ME can thus be reduced to those supporting only one reference frame. Moreover, based on SRMC scheme, an architecture prototype with two-stage mode decision flow is proposed. For HDTV specifications, 62.21 KB (74.8%) of SRAM and 364.3 MB/s (62.6%) of system bandwidth are saved in comparison with the MRSC scheme
Level C+ data reuse scheme for motion estimation with corresponding coding orders

The memory bandwidth reduction for motion estimation is important because of the power consumption and limited memory bandwidth in video coding systems. In this paper, we propose a Level C+ scheme which can fully reuse the overlapped searching region in the horizontal direction and partially reuse the overlapped searching region in the vertical direction to save more memory bandwidth compared to the Level C scheme. However, direct implementation of the Level C+ scheme may conflict with some important coding tools and then induces a lower hardware efficiency of video coding systems. Therefore, we propose n-stitched zigzag scan for the Level C+ scheme and discuss two types of 2-stitched zigzag scan for MPEG-4 and H.264 as examples. They can reduce memory bandwidth and solve the conflictions. When the specification is HDTV 720p, where the searching range is [-128,128), the required memory bandwidth is only 54%, and the increase of on-chip memory size is only 12% compared to those of traditional Level C data reuse scheme.
Efficient Hardware Architecture for Large Disparity Range Stereo Matching Based on Belief Propagation

This paper introduces an efficient hardware architecture for the belief propagation(BP) algorithm especially for large disparity range stereo matching applications. BP is a popular global optimization algorithm for labelling problems which is hardware friendly. There are few types of research focus on BP implementation in large disparity range stereo matching problem since traditional belief propagation hardware implementations suffer from a server trade-off between hardware efficiency and short critical path while the disparity range is larger than 64. In this paper, we eliminate the redundancy of previous BP implementation and propose an efficient architecture without introducing any delay overhead which is more suitable for large disparity range cases. As a result, the hardware complexity is reduced from O(L2) to O(Llog2 L), where L is the disparity range. We use a time-area term to demonstrate the trade-off between various architectures, results show that the proposed one can reach 49:6% and 71:2% reduction compared to the state-of-the-art implementation with disparity ranges 64 and 128 respectively.
An UVLC encoder architecture for H.26L

Variable length code (VLC) is widely used in various compression applications. The latest under development video coding standard, H.26L, uses a unique pattern VLC code called UVLC in the test model document. In this paper, an UVLC encoder architecture is proposed to meet the requirements of TML8. This architecture is composed of a code splitter, a first 1 detector, a shifter, a length accumulator, and a code mux/output. A modified code number technique and auto self alignment technique are used to simplify the architecture. By using these techniques, the size of this architecture is much smaller when compared to traditional VLC encoders. It has been synthesized in a 0.35 /spl mu/m cell library. The size of this architecture is 980 gates while critical path is less than 6 ns.
Video encoder design for high-definition 3D video communication systems

VLSI realization of video compression is the key to real-time high-definition 3D communication systems. The newly established multiview video coding standard, as an extension profile of H.264/AVC, draws more and more attention for its high compression ratio and free-viewpoint support. Besides providing the 3D experience, multiview video can also give users complete scene perception. However, the multiple-viewpoint throughput requirement of MVC increase the complexity and hardware cost dramatically. The system memory bandwidth, on-chip memory size, and processing data throughput of each module all need to be optimized in an MVC encoder. Therefore, efficient hardware solutions for MVC architecture design are needed. In this article an overview of 3D video coding standards developments and design challenges of an MVC encoder are discussed. Then the algorithm and architecture optimization schemes are proposed. For the trade-off between system memory bandwidth and on-chip memory size, a cache-based prediction engine is proposed to ease both design challenges. Moreover, the hybrid open-close loop intra prediction scheme and the frame-parallel pipeline-doubled dual CABAC solve the throughput requirement problem. At the end of this article, based on all the proposed solutions, a prototype single-chip MVC encoder design with processing ability of 4096 × 2160 single-view to 1280 × 720 seven-view is presented.
A 120 fps 1080p resolution block-based feature extraction architecture implementation for real-time action recognition

This paper introduces an efficient hardware accelerated feature extraction architecture with a high spec of 1920×1080 image resolution at 120 fps. We choose MoFREAK feature [1] to implement in our real-time action recognition system. MoFREAK is a local spatio-temporal feature, which combines the appearance and motion descriptor independently. We design a two phase architecture to balance the throughput difference between feature detection and feature description. Binary-mask image is adopted to detect feature point location efficiently. For feature description, to reduce high bandwidth requirement for spatial-temporal MoFREAK features, block-based keypoint technique is proposed to reduce bandwidth for grouped features. The synthesis result of our proposed architecture in TSMC 40nm technology works at 200 MHz with 1039K gate counts provides 1.2K block-based features per frame at 120 fps and 0.5K blockbased features at 240 fps. With binary-mask image, we reduce about 88% cycles and bandwidth of scanning image. With blockbased keypoint, we reduce about 81% of the salinet points and keypoints. The combination of binary-mask image and blockbased keypoint reduces about 81% of the feature extraction system bandwidth.
Hybrid-mode embedded compression for H.264/AVC video coding system

Applications of high resolution videos have great potential for H.264/AVC. However, due to the multi-frame motion estimation and large search range (SR) requirement, the ultra high system bandwidth becomes the challenge for the plateform based video codec. In this paper, a hybrid-mode embedded compression (EC) is proposed. Two different strategies are respectively used to compress the reconstructed macroblocks (MBs) of intra- and intermode. Up-to 9.2 times of compression ratio (CR) can be achieved even with lossless-compression constraint. Besides, with resource sharing, this system can be integrated into H.264/AVC codec with almost no area overhead. According to the simulation results, the system bandwidth can be reduced by 66.2% and 75.3% in average for high and median quality situation.
An MPEG audio decoder chip

A single chip MPEG audio decoder which performs the decoding scheme with a direct hardware implementation approach, without programming, is presented. Based on the computation analysis of the decoder, we develop a novel design which only requires half the computational capacity of previous decoders and half the storage memory too. The chip is designed with cost-effective and simple circuitry features, and thus it provides a consumer-economical solution, especially in design time and complexity.
Investigation of a visual telephone prototyping on personal computers

An investigation of a visual telephone prototyping is presented. All the related standards such as system requirements, video codec, and speech codec are introduced. Since the most time-consuming task is video encoding, more details about the H.263 video codec standard are explained. In addition, the strategies for real-time transmission and processing are discussed. From the simulation results, the suggested prototype on personal computers shows the potential on multimedia communication for consumer products.
A 69mW 140-meter/60fps and 60-meter/300fps intelligent vision SoC for versatile automotive applications

A machine-learning based intelligent vision SoC implemented on a 9.3 mm2 die in a 40nm CMOS process is presented. The architecture realizes 140 meters active distance at 60fps and 60 meters at 300fps under Quad-VGA (1280×960) resolution while maintaining above 90% detection rate for versatile automotive applications. The system supports 64 object tracking and prediction. It raises 1.62× improvement on power efficiency and at least 1.79× increase on frame rate with the proposed knowledge-based tracking processor. The chip achieves 354.2fps/W and 3.01TOPS/W power efficiency with 69mW average power consumption.
An H.264/AVC scalable extension and high profile HDTV 1080p encoder chip

The first single-chip H.264/AVC HDTV 1080 p encoder for scalable extension (SVC) with high profile is implemented on a 16.76 mm2 die with 90 nm process. It dissipates 349/439 mW at 120/166 MHz for high profile and SVC encoding. The proposed frame-parallel architecture halves external memory bandwidth and operating frequency. Moreover, the prediction architecture with inter-layer prediction tools are applied to further save 70% external memory bandwidth and 50% internal memory access.
An integrated system for object tracking, detection, and online learning with real-time RGB-D video

This paper introduces a highly integrated system providing very accurate object detection with RGB-D sensor. To solve the problem that there are always insufficient training sets for object detection in real world, we present an online learning architecture to learn templates and to detect objects real-time. The proposed novel concept skips the training phase required in previous recognition works, and it comprises independent tracking and detection function, which collaborates with each other to make the detection more precise. We furthermore illustrate four strategies for online learning and compare the efficiency. With depth information, the experiment results perform remarkable in challenging scenarios.
Efficient moving object segmentation algorithm using background registration technique

An efficient moving object segmentation algorithm suitable for real-time content-based multimedia communication systems is proposed in this paper. First, a background registration technique is used to construct a reliable background image from the accumulated frame difference information. The moving object region is then separated from the background region by comparing the current frame with the constructed background image. Finally, a post-processing step is applied on the obtained object mask to remove noise regions and to smooth the object boundary. In situations where object shadows appear in the background region, a pre-processing gradient filter is applied on the input image to reduce the shadow effect. In order to meet the real-time requirement, no computationally intensive operation is included in this method. Moreover, the implementation is optimized using parallel processing and a processing speed of 25 QCIF fps can be achieved on a personal computer with a 450-MHz Pentium III processor. Good segmentation performance is demonstrated by the simulation results.
Video stabilization for vehicular applications using SURF-like descriptor and KD-tree

This paper describes a method to stabilize video for vehicular applications based on feature analysis. An investigation on camera motion model is conducted. Harris features are extracted under the proposed resolution adaptation scheme. Besides, features are described with SURF-like descriptor. For feature matching, KD-tree with best-bin-first search significantly reduces the matching time. A damping filer is utilized to model and predict the unwanted oscillation. 93.1% correct rate in average is achieved in divergent driving conditions. Only 0.114 second is required to process a frame at resolution 1280×960. The provided benchmark shows outperformance of the proposed method.
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application

In this paper, a power-scalable H.264 encoding system is provided with the efforts on both the algorithm and the architecture levels. For a start, a motion estimation (ME) pre-skip algorithm is adopted as a system-level power-scalable algorithm. In order to realize a dedicated hardware, a novel reconfigurable macro-block (MB) pipelining architecture is proposed. It can improve not only system flexibility but also hardware efficiency. Besides, it is also beneficial for power management with module-level gated clock insertion. According to simulation results, the proposed H.264 encoder can support power-scalable functionality in the range of about 20 to 90 mW with graceful quality degradation
Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder

A new design of psycho-acoustic model (PAM) in MPEG-2/4 AAC encoding is proposed. Differing from the conventional PC-based and DSP-based encoders, it was based on hybrid architectures. It was optimized at algorithmic and at architectural levels. At the algorithmic level, MDCT-based PAM and fixed-coefficients were used to replace the original FFT-based PAM and spreading functions. At the architectural level, the co-processor PAM design is proposed. The proposed design could be used in a real-time MPEG-2/4 AAC LC stereo encoder while maintaining CD quality below 30 MHz.
Accurate and fast segment-based cost aggregation algorithm for stereo matching

An accurate segment-based cost aggregation method is proposed in this paper. Segment-based methods can speed up the procedure according to the assumption that pixels belonging the same segment should share the same physical property. One of the most critical problems of those methods is the limited pixels within the corresponding segment. To enlarge supporting region of aggregation efficiently, we include similar adjacent segments with a fixed weight instead of a complex one. With introducing the simplified spatial weight for adjacent segments, the proposed method outperforms existing segment-based cost aggregate method[11], the Adaptive Support-weight[3], and the cross-based cost aggregation[10]. Comparing the other aspect of performance, this algorithm also speeds up the computation time by 43%.
iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor

iVisual, an intelligent visual sensor SoC integrating 2790 fps CMOS image sensor and 76.8 GOPS, 374 mW vision processor, is implemented on a 7.5 mm t 9.4 mm die in a UMC 0.18 mum CMOS Image Sensor process. Light-in, answer-out SoC architecture is adopted to avoid possible privacy problems. A feature processor is designed to eliminate the dataflow mismatch between processor array and scalar processor to increase 36% of average throughput. To increase hardware utilization, an inter-processor synchronization scheme is adopted to increase 23% of average throughput. Memory access is reduced by 94% to save 726 mW of power consumption. A bitplane-based single port memory structure is adopted to reduce SRAM area. The 205 GOPS/W power efficiency and 1.16 GOPS/mm2 area efficiency are therefore achieved by use of the proposed techniques.
On-chip principal component analysis with a mean pre-estimation method for spike sorting

Principal component analysis (PCA) spike sorting hardware in an integrated neural recording system is highly desired for wireless neuroprosthetic devices. However, a large memory is required to store thousands of spike events during the PCA training procedure, which impedes the on-chip implementation for the PCA training engine. In this paper, a mean pre-estimation method is proposed to save 99.01% memory requirement by breaking the algorithm dependency. According to the simulation result, 100 dB signal-to-error power ratio can be preserved for the resulting principal components. According to the implementation result, 6.07 mm2 silicon area is required after a 283.16 mm2 area saving for the proposed PCA training hardware.
Algorithm and architecture of prediction core in stereo video hybrid coding system

3D video will become noticeable video technology in the next generation. In this paper, a stereo video coding system is proposed from algorithm level to hardware architecture level. We propose a novel stereo video coding system by exploiting joint block compensation scheme to achieve high coding efficiency. It is also suitable for hardware implementation. Due to more than twice computational complexity relative to mono video coding systems, a new hardware architecture based on hierarchical search block matching algorithm (HSBMA) with some modification is proposed. With special data flow, no bubble cycles exist during block matching process. Proposed architecture also adopts near overlapped candidates reuse scheme (NOCRS) to save heavy burden of data access. Besides, by the proposed new scheduling, both on-chip memory requirement and offchip memory bandwidth can be reduced. A prototype chip can achieve real-time requirement under the operating frequency of 81 MHz for 30 D1 frames per second (fps) in left and right channel simultaneously, with ME/DE search range of [-64,  in horizontal direction and [-32, +31]/[-16, +15] in vertical direction. Compared with the hardware requirement for implementation of full search block matching algorithm (FSBMA), only 11.5% on-chip SRAM and 1/30 amount of PEs are needed. It shows that the hardware cost is quite small.
Efficient hierarchical motion estimation algorithm based on visual pattern block segmentation

A new hierarchical block-matching motion estimation algorithm with the segmentation of variable block size and visual pattern is presented. The block partition with visual patterns which exploits the properties of the human visual systems (HVS) is employed to get a more precise motion estimation for the detailed regions with complex motion in an image. The hierarchical search expedites the motion estimation and simplifies the processing of the stationary area. Simple control overhead and low side information are required due to the regular decomposition of visual pattern structures. The performance of proposed method is superior over the conventional full search block-matching motion estimation while reducing computational complexity drastically. Extensive experimental results are included in this paper.
A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications

An H.264/AVC encoder is implemented on a 31.72mm/sup 2/ die with 0.18/spl mu/m CMOS technology. A four-stage macroblock pipelined architecture encodes 720p 30f/s HDTV videos in real time at 108MHz. The encoded video quality is competitive with reference software requiring 3.6TOPS on a general-purpose processor-based platform.
A cost effective architecture design of inverse quantization and multichannel processing for MPEG-2 audio decoding

An MPEG-2 audio decoding processor core is described with the main theme focused on inverse quantization (IQ) and multichannel processing (MC). By means of a novel architecture, the IQ achieves a high throughput, and MC performs different types of dematrixing modes employed by the standard MPEG-2 algorithm with a flexible data allocation. The processor core is implemented and controlled with a dedicated hardware approach instead of the traditional programmable techniques. Moreover, the design has the advantages of simplicity and low cost, satisfying the high efficient requirement with fixed throughput.