nils-herrmann/clean_scirepeval huggingface dataset:
Notched circular microstrip patch antennas with bow tie shaped aperture coupling for improved axial ratio bandwidth

This paper presents improvement in the axial ratio bandwidth obtained with notched circular microstrip patch antennas. The antenna is electro-magnetically fed with bow tie shaped apertures as compared to a full circular microstrip patch of the same configuration. The simulation has been carried out using a method of moments based computer aided design tool. A near to 1:1 ellipticity to impedance bandwidth has been obtained in simulation with the above configuration. It is observed that by cutting electrically small rectangular notches (W/sub /spl eta//=/spl lambda//sub 0//25 and L/sub /spl eta//=/spl lambda//sub 0//20) into the circular patch parallel to the current lines significantly improves the ellipticity bandwidth without changing its impedance bandwidth. The current distribution of the notched patch remains unaltered and hence the radiation pattern is also not affected. This has been verified from the simulated results. In simulation 2:1 impedance bandwidth of 34% and 3 dB axial ratio bandwidth of 33% has been achieved with the above geometry. An improvement of 6% in ellipticity bandwidth is obtained over a full circular patch antenna of same configuration. The use of dielectric foam makes the antenna light weight and low cost. The above features make it an ideal element for wide band applications as required for personal, mobile satellite and wireless communication systems.
Traveling-wave microwave switch using III-N gateless devices with capacitively-coupled contacts

Radio-frequency (RF) switches using Field-Effect Transistors (FETs) have low loss, high switching speed. The fabrication process allows for monolithic integration with such as power amplifiers, phase shifters, arrays, and other components. Recent advancements in III-nitride heterostructure field-effect transistors (HFET) have led to RF switches with remarkably low-loss and high power handling capability, ideal for numerous applications [1, 2]. However, relatively large OFF-state capacitance of HFETs limits their application to frequencies below 4–6 GHz. In the past, traveling-wave (TW) RF switches using GaAs-based HFETs have been reported with operating frequencies up to 40–80 GHz . The achieved insertion loss and isolation were below 3 dB and above 24 dB, correspondingly. The problem with GaAs-based TW switches is that for broadband performance, the switch should contain significant number (at least 10) of unit cells, each comprising multi-finger FETs. To make this technology feasible, either relatively small number of cell is used, or the unit cell periphery is decreased, or the source — drain distance is increased. All these measures deteriorate the performance. In addition, GaAs-based RF switches have relatively low power handling capability, high insertion loss and low maximum operating temperatures limited by fundamental material properties.
Improving Iris Identification using User Quality and Cohort Information

Iris is one of the most distinguishable features of a human body, which remains fairly stable throughout the lifetime of an individual. This makes iris recognition one of the most reliable methods for biometric based identification. This paper investigates a new technique to improve the performance of the system by using cohort information and user-quality as the weight in the matching. The proposed approach uses the cohort information at the decision stage as cascaded classifiers. However, the second stage is only used if the first stage classifier is uncertain of its decision. The experimental results from the decision-level classifiers combination are presented, which show that the cascaded classification system significantly outperforms the single classifier, especially at lower value of FAR which is most likely to be the operating point for any system. This paper also proposes a new approach to ascertain the user-quality (iris) and illustrates its usage in the performance improvement.
Analysis of video analytic architectures

Video technology is changing rapidly due to the advancement in the sensor technology, transmission bandwidth, higher storage capability and availability of high resolution displays. Conventional video systems are being replaced by intelligent video systems to cater for automatic handling of the specific tasks and availability of high-volume data due to network of sensors. These intelligent video systems incorporate video analytics to meet the specific requirements of the user. Video analytics involves autonomous understanding of events by the machine in order to reduce the burden by removing the uninformative data for subsequent analysis and to augment the given task for monitoring, logging and action. There are numerous application areas of video analytics such as intrusion detection, crowd management, face recognition, unattended baggage detection, traffic management, video surveillance, object classification, detection & tracking, etc. The present work provides an overview of the available state-of-the-art video analytics and the ongoing development in the area of video analytics. Framework for the development of video analytics algorithms and architectural issue has also been covered.
Statistical analysis of Power Delay Estimation in adder circuit using non-clocked pass gate families

In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cells, used for various pass gates circuit design styles are evaluated in terms of area, propagation delay, power dissipation and propagation delay product. The design styles are compared by performing detailed transistor-level simulations on a benchmark circuit (CSA adder) using DSCH3 and Microwind3. We have analysed the results in a statistical way. We have compared our results with the various published results of adder circuits. We found that the speed of the proposed circuit is enhanced and power consumption as well as the area has reduced tremendously due to multiplexing control input technique. Comparing the simulated results with other pass logic designs, it was observed that in all existing logic CPL is a promising candidate for future logic design.
GPU-Accelerated Stochastic Predictive Control of Drinking Water Networks

Despite the proven advantages of scenario-based stochastic model predictive control for the operational control of water networks, its applicability is limited by its considerable computational footprint. In this paper, we fully exploit the structure of these problems and solve them using a proximal gradient algorithm parallelizing the involved operations. The proposed methodology is applied and validated on a case study: the water network of the city of Barcelona.
An Image Compression Scheme Using AC Predictions

An improved image compression scheme using AC coefficient prediction of Hadamard transform is presented in this paper. In the prediction phase, information of the nearest neighbor dc values of Hadamard transform blocks is utilized to predict the center block AC coefficients. Linear programming based optimization technique is used to predict the AC coefficients. Results indicate that this method is superior in terms of improving peak signal to noise ratio (PSNR) and minimizing blocking artifacts .
Improving FPGA Performance for Carry-Save Arithmetic

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic data flow transformations that can be applied by a hardware compiler. Field-programmable gate arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, we introduce the ¿field programmable counter array¿ (FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks. In addition to multiplication and multiply accumulation, the FPCA can accelerate more general carry-save operations, such as multi-input addition (e.g., add k > 2 integers) and multipliers that have been fused with other adders. Our experiments show that the FPCA accelerates a wider variety of applications than DSP blocks and improves performance, area utilization, and energy consumption compared with soft FPGA logic.
Adaptive and localized iris weight map for accurate iris recognition under less constrained environments

Accurate iris recognition from the distantly acquired face or eye images requires development of effective strategies which can account for significant variations in the segmented iris image quality. Unlike conventional stop-and-stare mode iris recognition, iris images acquired under less constrained imaging environment specially those under visible illumination, are degraded by multiple sources of noise. Such accompanying noise is often embedded in the feature space (say iris code), during the feature extraction phase following the image normalization, and is highly correlated with the consistency of resulting iris bits. The bit consistency can be learned from the temporal iris codes such that the stable bits are considered less likely to be corrupted by noise, or vice versa. The relationship between the bit consistency and the accompanying noise is proposed to be modeled using a non-linear relationship that can follow a power-law. Therefore the noise perturbed bits are given less emphasis while consistent bits are given higher weight. The superiority of proposed iris matching strategy is ascertained by providing comparison with other state-of-the-art algorithms using publicly available databases: CASIA.v4-distance and UBIRIS.v2. Our experimental results suggest improvement of 13.9% and 47.2% in the average rank-one recognition respectively for the CASIA.v4-distance and UBIRIS.v2 databases.
Performance Indicators in a 802.11 WLAN Deployment

Organizations and Institutions across the world are increasingly deploying 802.11 based WLAN (in short Wi-Fi) to have mobility benefits in their operations. However, due to the nature of 802.11 technology, there are more number of challenges for an administrator in ensuring the optimum performance levels for the deployed WLAN compared to a Wired Network. Degraded performance leads to connectivity problems and low data throughput for wireless clients using the Wi-Fi network. In the presented work, we have identified a set of indicators whose values at any point of time signals a possible degradation in WLAN performance. Each of the identified indicators is explained and the behavior of same is illustrated using an example with respect to presence or absence of performance anomalies in a WLAN deployment.
3D-carrier profiling in FinFETs using scanning spreading resistance microscopy

In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate underlap, dopant conformality, source/drain doping profiles. The 3D-carrier profiles as extracted for two different device approaches (extensions vs. extension-less) are conclusive in demonstrating the differences in device performance and are consistent with first order 3D-simulations.
Experimental and simulation studies for optimal position of different horn length in acoustic cleaning

The formation of ash deposits on heat transfer surfaces has been one of the main problems encountered in industrial process equipment, Ash deposits not only lower the heat transfer rates but also result in frequent maintenance and unscheduled shutdown. The various methods are adopted to prevent and clean ash, dust, scale and soot formation of which acoustic cleaning is more effective. In acoustic cleaning sound waves are sent inside the process equipment which propagate in all directions and impact energy to ash particulates which fluidize and jump up from fouled surfaces. The aim of this work is to find the optimum position where desired SPL and frequency is obtained for cleaning the process equipment. Single horn with different geometry (i.e. horn with 2,4,6,8 and 10 bends) are considered for experimental and simulation study at 3 different positions with respect to center line with different inlet pressure (1.5 bar, 2 bar and 2.5 bar) respectively and at each positions, SPL and frequency is noted. It is observed that, as horn is moved away from center line there is decrease in SPL whereas frequency is independent of positions, thus position 1 (i.e. along center line) is the most optimum position.
A Z-source DC-DC dual output converter

A Z-source dc-dc dual output converter is presented in this paper, which has inherent behavior of two conventional converters, i.e. Z-source dc-dc converter and buck-boost converter. The proposed converter is synthesized using Z-source network and integrated dual output converter (IDOC). In comparison with conventional topologies, the proposed converter uses lesser number of components and hence it is more reliable. The proposed converter exhibits a high voltage gain, while boosting, over the IDOC topology. The operating principle is introduced first and then steady-state, small-signal analysis is presented. Converter parameters design equations are formulated and then comparison with other converters is presented. The dynamic behavior of the converter is analyzed through its control-to-output transfer functions. Simulation results validates the effectiveness of theoretical analysis of proposed converter.
Unmanned aerial vehicle based bomb detection

In any Bomb rescue operation, time factor plays a vital role. As Bomb can explore at any moment, Our task is to reduce the time consuming to detect the Bomb when compared to manual detection. Detecting Bomb manually is highly risky and much time consuming process. In this paper we propose a new technique using “Quadcopter” nothing but UA V (Unmanned Aerial Vehicle). It is an air vehicle which has multiple rotors (in our paper it is 4) and is controlled by the RC transmitter (joysticks). An attempt has been made to detect the bomb by using Geiger counter module. Geiger module can detect any type of radioactive radiation emitted from the Bomb. Bomb location information is sent to the user by making use of GPS and GSM modules. We integrated Geiger module, GPS module, GSM module, Arduino-UNO as a payload to the quadcopter. We need to pass the quadcopter on the area in which the operator wants to examine and if any Bomb is present, then Geiger tube detects it Then immediately Bomb location is sent to the operator's mobile by GPS and GSM modules. The main objective of this paper is to ensure the safety of the operator and to reduce the detection process time when compared to manual detection.
Distributed solution of stochastic optimal control problems on GPUs

Stochastic optimal control problems arise in many applications and are, in principle, large-scale involving up to millions of decision variables. Their applicability in control applications is often limited by the availability of algorithms that can solve them efficiently and within the sampling time of the controlled system. In this paper we propose a dual accelerated proximal gradient algorithm which is amenable to parallelization and demonstrate that its GPU implementation affords high speed-up values (with respect to a CPU implementation) and greatly outperforms well-established commercial optimizers such as Gurobi.
Allocation of DG and capacitor units for power loss reduction in radial distribution system

The significance of optimal distributed generations (DG) placement is to offer the appropriate locations and sizes of DG units. A novel technique is proposed in this paper for optimal placement of DG units in radial distribution system to reduce real power losses while satisfying operating constraints. The proposed method for optimal placement of DG units is developed based on a new mathematical formulation. The achievability of the technique has been verified on IEEE 69 and IEEE 118 bus distribution system. Up to 50% DG penetration level has been taken into account of total system load. The results are found encouraging when compared with latest approach.
Video retrieval based on color correlation histogram scheme of clip segmented key frames

The exponential increase in video potential applications and its complexity to manage diverse and complex multimedia resources in the current digital scenario reveals an exigent demand of retrieval techniques which have efficient time and space complexity. In this paper, we propose a key frame based retrieval technique which exploits the clip segmentation for generation of key frames and block based color correlation histogram for feature extraction of key frames. The Simulation results divulge the analysis that the algorithm has better retrieval with reduced time cost.
A study of comparative analysis of different PWM techniques

Multilevel inverter has benefits like low stress on switches, low harmonic distortion and can be used in high voltage and high power applications. In this paper 7 — level Multilevel inverter which has less number of switches is considered with various PWM Techniques. The different PWM techniques considered are Carrier-Overlap PWM(CO-PWM), Variable Frequency PWM(VF-PWM), Phase Shifted PWM(PS-PWM), Alternate Phase Opposition Disposition PWM(APOD-PWM), Phase Disposition PWM(PD-PWM), Phase Opposition Disposition PWM(POD-PWM). The given topology is modeled and simulated with the help of MATLAB/SIMULINK to check which PWM technique leads low THD value.
Removal of EMG artifacts from single channel EEG signal using singular spectrum analysis

The electroencephalogram (EEG) signals often contaminated by muscle or electromyogram (EMG) artifacts. The presence of these artifacts obscure the desired information in the EEG signal. In this paper, we proposed an efficient subspace based technique named singular spectrum analysis (SSA), to remove the EMG artifacts from the single channel EEG signals. For this we proposed a new grouping technique to extract efficiently the desired component from the contaminated EEG signal by setting a threshold. Firstly, single channel signal is mapped into multichannel signal or data, called embedding. Next, the orthogonal eigenvectors are estimated from the covariance matrix of the multichannel data by singular value decomposition (SVD). Since the local variations of eigenvectors corresponding to the EEG signals are low compare with the EMG signals, we set an arbitrary threshold (0.275) to find these eigenvectors, which are used to create the subspace corresponding to the EEG signals. After identifying the subspace, the EEG signals are extracted by simply projecting the multichannel data onto this subspace followed by reverse process of embedding step. Finally, the proposed method is applied on synthetic noisy sinusoidal signals and EEG signals contaminated by the EMG artifacts. The results shows that the proposed method can efficiently removes the EMG artifacts without altering the desired components.
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; however, converting each procedure to static single assignment (SSA) form ensures a chordal interference graph, which can be colored in O(V + E) time; the interprocedural interference graph (IIG) is not guaranteed to be chordal after this transformation. An extension to SSA form is introduced which ensures that the IIG is chordal, and the conversion process does not increase its chromatic number. The resulting IIG can then be colored in linear-time.
A novel approach of standard data base generation for defect detection in bare PCB

A bare PCB is PCB without any component mounted on it. PCB plays a significant role on the performance of various electronic products. So, there is requirement of fast & quantitative assessment. Since the manual inspection system is unreliable and time consuming, automatic optical inspection method is used. This paper presents an algorithm mainly having two parts, one is image enhancement and other is standard template formation. Image enhancement includes color plane extraction, LUT Transformation, Thresholding, Filtering, and Advance morphology, while Particle analysis is used for standard template generation. Particle analysis consists of various processing operations and analysis functions that produce some information about the particles in an image. Standard template can be used for referential matching of automatic defect detection. Lastly the performance meter is used which gives the response time taken during execution of different steps. The execution time taken of the proposed algorithm is 14 ms.
Influence of interface trap charge density on reliability issues of transparent gate recessed channel (TGRC) MOSFET

This paper examines the reliability issues of In2O5Sn (ITO) gate electrode (Transparent Gate) Recessed Channel (TGRC) MOSFET by considering the influence of interface trap charges polarity and density present at the Si/SiO2 interface. The reliability of TGRC MOSFET is observed in terms of Linearity and distortion FOMs such as gm, gm3, VIP3. IIP3, HD3. IMD3. Results so obtained revealed that the existence of interface trap charges alter the flat band voltage and thus the threshold voltage; thereby modifying the linearity performance of the device. Moreover, it is also observed that as trap charge density increases, performance escalates considerably. It is found that with positive trap density of 3e12 cm−2, VIP3, IIP3 degrades owing to high distortions (gm3). Thus, results signify that TGRC MOSFET is more reliable to negative trap charges at the Si/SiO2 interface as compared to positive trap charges.
A New Method for Generating Sigma Points and Weights for Nonlinear Filtering

In this letter, a new method termed as new sigma point Kalman filter, is proposed for generating sigma points and weights for estimating the states of a stochastic nonlinear dynamic system. The sigma points and their corresponding weights are generated such that the points nearer to the mean (in inner product sense) have a higher probability of occurrence, and the mean vector and covariance matrix are matched exactly. Performance of the new algorithm is compared with the existing unscented Kalman filter (UKF), the cubature Kalman filter (CKF), the cubature quadrature Kalman filter (CQKF) and higher order unscented filter (HOUF) for two different problems. Comparison is done by calculating the root mean square error, relative computational time and track-loss. From simulation results, it can be concluded that the proposed algorithm performs with superior estimation accuracy when compared to the UKF, CKF, CQKF and HOUF.
An algorithm for faults calculation in power system

This paper presents a simple algorithm for calculation of simultaneous faults.i.e. Series and parallel faults in power system. The objective of this paper is fault calculation which provides current at fault locations as well as the current through each branch and voltage at each bus; this helps to design a good protective scheme which gives compressive and pragmatic fault analysis. The most important technique of this paper is the consideration of unequal magnitude of source e.m.f and with different phase angle to show the effect on fault analysis and protection of the system. The algorithms help to find out the different parameter to analysis the fault in simple and complicated power system.