nils-herrmann/clean_scirepeval huggingface dataset:
Charge-based chemical sensors: a neuromorphic approach with chemoreceptive neuron MOS (C/spl nu/MOS) transistors

A novel chemoreceptive neuron MOS (C/spl nu/MOS) transistor with an extended floating-gate structure has been designed with several individual features that significantly facilitate system integration of chemical sensing. We have fabricated C/spl nu/MOS transistors with generic molecular receptive areas and have characterized them with various fluids. We use an insulating polymer layer to provide physical and electrical isolation for sample fluid delivery. Experimental results from these devices have demonstrated both high sensitivity via current differentiation and large dynamic range from threshold voltage shifts in sensing both polar and electrolytic liquids. We have established electrochemical models for both steady-state and transient analyses. Our preliminary measurement results have confirmed the basic design and operations of these devices, which show potential for developing silicon olfactory and gustatory units that are fully compatible with current CMOS technology.
Multi-level simulation of a translinear analog adaptive filter

In this paper, we briefly discuss a methodology for synthesizing analog systems from a high-level behavioral specification using a class of circuits called dynamic translinear circuits. We illustrate this method by synthesizing a Least-Mean-Square (LMS) adaptation algorithm used in an analog adaptive filter. The resulting systems can be simulated at various levels of abstraction during the design phase. As an example, we present simulation results from a four-tap analog adaptive filter simulated using Matlab and SPICE.
Inverting the bipolar differential pair for low-voltage applications

In this paper, the author presents a new bipolar differential transconductor that functions just like an emitter-degenerated differential pair, except for the following: it operates on a low power supply; it has a rail-to-rail common-mode input-voltage range; permits a wide output-voltage swing; has a transconductance gain that is nearly constant with the common-mode input voltage; and requires only n-p-n transistors in the signal path. We describe intuitively how the circuit functions and provide DC measurements from a prototype circuit, breadboarded from a quad TPQ3904 and a thick-film resistor array demonstrating proper operation on a single-ended 1.2-V power supply.
A simple way to extend the common-mode input-voltage range of the MOS differential pair

In this paper, we describe a simple technique involving indirect negative feedback that extends the useable common-mode input-voltage range of the MOS differential pair by a saturation voltage. In this method, we use a replica differential pair to sense when the bias transistor supplying the tail current falls out of saturation. We then set the bias voltage so that the sum of the two differential-pair output currents is equal to the bias current. We present experimental results from a version of the differential pair that was fabricated in a 0.5 /spl mu/m CMOS process along with a comparison with an identical differential pair with a fixed bias with respect to their common-mode input ranges.
A low-voltage MOS cascode bias circuit for all current levels

In this paper, the author describes a simple low-voltage MOS cascode bias circuit that functions well at all current levels, ranging from weak inversion to strong inversion. He describes an approach to defining the onset of saturation that is generally useful from a bias-circuit design viewpoint and explains specifically how it was used in designing the low-voltage cascode bias circuit. The author discusses an efficient strategy for laying out the cell in the full-stacked style. He also presents experimental results from a version of the bias circuit that was fabricated in a 1.2-/spl mu/m CMOS process.
A low-voltage MOS cascode current mirror for all current levels

In this paper, we describe a simple low-voltage MOS cascode current mirror that functions well at all current levels, ranging from weak inversion to strong inversion. The circuit features a wide output voltage swing and requires an input voltage of approximately one diode drop plus a saturation voltage. We present experimental results from a version of the current mirror that was fabricated in a 0.5 /spl mu/m CMOS process along with a comparison with several other current mirrors with respect both to required input voltage and to output compliance voltage.
Silicon synaptic adaptation mechanisms for homeostasis and contrast gain control

We explore homeostasis in a silicon integrate-and-fire neuron. The neuron adapts its firing rate over time periods on the order of seconds or minutes so that it returns to its spontaneous firing rate after a sustained perturbation. Homeostasis is implemented via two schemes. One scheme looks at the presynaptic activity and adapts the synaptic weight depending on the presynaptic spiking rate. The second scheme adapts the synaptic "threshold" depending on the neuron's activity. The threshold is lowered if the neuron's activity decreases over a long time and is increased for prolonged increase in postsynaptic activity. The presynaptic adaptation mechanism models the contrast adaptation responses observed in simple cortical cells. To obtain the long adaptation timescales we require, we used floating-gates. Otherwise, the capacitors we would have to use would be of such a size that we could not integrate them and so we could not incorporate such long-time adaptation mechanisms into a very large-scale integration (VLSI) network of neurons. The circuits for the adaptation mechanisms have been implemented in a 2-/spl mu/m double-poly CMOS process with a bipolar option. The results shown here are measured from a chip fabricated in this process.
A second-order section built from autozeroing floating-gate amplifiers

We introduce the autozeroing floating-gate (AFGA) second-order section. We built this second-order filter where the corner frequency and Q are electronically tunable based on a classic filter topology and principles of operational transconductance amplifiers. We built this second-order filter using three AFGAs-our floating-gate amplifier that sets its operating point by the interaction of hot-electron injection and electron tunneling.
A CMOS programmable analog memory-cell array using floating-gate circuits

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells.
Multiple-input translinear element networks

We describe a new class of translinear circuits that accurately embody product-of-power-law relationships in the current signal domain. We call such circuits multiple-input translinear element (MITE) networks. A MITE is a circuit element, which we defined recently that produces an output current that is exponential in a weighted sum of its input voltages. We describe intuitively the basic operation of MITE networks and provide a systematic matrix technique for analyzing the nonlinear relationships implemented by any given circuit. We also show experimental data from three MITE networks that were fabricated in a 1.2-/spl mu/m double-poly CMOS process.
Multiple-input translinear element log-domain filters

Describes the implementation of log-domain filters with multiple-input translinear elements (MITEs). Such circuit elements produce output currents that are exponential in a weighted sum of their input voltages. The author discusses the operation of the MITE building block circuit from which he constructs MITE log-domain filters. Then, he analyzes the behavior of a first-order low-pass MITE log-domain fitter, the simplest such circuit. He also presents a fully tunable second-order low-pass MITE log-domain filter with experimental measurements of a version of the second-order filter that was fabricated in a 1.2-/spl mu/m double-poly CMOS process with an npn bipolar option. The author also describes a simple procedure for synthesizing MITE log-domain filters from state-space descriptions. He can obtain such state-space descriptions from a variety of sources; the procedure described can be used regardless of the source of the description. We can often derive such descriptions conveniently from already extant filters that have been previously implemented within a different class of filters. The synthesis procedure is illustrated by deriving two simple MITE log-domain filters from single-ended voltage-mode operational transconductance amplifier C filter prototypes.
An Autozeroing Floating-Gate Amplifier

We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET's behavior, we obtain this adaptation with no additional circuitry. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and input waveforms. This autozeroing floating-gate amplifier demonstrates how to use continuous-time floating-gate adaptation in amplifier design.
Evolution of a folded floating-gate differential pair

The author presents a folded floating-gate MOS (FGMOS) differential pair circuit that is capable of simultaneously providing a rail-to-rail common-mode input voltage range and a rail-to-rail output voltage swing with a low power-supply voltage. In this configuration, the voltage drop across the bias current source is folded up into the same range over which the output voltages swing, facilitating low-voltage operation. The floating-gate charge can be used to trim out the offset voltage of the differential pair and to reduce the required power-supply voltage for a given bias current level. The author provides both a qualitative description of how the circuit works and a quantitative incremental high-frequency analysis of the differential-mode and common-mode transconductance gains and common-mode rejection ratio of the circuit. He also shows experimental measurements from a prototype circuit that was fabricated in a 1.2 /spl mu/m double-poly CMOS process.
Floating-gate techniques for assessing mismatch

I discuss the importance of capacitor matching in the context of using charge stored on floating-gate MOS (FGMOS) transistors to compensate for transistor mismatch in analog circuits. I describe a simple technique that only involves static measurements for assessing the relative mismatch between capacitors. I also show experimental measurements of capacitor mismatch for small capacitors fabricated in 1.2-/spl mu/m and 0.35-/spl mu/m double-poly it n-well CMOS process that are commonly available.
Homeostasis in a Silicon Integrate and Fire Neuron

In this work, we explore homeostasis in a silicon integrate-and-fire neuron. The neuron adapts its firing rate over long time periods on the order of seconds or minutes so that it returns to its spontaneous firing rate after a lasting perturbation. Homeostasis is implemented via two schemes. One scheme looks at the presynaptic activity and adapts the synaptic weight depending on the presynaptic spiking rate. The second scheme adapts the synaptic "threshold" depending on the neuron's activity. The threshold is lowered if the neuron's activity decreases over a long time and is increased for prolonged increase in postsynaptic activity. Both these mechanisms for adaptation use floating-gate technology. The results shown here are measured from a chip fabricated in a 2-µm CMOS process.
Synthesis of dynamic multiple-input translinear element networks

In this paper, the author discusses an approach to the synthesis of dynamic translinear circuits built from multiple-input translation elements (MITEs). In this method, we realize separately the basic static nonlinearities and dynamic signal-processing functions that when cascaded together, form the system that one wishes to construct. The circuit is then simplified systematically through local transformations that do not alter the behavior of the system. The author illustrates the method by synthesizing a simple nonlinear dynamical system, an RMS-DC converter.
A folded floating-gate differential pair for low-voltage applications

the author presents a new folded differential pair topology that is suitable for low-voltage applications. The new differential pair is made from floating-gate MOS (FGMOS) transistors and simultaneously provides a rail-to-rail common-mode input voltage range with a high rejection of the common-mode input voltage by keeping the sum of the two output currents fixed. Moreover, when biased in weak or moderate inversion, the allowable output voltage swing is also almost from rail-to-rail. The author discusses the operation of the circuit and some of the trade-offs involved in its design. He also shows experimental measurements from a version of the circuit, operating on a single 1.8 V power supply, that was breadboarded from transistors fabricated in a 1.2 /spl mu/m double-poly n-well CMOS process.
A UNIVERSAL MEMS FABRICATION PROCESS FOR HIGH-PERFORMANCE ON-CHIP RF PASSIVE COMPONENTS AND CIRCUITS

We have developed a fabrication approach that allows us to integrate monolithically on silicon high-performance on-chip radio-frequency (RF) passive components, such as inductors, transformers and fixed and tunable capacitors. We applied two- layer polysilicon surface micromachining to construct the devices, which were suspended over 30-pm-deep cavities formed into the silicon substrate. We also performed electroless copper (Cu) plating to metallize the polysilicon structures for high conductivity. The inner surfaces of the cavities were Cu coated too, providing good RF ground and electromagnetic shielding. The deep cavities dramatically reduce the electric and magnetic couplings and parasitic capacitances between the devices and the substrate. High quality factors over 30 and resonant frequencies over 10 GHz have been achieved for inductors. We have designed and fabricated high-performance varactors, transformers and LC-
Synthesis of multiple-input translinear element log-domain filters

Presents a single procedure for synthesizing multiple-input translinear element (MITE) log-domain filters from state-space descriptions. We can obtain such state-space descriptions from a variety of sources, and the procedure that is described can be utilized regardless of the source of the description. We can often derive such descriptions conveniently from already extant filters that have been previously implemented using a different class of filters. The author illustrates the synthesis procedure by deriving two simple MITE log-domain filters from single-ended voltage-mode OTA-C filter prototypes-both a first-order lowpass filter and a fully tunable second-order lowpass filter are synthesized.
Translinear analog signal processing: a modular approach to large-scale analog computation with multiple-input translinear elements

The author describes a general framework, called translinear analog signal processing (TASP), for implementing continuous-time analog signal processing systems that have a wide dynamic range and can operate with a low power-supply voltage. Such analog signal processing systems are highly modular, comprising only grounded capacitors, constant current sources, and simple circuit primitives called multiple-input translinear elements (MITEs). Moreover, the behavior of a TASP system is well described in terms of commonly used linear and nonlinear signal processing functions. Consequently, these systems should be highly amenable to behavioral-level descriptions and to computer-aided design automation techniques. The author briefly discusses the operation of MITEs and their circuit implementation. He describes the two classes of MITE circuits, MITE networks and MITE log-domain filters, that together make up the TASP framework and shows experimental data from a basic circuit from each class. The author then illustrates how we can interface these circuits in a seamless fashion to build large-scale TASP systems. Finally, he discuss the possibility of building adaptive and reconfigurable TASP systems.
A floating-gate technology for digital CMOS processes

We discuss the possibility of developing high-quality floating-gate memories and circuits in digital CMOS technologies that have only one layer of polysilicon. Here, the primary concern is whether or not we can get adequate control-gate linearity from MOS capacitors. We employ two experimental procedures to address this issue and find acceptable floating-gate circuit behaviour with MOS capacitors. First, we simultaneously characterize an MOS capacitor and a linear capacitor; the experimental data show that MOS capacitors behave similarly to linear capacitors over a finite, but usable range. Second, we characterize two typical floating-gate MOS circuit primitives, a floating-gate amplifier and a multiple-input translinear element, two basic circuits that rely heavily on the linearity of the capacitors that couple into the floating gates. Our measurements show that floating-gate circuits with MOS-capacitor control gates behave like their counterparts built with linear capacitors over specific regions of operation.
Adaptive circuits using pFET floating-gate devices

In this paper, we describe our floating-gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add floating-gate charge by electron tunneling, and we remove floating-gate charge by hot-electron injection. With this floating-gate technology, we cannot only build analog EEPROMs, we can also implement adaptation and learning when we consider floating-gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of floating-gate devices and we present two representative non-adaptive applications. First, we discuss using the floating-gate pFETs as non-volatile voltage sources or potentiometers (e-pots). Second, we discuss using floating-gate pFETs to build translinear circuits that compute the product of powers of the input currents. We then discuss the physics, behavior, and applications of adaptation using floating-gate pFETs. The physics of adaptation starts with floating-gate pFETs with continuous tunneling and injection currents. A single floating-gate MOS device operating with continuous-time tunneling and injection currents can exhibit either stabilizing or destabilizing behaviors. One particular application is an autozeroing floating-gate amplifier (AFGA) that uses tunneling and pFET hot-electron injection to adaptively set its DC operating point. Continuous-time circuits comprising multiple floating-gate MOS devices show various competitive and cooperative behaviors between devices. These floating-gate circuits can be used to build silicon systems that adapt and learn.
Floating-gate devices: they are not just for digital memories any more

Since the first reported floating-gate structure in 1967, floating-gate transistors have been used widely to store digital information for long periods in structures such as EPROMs and EEPROMs. Recently floating-gate devices have found applications as analog memories, analog and digital circuit elements, and adaptive processing elements. Floating-gate devices have found commerical applications, e.g. ISD, for long-term non-volatile information storage devices for analog applications. The focus of floating-gate devices has been towards fabrication in standard CMOS processes, as opposed to the specialized processes for fabricating digital non-volatile memories. Floating-gate circuits can be designed at any or all of three levels: analog memory elements, capacitive-based circuit elements, and adaptive circuit elements.
A transistor-only circuit model of the autozeroing floating-gate amplifier

We developed an transistor-only version of our autozeroing floating-gate amplifier (AFGA). We use a subthreshold transistor to model the behavior of an electron-tunneling device, and we use another subthreshold transistor to model the behavior of pFET hot-electron injection. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data. This circuit is a bandpass filter, and behaves similarly to the AFGA with different operating parameters. Both the low-frequency and high-frequency cutoffs are controlled electronically, as is done in continuous-time filters. This circuit has a low-frequency cutoff at frequencies above 1 Hz, and therefore complements the operating regimes of the AFGA.
Synthesis of multiple-input translinear element networks

We describe two systematic procedures for synthesizing multiple-input translinear element (MITE) networks that produce an output current that is equal to product of a number of input currents, each of which is raised to an arbitrary rational power. By using the first procedure, we obtain a MITE network, called a two-layer network, that is relatively insensitive to mismatch in the MITE weight values. By using the second procedure, we arrive at a MITE network, called a cascade network, that reduces the fan-in required of each MITE. We illustrate each of these procedures with an example.
Floating-gate MOS synapse transistors

Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEPROM transistors, typically are optimized for binary-valued storage , and do not compute their own memory updates. Although floating-gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through SiO2, these devices have not seen wide use as memory elements in silicon learning systems.
Continuous-time feedback in floating-gate MOS circuits

We present the negative- and positive-feedback circuit configurations of continuous-time floating-gate MOS circuits. We start by reviewing the dynamics of our pFET and nFET single-transistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circuits with one floating-gate synapse, including data from nFET and pFET synapses. We then show examples of competitive and cooperative behavior in multiple-synapse circuits. We present experimental data from circuits fabricated in the 2 /spl mu/m n-well Orbit CMOS process available through MOSIS.