nils-herrmann/clean_scirepeval huggingface dataset:
Comprehensive analysis of TIPS-Pentacene: Polymer blend organic field-effect transistor for device and circuit simulation

In this work, a TCAD based approach is presented to model electrical behavior of TIPS-Pentacene: polymer blend organic field-effect transistors (OFETs). Stress induced and temperature induced effects are also captured, thereby accurately modeling the device behavior under different operating conditions. The framework is validated against experimental results and is then used to estimate the effect of temperature on characteristics of inverter circuit using this device.
Design analysis of wireless sensors in BAN for stress monitoring of Fighter Pilots

It is anticipated that wearable wireless sensors in Body Area Network (BAN) will increase the functionality of lifestyle and health care devices to gradually match the needs of society by year 2010 and people will carry their personal Body Area Network. The applications in areas like lifestyle, assisted living, sports, entertainment functionalities, toxic levels in the lungs of a Fire- Fighter, radiation exposure in war zones etc are already being explored. Yet one very exciting, revolutionary and life saving application in the form of Real time stress monitoring of Fighter Pilots through wearable wireless sensors in BAN has not been thought of. The statistics reveal that 40% of total flying accidents in Indian Air Force (IAF) occur due to pilot error, however, so far no scientific study has been undertaken to ascertain whether certain non-action/delayed actions taken by pilots in such accidents were related to stress induced. The current paper proposes the entire workable concept which when implemented will be able to provide some valuable insights of human behavior under high 'g' conditions as well as save lives of pilots.
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits

The increasing importance of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the recent years to infer the use of the carry-save representation in the synthesis of arithmetic circuits. Yet, many cases of practical interest cannot be handled due to the scattering of logic operations among the arithmetic ones - particularly in arithmetic computations which are originally described at the bit level in high-level languages such as C. We therefore introduce an algorithm to restructure dataflow graphs so that they can be synthesized as high-quality arithmetic circuits, close to those that an expert designer would conceive. On typical embedded software benchmarks which could be advantageously implemented with hardware accelerators, our technique always reduces tangibly the critical path by up to 46% and generally achieves the quality of manual implementations. In many cases, our algorithm also manages to reduce the cell area by up to 10%-20%.
A generative model for intention recognition and manipulation assistance in teleoperation

Performing remote manipulation tasks by tele-operation with limited bandwidth, communication delays and environmental differences is a challenging problem. In this paper, we learn a task-parameterized generative model from the teleoperator demonstrations using a hidden semi-Markov model that provides assistance in performing remote manipulation tasks. We present a probabilistic formulation to capture the intention of the teleoperator, and subsequently assist the teleoperator by time-independent shared control and/or time-dependent autonomous control formulations of the model. In the shared control mode, the model corrects the remote arm movement based on the current state of the teleoperator; whereas in the autonomous control mode, the model generates the movement of the remote arm for autonomous task execution. We show the formulation of the model with virtual fixtures and provide comparisons to benchmark our approach. Teleoperation experiments with the Baxter robot for reaching a movable target and opening a valve reveal that the proposed methodology improves the performance of the teleoperator and caters for environmental differences in performing remote manipulation tasks.
Enhancing e-governance using data mining tools and techniques

With the influx of digital India movement, our country is equipped with strong digital infrastructure. In today's scenario, Government provide services to common people at their doorsteps through e-governance. Efficiency of government services can be enhanced through the use of ICT. The delegation of e-governance projects is channelized from central to state level and then to Gram Panchayats. Funds disbursed and the fund utilized for different projects are present in digital format at every level. After deploying the projects, there is a need to analyze the data stored at various levels. The effectiveness of government projects can be analyzed by applying various data mining tools and techniques. Data mining helps to extract hidden patterns from large pool of data. The aim of this research is to analyze the e-Governance data to measure the efficiency of different government schemes. Data mining techniques are used to analyze the data acquired from MNREGA (Mahatma Gandhi National rural employment guarantee act) and SBM (Swachh Bharat Mission) projects. The proposed approach of data mining can be helpful for the government to further analyze other public beneficiary schemes.
Micro power battery state-of-charge monitor

This paper presents the design and implementation of a micro power battery state of charge monitor. The novelty of this design lies in the extreme low power consumption and accurate prediction of the battery reserve time. The average current drawn is successfully limited to 60 muA, which is significantly smaller than those in currently available devices. The proposed design predicts the reserved battery charge with an accuracy of 5% under different discharge conditions. The automated learning scheme using software is utilized. Protection of the battery against excessive current drain and usage outside the specified temperature range is incorporated. This paper details the proposed technique adopted for power reduction. The battery temperature and current sensing circuits are normally in power down mode, they go into active mode for the microcontroller to take measurements. An ON/OFF ratio of 1:153 is achieved which results in power reduction by a factor of 59.30. The average current requirement of the proposed design is reduced from 3302.79 muA to 55.69 muA with the adoption of power reduction approach. The proposed design has been tested on a NiMH, NiCd and Li-Ion battery packs and the experimental results confirm the utility of the proposed design .
Comparative evaluation of algorithms for effective data leakage detection

Researchers have proposed several mechanisms to secure data from unauthorized use but there is very less work in the field of detecting and managing an authorized or trustworthy agent that has caused a data leak to some third party advertently or unknowingly. In this paper, we implement methods aimed at improving the odds of detecting such leakages when a distributer's sensitive data has been leaked by trustworthy agents and also to possibly identify the agent(s) that leaked the data. We also implement some data allocation strategies that can improve the probability of identifying leakages and can also be used to assess the likelihood of a leak at a particular agent assuming the fact that the data was not simply guessed by the third party where the leaked data set has been found. We also propose new allocation strategies that work on the basis of No-Wait model, i.e. agent does not need to wait for other agents' allocation and it is different from already proposed model that makes an agent wait for others. These methods do not rely on the alterations of the distributed data, but rather focus on minimizing the overlapping of the allocated data items to various agents, thus facilitating an exact determination of the guilty agent in a particular data leakage scenario.
A 12-/14-bit, 4/2MSPS, 0.085mm2 SAR ADC in 65nm using novel residue boosting

In this paper, a re-confîgurable 12/13/14-bit SAR ADC based on a 12-bit ADC core is presented. A novel residue-boosting algorithm is developed to increase the bit resolution of a SAR ADC up to 2 bits without significant additional area and power. In the 12-bit mode, the 65nm prototype shows both DNL and INL of about +/−0.5 LSB at 4MSPS, and in 14-bit mode, DNL and INL are about +/− 1 LSB and +/− 2 LSB at 2MSPS. ENOB is 11.5 bit and 13 bit for 12-bit and 14-bit mode each. The area of the ADC is 0.085mm<sup>2</sup>.
Low loss AlInN/GaN Monolithic Microwave Integrated Circuit switch

We report on the first AlInN/GaN Heterojunction Field Effect Transistor (HFET) based Monolithic Microwave Integrated Circuit (MMIC) switch. Lattice-matched AlInN/GaN heterostructures with indium contents of ∼17% exhibit a very large conduction band discontinuity, ΔE<inf>C</inf>, of 1.7 eV. This large discontinuity results in 2DEG densities as high as 4.7×10<sup>13</sup> cm<sup>−2</sup>  and electron mobilities as high as 1617 cm<sup>2</sup>/V-s . As a result these heterostructures can achieve record low sheet resistances, making them very attractive candidates for ultra-low loss microwave and other switching devices.
Towards the automatic exploration of arithmetic-circuit architectures

The optimization of arithmetic circuits has always been essentially a manual task: arithmetic experts study the best architectures for arithmetic components and write libraries of generators, and designer instantiate library components and rely on logic synthesizers to obtain good implementations. In this paper we look at the capabilities of commercial synthesizers when it comes to arithmetic circuits, and observe that they are essentially unable to switch from one arithmetic architecture to another (e.g., from a ripple-carry to a carry-look ahead adder). Therefore, users relying on logic synthesis miss most optimization potentials. We therefore investigate algorithms for factorization which can prepare structured VHDL or Verilog for synthesizers to implement, and show first steps into pruning the search space from many irrelevant or equivalent solutions. Our results are still very limited in complexity but we show that our techniques successfully concentrate on the automatic exploration of very different solutions, and discover architectures known and unknown to expert designers, such as different types of adders, the carry-save representation, or improved multipliers. This is a first step toward a class of arithmetic optimizers which sit on top of classic logic synthesizers
Atom Probe Tomography for 3D-dopant analysis in FinFET devices

As the nano scale device performance depends on the detailed engineering of the dopant distribution, advanced doping processes are required. Progressing towards 3D-structures like FinFETs, studying the dopant gate overlap and conformality of doping calls for metrology with 3D-resolution and the ability to confine the analyzed volume to a small 3D-structure. We demonstrate that through an appropriate methodology this is feasible using Atom Probe Tomography (APT). We extract the 3D-dopant profile and important parameters such as gate overlap and profile steepness, from transistor formed with plasma doping processes. Analyzing samples with different doping processes, the APT results are entirely consistent with device performances (Ioff vs. Ion).
Design of binary decision diagram (BDD) optical adder

In this paper a new design technique for 4-bit carry look ahead optical adder based on binary decision diagram (BDD) has been proposed. This technique can be used for the design of higher order bits. Performance analysis is carried out for longest and shortest path lengths in terms of power attenuation. In this paper, the threshold value of output power to interpret as logic 1 or logic 0 are also determined.
Performance analysis of hybrid multiple radio IoT architecture for ubiquitous connectivity

In this study, we propose a novel physical layer architecture which is a hybrid of IEEE 802.15.4 and IEEE 802.11b for providing ubiquitous connectivity in IoT remote sensing platforms. The proposed architecture multiplexes the commonly available functional units of IEEE 802.15.4 and IEEE 802.11b, thereby achieving significant area and power savings. In order to achieve this, we modified the existing PHY layer to incorporate QPSK and RC pulse shaping for both the radios during the process of modulation. Performance analysis shows that the proposed architecture resulted in an area savings of 17.2 % and power savings of 17.8 % compared to traditional architecture without any performance degradation. In addition the CMOS transistors count is reduced by 6592, which is a significant reduction in complexity when compared to traditional independent radio's architectures.
Iris recognition using quaternionic sparse orientation code (QSOC)

Personal identification from the iris images acquired under less-constrained imaging environment is highly challenging problem but with several important applications in surveillance, image forensics, search for missing children and wandering elderly. In this paper, we develop and formulate a new approach for the iris recognition using hypercomplex (quaternionic or octonionic) and sparse representation of unwrapped iris images. We model iris representation problem as quaternionic sparse coding problem which is solved by convex optimization strategy. This approach essentially exploits the orientation of local iris texture elements which are efficiently extracted using a binarized dictionary of oriented atoms. The feasibility of this approach is evaluated, both for the recognition and the verification problem, on the publicly available visible illumination UBIRIS V2 database. Our experimental results using the proposed formulation illustrate significant improvement in performance (e.g., ~30% improvement in rank-one recognition accuracy) over the previously studied sparse representation approach for the visible illumination iris recognition.
Comparative study of image encryption using 2D chaotic map

Securing digital image during transmission is very much important in the current era. For this purpose, cryptographic techniques as well as chaotic maps can be applicable. In this paper, we have given a detailed study of the image encryption using different 2D chaotic maps such as Arnold 2D cat map, Baker map, Henon map, Cross chaos map and 2D logistic map. The security analysis of these techniques has been done by the help of NPCR (Number of Pixels Change Rate) and UACI (Unified Average Changing Intensity) values. The experimental results of NPCR and UACI show the effectiveness of the encryption processes of different techniques.
Integrating shape and texture for hand verification

This paper investigates the performance of a bimodal biometric system using fusion of shape and texture. We propose several new hand-shape features that can be used to represent the hand shape and improve the performance for hand-shape based user authentication. We also demonstrate the usefulness of discrete cosine transform (DCT) coefficients for palmprint authentication. The score level fusion of hand shape and palmprint features using product rule achieves best performance as compared to max or sum rule. The two hand shapes of an individual are anatomically similar. However, the palmprint information from the two hands can be combined to further improve performance and is investigated in this paper. Our experimental results on the database of 100 users achieve promising results and therefore confirms the usefulness of the proposed method.
TCP-ADA: TCP with adaptive delayed acknowledgement for mobile ad hoc networks

Earlier studies have shown that TCP suffers from performance degradation over mobile ad hoc networks due to poor wireless channel characteristics and host mobility. This paper shows that generating acknowledgement for each data packet also deteriorates TCP throughput over these networks more significantly than in wired networks. In these networks, acknowledgement packets share the path with data packets. This creates the contention and collision between ACK and DATA packets, resulting in reduced TCP throughput. Decreasing the number of ACKs enhances the performance of TCP as it reduces the contention and collision with DATA packets. We analyse this enhancement mathematically and derive the relationship between throughput and number of DATA packets covered in one ACK. The study shows that maximum throughput is achieved when one ACK acknowledges full congestion window of packets. Based on this analysis, we devise and propose TCP with adaptive delayed acknowledgement (TCP-ADA), which tries to decrease the number of ACKs to one per congestion window, adapting the ACK generation time. Simulation analysis is performed to investigate the enhancement achievable in practical scenario and these results corroborate our mathematical study.
A proposed reliable and power efficient 14T full adder circuit design

This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a similar 14T adder circuits and found the proposed adder circuit consumes lower power due to smaller load capacitance and parasitic resistance. The logic level at the sum and carry nodes maintains at strong 1 or strong 0 due to proposed circuit's design architecture.
Optimistic congestion control to improve the performance of mobile ad hoc network

TCP Vegas for Ad hoc network is an end to end congestion avoidance protocol that uses conservative approach to determine and control network state. But this conservation scheme is not good in all conditions and it can unnecessarily reduce the size of congestion window. This paper proposes improved TCP Vegas an improvement over TCP Vegas in Ad hoc network that utilizes round trip time variation of packets at sender side, short term throughput and inter-delay difference at receiver side to measure the network state and then controls congestion window considering the path length and network state. Simulation results show the improvement of 5 to 15 % over Ad hoc TCP Vegas in high mobility and high traffic conditions.
A rapid charging system with bi-directional power flow for plug-in hybrid electric vehicle

This paper presents the rapid battery charging system with bidirectional power flow capability of Plug-in-Hybrid Electric Vehicle (PHEV) application. Rectangular Phase Shift with PWM (RPPWM) is used for Zero Voltage Switching (ZVS) based Dual-Active-Bridge, controls the power flow capability in both direction and reduces the control complexity. Boost converter is fed from the rectified ac mains voltage to regulate the constant output DC voltage at desired level and to improve the power factor. The proposed boost converter provides the bidirectional power flow, DAB is implemented. It chooses either the Constant-Current or Constant-Voltage approach and operates using RPPWM and Proportional-Integral controllers by which system complexity is reduced. The system could charge the battery from C.C to C.V smoothly which leads to a longer life cycle and safe operation of battery. In proposed control method, SOC reaches maximum value within 56.4 minutes which is less compared to that of the time. The charging/discharging response of the proposed system is tested and verified through simulation Study is performed in MATLAB/SIMULINK.
A proposed tail transistor based SRAM cell

In this paper, we have proposed a write efficient SRAM cell. The write power consumption is reduced compare to the 6T cell due to two extra nMOS tail transistors in the pulldown path of the respective inverter. These two tail transistors avoid the discharging of bitlines. The proposed cell is simulated with the help of the MICROWIND3 using advanced BSIM4 model. The SRAM cell is 1.85X faster and consumes 58% less power than the conventional SRAM cell during write mode. Due to two extra transistors, read power consumption and delay are degraded.
Multimodal biometrics management using adaptive score-level combination

This paper presents a new evolutionary approach for adaptive combination of multiple biometrics to dynamically ensure the performance for the desired level of security. The adaptive combination of multiple biometrics is achieved at the matching score level. The score level fusion rules are adapted to ensure the required/desired system performance using particle swarm optimization. The experimental results presented in this paper illustrates two main advantages of the proposed score-level approach over the decision level approach; better performance and stable performance that require smaller number of iterations. There has not been any effort in the literature to investigate the performance of adaptive multimodal fusion algorithm on real biometric data. This paper also presents the performance of the proposed algorithm on real biometric data which further validates contributions from this paper.
Weights Binary Decision Diagram (WBDD) and its application to Matrix Multiplication

Binary Decision Diagrams (BDDs) are the most frequently used data structure for handling Boolean functions because of their excellent efficiency in terms of time and space. Algebraic Decision Diagrams (ADDs) have been used to solve general purpose problems such as Matrix Multiplication, logic synthesis and Formal Verification. We propose a new type of BDD called Weights Binary Decision Diagram (WBDD). We apply the proposed BDD for matrix multiplication. We express weights as binary values and the matrix can be represented by a collection of matrices taken for each weight bit. Since the Boolean expressions are for weight values, the computations are easier and faster compared to ADDs.
Implementation of radix 4 booth multiplier using MGDI technique

Here we presents Modified Gate Diffusion Input technique used to implement radix 4 Booth Multiplier. Use of Booth algorithm as compare to other multiplication algorithms in multiplication process shows less computation and less complexity as it minimizes the total number of partial products to half of it. Booth multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design with new MGDI technique gives better result in terms of area, switching delay and power dissipation. The radix 4 Booth Multiplier is designed with MGDI technique in DSCH 2 and layout generated in microwind tool. The simulation done using 0.25μm technology at 2.5v supply voltage and results is compared with conventional CMOS technique. Simulation result shows great improvement in terms of area, switching delay and power dissipation.