nils-herrmann/clean_scirepeval huggingface dataset:
Properties and performance of the hierarchical hypercube

Interconnection networks play a crucial role in the performance of parallel systems. The paper introduces the hierarchical hypercube (HHC) interconnection topology, which is suitable for parallel systems with thousands of processors. An appealing property of this network is the low number of connections per processor which enhances the VLSI design and fabrication of the system. Other alluring features include symmetry and logarithmic diameter which imply easy and fast algorithms for communication. A wide class of problems, the Divide & Conquer class (D&Q), is easily and efficiently solvable on the HHC topology. The solution of a D&Q problem instance having up to k inputs, requires a time complexity of O(log/sub 2/ k).<<ETX>>
A high speed pipelined FFT processor

The authors describe a novel modular design and a VLSI implementation of a bit-serial pipelined fast Fourier transform (FFT) coprocessor. The proposed architecture is based on a distributed hardwired control mechanism. The control of various subunits in the processor is done by local controllers and the synchronization of operations is provided by a global controller. This FFT processor is a custom-built chip which has a built-in self-test (BIST) capability. BIST is provided using a coprocessor to a microprocessor, and the data transfer is controlled by asynchronous signals. A prototype of the proposed processor was implemented in 3- mu m SCMOS technology; it can operate at a maximum frequency of 50 MHz. The chip is a 32-pin square package, and it has a total area of 2.2 cm/sup 2/.<<ETX>>
A VLSI architecture for rate-distortion optimized motion compensation using variable size blocks

The authors propose an application specific architecture for motion estimation using variable block matching scheme. It is based on recent advances in rate allocation theory, developed for computing rate-distortion optimized movement compensation. The optimum motion vector and the best quadtree decomposition are determined in a closed loop optimization procedure. Only the quadtree and the motion vector, which are considered to provide the absolute minimum update information, are coded and transmitted. The proposed tree architecture supports pipelined operations. The architecture is suitable for VLSI implementation, owing to modular properties. The Processing Elements (PEs) also support pipelining. An Application Specific circuit prototype has been designed for 4 /spl times/ 4 image blocks. The proposed architecture is scalable and can be easily be adopted for large image blocks.<<ETX>>
Experimental evaluation of Opportunistic Spectrum Access in distributed cognitive radio networks

is foreseen as the future of wireless communications. However, today's cognitive radio technologies lag far behind the OSA goals and do not allow for the applicability of exiting theoretical distributed OSA techniques. In this paper, we experimentally demonstrate the ability of realizing OSA despite the practical limitations of existing transceiver technologies. We use the general purpose Wireless open-Access Research Platform (WARP) to instrument the implementation of fundamental OSA functionalities. Then we implement a suite of OSA schemes using this implementation framework. Our experiments show that suboptimal but practical OSA approaches such as random spectrum sensing and non-greedy access achieve superior performance given cognitive radios with limited capabilities compared to OSA approaches that are optimized for fully-capable cognitive radio networks (e.g., with wide-band sensing capability and adopt winner-takes-all access relying on network-wide coordination mechanisms).
Low-power and high-speed architecture for EBCOT block in JPEG2000 system

In this paper we propose a novel low power and high-speed architecture for the context formation sub block in tier-1 block of JPEG2000 system. The proposed architecture is inspired from the statistical analysis results on 20 images with 512*512 bits each. The behavior of the proposed architecture is compared to the speedy architecture proposed. For code block size of 64*64 bits, the timing and power consumption analysis show that the proposed architecture can reduce the power consumption by approximately 21% and increase the processing speed by approximately 46% with respect to the reference architecture.
Design of a power-efficient interleaved CIC architecture for software defined radio receivers

This paper presents a novel, power-efficient architecture for decimation filter which is a critical component in multistandard digital receivers. Cascade integrator comb (CIC) filter is used to reduce high data rate because of its straightforward structure composed of adders and delays. The proposed power reduction is obtained by designing the integrator section as a polyphase structure where each polyphase component operates at reduced frequency. The digital receiver must process the in-phase (I) and quadrature (Q) signals using two similar filters. This structure is modified to process both signals with interleaved techniques. Thus, just one structure is needed to perform this operation over the two signals. Additionally, reduced frequency operation on the new structure allows us to use low power circuit design techniques such as voltage scaling to reduce the power consumption without affecting the performance of the whole structure. Power-intensive multiplications required for the polyphase filter components are replaced by add-and-shift multiplications. Different communication standards such as data networks (Mobitex and Ardis) and cellular networks (GSM, IS-95, and UMTS) are considered in the filter design. The architecture has been designed, and analyzed. Power estimation shows that the new architecture consumes only 15% of the power of the original structure (i.e., a savings of 85%).
Secure localization for wireless sensor networks using decentralized dynamic key generation

Security frameworks for wireless sensor network localization application can no longer be ignored. Wireless sensor network are being deployed in sensitive environment that require high levels of confidentiality, integrity and authenticity. Employing already existing security algorithms dedicated for wireless networks are infeasible for sensor network environment due to limited resources. In this context, a security framework tailored for wireless sensor network localization applications is proposed. The algorithm uses symmetric key encryption where the keys are generated in a decentralized fashion. These keys are computed on the fly, never transmitted and, changes autonomously with each transmission. Furthermore, the algorithm utilizes the bitwise XOR function for all its encryption needs which presents low overhead. Simulations show the robustness of the proposed algorithm in case of malicious node attack on the localization process and on key deduction and computation.
Automated system partitioning for synthesis of multi-chip modules

We present a system-level partitioning technique for the synthesis of multi-chip modules. It is based on the stochastic evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. We perform the partitioning at the behavioral level. The advantage of partitioning at the behavioral level is that both area and time constraints can be taken care of at the system level and also that scheduling/allocation can be applied concurrently to system-level partitioning. We formulate the partitioning problem as an extension to the network-bisectioning problem for which the stochastic evolution heuristic has been shown to provide better results than the simulated annealing technique. Preliminary scheduling/allocation and pin sharing are also performed simultaneously to estimate the area and pincount of each of the partitions. Efficient partitions are obtained for some of the digital signal processing applications in reasonable CPU time.<<ETX>>
A massively parallel RNS architecture

Parallelism on the algorithmic, architectural, and arithmetic levels is exploited in the design of a residue number system (RNS) based architecture. The architecture is based on modulo processors. Each modulo processor is implemented by a two-dimensional systolic array composed of very simple cells. The decoding state is implemented using a two-dimensional array. The decoding bottleneck is eliminated. The whole architecture is pipelined, which leads to a high throughput rate. High speed algorithms for modulo addition, modulo multiplication, and RNS decoding are presented.<<ETX>>
Cost-effective and low-power memory address bus encodings

This paper presents encoding methods that build on TO-encoding to achieve considerable reduction in memory address bus wires with small performance overhead, while reducing address bus switching activity. The known TO-encoding is combined with a variable cycle transmission technique that uses the TO's increment signal (INC) as an indicator of the number of cycles. Two of the proposed methods maintain the energy efficiency that is significantly reduced due to time-multiplexing. Benchmark experiments show that wire count of the instruction memory address bus can be reduced by around half at the price of 12.89% average performance penalty, while maintaining the low switching activity of the original TO-encoded bus.
A fault-tolerant bit-serial array structure for digital filters

The authors propose a bit-serial structure using systolic arrays in the implementation of a finite-impulse-response (FIR) algorithm for large sizes of data and higher-order filters. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are used on the cell level which increases the throughput of the proposed pipelined structure. Moreover, the proposed architecture has distributed error-control features. The necessity of such distributed fault-tolerance in DSP (digital signal processing) architectures is due to its susceptibility to permanent and intermittent errors caused by the high complexity of these circuit structures.<<ETX>>
Fault diagnosis and reconfiguration for reliable VLSI arrays

An online fault-tolerant strategy is proposed; it is composed of two phases: testing and locating faults, and reconfiguration. In the first phase, an online testing technique is used, which is a compromise between the commonly used techniques of time and space redundancy. It is capable of detecting permanent as well as transient faults. The reconfiguration phase is realized by using a global control. Switches are used to bypass the faulty processing element (PE). Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection circuitry as simple as possible.<<ETX>>
Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture

As technology dives deeper into the submicron, the complexities of systems-on-chip (SoC) increase due to the integration of a large number IP cores on the same silicon die. The network-on-chip paradigm has been widely accepted as a promising solution to the increasing complexity of on-chip communication requirements, with the quality of service network-on-chip (QNoC) being an effective solution when dealing with networks that have varying bounds on latency and throughput for different applications. In this paper, we present a router architecture to provide QoS support based on a simple extension to the router architecture PMCNOC and based on the definition of service classes. Our experiments show that the proposed architecture can meet the quality of service (QoS) requirements of the different service classes while maintaining hardware simplicity.
A low-power multiplication algorithm for signal processing in wireless sensor networks

Multiplication is at the core of many data processing tasks and saving power at the multiplication level can significantly impact the lifetime of a wireless sensor network. This paper introduces a novel light-weight low-power multiplication algorithm which is tailored for sensor nodes featuring low-end microcontrollers. These microcontrollers might have no hardware multiplier, or feature a fixed-point hardware multiplier which incurs significant energy overhead when enabled. The proposed algorithm aims to reduce the number of add operations during multiplication by rounding any sequence of 1's in the fractional part. The applied rounding decreases the number of instruction cycles, and reduces the memory storage without increasing the code complexity or sacrificing accuracy. Simulation results show that the proposed algorithm achieves up to 17% power saving and 16% increase in speed, with only 1% accuracy loss compared to Horner's algorithm. The effectiveness of the algorithm was demonstrated by implementing a finite impulse response (FIR) using the proposed method. The new multiplication method has been validated experimentally using the eZ430-RF2500 wireless sensor board.
A low power VLSI design paradigm for iterative decoders

In this paper we present low power maximum a posteriori (MAP) decoder architectures using dual supply voltages. The architecture leverages an application specific integrated circuits (ASIC) structure, where the architecture components that require a higher performance are powered from a high supply voltages V/sub ddH/, and the less demanding components are powered from a low supply voltage V/sub ddL/. Salient features of this architecture include: (a) high level of parallelism, (b) reduced power consumption without affecting the architecture performance, and (c) a tradeoff between the decoding time delay and the number of state metric banks, branch metric banks, and state metric update kernels respectively. The power consumption reduction of the dual-supply voltage over the single-supply voltage has been estimated and the memory access frequencies as well. The proposed architecture achieves approximate 35-40% power reduction from the single-supply architecture.
On minimizing hierarchical mesh coding overhead: (HASM) hierarchical adaptive structured mesh approach

This paper presents an efficient mesh coding technique suitable for MPEG-4 video applications. The proposed technique significantly reduces the number of bits that are used to describe the mesh topology. It uses an adaptive structured mesh from coarse to fine, which can be coded as a count of splitting instead of nodes' locations. In the case of the quadtree, less than one bit per node can be achieved. This reduction induces an improvement of either the image quality or the global bit rate.
Secure End-to-End key establishment protocol for resource-constrained healthcare sensors in the context of IoT

Internet of Things (IoT) is an ubiquitous concept where physical objects are connected over the internet and are provided with unique identifiers to enable their self-identification to other devices and the ability to transmit data over the network. Sensor nodes along with their heterogeneous nature are the main part of the IoT and may act as internet hosts or clients. Communication security and end-users privacy protection is a major concern in the development of IoT especially if these IP-enabled sensor nodes have limited resources. Secret key distribution for heterogeneous sensors becomes challenging due to the inconsistencies in their cryptographic primitives and computational resources as in Healthcare applications. This paper introduces a new End-to-End key establishment protocol that is lightweight for resource-constrained sensors and secure through strong encryption and authentication. By using this protocol, resource-constrained nodes can also benefit from the same security functionalities that are typical of unconstrained domains, without however having to execute computationally intensive operations. The protocol is based on cooperation by offloading the heavy cryptographic operations of constrained nodes to the neighboring trusted nodes or devices. Security analysis and performance evaluation results show that the proposed protocol is secure and is sufficiently energy efficient.
A comparative analysis for low power motion estimation VLSI architectures

The power consumption is very critical for portable video applications. The largest portion of power is consumed in the motion estimation module, as it requires a huge amount of computations. This paper compares different full-search motion estimation architectures targeted for low power consumption. Each of the architectures is analyzed, and then compared to the others. An architectural enhancement to further reduce the power consumption is proposed. Our approach is based on further elimination of useless computations without scarifying throughput or optimality. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancement.
Image segmentation on a 2D array by a directed split and merge procedure

A 2D array implementation of image segmentation by a directed split and merge procedure is proposed. Parallelism is realized on two levels: one within the split and merge operations, where more than one merge (or split) may proceed concurrently, and the second between the split and merge operations, where several splits may be performed in parallel with merges. Both the split and merge operations are based on nearest neighbor communications between the processing elements (PEs), and facilitating low communication costs. The basic arithmetic operations required to perform split and merge are comparison and addition, allowing a simple structure of the PE as well as a hardwired control. A local of 512 bytes is sufficient to hold the interim data associated with each PE. A prototype PE has been constructed using 3 mu m double-metal CMOS technology. Scaling up to 0.8 mu m, it is possible to incorporate 32 PEs on a 5 cm/sup 2/ chip. With sufficiently large PE window sizes, image segmentation can be achieved in linear time.
Green arithmetic logic unit

With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. The power dissipation has become an obsessive concern in the design and implementation of VLSI circuits with the development of the technology. In this paper, conventional low-power design approaches are discussed, and a new design based on Chain structure is presented. It provides a green solution and an alternative way to solve the problems of power supply distribution, interconnection and interfacing in VLSI circuits and a comparison experiment was performed over two circuit layouts of 16bit ALIT implementations and using standard CMOS that saves more than 30% of power consumption, and 0.423 mg of CO2 emission.
An efficient successive elimination algorithm for block-matching motion estimation

processors are in high demand for the emerging wireless video applications. Video compression processors include VLSI implementation of a motion estimation algorithm. Many motion estimation algorithms are found in the literature. Some of them are fast but cannot guarantee an optimal solution; they can be stuck in local optima. Such algorithms are fast, consumes less power when implemented in VLSI, but they can result in high levels of distortion that cannot be accepted in many applications. On the other hand the full search block matching algorithm (FSBM) is computationally intensive and a VLSI implementation of such an algorithm has high power consumption. This paper presents an exhaustive search algorithm for block matching motion estimation. The proposed algorithm reduces the computational load with successive elimination of non-candidate blocks in the search window. Our proposed algorithm assigns each pixel to a category depending on its value. The number of categories is predetermined. The algorithm consists of number of stages, the first of which has the fewer categories, eliminating those search points that are the farthest from the match. The last stage is the FSBM but with fewer search points. This computational reduction leads to low-power VLSI implementation of the algorithm. Also, it leads to faster efficient motion estimation procedure. The correctness of this algorithm and its complexity are proved.
A reconfigurable 'ANN' architecture

Proposes a design of a digital artificial neural network (ANN). The architecture is based on a single-instruction multiple-data (SIMD) processing configuration. Communication is done through broadcasting and also by systolic methods. With the help of a microprogrammed control unit, the design is mainly capable of implementing the following three models: (1) Hamming, (2) Hopfield, and (3) Carpenter/Grossberg algorithms. The architecture was also designed to achieve parallelism, modularity, adaptability, flexibility, speed, low cost, smaller silicon area, and expandability.<<ETX>>
Correlation-based detection of TCM signals for cognitive radios

In this work, the inter-dependency of TCM signals is studied. Using this inter-dependency, correlation-based detectors are proposed for spectrum sensing of TCM signals in white Gaussian noise. In particular, a constant false alarm rate (CFAR) detector is presented and its performance is evaluated using simulations. We also describe an application of our detector for the classification of uncoded modulation systems vs. their TCM counterparts and present numerical results on their performance.
Design process management in a CAD framework

An attempt is made to highlight some important features or wish lists for a comprehensive CAD framework. A study of existing design systems that aid in the design of ASICs shows that although they tend to provide extensive support to cater to issues at the lower end of the design spectrum, for example, efficient place and route tools, good module generation environments, etc., they still lack tools that would aid the designer at the higher end of the design spectrum. It is seen that by incorporating methods and methodologies for efficient design representation, design process tracking, etc., existing design systems can become more powerful, effective, and useful.<<ETX>>
Efficient shield insertion for inductive noise reduction in nanometer technologies

With high clock frequencies, faster transistor rise/fall time, wider wires, and the use of Cu material interconnects, interconnect inductive noise is becoming an important design metric in digital circuits. An efficient technique to reduce the inductive noise of on-chip interconnects is to insert shields among signal wires. An efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The proposed algorithm determines the locations and number of shields needed to satisfy certain noise constraints. Experimental results show that the proposed approach minimizes the number of shields required to satisfy the noise constraints and uses less runtime than the best alternative reported approach.
On the hierarchical hypercube interconnection network

The paper explores the hierarchical hypercube (HHC) interconnection network, suitable for building massively parallel systems with thousands of processors. HHC is self-embedded, that is, an HHC can embed HHCs of lower dimensions. In addition, HHC is a communication-efficient architecture. Two algorithms for data communication in the HHC are presented. The first algorithm is for one-to-one transfer and the second is for one-to-all broadcasting. Both algorithms take O(log k), where, k is the total number of processors in the system. Moreover, the paper shows that the HHC VLSI layout has a relatively small area which is O((log log k).k/sup 2//log k).<<ETX>>