nils-herrmann/clean_scirepeval huggingface dataset:
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

Intra prediction with rate-distortion constrained mode decision is the most important technology in H.264/AVC intra frame coder, which is competitive with the latest image coding standard JPEG2000, in terms of both coding performance and computational complexity. The predictor generation engine for intra prediction and the transform engine for mode decision are critical because the operations require a lot of memory access and occupy 80% of the computation time of the entire intra compression process. A low cost general purpose processor cannot process these operations in real time. In this paper, we proposed two solutions for platform-based design of H.264/AVC intra frame coder. One solution is a software implementation targeted at low-end applications. Context-based decimation of unlikely candidates, subsampling of matching operations, bit-width truncation to reduce the computations, and interleaved full-search/partial-search strategy to stop the error propagation and to maintain the image quality, are proposed and combined as our fast algorithm. Experimental results show that our method can reduce 60% of the computation used for intra prediction and mode decision while keeping the peak signal-to-noise ratio degradation less than 0.3 dB. The other solution is a hardware accelerator targeted at high-end applications. After comprehensive analysis of instructions and exploration of parallelism, we proposed our system architecture with four-parallel intra prediction and mode decision to enhance the processing capability. Hadamard-based mode decision is modified as discrete cosine transform-based version to reduce 40% of memory access. Two-stage macroblock pipelining is also proposed to double the processing speed and hardware utilization. The other features of our design are reconfigurable predictor generator supporting all of the 13 intra prediction modes, parallel multitransform and inverse transform engine, and CAVLC bitstream engine. A prototype chip is fabricated with TSMC 0.25-/spl mu/m CMOS 1P5M technology. Simulation results show that our implementation can process 16 mega-pixels (4096/spl ) within 1 s, or namely 720/spl times/480 4:2:0 30 Hz video in real time, at the operating frequency of 54 MHz. The transistor count is 429 K, and the core size is only 1.855/spl times/1.885 mm/sup 2/.
VLSI architecture for discrete wavelet transform based on B-spline factorization

Based on B-spline factorization, a new category of architectures for the discrete wavelet transform (DWT) is proposed. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of a Pascal implementation. The latter is the only part requiring multipliers and can be implemented with type-I or type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could need fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with small area and low speed because only a few adders are on the critical path. Two cases of the JPEG2000 defaulted (9,7) filter and the (6,10) filter are given to demonstrate the efficiency of the proposed architectures.
Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile

Global motion estimation (GME) and compensation is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). However, there are no hardware architectures for GME since existing algorithms are not suitable for hardware implementation. In this paper, GME in MPEG-4 ASP is analyzed, and a hardware-oriented GME algorithm is proposed according to the analysis results, which is a combination of a feature points based algorithm and a novel iterative sprite point matching algorithm. The associated hardware architecture is also proposed. Simulation results show that the performance of the proposed algorithm is the same as that of MPEG-4 Verification Model. The implementation results show the proposed hardware architecture can achieve the requirements of MPEG-4 ASP@L3 with 66K gates and 31Kb internal memory at 100 MHz working frequency.
INVESTIGATION OF A VISUAL TELEPHONE PROTOTYPING ON PERSONAL COMPUTERS

A personal computer (PC) based platform for visual telephone prototyping is introduced in this paper. ITU-T H.324 standard is the basis of the whole system. Video compression algorithms are implemented to achieve satisfactory visual quality for bit-rate less than 28.8 Kbps. Window menu interactive environment and modem communication interface are developed. Simulation results reveal the potential of the PC based solution.
Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC

In motion estimation, fast algorithms usually lead to an irregular searching flow, and the power reduction on architecture level is constrained for poor data reuse (DR). In this paper, a parallel IME hardware for H.264/AVC is proposed to well combine the techniques on algorithm and architecture levels. The "2-D SAD Tree" is adopted to support intra- and inter-candidate DR for the content-adaptive parallel-VBS four step search algorithm. A ladder-shaped reference data arrangement is proposed to support DR in both horizontal and vertical directions, while an advanced searching flow is applied to reduce the latency cycles. After these two techniques, 77.6% power of search window SRAMs can be reduced. According to the implementation result, in ultra low power mode, only 1.424 mW is required for realtime encoding CIF 30 fps videos with 13.5 MHz operation frequency
A new block-matching criterion for motion estimation and its implementation

A novel and efficient block-matching motion estimation criterion called minimized maximum error (MiniMax) is considered. The proposed method can save hardware area about 15% with acceptable video performance. A chip which combines the MiniMax matching criterion and the one-dimensional full search algorithm is presented. The ASIC is motivated by the need of the intensive computational demand to perform motion estimation in real time. The proposed single chip can match the applications of H.261 and MPEG international standards. Chip cascading is allowed for larger searching range applications.
A self-adjusting weighted median filter for removing impulse noise in images

An intelligent self-adjusting weighted median filter for removing impulsive noise in images is presented. Three main techniques are developed to implement this self-adjusting weighted median filter: an intelligent classification to divide the image data into the "corrupted" pixels and the "uncorrupted" pixels, an efficient algorithm to find the median output of any weight set, and a realistic training procedure without the noise free image to obtain the proper weights. Our simulations on some test images demonstrate that the proposed filter has less smoothing effect and smaller mean square error (MSE) or mean absolute error (MAE) measurement than the standard median filter. At the same time, the quality of the filter output has been enhanced significantly. Finally, a demonstration chip of this weighted median filter for the 5/spl times/5 window size is also presented.
A hardware-oriented design for weighted median filters

In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design strategy, the proposed architecture can support not only weighted median filters but also rank order-based filters in high-speed applications.
A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques

Intensive pixel shading dominates the power dissipation of the graphics pipeline as the screen resolution grows. In this work, we propose a 130.3 mW 16-core mobile GPU with three pixel approximation techniques and a corresponding tile-based rasterization architecture. The proposed architecture can trade-off between power consumption and visual quality to provide power-aware capability, and is fabricated with TSMC 45 nm technology. The feasibility and effectiveness of these techniques are verified in this chip prototype. The implementation results show that, with satisfactory visual quality, 52.32% of the power consumption of the shader processors can be empirically reduced with an experimental Approximated Precision Shader architecture and a Screen-space Approximated Lighting technique. Furthermore, the Approximated Texturing technique can reduce 24.57% of L1 cache updates in our evaluation.
A block-based 2D-to-3D conversion system with bilateral filter

The three-dimensional (3D) displays provide a dramatic improvement of visual quality over the 2D displays. The conversion of existing 2D videos to 3D videos is necessary for multimedia application. This paper presents an automatic and robust system to convert 2D videos to 3D videos. The proposed 2D-to-3D conversion combines two major depth generation modules, the depth from motion and depth from geometrical perspective. A block-based algorithm is applied and cooperates with the bilateral filter to diminish block effect and generate comfortable depth map. After generating the depth map, the multi-view video is rendered to 3D display.
Algorithm analysis and architecture design for HDTV applications - a look at the H.264/AVC video compressor system

In this article, we suggest some techniques to design the H.264/AVC video coding system for HDTV applications. The design exploration is made according to software profiling. The design considerations of system scheduling and pipelining are discussed followed by the architecture optimization of the significant modules. The efficient H.264/AVC video coding system is achieved by combining these techniques
Concurrent error-detectable butterfly chip for real-time FFT processing through time redundancy

The chip design for a fast Fourier transform (FFT) butterfly module using a novel concurrent error detection (CED) technique is presented. It is a time-redundant realization based on the direct complex computation approach. By the use of symmetry and the exchanging design strategy, the recomputation step can be performed by interleaving the circuits for the real and imaginary parts in a complex function. It leads to a lower hardware overhead (about 7/(4n+8), where n is the word length), and the error detection capability is as robust as that of the duplicated module technique. The CED butterfly is designed in 1.2- mu m CMOS technology, using the structural silicon complier. The theoretical analysis and experimental results are presented. It is shown that the design is very attractive for real-time high-reliability DSP systems. Its regular structure make the proposed algorithm and architecture easy to implement in VLSI or WSI.
Bit-plane error recovery via cross subband for image transmission in JPEG2000

For multimedia transmission over noisy channels, the error robustness of JPEG2000 evidently outperforms that of JPEG. Since JPEG2000 is based on the discrete wavelet transform (DWT), traditional error concealment algorithms for still images in the discrete cosine transform (DCT) domain are not suitable for JPEG2000. In JPEG2000, decoding is processed bitplane by bitplane. Any data loss occurring in the bitstream will affect the consequent bitplanes and their wavelet coefficients. To solve this problem, the JPEG2000 VM7.2 program replaces the missing wavelet coefficients by zeros. However, the replacement may affect lots of significant nonzero coefficients such that some high frequency components are lost. In this paper, we present a novel error concealment algorithm for image transmission in the bitplane base. The proposed algorithm recovers the damaged bitplane data according to the cross subband and undamaged bitplane information. The recovered wavelet coefficients are similar with error-free data. The objective results show that the proposed algorithm has 3/spl sim/8dB improvement than those without the error resilient mechanism. From a subjective viewpoint, the proposed algorithm can achieve much smoother edges on the reconstructed image using our concealment algorithm.
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank

In this paper, an efficient hardware implementation of two-dimensional shape-adaptive discrete wavelet transform (2-D SA-DWT) with the JPEG2000 defaulted (9,7) filter bank is presented. Two techniques are used to minimize the critical path and the internal buffer size. One technique is the flipping structure which can shorten the critical path of the lifting scheme by flipping multiplier coefficients, rather than pipelining. The other technique is a shape-adaptive boundary handling strategy which can enhance lifting-based architectures to solve boundary extension problems of SA-DWT with little hardware overhead. A prototyping chip of this implementation will be fabricated with TSMC 0.25 /spl mu/m CMOS 1P5M process, and the estimated frequency and the core area are 50 MHz and 2.83 mm/sup 2/, respectively.
Predictive watershed for image sequences segmentation

Watershed transform is a key operator in video segmentation algorithms. In this paper, a new fast watershed algorithm named P-Watershed for image sequences segmentation is proposed. By utilizing the temporal coherence property of video signal, this algorithm updates watersheds instead of searching watersheds in whole image. The watershed process can be accelerated and the segmentation results are almost the same as those of conventional algorithms. Moreover, an intra-inter watershed scheme (IP-Watershed) is also proposed to further improve the results. Experimental results show this algorithm can save 50% computation without degrading the segmentation results.
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency.
Design and VLSI implementation of real-time weighted median filters

In this paper, a novel design method and VLSI implementation of weighted median filters is presented. The weight parameters are incremented to minimize the mean square error of the input signal and desired signal when the sub-set of the image data is applied. The suboptimal(optimal) weight set is achieved after 71 training cycles for 5*5 window size under the MSE criteria. A two-level adder tree architecture with pipelined latches is proposed to find the weighted median output with versatile definition of weight. It requires only K iterations to find output, where K means the resolution of the input signal samples. The task interleaved processing is also adopted to improve the throughput. The final chip layout with pipelined latches for 5*5 window size is also given in this paper. This high-speed VLSI implementation of weighted median filter will meet the real-time application requirements.
JPEG, MPEG-4, and H.264 codec IP development

The paper summarizes our design experiences of various image and video codec IPs. The design issues and methodology of custom video codecs are discussed. The design methodology can be summarized as four stages: system analysis; algorithm optimization; architecture exploration; code development. Based on these guidelines, several design cases are presented, including the proposed JPEG, MPEG-4, and H.264 architectures.
A multimedia video conference system: using region base hybrid coding

In this paper, a video coding algorithm suitable for video conference application, and an investigation of a video conference system over a LAN are presented. The proposed video coding algorithm is called the region base hybrid coding algorithm. This method can perform foreground and background segmentation. This is based on the characteristic of an unchanged background on most of the video conference applications. This property can reduce both data rate and computation load. The proposed algorithm is verified on a video conference system over a LAN, and it can work successfully.
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

Embedded block coding with optimized truncation (EBCOT) is the most important technology in the latest image-coding standard, JPEG 2000. The hardware design of the block-coding engine in EBCOT is critical because the operations are bit-level processing and occupy more than half of the computation time of the whole compression process. A general purpose processor (GPP) is, therefore, very inefficient to process these operations. We present detailed analysis and dedicated hardware architecture of the block-coding engine to execute the EBCOT algorithm efficiently. The context formation process in EBCOT is analyzed to get an insight into the characteristics of the operation. A column-based architecture and two speed-up methods, sample skipping (SS) and group-of-column skipping (GOCS), for the context generation are then proposed. As for arithmetic encoder design, the pipeline and look-ahead techniques are used to speed up the processing. It is shown that about 60% of the processing time is reduced compared with sample-based straightforward implementation. A test chip is designed and the simulation results show that it can process 4.6 million pixels image within 1 s, corresponding to 2400 /spl times/ 1800 image size, or CIF (352 /spl times/ 288) 4 : 2 : 0 video sequence with 30 frames per second at 50-MHz working frequency.
Vlsi Implementation Of The Motion Estimator With Two-dimensional Data-reuse

This paper describes the VLSI implementation with a two-dimensional (2-D) data-reuse architecture for a full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
MPEG-4 FGS encoder design for an interactive content-aware MPEG-4 video streaming SOC

In this paper, the computational complexity of MPEG-4 fine granularity scalability (FGS) coding is analyzed to explore an efficient FGS implementation for video streaming applications. With the proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to provide a cost-effective solution. It can be integrated into an existing MPEG-4 coding system to form an interactive video streaming system. By the proposed FGS coder with reordered coding flow, the streaming server can adaptively decide quality-enhanced region by selective enhancement according to both object information from encoding side and user-defined region from receiver side. The proposed hardware core can support FGS profile level 5, frame size 720x576, 30Hz, for real-time streaming applications at 54 MHz.
Automatic video segmentation for MPEG-4 using predictive watershed

A fast watershed based video segmentation algorithm is proposed in this paper. Watershed based video segmentation algorithms are the mainstream because of high subjective quality; however, they are too computational intensive for real-time applications. Combining prior fast segmentation algorithm, which is based on change detection and background registration, and predictive watershed, a novel fast watershed algorithm for image sequences segmentation, this algorithm can give precise segmentation results and achieve real-time requirement. Simulation shows processing speed of 9.4 QCIF fps can be achieved on a PC with a Pentium-III 800 MHz processor.
Design and VLSI implementation of MPEG audio decoder

The paper presents a chip design for an MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced to half of the original number, and the storage demand reduced too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words of memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using a silicon compiler structure in the Genesil system, with 0.8-/spl mu/m CMOS technology.
Scalable video adaptation optimization using soft decision scheme

Video transmission over a heterogeneous network suffers a condition that it has required to satisfy many different constraints because of the variety limitations of client equipments and preferences of each user. In this condition, the video stream should have the flexibility feature. Scalable video coding is one of the solutions to serve this condition. In order to provide a better flexibility on scalability feature, more than one combination with video spatial size, temporal frame rate, and visual quality resolution are utilized. It is difficult to adapt the appropriate relation between the various combinations and user preference. In this paper, we propose an objectivity-derived algorithm with soft decision scheme for serving scalable video adaptation. This method can be used in existing equipments without much computation overhead. This useful and simple solution is not only a practical way in scalable video adaptation design, but also an efficient scheme of achieving subjective satisfaction.
A cost-effective design for MPEG2 audio decoder with embedded RISC core

MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. The first type is regular but computation-intensive such as filtering, matrixing, degrouping, and transformation operations. The second type is not regular but computation-intensive such as parsing bitstream, setting operation mode and controlling of all system operations. Based on standard cell design technique, the chip size is 6.4/spl times/6.4 mm/sup 2/, and the tested chip can run at maximum 43.5 MHz clock rate.