nils-herrmann/clean_scirepeval huggingface dataset:
Brain-Inspired Framework for Fusion of Multiple Depth Cues

2-D-to-3-D conversion is an important step for obtaining 3-D videos, as a variety of monocular depth cues have been explored to generate 3-D videos from 2-D videos. As in a human brain, a fusion of these monocular depth cues can regenerate 3-D data from 2-D data. By mimicking how our brains generate depth perception, we propose a reliability-based fusion of multiple depth cues for an automatic 2-D-to-3-D video conversion. A series of comparisons between the proposed framework and the previous methods is also presented. It shows that significant improvement is achieved in both subjective and objective experimental results. From the subjective viewpoint, the brain-inspired framework outperforms earlier conversion methods by preserving more reliable depth cues. Moreover, an enhancement of 0.70-3.14 dB and 0.0059-0.1517 in the perceptual quality of the videos is realized in terms of the objective-modified peak signal-to-noise ratio and disparity distortion model, respectively.
Rate-Optimal DSP Synthesis by Pipeline and Minimum Unfolding

DSP algorithms w i t h recursions o r feedback loops lead t o a n inheren t lower bound o n t h e achievable i terat ion period, called a n iteration period bound. A hardware DSP synthesis schedule is rate-optimal if t he i terat ion period equals t h e i terat ion period bound, and n o fa s t e r realization exis ts even w h e n infinite processor s are available. Sys t emat i c unfolding of t h e recursive data p o w graph is presented. T h e unfolding technique increases t h e number of tasks , unravels t he hidd e n concurrency in the recursive data f l ow graph, and reduces t h e i terat ion period. T h e compu ta t ion paths longer t h a n i terat ion period bound are pipelined and allocated o n dif ferent processors w i th in the i terat ion period bound. B y use of t h e opt imal unfolding transf o r m a t i o n , a recursive data f l ow graph i s equivalent t o a n a-unfolded data f l ow graph wh ich t h e n be scheduled rate-optimally. T h i s op t ima l unfolding fac tor i s determ i n a t e and smaller t h a n all previous works and theref o re reduces m o r e overhead. All experimental results show opt imal per formance of t he rate-optimal design
Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements

Mathematical morphology operations are applied in many real-time applications, such as video segmentation. For real-time requirement, efficient hardware implementation is necessary. This paper proposes a new architecture named Partial-Result-Reuse (PRR) architecture for mathematical morphological operations with flat structuring elements. Partial results generated during calculation process are kept and reused in this architecture to reduce hardware cost. With PRR concept and self-affinity property of structuring elements, the proposed architecture is more cost-effective and more general than existing morphology architectures. Moreover, it can be combined with systolic array to give consideration to both flexibility and hardware cost. We also propose a methodology to generate PRR architecture. With graphic method, the PRR architecture can be easily generated, and it can deal with structuring elements of any shape. The very large scale integration implementation of the PRR architecture shows that the area of processing element is small and can be fully piplelined without large overhead. The maximum frequency of the chip is 200 MHz in simulation, while processing speed of 550 morphological operations/s on a 720/spl times/480 frame can be achieved.
Relative Depth Layer Extraction for Monoscopic Video by Use of Multidimensional Filter

This paper presents a relative depth layer extraction system for monoscopic video, using multi-line filters and a layer selection algorithm. Main ideas are to extract multiple linear trajectory signals from videos and to determine their relative depths using the concept of motion parallax. The proposed superficial line model used for detecting slow moving objects provides sufficient taps within few frames to reduce frame buffer, while the closest-hit line model used for detecting fast motion objects provides few enough taps to prevent blurring. To increase the correctness of layer map, three-level layer map co-decision is used to compensate low texture region defect
Intelligent document capturing and blending system based on robust feature matching with an active camera

We propose an intelligent document capturing and blending system based on robust feature matching for efficient document management. The proposed system not only supports handwritten text and figure extraction, but also provides image blending mechanism to automatically merge the extracted handwritten texts and figures into electronic documents for the user. The proposed system addresses camera shake and luminance variation problems caused by active cameras. Besides, we adopt robust feature matching techniques to improve the system accuracy. Experimental results show that our system supports 95.65% detection rate and achieves 88.3% compression ratio reduction compared with the previous work. Besides, we also compare system performance considering Scale Invariant Feature Transform (SIFT)  and Speeded-Up Robust Features (SURF) . We derive 71.2% complexity reduction and 4.3% detection rate degradation with SURF feature matching.
Architecture design for deblocking filter in H.264/JVT/AVC

This paper presents an efficient VLSI architecture for the deblocking filter in H.264/JVT/AVC. We use an array of 8/spl times/4 8-bit shift registers with reconfigurable data path to support both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Two SRAM modules are carefully organized not only for the storage of current macroblock data and adjacent block data but also for the efficient access of pixels in different blocks. Simulation results show that under 0.25 /spl mu/m technology, the synthesized logic gate count is only 19.1 K (not including a 96/spl times/32 SRAM and a 64/spl times/32 SRAM) when the maximum frequency is 100 MHz. Our architecture design can easily support real-time deblocking of 720p (1280/spl times/720) 30 Hz video. It is valuable for platform-based design of H.264 codec.
1.4µW/channel 16-channel EEG/ECoG processor for smart brain sensor SoC

A 16-channel smart brain sensor SoC is proposed with the integrated digital EEG/ECoG processor (DEEP) to perform multi-dimension feature space analysis algorithms. The DEEP has three processing pipelines to filter out the artifacts, extract the multi-domain features, and interpret the inherent meanings according to the applications. Dedicated accelerators as well as a RISC are embedded to provide efficient computation and flexibility. Processing folding among channels saves the dominating leakage power. 1.4µW/channel power is achieved after the implementation in 90nm process.
Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC

The first SRAM-based multi-symbol arithmetic encoder was proposed in this paper. Since several SRAM problems arise in this highly data-dependent operation, four methods were introduced to make it feasible. Based on data-forwarding architecture, modular banks with throw-backward/catch-forward and read/write isolation greatly enhanced the throughput. Our SRAM-based approach was implemented with 29%-35% of area compared to register-based design. Moreover, different throughput required in various applications could be attained by changing the number of SRAM banks. The proposed SRAM-based multi-symbol arithmetic encoder achieved high throughput and low cost at the same time
Object-oriented video coding algorithm for very low bit-rate system

In this paper, a video coding method based on region segmentation is proposed. It is designed for very low bit-rate systems such as video-phone and video-conferencing. Instead of block-based coding, we adopt an object-oriented approach, which first calculates the motion vector of each pixel using a modified optical flow approach, then segments the motion field into circumscribed rectangular regions that can be efficiently coded. Simulation results of several typical image sequences reveal that the proposed algorithm is both effective and of high performance.
A 212 MPixels/s 4096  $\times$ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications

Multiview video coding (MVC) plays an important role in a 3-D video system. In addition, the resolution of HDTV is increasing to present more vivid perception for users. To realize real-time processing of dozens of TOPS, VLSI solution is necessary. However, ultra high computational complexity, a large amount of external memory bandwidth and on-chip SRAM size, and complex MVC prediction structures are three main design challenges of implementation of MVC hardware architecture. In this paper, an MVC single-chip encoder is proposed for H.264/AVC Multiview High Profile and High Profile for 3-D and quad full high definition (QFHD) TV applications, respectively. The 4096 × 2160 p multiview video encoder chip is implemented on a 11.46 mm2 die with 90 nm CMOS technology. An eight-stage macroblock pipelined architecture with proposed system scheduling and cache-based prediction core supports real-time processing from one-view 4096 × 2160 p to seven-view 720 p videos. The 212 Mpixels/s throughput is 3.4 to 7.7 times higher than previous work. The 407 Mpixels/W power efficiency is achieved, and 94% on-chip SRAM size and 79% external memory bandwidth are saved by the proposed techniques.
Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture

In this paper, an area-efficient JPEG 2000 codec is implemented on 6.1 mm2 with 0.18 mum CMOS technology dissipating 180 mW at 1.8 V and 60 MHz. It is capable of processing 78 MS/s for lossy coding at 1 bpp and 50 MS/s for lossless coding. Four techniques are used to implement this chip. The pre-compress ion rate-distortion optimization (pre-RDO) determines truncation points before coding to reduce computations for the EBC. The dataflow conversion and embedded compression reduces the tile memory bandwidth. The bit-plane parallel context formation enables scalable bit-plane coding. Experimental results show this chip has higher area efficiency than the previous works
Efficient Depth Image Based Rendering with Edge Dependent Depth Filter and Interpolation

An efficient depth image based rendering with edge dependent depth filter and interpolation is proposed. The proposed method can solve the hole-filling problem in DIBR system efficiently with high quality. The PSNR of the proposed method is better than the previous work by 6 dB and the subjective view shows the quality is better. In addition to that, the number of instruction cycles is 3.7 percent compared with the previous work
A simple and low-cost MPEG audio degrouping algorithm

Degrouping is the key component in MPEG Layer II audio decoding. It mainly contains the arithmetic operations of division and modulo, which require lots of hardware and computation time. In this paper, we propose a novel degrouping algorithm with a low complexity design concept. By using mode selection and iterative decomposition, only the addition and subtraction are needed. The elimination of the multiplier, divider and ROM table can therefore save a lot of chip area, but still keeps the high efficiency without loss of any accuracy.
Advances in Hardware Architectures for Image and Video Coding - A Survey

This paper provides a survey of state-of-the-art hardware architectures for image and video coding. Fundamental design issues are discussed with particular emphasis on efficient dedicated implementation. Hardware architectures for MPEG-4 video coding and JPEG 2000 still image coding are reviewed as design examples, and special approaches exploited to improve efficiency are identified. Further perspectives are also presented to address the challenges of hardware architecture design for advanced image and video coding in the future.
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

In this paper, an efficient very large scale integration (VLSI) architecture, called flipping structure, is proposed for the lifting-based discrete wavelet transform. It can provide a variety of hardware implementations to improve and possibly minimize the critical path as well as the memory requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. The precision issues are also analyzed. By case studies of the JPEG2000 default lossy (9,7) filter, an integer (9,7) filter, and the (6,10) filter, the efficiency of the proposed flipping structure is demonstrated.
VLSI architecture design of MPEG-4 shape coding

This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 video standard. The real-time constraint of MPEG-4 shape coding leads to a heavy computational bottleneck on today's computer architectures. To overcome this problem, design analysis and optimization of MPEG-4 shape coding are addressed. By utilizing the RISC-based model, computational behaviors of the MPEG-4 shape coding tool are carefully examined and analyzed. The characteristic of a large amount of bit-level data processing and data transfer of MPEG-4 shape coding motivates the optimization of bit-level data operations. Applying data-flow optimization and data reuse techniques, bit-level computation-efficient architectures, such as data-dispatch-based binary-shaped motion estimation, the delay-line model, and configurable context-based arithmetic coding, are designed to accelerate bit-level processing. These hardware blocks are integrated and scheduled in a very efficient data flow to achieve real-time performance for MPEG-4 CPL2 (core profile level 2) specification at 23.5 MHz clock rate. The system architecture is implemented using Verilog HDL and synthesized with a 0.35 /spl mu/m four-layer CMOS standard library.
A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

In this paper, a flexible CABAC encoder architecture for H.264/AVC encoder applications up to UHDTV (7680×4320) resolution is proposed. Stages of CABAC encoding are analyzed and a generalized CABAC architecture is designed. The parallel binarizer and context modeler (BCM) and multi-symbol binary arithmetic coder (MSBAC) is coupled together by a variable throughput buffer and packers (VTBAP) for throughput matching. Syntax elements (SEs) are analyzed thoroughly and various SEs processing engines are proposed to achieve parallelism for performance with high degree of flexibility for CABAC designers. Special attentions have been paid to the feeding of SEs into BCM that is not discussed in most other works. Without the bubble-free access control and the bubble-free feeding of SEs, the high throughput of BCM and MSBAC engine will not be possible to integrate with the rest of the encoder engine, otherwise external pre-processing has to be applied for SEs feeding. Flexibilities of architecture and level of parallelism are incorporated into a CABAC auto generating scheme that can produce the CABAC configurations according to user requirements. Towards a 0.13 μm CMOS technology, the highest performance design generated by the automatic generation scheme can encode 4.86 bins per cycle on the average, and it provides a throughput of 1234 Mbin/s. The proposed CABAC encoder architecture has been integrated into a H.264/AVC encoder of a multimedia SoC successfully.
Video de-interlacing by adaptive 4-field global/local motion compensated approach

A de-interlacing algorithm using adaptive 4-field global/local motion compensated approach is presented. It consists of block-based directional edge interpolation, same-parity 4-field motion detection, global/local motion estimation and compensation. The edges are sharper when the directional edge interpolation is adopted. The same parity 4-field motion detection and the 4-field local motion estimation detect the static areas and fast motion by four reference fields, and the global motion estimation detects the camera panning and zooming motions. The global and local motion compensation recover the interlaced videos to the progressive ones. Experimental results show that the peak signal-to-noise ratio of our proposed algorithm is 2/spl sim/3 dB higher than that of previous studies and attain the best quality of subjective view.
Low-delay and error-robust wireless video transmission for video communications

Video communications over wireless networks often suffer from various errors. A novel video transmission architecture is proposed to meet the low-delay and error-robust requirement of wireless video communications. This architecture uses forward error correction coding and automatic repeat request (ARQ) protocol to provide efficient bandwidth access from wireless link. In order to reduce ARQ delay, a video proxy server is implemented at the base station. This video proxy not only reduces the ARQ response time, but also provides error-tracking functionality. The complexity of this video proxy server is analyzed. Experiment shows that about 8.9% of the total macroblocks need to be transcoded under a random-error condition of 10/sup -3/ error probability. Because H.263 is the most popular video coding standard for video communication, we use it as an experiment platform. A data-partition scheme is also used to enhance error-resilience performance. This architecture is also suitable for various motion-compensation-based standards like H.261, H.263 series, MPEG-1, MPEG-2, MPEG-4, and H.264. For "Foreman" sequence under a random-error condition of 10/sup -3/ error probability, luminance peak signal-to-noise ratio decreases only 0.35 dB, on average.
Analysis and design of on-sensor ECG processors for realtime detection of VF, VT, and PVC

Cardiovascular disease remains the main cause of death, and great efforts are spent on the design of ECG body sensors these years. Essential components such as analog frontend and wireless transceivers have been integrated on a compact IC with micro-Watt power consumption. To provide timely warning against the fatal vascular signs, based on the Chaotic Phase Space Differential (CPSD) algorithm, on-sensor processors are implemented to detect the abnormal ECG for VF, VT and PVC. The on-sensor processing reduces 98.0% power of wireless data transmission for raw ECG signals. The application specific processor is designed to accelerate CPSD algorithm with 1.7μW power while the OpenRISC is integrated to provide the system flexibility. The architecture is realized on the FPGA platform to physically demonstrate the detection of the abnormal ECG signals in a real time.
Acquire user's distance by face detection

In this paper, we propose an algorithm using only two commodity webcams without calibration to detect distance between user and display by face detection. According to the experimental result, the correlation coefficient of distance and the reciprocal of disparity is up to 0.9984. Our proposed algorithm can provide user's depth information with high accuracy from calibration free stereo capture image pair for the application, such as interactive 3DTV or user-aware auto-stereoscopic display.
A 100 MHz 1920×1080 HD-Photo 20 frames/sec JPEG XR encoder design

A JPEG XR chip for HD-Photo is implemented with 25 mm2 area in TSMC 0.18 um CMOS 1P6M technology at 100 MHz. According to the simulation results, the 4:4:4 1920x1080 HD-Photo 20 frames/sec can be encoded smoothly.
A branch selection multi-symbol high throughput CABAC decoder architecture for H.264/AVC

Context-based adaptive binary arithmetic coding (CABAC) is a crucial part in H.264/AVC which provides a great compression gain. However, the throughput of CABAC decoder is limited due to the data dependency of decoding algorithm. This paper presents a branch selection hardware architecture which employs the two-symbol parallel decoder by providing all possible choices and then selecting the true one. The proposed CABAC decoder hardware architecture can decode 1.95∼1.98 bins per cycle. It is implemented by UMC 90nm technology with 82k gate counts at 222 MHz. The maximum throughput is 410 Mbins/sec which is sufficient for decoding video sequence at Level 5.0.
A cost effective reconfigurable memory for multimedia multithreading streaming architecture

Data flow plays an important factor when design a multimedia multithreading streaming system. In this paper, a reconfigurable memory architecture is proposed to smooth the stream data flow to decrease maximum stream data bandwidth from the external memory. The reconfigurable memory not only can configure as data cache but also can configure as tightly couple memory depending on the application. In addition, heterogenous threads level configurability can adjust the optima on chip thread number in different pipeline stage. Experiment shows the proposed architecture can reduce at least 27% external bandwidth and increase at least 25% throughput in a graphic streaming example.
Computation reduction technique for lossy JPEG2000 encoding through EBCOT Tier-2 feedback processing

A novel method to reduce computation of JPEG2000 encoding is proposed. The main concept is that most of the computation in the entropy coder (EBCOT Tier-1) of JPEG2000 is redundancy especially at lower bit-rates, and the proposed method can greatly reduce this redundancy through the feedback of EBCOT Tier-2 processing. By the information generated from Tier-2, the computing time of EBCOT Tier-1 at irreversible wavelet transform mode (9-7 filter) can be reduced to about 40% and 20% at general and high compression rates, respectively. And there is even more reduction at reversible wavelet transform mode (5-3 filter).
Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis

A new machine learning SoC (MLSoC) for multimedia content analysis is implemented with 16-mm2 area in 90-nm CMOS technology. Different from traditional VLSI architectures, it focuses on the coacceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements are integrated to achieve tera-scale performance. In the dual stream processor (DSP) architecture, the data are transferred between processors and the high-bandwidth dual memory (HBDM) through the local media bus without consuming the AMBA AHB bandwidth. The image stream processor (ISP) of the MLSoC can handle common window-based operations for image processing, and the feature stream processor (FSP) can deal with machine learning algorithms with different dimensions. The power efficiency of the proposed MLSoC is 1.7 TOPS/W, and the area efficiency is 81.3 GOPS/mm 2.
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC

In an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR). In this paper, a hardware-oriented fast algorithm is proposed with the intra-/inter-candidate DR considerations. In addition, based on the systolic array and 2-D adder tree architecture, a ladder-shaped search window data arrangement and an advanced searching flow are proposed to efficiently support inter-candidate DR and reduce latency cycles. According to the implementation results, 97% computational complexity is saved by the proposed fast algorithm. In addition, 77.6% memory bandwidth is further saved with the proposed DR techniques at architecture level. In the ultra-low-power mode, the power consumption is 2.13 mW for real-time encoding CIF 30-fps videos at 13.5-MHz operating frequency