nils-herrmann/clean_scirepeval huggingface dataset:
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders
Industry forum: IoT for real life part I

If everybody tells the same story, then it's time to start new adventures! For a short time let the ARMy of boring “me-too” behind and discover a new realm of possibilities in the melting pot of digital and analog circuits. Experience a new form of “Inherent Artificial Intelligence”, self-powered contactless “Smart-by-Nature” sensing circuits (beyond RFID & NFC), as well as new ideas for MEMS and Charge Coupled Devices (CCD). How about a kind of “Alma-Mater-on-Chip”, a vast cluster of “teachers” and “students”, realized with “EPIC's nCP nanoCloudProcessors”, to outsmart even Quantum computers? Wolf Richter talks & demonstrates (live on stage) what's possible today, to give you “Epic” ideas for tomorrow!
A band-matching approach for motion estimation

A new algorithm to compute motion vectors has been developed based on the block-matching approach which uses bands are instead of blocks. The new band-matching algorithm (BDMA) offers better performance than both fixed and variable size block-matching algorithms because it uses fewer vectors and processes parts of the image instead of the whole image. The BDMA then uses edge and texture information to search for a match. Matching results produce a specific vector for the estimated motion. The new algorithm has been evaluated using several standard video images.
High speed single-ended pseudo differential current sense amplifier for SRAM cell

With reducing feature sizes, SRAM stability has become a major concern for future technologies. This critical issue can be solved by using highly stable separate bit-line read SRAM cell, but access time improvement becomes critical, since differential sense amplifier cannot be used for single bit-line read operation. In this paper, a novel pseudo differential single ended current mode sense amplifier is proposed. We demonstrate that this design can deliver a performance similar to that of conventional current mode differential amplifier without using dual bit-line for read operation. The overall read operation delay of the proposed single-ended design is almost 60% less than conventional single-ended design in 90 nm CMOS technology. The proposed design consumes 51.6% less energy than conventional design counterpart.
Yield modeling for fault tolerant WSI arrays

An approach to modeling the yield of WSI architectures in view of spatial distribution of defects on a wafer and varying clustering parameter alpha is proposed. The results are mapped onto two-dimensional array architectures and the basis for determining the estimate for required redundancy of processing cells on various regions of the wafer has been proposed. The authors first elucidate the definitions of chip yield and wafer yield in VLSI and WSI to clarify the understanding of WSI wafer yield. The approach to modeling defect spatial distribution is discussed. A universal mesh interconnected processing cell array built on a wafer is analyzed using the model developed. The preliminary analysis is on a unit section and associated probability of a failure/failure-free composite section. This has been generalized in terms of spatial aspects of fault distribution to serve as a basis for the estimation of redundant cells for different sections of the array.<<ETX>>
A non-zero clock skew scheduling algorithm for high speed clock distribution network

In this paper, we present a novel algorithm for scheduling clock skews in a synchronous digital circuits to optimize performance. The new algorithm Is based on inclusively matching allowable clock skews intervals of all local data path in the circuit in order to determine the proper global skew ranges. This algorithm will lead to minimizing the clock period as wed as obtaining a list of scheduled skews to be inserted in the clock network. These scheduled skews are then used to obtain a delay model for all branches of the clock distribution network tree, The delay values ensure the proper synchronization of data and eliminate any potential race condition in the circuit. The new algorithm has been tested and found to be a good approach toward reducing the clock period compared with zero intentional skew clocking.
An efficient minimum area spacing algorithm for noise reduction

With high clock frequencies, faster transistor rise/fall time, long signal wires, the use of wider wires and Cu material interconnects, the decreased spacing between adjacent wires, and the increased aspect ratio, the crosstalk noise is becoming an important design metric in digital circuits. For a risk-free layout solution of a chip, capacitive and inductive noises should be considered at various routing process stages. A formulation and efficient solution for the min-area spacing problem to satisfy maximum reliability in multiple coupled nets is provided. The noise model used can handle different wire widths, different spacing among wires, and different wire lengths. Experimental results show that the proposed framework redistributes the spacing among neighboring wires to achieve maximum reliability through the minimization of the maximum crosstalk noise in nets.
A VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression

We present an adaptive neural network processor for image compression based on a modified frequency-sensitive self-organization algorithm. In this algorithm updating the code vector has a complexity of O(1) and O(N) for best case and worst case situations respectively. Experiments have shown that the worst case situation occurs only at the initial stage of the learning process, and performance improves as the learning continues. The utilization of learning neurons is considerably increased compared to other algorithms. This algorithm not only achieves a near-optimal result, comparable with Linde-Buzo-Gray (LBG), but also retains simplicity for hardware implementation. A mixed-signal architecture is proposed for this algorithm. It consists of analog circuitry which is responsible for neural network computation and digital circuitry for frequency updating and loser selection.
A scalable shared buffer ATM switch architecture

A scalable shared buffer switch architecture for asynchronous transfer mode (ATM) with O(/spl radic/N) complexity for memory bandwidth requirement and maximum crosspoint switch size, and O(N) scalability for buffer memory size is proposed. Access time to buffer memories has been reduced by virtue of parallel access. The switch architecture features multiple buffer memories between the input and output side crosspoint switches. The new switch architecture is better than the standard shared buffer approach as it eliminates the use of input and output time division multiplexing and makes it possible to meet buffer memory access time limitations for larger switches. At the same time, the proposed switch architecture is able to keep the crosspoint switches from growing as O(N/sup 2/) as is the case in the pure multibuffer architecture. The proposed architecture offers a good compromise between the simple shared buffer and shared multibuffer architectures Architectural and implementation details are discussed and a quantitative comparison between the buffer architectures given. Implementation of an 8/spl times/8 switch in 1.0 /spl mu/m CMOS technology is described.
A scalable systolic array architecture for 2D discrete wavelet transforms

A systematic synthesis approach has been developed for scalable systolic array architecture for a 2D discrete wavelet transform (DWT) based on the data dependence analysis and linear index space transformation. The proposed architecture has regular topology, local routing, simple controller and high throughput rate. It can be easily extended to different parameters of various levels, macroblocks and filters. The derived architecture has been prototyped using Cadence Edge Framework.
On sub-Nyquist spectrum sensing for wideband cognitve radios

This paper presents a survey of the recently proposed sub-Nyquist spectrum sensing methods for wideband cognitive radio systems. Sub-Nyquist sensing aims at acquiring wideband signals at low rates offering a feasible realization of wideband cognitive radios using the off the shelf components. In this paper, the relevant scientific literature has been classified to three approaches. The first approach assumes a discrete multitoned signal model while the second assumes a continuous multiband signal model. The third approach adopts cooperation among spatially distributed cognitive radio devices. Finally, the pros and cons of each of these approaches are presented and discussed.
Testbed implementation for Autonomic Network Performance Management of wireless mesh networks

In previous work, we proposed an Autonomic Network Performance Management (ANPM) framework that follows a control-theoretic approach. We built and verified the framework using network simulations but there were many questions needed to be accurately answered concerning the feasibility of such framework in real networks. In this paper, we are going from simulation to testbed implementation to accurately answer such key questions. We use over-the-counter platforms and open source software to build the test-bed that supports 700 MHz, 2.4 GHz, and 5 GHz frequency bands. Multithreaded code is written to verify the ability of the ANPM framework to react, in a timely manner, to the increase in network traffic load.
A low power high performance distributed DCT architecture

A new distributed arithmetic architecture, NEDA, is presented in this paper. NEDA is a low power optimized architecture based on the distributed arithmetic paradigm. In addition to low power performance, NEDA offers high speed and reduced area. In NEDA, inner product computational module has been proved, mathematically, to require only additions. Moreover, minimum number of additions is used by exploiting the redundancy in the adder array. Such properties have made a NEDA unit a basic computational module for high performance DSP architectures. A case study of 8/spl times/8 DCT NEDA-based architecture is analyzed. Savings exceeding 88% are achieved for the DCT implementation.
Fast and flexible architectures for RNS arithmetic decoding

An implementation of a fast and flexible residue decoder for residue-number-system (RNS)-based architectures is proposed. The decoder is based on the Chinese remainder theorem. It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders, while the other is based on utilizing modulo adders. The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of theta (log N), where N is the number of moduli.
Building and Evaluating COTS Based Optical Interlinks for Nanosatellites

Nanosatellites in low earth orbit are becoming more popular due their proven performance using accessible COTS components. Optical interlinks for such satellites have been suggested before as an alternative to RF links. In this paper we present the steps involved in selecting suitable COTS components for such links and evaluating them as well. Finally we compare the achievable performance of these links to what current low power RF technologies offer.
From algorithms to parallel architectures: a formal approach

The authors introduce a formal approach for synthesis of parallel architectures. Four different forms are used to express the given algorithms: simultaneous recursion, recursion with respect to different variables, fixed nesting and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multiplication algorithm is used to obtain four different optimal architectures. The different architectures of this example are compared in terms of area, time, broadcasting and required hardware. The approach is providing two main features: completeness and correctness.<<ETX>>
Acoustic target localization in sensor networks with FUZZYART

A low cost target localization algorithm is developed for wireless sensor networks based on acoustic signals. When an object is detected, each sensor will start delay calculations to estimate the TDOA (time difference of arrival) of the target in hand with respect to each sensor. Each sensor will exchange the delay information between each other. Then the sensors will reach a general consensus of where the target is located in the sensor field using triangulation, assuming each sensor is aware of its own location and that the data transmission is synchronized. Furthermore a FUZZYART neural network model is introduced at the cluster head to detect errors and assign probabilistic weight to each estimate to cope with spatial correlation and consensus vote. The algorithm proposed performs triangulation with low overhead in computations. Moreover simulation results show that the error in target localization averages around 23 cm and the maximum is 35 cm which is acceptable in sensor network environment.
A formal design methodology for parallel architectures

The authors introduce a formal approach for synthesis of array architectures. The methodology provides two main features: completeness and correctness. Completeness means the ability to use the approach for any general algorithm. Correctness is achieved by using a set of transformations that are proved to be correct. Four different forms are used to express the input algorithm: simultaneous recursion, recursion with respect to different variables, fixed nesting, and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multiplication algorithm is used to obtain four different optimal architectures. The different architectures of this example are compared in terms of area, time, broadcasting, and required hardware.<<ETX>>
Keynote speech 1: Wireless sensors networks: Challenges and opportunities

Computers, communication, and sensing technologies are converging to change the way we live, interact, and conduct business. Wireless sensor networks reflect such convergence. These networks are based on collaborative efforts of a large number of sensor nodes. They should be low-cost, low-power, and multifunction. These nodes have the capabilities of sensing, data processing, and communicating. Sensor networks have a wide range of applications, from monitoring sensors in industrial facilities to control and management of energy applications to military and security fields. Because of the special features of these networks, new network technologies are needed for cost effective, low power, and reliable communication. These network protocols and architectures should take into consideration the special features of sensor networks such as: the large number of nodes, their failure rate, limited power, high density, etc. In this talk the impact of wireless sensor networks will be addressed, several of the design and communication issues will be discussed, and a case study of a current project of using such networks in drilling and management off-shore oil and natural gas in the gulf region will be given.
A new ATM switch architecture: scalable shared buffer

In this paper, a scalable shared buffer switch architecture for asynchronous transfer mode (ATM) is proposed. It has O(/spl radic/N) complexity for the memory bandwidth requirement and the maximum crosspoint switch size, together with O(N) scalability for buffer memory size. In this architecture, multiple buffer memories are used between the input and output side crosspoint switches. By eliminating the use of input and output time division multiplexing, the new switch architecture is an improvement over the standard shared buffer approach. The proposed switch architecture is able to keep the crosspoint switches from growing as O(N/sup 2/) as is the case in the pure multibuffer architecture. It offers a good compromise between the standard shared buffer and shared multibuffer architectures. Architectural and implementation details are discussed and a quantitative comparison between the buffer architectures is given. Implementation of an 8/spl times/8 switch in 1.0 /spl mu/m CMOS technology is described.
An ultra-low power current reused CMOS low noise amplifier for x-band space application

This paper presents fully integrated ultra-low power CMOS low noise amplifier (LNA) for x-band space application by employing current reused technique. It also operates in subthreshold region to reduce power consumption significantly. The state-of-art low noise amplifier targets 10.8 GHz for x-band frequency in advanced conventional 65-nm CMOS technologies. It achieves power gain (S21) of 10 dB, noise figure (NF) of 2.9 dB, input-referred third-order intercept point (IIP3) of -9 dBm, while consumes only 125 uA and operates with supply voltage of 0.6 V which results in total power consumption of less than 80 uW.
The nature of defect patterns on integrated-circuit wafer maps

The history of IC-yield models dates from those based on the simple Poisson distribution to current models based on the families of compound and generalized Poisson distributions. The latter are more complex because the IC chips have grown larger in area and circuit density, thereby unveiling the clustering (aggregation) properties of defects on wafers. These clustering properties are reflected by the parameters of the distributions on which the existing yield models are based. The possibility of any statistical distribution providing an exact representation of some actual population is very small. It is important, though, that the parameters of alternative statistical distributions describing some actual population should have some physical meaning. This paper considers 3 distributions used to model empirical defect distributions in IC manufacturing. The applicability of these distributions depends strongly on the area of the chips fabricated on a wafer. The authors discuss the cases where a study of the parameters alone might not provide conclusive evidence about the spatial properties of defect patterns on IC-wafer maps. They propose some measures to explain defect clustering: variance/mean ratio, turning point, mean crowding, and patchiness. Due to the complementary nature of these measures, no measure, by itself, can provide sufficient information about defect patterns or complete details of the differences between several patterns. It is therefore instructive to analyze defect patterns by as many measures as feasible.
A novel clustering paradigm for key pre-distribution: Toward a better security in homogenous WSNs

Homogeneous wireless sensor networks (HWSNs) are a class of WSNs in which nodes have identical hardware configurations. A HWSN inherits the same constraints from WSNs such as limited processing capacity and resources. However, the unique characteristic of HWSNs gets more attention for recent security applications. The environment of these applications mandates lightweight security provisions, especially a key management protocol that endures security threats such as node capture attack. On the other hand, the limited computation and communication capabilities of sensor nodes make it hard to deal with such security threats. Thus, in this paper, we introduce a novel clustering paradigm to be used in a key pre-distribution key management scheme designed for HWSNs. Then, we develop a cluster-based key pre-distribution based on this paradigm. Our developed scheme improves the security dramatically by partitioning sensor nodes to the disjointed clusters and letting clusters to be inter-connected via randomly selected nodes as consular nodes from all the clusters to form a universal cluster. As opposed to the adopted schemes, we provide a comprehensive analysis for both sensor node connectivity, and resiliency against node capture attack, and also computational results are presented.
An algorithm transformation technique for multi-dimensional DSP systolic arrays

Algorithm such as FIR (finite-impulse-response) filtering, 1-D convolution, and DFT (discrete Fourier transform), which are traditionally mapped onto 1-D systolic network, can be formally transformed and mapped onto higher-dimensional systolic networks. With suitable implementation algorithms developed for these transformed digital signal processing (DSP) algorithms, the speed of computation can be significantly improved without increasing the order of area complexity. Results of transforming and implementing these DSP algorithms onto higher-dimensional systolic arrays are presented. The proposed technique leads to a significant improvement in computational time while keeping the area complexity constant.<<ETX>>