nils-herrmann/clean_scirepeval huggingface dataset:
Low-power parallel tree architecture for full search block-matching motion estimation

In this paper, a novel low-power parallel tree architecture is proposed for full search block-matching motion estimation. The parallel tree architecture exploits the spatial data correlations between parallel candidate block searches for data sharing, which effectively eliminates huge amount of data access bandwidth while consumes fewer hardware resources compared with array-based architectures. Combining with adaptive parallel partial distortion elimination algorithm, the required average clock cycle count for each macroblock search can be greatly reduced to below 50% to achieve low-power operation. Besides, this architecture can also eliminate redundant computation without pipeline latency and excess power consumption caused by register shifting and redundant memory accessing in array-based architectures. The proposed architecture is suitable for high-end real-time portable video encoding system, which desires high-quality video but low-power consumption.
One-dimensional full search motion estimation algorithm for video coding

A new hardware-oriented algorithm called the one-dimensional full search (1DFS) is presented for block-matching motion estimation in video compression. The simulation for this algorithm follows H.261 and MPEG international standards. In MPEG simulation, structures with 1-, 2- and 3-frame interpolation are compared. The performance of 1DFS is superior to that of other fast search algorithms. And it has more regular data flow, data reuse and less control overhead. It is an alternative for 2D full search block matching and achieves a good compromise between computational complexity and performance. With competent performance and reasonable computation complexity, the proposed method is more suitable for real-time hardware realization of a VLSI motion estimator for video applications.
A novel video signal processor with programmable data arrangement and efficient memory configuration

This paper describes a novel video signal processor (VSP) with a fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of a programmable data arrangement and an intelligent memory configuration. Techniques for reducing the interconnections and external memory accesses are also presented. A configuration of random-access on-chip memory modules solves the problems of chip I/O and memory bandwidth requirement. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.
Power-efficient FIR filter architecture design for wireless embedded system

This paper presents a novel approach for implementing power-efficient finite-impulse response (FIR) filters that requires less power consumption than traditional FIR filter implementation in wireless embedded systems. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, balanced-modular techniques with retiming and separated processing data-flow scheme with modified canonical signed digit (CSD) representation, experimental results show that the proposed scheme reduce 76% power consumption of the original direct-form structure with slight area overhead.
Line Buffer Wordlength Analysis for Line-Based 2-D DWT

The on-chip line buffer dominates the total area and power of line-based 2-D DWT. Therefore, the line buffer wordlength has to be carefully designed to maintain the quality level due to the dynamic range growing and the round-off errors. In this paper, a complete analysis methodology is proposed to derive the required wordlength of line buffer given the desired quality level of reconstructed image. The proposed methodology can guarantee to avoid overflow of coefficients, and the difference between predicted and experimental quality level is averagely 0.06 dB in terms of PSNR
A Multimedia Video Conference System: Using Region Base Hybrid Coding

Using Region Base Hybrid Coding Hsu-Tung Chen and Liang-Gee Chen DSP/IC Design Lab., National Taiwan Universify, Taipei, Taiwan, R. 0. C. Email : d81054@video.ee.ntu.edu.t~ A suitable algorithm for video conference system is described. We call it region base hybrid coding algorithm. This method can do foreground and background segmentation. This is based on characteristic of an unchanging background on most of the video conference applications. This property provides as to reduce data rate and computation load. This algorithm is verified implementing a video conference system over LAN.
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT

In this paper, a memory-efficient VLSI implementation for line-based 2D DWT, named the multiple-lifting scheme, is proposed. Memory bandwidth and memory size dominate the cost of 2D DWT and are highly related to the total power and area of 2D DWT VLSI implementation, respectively. The proposed multiple-lifting scheme can reduce not only the average memory bandwidth but about 50% area of the line buffer in the 2D DWT module. The corresponding data scan, M-scan, is proposed to achieve the multiple-lifting scheme and eliminate the data buffer as well.
One-pass computation-aware motion estimation with adaptive search strategy

A computation-aware motion estimation algorithm is proposed. Its goal is to find the best block matching results in a computation-limited and computation-variant environment. Our new features are one-pass flow and adaptive search strategies. The prior scheme allocates more computation to the macroblock with the highest distortion in the entire frame step by step. This implies that random access of macroblocks is inevitable, and the search pattern must be determined in advance. The random access flow requires a huge size of memory for all macroblocks to store the up-to-date minimum distortions, best motion vectors, and searching steps. In contrast, the one-pass flow can not only significantly reduce the memory size but also effectively use the context information of neighboring macroblocks to achieve faster convergence and better quality. Moreover, to improve video quality when computation resource is still sufficient, the search strategy is allowed to change adaptively from diamond search to three step search, and then to full search. Last but not least, traditional block matching speedup methods are combined to provide much better computation-distortion curves.
A globally static rate optimal scheduling for recursive DSP algorithms

A set of techniques for rate-optimal scheduling of recursive DSP algorithms is presented. The underlying microprocessor system is based on the RISC architecture. The retiming process evenly distributes the delays and optimizes the scheduling time of each iteration. The unfolding of recursive data flow graph exploits intraiteration and interiteration parallelism, and the schedule can be more compacted. It is shown that after evenly retiming and unfolding with the optimal unfolding factor, a fully-extended precedence graph is generated, which can be scheduled in rate-optimal by a simple contiguous scheduling. The optimal unfolding factor is equal to the delay counts of the critical loop.<<ETX>>
Accuracy improvement and cost reduction of 3-step search block matching algorithm for video coding

Proposes three modifications on the 3-step hierarchical search for video coding: the multiple-candidate search that improves the estimation accuracy, a method of subsampling that reduces computation and input data amount, and an overlapping strategy to improve the accuracy of a large-area search. Experimental results show that combining these techniques provides high-speed and high-precision motion estimators with reduced on-chip buffers and lower input bandwidth requirements.
Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem

It is impractical to apply a general spike sorting algorithm for every subject because of the individual characteristics of brain signal. Furthermore, extracting more neural activities for higher accuracy of spike sorting requires more input electrodes as well as large power consumption and chip area. Therefore, several practical constraints are considered in this work when implementing a programmable spike sorting hardware with large number of input channels. In this paper, we provide a 128-channel spike detection processor for spike sorting microsystem without compromise of the power efficiency. This chip consumes only 87.02uW and 9.7uW/mm2 of power density, fabricated with 90nm low-leakage CMOS process.
Mapping Scalable Video Coding decoder on multi-core stream processors

Scalable Video Coding (SVC) is an advanced video compression technique that can support temporal, spatial, and quality scalability to terminals with different network conditions. SVC adopts layered coding techniques to improve coding efficiency for spatial and quality scalability. Upsampling and inter-layer prediction are two important mechanisms to remove redundant information between different layers. However, upsampling occupying around 75% memory bandwidth of SVC decoder results in serious performance degradation, especially for applications with high resolutions. Moreover, inter-layer prediction with complex scheduling leads to difficulties when mapping the SVC decoder in parallel. In this paper, we propose a method to parallelize the SVC decoder on a multi-core stream processor platform in both efficiency and flexibility. We focus on mapping issues of spatial scalability supporting with various resolutions of decoded frames. The experiment result proves the proposed design for SVC decoder reduces 95% memory bandwidth of the upsampling module in JSVM, performed on a single general-purpose processor.
Building a pseudo object-oriented very low bit-rate video coding system from a modified optical flow motion estimation algorithm

A modified optical flow algorithm (MOFA) is proposed for the development of a very low bit-rate video coding system. Another edge preserving constraint and pyramid approach are suggested to generate an accurate motion field and reduce the possibility of being trapped in a local minimum. Post-processing schemes are also designed to eliminated the problems for special regions. Compared with other motion estimation algorithms, the proposed method gives a more exact estimation in terms of the PSNR and subjective view. The arbitrarily shaped transform of the motion field is then selected to further remove the spatial redundancy. According to some primary simulation results, most of the test sequences are compressed into 16 kbps or lower with excellent picture quality.
A digital signal processor with programmable correlator array architecture for third generation wireless communication system

A digital signal processor (DSP) with programmable correlator array architecture is presented for third generation wireless communication system. The programmable correlator array can be reconfigured. as a chip match filter, code group detector, scrambling code detector, and RAKE receiver with low power consideration. The architecture and instruction set of the proposed DSP are specially designed for several key operations of wireless communications, such as channel estimation for RAKE combining, Viterbi algorithm and finite-impulse response filtering. The proposed DSP outperforms other previously presented communication digital signal processors in terms of several crucial operations of wireless applications. A chip of the proposed DSP was implemented using hybrid design method where the timing critical components were full-custom designed and the other parts were cell-based designed under TSMC 0.35-/spl mu/m CMOS 1P4M technology. We believe that the proposed system architecture would be useful for upcoming 3G mobile terminal applications.
A very low bit rate video coding system using adaptive region-classified vector quantization

In this paper, a new video coding algorithm suitable for the very low bit rate video application is presented. It takes advantage of the prior knowledge of the image type to segment the image into different regions, then codes each region with different coding criterion and method according to the different importance. An adaptive region-classified vector quantization strategy is also exploited in this algorithm. With the segmentation of the frame and high correlation between frames, better codebooks of vector quantisation are constructed to improve the quality. According to the simulation results, acceptable quality at about 10 kbit/s can be obtained for the typical test sequences.
Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC

Context-based adaptive variable-length coding (CAVLC) is a new and important feature of the latest video coding standard, H.264/AVC. The direct VLSI implementation of CAVLC modified from the conventional run-length coding architecture will lead to low throughput and utilization. In this brief, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4 times 4 blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bitstream. Our dual-block-pipelined architecture doubles the throughput and utilization of CAVLC at high bit rates. Moreover, a zero skipping technique is adopted to reduce up to 90% of cycles at low bit rates. Last but not least, Exp-Golomb coding for other general symbols and bitstream encapsulation for the network abstraction layer are integrated with CAVLC as a complete H.264/AVC baseline profile entropy coder. Simulation shows that our design is capable of real-time processing for 1920 times 1088 30-fps videos with 23.6 K logic gates at 100 MHz
Compressive Sensing based Client-Cloud system for 3D depth reconstruction

We present a Compressive Sensing (CS) based Client-Cloud system describing the future Cloud Computing structure, which takes 3D depth reconstruction as an instance. First, a sparse representation for continuous depth data is exploited. Second, we propose a dynamic measurement generation method adapted to the variation of sparsity to reduce bandwidth requirements. Third, a feedback correction scheme is developed to detect the incorrectly reconstructed signals and perform supplementary reconstruction. According to the experimental results, the proposed system can reduce about 40% to 70% bandwidth requirements and lower about 50% error rate while reconstruction.
A hardware accelerator for video segmentation using programmable morphology PE array

Video segmentation is a key operation for MPEG-4 and MPEG-7. It is a computationally intensive task and cannot be afforded by general microprocessors. In this paper, we propose a hardware accelerator for video segmentation. Since most of the core operations of video segmentation algorithms can be mapped to morphological operations, the core of this accelerator is a programmable morphology PE array. With the programmable ability of each PE and the interconnection between them, this accelerator can achieve both high throughput and high flexibility. Simulation shows the proposed hardware accelerator can speed up the most important video segmentation algorithms 20 times to achieve realtime performance and has high programmability with a little hardware cost overhead.
Hardware-efficient belief propagation

Belief propagation (BP) is an effective algorithm for solving energy minimization problems in computer vision. However, it requires enormous memory, bandwidth, and computation because messages are iteratively passed between nodes in the Markov random field (MRF). In this paper, we propose two methods to address this problem. The first method is a message passing scheme called tile-based belief propagation. The key idea of this method is that a message can be well approximated from other faraway ones. We split the MRF into many tiles and perform BP within each one. To preserve the global optimality, we store the outgoing boundary messages of a tile and use them when performing BP in the neighboring tiles. The tile-based BP only requires 1-5% memory and 0.2-1% bandwidth of the ordinary BP. The second method is an O(L) message construction algorithm for the robust functions commonly used for describing the smoothness terms in the energy function. We find that many variables in constructing a message are repetitive; thus these variables can be calculated once and reused many times. The proposed algorithms are suitable for parallel implementations. We design a low-power VLSI circuit for disparity estimation that can construct 440 M messages per second and generate high quality disparity maps in near real-time. We also implement the proposed algorithms on a GPU, which can calculate messages 4 times faster than the sequential O(L) method.
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos

The most critical issue of an H.264/AVC decoder is the system architecture design with balanced pipelining schedules and proper degrees of parallelism. In this paper, a hybrid task pipelining scheme is first presented to greatly reduce the internal memory size and bandwidth. Block-level, macroblock-level, and macroblock/frame-level pipelining schedules are arranged for CAVLD/IQ/IT/INTRA/spl I.bar/PRED, INTER/spl I.bar/PRED, and DEBLOCK, respectively. Appropriate degrees of parallelism for each pipeline task are also proposed. Moreover, efficient modules are contributed. The CAVLD unit smoothly decodes the bitstream into symbols without bubble cycles. The INTER/spl I.bar/PRED unit highly exploits the data reuse between interpolation windows of neighboring blocks to save 60% of external memory bandwidth. The DEBLOCK unit doubles the processing capability of our previous work with only 35.3% of logic gate count overhead. The proposed baseline profile decoder architecture can support up to 2048/spl  30 fps videos with 217 K logic gates, 10 KB SRAMs, and 528.9 MB/s bus bandwidth when operating at 120 MHz.
A system level integration methodology for MPEG-2 audio decoder with embedded RISC core

MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4/spl times/6.4 mm/sup 2/, and the tested chip can run at maximum 43.5 MHz clock rate.
Partial-result-reuse architecture and its design technique for morphological operations

This paper proposes a new cost-effective architecture for mathematical morphology named partial-result-reuse (PRR) architecture. For many real-time applications of mathematical morphology, the hardware implementation is necessary; however, the hardware cost of most existing morphology architectures is too high when dealing with large structuring elements. With the partial-result-reuse concept and self-affinity property of general structuring elements, the proposed architecture is more cost-effective and more general than the existing morphology architectures. It can deal with morphological operations with arbitrary structuring elements and can be used for other semi-group operations, and only 2[log/sub 2/n] comparators are needed for n/spl times/n structuring elements. Simulation shows that this architecture can dramatically reduce the hardware cost of morphological operations with all kinds of structuring elements.
Analysis and architecture for memory efficient JBIG2 arithmetic encoder

JBIG2 is the latest international standard for bilevel image compression. It partitions a bilevel image into three types of region - text, halftone, and generic region. This paper addresses the problem of large memory requirements for the contexts. The arithmetic encoders of text region in JBIG2 require a large memory for the contexts. In this work, we proposed several algorithms to reduce the memory requirements. A large portion of total memory requirements are reduced by the proposed algorithms. Moreover, the proposed algorithms are implemented as memory efficient hardware architecture, the unified arithmetic encoder. The experimental results show that the proposed algorithms are efficient. The proposed algorithms can reduce the memory requirements for the contexts by 98.7%. Moreover, the drop of coding gain due to memory reduction for the contexts is only 4.83% in average.
A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method

Among the various transform techniques for image compression, the discrete cosine transform (DCT) is the most popular and effective one in practical image and video coding applications, such as high-definition television (HDTV). We develop a novel 8/spl times/8 two-dimensional (2-D) discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture based on the direct 2-D approach and the rotation technique. The computational complexity is reduced by taking advantage of the special attribute of a complex number. Both the parallel and the folded architectures are proposed. Unlike other approaches, the proposed architecture is regular and economically allowable for VLSI implementation. Compared to the row-column method, less internal wordlength is needed in order to meet the error requirement of IDCT, and the throughput of the proposed architecture can achieve two times that of the row-column method with 30% hardware increased.
A partitioning approach to design fault-tolerant arithmetic arrays

An alternative fault-tolerant design in VLSI-based arithmetic arrays using the partitioning technique is presented. The basic concept is that the arithmetic array can be divided into m parts and its operation can be completed through m iterative calculations with some one part. By taking three such parts with a majority-voting technique at each iteration, error correction can be achieved through m-step computations. This leads to the same fault tolerance capability as triple modular redundancy (TMR). The overheads of chip area and operation time are only introduced by multiplexers, latches, and voters and can be reduced by selecting an appropriate value of m. Based on the AT/sup 2/ (where A is the chip area and T is the operation time) measure of VLSI performance, the proposed design is shown to be superior to the general TMR method. Some application-specified tradeoffs between speed performance and area cost are also presented.<<ETX>>
High performance two-symbol arithmetic encoder in JPEG 2000

In JPEG 2000, the Arithrneric Encoder (AE) is the throiighpirt bottleneck. A n AE capahle of encoding mnltiple symho1.s per cycle i s an @cient way to increase the throitghput .for higli-i-esohiiion inluge. In this paper, a twosyinhol AE arcliitectiire is pi-oposed. which can encode two symmhu1.s percycle. Tliis ar.chitectnre e.rploits  to .slior.teii the critical path fbr two-symbol encoding. Tlir proposed architecfirre can achieve 180 M .syinlJol.shc with 0.35 m?i CMOS tecl?nology and the gate miniit i s 7.7 K.' lnder TermsJPEC 2000, arithmetic encoder, embedded block coding with optimized truncation (EBCOT), MQcoder, JBICZ, multi-symbol AE.