nils-herrmann/clean_scirepeval huggingface dataset:
A motion-robust contactless photoplethysmography using chrominance and adaptive filtering

Recently, the camera-based photoplethysmography (PPG) techniques have been proposed for heart rate measurement due to the contactless and low-cost features. However, the previous works showed limited success for moving subjects, especially when the signal of skin color changes rendered by vigorous motion is in the same frequency band as that by blood volume variations. This paper proposed a motion robust, contactless method for measuring heart rate when the human subject is exercising on some fitness machines, e.g. treadmill or stepper. The proposed method combines the chrominance-based method with adaptive filtering to make the heart rate measurement robust to vigorous motions on fitness machine while estimating the heart rate in frequency domain. To demonstrate the performance of heart rate measurement, we taped a video sequence of treadmill exercise with various motion themes. As shown in experimental results on the video sequence, our method can significantly improve the measurement accuracy from 61% to 90%, comparing to the previous chrominance-based method.
A VLSI implementation of variation-free PUF-based processor for RFID applications

The Physically Unclonable Function (PUF) has been presented to defend physical attacks for RFID authentication. The silicon PUF employs difference of gate and wire delays on silicon chip to protect hardware copies of RFID. Because of the process variation in IC manufacturing, each silicon chip has different delays for gates and wires and, thus, the PUF-based encryption on each chip has different output even though the logic design is the same as the others. Research has been focusing on low-cost PUF implementation with a chain of logic blocks. However, some operating variations such as power-supply voltage and temperature variations might cause the failure of authentication. This paper presents a variation-free PUF-based processor with error control coding (ECC) technology. We used the ECC encoder to generate parity code for variation compensation. Therefore, our chip can generate a variation-free PUF encryption for RFID application. The chip is implemented by TSMC 0.18um CMOS process. As shown in the results, the chip area is as small as 0.83 mm^2 and its power dissipation is 87 uW.
A 2.5-V 14-bit, 180-mW Cascaded  $\Sigma\Delta$ ADC for ADSL2+ Application

This paper presents a sigma-delta (SigmaDelta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 SigmaDelta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 d 15 and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-mum CMOS technology, in a 2.8 mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.
Modeling and formal verification of dataflow graph in system-level design using Petri net

Formal verification at system-level, which also means architecture verification, is different from functional verification at RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping onto silicon. However, a suitable CAD tool is absent to support the simulation and verification at high-level. This paper presents a novel modeling and high-level verification methodology based on a Petri net (PN) model. By the proposed method, a DSP algorithm system in the form of FSFG (fully specified flow graph) is transformed into a PN model. Moreover, verification methods which include static and dynamical phases are applied in the PN domain. Finally, we introduce our software implementation, called HiVED, to show the experimental results.
System-level verification on high-level synthesis of dataflow graph

This paper presents a system-level verification algorithm using the Petri net theory to detect design errors for high-level synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto silicon. Many tools exist for RTL design, but few for high-level synthesis. Instead of applying Boolean algebra, this paper adopts the Petri net theory to verify the correctness of the synthesis result. Herein, we propose three approaches to realize the Petri net based formal verification algorithm and identify the best one that outperforms the others in terms of processing speed and resource usage
VLSI implementation for MAC-level DWT architecture

This paper presents a VLSI design methodology for the MAC-level DWT processor based on a novel limited-resource scheduling (LRS) algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of the limited-resource FIR filter has been developed for the scheduling of MAC-level DWT signal processing. Given a set of architecture constraints and DWT parameters, the LRS algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation, and the performance has also been investigated. Because the registers of FIR filtering are reused for the inter-octave storage, the MAC-level DWT architecture may require less extra inter-octave memory than the traditional architecture.
A wireless narrow-band imaging chip for capsule endoscope

NBI endoscope has been shown to be a superior diagnostic tool for early stage lesion detection, equally wireless capsule endoscope has been proven a effective means of gastrointestinal tract diagnosis. In this paper, we present the first narrow band imaging wireless capsule endoscope. The dedicated dualmode COMS sensor can offer both white light and narrow band images. Implementation results show that the designated 512- by-512 CMOS sensor consumes only 2mA at 3V power supply. The average current of the NBI capsule with a 8Mbps RF transmitter is nearly 7 mA that can work for 6 to 8 hours with two 1.5V 80mA button batteries while the frame rate is 2 fps.
Virtual prototyping of embedded DSP systems

The Rapid Prototyping of Application Specific Signal Processors (RASSP) program initiated by the Advanced Research Projects Agency (ARPA) has proposed a design process that is based on a new design methodology called Virtual Prototyping, wherein VHDL models of hardware components are integrated with application, control and diagnostic software to rapidly prototype complex embedded DSP systems. This paper discusses this new methodology, and compares the RASSP process with current design practice (circa 1993).
A content-based methodology for power-aware motion estimation architecture

This paper presents a novel power-aware motion estimation algorithm, called adaptive content-based subsample algorithm (ACSA), for battery-powered multimedia devices. While the battery status changes, the architecture adaptively performs graceful tradeoffs between power consumption and compression quality. As the available energy decreases, the algorithm raises the subsample rate for maximizing battery lifetime. Differing from the existing subsample algorithms, the content-based algorithm first extracts edge pixels from a macro-block and then subsamples the remaining low-frequency part. In this way, we can alleviate the aliasing problem and thus keep the quality degradation low as the subsample rate increases. As shown in experimental results, the architecture can dynamically operate at different power consumption modes with little quality degradation according to the remaining capacity of battery pack while the power overhead of edge extraction is under 0.8%.
An Aging-Compatible Inductor-Based Equalization Mechanism for LFP Batteries

This paper proposes an aging-compatible inductor- based equalization mechanism for LFP batteries. Due to the characteristic of flat voltage curve, voltage equalization does not always successfully balance a series-connected battery pack. The proposed inductor-based equalization mechanism is developed to smartly balance battery voltage in the right state-of-charge (SOC) region regardless of the extent of battery aging deterioration. The mechanism includes two parts: one is balancing trigger voltage search, and the other one is the balancing current control. Experimental results show that the proposed equalization mechanism can increase the 8.4% storage capacity of the fresh cell and the 3.6% storage capacity of the aging cell. The conventional equalization can increase the 8.3% storage capacity of the fresh cell but decrease the 2.7% storage capacity of the aging cell. The experimental results also prove that equalization at different stages are not always beneficial. Using the aging-compatible inductor- based equalization mechanism can obtain a better balancing performance.
Shadow touching for interactive projectors

Touching devices have become one of the major elements in today's most electronic devices. As the increasing demands of large touching area, the state-of-the-art touching approaches become costly and infeasible. Therefore, it is essential to design a new kind of touch techniques with high touching accuracy and scalability with touching panel size. The purpose of this paper is to provide a touch system that uses the distance between the object (finger or stylus) and its shadow to detect the touch-timing and position. It can be applied to an interactive projection system without using large amount of touch-detecting elements. The proposed touch system only requires a camera and an IR source with an interactive projector to detect the occurrence of touching and its location. The proposed system achieves an average detection rate of 97.53% when the error tolerance is 10 pixels.
A novel vario-power architecture of motion estimation using a content based subsample algorithm

Motion estimation is a key element in many video compression systems; it tends to dominate computational, and hence power, requirements. With the increasing demand for portable, power-aware, multimedia devices, an architecture that can be flexible in both power consumption and compression quality is required. To meet the requirement, the paper presents a novel power-aware architecture, called the vario-power architecture, for motion estimation. Based on a semi-systolic array with a content-based subsample algorithm, the architecture dynamically disables some processing elements to reduce the power consumption. By performing edge extraction first, a threshold is then set as the criterion of whether to enable/disable processing elements and thus the switching activities of the system can be reduced. As a result, the architecture may operate dynamically at different power consumption modes, according to the remaining capacity of the battery pack, with little quality degradation.
The prototype implementation of a varying current charger for aged rechargeable Lithium-ion batteries

A varying current charger for rechargeable Lithium-ion battery is implemented to maintain a predefined energy bound which is consumed by the overpotential equivalent resistance. For aged Lithium-ion batteries, the traditional CCCV charging method charges the battery with the same constant current no matter how the battery internal overpotential resistance increases. The varying current charger developed in this paper will follow the pre-defined energy bound, calculate the internal resistance from EMF and update the next charge current by matching the estimated time to consume the energy bound and the end of charge time. The hardware prototype is implemented with a FPGA and a current source board and the communicates with PC user interface through UART. The experiments show that the efficiency for the varying charge current method is hold for both a new battery and an aged battery although the charging time is compromised.
Two-step windowing technique for wide range motion estimation

This paper presents a memory-efficient motion estimation (ME) technique for high-resolution video compression. The main objective is to reduce the external memory access, especially for limited local memory resource. The key to reduce the memory accesses is based on center-biased algorithm in that the center-biased algorithm performs the motion vector (MV) searching with the minimum search data. While considering the data reusability, the proposed two-step windowing approaches use the secondary windowing as an option per searching necessity. The proposed techniques can save up to 81% of external memory bandwidth and require only 135 MBytes/sec, while the quality degradation is less than 0.2 dB for 720 p HDTV clips coded at 8 Mbits/sec.
A NAND Flash Memory Controller for SD/MMC Flash Memory Card

In this paper, a novel NAND Flash Memory Controller was designed. A t-EC w-bit parallel BCH ECC code was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND type Flash memory. A Code-Banking mechanism was designed for the trade-offs between the controller cost and the ISP (in system programmability) support. With the ISP functionality and the Flash Parameters programmed in the reserved area of the Flash Memory chip during the card production stage, the function for supporting various kinds of NAND Flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual Channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real SD/MMC flash memory card controller chip was designed and implemented with UMC 0.18mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.
A maskable memory architecture for rank-order filtering

This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a bit-serial rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank-order filtering, polarization and update. Using the memory-orient architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined datapath. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits. The bit-sliced read with a polarization selector allows PMM to perform polar determination while the partial write helps next-bit update. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed
A maskable memory architecture for rank-order filtering

This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a generic bit-sliced rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank-order filtering, threshold decomposition and polarization. In conventional designs, these operations are usually implemented as logic circuit and require complex computation. Using the memory-oriented architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined processing. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits for parallel read/write operations. Combining the bit-sliced read with polarization selector allows PMM to perform polar determination while the partial write achieves polarization. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed.
Natural User Interfaces: Cyber-Physical Challenges and Pervasive Applications - A Panel Discussion

This panel discussion aims at exploring the potential applications of emerging natural user interface (NUI) technologies and the challenges they pose to the design and deployment of cyber-physical systems. Based on their research work, six panelists will take turns to present the outlook, the cyber-physical requirements and the promising applications of implicit NUI. We hope these short presentations will lead to thought-provoking discussions and inspire further innovation.
Resonator-based multi-stage modulator for wideband applications with improved dynamic range

A new design methodology for wideband, multi-stage, multi-bit /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) with improved dynamic range, is presented. The key to improving dynamic range is to have the first stage oscillated, then the coarse quantisation noise vanishes and hence circuit non-linearities do not cause a leakage quantisation noise problem. Based on the proposed methodology, a fourth-order four-bit /spl Sigma//spl Delta/M can achieve the dynamic range of 80 dB at the OSR of 8 without using additional calibration techniques.
A voltage-gradient based gas gauge platform for lithium-ion batteries

A supplementary compensator for Texas Instruments gauge IC state-of-charge estimation for lithium-ion batteries is proposed and a hardware platform is designed to verify the proposed compensation. A sudden change in TI gauge SOC estimation sometimes happens near the end section of the battery discharge curves. The reason is that there are non-modification regions posed by the gauge due to larger parameter variation caused larger SOC estimation errors. By designing the OCV extraction hardware and find that the difference of slopes has a big drop when approaching to 50% SOC and the value can be identified. The slope of 50% SOC is a fixed value which can be applied to SOC compensation. By analyzing the discharging curves for many vendors' lithium-ion batteries, we find that there are two conditions can be applied to compensate the SOC estimation. One is the specific difference of voltage slopes during discharging and the other is a specific discharging slope when SOC equals 50%. These check points can provide nearly consistent estimation of SOC for batteries with different cycle times and different ambient temperatures. An add-on platform is designed with the embedded voltage-gradient checkpoint and EMF table and the experimental results show that the SOC estimation accuracy is improved. The accuracy of SOC estimation with the help of the proposed compensation is increasing up to 11% under different variant current profiles.
Rapid prototyping of multimedia chip sets

We have developed a rapid prototyping environment for multimedia applications. The design environment is based on efficient hardware and software reuse, abstraction, design parameterization, and automation. The design methodology maintains a flexible boundary between hardware and software by eliminating hardware fabrication from the design loop. A reusable hardware/software library for video compression has been developed to support the design methodology. We present a case study involving the design of an H.263-based video decoder. This case study illustrates the efficiency and flexibility of the design methodology.
An SOH estimation system based on time-constant-ratio measurement

The SOH of batteries is critical information for electric vehicle (EV) and hybrid electric vehicle (HEV) systems. This paper proposes an SOH estimation system based on time-constant-ratio measurement. There are two reasons of choosing time-constant as aging criterion. First, time-constant represents the response speed of terminal voltage during charging and discharging. Second, time-constant represents the change of internal chemical reactions. The proposed estimation resolves the issues of traditional SOH estimations. There are two widely used SOH estimations. The first one is full-charge-capacity (FCC) estimation. Unfortunately, to access FCC information need to take a long-term charging and discharging test. Therefore, FCC estimation fails to be a fast SOH estimation. The second estimation is internal impedance estimation. However, this SOH estimation may cause large error due to the effect of environmental impedance. For improving the above issues on different SOH estimations, this paper proposes an SOH estimation system based on time-constant-ratio measurement. The time-constant-ratio is a novel criterion for aging effect. The use of this novel criterion for SOH estimation helps to achieve the purpose of an environmental-impedance-free and fast SOH estimation. The proposed estimation is 0.14% the measured time of FCC estimation based on 1C charging and discharging. The measured results have average error below 1% and maximum error below 2%.
A NAND Flash Memory Controller for SD/MMC Flash Memory Card

In this paper, a novel NAND flash memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash memory chip during the card production stage, the function for supporting various kinds of NAND flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash memory card controller chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances
A cardinal image compressor for capsule endoscope

This paper intends to reduce the power dissipation of the GICam image compressor for capsule endoscope or swallowable imaging capsules while the gastrointestinal images are cardinal. In order to further extend the battery life of capsule endoscope, we firstly attempt to analyze the energy distribution and variation of DC/AC coefficients in 2D-DCT domain for twelve tested GI images. According to the analysis results, we can efficiently take advantages of the subsample technique to reduce the memory requirements of green and blue components and hence propose an improved ultra-low-power subsample-based GICam image compressor, called SGICam, to reduce the power dissipation of compression process. Simulation results have been shown that the SGICam image compressor can significantly save 38.5% power dissipation than GICam image one and the average PSNR is 32.18 dB, while the compression ratio can be as low as 4:1.
A VLSI Progressive Coding for Wavelet-based Image Compression

This paper presents a new algorithm for progressive image coding, called tag setting in hierarchical tree (TSIHT). The TSIHT coding can save the memory requirement while keeping the low-bit-rate quality high. The TSIHT algorithm has been implemented onto a chip with 0.35 mu 1P4M CMOS technology. The chip can handle 256times256 gray-scale images and the gate count is about 2560 gates within 247500 mum2 area. The latency of the critical path is 6.32 ns, and the maximum working frequency can be as high as 158 MHz.