nils-herrmann/clean_scirepeval huggingface dataset:
A new thinning algorithm for Arabic characters using self-organizing neural network

In this paper, we propose a new thinning algorithm based on clustering the data image. We employ the ART2 network which is a self-organizing neural network for the clustering of Arabic characters. The skeleton is generated by plotting the cluster centers and connecting adjacent clusters by straight lines. This algorithm produces skeletons which are superior to the outputs of the conventional algorithms. It achieves a higher data reduction efficiency and much simpler skeletons with less noise spurs. Moreover, to make the algorithm appropriate for real-time applications, an optimization technique is developed to reduce the time complexity of the algorithm. Nevertheless, the algorithm is not limited to Arabic characters, it can, also, be used to skeletonize characters of other languages.
An architecture for rate-distortion optimized motion estimation

In this paper, we propose an architecture for motion estimation using variable block matching scheme. It is based on recent advances in rate allocation theory, developed for computing rate-distortion optimized movement compensation. The optimum motion vector and the best quad tree decomposition are determined in a closed loop optimization procedure. Only the quadtree and the motion vector, which are considered to provide the absolute minimum update information, are coded and transmitted. The proposed tree architecture supports pipelined operations. The architecture is suitable for VLSI implementation, owing to modular properties. The Processing Elements (PEs) also support pipelining. An Application Specific circuit prototype has been designed for 4/spl times/4 image blocks. The proposed architecture is scalable and can be easily be adopted for large image blocks.<<ETX>>
A formal high level synthesis approach for DSP architectures

An approach is presented for high-level synthesis of digital signal processing (DSP) algorithms. Two features are provided by the approach: completeness and correctness. A given algorithm is represented in a newly developed language termed the algorithm specification language (ASL). ASL had the ability to describe any general algorithm. An automatic procedure is used to transform an ASL representation into a specific realization specification using a correctness preserving set of transformations. The realization format is based on representing the digital architectures by another language called the realization specification language (RSL). Logic programming is used as a user interface for the synthesis procedure.<<ETX>>
A new ATM congestion control scheme for shared buffer switch architectures

In this paper, we propose a new pre-emptive congestion control (PECC) scheme for deployment in shared buffer-based ATM networks. The proposed PECC uses a rate-based feedback scheme for dynamic bandwidth allocation to best-effort traffic coexisting with guaranteed service traffic. Policing of the guaranteed service continuous bit-rate and variable bit-rate traffic is done using the leaky bucket mechanism. The PECC is a predictive scheme rather than a reactive one. The internal state of the ATM switch is used to predict the onset of congestion. The backward explicit congestion notification feedback scheme developed in earlier works for ATM local area networks has been effectively used in our scheme for delays equivalent to those of MANs and WANs. A simulation model for an illustrative ATM network exhibiting congestion has been constructed. The effect of varying key parameters including mean inter-arrival time, buffer threshold throttle factor, cell reject throttle factor, buffer threshold, filter time and rate reduction delta has been studied. Transient behaviour of an example ATM network employing shared buffer switches under the event of congestion, and its control by backward explicit congestion notification has also been simulated.
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits

Subthreshold operation enables CMOS circuits to operate using very low supply voltages and to dissipate extremely low power with moderate performance. The dynamic threshold MOS technique (DTMOS) is an effective way to improve subthreshold circuit performance. In this paper, we propose a new body biasing technique for PMOS transistors working in the subthreshold region. In the proposed PMOS body biasing technique, the n-wells of PMOS transistors are biased with the gate output. The new technique improves circuit performance over DTPMOS and consumes less power. Simulations done using 0.18 /spl mu/m CMOS technology show that the proposed technique improves a 3-input AND gate speed by 40.1% and has a 82.3% energy-delay-product (EDP) savings over the DTPMOS scheme at 0.37 V supply voltage and 2 MHz operating frequency.
A high-performance 1D-DCT architecture

A high performance 1D-DCT is proposed. It is based on a new distributed arithmetic architecture technique (NEDA). Only addition operations are used, with 35 additions to complete the first phase of the computations. The final phase is the primitive add-and-shift operation. No subtraction, multiplication, or ROM are needed. High-throughput is achieved by pipelining the architecture. The delay of one stage is the delay of one 12-bit addition. Low power consumption is achieved by reducing the computation requirements compared to other implementations of the 1D-DCT.
A fast new method to mitigate amplifier-induced ICI in OFDM systems based on predistortion in DFT domain

We consider the problem of inter-carrier interference (ICI) in orthogonal frequency division multiplexing (OFDM) signals stemming from nonlinearities of power amplifiers (PA). OFDM signals often provoke amplifier nonlinearities due to their high peak-to-average power ratio. Predistortion is often considered in order to mitigate the resulting ICI. We consider a digital baseband predistorter based on the memory polynomial model. The predistorter is designed in the frequency domain using the the indirect training and the linear minimum mean-squared error (LMMSE) estimation method. It is shown that the proposed algorithm has a very low computation complexity and is scalable for systems with a large number of subcarriers. The simulation results show that for similar computational complexities, the proposed method has a significant performance improvement in the sense of total degradation compared to the methods in  and .
Efficient Mapping of ANNs on Hypercube Massively Parallel Machines

This paper presents a technique for mapping artificial neural networks (ANNs) on hypercube massively parallel machines. The paper starts by synthesizing a parallel structure, the mesh-of-appendixed-trees (MAT), for fast ANN implementation. Then, it presents a recursive procedure to embed the MAT structure into the hypercube topology. This procedure is used as the basis for an efficient mapping of ANN computations on hypercube systems. Both the multilayer feedforward with backpropagation (FFBP) and the Hopfield ANN models are considered. Algorithms to implement the recall and the training phases of the FFBP model as well as the recall phase of the Hopfield model are provided. The major advantage of our technique is high performance. Unlike the other techniques presented in the literature which require O(n) time, where N is the size of the largest layer, our implementation requires only O(log N) time. Moreover, it allows pipelining of more than one input pattern and thus further improves the performance.
Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-Vth keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design.
A low power architecture for a new efficient block-matching motion estimation algorithm

This paper presents an exhaustive search algorithm for block matching motion estimation. The proposed algorithm reduces the computational load with successive elimination of non-candidate blocks in the search window. The proposed algorithm locates the global optima as located by the full search block-matching algorithm. This computational reduction leads to low-power VLSI implementation of the algorithm. Also, it leads to a faster efficient motion estimation procedure. The correctness of this algorithm and its complexity are presented. Simulation results on benchmark video clips are presented.
A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000

For JPEG 2000-based multimedia systems, embedded block coding with optimized truncation (EBCOT) tier-1 has become a bottleneck for the entire system. EBCOT tier-1 is full with bit operation, so hardware implementation is more efficient in both system throughput and power consumption. In this paper, a three-level parallel high-speed power-efficient architecture for EBCOT tier-1 is proposed. This architecture is divided into bit-plane coding (BC), arithmetic encoding (AE), and first-in first-out (FIFO) that connects BC with AE and balances the different throughput between them. To improve the system throughput, three levels of parallelism in BC are adopted: 1) the parallelism among bit planes; 2) the parallelism among three pass scans; and 3) the parallelism among coding bits. AE is implemented in four pipeline stages. To achieve power efficiency, several techniques are applied: in BC, simple control logics are added to reduce computation in BC; in FIFO, memory access is reduced since AE is fed with fixed values instead of reading from FIFO; in AE, simple control logics are added to reduce computation in AE and forwarding technique combined with clock gating is adopted to reduce switching activities in the last two pipeline stages. The proposed architecture can encode one code block with size NtimesN in only around (0.35~0.46)timesNtimesN clock cycles. Experimental results, with standard test image benchmarks, show that the proposed power reduction techniques keep the same system throughput and achieve about 27% improvement in the power consumption by comparison with the architecture without these techniques
Power efficient architecture for (3,6)-regular low-density parity-check code decoder

Most of the current LDPC decoder VLSI architecture research focuses on increasing system throughput or reducing hardware implementation complexity, but neglects power consumption. In this paper, we analyze the power consumption of the (3,k)-regular LDPC decoder architecture. Our analysis shows that 95% of the power consumption is consumed in accessing the memory. A new architecture is proposed which reduces memory access, hence power consumption, without sacrificing the performance. Experimental results show reduction in the power consumption by 14% and lower hardware complexity without sacrificing the Bit-Error-Ratio performance compared to previous work.
Analysis and enhancements for EBCOT in high-speed JPEG2000 architectures

Due to the advanced features of the JPEG2000 compression algorithm, hardware designs of the system often face great challenges in terms of reducing delay, power, and silicon area. This paper implements an architecture for Tier-1 of EBCOT in the JPEG2000 encoder that focuses on high speed. Through the design process, critical components that affect the speed of the system are identified and enhancements to reduce the delay are presented at the system and circuit levels. Simulations results show a 17% improvement in speed for some of these components.
Sand monitoring in pipelines using Distributed Data Fusion algorithm

Installation of a system to monitor and measure sand production from an oil well would be valuable to assist in optimizing well productivity and to detect sand as early as possible. In this paper we present a framework for sand monitoring using Wireless Sensor Network (WSN). The framework combines two modules: a Sand Rate Calculation (SRC) module and a Distributed Data Fusion (DDF) module. The framework is designed to collect data from oil pipeline using acoustic sensors (SENACO AS100) in real time. A test bed was established from ten acoustic sensors mounted on a closed loop pipeline. Each acoustic sensor is attached to WSN node. Each node calculates its local sand rate using SRC module. Every node sends its sand rate to the neighbors. The DDF module at each node is using its own local sand rate and the neighbors' sand rate to calculate the global sand rate. The DDF is implemented using a Distributed Kalman Filter (DKF). The proposed framework was successfully evaluated throughout experimental tests.
BCI/AIS low power adaptive architecture for early prediction of epilepsy seizures

Epilepsy is a group of neurological diseases characterized by epileptic seizures. It affects millions of people worldwide, with 80% of cases occurring in developing countries. This can result in accidents and sudden, unexpected death. Seizures can happen undetectably in newborns, comatose, or motor impaired patients, especially due to the fact that many medical personnel are not qualified for EEG signal analysis. Therefore, a portable automated detection and monitoring solution is in high demand. Thus, in this study a system of a wireless wearable adaptive for early prediction of epilepsy seizures, works via noninvasive wireless technology paired with an external control device (e.g., a doctors' smartphone), with a higher than standard accuracy (71%) and prediction time (14.56 sec) using artificial immunity system based detector. These novel architecture can save a life by helping to prevent a seizure's fatal consequences.
A complete scheme for distributed LU decomposition on wireless sensor networks

In this work we are proposing a light-weight energy-aware distributed LU decomposition on energy-constrained wireless sensor networks (WSN). This work builds a complete scheme for the distribution; it involves an efficient block-based distribution of the LU decomposition, a simple energy-aware task mapping, a light-weight TDMA transmission schedule where each node can infer its transmission time slot through a temporary code assigned to it. The proposed scheme achieves 4x speedup in computation, and decreases the average energy consumption by a factor of 3.79.
A VLSI implementation of residue adders

The efficient hardware implementation of residue number system (RNS) architectures has evolved based on the development of integrated circuit technology. The implementation of RNS adders is discussed in this paper. Three approaches (the binary adder, the look-up table, and the hybrid implementation) are analyzed in the scope of VLSI criteria where the performance measures are area and time. Two layout design procedures have been used. They are flexible and support any type of moduli. The implementation complexity depends on the form and size of the modulus, but, in general, the look-up table approach is preferable in both area and time for moduli up to five bits, while the binary adder and the hybrid approaches offer better performance for larger moduli.
A partial parallel algorithm and architecture for arithmetic encoder in JPEG2000

For JPEG2000 real-time applications, embedded block coding with optimized truncation (EBCOT) is a time-consuming part and becoming a bottleneck for the entire system throughput. Since the arithmetic encoder (AE) is one part of EBCOT, low performance of AE can significantly degrade the performance. AE is inherently a serial process with high dependency and parallelization of AE is difficult. In this paper, a partial parallel algorithm for AE is proposed. One distinct characteristic of the proposed algorithm is that two contexts can be processed in one clock cycle. Based on the proposed algorithm, a pipelined architecture is implemented. Experimental results, with standard test image benchmarks, show that the proposed algorithm and architecture achieves about 24% improvement in the system throughput in comparison with the architecture based on the original AE algorithm.
Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion

Coupling capacitances between neighboring wires have a significant effect on performance and delay uncertainty of on-chip interconnects in deep submicron (DSM) technologies. We propose combining inverting and non-inverting repeater insertion to achieve a constant effective coupling capacitance for all possible input transitions. Unlike staggered repeater scheme, the increased wire resistance does not have any effect on our technique, and the performance is less sensitive to repeater placement variation. Simulations at the 90-nm node on a semi-global METAL5 layer show around 25% reduction in worst case delay and 86% delay uncertainty minimization
Improving capacity in bluetooth ad-hoc networks

AbsrrucrBluetooth is a global de facto standard for wireless connectivity. Based on a low-cost, short-range radio link (10 meters), Bluetooth is used as a cablereplacement technology. Bluetooth enabled digital devices can connect and communicate via short-range ad hoc wireless networks. However, a device can only communicate with up to seven other devices per piconet. In this paper, we present some techniques aimed to increase the capacity of the Bluetooth wireless networks. The main advantage and disadvantage of each technique is pointed out. Finally, we provide some performance analysis and simulations of the proposed techniques.
A low power and high performance core for planar object overlaying

The object overlaying operation is one of the most important operations in the Geographical Information Systems and spatial data application. The object overlaying is costly operation due to the amount of data processed during the performing of this operation. One technique to speed up an intensive computational operation is to implement a hardware circuit. This paper presents a low power and high performance core that can be embedded in graphical processors and applications specific chips. It demonstrates the effectiveness of prototyping a core and shows how different design decisions (such cache memory size, memory address generation...) are taken. The core has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype core is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype shows that it is has a maximum delay of 3.2/spl times/10/sup -9/ s, and the power consumption is 0.376 mW. The simulation results indicate a considerably gain in the speed up of the operation and low power consumption.
Dynamic profiling algorithms for low bit rate video applications

We propose three algorithms for low bit-rate (LBR) video transmission, namely simple dynamic profiling (SimpleDP), minimum dynamic profiling (MinimumDP) and mean dynamic profiling (MeanDP). These techniques can be used in conjunction with other low bit rate techniques. Many of the techniques available for low bit rate video applications either require a lot of hardware resources or take advantage of the powerful computer platform that is used for their software implementation. On the other hand, the proposed algorithms are devised to target hardware implementation for systems with limited hardware resources. When compared to the coarse quantization technique, the new techniques not only achieve better compression ratio (twice that of coarse quantization), but also result in better PSNR results (27 dB for coarse quantization versus 33 to 36 dB for the new techniques).
Performance analysis of low-power 1-bit CMOS full adder cells

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.
Rate-adaptive probabilistic spectrum management for cognitive radio networks

Existing distributed opportunistic spectrum management schemes do not consider the inability of today's cognitive transceivers to measure interference at primary receivers. Consequently, optimizing the constrained cognitive radio network performance based only on local interference measurements at cognitive senders does not lead to truly optimal performance due to hidden and exposed primary senders. In this paper, we present the rate-adaptive probabilistic medium access protocol (RAP-MAC) for opportunistic spectrum management. In contrast to existing techniques, our approach addresses the unavoidable inaccuracy in spectrum sensing via a probabilistic spectrum access strategy. Furthermore, RAP-MAC allows multiple cognitive flows to fairly share the available bandwidth without explicit coordination by adopting a non-greedy transmission approach that prevents a single cognitive transmitter from monopolizing an available spectral opportunity. We analytically formulate the cognitive user performance optimization problem as a mixed integer non-linear programming to derive the optimal parameter values. Packet-level simulations show that RAP-MAC achieves between 65% to 119.5% higher goodput with significantly better fairness characteristics compared to existing greedy approaches that overlook the spectrum sensing limitations.
A low power VLSI architecture for multistage interval-based motion estimation (MIME) algorithm

We present an algorithmic enhancement of the full-search block-matching algorithm for motion estimation. The proposed algorithm reduces the computational load by successively eliminating noncandidate blocks from the search window. The elimination process uses low bit-resolution blocks and it is applied in two stages for motion vector computation. This computational reduction leads to enhanced performance in terms of low power consumption and fast motion vector estimation. A low power VLSI implementation of the algorithm is also presented. Simulation results show that the new algorithm, at an average, eliminates more than 88% of the candidate blocks in the search window.