nils-herrmann/clean_scirepeval huggingface dataset:
Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution

Feature matching is an indispensable process for object recognition, which is an important issue for wearable devices with video analysis functionalities. To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP) is employed to accelerate the speed of feature matching. The VVP can transform hundreds of 128-D SIFT vectors into a 64-D histogram for object matching by using the binary-tree-based architecture, and 16 calculators for the computations of the Euclidean distances are designed for each of the two processors in each level. A total of 126 visual words can be saved in the six-level hierarchical memory, which instantly offers the data required for the matching process, and more than 5 times of bandwidth can be saved compared with the non-binary-tree-based architecture. As a part of the recognition SoC, the VVP is implemented with the 65-nm CMOS technology, and the experimental results show that the gate count and the average power consumption are 280 K and 5.6 mW, respectively.
High-performance JPEG 2000 encoder with rate-distortion optimization

An 81 MSamples/s JPEG 2000 single-chip encoder is implemented on 5.5 mm2 area using 0.25-mum CMOS technology. This IC can losslessly encode HDTV 720p resolution at 30 frames/s in real time. Three techniques are adopted: line-based discrete wavelet transform, parallel embedded block coding, and precompression rate-distortion optimization. The line-based discrete wavelet transform achieves the minimum external memory access, while the internal memory is reduced by a proper memory access scheme. The parallel embedded block coding increases the throughput and reduces the memory bandwidth with similar hardware cost comparing to conventional architectures. By accurately estimating bit rates, the precompression rate-distortion optimization reduces the required computational power and processing time of the embedded block coding since the code-blocks are truncated before compression. Experimental results show that this encoder has the highest throughput with the smallest area compared with other designs in the literature
Multiple sprites and frame skipping techniques for sprite generation with high subjective quality and fast speed

Sprite is an image collecting information of a video object through a video sequence. It can be used for efficient video coding, video summary, browsing, and editing. In this paper, three new techniques for sprite generation are proposed. Boundary matching and multiple sprites techniques can improve the subjective quality with refining the positions of the warped frames and generating more than one sprites. The frame skipping technique can skip redundant frames that contain only little new information when the camera revisits a scene several times to accelerate the sprite generation process. Experimental results show that these techniques can be employed independently and can improve the subjective quality as well as reduce the 47.68% - 17.22% runtime of sprite generation. They can be applied with any sprite generation algorithms.
Spatial-temporal consistent labeling for multi-camera multi-object surveillance systems

For an intelligent multi-camera multi-object surveillance system, object correspondence across time and space is important to many smart visual applications. In this paper, we propose a temporal and spatial consistent labeling algorithm for this demand. In the algorithm, an object corresponding database records the temporal and spatial consistency information for each segmented mask. With the database, the object-mask correlations are propagated through the propagation rules by analyzing mask splitting/merging conditions. In the spatial consistent labeling method, the homography warping and the earth mover's distance are adopted to match same objects across different views. The earth mover's distance solves the double matching problem, allows the algorithm to work normally under a small deviation of detected object locations, and makes pairing results have minimum global matching distances. The concept trusting-former- pairs-more is also adopted to avoid frequent pair switching if two objects are too close. The correct spatial labeling rate is about 89.25% in average. For online processing applications, the algorithm need not trace back to the past frames. The overall processing speed is about 10.24 frame per second (fps) with CIF size video running on a 2.8GHz general purpose CPU.
WarmL1: A warm-start homotopy-based reconstruction algorithm for sparse signals

A sparse signal can be reconstructed from a small amount of random and linear measurements by solving a system of underdetermined equations. In this paper, we study the reconstruction problem while the system undergoes dynamic modifications. Resolving this problem from scratch requires high computational efforts. Therefore, we propose an efficient homotopy-based reconstruction algorithm with warmstart, named WarmL1. WarmL1 quickly updates the previous solution to the desired one. Based on the concept of homotopy, WarmL1 breaks the reconstruction procedure into simple steps, and solves the problem iteratively. Four possible applications are presented and discussed to demonstrate the usage of WarmL1 for different warm-start situations. Experiments on these applications are performed. The results show that WarmL1 achieves 3.2× to 37.5× speeding up or up to 1/5100 l2-error at the same computational cost compared to related works.
An efficient parallel motion estimation algorithm for digital image processing

The authors present an efficient block-matching algorithm called the parallel hierarchical one-dimensional search (PHODS) for motion estimation. Instead of finding the two-dimensional motion vector directly, the PHODS finds two one-dimensional displacements in parallel on the two axes (say x and y) independently within the search area. The major feature of this algorithm is that its search speed for the motion vector is faster than that of the other search algorithms on account of its simpler computations and parallelism. Compared with previous research in terms of four measurements, the PHODS can rival those algorithms for performance. The hardware-oriented features of the PHODS, i.e., regularity, simplicity, and parallelism, guarantee that the PHODS is more suitable for hardware realization of a VLSI motion estimator.
System perspective on embedded multimedia

Today's user demand for multimedia has moved into an anywhere anytime paradigm. The ubiquitous usage model creates lots of needs for embedded multimedia system design, and traditional module-wise design concept will not suffice. In this talk, the system design view of modern VLSI architectures for multimedia applications, including H.264, scalable video coding (SVC) and stereo/3D video coding, will be reviewed. In addition, several emerging applications, where machine-to-machine and machine-to-human design factors also become important, like distributed video coding (DVC), free-viewpoint TV and intelligent image recognition, will also be introduced. With the growth of these embedded architecture researches, we can expect a fruitful future of multimedia ICs and systems.
Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory
A novel image compression algorithm by using Log-Exp transform

Based on the logarithmic and exponential transform, an efficient Log-Exp still image compression system is proposed. The Log-Exp compression is designed for the high quality still image, especially for the PSNR above 36. At similar image quality (Log-Exp PSNR=41.52 and JPEG PSNR=41.23), the Log-Exp compression can get a higher compression ratio than JPEG by a factor of1.84 times for the benchmark image Lena. Besides, the Log-Exp compression is computed in pixel-by-pixel without the block artifacts. In comparison with the JPEG compression result (bpp=0.99. PSNR=26.9), the Log-Exp compression uses less bpp (bpp=0.87) to get higher image quality (PSNR=36.38) for the benchmark image baboon.
Parallel architectures of 3-step search block-matching algorithm for video coding

This paper describes fully pipelined parallel architectures for the 3-step search block-matching motion estimation algorithm. Difficulties of this algorithm in hardware implementation were overcome by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed architectures provide efficient solutions for real-time motion estimations required by various video applications.<<ETX>>
Intelligent 3D online virtual conferencing system with natural human-computer interaction

In this paper, we propose an intelligent 3D online virtual conferencing system with a natural human-computer interactive mechanism. With 4 degree-of-freedom of gesture commands as the human-computer interface of the system, participants can change their positions and orientations in a virtual space to interact with others and observe the environment. A 3D tracking-based gesture recognition method with high accuracy and a 3D scene construction technique are adopted in the proposed system. With the real 3D interactive experience provided, the system enables people around the world to communicate and cooperate with each other easier and more efficient than ever before.
Intelligent image inpainting based on a brain-mimicking Recognition-Mining-Synthesis network

In this paper, a new image inpainting method based on a brain-mimicking Bayesian network is proposed. It features the Hierarchical-Spatial-Temporal prediction for simulating brain's neural projections. The trained network can recognize image and automatically mine for defects by its attention model, before synthesizing lost image parts. Difficult inpainting problems, like images with important features lost, are shown to have good results.
Interactive clothing retrieval system

We present an interactive clothing retrieval system, which supports query by a real-world image with target clothing and returns real-world images with similar clothing. The novel clothing shape feature is proposed to describe the shape of clothing in human-oriented coordinate system. We also propose a supervised method for learning a weighting matrix to minimize the intra-class distance while maximize the inter-class distance. The clothing retrieval results are reported quantitatively and the experiment results show that our system supports an accuracy of 61% over the dataset consist of practical various clothing types.
Parallel embedded block coding architecture for JPEG 2000

This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC algorithm. By processing all the bit planes in parallel, the state variable memories for the context formation (CF) can be completely eliminated. The length of the FIFO (first-in first-out) between the CF and the arithmetic encoder (AE) is optimized by a reconfigurable FIFO architecture. To reduce the hardware cost of the parallel architecture, we proposed a folded AE architecture. The parallel EBC architecture can losslessly process 54 MSamples/s at 81 MHz, which can support HDTV 720p resolution at 30 frames/s.
CDSP: an application-specific digital signal processor for third generation wireless communications

We present an application-specific digital signal processor (DSP) for third generation wireless communications. The processor architecture and instruction set of proposed DSP are specially designed for the WCDMA system, where the Viterbi decoding and complex arithmetic are enhanced. These key features make the proposed DSP consume much lower processor MIPS and therefore outperform prior arts in terms of several crucial operations of wireless applications. A prototyping chip has been implemented by using cell-based design approach under TSMC 0.35 /spl mu/m CMOS IP4M technology. At 3.3 V supply voltage, it can operate up to 40 MHz.
3-D perception enhancement in autostereoscopic TV by depth cue for 3-D model interaction

Autostereoscopic TV provides users 3-D experience without wearing glasses. To overcome its poor resolution and to improve the 3-D perception, in this paper, based on Human Visual System (HVS) theory, some depth cues were added into the proposed system. It is shown in the result that the viewers can perceive the 3-D models twice as much as the conventional one. A 3-D model interaction system was built with the proposed framework.
Analysis and reduction of reference frames for motion estimation in MPEG-4 AVC/JVT/H.264

In the new video coding standard, MPEG-4 AVC/JVT/H.264, motion estimation is allowed to use multiple reference frames. The reference software adopts a full search scheme, and the increased computation is in proportion to the number of searched reference frames. However, the reduction of prediction residues is highly dependent on the nature of the sequences, not on the number of searched frames. We present a method to speed up the matching process for multiple reference frames. For each macroblock, we analyze the available information after intra prediction and motion estimation from the previous frame to determine whether it is necessary to search more frames. The information we use includes selected mode, inter prediction residues, intra prediction residues, and motion vectors. Simulation results show that the proposed algorithm can save up to 90% of unnecessary frames while keeping the average miss rate of optimal frames less than 4%.
CRISP-II: Coarse-grained reconfigurable image stream processor for image-processing and intelligent operations in QFHD video cameras

A 372.3 mW coarse-grained reconfigurable image stream processor, CRISP-II, for image-processing and intelligent operations is implemented in TSMC 90 nm low-power technology with a core size of 15.21 mm2. With the proposed multi-stream mode unified protocol, hierarchical ring architecture, and adaptive computing engine, CRISP-II is able to solve the emerging scalability and flexibility problems. It could execute several advanced operations efficiently, like high-dynamic-imaging and face detection. Compared with other state-of-the-art processors, CRISP-II achieves 8.42 times power efficiency than the highly parallel SIMD processor, and meets the real-time requirement of video cameras with QFHD (3840 × 2160) resolution.
Assessing normality of heart sound by matching pursuit residue with frequency-domain-based templates

The healthiness of the heart is import to human for leading a healthy life. Some of the abnormal conditions of heart could be detected by the heart sound. For example, heart murmur is one of the conditions possibly resulting from the illness of heart valves. In this work, we propose a new template family used in the matching pursuit (MP) algorithm to assess the degree of normality of the heart sound. Not only the rating of normality is generated but also an intuitive visual feedback with abnormal interval highlighted is outputted. In this way, the condition like heart murmur is well-identified by inspecting the matching residue. Comparison with previous work which adopts different template family is also given. Experiment results indicate that the proposed family is more effective to matching the normal heart sound to achieve better assessing result.
A 26mW 6.4GFLOPS multi-core stream processor for mobile multimedia applications

A 26 mW 6.4 GFLOPS multi-core stream processor for mobile applications is implemented in 90 nm CMOS technology. A unified stream processing architecture with power-aware frequency scaling and adaptive task scheduling techniques are proposed to reduce the power consumption and increase the performance to achieve the performance of 200 Mvertices/s and 400 Mpixels/s in 3D graphic applications.
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method

In this paper, an effective systematic design method is proposed to construct several efficient VLSI architectures of 1-D and 2-D lifting-based discrete wavelet transform. This design method first performs a specific lifting factorization for any finite discrete wavelet transform filter to obtain an optimal algorithm representation for hardware implementation. The optimized algorithm then turns into 1-D systolic architectures through dependence graph formation and systolic arrays mapping. Based on the 1-D architectures, a general 2-D discrete wavelet transform framework is used to construct the corresponding 2-D architectures. According to the comparison results, the constructed VLSI architectures are more efficient than previous arts in term of arithmetic units and memory storage.
Reconfigurable discrete cosine transform processor for object-based video signal processing

In this paper, a novel reconfigurable discrete cosine transform processor is proposed to perform the Shape-Adaptive DCT (SA-DCT) algorithm, which is a dominating computational kernel of various object-based video signal processing. The SA-DCT algorithm is analyzed in detail to capture important architecture design issues and then design efficient hardware architecture. A dynamically reconfigurable datapath is proposed to meet the run-time reconfigurable computational requirement of SA-DCT. Besides, a prototyping chip has been implemented to prove the feasibility of proposed architecture. This reconfigurable DCT processor supports complete functions of SA-DCT and therefore suitable for high-end and high-quality object-based video applications.
81MS/s JPEG2000 single-chip encoder with rate-distortion optimization

An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128/spl times/128, code block size of 64/spl times/64, and image size up to 32K/spl times/32K.
Design of concurrent error-detectable VLSI-based array dividers

A building-block design for VLSI-based array dividers with concurrent error detection by recomputing using partitioned architecture (REPA) is proposed. The basic concept is that the divide array can be divided into two identical parts and its operation can be completed by using one part through two iterative calculations. With two such parts, a concurrent error detection scheme based on a space redundancy approach can be designed, and error detection is achieved at each iteration. The design is better than previous designs in terms of area requirement, time penalty, error detection capability, and detection period. Advanced analysis with m partitions is included. The experimental results are attractive, especially for certain designs with application-specified tradeoffs between speed performance and area cost.<<ETX>>
Scalable implementation scheme for multirate FIR filters and its application in efficient design of subband filter banks

A scalable implementation scheme for multirate finite impulse response (FIR) filters is presented in this paper. The implementation scheme can reduce the time and area cost of a multirate FIR filter simultaneously. According to the throughput requirement, the proposed scheme achieves a minimum-area design with specified speed. Furthermore, by employing the scalable implementation scheme, we also propose an efficient design technique for subband filter banks.
Efficient stereo video coding system for immersive teleconference with two-stage hybrid disparity estimation algorithm

An efficient coding system is required for immersive teleconference to transmit stereo video. We propose a novel stereo video coding system by exploiting mesh-based disparity estimation and compensation scheme to achieve high coding efficiency and view synthesis ability. Based on the base-layer-enhance-layer structure, this system can provide stereoscopic scalability and compatibility to standards. With considering asymmetric spatial resolution property, good subjective quality can be achieved in ultra low bitrate situation. A novel fast disparity estimation algorithm named as two-stage iterative block and octagonal matching (TS-IBOM) algorithm is also proposed for this system. Experiments show that the proposed disparity estimation algorithm can generate accurate disparity vectors quickly. It is also shown that the proposed coding system has better coding efficiency than MPEG-4 simple profile and temporal scalability tool. The ultra low bitrate of 69 Kbps can be reached to encode 384/spl times/192 60 fps stereo video.
Multi-mode content-aware motion estimation algorithm for power-aware video coding systems

By exploiting the characteristics of the video signal, two content-aware decision criteria are proposed to identify the complexity of motion vectors. Based on these two decision criteria, as well as different combinations of various motion estimation algorithms, four different modes are proposed to allow the computation resources to be varied dynamically between different power constraints. The proposed decision criteria also enable the maximization of quality under each power constraint by a quality-driven diversity-based search approach. According to our simulation results, the proposed algorithm can effectively reduce the computation resources to 40%, 21%, and 3.73% with only 0.0036 dB, 0.01 dB, and 0.16 dB average quality degradation, respectively. As a result, the proposed algorithm is well-suited for video coding systems that desire a power-awareness feature.
A low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-forths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.