nils-herrmann/clean_scirepeval huggingface dataset:
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC

This paper presents design of an 8-bit 1.8 V segmented current steering (CS) digital-to-analog converter (DAC)using 0.18 μm double poly five metal CMOS technology. The DAC has been segmented as 6+2 to achieve optimum performance for minimum area. The simulation result shows a maximum DNLof 0.30 LSB and an INL of 0.33 LSB. The midcode glitch is0.27 pV s. The simulated SNDR and SFDR of the segmented DAC are 52.13 dB and 44.83 dB respectively. The settling of the segmented DAC is 6.02 ns. The power consumption is simulated as 7.88 mW. The prototype will be used in telecommunication applications.
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

In this paper, we proposed a novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that, depending on the input angle, the scale factor can assume only two values, viz., 1 and 1//spl radic/2, and it is independent of the number of executed iterations, nature of iterations, and word length. In this algorithm, compared to the conventional CORDIC, a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle, and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm/sup 2/ and its power dissipation is 7 mW in IHP in-house 0.25-/spl mu/m BiCMOS technology.
A High-Precision Low-Area Unified Architecture for Lossy and Lossless 3D Multi-Level Discrete Wavelet Transform

This paper presents a high-precision low area lifting-based architecture for the unified implementation of both lossy and lossless 3D multi-level discrete wavelet transform (DWT) using LeGall 5/3 wavelet and cohen-daubechies-feauveau 9/7 wavelet. The proposed system is parallel-pipelined, and resource is shared between the lossy and lossless modes, producing a throughput of two outputs/clock and achieving a high-speed and low-area solution. The data width of the design is taken as 20 bits to reach a high peak signal-to-noise-ratio value for multi-level 3D DWT. Targeting a portable and real-time solution, the proposed architecture was successfully implemented on Xilinx Virtex-5 series field programmable gate array, achieving a clock speed of 290 MHz with a power consumption of 467 mW at 200 MHz clock frequency. The design has also been implemented in UMC 90 nm CMOS technology, which consumes 329 mW power at 200 MHz clock frequency. The proposed solution may be configured as lossless or lossy compression, in the field of 3D image compression system, according to the necessity of the user.
Finite element analysis of SiGe heterojunction devices

Two SiGe devices, a n/sup +/-n-p heterojunction diode and an n-p-n HBT have been analyzed using a two-dimensional bipolar device simulator which is based on the finite element method. The various shape functions used in the finite element formulations have been detailed. The dependence of the device characteristics on the various Ge mole-fraction material parameters has been studied. The variation of current gain of SiGe HBT with temperature is discussed.
A parallel approach for affine transform of 3D biomedical images

In biomedical imaging systems, the analysis of the interior of an organ is critical to detect eventual diseases or for surgical operations. So, to get a better view of the organs in 3D coordinate system, the affine transform (AT) has to be applied on the acquired volumetric image. The AT is also applied for biomedical CT image registration. The AT consists of four basic operations viz. rotation, shearing, scaling and translation. In this paper, we have proposed a new algorithm for applying the AT on 3D images. This algorithm exploits the replication of the voxel location to obtain the AT of a volumetric image. This helps in reducing the number of matrix multiplication almost by 50% compared to the conventional algorithm and increases the speed of the execution by a factor of 2. The proposed algorithm is simulated using MATLAB. The algorithm is much faster compared to the conventional method without deteriorating the quality of the 3D image.
A memory efficient 3-D DWT architecture

This paper proposes a memory efficient real-time 3-D DWT algorithm and its architectural implementation. As the running 3D-DWT refreshes the wavelet coefficients with the arrival of every two new frames, the latency of the conventional 3D-DWT reduces by at least 1/4 times. For realization of the transform canonical signed digit multiplier has been used. Parallelism being an added advantage for fast processing has been used with three pipelined stages in this architecture. For coefficient mapping, correlation between LPF and HPF in orthogonal Daubechies wavelet filter has been used. In this design the memory requirement has been optimized to the order O(KN/sup 2/ + (K - 2) /spl times/ N). The proposed architecture has been implemented on Xilinx FPGA devices at an operating frequency of 75 MHz. This low complexity architecture ensures 100% hardware utilization.
A Feasibility Study on Noninvasive Blood Glucose Measurement Using Photoacoustic Method

Diabetes is a disease of concern, which affects vital organs of body. In order to prevent complications, frequent glucose measurement is necessary. This paper presents a possible methodology for noninvasive blood glucose measurement using photoacoustic (PA) method. Although encouraging results have been obtained using the developed system, certain other error sources like melanin content of skin, tissue and skin profiles, variation of blood flow due to pressure changes, should also be considered and investigated.
A novel RAM architecture for bit-plane based coding

An optimized memory organization has been designed for the hierarchical coding of wavelet subbands. Changing the RAM access pattern and using multiple location access at each clock instant can accomplish a better economy in time and resources. The bit-planes are distributed along the z-direction and the x-y plane contains 256 /spl times/ 256 number of memory elements. The memory plane selection is done by the plane-decoder. Each plane has in turn N /spl times/ N memory units, which are addressed by the row and column decoders, composed of 8 number of 8-to-256 decoders. In the proposed organization, a switching structure is used for selection of the data line. In a 256 /spl times/ 256 image, for EZW or SPIHT coding, the proposed RAM structure requires 8 /spl times/ 32 /spl times/ 256 clocks compared to the conventional RAM that requires more clocks. This shows that the proposed RAM requires much fewer clocks to read the data for bit-plane coding.
A 160 MSPS 8-bit pipeline based ADC

This paper presents an 8-bit 160-MS/s pipeline analog-to-digital converter using 0.25-micrometer double poly BiCMOS technology of which the total power dissipation is 135mW with 3.3V of analog power supply. The input signal is assumed to be IV. Double sampling technique is used to increase the sampling speed. The sub-circuits are optimized in terms of power and speed. It achieves differential nonlinearity and integral nonlinearity of /spl plusmn/0.65 LSB and /spl plusmn/0.8 LSB and an estimated area of 1.60mm/sup 2/.
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect

This paper describes the design techniques of a segmented current steering (CS) digital-to-analog converter (DAC)with optimum sizing of the current sources. The DAC has been designed in 0.18 μm CMOS n-well technology provided by National Semiconductor. The 10-bit DAC is segmented as 5+5, where the 5-LSB bits are implemented in binary and the 5-MSB bits are implemented in unary architecture. The matching of the unit current sources plays an important role in determining the overall linearity of the DAC. Static linearity of the DAC can be improved by using larger area of the current source transistors, sacrificing the dynamic performances. At high frequency the spectral performance of the DAC degrades due to the increased parasitic. In this work the current sources are designed with optimum sizes to achieve improved static as well as dynamic performances. In simulation, the DAC achieves a maximum DNL of 0.248 LSB and a maximum INL of 0.440 LSB. The DAC achieves a maximum spurious free dynamic range (SFDR) of 59.79 dB for 5.37 MHz signal in mismatch environment at 500 MSPS sampling rate. The DAC shows a Nyquist SFDR of 57 dB at 500 MSPS sampling rate with mismatch. The DAC consumes only 17.85 mW of power for Nyquist signal at 500 MSPS sampling rate with 1.8 V supply.
Efficient VLSI architecture for bit plane encoder of JPEG 2000

In this paper an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm targeting its FPGA implementation is proposed. Although several speed up techniques exist, we present architecture whose performance is improved based on detailed analysis of data path used to obtain context windows. Multiplexer based coding style is adapted to utilize the resources optimally. After place and route on Xilinx XC2VP30 the proposed design operates at 82 MHz which is capable of encoding 720p (HDTV 1280 × 720, 4∶2∶2) pictures at nearly 44 frames per second. Even though 14 bit planes are used, the implementation results show that the consumption of logic resources in terms of LUTs, slices and flip-flop slices have reduced drastically compared to that of reported designs [1, 2, 3, 4 and 5].
Design, fabrication, testing and simulation of porous silicon based smart MEMS pressure sensor

Porous silicon based piezoresistive pressure sensor has been designed, fabricated and tested in the range of 0 to 1 bar and temperature range of 20/spl deg/C to 80/spl deg/C. A suitable signal conditioning analog circuit consisting of constant current generator and an offset adjustable low noise instrumentation amplifier has been designed and tested. The analog output is then digitized through an ADC and fed to FPGA. Architecture for compensation of nonlinear temperature dependence of pressure sensor has been implemented and tested in FPGA. A device model of porous silicon pressure sensor has also been developed with a view to realize a SMART pressure sensor.
Design of a log-domain differentiator and integrator based universal analog biquadratic filter

A novel implementation of a continuous-time universal analog biquadratic filter is presented. Using a log-domain differentiator and integrator along with a few current mirrors and current copiers, the low pass, high pass, band pass, band elimination (notch) and all pass filter transfer functions are realized. The filter has been designed using a purely current-mode approach. The filter realized is electronically tunable by altering the magnitude of the bias/control current sources. Both the differentiator and the integrator used here have been designed using bipolar junction transistors. The design can be extended and realized with MOSFETs operating in the weak inversion region. The concept has been validated by circuit simulations.
Real time noise cleaning of ultrasound images

This paper presents an efficient algorithm for real time noise cleaning of biomedical ultrasonic images and its VLSI implementation into FPGA. An optimized architecture has been designed with proper parallelism and pipelining as well as removing redundancies to achieve high speed. The implementation has been done in Xilinx XCV50TQ144-5 chip to yield a throughput of one output data per clock cycle with an operating speed of 51 MHz.
Homogeneity induced inertial snake with application to medical image segmentation

Snakes or active contour model is used extensively for image segmentation in varied fields. However, some of its limitations restrict its use in many fields. This paper proposes a new homogeneity controlled inertial force driven energy minimizing spline for tracking object contours. An inertial force apart from the first and second order continuity forces controls the proposed spline. The inertial force is in turn guided by a homogeneity criteria, defined based on the initial location of the spline. This new force field pushes the snake through the concavities and also against weak edge forces. A greedy snake has been used for computation of the energy minimizing spline. The algorithm has been tested on phantoms and ultrasound images as well. This algorithm can even be extended for textured image segmentation and many other areas, where the application of snake is restricted by its inability to conform to true edges or converge to concavities.
A new interpolation free method for X-ray CT image reconstruction

The new fast Radon transform (NFRT) algorithm proposed by the authors is applied here to reconstruct the X-ray CT image. Satisfactory agreement between the original and reconstructed images was obtained. The algorithm does not require computation intensive data interpolation and convert directly between a raster scan grid and the rectangular/polar grid in one step as compared to the back-projection method. Most importantly the compatibility of this algorithm for the X-ray CT system is also verified here.
Design of continuous-time filter for hearing aid application using current conveyors

In this paper we discuss the design of a continuous-time biquadratic filter using second-generation current conveyors, which can be used in hearing aids and also in other analog signal processing applications. The proposed filter has the capability of amplifying as well attenuating the signal of any desired frequency band. This design can be easily implemented in MOS VLSI thereby allowing electronic tuning of the filter parameters. The circuit details of the filter element are presented along with simulation result of the overall filter.
A regular algorithm for real time Radon & inverse Radon transform [image processing applications]

To meet the real time requirements an interpolation free, parallel algorithm for the fast Radon transform (FRT) and inverse FRT (IFRT) is proposed. The proposed method solves all the important problems associated with the previous interpolation free FRT and IFRT algorithm and reduces the number of computations and algorithmic complexities significantly. The proposed algorithm is highly regular and we also describe a methodology to design a dedicated parallel processing architecture from the view point of its efficient implementation.
Cloud Computing-Based Non-Invasive Glucose Monitoring for Diabetic Care

Near infrared photoacoustic spectroscopy is utilized for the development of a continuous non-invasive glucose monitoring system for diabetics. A portable embedded system for taking photoacoustic measurements on tissues to estimate glucose concentration is implemented using field programmable gate array (FPGA). The back-end architecture for high-speed data acquisition and de-noising of photoacoustic measurements operates at 274.823 MHz on a Xilinx Virtex-II Pro FPGA. The glucose measurement technique is verified in vitro on glucose solutions and in vivo on tissues, with photoacoustic signal amplitude varying linearly with sample glucose concentration. A kernel-based regression algorithm using multiple features of the photoacoustic signal is used to estimate glucose concentration from photoacoustic measurements. The calibration algorithm provides a superior performance over previous efforts with a mean absolute relative difference of 8.84% and Clarke Error Grid distribution of 92.86% and 7.14% over Zones A and B of the grid. A cloud computing platform for automated monitoring of blood glucose levels is proposed to enable individuals with diabetes to connect with doctors and caretakers. The developed system is connected to the cloud service using a mobile device, which facilitates implementation of computationally intensive calibration tasks and the storage and analysis of measurement data for treatment and monitoring.
Design of static and dynamic translinear circuits based on CMOS CCII translinear loops

A novel technique to implement static and dynamic translinear circuits based on CMOS CCII translinear (TL) loops is proposed. Various examples of static translinear circuits, such as squaring, square-root, geometric-mean circuits, are introduced. Falling into the category of dynamic translinear circuits, a second-order low-pass filter and a fourth-order filter offering high-pass, low-pass and band-pass transfer functions are presented. This approach opens a new paradigm for design of translinear circuits using CMOS CCIIs and diodes implemented using CMOS technology. The filters realized are electronically tunable by altering the magnitude of the bias/control currents.
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture

This paper presents an 8 bit 1.8 V 500 MSPS digital- to analog converter using 0.18mum double poly five metal CMOS technology for frequency domain applications. The proposed DAC is composed of four unit cell matrix. A novel decoding logic is used to remove the inter block code transition (IBT) glitch. The proposed DAC shows less number of switching for a monotonic input and the product of number of switching and the current value associated with switching is also less than the segmented DAC. The SPICE simulated DNL and INL is 0.1373 LSB and 0.331 LSB respectively and are better than the segmented DAC. The proposed DAC also shows better SNDR and THD than the segmented DAC. The MATLAB simulated THD, SFDR and SNDR is more than 45 dB, 35 dB and 44 dB respectively at 500MS/s with a 10 MHz input sine wave with incoherent timing response between current switches.
Implementation of Smartphone Based Blood Flow Diagnoses from Doppler Spectrogram

This paper introduces a new scheme to identify the blood flow condition based on a processing of the Ultrasound Doppler spectrograms on an Android Smartphone. A set of blood flow spectrograms are processed to denoise and some features are extracted. These features are used in supervised classifiers (support vector machine and k-nearest neighbors) to detect the blood flow abnormalities. Due to better performance of support vector machine, an Android application is implemented based on this classifier for diagnosing arterial diseases.
Accuracy Enhancement for Noninvasive Glucose Estimation Using Dual-Wavelength Photoacoustic Measurements and Kernel-Based Calibration

Frequent monitoring of blood glucose levels is an essential part of diabetes care, but the invasiveness of current devices deters regular measurement. Noninvasive measurement techniques are painless to implement and rely on changes in sample properties to estimate glucose concentration. However, such methods are affected by the presence of different biomolecules, resulting in an increased estimation error and necessitating calibration to obtain accurate glucose concentration estimates. The use of photoacoustic spectroscopy for continuous noninvasive glucose monitoring is studied through measurements on different sample media. In vitro photoacoustic measurements taken from aqueous glucose solutions, solutions of glucose and hemoglobin, and whole blood samples at multiple excitation wavelengths show amplitude and area-based signal features to rise with the increase in sample glucose concentration. The calibration of photoacoustic measurements from glucose solutions using Gaussian kernel-based regression results in a root mean square error (RMSE), mean absolute difference (MAD), and mean absolute relative difference (MARD) of 7.64 mg/dl, 5.23 mg/dl, and 2.07%, respectively. Kernel-based calibration also performs well on solutions of glucose and hemoglobin, and whole blood samples, resulting in lower estimation errors than that of previous efforts and with glucose estimates being in the acceptable zones of a Clarke error grid (CEG). It allows for individual calibration of photoacoustic measurements in vivo, resulting in an RMSE, MAD, and MARD of 19.46 mg/dl, 10.79 mg/dl, and 7.01%, respectively, with 89.80% of the estimates being within Zone A of the CEG. The improvement in estimation accuracy with dual-wavelength photoacoustic measurements and kernel-based calibration would enable continuous noninvasive glucose monitoring, facilitating improved diabetic care.
A 16-bit CORDIC rotator for high-speed wireless LAN

We propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm and it dissipates 7 mW power at 20 MHz frequency.
Architecture of a real-time delay calculator for digital beamforming in ultrasound system

In ultrasound systems synthetic transmit aperture and phased array imaging are widely used for obtaining the high quality images. These imaging systems require dynamic focusing of the multi-element transducer array at large number of scan points during transmission and reception. The array can be focused at any point by applying proper delay values to the signals, received or transmitted by each element of the array. Dynamic focusing requires on-line computation of the delay values, for large number of scan points, corresponding to all the elements of the array. This paper describes a delay calculation algorithm and corresponding hardware architecture for dynamically focusing the convex transducer array at large number of scan points. The hardware architecture for the 64-element convex transducer array, which scans 128 scan lines having 1024 scan points on each scan line, consumes 61k gates. It shows around 57–86% improvement in terms of hardware consumption with respect to those of other available architectures. To reduce the overall complexity and latency of the delay calculator, a 28- bit radicand square root calculator architecture which requires less initial memory than that of the linear approximation and less hardware resources than that of the quadratic approximation is also presented.
VLSI implementation of MQ decoder in JPEG2000

JPEG2000 image compression system consists of two main algorithms namely, discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). These algorithms are compute intensive and require efficient VLSI implementation for real time applications. Bit plane coder (BPC) and MQ coder are the two cores of the EBCOT algorithm. All processes to be executed by the MQ coder are sequential in nature and hence restricts the speed of EBCOT. In this paper we propose a high speed and area efficient architecture of MQ decoder which is implemented on Virtex-2 FPGA. The implementation results show that the design operates at 142 MHz and hardware cost is very low. Estimated frame rate is 20.41 frames per second (FPS) at this frequency. On Virtex-5 device design operates at 222.8 MHz and estimated frame rate is 32.02 FPS. Hardware overhead is reduced to the great extent because shift register based renormalization unit is used which operates at high speed.