nils-herrmann/clean_scirepeval huggingface dataset:
Trends in Design and Implementation of Signal Processing Systems [In the Spotlight]

The design and implementation of SP systems (DISPS) includes the development of software tools and methodologies to support the design of these complex systems. In its early days, DISPS focused on the hardware-based design of SP algorithms to meet real-time requirements. This topic was often called very large-scale integration (VLSI) SP. The emphasis has gradually shifted to include software and hardware/software codesign and implementation aspects. Programmable digital signal processors (DSPs) and embedded central processing units (CPUs) are now popular for real-time SP, such as mobile phones. Field programmable gate array (FPGA)-based designs are also replacing application-specific integrated circuits (ASICs) in many applications.
A high speed feature matching architecture for real-time video stabilization

An efficient feature matching architecture targets at real-time video stabilization is revealed in this paper. For some applications, such as vehicular application, real-time video stabilization is needed to provide instant stable video input. However, feature matching is usually the bottleneck to achieve high performance. High speed feature matching architecture is proposed to accelerate the performance of video stabilization. Locality sensitive hashing (LSH) helps us realize the feature matching procedure in hardware implementation. By applying the proposed dynamic table allocation and on-chip cache mechanism, this work achieves 422K queries/s and real-time feature matching with 90% in memory reduction and more than 50% in relieving the feature bus burden of the system.
Extended intelligent edge-based line average with its implementation and test method

In this paper, an extended intelligent edge-based line average-EIELA is proposed. The EIELA could be used in intra-field de-interlacing to remove the jagged edges and the blurring effect of the bilinear interpolation or the traditional algorithms. The EIELA could change its performance dynamically according to the user's requirement. The proposed method can achieve the highest image quality of the traditional ELA if all the taps in the module are enabled, and it also possesses the ability to reduce the taps usage and instruction counts through the turn-off of some calculating sub-modules. The results and VLSI implementation show the proposed method achieve high image quality and low hardware complexity.
Rate-optimal DSP synthesis by pipeline and minimum unfolding

This paper presents a rate-optimal scheduling for real-time DSP algorithms. By using pipelining and unfolding techniques, the parallel characteristics of recursive DSP algorithms can be exploited. A novel unfolding technique is developed to unravel all concurrency in the recursive data flow graph. A perfect rate unfolded data flow graph is also introduced, which can cause a fully static rate optimal functional pipeline schedule. Experimental results have shown that the proposed method can always yield rate-optimal designs with a smaller unfolding factor compared to previous studies.
A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2/spl times/32.2 /spl mu/m/sup 2/ of chip area with a fill factor of 33%. A 128/spl times/98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-/spl mu/m double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply.
LSI design for MPEG-4 coding system

This paper presents an LSI design for MPEG-4 video coding. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A fast motion estimator architecture supporting predictive diamond search and spiral full search with halfway termination is implemented to make good compromise between compression performance and design cost. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. With high degree of optimization in both algorithm and architecture levels, a cost-efficient video encoder LSI is implemented. It consumes 256.8mW at 40MHz and achieves real-time encoding of 30 CIF (352/spl times/288) frames per second.
Tera-scale performance image stream processor with SoC architecture for multimedia content analysis

A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2mm2 area in 90nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.
A 2D-to-3D conversion system using edge information

The three-dimensional (3D) displays provide a dramatic improvement of visual quality than the 2D displays do. However, for existed 2D contents, depth information is not recorded. Therefore, 2D-to-3D conversion is necessary. This paper presents an automatic system which convert 2D videos to 3D videos. The proposed system groups the blocks into regions using edge information. A prior hypothesis of depth gradient is used to assign depth of regions. Then, the bilateral filter is also applied to diminish block effect and to generate comfortable depth map for 3D visualization.
Computation with simultaneously concurrent error detection using bi-directional operands

A novel method of computation with simultaneously concurrent error detection using bidirectional operands (BIDO) is presented. This technique will provide an efficient and optimal design for an arithmetic unit with fault tolerance. The technique retains all the capabilities of the space redundancy and time redundancy methods, but does not inherit their drawbacks. BIDO requires less hardware overhead than RESO techniques and hardly any redundant time. These capabilities and features make BIDO better suited for designing arithmetic units of VLSI systems, which require high performance and high reliability.<<ETX>>
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method

In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive pyramid algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility.
Content-Aware Prediction Algorithm With Inter-View Mode Decision for Multiview Video Coding

3-D video will become one of the most significant video technologies in the next-generation television. Due to the ultra high data bandwidth requirement for 3-D video, effective compression technology becomes an essential part in the infrastructure. Thus multiview video coding (MVC) plays a critical role. However, MVC systems require much more memory bandwidth and computational complexity relative to mono-view video coding systems. Therefore, an efficient prediction scheme is necessary for encoding. In this paper, a new fast prediction algorithm, content-aware prediction algorithm (CAPA) with inter-view mode decision, is proposed. By utilizing disparity estimation (DE) to find corresponding blocks between different views, the coding information, such as rate-distortion cost, coding modes, and motion vectors, can be effectively shared and reused from the coded view channel. Therefore, the computation for motion estimation (ME) in most view channels can be greatly reduced. Experimental results show that compared with the full search block matching algorithm (FSBMA) applied to both ME and DE, the proposed algorithm saves 98.4-99.1% computational complexity of ME in most view channels with negligible quality loss of only 0.03-0.06 dB in PSNR.
A fast and high subjective quality sprite generation algorithm with frame skipping and multiple sprites techniques

Sprite coding, which is a new coding tool in MPEG-4, can achieve high coding efficiency with high subjective quality at low bit rate. Many sprite generation algorithms have been proposed; however, the computational intensity is very high and the quality is not good enough because of the limitation of simple motion models. A novel sprite generation algorithm is proposed with several new techniques. A frame skipping technique can generate the sprite using only several important frames to accelerate the process and achieve similar subjective quality. In addition, boundary matching and multiple sprites techniques can overcome the limitation of simple motion models to achieve high subjective quality with little computation overhead. Experiments show the proposed algorithm is 46 times faster than the algorithms in MPEG-4 VM and have high subjective quality. These techniques can be also applied with other sprite generation algorithms.
A 473 μW wireless 16-channel neural recording SoC with RF energy harvester

An ultra low-power 16-channel wireless neural recording system-on-a-chip (SoC) is implemented in 0.18μm standard CMOS process. A novel topology of analog front-end (AFE), which combines the auto-zero technique and channel switching method to obtain both low-noise and low-power features, is presented in this work. A time-domain-based modulation approach reduces the power consumption of wireless transmitter dramatically by 80%. A RF energy harvester is also employed in this chip for sustainable use. The input referred noise and average power per channel of AFE are 0.5 μVrms and 1.345 μW respectively. The whole system consumes only 473 μW while performing the signal recording and wireless transmission. Furthermore, practical experiments of human EEG signal recording are demonstrated to verify the functions of proposed SoC.
Mobile energy expenditure tracking system based on heart rate and motion providing extra extensions for personalized care

In order to keep a healthy body it is very important to have balanced energy expenditure (EE). The proposed system utilized the phonocardiogram (PCG) and motion from the user to generate the heart rate. The heart rate has been deemed as a very reliable index to estimate the EE of human body. Efforts are put on developing our system to deal the situations when severe interference coupled into the system while the user is exercising. Accelerometer is used to get the motion status and also the posture of the user which is monitored to determine any anomaly. If anomaly is detected, the system actively issues notification to whom that might give back a timely aid.
A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications

With advances in video coding technology, two main streams of multimedia applications are emerging. The first involves more vivid perceptual experience and is leading to the next generation of TV specifications - Quad Full HD (QFHD, 4096×2160p) and 3D/multi-view TV. The second is the scalable broadcasting and streaming of video.
A novel low-power full-search block-matching motion-estimation design for H.263+

In this paper, a low-power full-search block matching (FSBM) motion-estimation design for the ITU-T recommendation H.263+ standard is proposed. New motion-estimation modes in H.263+ can be fully supported by our architecture. Unlike most previously presented motion-estimation chips, this design can deal with 8/spl times/8 and 16/spl times/16 block size with different searching ranges. Basically, the proposed architecture is composed of an integer pixel unit with 64 processing elements, and a half-pixel unit with interpolation, a control unit, and data registers. In order to minimize power consumption, gated-clock and dual-supply voltages are used. This design has been realized by TSMC 0.6 /spl mu/m SPTM CMOS technology. The power consumption is 423.8 mW at 60 MHz and the throughput is 36 fps in CIF format.
Hybrid color compensation for virtual view synthesis in multiview video applications

Multiview video (MVV) can provide viewers a complete 3D perception by its multiple-viewpoint feature. In order to support smooth viewpoint switching, virtual view synthesis is required. However, color and illumination information varies between views according to the light field conditions. This mismatch leads to ghost effects and wrong reflection phenomena. In this paper, a hybrid color compensation method is proposed. With the proposed inter-view color correspondence estimation, a smoothly changing color/illumination field is established between reference views. Furthermore, the reflection on mirrorlike materials can also be detected and optimized by the proposed hybrid reflection model. As a result, virtual view frames with better perceptual quality are generated. In the objective test, the proposed algorithm also provides 0.26–0.42 dB PSNR gains.
Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events

Most of the abnormal cardiac events such as myocardial ischemia, acute myocardial infarction (AMI) and fatal arrhythmia can be diagnosed through continuous electrocardiogram (ECG) analysis. According to recent clinical research, early detection and alarming of such cardiac events can reduce the time delay to the hospital, and the clinical outcomes of these individuals can be greatly improved. Therefore, it would be helpful if there is a long-term ECG monitoring system with the ability to identify abnormal cardiac events and provide realtime warning for the users. The combination of the wireless body area sensor network (BASN) and the on-sensor ECG processor is a possible solution for this application. In this paper, we aim to design and implement a digital signal processor that is suitable for continuous ECG monitoring and alarming based on the continuous wavelet transform (CWT) through the proposed architectures - using both programmable RISC processor and application specific integrated circuits (ASIC) for performance optimization. According to the implementation results, the power consumption of the proposed processor integrated with an ASIC for CWT computation is only 79.4 μW. Compared with the single-RISC processor, about 91.6% of the power reduction is achieved.
Analysis and VLSI architecture of update step in motion-compensated temporal filtering

Motion-compensated temporal filtering (MCTF) is the core technology of the next generation scalable video coding schemes. There are two key steps in MCTF process, prediction step and update step. In this paper, an efficient scheme along with the hardware architecture of update step for VLSI implementation is proposed. The proposed update step scheme can reduce 55% off-chip memory access and turn the irregular access into regular access. 25% on-chip memory access is also reduced in deriving inverse motion vectors. 80% hardware area is saved by reusing the hardware resources of prediction step
Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding

Fractional motion estimation (FME) is widely used in video compression standards. In H.264/AVC, the precision of motion vector is down to quarter pixels to improve the coding efficiency. However, FME occupies over 45% of the computation complexity in an H.264 encoder and this high complexity limits the processing capability. In this paper, a single-iteration full search FME is proposed. By the algorithm and architecture co-optimization, the bandwidth to the frame buffer is reduced by 31%. Furthermore, 82% of circuit area for the Hadamard transformation and subtraction are saved from the direct implementation. Compared with prior arts, the proposed design supports 3.39 × higher throughput with only 0.02 dB PSNR drop. Thus, the specification of 4096 × 2160 quad full high definition H.264/AVC FME processing can be achieved.
Analysis and architecture design of lifting based DWT and EBCOT for JPEG 2000

Analysis and architecture design for two major parts of JPEG 2000, discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT), are presented in this paper. For DWT, a configurable lifting based 1-D DWT core for both 5-3 and 9-7 filters is proposed. Folded architecture is adopted in DWT to reduce the hardware cost and to achieve the higher hardware utilization. For EBCOT, column-based coding architecture of Tier-1 coding with three speedup methods is proposed. Computation time of context formation in EBCOT can be reduced up to 70%.
Feature-based video stabilization for vehicular applications

This paper describes a method to stabilize video for vehicular applications based on Harris features and adaptive resolution. Lucas-Kanade method is applied to match feature points of consecutive frames and construct the feature motion flow. A damping filer is utilized to model the unwanted motion and global motion is separated by extracting oscillation. 92% correct rate with 0.54 second per frame is achieved. The provided benchmark shows outperformance of the proposed method.
An efficient motion estimation algorithm for real-time MPEG-4 video encoding on multimedia processors

This paper describes an efficient motion estimation algorithm, the predictive line search (PLS), for real-time implementations of MPEG-4 encoder on multimedia processors. The motion vector predictor position is used as the starting point in the search process because the correlation between neighboring motion vectors is strong. The line search pattern is used in the proposed algorithm to reduce the memory access as well as to exploit the special multimedia processor instructions for SAD calculations. Experimental results show that the performance of the predictive line search is very close to the full search algorithm with a speed up of 10. Compared with the well-known diamond search, the predictive line search shows better performance and robustness especially for high motion sequences. prototype MPEG-4 encoding system is implemented on a 216 MHz multimedia processor with VLIW (very long instruction word) architecture to verify the effectiveness of the predictive line search. Real-time encoding of MPEG-4 Simple Profile Level 3 (CIF, 30 fps) can be achieved with only 63% of the processor load.
An efficient architecture for two-dimensional discrete wavelet transform

This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform module, we employ the polyphase decomposition technique and the coefficient folding technique to the decimation filters of stages 1 and 2, respectively. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are 100% hardware utilization, fast computing time (0.5-0.67 times of the parallel filters'), regular data flow, and low control complexity, making this architecture suitable for next generation image compression systems, e.g., JPEG-2000.
System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint

Multiview video coding (MVC) systems require much more bandwidth and computational complexity relative to mono-view video systems. Thus, when designing a VLSI architecture for MVC systems, the hardware resource allocation is a critical issue. In this paper, we propose a new system bandwidth analysis scheme for various and complicated MVC structures. The precedence constraint in the graph theory is adopted for deriving the processing order of frames in a MVC system. In addition, current block centric scheduling (CBCS) and search window centric scheduling (SWCS) are proposed for MVC bandwidth analysis. By adopting data reuse schemes, several design points are explored with the aid of the proposed analysis scheme. The suitable hardware resource allocation can be easily determined.
Algorithm and architecture of video segmentation hardware system with a programmable PE array

Video segmentation is a key unit in content-based video encoding systems, such as MPEG-4. Existing algorithms are too complex for real-time applications, and hardware implementation is infeasible because of the global and irregular operations. In this paper, a hardware system for video segmentation is proposed from algorithm level to hardware architecture level. A hardware-oriented algorithm is first proposed to generate accurate object masks with local pixel operations and morphological operations, which are suitable for hardware implementation. After that, the hardware architecture is designed based on partial-result-reuse architecture and programmable morphology PE array architecture, which can achieve both high flexibility and throughput. A prototype chip is implemented to achieve the processing speed of 30 QCIF frames per second and 7,680 morphological operations per second at 26 MHz. It also shows the hardware cost is small, and the proposed video segmentation hardware system is suitable to be integrated into any content-based video encoding systems.
Memory analysis and architecture for two-dimensional discrete wavelet transform

The large amount of the frame memory access and the die area occupied by the embedded internal buffer are the most critical issues for the implementation of the two-dimensional discrete wavelet transform (2D DWT). The former may consume the most power and waste the system memory bandwidth. The latter may enlarge the chip size and also consume much power. We categorize and analyze the 2D DWT architectures by different external memory scan methods. Then the overlapped stripe-based scan method is proposed to provide an efficient and flexible implementation for 2D DWT. The implementation issues of the internal buffer are also discussed, including the lifting-based and convolution-based. Some real-life experiments are given to show that the performance of area and power for the internal buffer is highly related to memory technology and working frequency, instead of the required memory bits only.
The chip design of a 32-b logarithmic number system

To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log/sub ) function and Iterative Difference by Linear Approximation (IDLA) to design 2/sup 0.x/ function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.<<ETX>>