Optical linear feedback shift register

Linear feedback shift registers (LFSRs) are essential components of communications systems such as pseudo random bit sequence (PRBS) generators, convolutional encoders, scramblers and randomizers [1, 2]. Fig.1 (left) shows a LFSR scheme in which the XOR gate is operated among two tapped bits i and i+k within the shift register. The result bit is fed to the shift register at the last position (n) and the sequence in the register is 1-bit shifted as well. The experimental setup for demonstrating an all-optical LFSR is shown in Fig.1 (middle). The main components of the scheme are an optical buffer , a bit selecting circuit, and a XOR gate. The data vector (A) is generated by modulating the continuous wave (CW) λs with a 10Gbps non-return-to-zero (NRZ) electrical pattern whose period is TP=33.3168µs. Only 5 bits are used as the initial sequence for the shift register. The travelling time of the packet in the buffer is TL=1.85 µs, meaning that up to 18 round trips can be accommodated by the pattern's period TP but one of those should be preserved for erasing the buffer before it is fetched a new sequence. The initial sequence enters the buffer as well as propagates directly to the bit selecting circuit. Every round trip, a new sequence as a replica of the previous one plus the feedback bit comes out. At the last round trip, a pump signal inserted into the buffer through the circulator will strongly reduce the gain of the semiconductor optical amplifier (SOA). Both the circulating packet and the accumulating in-band amplified spontaneous emission (ASE) noise will be suppressed. The buffer is now completely cleaned for a new cycle. The first and the last bits of the 1-bit shifted sequence are selected for the XOR operation. Referring to Fig.1 (left), i=1 and k=4, n=5. With this setup, the bit selecting circuit requires 2 clock signals (C) for tap the proper bits from the incoming sequence. The sampling process is done by exploiting four-wave-mixing (FWM) in a 250m-long highly nonlinear fiber (HNLF). Since at every round trip the sequence must be 1-bit shifted, the sampling clocks must be accordingly delayed for 1 bit, resulting the clock period of TC=TL+TB where TB=100ps is the bit time. The outputs of the bit selecting circuit are fed as pump signals to port a and d of a SOA Mach Zehnder interferometer (MZI). They are synchronized with a clock at λs used as the probe signal (F) at port b. The output of the XOR gate is then fed back into the buffer. The feedback bit should be precisely allocated at the end of the packet circulating inside the buffer, meaning that the feedback time should be TF=TL+TB+Tseq in which Tseq is the original sequence duration and equal to 500ps in our setup. Fig.1 (right) depicts the results at the 10th round trip for two different input initial sequences (10001) and (10011) taken at point (B). The equalization between bits in the sequence and the quality of the pulses is strongly limited by the accumulating ASE noise inside the buffer, the long fiber-based structure and the bit's polarization. The fiber-based setup also causes misalignment between the clocks, spoils the essential synchronism and degrades the performance of the FWM and the XOR operation. One possible solution for solving all of these problems and hence improving the performance is the integration approach. The bit selection could be implemented exploiting nonlinear effects into an SOA or a periodic-poled lithium niobate (PPLN) instead of using a long HLNF. Moreover the extinction ratio of the pulses at the SOA-MZI XOR output (&#60;13.5dB) could be improved, e.g. with a saturable absorber at its output, thus increasing the number of allowed round trips into the shift register and reducing the noise on the final bit sequence.