nils-herrmann/clean_scirepeval huggingface dataset:
An autozeroing floating-gate bandpass filter [in CMOS]

We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its DC operating point adaptively. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cut-off is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data. This autozeroing floating-gate amplifier demonstrates how to use continuous-time, floating-gate adaptation in amplifier design.
The multiple-input translinear element: a versatile circuit element

We define the multiple-input translinear element (MITE), a versatile circuit primitive from which we can construct low-voltage translinear circuits and log-domain filters. A K-input MITE produces an output current that is exponential in a weighted sum of its K input voltages. We briefly discuss six MITE implementations and show experimental data from two of these six that we have fabricated in a 2-/spl mu/m double-poly CMOS process available through MOSIS.
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

| Four-quadrant synapse stuu In our rst treatments of single-transistor synapses ((1], 2]; elaborated in 3]), we presented the electron-tunneling, hot-electron{injection, and multiplicative behavior of these devices. We used a feedback connguration to characterize the tunneling and hot-electron injection phenomena in these synapses 3]. We also derived an eeective learning rule, but we did not consider any speciic ways that these synapses could be used in a network. Our presentation of the autozeroing oating-gate ampliier (AFGA) 5], 6] showed the rst circuit applications of a single-transistor synapse with continuous oxide currents. In another paper , we generalized the AFGA synapse connguration to consider the behaviors that emerge when single-transistor synapses are coupled together to form various continuous-time learning networks 7]. This paper began to consider these oating-gate devices as continuous-time circuit elements. This paper presents the next fundament a oating-gate synapse that computes four-quadrant products of its input and weight value, and computes a four-quadrant correlation of the input and output or error function variables. * need to say something of why four-qudrant computations are important, why they are diicult, etc.  Four quadrant operation is essential in most adaptive lter and neural network applications. Biological synapses have only seem to have two-quadrant behavior, but ..... ** make this paragraph smaller ** Our oating-gate synapses possess ve important necessary to build adap-tive analog VLSI systems 1], 4]. First, in the absence of learning, the weight is stored permanently; because the oating gate is surrounded by SiO 2 , charge leakage is negligible. Second, when operated with subthreshold currents, the synapse's output current is the product of the input signal with the synaptic weight. Third, the synapse requires minimal area, because it comprises only one or two transistors. Fourth, the synapse dissipates a minimal amount of power, because it operates at subthreshold current levels. Fifth, the synapse implements a learning rule for modifying the weight on the oating gate; the form of this rule depends on how various error signals are fed back to the oating gate. In Section I, we review the source-degenerated pFET synapse, and present the operating conditions that we will (a) (b) Fig. 1. The source-degenerated (s-d) pFET synapse. (a) Circuit diagram of the s-d pFET synapse. The s-d pFET synapse is comprised of a pFET single-transistor synapse and the x diode element, which provides feedback to the source terminal. This feedback results in a weaker exponential …
Floating-gate CMOS analog memory cell array

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip non-volatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We achieve greater than 13-bit precision with no crosstalk between memory cells.
A four-quadrant floating-gate synapse

We present a new type of pFET synapse; by degenerating the source, the oxide currents provide stabilizing feedback to the floating gate and to the drain. We present experimental measurements from a floating-gate synapse that simultaneously computes four-quadrant products of its input and weight values, and computes a four-quadrant correlation, typical of Hebbian and backpropagation learning rules, between the input and drain voltages. Our four-quadrant synapse is built from two source-degenerated pFET synapses; by adding weak exponential feedback to the source of a floating-gate pFET synapse, we obtain a floating-gate synapse with unique dynamical properties. This four-quadrant synapse can become the fundamental building block of many continuous-time neural-network learning algorithms.
Multiple-input translinear element networks

We describe a class of nonlinear circuits that accurately embody product-of-power-law relationships in the current signal domain. We call these circuits multiple-input translinear element (MITE) networks. A MITE is a circuit element that produces an output current that is exponential in a weighted sum of its input voltages. We describe intuitively the basic operation of MITE networks and we show experimental data from a squaring-reciprocal circuit breadboarded from bipolar-floating-gate MOS (biFGMOS) MITEs that we fabricated in a 2-/spl mu/m double-poly CMOS process available through MOSIS.
AN AUTOZEROING FLOATING-GATE BANDPASS FILTER

We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its DC operating point adaptively. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that complete1,y characterize the amplifier and that are in good agreement with experimental data. This autozeroing floating-gate amplifier demonstrates how to use continuous-time, floatinggate adaptation in amplifier design.
Impact Ionization and Hot-Electron Injection Derived Consistently from Boltzmann Transport

We develop a quantitative model of the impact-ionizationand hot-electron–injection processes in MOS devices from first principles. We begin by modeling hot-electron transport in the drain-to-channel depletion region using the spatially varying Boltzmann transport equation, and we analytically find a self consistent distribution function in a two step process. From the electron distribution function, we calculate the probabilities of impact ionization and hot-electron injection as functions of channel current, drain voltage, and floating-gate voltage. We compare our analytical model results to measurements in long-channel devices. The model simultaneously fits both the hot-electron- injection and impact-ionization data. These analytical results yield an energydependent impact-ionization collision rate that is consistent with numerically calculated collision rates reported in the literature.
Analysis, synthesis, and implementation of networks of multiple-input translinear elements

At the time of its invention in the seventeenth century, the logarithmic slide rule literally revolutionized the way calculation was done. From then until the advent of the pocket calculator, this analog computational device was widely used to perform multiplications and divisions, to raise numbers to fixed powers and extract fixed roots of numbers. Today, the slide rule may be gone, but it is not forgotten. In this thesis, I present a class of simple translinear network circuits which essentially function as electronic slide rules, accurately computing products, quotients, powers, and roots. I describe two different analysis procedures that allow us to determine the steady-state relationship between input and output currents. I also describe systematic techniques for synthesizing such circuits whereby we can produce a circuit whose steady-state transfer characteristics embody some desired product-of-power-law relationship between input and output currents. These circuits are made from multiple-input translinear elements; such elements produce output currents that are proportional to the exponential of a weighted sum of their input voltages. We can implement the weighted voltage summations with either resistive or capacitive voltage dividers. We can obtain the required exponential voltage-to-current transformations from either bipolar transistors or subthreshold MOS transistors. The subthreshold floating-gate MOS transistor naturally implements the exponential-of-a-weighted-sum operation in a single device. I will present experimental results from several of these translinear network circuits breadboarded from subthreshold floating-gate MOS transistors. I will also describe and present experimental data from a variety of other implementations of the multiple-input translinear element.
A Complementary Pair of Four-Terminal Silicon Synapses

We have developed a complementary pair of pFETand nFET floating-gate silicon MOS transistors foranalog learning applications. The memory storage is nonvolatile;hot-electron injection and electron tunneling permit bidirectionalmemory updates. Because these updates depend on both the storedmemory value and the transistor terminal voltages, the synapsescan implement a learning function. We have derived a memory-updaterule for both devices, and have shown that the synapse learningfollows a simple power law. Unlike conventional EEPROMs, thesynapses allow simultaneous memory reading and writing. Synapsetransistor arrays can therefore compute both the array output,and local memory updates, in parallel. We have fabricated prototypesynaptic arrays; because the tunneling and injection processesare exponential in the transistor terminal voltages, the writeand erase isolation between array synapses is better than 0.01 percentThe synapses are small, and typically are operated at subthresholdcurrent levels; they will permit the development of dense, low-powersilicon learning systems.
A floating-gate MOS learning array with locally computed weight updates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 /spl mu/s, whereas the weight normalization takes minutes to hours.
The matching of small capacitors for analog VLSI

The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 /spl mu/m/spl times/6 /spl mu/m to 20 /spl mu/m/spl times/20 /spl mu/m fabricated in a standard 2 /spl mu/m double-poly CMOS process available through MOSIS. For a size of 6 /spl mu/m/spl times/6 /spl mu/m, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 /spl mu/m/spl times/20 /spl mu/m size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching.
An Adaptive WTA using Floating Gate Technology

We have designed, fabricated, and tested an adaptive Winner-Take-All (WTA) circuit based upon the classic WTA of Lazzaro, et al . We have added a time dimension (adaptation) to this circuit to make the input derivative an important factor in winner selection. To accomplish this, we have modified the classic WTA circuit by adding floating gate transistors which slowly null their inputs over time. We present a simplified analysis and experimental data of this adaptive WTA fabricated in a standard CMOS 2µm process.
An autozeroing amplifier using PFET hot-electron injection

We have developed an amplifier which removes its "off-set" as a natural part of its operation by modifying the charge on a floating gate. The charge on the floating gate is adapted by a combination of electron tunneling and hot-electron injection, resulting in a nonlinear high-pass filter with a cutoff frequency less than 1 Hz. We show experimental data from this autozeroing amplifier for various input waveforms, and an analytical model which fits the output waveforms. This autozeroing amplifier is a single-input case of a continuous learning circuit.
Translinear circuits using subthreshold floating-gate MOS transistors

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2μm double-poly p-well process through MOSIS.
Single transistor learning synapse with long term storage

We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectivity for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current.
A /spl nu/MOS soft-maximum current mirror

In this paper, we describe a novel circuit consisting of N+1 MOS transistors and a single floating gate which computes a soft maximum of N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage swing and an interesting feedback mechanism which causes its output impedance to be comparable to that of a normal MOS transistor despite the fact that the output device is a floating-gate transistor.
A high-resolution non-volatile analog memory cell

A 3-transistor non-volatile analog storage cell with 14 bits effective resolution and rail-to-rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hot-electron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feedback control, errors due to oxide mismatch or trapping can be nearly eliminated, Small size and low power consumption make the cell especially attractive for use in analog neural networks. The cell is fabricated in a 2 /spl mu/m n-well silicon Bi-CMOS process available from MOSIS,.
Bayesian Analysis of fMRI data with Spatial Priors

Functional Magnetic Resonance Imaging (fMRI) using Blood Oxygen Level Dependent (BOLD) contrast is an established method for making inferences about regionally specific activations in the human brain [7]. From measurements of changes in blood oxygenation one can use various statistical models, such as the General Linear Model (GLM) , to make inferences about task-specific changes in underlying neuronal activity. In previous work [21, 23, 22] we have developed a spatially regularised General Linear Model (GLM) for the analysis of fMRI data which allows for the characterisation of regionally specific effects using Posterior Probability Maps (PPMs). This spatial regularisation has been shown [23] to increase the sensitivity of inferences one can make. This paper reviews our body of work on spatially regularised GLMs and describes two new developments. These are (i) an approach for assessing multivariate contrasts and (ii) a method for choosing the thresholds that generate PPMs. The paper is structured as follows. Section 2 reviews the theoretical development of the algorithm. This includes a description of a Variational Bayesian algorithm in which inference is based on an approximation to the posterior distribution that has minimal KLdivergence from the true posterior. Sections 3 and 4 describe the new approaches for assessing multivariate contrasts and PPM thresholding. In section 5 we present results on null fMRI data, synthetic data and fMRI from functional activation studies of auditory and face processing. The paper finishes with a discussion in section 6.
Technical Note Conjunction revisited

The aim of this note is to revisit the analysis of conjunctions in imaging data. We review some conceptual issues that have emerged from recent discussion (Nichols, T., Brett, M., Andersson, J., Wager, T., Poline, J.-B., this issue.  Inference with the Minimum Statistic.) and reformulate the conjunction of null hypotheses as a conjunction of k or more effects. Analyses based on minimum statistics have typically used the null hypothesis that k = 0. This enables inferences about one or more effects (k N 0). However, this does not provide control over false-positive rates (FPR) for inferences about a conjunction of k = n effects, over n tests. This is the key point made by Nichols et al., who suggest a procedure based on supremum P values that provides an upper bound on FPR for k = n. Although valid, this is a very conservative procedure, particularly in the context of multiple comparisons. We suggest that an inference on a conjunction of k = n effects is generally unnecessary and distinguish between congruent contrasts that test for the same treatment and incongruent contrasts of the sort used in cognitive conjunctions. For congruent contrasts, the usual inference, k N 0, is sufficient. With incongruent contrasts it is sufficient to infer a conjunction of k N u effects, where u is the number of contrasts that share some uninteresting effect. The issues highlighted by Nichols et al., have important implications for the design and analysis of cognitive conjunction studies and have motivated a change to the SPM software, that affords a test for the more general hypothesis k N u. This more general conjunction test is described.
Investigating the Functional Role of Callosal Connections with Dynamic Causal Models

The anatomy of the corpus callosum has been described in considerable detail. Tracing studies in animals and human postmortem experiments are currently complemented by diffusion‐weighted imaging, which enables noninvasive investigations of callosal connectivity to be conducted. In contrast to the wealth of anatomical data, little is known about the principles by which interhemispheric integration is mediated by callosal connections. Most importantly, we lack insights into the mechanisms that determine the functional role of callosal connections in a context‐dependent fashion. These mechanisms can now be disclosed by models of effective connectivity that explain neuroimaging data from paradigms that manipulate interhemispheric interactions. In this article, we demonstrate that dynamic causal modeling (DCM), in conjunction with Bayesian model selection (BMS), is a powerful approach to disentangling the various factors that determine the functional role of callosal connections. We first review the theoretical foundations of DCM and BMS before demonstrating the application of these techniques to empirical data from a single subject.
Human Brain Function, Second Edition

This updated second edition provides the state of the art perspective of the theory, practice and application of modern non-invasive imaging methods employed in exploring the structural and functional architecture of the normal and diseased human brain. Like the successful first edition, it is written by members of the Functional Imaging Laboratory - the Wellcome Trust funded London lab that has contributed much to the development of brain imaging methods and their application in the last decade. This book should excite and intrigue anyone interested in the new facts about the brain gained from neuroimaging and also those who wish to participate in this area of brain science.
Dynamic causal models of brain responses

Functional magnetic resonance imaging (fMRI) is used to investigate where the neural implementation of specific cognitive processes occurs. The standard approach uses linear convolution models relating experimentally designed inputs, through a hemodynamic response function (HRF), to observed blood oxygen level dependent (BOLD) signals. However, these models are blind to the causal mechanisms that underlie observed BOLD responses, both in terms of neural dynamics and neurovascular coupling. This article reviews current developments towards causal models of how BOLD responses are generated. We focus on (i) biophysical input-state-output models with neural and hemodynamic state equations, and (ii) models of functional integration that explain local dynamics through interactions with remote areas. Forward models with parameters at the neural level, e.g. Dynamic Causal Modeling, combine both approaches, modeling the entire causal chain from external stimuli, via induced neural dynamics, to observed BOLD responses.