nils-herrmann/clean_scirepeval huggingface dataset:
A clock gated flip-flop for low power applications in 90 nm CMOS

A new clock gated flip-flop is presented. The circuit is based on a new clock gating approach to reduce the consumption of clock signal's switching power. It operates with no redundant clock cycles and has reduced number of transistors to minimize the overhead and to make it suitable for data signals with higher switching activity. The proposed flip-flop is used to design 10 bits binary counter and 14 bits successive approximation register. These applications have been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and have been simulated using Spectre. Simulations with the inclusion of parasitics have shown the effectiveness of the new approach on power consumption and transistor count.
A computational kernel for fast and efficient compressed-domain calculations of wavelet subband energies

This paper develops algorithms for calculating commonly used energy measures directly from the data stream of wavelet-compressed images. Incorporating these techniques into an underlying computational kernel allows many image-processing tasks to be efficiently implemented in the compressed domain. Compared to traditional decompress-process methods, the proposed techniques offer significant memory savings and reduce the computational load of the system. Experimental results show that the calculated energy values are accurate and obtained with less strain on system resources. The potential savings achieved by incorporating the proposed kernel are illustrated in a texture classification example.
A structured approach for designing low power adders

A performance analysis of a general 1-bit full adder cell is presented. The adder cell is anatomized into smaller modules using the proposed structured approach. The modules are studied extensively and several designs of each of them are shown. Connecting combinations of designs of these modules together we construct 24 different 1-bit full adder cells (some of them are novel circuits). Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Some of the new cells outperform existing standard designs of the full adder cell.
A high speed array architecture for 2-D wavelet transform

In this paper, an efficient, simple and fast systolic-like architecture for a 2-D Discrete Wavelet Transform (DWT) is proposed. The "approximation" and "detailed" components of a signal are computed simultaneously in the first octave and alternately in other octaves. Each processing element has its own local memory for storing the intermediate data. The proposed architecture uses the same clock frequency for every octave level. It has a 100% utilization for a 2-octave level architecture, and N/sup 2/+N period cycle. The architecture is scalable for different filter length (divisible by 2) and different octave levels.
Green novel power control framework for dense femtocell grids

High dense neighboring Femtocells are seen as future low-cost solution to significantly gain capacity compared to Macro-only deployment. Dense HetNet, which requires progressive introduction of Femtocells, offers scalable networks towards 1000 fold gains in capacity as per technology vision for 5G. In such dense networks, the problem of interference comes between the Macrocells and Femtocells as well as among the Femtocells themselves. Valuable insights in the Macro-Femto interference are available, while the Femto-Femto interference aspects remain partially addressed. This paper outlines this problem and points potential solution strategies to mitigate the Femto-Femto interference, increase the network capacity, decrease the power consumption and likewise reduce the CO2 footprint. According to the system level simulation of our novel power control framework, user throughput is 15,9% to 49,3% greater than that of the conventional power control schemas. This is equal to 9,87 to 12,35kg CO2 emission reduction per year for one Femtocell BS.
System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies

Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution schemes for managing simultaneous access requests to the communication resources are required to prevent system performance degradation. A new SOC on-chip communication architecture, Dynamic Parallel Fraction Control Bus, which offers an attractive solution for the problem and addresses shortcomings of existing communication architectures is presented. To demonstrate the benefits of the proposed architecture, several existing communication architectures were compared with the proposed architecture on the basis of two application prototypes. Through experimentation it has been shown that the proposed architecture not only exhibits both hardware simplicity and system performance improvements, but also produces better bus bandwidth control and scalability properties compared with the existing communication architectures.
Opportunistic Spectrum Access: From Theory to Practice

In this article, an experimental study of the less studied topic of distributed OSA implementation have been presented. Hardware technologies do not provide the cognitive transceiver requirements needed to exploit OSA to its full potential, suboptimal OSA approaches developed to target that low-complexity transceivers can achieve significant performance gains compared to approaches theoretically optimized disregarding the practical system constraints, is demonstrated. Theoretical OSA approaches can exploit the gains available to the individual practical components. A radio transceiver with cognition capabilities and real-time reconfigurability can be used to realize cognitive radio networks.
A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers

A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (VCDL) are used to multiply the input frequency of a clock signal by n. This frequency multiplier is less susceptible to jitter- accumulation as it is a DLL-based design. The proposed circuit can operate at a substantially low supply voltage. Simulation results show that the proposed frequency multiplier dissipates about 10% to 50% less power than similar clock multiplier circuits. In addition, an architecture for programmable frequency multiplication has been proposed in this paper.
An efficient area manipulation architecture for frequency domain encoding process

Frequency-Domain Motion Estimation (FD-ME) evolved as a technique that would greatly reduce ME computations and the whole encoding time. In Dynamic Padding FD-ME (DP-FD-ME), a dynamic padding threshold adaptively selects the proper search area size according to a pre-estimated set of motion vectors. The main drawback of DP is the mismatched transformed search area formed from different consecutive transformed blocks which would lead to inaccurate ME. In this paper, efficient area and high speed Manipulation Unit Engine (MUE) is proposed, a main module of DP-FD-ME system, to forge a matched transformed search area from successive transformed blocks. Implementation results nominate the proposed MUE architecture to those multimedia applications that favors reducing both area and power consumption. Simulation results project that MUE, when integrated in a whole FD-ME system, can perform ME for 60 fps of 4CIF video at 172 MHZ. For the best of our knowledge, it is the first attempt to address such architecture.
An efficient technique to improve NORA CMOS testing

This paper presents a novel circuit technique to improve the testability of NORA (NO RAce) CMOS circuits. It is based on the structure, properties and operations of NORA CMOS. The precharge and evaluation properties of NORA CMOS enable one to design simple testing circuit for output stuck-at-zero, stuck-at-one, stuck-open and stuck-on faults. Area and time considerations, as well as the applications of this testability enhancement technique are also discussed.
A quadratic residue processor for complex DSP applications

The performance requirements for high speed real-time Digital Signal Processing (DSP) applications, coupled with the hardware complexity for manipulating data over complex fields can often exceed the capacity of the traditional signal processors. In this paper, a signal processor for complex DSP applications has been developed. It is based on using the Quadratic Residue Number System (QRNS) which establishes parallelism on the functional level and optimizes the required hardware. By employing QRNS, the interaction between the real and imaginary channels in complex arithmetic is eliminated, and two real multiplications are only required to perform complex multiplication. The processor design is optimised for efficient computation of the FFT and signal processing operations based on FFT such as FIR filtering, IFFT, convolution, correlation, and multiplication. This computational versatility is achieved through macroprogrammability. FIFO's (First-in First-out) are used for storing the input, intermediate, and output data (and coefficients). Customized look-up tables are employed for implementing the residue operations. The developed processor can be employed either as a stand-alone processor or as a peripheral processor (Co-processor).
Wireless sensor networks: the product of a marriage made in heaven

Computers, communication and sensing technologies are converging to change the way we live, interact, and conduct business. Wireless Sensor networks reflect such convergence. These networks are based on collaborative efforts of a large number of sensor nodes. They should be low-cost, low-power, and multifunction. These nodes have the capabilities of sensing, data processing, and communicating. Sensor networks have wide range of applications, from monitoring sensors in industrial facilities to control and management of energy applications to military and security fields. Because of the special features of sensor networks, new network technologies; communication and protocol, are needed for cost effective, low power, and reliable communication. These network protocols and architectures should take into consideration the special features of sensor networks such as the large number of nodes, their failure rate, limited power, high density, etc. In this talk the impact of wireless sensor networks will be addressed, several of the design and communication issues will be discussed, and a case study of a current project of using such networks in drilling and management off-shore oil will be given.
Affine schemes in mesh-based video motion compensation

We evaluate the performances of different implementations of affine transform in a motion compensation architecture based on a hierarchical adaptive structured mesh. The architecture predicts the next video frame using the reference frame, mesh code and mesh node motion vectors. It achieves significant reduction in describing the mesh topology by coding the splitting in recursive triangulation of the initial coarse geometry. It uses a memory serialization unit and one simple warping unit to map the hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. We compare shift-after-difference (SAD), lookup table (LUT) and naive implementations of the affine unit. Computing the affine transform using the multiplication-free SAD algorithm significantly reduces the complexity of the architecture. We establish from simulation results that our multiplication-free SAD affine computation requires far less power and area than other schemes. We discuss the limitations and advantages of different motion compensation schemes. Performance analysis shows that this scheme is suitable for video applications like MPEG and VRML.
A data merging technique for high-speed low-power multiply accumulate units

In an attempt to meet the low-power requirements of high performance portable signal processing VLSI systems, while maintaining a high operating speed, a new data merging architecture for high-speed multiply accumulate units is proposed. The architecture can be applied on binary trees constructed using 4:2 compressor circuits. Increasing the speed of operation is achieved by taking advantage of the available free input lines of the compressor circuits, which result from the natural parallelogram shape of the generated partial products and using the bits of the accumulated value to fill in these gaps. This results in merging the accumulation operation within the multiplication process.
Testing of a NORA CMOS serial-parallel multiplier

The NORA-CMOS (no-race complementary metal-oxide-silicon) serial-parallel multiplier presented here is testable. Error detection is achieved at two levels: online functional testing and offline structural testing. Functional testing uses low-cost residue codes to detect errors at the overall level. Modulus is adopted as the check base. For structural testing, a NORA CMOS circuit error detection technique proposed based on the structure, properties, and operations of NORA CMOS is used. The proposed technique can detect output stuck-at, stuck-open, and stuck-on faults. Such a two-level testing strategy reduces test time and chip area overhead, identifies faulty locations, and has the ability to detect both transient and permanent faults.
Methodologies for binding function units for low power in high level synthesis

This work considers binding of function units, operating at multiple voltages, in a post-scheduling scenario. The main aim is to minimize the power consumption due to switching activities on the physical adders and multipliers etc. To achieve this, switching activities on the function units are gathered through profiling the data-flow graph of the design by employing random input patterns. The problem of binding is then transformed into a graph-theory problem and solved for optimization of power consumption. Two approaches are considered in this work: a greedy approach, and an optimal approach. Cases are considered when all the resources are operating at the same voltage, as well as, when resources are operating at possibly different voltages. This is the first reported work on binding in a post-scheduling phase when the resources are operating at multiple voltages.
Decentralized clustering in VANET using adaptive resonance theory

Nowadays VANETs are becoming a dominating technology in automotive industries where vehicles communicate with each other to deliver safety messages or any type of information to other vehicles. However, the increasing numbers of vehicles on the roads poses a challenge on designing an efficient communication protocol for VANETs. The scalability issue in VANETs has a deteriorating effect on latency and on the stability of the network. Clustering is one technique used for solving this issue. In this work, we propose a clustering technique that creates mini clusters that are in the same communication range of the vehicles with the help of Adaptive resonance theory (ART). These mini clusters are created based on speed where it categorizes the vehicle in one of three levels: high, medium or low speeds. ART is an unsupervised neural network model that classifies inputs based on the degree of similarities of the input. By carefully tuning ART, three clusters are always obtained corresponding to the above speed classifications. The proposed work was simulated and compared against traditional clustering methods where our work presented a 50% advantage over these techniques.
Design and Realization of Analog Phi-Function for LDPC Decoder

One of the ambitious design goals of future generations of wireless systems, including 4G, IEEE 802.11n/802.16 standards, is to reliably provide very high data rate transmission in real-time. This poses a challenge to find an optimal coding scheme that has good performance and can be efficiently implemented in hardware. The most well-known LDPC decoding algorithm is log sum product (log-SP) in which a set of calculations on a non-linear function called Phi-function is approximated by a minimum function. Until now this function has been implemented through look up tables (LUT). But this direct implementation is costly for hardware. Also LUTs are very sensitive to the number of quantization bits and number of LUT values. Therefore, we have proposed analog Phi-function. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed design dissipates only 18 nW.
A novel technique for noise-tolerance in dynamic circuits

Noise issues in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption issues due to aggressive scaling trends in devices and interconnections. An attempt has been made to address this problem in this paper. A new technique to make dynamic CMOS circuits noise tolerant has been proposed by the authors. Simulation results for a dynamic-CMOS NAND gate and a dynamic-CMOS 1-bit full-adder circuit show that the proposed technique has an improvement in ANTE of 6.0X over conventional dynamic logic. The proposed technique, in comparison with the twin transistor technique, proves to improve ANTE by 2.8X. There is a large power dissipation incurred during the evaluation period for certain input combinations.
Symbolic execution using approximate computing (SEAC) — A novel branch hazard distribution method

To improve the overall performance of computer systems, instruction-level parallelism (ILP) has been widely exploited. However, branch hazards, conditional and unconditional, still limit the efficiency of most ILP techniques. Compiler techniques such as loop unrolling, software pipelining, and trace scheduling are being used to increase the amount of parallelism available in systems with fairly predictable branches, while predicated instructions have been useful in eliminating branch hazards in specific cases. The limitations imposed on ILP by branch hazards, however, are significant in large blocks of codes or, at best, hidden at the expense of processor resources. As a result, researchers are exploring the techniques of approximate computing, which when applied, would be suitable for only fault-tolerant systems. Some are also working on the methods of code approximation, which mainly involves hazard minimization by distribution over specific parts of code segments. In this work, we propose and demonstrate a novel branch hazard distribution technique — Symbolic Execution using Approximate Computing (SEAC). We applied the proposed technique to a test program and ran simulation experiments using the Detailed CPU model in gem5 simulator. Simulation results show that SEAC is 3.57, 1.95 and 1.32 times better than the best, among the tested conventional ILP techniques, based on speedup, energy saving, and branch hazard distribution coefficient respectively.
SoC interconnect in deep submicron

The migration to using ultra deep-submicron (UDSM) processes of 0.25 /spl mu/m or below has enabled the integration of complete electronic systems onto one single chip. These systems-on-chip (SoCs) introduce various challenges in terms of design flows and CAD tools. A design methodology that allows component reuse and intellectual property is necessary for achieving the required functionality, performance and testability while minimizing the cost and time to market. This design methodology relies on the use of a standardized connection interface like a shared bus, which presents increasing difficulties in SoC. This paper describes research directions and various levels of design abstraction to increase the performance of interconnects. These directions include approaches to adopt new analytical models for interconnects and ways to face these challenges early in the design flow. To maximize the benefits of this paper, an extensive set of references is given.
Design of a 24 GHz ultra low power current reused CMOS LNA in subthreshold region

This paper presents a single-stage ultra-low power low voltage low noise amplifier (LNA) at 24 GHz in commercially available CMOS technology in 90 nm. The LNA has been implemented by using current reused technique with operation biased in subthreshold region to reduce power consumption. The state of art LNA in this work achieves 10 dB power gain (S21), 1.2 dB noise figure (NF), and input-referred third-order intercept point (IIP3) of 12 dB. It consumes significantly low power of only 160 uW from very low voltage power supply of 0.55 V and DC current of 287 uA at 24 GHz.
A low-power clock frequency multiplier

A low-power output feedback controlled frequency multiplier is proposed for delay locked loop (DLL) based clock synthesizers. It uses N voltage controlled delay lines (VCDL) to multiply the input clock frequency by a factor of N/2. This frequency multiplier is less susceptible to jitter-accumulation. The proposed circuit can operate at a substantially low supply voltage. Simulation results show that the proposed frequency multiplier dissipates about 27% to 36% less power than other similar circuits. In addition, the proposed circuit can be easily programmed for generating various output clock frequencies
Block computation architectures for 2-D discrete wavelet transforms

In this paper, we will introduce two coarse-grained architectures for the block computations of 2-D separable DWT. Parallel-sequential architecture shows an improvement in computational complexity by a factor of JK, where J is the octave requirement and K is the filter size, when compared to sequential architecture. The parallel-parallel architecture has a computational complexity of O(N). Both architectures are scalable for different filter sizes and octave levels.
A novel architecture for low-power design of parallel multipliers

In this paper, a new architecture for low-power design of parallel multipliers is proposed. Reduction of power consumption is achieved by reducing the circuit activity at the architecture level by dividing the multiplication circuit into clusters of smaller multipliers. By applying clock gating techniques and preprocessing operations on the input pattern using simple logic functions, some of these clusters that are producing a zero result can be disabled and hence saving the switching power component that could be consumed by these clusters. The amount of power savings is dependent on the nature of the input pattern, which varies according to the application. Analysis of the input pattern is performed. For testing purposes, A 8-bit multiplier prototype is constructed in 0.35 micron double metal CMOS technology using Cadence development tools. For the average case when all the input combinations have an equal probability of occurrence, HSPICE simulation results at 3.3 V and 500 MHz frequency show that the proposed architecture results in 13.4% power savings.
On Through Silicon Vias as used in three dimensional integrated circuits

This paper presents a survey of 3D Integrated Circuits using Through Silicon Vias (TSV). 3D Integrated Circuits and the TSV will be defined, the rationale for moving to these systems will be given, and an overview of the construction of the 3D Integrated Circuit and TSV will be presented. Lastly, the challenges for 3D Integrated Circuits using TSVs will be discussed.