nils-herrmann/clean_scirepeval huggingface dataset:
GP based transistor sizing for optimal design of nanoscale CMOS inverter

This paper proposes a simple method to formulate the transistor sizing problem as a geometric program (GP) by using a modified I-V model which performs well up to 10 nm. The geometric program model for dynamic power delay product (PDP) expression has been formulated by using the modified I-V model for nanoscale CMOS inverter. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (250 nm) results. Further the approach has been extended to predict the transistor sizing for nanoscale (up to 50 nm) CMOS inverter and the simulation results of the proposed model are compared with the Berkeley Predictive Technology Model (BPTM) to establish the usefulness of the approach.
500 MHz differential latched current comparator for calibration of current steering DAC

This paper proposes the design techniques of high performance current comparator which can sense a minimum change of 8 nA for 10 μA input current. The current comparator shows fast response with 0.95 ns delay for an input current difference of 0.1 μA peak-to-peak and it can work up to 500 MHz clock frequency. The use of low impedance trans-impedance stage makes it faster and the preamplifier removes kickback noise. Using latch at the end of comparator provides a faster response. The dynamic comparator is pre-charged to VDD during low clock phase to remove the memory effects. The current comparator has been designed in 180 nm CMOS process with 1.8 V supply. The comparator shows an average power consumption of 697 μW for 10 μA input current.
Pipelined DSP implementation of nonlinear anisotropic diffusion for speckle reduction of USG images

In this paper a real time approach to reduce speckle noise and enhance structures in speckle corrupted ultrasound image is proposed. It utilizes nonlinear anisotropic diffusion for speckle removal and edge enhancement. Unlike the conventional anisotropic diffusion performed in four different directions, here diffusion is performed in eight different directions. The algorithm has been proficiently implemented using a low cost Texas Instruments (TI) Digital Signal Processor (DSP) of series TMS320C64x+. The approach speeds up the computation by utilizing the ability of Very Long Instruction Word (VLIW) processor to perform multiple operations in parallel. In addition, a new feature to select a Speckle Reduction Imaging (SRI) mode is introduced which facilitates different degree of smoothing depending on the requirement. The experimental results show that with an speckled input image of size 640 × 480 the algorithm is capable of supporting 105 frames per second (fps). This method also promises better image quality than window based filtering techniques [1]–[4].
A less computation intensive non-rigid image registration by modifying demons deformation algorithm

Image registration is the process of aligning two images of different modalities or images acquired at different times using the same modality. Minimization of the alignment error with less computation is a challenging task especially in a medical imaging system. To deform the image for alignment with reference image, the Demons deformation algorithm has been used extensively. This paper presents some modification in Demons deformation algorithm which helps to reduce alignment error as well as runtime by 25% and 33% respectively.
Regularized least squares regression for calibration of a photoacoustic spectroscopy based non-invasive glucose monitoring system

Near infra red photoacoustic measurements can be used to estimate blood glucose concentration in a non-invasive manner. A multi-wavelength photoacoustic measurement apparatus operating at 905 nm and 1550 nm is used to obtain measurements from glucose solutions with concentration in the physiological blood glucose range (0-500 mg/dl). Amplitude and area based features computed from photoacoustic measurements at both wavelengths are calibrated to obtain the glucose concentration. A Mean Absolute Difference (MAD) of 14.95 mg/dl (0.83 mmol/l), Mean Absolute Relative Difference (MARD) of 8.94 % and a Root Mean Square Error of Prediction (RMSEP) of 18.39 mg/dl (1.02 mmol/l) is obtained using regularised least squares regression. This performance is comparable to other non-invasive measurement methods and can be improved upon to realize a fully non-invasive glucose monitoring system.
Modified Demons deformation algorithm for non-rigid image registration

Image registration is a technique used for aligning two different images taken at different times and/or from different viewing and different imaging setups/modalities. A key challenge for medical image registration is to minimize computation time and reduce alignment errors. The Demons deformation algorithm has been used extensively for deformation medical images for image registration. In this paper we present modifications to Demons deformation algorithm that reduce runtime while giving good deformation.
Motion estimation in medical video sequences using affine transform

Motion estimation is an important task in the video encoding process. This plays an important role for high definition television (HDTV) and internet broadcasting as well as in medical imaging system like dynamic MRI. Accurate estimation of the predicted frame is required in dynamic MRI. The block search method is very easy to implement, but it estimates very poorly if complex motion is present in the frame sequences. In this paper, we present a new affine based motion estimation method which can be used for medical video processing. The proposed method provides sufficient parallelism in the implementation while giving good result in terms of motion estimation.
Efficient Hardware Implementation of Encoder and Decoder for Golay Code

This brief lays out cyclic redundancy check-based encoding scheme and presents an efficient implementation of the encoding algorithm in field programmable gate array (FPGA) prototype for both the binary Golay code (G23) and extended binary Golay code (G24). High speed with low-latency architecture has been designed and implemented in Virtex-4 FPGA for Golay encoder without incorporating linear feedback shift register. This brief also presents an optimized and low-complexity decoding architecture for extended binary Golay code (24, 12, 8) based on an incomplete maximum likelihood decoding scheme. The proposed architecture for decoder occupies less area and has lower latency than some of the recent work published in this area. The encoder module runs at 238.575 MHz, while the proposed architecture for decoder has an operating clock frequency of 195.028 MHz. The proposed hardware modules may be a good candidate for forward error correction in communication link, which demands a high-speed system.
Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid

This paper describes a new radix based calibration technique for pipelined analog-to-digital converters (ADCs). The proposed technique uses sinusoidal signal sampled at Nyquist rate to mitigate the effects of capacitor mismatch and finite op amp gain error that degrade the performance of a typical pipelined ADC. The calibration has been illustrated using a 1.5-bit per stage non-flipover topology. This technique is promising compared to the existing foreground calibration algorithms as it requires sinusoidal input which is easily available. Since this technique does the calibration at Nyquist rate it captures the finite op amp settling effect, which no other foreground calibration technique does. Behavioral simulations for a 12-bit pipelined ADC which has 11, 1.5-bit stages followed by 2-bit flash, validate the calibration technique.
Low-cost, high-performance VLSI design of an MQ coder for JPEG 2000

Embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. In this algorithm, output generated by the bit plane coder (BPC) is supplied to an MQ coder. Though several high speed BPC architectures are available, overall performance EBCOT algorithm is getting restricted by the speed of an MQ coder. Therefore, we propose a high speed, area efficient VLSI architecture for an MQ coder. This pipelined design is implemented on Startix series FPGA and it operates at 153 MHz. The synthesis report demonstrates that as compared to existing designs, the requirement of logic- and memory-elements is reduced by about 71.53% and 59.3%, respectively. Throughput of the proposed MQ coder is 137.7 MS/s which is 1.85 times higher compared to the designs reported. The renormalization module is capable of operating at 326 MHz. So, coding efficiency can further be improved by using multiple clock domains.
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier

A fully differential CMOS sample and hold amplifier SHA) is described here.The circuit is designed as a front end sampler of a low-power, high-speed analog to digital converter. The SHA uses double-sampling technique to achieve high speed with reasonably low power consumption. Using 0.18oc CMOS technology, a resolution of 9 bit has been achieved at a sampling rate of 400 MHz. Also, to acquire superior linearity, boot-strapping technique has been used while implementing the switches and to reduce clock feed through, concept of bottom plate sampling has been utilized. Using a supply voltage of 1.8 V and a signal swing of 0.6Vpp the circuit consumes approximately 10 mW of power.
ASIC implementation of a 512-point FFT/IFFT processor for 2D CT image reconstruction algorithm

The CT scan medical imaging requires huge amount of computations for reconstructing the images. Modified Fast Radon Transform (MFRT) uses FFT based parallel algorithm for reconstruction of 2D/3D CT images from its sonogram data using convolution operation by concurrent 1D FFT/IFFT and matrix multiplications. To achieve optimum hardware utilization with low power consumption an FFT module, based on iterative radix-2 decimation in frequency (DIF) algorithm, has been designed and implemented. The module has been designed in such way so that it can also be used for IFFT computation only by changing a single parameter. To compute the FFT, the twiddle factor has been calculated using Coordinate Rotation Digital Computer (CORDIC), by steering the data properly in the butterfly structure. The synthesized frequency of FFT/IFFT module is 220 MHz and gate count is 1,040,136 using 130 nm faraday digital libraries. The power has been analyzed using prime power and the value of the power consumption is 15mW. The designed FFT/IFFT ASIC chip is very much suitable for low-area and low power biomedical applications like CT image reconstruction, Doppler wave spectrogram etc.
A new approach to analyze a sub-micron CMOS inverter

An analytical model is proposed for submicron CMOS devices based on Thornber's scaling law where the field dependent mobility and carrier velocity saturation are treated independently. Comparison of simulated results with the experimental results of I/spl sim/V data for sub and deep sub micrometer MOSFETs down to 0.09 /spl mu/m effective gate length demonstrates the accuracy of the model. A sub micron CMOS (0.2 /spl mu/m technology) inverter is analyzed by using the proposed model. Results show that the calculated propagation delay and output voltage waveform are in good agreement with Spectre simulation results.
Unified CORDIC-based chip to realise DFT/DHT/DCT/DST

Frequency analysis using the DFT, the DHT, the DCT or the DST is an obvious choice for the entire image and signal processing domain. A chip has been designed to obtain a unified architecture for the DFT/DHT/DCT/DST called DXT. For the low-power budget of many signal processing requirements, e.g. biomedical signal processing, a parallel and pipelined architecture is adopted for the unified design. The parallelism environment provides a real-time and low-power application of biomedical and other signal processing requirements, whereas the pipelined structure ensures high throughput of the design. The DXT architecture uses a CORDIC unit as the basic processing element. The UMC library (europractice) of 0.25 micron CMOS technology has been used to obtain a DXT chip of transform length ‘7’ for the synchronous design. The total dynamic power was found to be 204.89 mW, with an operating frequency of 160 MHz and an operating voltage of 2.5 V.
Analysis of temperature dependence of Si-Ge HBT

In this paper the dependence of characteristics of SiGe heterojunction bipolar transistors on Ge mole-fraction and also variation of gain with temperature are presented. The simulation is carried out using a two dimensional device simulator, BISOF, based on finite element method. It is observed that the current gain of graded HBT improves when the temperature falls from 300 K to 200 K which matches well with the available experimental results.
VLSI architecture for IEEE single precision floating point moving average calculator

Moving average is largely used in various image and signal processing applications. Direct calculation of moving average requires a large number of additions which depends upon the segment length. A moving average calculation method which calculates the moving average by updating the previous moving average output with the help of two subtractions regardless the segment length is widely used. This method can be implemented in fixed point arithmetic by using two subtractors and a divider. But, this method cannot be implemented for IEEE floating point arithmetic directly as floating point adder/subtractor have the latency more than one clock cycle. In this paper, a reformed moving average method for implementing it in the IEEE floating point format is proposed. A resource-optimized architecture of the proposed method is also given in the paper. The proposed architecture is synthesized in Xilinx FPGA XC4VLX100 (Virtex 4). It occupies 2785 slices and the maximum operating frequency is found to be 353.107 MHz.
A 10-bit 500 MSPS segmented DAC with distributed octal biasing scheme

The effect of bias node voltage fluctuations on the performance of the current steering (CS) DAC is studied in this work. For that purpose a 10-bit segmented CS-DAC has been designed in 0.18 μm CMOS n-well technology provided by National Semiconductor. All current sources connected to the same bias cell act as correlated noise sources and generates more nonlinearity at the output. To improve the spurious free dynamic range (SFDR) of the DAC a new octal biasing technique is used in this paper. In the octal biasing technique 8-bias cells are used and they are placed in a 4×2 array structure. There is no direct connection between any two bias cells and they are considered as non-correlated cells. Thus the octal biasing and the non-correlated current sources help to reduce the noise and the input code dependent nonlinearities at the output. In Monte Carlo mismatch simulation the proposed DAC achieves 60.83 dB SFDR for 15.136 MHz signal at 500 MSPS sampling rate. The DAC shows a Nyquist SFDR of 60.57 dB in for 500 MSPS sampling rate. The DAC consumes only 31.62 mW of power at Nyquist signal frequency for 500 MSPS sampling rate with 1.8 v supply.
Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter

This paper proposes a low-power, high-speed architecture of a reconfigurable root-raised cosine (RRC) filter which serves as a major component of a digital up converter (DUC). The proposed RRC filter can be reconfigured at any time to suit one of three different interpolation factors and one of two different roll-off factors pertaining to various modern wireless communication standards. The fact that the design is multiplexer-based has ensured reduction in power consumption. In addition, transposed direct form II realization of the RRC filter has enabled maximum operating frequency by placing a set of registers at proper locations of the data path. Power consumption of an FPGA implementation of the proposed filter has been found to be about 234 mW at 50 MHz clock frequency. However, the designed filter is capable of operating at a maximum clock frequency of 229 MHz on XC2VP30 FPGA devices while requiring only 7K gates. Significant reduction in area and power of the proposed RRC filter makes it very suitable for an area critical power efficient reconfigurable multi-standard DUC.
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm

Increasing demand of high-speed portable modules for multimedia applications has motivated the development of hardware-based solutions for image processing applications. Most of the nonrigid image registration algorithms are found to be unsuitable for hardware implementation because of their nonlinearity and computationally intensive nature. In this paper, an algorithm for nonrigid image registration based on Demons approximation is proposed. The algorithm has been simulated in MATLAB and results show a 15% improvement in peak-signal-to-noise-ratio with a 17% reduction in registration time for 256 × 256 image over the original Demons algorithm. The proposed algorithm is synthesized in Virtex6-xc6vlx760-2-ff1760 and maximum synthesized frequency is found to be 174 MHz. The proposed architecture provides the low cost, high-speed solution for the registration process, which is also helpful for making a portable system.
Modified Frei-Chen Operator-Based Infrared and Visible Sensor Image Fusion for Real-Time Applications

Real-time fusion of images acquired from multiple sensors is significant in various fields, including military and aviation, to reduce the uncertainty in the acquired images and for wider temporal and spatial coverage. Current approaches to multi-sensor image fusion have a high computational complexity and difficult to implement in hardware. This paper presents a method based on two-scale decomposition and modified Frie-Chen operators to fuse images acquired from infrared and visible image sensors and its corresponding hardware implementation. The proposed method achieves 48%, 15%, and 100% improvements in total edge transfers, structural similarity, and night vision contrast, respectively, with respect to those of the latest publications known to the authors. The corresponding hardware architecture, synthesized using the Xilinx tool, is shown to consume 4% of the resources in the Virtex 4 field programmable gate array (FPGA-xc4vlx200). The proposed architecture has one unit of throughput per clock cycle and is able to process 30 high definition images/sec. The proposed architecture is also analyzed using the synopsis design vision tool with the 90-nm UMC standard complementary metal–oxide–semiconductor cell library. It is found that the architecture consumes 251.6 mW of power and has an area equivalent to 580K NAND2 gates. The lower hardware resource requirement and support of parallelism and pipelining make the proposed algorithm suitable for low-power, real-time image fusion applications.
Low power architecture of running 3-D wavelet transform for medical imaging application

In this paper a real-time 3-D DWT algorithm and its architecture realization is proposed. Reduced buffer and low wait-time are the salient features which makes it fit for bidirectional videoconferencing applications mostly in real-time biomedical applications. The proposed algorithm updates the coefficients in the temporal direction with every two new frames. In the architectural implementation, the memory requirement is minimal due to low buffering requirement. The reduced hardware complexity and 100% hardware utilization is ensured in this design. Time area product for the spatial DWT is 1.5 at. This architecture implemented on 0.25 /spl mu/ BiCMOS technology. At a operating frequency of 100 MHz the power consumption is appreciably lower compared to those reported.
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.
Computation of two N-point IDCT s via a single N-point IFFT using radix-4 algorithm & its proposed architecture

This paper addresses the problem of the evaluation of inverse discrete cosine transform (IDCT) using existing radix-2 IFFT algorithm applicable for image and signal processing where a huge number of data points are required for a particular operation. Since radix-4 architecture has fewer multiplications than radix-2, then it is judicial to carry out the IDCT operation via radix-4 IFFT for a huge savings of number of computations for the data points which are power of four. In this paper the authors have modified the existing IDCT-DFT algorithm to allow the computation of two concurrent N Point IDCT s via a single N point radix-4 IFFT instead of using radix-2 IFFT. As a result the total amount of arithmetic workload is greatly reduced. A supporting architecture which can be applicable for real time operation is also suggested to realize a 16 point IDCT algorithm.
An array architecture for fast computation of discrete Hartley transform

Fast computation of the discrete Hartley transform (DHT) may be performed by employing a set of linear arrays of Givens rotors. It is shown that the interconnections between the linear arrays can be realized in a regular fashion governed by a permutation cycle that can be determined by simple arithmetic involving a primitive root of the transform length. A suitable implementation of the Givens rotor with add/subtract units and hard-wired shifters is also suggested.