nils-herrmann/clean_scirepeval huggingface dataset:
An efficient array architecture with data-rings for 3-step hierarchical search block matching algorithm

This paper describes an efficient 9-cells array architecture with data-rings for the 3-step hierarchical search block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify the control scheme and reduce latency, respectively. In addition, we utilize a three-half-search-area scheme to reduce external memory access and interconnection. The results demonstrate that the array architecture with the data-rings gives short latency and low input ports. It also provides a high normalized throughput solution for the 3SHS.
An exploration of on-road vehicle detection using hierarchical scaling schemes

This paper targets at detecting preceding vehicles in a wide range of distance. We propose an Adaboost-based approach combined with hierarchical image and sub-window scaling schemes. The relationship is investigated among object characteristics, image structures and image scales. A parameter set is developed to easily adjust overall performance, which benefits researchers to establish a vehicle detection system. It achieves 96.6% detection rate with 2.0% false alarm rate along proposed methodology. The benchmark of several learning-based vehicle detection approaches is also provided. The results show the outperformance of the proposed method.
A real-time 1080p 2D-to-3D video conversion system

In this paper, we demonstrate a 2D-to-3D video conversion system capable of real-time 1920×1080p conversion. The proposed system generates 3D depth information by fusing cues from edge feature-based global scene depth gradient and texture-based local depth refinement. By combining the global depth gradient and local depth refinement, generated 3D images have comfortable and vivid quality, and algorithm has very low computational complexity. Software is based on a system with a multi-core CPU and a GPU. To optimize performance, we use several techniques including unified streaming dataflow, multi-thread schedule synchronization, and GPU acceleration for depth image-based rendering (DIBR). With proposed method, real-time 1920×1080p 2Dto- 3D video conversion running at 30fps is then achieved.
A spatial first 3-D XYT feature point extraction algorithm for efficient human action recognition

In this paper, we present a novel method of 3-D XYT feature extraction for efficient human action recognition. We propose the spatial first 3D feature extraction method to reduce the computation time and data bandwidth compared with Harris 3D corner detection. We also present experimental results through the proposed spatial first feature extraction to reach 83.33% accuracy of human action recognition through KTH dataset. Finally, we demonstrate the 67.8% computation time and 66.7% bandwidth reduction for the efficient human action recognition system.
Design and implementation of JPEG encoder IP core

A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-/spl mu/m single-poly triple-metal process. It can run up to 40 MHz at 3.3 V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc.
A novel architecture of inverse quantization and multichannel processing for MPEG-2 audio decoding

An MPEG-2 audio decoding processor core is described with a focus on inverse quantization (IQ) and multichannel processing (MC) of Layer I and II decoding. A novel architecture that we propose can perform IQ at a high throughput. In addition, different types of dematrixing modes for MC process in the MPEG-2 standard can also be performed. The processor core is implemented and controlled with a dedicated hardware approach instead of the traditional programmable techniques. Moreover, the design has the advantages of simplicity and low cost while meeting the high-efficiency requirements with a fixed throughput.
A LOG-EXP still image compression chip design

In this paper, a fully pipelined single chip is proposed for LOG-EXP still image compression. The design of the LOG-EXP image compression focuses on the high compression ratio of a complex texture (e.g. benchmark image baboon) and high quality image, especially the PSNR requirement above 36. In comparison with the JPEG compression result (bpp=0.99, PSNR=26.9), this compression algorithm uses less bpp (bpp=0.87) to get a higher image quality (PSNR=36.38) for the benchmark image baboon. The entire LOG-EXP image compression system can be implemented on a single chip to yield a clock rate of 175 MHz which allow an input rate of 30 frames per second for 1024/spl times/1024 color images.
Region-of-unpredictable determination for accelerated full-frame feature generation in video sequences

In this paper, we propose a novel concept of region-of-unpredictable (ROU) to accelerate full-frame feature generation in video sequences. Due to the high correlation between successive frames, there are only few regions in which the features could not be estimated accurately from the previous frame called region-of-unpredictable (ROU). We develop a scheme combining partial feature extraction in ROU with feature prediction from the previous frame. The full-frame features of the current frame can then be obtained to minimize information loss. Experimental results show that the ROU determination algorithm supports 95.71% detection rate. The full-frame feature generation scheme using ROU determination saves 79.38% computational time compared with the full-frame feature extraction.
A Localized Approach to Abandoned Luggage Detection with Foreground-Mask Sampling

In this paper we propose a novel approach to the detection of abandoned luggage in video surveillance. Candidates of abandoned luggage items which may pose potential security threats are first identified and localized by our proposed foreground-mask sampling technique. Our approach can deal with luggage pieces of arbitrary shape and color without the need for prior learning, and it works well under crowded and highly-cluttered situations. This localization of suspicious luggage items in the scene enables us to focus attention and subsequent processing solely on their neighborhoods. The owner of the luggage is then located and tracked to determine whether or not the luggage has been abandoned deliberately. A probability model using the MAP principle is employed to calculate a posteriori confidence score for the luggage-abandonment event, and an alarm will be automatically triggered if the certainty of luggage abandonment is higher than a pre-defined threshold. We show our results on the video datasets provided by the 2007 IEEE International Conference on Advanced Video and Signal based Surveillance (AVSS 2007) and the 2006 PETS 2006).
Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension

In addition to coding efficiency, the scalable extension of H.264/AVC provides good functionality for the adaptation in heterogeneous environments. Fine grain scalability (FGS) is a technique to extract video at the best quality level under the available bandwidth. In this paper, an architecture of FGS encoder with low external memory bandwidth and low hardware costs is developed. At most 92% bandwidth reduction can be attained by the proposed scan bucket algorithm, early context modeling with context reduction, and first scan pre-encoding. The area-efficient architecture is implemented by layer-wise hardware reuse, and three design strategies for enhancement layer coder are explored so that the trade-off between external memory bandwidth and silicon area is allowed. This design can real-time encode HDTV 1280×720 video at 130 MHz working frequency.
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications

Depth information has become essential in emerging computer vision applications. Although active sensing methods can provide an accurate indoor depth map, they have limited resolution and consume significant power, such as the 2.1W time-of-flight sensor in . In contrast, depth estimation for stereo RGB images can provide high-resolution depth maps, even in outdoor or low-power scenarios. And, the depth accuracy can be increased by using multi-view light-field images. This paper presents an integrated circuit which estimates full HD (1920×1080) depth maps at 30fps and provides a tradeoff between depth accuracy and power consumption based on two-/three-/five-view stereo images. It addresses design challenges with three primary contributions: 1) a stripe buffering scheme which is designed to reduce the DRAM bandwidth induced by multi-view image access; 2) a four-bank interleaving architecture, which boosts computation performance by parallelizing belief-propagation (BP) operations; and, 3) an adaptive view selection unit, which realizes the accuracy-power tradeoff.
A flexible data-interlacing architecture for full-search block-matching algorithm

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm.
An efficient visual pattern block truncation coding

This paper presents a new practical image coding system, visual pattern block truncation coding (VPBTC). The first idea of this new algorithm is the application of block truncation coding (BTC), which encodes an original image and obtains a bitmap. This bitmap is applied to computing the block gradient orientation and matching the block pattern. Another refinement is that the classification of blocks are based on properties of human visual perception. Blocks are classified into two types: uniform blocks and edge blocks. Not only can VPBTC remove the drawbacks of BTC (e.g. higher bit rate) but also can it repair the defects of VPIC (e.g. mismatching pattern). Four benchmarks prove that the MSE of this algorithm is less than that of VPIC by 37%. Its bitrate, furthermore, is about 60% of BTC's. The advantages of this coding method are fine edge preservation, low computational complexity, and easy implementation.
Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications

This paper proposes a practical content-dependent low-power DCT design with tolerable quality drop. Low-power issue has become more and more important, especially for portable devices. Unfortunately, low-power design always brings in significant quality drop at the same time. This work not only achieves ultra low power dissipation but also remains tolerable quality drop (about 0.1 dB) in most cases. The proposed architecture is based on distributed arithmetic architecture [A. Peled et. al., (1974)] and combined with more reliable PPA classification algorithm [T. Xanthopoulos et. al., (2000)]. It can accurately control bit-level calculation and avoid unnecessary calculation to save power. This characteristic is powerful and very useful in video encoder systems, since coefficients after DCT and Q become zero with high probability. This part of power can be saved without causing undesired quality drop
Using a region-based blurring method and bits reallocation to enhance quality on face region in very low bitrate video

A region-based blurring algorithm to reduce bitrate in very low bitrate video coding is proposed. This algorithm reduces the bitrate by passing the original background image through a filter before motion estimation. Each frame in original sequence will be segmented into foreground and background at first. The background part, which is of less importance for human vision, will be blurred through a blurring filter, while the foreground is kept unchanged. The bitrate for head-and-shoulder type sequences can achieve 5%/spl sim/20% bitrate saving by this blurring algorithm. According to the human vision model, PSNR degradation in the background is not evident. Using this blurring algorithm, but keeping the coded bitstream at the same bitrate as the original sequence, about 0.5/spl sim/1 dB gain in the foreground can be achieved due to bits reallocation between foreground and background.
A novel scalable architecture with memory interleaving organization for full search block-matching algorithm

This paper describes a high-throughput scalable architecture for full-search block-matching algorithm (FSBMA). The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. By use of the efficient PE-rings and the intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Techniques for reducing interconnections and external memory accesses are also presented. Our results demonstrate that the scalable PE-ringed architecture is a flexible and high-performance solution for FSBMA.
Four field local motion compensated de-interlacing

A four field local motion compensated de-interlacing method is proposed to solve the occlusion and true motion vector problems of motion compensated de-interlacing. The proposed de-interlacing method consists of four field motion estimation, 5+5 taps ELA, and intra/MC macroblock mode decision. True motion vectors can be obtained by the four field motion estimation and its matching criterion is extended by the characteristic of interlace-scanned fields. The mode decision could detect an occlusive macroblock and choose its best mode. Hardware implementation has been considered. The results show that the proposed de-interlacing method can produce images compensated by a great majority of the original fields with little intra-field interpolation, and the subjective view results are jag-free and flicker-free high quality images.
Accurate positioning system based on street view recognition

In this paper, an accurate and robust positioning system based on street view recognition is introduced. Vision-based technique is employed for dynamically recognizing shop or building signs on the GPS map. Two mechanisms including view-angle invariant distance estimation and path refinement are proposed for robust and accurate position estimation. Through the combination of visual recognition technique and GPS scale data, the real user location can be accurately inferred. Experimental results demonstrate that the proposed system is reliable and feasible. Compared with 20m error of position estimation provided by the GPS, our system only has 0.97m error estimation.
A depth adaptation system based on perceptual horopter effect

This paper presented a depth adaptation system. At first, the proposed method uses saliency detection algorithm to determine visual attention, and then it applies depth shifting to reduce convergence and accommodation conflict. We also took human perceptual effect into consideration, and proposed an iso-perceptual disparity curve for horopter remapping. By using subjective tests, subjects are asked to score overall preference and comfortable feelings on the stereo images.
Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems

Depth buffer bandwidth minimization with depth filter plays an important role in designing low power graphics processors. In this paper, an efficient adaptive tile depth filter (ATDF) algorithm is proposed. The key concept is to consider more occlusion conditions in order to achieve better performance. Two existing algorithms, Zmax  and Zmax algorithms, are integrated to detect both occluded and non-occluded fragments. Moreover, two new techniques, coverage mask and adaptive tile mode, are proposed to further improve the performance. Experiments show that the proposed algorithm can filter out up to 85% fragments to reduce 40% memory bandwidth for test applications with complex scenes, which outperforms the previous works
Novel Configurable Architecture of ML-Decomposed Binary Arithmetic Encoder for Multimedia Applications

A novel architecture of ML-decomposed binary arithmetic coder is proposed. Through the analysis of previous designs, the traditional processing unit is divided into two parts, MPS encoder and LPS encoder. With different arrangements of these two basic components, we develop two types of ML-decomposed structures. To increase the throughput of arithmetic coding, ML cascade architecture puts the coders in serial, while throughput-selection architecture offers several choices in parallel. Their design methodologies are described in this paper. Both methods achieve very high throughput, more than 800 M symbols/sec. And they are configurable and extensible to supply a wide range of specifications. Moreover, the proposed architecture can be used in binary arithmetic coding of various video and image standards.
Hardware oriented rate control algorithm and implementation for realtime video coding

In this paper, a novel rate control algorithm suitable for real-time video encoding is proposed. The proposed algorithm uses mean absolute error (MAE) results of motion estimation (ME) to achieve bit-rate control. Neither pre-analysis nor multi-pass encoding is required in our algorithm, which makes real-time hardware implementation possible. A new hardware oriented scene change detection method is also included in this rate control framework to achieve better video quality. Experiments show our rate control algorithm behaves well in all situations. The hardware architecture for this algorithm is also described. Implementation shows our proposed algorithm can be efficiently integrated into a low cost, high efficiency video encoder.
Motion adaptive de-interlacing by horizontal motion detection and enhanced ELA processing

A motion adaptive de-interlacing algorithm and its hardware architecture are presented in this paper. It consists of the directional interpolation ELA with median processing, and 4-field horizontal motion detection. The edges can be sharper while the ELA with median processing is adopted. Enhanced ELA with median processing can prevent the happening of the bursting pixels. Proposed 4-field horizontal motion detection discovers faster motion and makes more accurate motion detection. The proposed method achieves hardware considerations on low complexity, low memory usage, and high speed processing. The experimental results show that the image quality of the proposed algorithm is superior to previous systems, and the cost is also more efficient. It is very suitable to be integrated into any display device such as projection TV and Plasma display.
Multi-mode embedded compression codec engine for power-aware video coding system

In a typical multi-chip handheld system for multi-media applications, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 50%, 61%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With Artisan 0.18 /spl mu/m cell library, the proposed EC codec engine can encode or decode at VGA@30fps with area and power consumption of 293,605 /spl mu/m/sup 2/ and 3.36 mW.
Plenary presentation B

Due to the continue driving of the Moore's law, semiconductor technology make the tera-scale integration become possible. With so many transistors in a single chip, many dream applications become possible. Designers are eager to use those tremendous capacity of the integration circuits to bring more intelligent, more smart functions. One of the challenge target is can we design the circuits to make the SOC perform tasks that humans do quickly and easily? Can we make the computer to recognize images, understand language, learn knowledge, and control robots? In this presentation, the concept of Bio-inspiring computing which takes the advantages of neural science will be described. Some previous studies tried to explain the behavior of the human neocortex and provide a framework for building models that could be implemented and executed with Tera-scale SOC. Research suggested that the structure of the neocortex is hierarchical, and that the emulation of 6 levels of hierarchy is sufficient to achieve sophisticated recognition and analysis of visual images. Some experimental results will be presented to demo the possibility. It could be the dawn of the age of intelligence machines and neocortical computing. There will be many opportunities that Tera-scale SOC could create.
Performance analysis of hardware oriented algorithm modifications in H.264

H.264 is initiated by ITU-T as H.26L and will become a joint standard of ITU-T and MPEG. The coding complexity of H.264 is much higher than MPEG-4 simple profile and advance simple profile algorithms. In order to achieve real-time encoding, hardware implementation is required. The original test model of H.264 (JM) is designed to achieve high coding performance. Some algorithms of the test model require lots of operations with little coding efficiency improvement. And some algorithms create data dependencies that prevent parallel hardware accelerations. This paper presents analysis of the H.264 video coding algorithm from a hardware-oriented viewpoint. Intra prediction, Hadamard transform and motion estimation algorithms are reviewed and modified to a hardware friendly configuration. The rate distortion penalties of these modifications are simulated and shown in this paper.