nils-herrmann/clean_scirepeval huggingface dataset:
Region Adaptive R- $\lambda$  Model-Based Rate Control for Depth Maps Coding

In this paper, a novel rate-control algorithm based on the region adaptive R-<inline-formula> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> model is proposed for depth maps coding. First, in order to obtain an accurate rate control for depth maps coding, a modified frame level bit allocation method based on coding bits statistical distribution of depth maps is proposed. Second, considering that different areas in a depth map have an imparity effect on virtual view rendering, the blocks of the depth map are divided into two types, namely, interested blocks for virtual view rending (IBV) and noninterested blocks for virtual view rending (NIBV). Then, two different R-<inline-formula> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> models are derived for IBV and NIBV, respectively. The optimal bitrates for IBV and NIBV are determined by solving an optimization problem. After that, based on the regional R-<inline-formula> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> models, the optimal Lagrange multipliers are calculated for both IBV and NIBV. Finally, the largest coding unit (LCU) level rate control is performed by adaptively adjusting the Lagrange multiplier to avoid blocking artifacts and smooth the quality of coding. Experimental results demonstrate that the proposed method can achieve considerable BD-PSNR gains compared with the unified rate-quantization model and conventional R-<inline-formula> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> model-based algorithms in terms of rendered virtual views quality.
Fast skip mode decision with rate-distortion optimization for High Efficiency Video Coding

In High Efficiency Video Coding (HEVC), the computational complexity has been increased so that an Early SKIP mode decision method is proposed by using coded block flag of an inter prediction unit (PU) to speed up mode decision with BD-bitrate increase. In this paper, we propose a fast SKIP mode decision algorithm to speed up PU mode decision for HEVC in a rate-distortion (RD) optimization sense. It is based on an adaptive linear predictor for PU mode type and available neighboring SKIP mode units on the quad-tree partition structure in HEVC for adaptive RD optimization. Moreover, the proposed method consists of both local (neighboring PUs) and global (previous PUs in current frame) level schemes on each coding unit (CU) level. In this way, it is possible to exploit high correlations between the RD cost of SKIP mode and spatial characteristics of video sequences by using the distribution of SKIP mode and a linear RD cost predictor. Experimental results show that the encoding computational complexity can be reduced by an average of 36 % with threshold RD cost, when compared to that of the HM 12 reference software.
Context Adaptive Lagrange Multiplier (CALM) for Rate-Distortion Optimal Motion Estimation in Video Coding

In this paper, we propose an efficient and practical algorithm to dynamically adapt the Lagrange multipliers for each macroblock based on the context of the neighboring or upper layer blocks to improve rate-distortion performance. Our method improves the accuracy for the detection of true motion vectors as well as the most efficient encoding modes for luma, which are used for deriving the motion vectors, and modes for chroma. Simulation results for H.264/advanced video coding video demonstrate that our method reduces bit rate significantly and achieves peak signal-to-noise ratio gain over those of the joint model (JM) software for all sequences tested, with negligible extra computational cost. The improvement is particularly significant for high motion high-resolution videos. This paper describes our work that led to our Joint Video Team adopted contribution (included in software JM 12.0 onward), collectively known as context adaptive Lagrange multiplier (CALM).
Systolic architectures for artificial neural nets

A novel design of neural networks using a two-dimensional systolic array is proposed. Two techniques are applied in the design, namely, two-dimensional pipelining and multirate processing (two-level clocking). Two-dimensional pipelining operation gives significant improvement in computation time compared to the currently known 1-D and 2-D systolic implementation schemes. Multirate clocking is used so that weights (synapses) can be transmitted and passed systolically at a rate much higher than activation voltages, to achieve maximum array throughput and to eliminate global interconnections present in many arrays (including systolic) designs, thus reducing synchronization and propagation delay problems. This scheme of passing weights also saves area significantly, since local storage area for the weights can be reduced. The design is applied to the implementation of two popular neural networks namely the Hopfield neural network and the back-propagation neural network, which are supposed to be difficult to implement using the proposed scheme because of feedback and multilayer characteristics.<<ETX>>
A bus-monitoring model for MPEG video decoder design

The variety of macroblock types and variable-length codes has increased the difficulty in predicting memory accesses and bus utilization pattern for accessing compressed data or pixels to/from external RAMs during the MPEG video decoding process. In this paper, we present a model and a simulator to aid MPEG decoder design by providing useful statistics related to bus utilization and waiting cycles. The model explores MPEG decoder architecture and data nature; it provides results to analyze bus bandwidth and determine proper sizes of decoder I/O buffers connected to the bus. Simulation is performed to test out different bus arbitration schemes for MP@ML data in MPEG-2 decoding.
Improved content adaptive update weight control in motion-compensated temporal filtering

In this paper, we present a content-adaptive chrominance and motion vector correlation-based update step for scalable video coding. It takes advantage of the chrominance information in the video sequence and the correlation of motion vectors (MVs) of the neighboring blocks as well as the correlation of the derived update MVs in the low-pass frames to improve the update step of lifting-based motion-compensated temporal filtering (MCTF). We further enhance our proposed method via an efficient content adaptive analysis. Experimental results show that the proposed algorithm improves the visual quality of the reconstructed video sequences at different bit rates and resolutions
Object contour tracking using multi-feature fusion based particle filter

In this paper, a novel object contour tracking framework integrating independent multi-feature fusion object rough location and region-based temporal differencing model is proposed. In our model, the object rough location tracking is realized by color histogram and Harris corner features fusion method in particle filter framework. Thus it can achieve more robust tracking performance in many challenge scenes. And this particle filter framework is based on our previous CamShift guided particle filter [7]. With the rough object location, efficient region-based temporal differencing model is adopted for object contour detection, then this method is faster and more effective compared to active contour models or conventional global temporal differencing models. Moreover, exact contour tracking result can be used to guide the particle propagation of next frame, to enable more efficient particle redistributions and reducing particle degeneration. Experimental results demonstrate that this proposed method is simple but effective in object location and contour tracking.
The use of fixed point induction in verifying systolic array designs: an applicative approach

The paper presents our applicative approach of using fixed point induction principle to verify the correctness of systolic array designs. Fixed point induction exploits the repeatable, regular, and local attributes of systolic arrays in realizing recursive functions. The applicative language in denotational semantics improves proof efficiency by skipping the redundant search time and space that occurred in other techniques. Our approach, as well as an example of applying it to prove a systolic array for matrix inversion, are provided in the paper.<<ETX>>
A model parameter and MAD prediction scheme for h.264 macroblock layer rate control

In this paper, we show that inaccurate model parameters degrade performance of R-Q model based rate control, and oscillations of estimated model parameters often occur in the classic quadratic R-Q model based macroblock (MB) layer rate control. To resolve the parameter oscillation problem, we thus propose to use a linear R-Q model rather than the quadratic R-Q model for MB layer rate control and a novel context-adaptive scheme for estimating mean absolute difference (MAD) and parameters for the linear R-Q model. The proposed context is adaptively computed according to local video signal characteristics using a Manhattan distance metric and an improved 2D sliding window method. Extensive experiments show that compared to the H.264 reference JM software, MB layer rate control algorithm using our proposed scheme significantly improves the MAD and model parameters prediction accuracy and bit achievement accuracy, and hence obtains much better rate distortion performance.
Analysis of Structural Characteristics for Quality Assessment of Multiply Distorted Images

Perceptual image quality assessment (IQA) plays an important role in numerous applications, including image restoration, compression, enhancement, and others. Although many works have been conducted on individually distorted IQA problems and have achieved encouraging results, few studies have been conducted on multiple distorted (MD) IQA problems. Thus, limited progress has been made. In this paper, we propose a novel no reference image quality assessment (NR-IQA) method, named improved multiscale local binary pattern (IMLBP), for addressing multiply distorted IQA problems. The image structures are sensitive to image distortions, which motivates us to utilize the structural characteristics for overall image quality prediction. We improved the local binary pattern (LBP) by considering the human visual mechanism to better extract the structural information. The IMLBP contains two parts, the LBP and the radius difference LBP (DLBP). The DLBP reflects the values’ changes in the radial direction. Specifically, when the radius value is small, the proposed descriptor is computed to represent microstructural information. Conversely, it represents macrostructural information when the radius becomes large. Moreover, to better mimick the human visual mechanism, the IMLBP is computed with the multiscale strategy and the operation is based on a patch unit whose size is proportional to the radius value. The frequency histogram of feature maps is transformed to feature vectors. Subsequently, a predictable function trained by the support vector regression is used to infer the overall quality score. Experimental results show that the proposed method outperforms most state-of-the-art IQA metrics on publicly available multiply distorted image databases.
On Derivation of Most Probable Modes for Intra Prediction in Video Coding

High Efficiency Video Coding (HEVC) standard introduced 35 intra prediction modes in order to improve intra prediction performance. To signal mode of the current block to the decoder a list of three most probable modes (MPM) is derived based on the modes of the two neighboring blocks. Similarly, six MPMs are used in the recent Joint Exploration Model (JEM) to accommodate the increased number to 67 intra prediction modes. One method to achieve this is to use an extension of HEVC approach. The other one employs the modes of the five neighboring blocks, together with their derived modes and default modes, in an ordered MPM candidate list. Our contribution is to use case-based multiple candidate lists. For each defined case, the corresponding list is sorted based on the probability of each candidate. The index of a case is computed based on the defined status values. Experimental results show 0.22%, 0.19%, 0.18% BD rate savings for Y, U, and V components for all-intra configuration, respectively.
Human attention region-of interest in I-frame for video coding

We propose a new scheme that exploits characteristics of motion vectors combined with luminance contrast to automatically detect human attention regions of interest (HAROIs) in every I-frame or intra-coded blocks in a group of pictures (GOP). These HAROIs can then be used for adaptive quantization. Motion vectors information is collected before the encoding phase. Our ultimate goal is to obtain a generic HAROI detection scheme of relatively low additional complexity per I-frame that can be used to improve compression while maintaining video quality and perception. Experimental results show consistency between actual human attention regions and the most relevant regions identified by our algorithm. Our algorithm also produces better compression of I-frames while improving both peak-signal-to-noise ratio (PSNR) and structural similarity (SSIM).
Automatic formal verification of systolic array designs

The authors have previously (1990) developed a new formalism, called systolic temporal arithmetic (STA), for formal specification and verification of systolic arrays at the array level. The formalism exploits systolic array attributes to produce elegant specification and effective formal design verification and is suitable to be combined with interval temporal logic for multilevel reasoning for several abstraction levels of systolic architecture. Besides providing a brief review of the STA formalism, the paper concentrates on discussing and expanding several formal techniques that the authors developed recently to verify the correctness of different systolic architectures. The paper emphasizes two verification strategies: verification by different induction techniques and verification by solving STA difference equations. Verification techniques are developed to produce sound and efficient verification procedures and provide short-cuts to proofs. In addition, the paper also presents a Prolog-based verifier that the authors developed to automate the proofs. Prolog is adapted for automated verification due to its popularity and its closeness in representing STA predicate-type notations. This allows easy encoding and user control to improve efficiency. The automatic backtracking and pattern matching mechanisms of Prolog serve as a useful tool for implementing the proofs.<<ETX>>
High Efficiency Video Coding and its 3D extension: A research perspective

High Efficiency Video Coding (HEVC) is jointly developed by the Joint Collaborative Team on Video Coding (JCT-VC) of the ISO/IEC Motion Picture Experts Group (MPEG) and the ITU-T Video Coding Experts Group (VCEG). At the present time, HEVC development is at its finalizing stages and achieving a 50% bit-rate reduction as compared to that of the current H.264/AVC video coding standard. Significant increase in resolution and perceptual quality can be expected for home and mobile video applications with future devices and content using HEVC. Beyond 2D video, the work for the 3D extension of HEVC has begun. In this paper, we look at HEVC and its 3D extension and discuss future research challenges addressing them. We explain the essential HEVC coding tools, and highlight the ones giving high coding gains. Finally, we highlight some of our current research related to HEVC.
Verification tool for systolic array design

The axiomatization of STA (systolic temporal arithmetic) defines rules for the systolic array in the language of the predicate calculus. The STA formalism is briefly reviewed and an automated verifier is constructed using Prolog. The verification tool is developed to produce a sound and efficient verification process and to provide short-cuts to justify systolic array designs. The STA specifications and the corresponding Prolog programs can be written using an almost identical notation.<<ETX>>
An automated design specification and verification tool for systolic architectures

Presents a Prolog-based verifier, VSTA, for formal specification and verification of systolic architectures. VSTA allows users to design systolic array architectures in the systolic temporal arithmetic (STA) specification language, and the designs can be semi-automatically verified by the system. In addition, the authors describe how a systolic array for LU decomposition can be specified and verified with respect to its algorithm. The proof techniques used are mathematical induction and rewriting. The induction technique is adopted to exploit the regularity and locality nature of systolic array architectures. A number of verification tactics are developed in the verifier and their operational rules are used in the verifier. Using the powerful symbolic computation ability of Prolog, particularly pattern matching, automatic backtracking, and the depth-first searching rules, the verifier performs efficiently in the construction of proofs.<<ETX>>
Application of QR decomposition-based least squares technique to improve air traffic control radar

For real-time radar processing, it is very desirable to have an algorithm that does not assume restricted statistics of the input data and can be implemented for high-speed processing (without a high cost) to meet real-time requirements. We therefore apply the QR decomposition-based least-squares method for linear prediction to the problem of computing the reflection coefficients of a lattice predictor, instead of using the conventional Burg algorithm. We also propose a modified one-dimensional ring architecture for implementing the QR method of least-squares. The particular application considered in this case is that of surveillance radar systems for air traffic control.<<ETX>>
An efficient systolic array design for the discrete sine transform

A two-dimensional systolic array is designed for the 1-D Discrete Sine Transform (DST). The implementation of the DST is carried out by defining the 1-D DST in terms of the Discrete Fourier Transform (DFT). A 1-D array is initially designed for the DFT by utilizing Goertzel's algorithm which requires N processors with a computation time of O(N). The 1-D array for the DST is designed by adding additional computational elements to the 1-D DFT array. A 2-D array for the DST is designed by partitioning the indices of the input data. The 2-D array achieves a speedup of O(/spl radic/N) for the N-point DST when compared to the computation time for the 1-D systolic array without increasing the number of processors.<<ETX>>
A two-level rate control approach for video transcoding

We present a two-level rate control approach for VC-1 to H.264 transcoding. First, a low complexity algorithm in which the key is to find the relationship between quantization parameters (QPs) in VC-1 to QPs in H.264. Second, a medium complexity algorithm in which the key is to use mean absolute differences and sum of absolute transform differences calculated in VC-1 to estimate the complexity of macroblocks in H.264 for a pixel/transform domain transcoder. The low complexity rate control tool has a limitation of only able to rate-control transcode for QP ranges from 10 to 29. To transcode the entire QP range we propose a combination of low and median complexities tools. Results show that the proposed rate control transcoding is less complex than that of a full-cascaded transcoder with regular rate control turned on, while maintaining target bit-rate and PSNR.
Polyphase filter architectures for MPEG audio using fast IDCT

We present a fast architecture by using a fast IDCT algorithm for polyphase analysis subband filtering, a computational-intensive operation in MPEG audio coding. Our basic approach is to use only one adder/subtractor and one multiplier, but each has its own data bus, and a process controller is used to control the overall processing. The bus width is found by finite wordlength simulation. Simulation results and summaries have shown that a low cost adder/subtractor and multiplier in VLSI implementation can be designed for real-time applications.
Improved frame-layer rate control for H.264 using MAD ratio

In recent years, rate control plays an increasing important role in real-time video communication applications using MPEG-4 AVC/H.264. An important step in many existing rate control algorithms, which employs the quadratic rate-distortion (R-D) model, is to determine the target bits for each P frame. This paper aims in improving video distortion, due to high motions or scene changes, by more accurately predicting frame complexity using the statistics of previously encoded frames. We use mean absolute difference (MAD) ratio as a measure for global frame encoding complexity. Bit budget is allocated to frames according to their MAD ratio, combined with the bits computed based on their buffer status. Simulation results show that the H.264 coder, using our proposed algorithm with virtually little computational complexity added, effectively alleviates PSNR surges and sharp drops for frames caused by high motions or scene changes.
A mesh-based method for wavelet video coding using edge-detection in low frequency subband

In this paper, we propose a mesh-based method for motion estimation and compensation over low frequency subband for wavelet video coding. We concentrate on edge-detection information and apply different parameters using edge magnitude and edge angle values to indicate curvature values for objects. This helps to detect motion patches between adjacent frames for meshes. We analyze and compare coding efficiency with a variety of video test sequences. Experimental results show that our mesh method improves coding performance for videos with less globally distributed motions compared to local motions.
A high speed motion estimator using 2-D log search algorithm

This paper describes the design of a high speed motion estimator using the 2-D log search algorithm. The architecture consists of 5 simple processing elements (PE) where each PE is capable of computing the sum-of-absolute-difference (SAD) to exploit the parallelism. For each step in the 2-D log search procedure, the 5 SADs of the 5 search points are computed in parallel. The design is implemented using Verilog and synthesized using Synopsys. Simulations show that the architecture is able to generate the motion vector for each 16/spl times/16 macroblock in 14.58 /spl mu/s for 3-step log search, and 24.30 /spl mu/s for 5-step log search. The architecture is thus well suited for encoding MPEG2 video up to MP@ML.
An architecture for MPEG-4 binary shape decoder

An architecture for MPEG-4 binary shape decoder is presented. Our novel techniques include a look-ahead unit to speed up the probability generation process, the usage of synchronous ROM for reduced power consumption, and the use of simple shift registers instead of large barrel shifters to reduce the area of the decoder. The decoder architecture is designed using VHDL. The decoder is able to decode up to 100 Mbits/s and can be used to achieve Main Profile at Level Three performance requirement.