nils-herrmann/clean_scirepeval huggingface dataset:
Design of digital accelerators for backpropagation

This paper proposes an efficient technique for implementing artificial neural networks (ANNs). This technique is utilized to design two fast neurocomputers; FMAT1 and FMAT2. The paper concentrates on the recall and learning phases of multilayer perceptrons with backpropagation learning. FMAT1 requires less hardware but is appropriate for the recall phase only. With a small additional cost, FMAT2 adds the capability of learning. When compared to other techniques in the literature, FMAT1 and FMAT2 exhibit superior performance. They provide a better connections per unit time measure. To compute a neural network having N Neurons in its largest layer, These two architectures require O(log N) processing time. Another major virtue of these architectures is their ability to pipeline multiple patterns which further improves performance.
ETSSI: Energy-based Task Scheduling Simulator for wireless sensor networks

Distributed processing has been a viable solution for enabling the next generation of real-time wireless sensor networks (WSN). Efficient task scheduling and allocation (TSA) policies guarantee that efficiency of the distribution. However, TSA policies in WSN face the challenges imposed by the wireless communication medium. This makes the accurate evaluation and verification of TSA policies difficult in live systems. Hence, developing a TSA simulator becomes essential to decrease the time for successful development and testing of relevant algorithms. This work addresses the need for a TSA simulator for WSN and develops ETSSI an Energy-based Task Scheduling Simulator. ETSSI is an event-driven, scalable, simulator which provides a user-friendly graphical interface. Its accuracy is more than 80% compared to in-door live implementations on a test bed of Telosb nodes. Most importantly, the TSA policy designer using ETSSI is only concerned about the application model, not the actual application implementation, which is mandatory in today's WSN simulators.
Comparing performance metrics of a parallel ECC architecture vs. input data patterns and granularity

In this paper, we first introduce a parallel Elliptic Curve Cryptography (ECC) architecture that performs the operations required for ECC scalar point multiplication on GF(2m) operands and then we analyze the performance metrics of the architecture. The architecture is modular, can handle various operands sizes. The architecture performs several different operations in parallel when each operation requires small key size and uses power gating technique to deactivate the unutilized modules to save power. An exhaustive simulation-based study of the different performance aspect of architecture is provided considering the input data patterns, the granularity of the system and the parallelism level of the architecture.
A low power architecture for a new efficient block-matching motion estimation algorithm

This paper presents an exhaustive search algorithm for block matching motion estimation. The proposed algorithm reduces the computational load with successive elimination of non-candidate blocks in the search window. The proposed algorithm locates the global optima as located by the full search block-matching algorithm. This computational reduction leads to low-power VLSI implementation of the algorithm.. Also, it leads to faster efficient motion estimation procedure. The correctness of this algorithm and its complexity presented. Simulation results on benchmark video clips are presented.
Lightweight highly secure PUF protocol for mutual authentication and secret message exchange

PUFs or Physically Unclonable Functions are emerging hardware security primitives that offer a lightweight alternative to standard security for highly restricted devices like RFIDs. PUFs, however, have been found to be vulnerable to modeling attacks and as such PUF-based authentication protocols had to employ cryptographic primitives to establish reliable security. We introduce a novel lightweight, PUF-based protocol that offers unlimited number of highly secure mutual authentications and secret message exchanges while utilizing no cryptographic or hash functions. The protocol uses simple binary operations, a strong PUF circuit and a true random number generator to establish cryptography-strength security making it the first lightweight PUF-based protocol that can truly match cryptographic algorithms in terms of reliable security and unlimited authentications.
Memory accesses reduction for MIME algorithm

Power consumption of digital systems has become a critical design parameter. An important class of digital systems includes applications such as video image processing and speech recognition, which are extremely memory dominant. In such systems, a significant amount of power is consumed during memory accesses. Reducing the number of memory accesses can considerably impact the power dissipation in the rest of the design. Therefore, optimizing an application for reduced memory access can greatly effect the overall power consumption in the entire system. This paper presents an architectural enhancement multi-stage interval-based motion estimation (MIME) algorithm that not only saves power by reducing the number of memory accesses but also significantly increases the speedup.
Noise-tolerant design and analysis for a low-voltage dynamic full adder cell

In an attempt to study the behavior of dynamic circuits in the presence of deep submicron noise when operating at a low supply voltage, this paper presents noise tolerant design and analysis for an enhanced dynamic full adder cell based on the NORA-CMOS logic style. The noise tolerance capability is achieved by applying the twin-transistor technique on both the p and the n parts of the circuit. A prototype is constructed for both the standard and the designed noise tolerant circuits using 0.18 /spl mu/m CMOS technology and simulated using HSPICE at supply voltage ranges from 0.9 V to 2.7 V. Noise immunity curves are developed and used to calculate the average noise threshold energy which shows a 2.5 times improvement when compared with the conventional design. The noise enhancement comes at the expense of 2.1 times extra power consumption.
Parallel algorithms prototyping: a case study

A prototyping approach for systolic algorithms is presented. While systolic algorithms are considered simpler and more straight-forward than the other forms of parallel algorithms, they have served the purpose of illustrating the prototyping aspect of the proposed paradigm. The systolic model provides a notation for specifying both systolic computation and the architecture. The communication requirements are specified. A cost function is developed to be used for comparison analysis. It is shown how the proposed model and language constructs can be easily interfaced to a high-level parallel language.<<ETX>>
An architecture for automated scene understanding

This paper presents distributed, automated, scene surveillance architecture. Object detection and tracking is performed by a set of region and object agents. The area under surveillance is divided in several sub-areas. One camera is assigned to each sub-area. A region agent is responsible for monitoring a given sub-area. Background subtraction is first performed on the scene taken by the camera. Based on the foreground mask, the region agent segments the incoming frame and creates object agents dedicated to tracking detected objects. Tracking information and segments are sent to a scene processing unit that analyzed this information and determined if a threat pattern is present at the scene and performed appropriate action.
Low-latency power-efficient adaptive router design for network-on-chip

Network-on-chip (NOC) technology has offered an efficient solution for scalability problem. Following the advent of the NOC technology, decreasing the static power consumption has been at the focus of research and development. Since the routers are the most important and main power-consuming modules of NOC, most of the contributions are related to improvement in router micro-architecture design , . Power-gating is currently an effective solution in this area but it causes overhead in terms of delays and in some cases it deteriorates the performance. In this paper, a power efficient design for the network-on-chip (NOC) routers using adaptive routing has been proposed. The Proposed scheme is directing the traffic in a power-gated network with respect to the routers status. In this way, we avoid to turn on the routers, that are in sleep state by alternating the paths. Our simulation has shown that we can achieve near 80% reduction in static power consumption compared to non-power-gated design and we improved the average delay by 35% in comparison with conventional power-gated design.
A VLSI architecture for hybrid object-based video motion estimation

This paper presents a VLSI architecture that can be used for video object motion estimation. The architecture generates a 2D hierarchical mesh that represents the dynamics of the video object, and it uses a block matching core to generate the motion vectors of the mesh nodes. The architecture uses parallel block matching motion estimation to optimize the latency. Moreover, using the three steps motion estimation algorithm simplifies the motion estimation of the mesh nodes. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications such as in MPEG-4, and VRML.
SEDLRF: A New Door Detection System for Topological Maps

Autonomous robots are currently receiving an increasing attention in the scientific community as well as in the industry. This is due to the upcoming applications in the field of service robotics. The first requirement for a robot to be able to do such tasks is to navigate successfully to desired locations in its environment. This paper investigates a perception system for topological navigation using real time laser information. The newly developed door detection system is named "space and edge detection laser range finder" or SEDLRF. SEDLRF detects space between door edges enabling fast door detection. Various experimental results show the performance of the presented system in detecting various doors by filtering at least 10 times of the detected points. SEDLRF achieves good performance with higher robot speed than other door detection systems.
An Adaptive Block Size Phase Correlation Motion Estimation using Smart Multireference Frames Selection in Frequency Domain

The multiple reference frame motion compensation (MRMC) supported by H.264 makes use of redundancy between multiple frames to enhance the coding efficiency over the techniques which use a single reference frame motion compensation. However, searching the motion vectors in multiple frames is computationally expensive. This paper proposes a smart MRMC selection technique, which has a lower search complexity without sacrificing video quality. To reduce the complexity of the motion estimation process, adaptive block size phase correlation motion estimation (ABS-PC-ME) technique using several prediction techniques is used. The proposed scheme has lower complexity compared with the conventional schemes.
Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects

Global signaling is becoming more and more challenging as technology scales down toward the deep submicron. We propose a new bus encoding technique, transition skew coding, that targets many of the global interconnects challenges such as crosstalk, peak energy and current, switching and leakage power, repeaters area, wiring area, signal integrity and noise. Simulations are done on different bus lengths using a 90nm library. Repeaters sizing and spacing are optimized, and the proposed encoded bus is compared against a standard bus and a bus with shields inserted between every two wires. The encoding and decoding latencies are also analyzed. Simulations show that transition skew coding is efficient in terms of energy and area with low encoding and decoding latency overhead.
A high speed architecture for MAP decoder

In this paper, a new high speed MAP decoder architecture is presented. The speed in the MAP decoder is limited by the recursive iteration loop which updates the state metrics. Lookahead transformation technique alleviates the limitation of the recursive loop by expanding it in time. The focus in this paper is on the design of MAP decoder architecture based on lookahead transformation. One level of lookahead is applied that can process two updating trellis iterations at the same time. Resulting in improving the throughput and reducing the state metric memory. This technique is limited by the increased complexity of the add-compare-select-add (ACSA) unit. Design of less complex ACSA is presented, also the MAP decoder based on the look-ahead is prototyped on Xilinx FPGA.
Frequency domain: Efficient and high speed technology for video transmission

Motion Estimation (ME) consumes up to 70% of the entire video encoder's computations and is, therefore, the main encoding-time consuming process. Using DCT along with Adaptive Padding (AP) in frequency domain are the recently evolved Frequency Domain ME (FDME) techniques that efficiently reduce the ME computational complexity. There are two main problems of using such conventional AP in the frequency domain. Firstly, the adaptive thresholds need to be estimated in the pixel (IDCT) domain which increases complexity. Secondly, the mismatched transformed search area is formed from different successive transformed blocks, which would lead to an inaccurate ME if the search area is not manipulated. In this paper, an efficient low complexity algorithm and high speed architecture are proposed to implement an adaptive Manipulation Unit (MU). The MU, the main module of the FDME system, adaptively decides the padding size and forges a matched transformed search area from the successive transformed blocks. Additionally, the proposed utilized adaptive thresholds are efficiently estimated in the Frequency Domain (FD). The MU architecture is presented with two different design implementations trading off the VLSI design parameters.
PPT based fast architecture & algorithm for discrete wavelet transforms

A non recursive (unlike classical dyadic decomposition) and Fast Fourier Transform based architecture for computing Discrete Wavelet Transforms (DWT) of a one dimensional sequence is presented. DWT coefficients at all resolutions can be generated simultaneously without waiting for generation of coefficients at a lower octave level. This architecture is faster than architechlres proposed so far [l] for DWT decomposition (which are implementations based on recursion) and can be fully pipelined. Complexity of control circuits for this architecture is much lower as compared to implementation of recursive methods. Now consider computation of DWT (four octaves) of a sequence. Recursive dyadic decomposition can be converted to non recursive method as shown in the figure. We can move all the decimators shown to the extreme right (towards output end) and have a single filter and a single decimator in each path. we note that a decimator (of factor k) when so moved across a filter of length L will increase the length of the filter by a factor of k Thus we will get first octave DWT coefficients by convolving input sequence with a filter of length L and decimating the output by a factor of 2. Second octave coefficients are generated by convolving input sequence with a filter of length 3L and decimating the outpul by a factor of 4. 3rd and 4th octaves are got by convolving with filters of length 7L and decimating by a factor of 8. Now all the convolutions can be done in frequency domain by overlap save method, for example. Input is divided into overlapping (with a overlap of L) blocks of length N1 = 2JL where j is the maximum octave generated (4 here). DFT coefficients of the input sequence block is computed by any of the FFT algorithm implementation and multiplied with precomputed DFT coefficients of all the four filter blocks. First L results of each of these block outputs are discarded. ( N I -L ) length IDFTs of each of these block outputs are found and each of the resulting block outputs are decimated, by appropriate factors. For example to generate first octave DWT, the corresponding output from the convolver is decimated by a factor of 2 etc., Note that decimation does not involve any hardware. Hardware complexity of the whole scheme is O(NlZogN1) i.e, 0 [ (J + L)2JL], whereas the recursive implementations have a complexity of only O(L) (this is without considering overhead due to maintenance of intermediate result queues). The new architecture is faster than recursive methods by an order of O(23L)
A low power CMOS UWB pulse generator

The paper presents a low power CMOS pulse generator design for impulse based UWB applications. The basic structure of the design involves a variable length rectangle pulse generator, a CMOS quasi-Gaussian pulse shaping filter and a small monopole antenna model. Simulation results show the pulse after the antenna is compliant with the FCC's spectrum mask for 0~960 MHz band and has a power consumption of 234 muW at the pulse repetition frequency of 100 MHz. The CMOS circuit used to create the pulse generator is simple and lends itself to a low-power, single-chip UWB transmitter solution
A fast and flexible residue decoder based on the Chinese remainder theorem

An implementation of a fast and flexible residue decoder based on the Chinese remainder theorem (CRT) is proposed for decoding a set of residues to its equivalent representation in a weighted binary number system. This decoder is flexible, since the decoded data can be selected to be either unsigned magnitude of two's complement binary number. It is shown that this residue decoder is extremely fast compared to previously proposed residue decoders.<<ETX>>
VLSI architecture for hierarchical mesh-based motion estimation

Methods for object-based compression and composition of natural and synthetic video content are currently emerging in standards such as MPEG-4 and VRML. This paper shows a novel VLSI architecture for generating content-based video object representation. The architecture uses a novel technique, borrowed from the 3D modeling, to optimize the mesh coding. The architecture generates the mesh nodes location as well as the associated motion vectors. The performance results show that the prototype contributes practical delay, and it can be used in online application and the power consumption shows that it is good enough in mobile application. Moreover, the number of bits used for the coding shows that the architecture is suitable for very low bit rate applications since it reuses the motion vector values.
Digital IF decimation filters for 3G systems using pipeline/interleaving architecture

This paper presents efficient of IF decimation filters architecture using pipeline/interleaving (PI) technique in which the amount of multiplications is reduced by 50%. The decimation filters are important blocks in software radio terminals to process different communications standards like GSM, IS-95, and UMTS. These kinds of blocks are needed to process the I, and Q components on the digital down-converter. The proposed architecture is evaluated by MATLAB. This evaluation shows that the proposed structures can be utilized in a multimode fashion. The frequency response of the decimator filter for each standard is analyzed and the frequency response for the decimator filter using Pl architectures is also evaluated. The new architecture offers saving of 50% the amount of multiplications compare to the traditional implementation.
Remote Measuring for Sand in Pipelines Using Wireless Sensor Network

Sand production is considered one of the major problems facing the petroleum industry since a small amount of sand in the produced fluid can result in significant erosion in a very short time period. Installation of a system to monitor and quantify sand production from a well would be valuable to assist in optimizing well productivity and to detect sand as early as possible. In this paper, we present a framework for sand detection and sand production rate measurement. The framework combines two modules: 1) a wireless sensor data acquisition (WSDA) module and 2) a central data fusion (CDF) module. The framework is designed to collect data from oil pipeline using acoustic sensors (SENACO AS100), flow analyzer (MC-II), and differential pressure transmitter (EJA110A) in real time. A test bed is established from ten acoustic sensors mounted on a closed-loop pipeline. The flow rate and the differential pressure are monitored as well. The sand is injected in the test bed with a constant flow and pressure. The output of the acoustic sensor is analyzed in order to calculate the sand production rate. The sand rate, flow rate, and pressure are digitized for wireless transmission using the WSDA module. The data are collected in the gateway, i.e., a laptop in our case. The CDF module is implemented in the gateway. The purpose of data fusion is to improve the system performance. Three different fusion methods, fuzzy art, maximum-likelihood estimator, and moving average filter are evaluated throughout the simulation and experimental results. The proposed framework is successfully tested and evaluated.
On block architectures for discrete wavelet transform

Architectures for the discrete wavelet transform (DWT) operate typically on a sequential input. This input consists of a single data value every clock cycle. While this can be efficient for 1-D applications, 2-D ones, such as image processing, suffer from the dimensional direction bottleneck of the separable 2-D filter. The block-based architectures greatly reduce these on-chip memory requirements. Though the block-based architectures may take more computation time, the work can be divided among several processors. This paper demonstrates how a block processing architecture can be achieved, with advantages for the 2-dimensional DWT; less memory and parallel computation. Though the 2-D DWT in particular is discussed, these ideas apply to multi-dimensional cases as well.
A non-zero clock skew scheduling algorithm for high speed clock distribution network

In this paper, we present a novel algorithm for scheduling clock skews in a synchronous digital circuits to optimize performance. The new algorithm is based on inclusively matching allowable clock skews intervals of all local data path in the circuit in order to determine the proper global skew ranges. This algorithm will lead to minimizing the clock period as well as obtaining a list of scheduled skews to be inserted in the clock network. These scheduled skews are then used to obtain a delay model for all branches of the clock distribution network tree. The delay values ensure the proper synchronization of data and eliminate any potential race condition in the circuit. The new algorithm has been tested and found to be a good approach toward reducing the clock period compared with zero intentional skew clocking.
Minimizing switchings of the function units through binding for low power

This paper considers minimizing the switchings of the function units in high-level synthesis. Switching activities on the function units are gathered through profiling the data-flow graph of the design at hand. Several thousands of random input streams are generated and used for such profiling. A genetic algorithm is employed for creation of a wide variety of random input patterns which are critical to measuring the switching activities. The switching activities are obtained and stored in a matrix. The problem of binding the function units for low power is then formulated and solved by using the proposed method. Based on the simulations, a power saving of 8%-24%, due to reduced switchings, is indicated for the considered standard benchmarks.