nils-herrmann/clean_scirepeval huggingface dataset:
Morphological steganalysis of audio signals and the principle of diminishing marginal distortions

Steganographic methods attempt to insert data in multimedia signals in an undetectable fashion. However, these methods often disrupt the underlying signal characteristics, thereby allowing detection under careful steganalysis. Under repeated embedding, disruption of the signal characteristics is the highest for the first embedding and decreases subsequently. That is, the marginal distortions due to repeated embeddings decrease monotonically. We name this general principle as the principle of diminishing marginal distortions (DMD) and illustrate its validity in the audio domain using a morphological distortion metric. The principle of DMD is used to derive a steganalysis tool that detects the presence of hidden messages in uncompressed audio files. Detailed analysis and experimental results are provided for the detection of spread spectrum watermarking and stochastic modulation steganography.
Adder-accumulator cells in RSFQ logic

We are in the process of designing a Finite Impulse Response (FIR) filter for use in a Digital Signal Processing (DSP) system based entirely on Rapid Single Flux Quantum (RSFQ) logic. One aspect of this project involves the development of the arithmetic unit of the filter, in this case an adder-accumulator multiplier. This article describes two cells can perform the function of accumulated addition in the adder-accumulator multiplier. We have fabricated both cells and tested them at low speed.<<ETX>>
Non-Contact ECG Sensing Employing Gradiometer Electrodes

Noncontact, capacitive electrocardiogram (ECG) measurements are complicated by motion artifacts from the relative movement between the ECG electrodes and the subject. To compensate for such motion we propose to employ first and second order gradiometer electrode designs. A MATLAB-based simulation tool to enable assessment of different electrode configurations and placements on human subjects has been developed to guide the refinement of electrode designs. Experimental measurements of the sensitivity, motion artifact cancellation, and common mode rejection for various prototype designs were conducted with human subjects. Second order gradiometer electrode designs appear to give the best performance as measured by signal to noise plus distortion ratio. Finally, both gradiometer designs were compared with standard ECG recording methods and showed less than 1% beat detection mismatch employing an open source beat detection algorithm.
Picosecond on-chip qubit control circuitry

Fast on-chip control of superconducting qubits has engaged complex and power consuming RSFQ circuits that currently pose more of an experimental burden than an asset. Measurements of quantum coherent oscillations of qubits require dilution refrigerator temperatures. The motivation of this design is to minimize the necessary bias leads and power dissipation for an SFQ based control circuit. Elimination of redundant circuit elements by innovative use of fundamental elements allows small-scale control circuitry.
Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling $\Sigma\Delta$  Analog-to-Digital Conversion

We present a theoretical analysis, design, and experimental characterization of a CMOS image sensor with pixel-level ΣΔ oversampling analog-to-digital conversion (ADC). The design employs five transistors per-pixel to implement a charge-based ΣΔ ADC at each pixel. In the current design a dynamic regenerative latch comparator is divided into an input transistor, which is contained within each pixel, and the remaining comparator structure shared among the pixels of each column. A charge feedback digital-to-analog converter (DAC) is implemented at each pixel with a three-transistor structure. As opposed to more traditional CMOS image sensors, this image sensor architecture is suitable for implementations in advanced low supply voltage CMOS technologies since its dynamic range is not affected by the reduction of the pixel reset voltage. In addition, similar to the readout methods in low power random access memory designs, this pixel readout architecture does not employ any active amplifiers which allows for low static power operation. Experimental characterization of a prototype fabricated in a 0.35 μm silicided CMOS technology is presented. The estimated power consumption of the fully integrated 128 × 128 imager including decimation filters and I/O interface is 60 nW/pixel at 30 frames per second for 8-bits per-pixel. A peak signal-to-noise ratio of 52 dB and intra-scene dynamic range of 74 dB were measured. The dynamic range was extended to 91 dB through control of the in-pixel DAC supply voltage over the range of 0.8 V-3.3 V.
Non-Uniformly Tiled CMOS Image Sensors for Efficient On-Chip Image Compression

We present a complementary metal-oxide semiconductor (CMOS) image sensor with non-uniform pixel placement that enables a highly efficient calculation of the discrete cosine transform (DCT), which is the most mathematically intensive step of an image compression algorithm. This technique is based on the arithmetic Fourier transform (AFT), which has been shown to be five times more computationally efficient than DCT derivation methods commonly used. In this paper, the focus is on the basic theory and algorithm as well as the sensitivity of the method to image sensor fixed pattern noise (FPN). The architecture and circuits have been implemented in a conventional CMOS process. The method has been demonstrated in the current prototype and results that enable an assessment of the sensitivity to FPN have been obtained.
A CMOS Image Sensor with Focal Plane Discrete Cosine Transform Computation

In this paper we describe an image sensor with nonuniform pixel placement that enables a highly efficient computation of the discrete cosine transform, which is the most computationally demanding step of the image compression algorithm. This technique is based on the arithmetic Fourier transform (AFT), which we show to be 5 times more computationally efficient than currently used DCT computation methods. The architecture and circuits described can be implemented in conventional CMOS processes.
Collusion Resilient Fingerprint Design by Alternating Projections

Digital fingerprinting techniques aim to embed unique identification information into digital content distributed to individual users in order to track unauthorized use of multimedia files. Fraudulent users may not only attempt to remove the embedded signatures but also may form coalitions in order to remove the embedded fingerprint and disable tracking. This makes the design of fingerprints challenging. An effective fingerprint should not only carry the assigned users information but also guard against the possibility of falsely implicating an innocent user. Furthermore, in possible collusion scenarios, the colluded copies should identify each of the colluders. The embedded fingerprints should be imperceptible to maintain the commercial value of the content and preferably the fingerprint-based identification should survive content preserving signal processing. In this paper we give a precise description of each of these requirements and give a solution framework to obtain a set of fingerprinted images meeting these requirements.
Reverberation features identification from music recordings using the discrete wavelet transform

This paper presents a method of extracting reverberation features from music recordings. First, we perform a short time Fourier transform to transform the audio signal into a 2D time-frequency representation in which reverberation features appear as blurring of spectral features in the time dimension. Employing image analysis method we may quantitatively estimate the amount of reverberation by transforming the STFT “image” to a wavelet domain where we can perform efficient edge detection and characterization. Experiments demonstrate that quantitative estimates of reverberation time extracted in this way are strongly correlated with physical measurements.
Short-term frequency stability of clock generators for multigigahertz rapid-single-flux quantum digital circuits

Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.
Direct Digital Predistortion on a Computer Controlled FPGA

We report on the development of direct digital radio frequency predistortion techniques for high power amplifiers and their demonstration in a MF band FPGA-based system. The basic component of our work is a nonlinear cubic voltage characteristic which is realized digitally by means of a look-up table. This method is situated in the context of existing baseband and analog predistortion techniques. In particular, we demonstrate our results experimentally and show a relationship between the bit-depth of our look-up table and the size of intermodulation distortions in the output of a class A amplifier.
A transducer based upon vacuum tunneling

The phenomenon of quantum-mechanical vacuum tunneling of electrons between conductors is highly sensitive to the separation of the conductors. This sensitivity is exploited by using vacuum tunneling to detect the relative motion of two conductors. The basic theory of the tunneling transducer is presented. It is shown that the vacuum tunneling transducer can be more sensitive than a conventional reciprocal transducer and that it can surpass the limits which the amplifier forces upon a reciprocal transducer. The noise present within the tunneling transducer is discussed, and experimental results are presented.<<ETX>>
Set Theoretic Quantization Index Modulation Watermarking

We introduce a set theoretic framework for quantization index modulation (QIM) watermarking and illustrate its potency by designing a semi-fragile watermark that is both visually adaptive and tolerant to compression. We determine the watermarked image to satisfy the multiple constraints of watermark detectability, imperceptibility and robustness to compression using the method of projections onto convex sets (POCS). Mark embedding is performed through implicit quantization of statistical features, specifically the mean, of randomly selected pixel locations from the image. This is accomplished by defining a detectability constraint set that imposes the quantization constraint. We present experimental results demonstrating the efficacy of the technique in the presence of JPEG compression
Optimum Watermark Design by Vector Space Projections

We introduce an optimum watermark embedding technique that satisfies common watermarking requirements such as visual fidelity, sufficient embedding rate, robustness against noise and tolerance to benign signal processing, while optimizing one of these requirements. The algorithm distinguishes itself from other watermark optimization techniques in its flexibility for incorporating constraints and in assuring convergence to the globally optimum point when all constraints are convex. The proposed scheme is a natural extension of set-theoretic watermark design and inherits all the advantages of it. A watermarked image is first obtained by POCS, then optimum watermarked image is determined by an iterative search procedure based on a simple bi-section method. Experimental results are presented to illustrate the effectiveness of the method.
Thermal design of superconducting digital circuits for milliKelvin operation

Niobium based rapid-single-flux-quantum (RSFQ) digital circuits generally operate at temperature 4 K. It is desirable to develop RSFQ circuits for operation at much lower temperatures, in particular to use as control and interface circuitry for superconducting qubits, and eventually for a full scale quantum computer. The total heat load is moderate - current designs generate 0.5 /spl mu/W per bias resistor, so simple RSFQ integrated circuits are easily compatible with commercial helium dilution refrigerators, and this power can readily be reduced by several orders of magnitude for complex future designs - but thermal conductivity will be a bottleneck. We present a simple model of heat flow through standard RSFQ structures. We find that circuits designed for 4 K operation can be used with little or no modification below one Kelvin. At lower temperatures however the heat generated on chip cannot be removed, and the temperature of a working circuit will rise. We suggest fabrication design rule changes to address this problem.
Semifragile hierarchical watermarking in a set theoretic framework

We introduce a set theoretic framework for watermarking and illustrate its effectiveness by designing a hierarchical semi-fragile watermark that is tolerant to compression and allows tamper localization. Using a quad-tree representation, a spatial resolution hierarchy is established on the image and a watermark is embedded corresponding to each node of the hierarchy. The watermarked image is determined so as to jointly satisfy the multiple constraints of watermark detectability, imperceptibility, and robustness to compression using the method of projections onto convex sets. The spatial hierarchy of watermarks provides a graceful trade-off between robustness and localization under JPEG compression: mild JPEG compression preserves watermarks at all levels of the hierarchy allowing fine localization of malicious changes while aggressive JPEG compression preserves watermarks at coarser levels of the hierarchy still assuring overall image integrity but giving up the capability for localization. Experimental results are presented to illustrate the effectiveness of the method.
A low noise, non-contact capacitive cardiac sensor

The development of sensitive, non-contact electric field sensors to measure weak bioelectric signals will be useful for the development of a number of unobtrusive health sensors. In this paper we summarize our recent work on a number of specific challenges in the development of non-contact ECG sensors. First, we considered the design of a low noise sensor preamplifier. We have adapted circuit designs that incorporate a double feedback loop to cancel the input transistor leakage current while providing stable operation, fast settling time and good low frequency response without the need for ultrahigh value resistors. The measured input referred noise of the preamplifier in the frequency band 0.05-100 Hz is 0.76 μVrms, which is several times lower than existing ECG preamplifiers.
Generative modeling of temporal signal features using hierarchical probabilistic graphical models

We propose generative modeling algorithms that analyze the temporal features of non-stationary signals and represent their temporal structural dependencies using hierarchical probabilistic graphical models. First, several template sampling methods are introduced to embed the temporal signal features into multiple instantiations of statistical variables. Then the learning schemes that obtain hierarchical probabilistic graphical models from data instantiations are detailed. Based on the sampled temporal instantiations, multiple probabilistic graphical models are discovered and fit to the signal support regions. The evolution structure of these graphical models is depicted using a higher-level structural model. Finally, performance evaluations based on both simulated datasets and audio feature dataset are presented.
An expressive and compact representation of musical sound

We describe a representation of musical instrument sounds in which the sound is codified as the time histories of the parameters controlling a nonlinear physical model of the target musical instrument. As opposed to source-filter models often employed in speech, in which an assumed periodic source is filtered by a time varying acoustic transfer function, in our proposed method the nonlinear dynamical behavior of the source generator in interaction with an acoustic filter is directly simulated. The resulting autonomous oscillations of the combined system are controlled by a small number of slowly varying parameters. This representation has two advantages; first, it is extremely compact, requiring only 10's of bytes/sec of data, and second, it naturally captures variations of musical timbre and other nuances of live musical performance. We present preliminary results for recorded clarinet sounds in which the maximum likelihood estimation (MLE) method is used to infer the control parameter histories for an assumed target clarinet model.
Design and low speed testing of a four-bit RSFQ multiplier-accumulator

We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.
Indirect-feedback Sigma-Delta CMOS image sensors with SAR-based startup

A novel type of CMOS image sensor (CIS) leveraging two types of analog-to-digital converters (ADCs) is presented in this work. Contrary to conventional ΣΔ image sensors, which implement ΣΔ ADCs at the column or pixel array level, this work utilizes the pixel structure as part of the ΣΔ modulator to enhance the noise shaping capabilities of the readout scheme. The overall speed performance of this indirectfeedback (IF) ΣΔ image sensor is enhanced with the addition of a Successive Approximation Register (SAR) startup. The SAR startup has been successfully demonstrated on two prototype image sensors developed in a generic 0.35μm digital CMOS process. For the column-level, 320x180 pixel implementation, the SAR startup is included with minimal additional overhead, 1.8% of original ΣΔ column readout circuitry.
gMRAM: Gain-cell magnetoresistive random access memory for high density embedded storage and in-situ computing

High density embedded memories have been demanded increasingly to enhance the performance and reduce the power dissipation of advanced systems, such as multicore processors, which have been used in a wide variety of applications from servers to Internet-of-things (IoT) devices. In this paper, a memory cell, referred to as the gain-cell magnetoresistive random access memory (gMRAM), is introduced. The gMRAM significantly reduces the cell area per bit as compared to state-of-the-art embedded memories, provides opportunities for the joint enhancement of performance and reduction of power dissipation, and provides a natural basis for in-situ computing. A gMRAM cell simultaneously retains two bits, a nonvolatile bit using a magnetic tunnel junction (MTJ) and a dynamic bit using the access transistor of the MTJ. The two bits are independently and nondestructively accessible for read and write. This paper focuses on the design and characterization of the gMRAM cell, array architecture, and read/write circuitry. Simulation results from an 8 kb gMRAM array using a 14 nm standard FinFET CMOS technology demonstrate a 750 ps / 475 ps access time for dynamic read/write, while the nonvolatile bit can be read from or written to the same cell with a, respectively, 750 ps and 3.5 ns access time. The gMRAM cell area per bit is 3× (2×) smaller than a SRAM (3T eDRAM) cell in the same technology.
On-chip picosecond delay measurement of RSFQ digital logic gates

Because RSFQ circuits are intended to operate at multi-GHz frequencies, a logical requirement for developing the technology is a method of accurately measuring the picosecond delays associated with individual logic circuits. A technique has been developed for on-chip measurements of such RSFQ gate delays. The central element in this scheme is a race between a path of calibrated variable delay and a path of unknown delay. Modification of the canonical RSFQ RS flip-flop circuit yields a multiple state destructive readout cell (MDRO), in which one can configure the number of flux quanta to be stored. This circuit has been experimentally verified for groups of two flux quanta. Used in concert with the confluence buffer, this scheme can provide the RSFQ designer with sub-picosecond pulse arrival delay information crucial for higher order circuit simulation. A detailed experimental process is presented from which this timing information can be extracted using basic low-speed measurement techniques.<<ETX>>
An oversampling digital pixel sensor with a charge transfer DAC employing parasitic capacitances

An image sensor design with pixel-level sigma-delta (ΣΔ) conversion employing four transistors at each pixel where the feedback charge transfer is realized through the parasitic capacitances of an inactive transistor is presented. This architecture is a relatively simple and robust design where the only analog components required outside of the pixel array are shared row comparators and a voltage mode digital-to-analog converter (DAC) to supply the in-pixel charge feedback structures. The photodiode acts as the integrator of the ΣΔ modulator and an in-pixel charge feedback DAC is realized with two PMOS transistors. A third, minimum size PMOS transistor operating in the cut-off region provides capacitive coupling through which a controlled amount of charge is injected to the photodiode. The sensitivity of the image sensor is determined by the size of the feedback charge packets in the ΣΔ modulator. The remainder of the image sensor is all digital, including a decimation filter to convert each pixel's single bit output stream into a multi-bit sample. We fabricated a test pixel structure in the TSMC-0.35µm CMOS technology with 10µm × 10µm pixels and a fill factor of 31%. Experimental results demonstrated a SNR of 60dB and a dynamic range of 83dB.
Current Sensing-Assisted Active Pixel Sensor for High-Speed CMOS Image Sensors

In this paper, we describe an active pixel CMOS image sensor that employs a current-sensing readout circuit. The readout uses a column-level current-sensing amplifier with negative feedback to increase current driving capability, which gives significantly faster settling time. A prototype 128 × 3 pixel sensor with a current gain of 10 was fabricated using standard 0.3-μm CMOS technology and demonstrated a reduction in settling time by a factor of 14 for both negative and positive voltage swings of the output node. The power consumption of the column-level readout amplifier is 110 μW.