nils-herrmann/clean_scirepeval huggingface dataset:
An Efficient Architecture for 3-D Discrete Wavelet Transform

This paper presents an architecture of the lifting-based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-D-DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for real-time compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7).
A new approach to model the I/spl sim/V characteristics for nanoscale MOSFETs

A compact current voltage model is proposed for nanoscale MOSFET device. I/spl sim/V characteristics are plotted based on the modified mobility and carrier velocity saturation models including the high field effects along the entire channel. Results of the proposed model are in good agreement with the experimental and TCAD simulator results down to channel length of 10 nm MOSFET.
Knowledge-based Doppler blood-velocimeter system

A scheme of a knowledge-based Doppler blood-velocimeter system using an artificial neural network is proposed. The scheme supports feature extraction from a Doppler ultrasonography periodogram, and comparison with statistical data to make therapeutic studies on that basis. A physical model of blood flow with salient features taken into account, spectral estimation using the time varying autoregressive moving average (ARMA) model, and an artificial neural network (ANN) scheme for the determination of the coefficients of the ARMA model has been presented.
A photoacoustics based continuous non-invasive blood glucose monitoring system

The paper examines the use of photoacoustic spectroscopy (PAS) for making continuous non-invasive blood glucose measurements. An apparatus for performing photoacoustic (PA) measurements is constructed and the technique is verified in vitro and in vivo through measurements on glucose solutions and live tissue. The signal amplitude is observed to increase with the glucose concentration in both cases. A linear calibration method is applied on each individual to obtain a glucose concentration value from each PA measurement. The glucose values obtained are compared with reference glucose concentrations measured using a standard glucose meter, giving a mean absolute difference (MAD) of 23.75 mg/dl and a mean absolute relative difference (MARD) of 18.03%. A plot of 196 measurement pairs taken over 30 normal subjects on a Clarke Error Grid gives a point distribution of 67.86%, 31.12%, 0.0%, 1.02% and 0.0% over zones A to E of the grid. This performance is an improvement over those obtained previously using PAS and point to the potential of the technique for non-invasive glucose measurements. An FPGA based reconfigurable embedded architecture is proposed for high speed data acquisition, noise reduction and display of PA measurements. The architecture operates at 274.823 MHz on a Xilinx Virtex-II Pro FPGA providing an SNR improvement of 30 dB and enabling a portable blood glucose monitoring system.
Geometric programming based power-delay optimization using transistor-sizing for submicron and deep submicron CMOS inverter

This paper proposes a new method to formulate the transistor sizing problem as a geometric programming by using a modified I-V model in the power-delay product (PDP), for sub micron and deep sub micron CMOS inverter circuits. The design objective and constraints are modeled as posynomial functions of the design variables. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (0.25-/spl mu/m) results. Further the approach has been extended to predict the transistor sizing for deep submicron (0.09-/spl mu/m) CMOS inverter.
Doppler ultrasonograph with CORDIC based spectrum analyzer for blood flow velocity estimation

An ultrasonograph system for estimating flow velocity of blood in vessels is proposed which incorporates a spectrum analyzer for observing the Doppler shift occurring due to the flowing blood. The Doppler signal is extracted from the reflected ultrasonic wave by a synchronous demodulation technique and then fed to an analog-to-digital converter through a sample-and-hold circuit. The spectrum analyzer uses FPGA based signal processing chips realizing vector rotations utilising a modified CORDIC algorithm for computing the discrete Hartley transform which is a real valued alternative to the discrete Fourier transform.
NIR photoacoustic spectroscopy for non-invasive glucose measurement

The use of near infra red (NIR) photoacoustic spectroscopy (PAS) for continuous non-invasive glucose measurement is outlined in the paper. A photoacoustic (PA) measurement apparatus was constructed and PA measurements were made on glucose solutions at multiple NIR excitation wavelengths. A variety of time and frequency domain features, including amplitude and area based features, were extracted from the PA measurements. These features were observed to be proportional to the glucose concentration of the sample. PA measurements from samples of whole blood at different glucose concentrations showed similar results. Subsequently, in vivo PA measurements made on a cohort of 30 volunteers were calibrated using a quadratic fit, and the results were compared to reference glucose concentrations made using a regular blood glucose meter. A comparison of 196 measurement pairs of predicted and reference glucose concentrations using a Clarke Error Grid gave a point distribution of 87.24% and 12.76% over zones A and B of the grid, with no measurement pairs falling in unacceptable zones C-E of the error grid. The predicted measurements had a mean absolute difference (MAD) of 12.57 ± 13.90 mg/dl and a mean absolute relative difference (MARD) of 9.61% ± 10.55%. This is an improvement over previous results obtained using PAS and other non-invasive techniques, validating the potential of PAS for continuous noninvasive glucose monitoring.
FPGA implementation of a fetal heart rate measuring system

Labor during pregnancy is an inherently dangerous life event for a live fetus and its mother. Non-invasive method of Fetal Heart Rate (FHR) measuring system helps to reduce Infant Mortality Rate (IMR) by continuous monitoring of the fetus heart rate. In this paper real-time implementation of a FHR measuring system has been developed using Xilinx Spartan-6 FPGA device, which can calculate the fetus heart rate and display ECG signal through HDMI port. In FHR extraction of the cleaned fetal ECG signal from the maternal ECG is the main challenge. In our proposed work Least Mean Square (LMS) adaptive filter has been used as the adaptive noise canceller along with dynamic thresholding technique for de-noising the fetus ECG signal and helps to achieve 88% accuracy in the proposed FHR system. FPGA implementation of the FHR system consumes 7.8K slices and can achieve sampling frequency of 80 MHz while implemented on XC6SLX45-3CSG484 FPGA device. The comparison results show that our proposed design is more efficient than the literature reported earlier.
A low complexity architecture for complex discrete wavelet transform

This paper presents a low complexity architecture for realization of CDWT for minimal resource environment like FPGA and SoC applications in image processing. The proposed architecture uses parameterization of the coefficients for reduced redundancy in computation. Use of CSD based multipliers along with pipelined CORDIC provided an architecture for efficient implementation in contrained environment along with high speed and efficiency. Low data path length and lower control complexity are other salient features of the architecture presented in the paper. This design was implemented on Xilinx FPGA platform. The operational frequency of the implemented circuit is 47 MHz.
Implementation of Katsevich algorithm for helical cone-beam computed tomography using CORDIC

Katsevich algorithm is the first exact cone-beam reconstruction algorithm for helical cone-beam computed tomography (CT) reconstruction. The commonly used Feldkamp-Davis-Kress (FDK) reconstruction algorithm is an approximate algorithm. The Katsevich algorithm is of filtered backprojection (FBP) type and is an exact algorithm. Although the acceleration of Katsevich algorithm on CPU or GPU have been widely studied, the FPGA implementation is yet to be explored. In this paper, a parallel and pipeline architecture for Katsevich algorithm has been implemented in Xilinx Virtex 4 FPGA. COordinate Rotation DIgital Computer (CORDIC) algorithm has been used to compute complex mathematical and trigonometric functions. We have also analyzed the effect of various windowing techniques for implementation of Hilbert transform on the reconstruction of the CT image. The architecture is able to reconstruct a CT volume image of size 2563 in 7s.
A 10-bit 80-MSPS 2.5-V 27.65-mW 0.185-mm/sup 2/ segmented current steering CMOS DAC

This paper presents a 10 bits 80 MSPS 2.5 V digital-to-analog converter (DAC) using 0.25 micrometer double poly four metal CMOS technology for mixed-signal applications. A segmented current steering architecture is used for this DAC. This architecture gives the most optimized results in terms of speed, resolution, area and power. The DAC can operate at a frequency of 80MHz and above. Total power dissipation is 27.6525 mW with 2.5 V power supply. It achieves differential nonlinearity and integral nonlinearity of /spl plusmn/0.55 LSB and /spl plusmn/0.4 LSB. It occupies an area of 0.185 mm/sup 2/.
A tunable transconductor with high linearity

In this paper a high frequency low voltage low power tunable highly linear transconductor is presented. Shift level biasing is used at the inputs of both the amplifiers of a cross coupled differential pair for tuning. Bias currents of cross coupled differential amplifiers are adjusted to cancel third harmonic distortion. The proposed circuit is simulated in Cadence VIRTUOSO environment with UMC 0.18 µm CMOS process technology. Simulation results show that for the biasing current of 206 µA (Gm of 222 µS), the circuit exhibits less than −51 dB total third harmonic distortion (HD3) at 1 Vp-p @ 50 MHz.
VLSI architecture for a new real-time 3D wavelet transform

In this paper a real-time 3-D discrete wavelet transform algorithm is proposed. The inter-frame decomposition is achieved using the last two frames of the sequence. Reduced buffer and real-time applicability makes the algorithm usable for high-speed bi-directional interactive applications of multimedia and also HOTY. An efficient VLSI architecture which promises 100% hardware utilization low buffering and low hardware complexity is designed for the realization of the 3-D wavelet transform. DWT filters, designed by data-folding architecture and QMF lattice filters are arranged in pipeline to achieve the spatial decomposition with high through-put. A parallel array architecture is used for the decomposition in temporal direction which proves efficient to accomodate the huge amount of data.
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000

The embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. Various applications, such as medical imaging, satellite imagery, digital cinema, and others, require high speed, high performance EBCOT architecture. Though efficient EBCOT architectures have been proposed, hardware requirement of these existing architectures is very high and throughput is low. To solve this problem, we investigated rate of concurrent context generation. Our paper revealed that in an image rate of four or more context pairs generation is about 68.9%. Therefore, to encode all samples in a stripe-column, concurrently a new technique named as compact context coding is devised. As a consequence, high throughput is attained and hardware requirement is also cut down. The performance of the matrix quantizer coder is improved by operating renormalization and byte out stages concurrently. The entire design of EBCOT encoder is tested on the field programmable gate array platform. The implementation results show that throughput of the proposed architecture is 163.59 MSamples/s which is equivalent to encoding 1920p (1920 × 1080, 4:2:2) high-definition TV picture sequence at 39 f/s. However, only bit plane coder (BPC) architecture operates at 315.06 MHz which implies that it is 2.86 times faster than the fastest BPC design available so far. Moreover, it is capable of encoding digital cinema size (2048 × 1080) at 42 f/s. Thus, it satisfies the requirement of applications like cartography, medical imaging, satellite imagery, and others, which demand high-speed real-time image compression system.
A parallel pipeline ADC with a Sub-ADC employing an improvized dynamic comparator

This paper presents an Analog to Digital Converter (ADC) capable of resolving 8 bits at a sampling rate of 250 MSPS. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecrure was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch generated charge injection error in order to maintain good overall accuracy. Simulation showed non-linearity figures of −0.3173LSB ≤ DNL ≤ 0.28LSB and −0.0373LSB ≤ INL ≤ 0.7LSB. From the sinusoid response, SNDR turns out to be 49.6 dB which yields an ENOB of 7.94 bits. Power consumed by the ADC at the highest sampling rate of 250 MSPS is ≈ 108mW using a power supply of 1.8 V. The ADC occupies an area of 2.371mm2.
Anti-collusion codes: multi-user and multimedia perspectives

Digital fingerprinting is an effective method to identify users who might try to redistribute multimedia content, such as images and video. These fingerprints are typically embedded into the content using watermarking techniques that are designed to be robust to a variety of attacks. A cheap and effective attack against such digital fingerprints is collusion, where several differently marked copies of the same content are averaged or combined to disrupt the underlying fingerprint. We present a construction of collusion-resistant fingerprints based upon anti-collusion codes (ACC) and binary code modulation. ACC have the property that the composition of any subset of K or fewer codevectors is unique. Using this property, we build fingerprints that allow for the identification of groups of K or less colluders. We present a construction of binary-valued ACC under the logical AND operation using the theory of combinatorial designs. Our code construction requires only /spl Oscr/(/spl radic/n) orthogonal signals to accommodate n users. We demonstrate the performance of our ACC for fingerprinting multimedia by identifying colluders through experiments using real images.
Time-Reversal Massive Multipath Effect: A Single-Antenna “Massive MIMO” Solution

The explosion of mobile data traffic calls for new efficient 5G technologies. Massive multiple-input multiple-output (MIMO), which has shown the great potential in improving the achievable rate with a very large number of antennas, has become a popular candidate. However, the requirement of deploying a large number of antennas at the base station may not be feasible in indoor scenarios due to the high implementation complexity. Does there exist a good alternative that can achieve similar system performance to massive MIMO for indoor environment? In this paper, we show that by using time-reversal (TR) signal processing, with a sufficiently large bandwidth, one can harvest the massive multipaths naturally existing in a rich-scattering environment to form a large number of virtual antennas and achieve the desired massive multipath effect with a single antenna. We answer the above question by analyzing the TR massive multipath effect and the achievable rate with some waveforms. We also derive the corresponding asymptotic achievable rate under a massive multipath setting. Experiment results based on real indoor channel measurements show that the massive multipaths can be revealed with a sufficiently large bandwidth in a practical indoor environment. Moreover, based on our experiments with real indoor measurements, the achievable rate of the TR wideband system is evaluated.
DMUSIC algorithm for 2D NMR signals

The authors propose a super-resolution scheme for the parameter estimation of two-dimensional (2-D) NMR signals. 2-D NMR signals can be modeled as the summation of 2-D damped sinusoids. The frequencies and the damping factors of 2-D damped sinusoids play important roles in protein structure determination using 2-D NMR spectroscopy. The authors develop a super-resolution frequency and damping factor estimation algorithm-the damped MUSIC (DMUSIC) algorithm. Since the DMUSIC algorithm makes full use of the rank-deficiency and the Hankel property of the data matrix composed of the 2-D NMR data, compared with other NMR data analysis algorithms, it can resolve NMR spectroscopy signals under a low signal to noise ratio. The performance of the DMUSIC algorithm is demonstrated by simulations.
Low-power design methodology for DSP systems using multirate approach

We present a low-power design methodology based on the multirate approach for DSP systems. Since the data rate in the resulting multirate implementation is M-times slower (where M is a positive integer) than the original data rate while maintaining the same throughput rate, we can apply this feature to either the low-power implementation, or the speed-up of the DSP systems. This design methodology provides VLSI designers a systematic way to design low-power DSP systems at the algorithmic/architectural level. The proposed low-power multirate design scheme is verified by the implementation of two FIR VLSI chips with different architectures: One is the normal pipelined design and the other is the multirate design with downsampling rate equal to two. The experimental results show that the multirate FIR chip consumes only 21% power of the normal FIR chip given the same data throughput rate.
A multi-winner cognitive spectrum auction framework with collusion-resistant mechanisms

Dynamic spectrum access, enabled by cognitive radio technologies, has become a promising approach to improve efficiency in spectrum utilization, and the spectrum auction is one approach in which unlicensed wireless users lease some unused bands from spectrum license holders. However, spectrum auctions are different from traditional auctions studied by economists, because spectrum resources are interference-limited rather than quantity-limited, and it is possible to award one band to multiple secondary users with negligible mutual interference. Due to its special feature, the multi-winner auction is a new concept posing new challenges in the existing auction mechanisms such as the Vickery-Clarke-Groves (VCG) mechanism. Although widely employed in other auctions, the VCG mechanism does have serious drawbacks when applied to the multi-winner auction, such as unsatisfactory revenue and vulnerability to collusive attacks. Therefore, in this paper, we propose a multi-winner spectrum auction framework, and develop suitable mechanisms for this kind of auction. In specific, the mechanism awards the bands in such a way that the spectrum efficiency is maximized, and determines prices based on the Nash bargaining solution to improve revenue and prevent collusion. We further analyze that secondary users do not have incentives to manipulate information about mutual interference which is essential to the auction. Finally, simulation results are presented to evaluate our proposed auction mechanisms.
A factor-image framework to quantification of brain receptor dynamic PET studies

The positron emission tomography (PET) imaging technique enables the measurement of receptor distribution or neurotransmitter release in the living brain and the changes of the distribution with time and thus allows quantification of binding sites as well as the affinity of a radioligand. However, quantification of receptor binding studies obtained with PET is complicated by tissue heterogeneity in the sampling image elements (i.e., voxels, pixels). This effect is caused by a limited spatial resolution of the PET scanner. Spatial heterogeneity is often essential in understanding the underlying receptor binding process. Tracer kinetic modeling also often requires an intrusive collection of arterial blood samples. In this paper, we propose a likelihood-based framework in the voxel domain for quantitative imaging with or without the blood sampling of the input function. Radioligand kinetic parameters are estimated together with the input function. The parameters are initialized by a subspace-based algorithm and further refined by an iterative likelihood-based estimation procedure. The performance of the proposed scheme is examined by simulations. The results show that the proposed scheme provides reliable estimation of factor time-activity curves (TACs) and the underlying parametric images. A good match is noted between the result of the proposed approach and that of the Logan plot. Real brain PET data are also examined, and good performance is observed in determining the TACs and the underlying factor images.
Optimum Power Allocation for Maximum-Likelihood Channel Estimation in Space-Time Coded MIMO Systems

This paper presents an optimum power allocation strategy for the maximum likelihood based channel estimation in the space-time coded multiple-input multiple-output systems employing a data-bearing approach for pilot-embedding. The corresponding channel estimation error, the Chernoff's upper bound on the detection error probability, and a lower bound on channel capacity of such systems are analyzed. Based on such analysis, the relationship between these two bounds are revealed, then a unified optimum power allocation scheme is proposed based on jointly optimizing both bounds subject to an acceptable channel estimation error. Simulation results indicate that the proposed power allocation scheme yields a better performance in terms of the error probability, whereas the equal power allocation scheme can be reasonably used as a suboptimum approach with an acceptable performance degradation. Furthermore, the unequal power allocation with more power constantly allocated to the data part yields a much better performance than the one with more power constantly allocated to the pilot part
Performance analysis for multi-node decode-and-forward relaying in cooperative wireless networks

We provide symbol-error-rate (SER) performance analysis for a multi-node wireless network employing a decode-and-forward cooperation strategy. An approximate expression for the SER of an N relay network with M-ary phase-shift-keying (M-PSK) signalling is derived at high enough signal-to-noise ratio (SNR). The approximation hinges on ignoring terms in the SER which are of order higher than (N+1) in the SNR. The validity of the derived approximate SER is justified through computer simulations for networks with different numbers of relays. The simulation results show that the approximation is tight at high SNR and that the cooperation protocol can achieve full diversity order equal to the number of cooperating terminals.