nils-herrmann/clean_scirepeval huggingface dataset:
The design and implementation of multidimensional systolic arrays for DSP applications

The authors present a technique for transforming DSP (digital signal processing) algorithms to a form suitable for multidimensional systolic array implementation. The aim of the transformation is to speed up computation without much increase in area requirement. The price to be paid is the small amount of additional circuitry (usually in the form of adders and interconnection wires) required for interrow or interplane communications. The application of the technique to some DSP algorithms is presented. The systolic networks produced are implemented using NORA CMOS logic structure and laid out using 3- mu m CMOS p-well technology. Areas and times for the resulting architectures are evaluated and discussed.<<ETX>>
A review of VLSI technologies in digital signal processing

The authors discuss current VLSI technologies that are in use for implementing digital signal processing (DSP) algorithms at the integrated circuit level. The authors start by introducing the technologies, including features and properties associated with high-performance implementation of DSP systems. This is followed by a technology and architectural view of current commercial DSP chips, including both general-purpose programmable devices and some special-purpose devices. It is shown that not only advanced technology can be used to improve the performance of VLSI processors but that special parallel architectures can introduce much higher levels of performance improvement. The authors conclude with a look at the new technology of integrating sensor devices with DSP processing architectures.<<ETX>>
On low power high level synthesis using genetic algorithms

This paper describes a new approach for utilizing genetic algorithms to solve high-level synthesis tasks with multiple voltages. The novelty of the method lies in its approach for modeling and encoding the resulting chromosomes. The proposed system receives a control/data flow graph, hardware library, and the constraints for area, time, and power as inputs. It then uses this information to concurrently solve the scheduling, binding, and allocation problems in order to generate a solution optimized for average and peak power. The new formulation eliminates the need to check for a valid schedule since it always generates a valid one. This leads to a simple evaluation function and a quick solution. The evaluation function is a mix of constraints satisfaction and a consideration of average and peak power. Simulation results show that the lower power solutions are obtained in a reasonable CPU time, which is in the range of seconds.
Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era

Due to the end of Dennard Scaling and the rise of dark silicon, it is essential to design energy-efficient heterogeneous NoC under critical power and thermal constraints. The challenge is to determine and configure NoC resources while meeting the application(s) requirements. Because of the large and complex many-core NoC design space (voltage/frequency scaling, link bandwidth, power-gating, etc.), design space becomes difficult to explore within a reasonable time for optimal decision at run-time. Furthermore, reactive resource management is not effective in preventing problems, such as creating thermal hotspots and exceeding power budget, from happening. Therefore, we propose a Neuro-NoC model, which utilizes neural networks learning algorithm to dynamically monitor, predict, and configure NoC resources based on online learning of the system status. Distributed cluster-wise neural network and a global neural network model for resource monitoring and configuration in many-core NoC has been proposed. Simulations demonstrate that Neuro-NoC can predict the global optimal NoC configuration with high accuracy (88%), sensitivity (97% true positive), and specificity (88% true negative).
A new full adder cell for low-power applications

A new low power CMOS 1-bit full adder cell is presented. It is based on recent design of XOR and XNOR gates, and pass-transistors, it has 17 transistors. This cell has been compared to two widely used efficient adder cells; the transmission function full adder cell (16 transistors) and the low power adder cell (14 transistors). The new cell has no short circuit power and lower dynamic power (than the other adder cells), because of less number and magnitude of circuit capacitances. It consumes 10% to 15% less power than the other two cells. A comparative analysis (using Magic and Hspice) for 8-bit ripple carry and carry select adders shows that the adders based on the new cell can save up to 25% of power consumption.
CVSS: A Cost-Efficient and QoS-Aware Video Streaming Using Cloud Services

Video streams, either in form of on-demand streaming or live streaming, usually have to be converted (i.e., transcoded) based on the characteristics of clients' devices (e.g., spatial resolution, network bandwidth, and supported formats). Transcoding is a computationally expensive and time-consuming operation, therefore, streaming service providers currently store numerous transcoded versions of the same video to serve different types of client devices. Due to the expense of maintaining and upgrading storage and computing infrastructures, many streaming service providers (e.g., Netflix) recently are becoming reliant on cloud services. However, the challenge in utilizing cloud services for video transcoding is how to deploy cloud resources in a cost-efficient manner without any major impact on the quality of video streams. To address this challenge, in this paper, we present the Cloud-based Video Streaming Service (CVSS) architecture to transcode video streams in an on-demand manner. The architecture provides a platform for streaming service providers to utilize cloud resources in a cost-efficient manner and with respect to the Quality of Service (QoS) demands of video streams. In particular, the architecture includes a QoS-aware scheduling method to efficiently map video streams to cloud resources, and a cost-aware dynamic (i.e., elastic) resource provisioning policy that adapts the resource acquisition with respect to the video streaming QoS demands. Simulation results based on realistic cloud traces and with various workload conditions, demonstrate that the CVSS architecture can satisfy video streaming QoS demands and reduces the incurred cost of stream providers up to 70%.
Low power VLSI prototype for motion tracking architecture

This paper presents a low power VLSI prototype for a video object motion tracking architecture that can be used for very low bit rate online video applications. The architecture prototypes a 2D mesh-based video object motion tracking algorithm. It can be used as a building block for 2D mesh-based video object systems such as MPEG-4 and MPEG-7 systems. Moreover, the power consumption and the delay show that the prototype can be used in mobile online video applications.
Repair techniques for aged TSVs in 3D integrated circuits

Through silicon via (TSV) based 3D integrated circuits (ICs) have become a popular approach to revive Moore's law. However, the reliability of a TSV is an important issue, as a faulty TSV can result in the failure of the entire 3D IC. Most of TSV faults can be detected during the testing process, however, detecting TSV aging faults during the testing process is impossible. Certain mechanisms are required to be deployed to control the reliability of the chip in the presence of aging faults. In this paper we propose some solutions to repair the TSVs suffering from moderate types of delay fault without re-routing through a spare TSV while meeting the specified constraints of the design. Our experimental results indicate the efficiency of our proposed methods in reducing the adverse effects of an aged TSV in terms of delay reduction.
A look-up table VLSI design methodology for RNS structures used in DSP applications

In current high-speed digital signal-processing (DSP) architectures, the Residue Number System (RNS) has an important role to play. RNS implementations have a highly modular structure, and are not dependent upon large binary arithmetic elements. RNS implementations become more attractive when combined with the advantages offered by VLSI fabrication technology. In this paper, a novel design methodology has been developed for RNS structures, based on using look-up tables, which takes into consideration the unique features and requirements of RNS. The paper discusses the following three phases: 1) developing a look-up table layout model, which is used to derive relationships between the size of each modulus and both chip area and time; this model supports all types of moduli; 2) selecting the most efficient layout according to the design requirements; the procedure allows the designer to control the area, time, or the configuration of the memory module required for implementing a modulo look-up table; 3) proposing a set of multi-look-up table modules, to be used as building block units for implementing digital signal-processing architectures. The paper uses two examples to -illustrate the use of the modules in phase 3).
Noise tolerant low power dynamic TSPCL D flip-flops

The extensive use of a dynamic circuit techniques for higher performance has already been implemented in many circuits like microprocessors. With the scaling down to deep submicron technology and the move towards dynamic circuit techniques, noise immunity is becoming an important metric like power, speed, and area. This paper proposes a technique to achieve low energy consumption in TSPCL D flip-flops. The paper studies some published flip-flops and carries out a modification that reduces the switching activity of some internal nodes, causing a big saving in power consumption. The proposed flip-flop is characterized and compared with those published ones for reliability and energy efficiency. Comparison for speed, power consumption, and noise tolerance is also presented. The average noise threshold energy (ANTE) and the energy normalized ANTE metrics are used for quantifying the noise immunity and energy efficiency, respectively of flip-flops. Results using 0.18 /spl mu/m CMOS technology and HSPICE for simulation, show that the proposed TSPCL D flip-flop achieves reduction in power dissipation ranging from 4.6% to 80% depending on the input pattern and the technology in use. The noise immunization curves show that the modified flip-flop is more susceptible to noise. Hence, one of the known noise immunization techniques should be applied.
Novel 7T sram cell for low power cache design

Low-power on-chip cache is a crucial part in many applications. Conventional write operation depends on discharging/charging large bit lines capacitance which causes high power consumption. We propose a 7T SRAM cell that only depends on one of the bit lines during a write operation and reduce the write power consumption. HSPICE simulation shows that at least 49% write power saving, higher stability, and no performance degradation with additional 12.25% silicon area
Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling

The continuous semiconductor technology scaling has made on-chip interconnect the major determinant of VLSI design cost and complexity. This necessitates the usage of signaling techniques that reduce the number of long on- chip wires and repeaters. In this paper, we present a point-to-point inter-block on-chip link design that allows simultaneous bidirectional signaling, thus reducing the number of signal lines and repeaters, while achieving high performance. By using accelerating repeaters and inserting a bidirectional latch at the midpoint of the link high performance simultaneous bidirectional signaling can be achieved with significant reduction in repeater and wire counts. We analyze the switching behavior of the proposed on-chip simultaneous bidirectional link (SBL) and find that it suffers from large switching activity overhead. Therefore, an opposite-polarity transition encoding is also proposed to reduce the power overhead of SBL without affecting its performance.
A 1-GS/s 6-bit flash ADC in 90 nm CMOS

In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.
ASPEN: An Asynchronous Signal Processor for Energy Efficient Sensor Nodes

For ubiquitous wireless sensor networks, there are three main requirements. The devices must be extremely small, consume very little operating power, and capable of distributed signal processing to enable in situ processing of sensed data at leaf nodes of the network. This paper presents the design of an Asynchronous Digital Signal Processor (ASPEN) to realize these goals. Using Quasi-delay insensitive (QDI) asynchronous templates in the processor core, the energy consumption per instruction is reduced, while performing Digital Signal Processor (DSP) tasks. The processor takes advantage of multiple functional blocks, which are activated only when an instruction requiring their use is found in the instruction queue. The primary processor pipeline resembles that of a microcontroller while other units remain dormant until an instruction using them arrives in the queue. Functional blocks implemented include an asynchronous FFT core and a DSP datapath. The processor has been designed in a commercial 90 nm process. It consumes less than 10 pJ/instruction for ALU computations, and up to 80 pJ/operation for instruction fetch and decode operations. The FFT unit consumes 132 pJ for a 16-point FFT.
Systolic array architectures for full-search block matching motion estimation

We present various systolic architectures for full search block matching motion estimation. Along with one dimensional (N PE's) and two dimensional (N/sup 2/ PE's) systolic array architectures using 2N, 3N,... ...., N/sup 2/-N processing elements are also presented. Each of the architectures is analyzed and then compared with others in terms of power consumption, area, delay and noise. Simulation and analysis results of the architectures are presented. The results show the trade-off between the number of processing elements used, processing rate and power dissipation.
Fast Variable Padding Motion Estimation Using Smart Zero Motion Prejudgment Technique for Pixel and Frequency Domains

Motion estimation (ME) plays an important role in modern video coders since it consumes approximately 60-80% of the entire encoder's computations. In this paper, three novel techniques are proposed to effectively speed up the ME process. First, a smart prediction technique for effectively deciding an initial search center is proposed. Second, a zero motion prejudgment technique is proposed to accurately decide whether the pre-estimated ISC can be considered as a best match motion vector (MV) and consequently save the required computations for the MV refinement process. Finally, a variable padding pixels ME technique is proposed to adaptively determine the number of padding pixels required for the search window for more computational cost savings. The three techniques are combined and applied to the block-based ME for a superior computational complexity savings in the ME process. The performance of the proposed techniques is tested in both the pixel domain ME and the frequency domain ME in terms of their quantitative visual quality (peak signal-to-noise ratio, PSNR), their computational complexity, and their bit rate. Experimental results demonstrate that the proposed fast ME technique is able to achieve approximately a 99.4% reduction in ME time compared to the conventional full search block-based ME (FSSBB-ME) with negligible degradation in both the PSNR and the bit rate. Additionally, the experimental results prove the effectiveness of the proposed techniques if they are combined with any block-based ME technique such as the fast extended diamond enhanced predictive zonal search. Experimental results also demonstrate that there is at least an additional savings of 72% in ME time using the conventional discrete cosine transform phase correlation ME (DCT-PC-ME) in the frequency domain compared to the conventional FSBB-ME technique in pixel domain. Compared to the conventional DCT-PC-ME, applying the proposed novel techniques to the DCT-PC-ME saves up to 89% in ME time.
A high speed VLSI architecture for scaleable ATM switches

This paper presents a prototype of a VLSI chip to be used as a building block for an efficiently scaleable ATM switch with a link speed of 622.2 Mb/s. The chip is a 4/spl times/4 shared multibuffer ATM switch based on the distributing banyan architecture. It is efficient in storage space like a shared memory switch and scaleable in size like a space division switch. Since the architecture is self-routing, the chip contains all necessary routing control. Special high speed and low power circuitry is used. The chip is implemented in 1.0 micron static CMOS and measures only 25 mm/sup 2/ in area.
FinFET based SRAM design: A survey on device, circuit, and technology issues

In this paper, we did a survey on FinFET based SRAM related device, circuit, and technology issues. As this is a novel and emerging technology to cope up with the technology scaling; therefore, we believe this literature review is much required and will help in future research in this area. The issues of optimized threshold voltage and supply voltage, metal gate work-function variation, surface orientation effect on circuit design, fin configuration optimization, independent gate-based design, asymmetrical designing concept, fabrication level optimization issues, tunnel FinFET, junctionless FinFET, pseudo-spin FinFET, etc. have been discussed throughout the paper.
P2E-DWT: A parallel and pipelined efficient VLSI architecture of 2-D Discrete Wavelet Transform

Discrete Wavelet Transforms has surpassed its counterparts due to its attractive properties, and hence been adopted by image processing algorithms. However, with the emergence of real-time resource constrained embedded imaging platforms, DWT manifests as a bottleneck. This article presents a hardware implementation for 2-D DWT. An area-efficient, parallel and pipelined architecture is proposed with a modified image scan coupled with “multiplier-free” multiplications. Through simulations and implementation, the proposed scheme proves to be a fast, area and power efficient solution for DWT.
RBS: Redundant Bit Security Algorithm for RFID Systems

In this paper, we propose a symmetric encryption algorithm for RFID systems called RBS (Redundant Bit Security). RBS is based on inserting redundant bits into the original data bits. The location of redundant bits inside the transmitted data represents the secret key. The redundant bits are generated by Light Weight Mac algorithm in order to provide integrity and authentication as well. The implemented hardware architecture meets the resource constraints of RFID systems, and encryption and decryption time is shorter compared to existing algorithms.
An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation

Motion estimation (ME) consumes up to 70% of the entire video encoder's computations and is, therefore, the main encoding-time consuming process. Discrete cosine transform (DCT)-based phase correlation along with dynamic padding (DP) are the recently evolved frequency domain ME (FDME) techniques that promise to efficiently reduce the computational complexity of the ME process. DP uses dynamic padding thresholds to select the proper search area size according to a pre-estimated set of motion vectors (MVs). The main drawbacks of using conventional DP in the frequency domain are two-fold. First, the dynamic thresholds need to be estimated in the pixel (IDCT) domain which increases complexity. Second, the mismatched transformed search area is formed from different successive transformed blocks, which would lead to an inaccurate ME if the search area is not manipulated. In this paper, an efficient low complexity algorithm and high speed architecture are proposed to implement an adaptive manipulation unit engine (MUE). The MUE, the main module of the FDME system, adaptively decides the padding size and forges a matched transformed search area from the successive transformed blocks. Additionally, the proposed utilized dynamic thresholds are efficiently estimated in the frequency domain (FD). The MUE architecture is presented with two different design implementations trading off the VLSI design parameters. Implementation and simulation results project that the proposed MUE, when integrated in a whole FDME system, can perform ME for 60 fps of 4CIF video at 172 MHz.
A highly reliable dual-arbiter PUF for lightweight authentication protocols

PUFs are an emerging security primitive that offers a lightweight security alternative to highly constrained devices like RFIDs. PUFs used in authentication protocols however suffer from unreliable outputs. This hinders their scaling, which is necessary for increased security, and makes them also problematic to use with cryptographic functions. We introduce a new Dual Arbiter PUF design that reveals additional information concerning the stability of the outputs. We then employ a novel filtering scheme that discards unreliable outputs with a minimum number of evaluations, greatly reducing the BER of the PUF.
A Logic Programming Approach For DSP Architectures Design

This paper introduces a logic programming approach for specifying, simulating, and testing Digital Signal Processing (DSP) systems. Prolog is used as a Hardware Description Language and a, host one, too. Backtracking and pattern matching of Prolog are employed for simulation and testing, respectively. Prolog provides homogeneity to the developed system as it supports hierarchical development and mixing of description at various hierarchical levels. The developed sys tem belongs to Algorithmic Specific CAD family. It can be employed for many DSP algorithms and applications development.
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.