Highly Conducting In2O3 Nanowire Network with Passivating ZrO2 Thin Film for Solution Processed Field Effect Transistors

DOI: 10.1002/aelm.201600218 In this study, we demonstrate solution processed In2O3 NWFETs for conventional bottom gate top contacts (BGTC structure) with a multiple nanowire network. Electrospinning is utilized to readily produce a scalable continuous In2O3 nanowire network. After an annealing process to remove the polymer matrix, the polycrystalline nanowire network exhibits a conductive channel property. To improve the FET performance, a bilayer structure comprising insulating zirconium oxide (ZrO2) and a nanowire network is adopted. Having a high binding energy with oxygen, ZrO2 is favorable for the passivation of oxygen related surface defects, firmly securing the nanowire network to the substrate. In addition, ] reported that electrons can pass through several insulating oxides when those oxides are combined with a semiconducting buffer layer. ZrO2, specifically, has a low work function compared to those of other insulating oxides,[6] so it is often applied to injection layer in organic light emitting diodes or resistive memory layers in resistive random access memory.[7] With a ZrO2 top layer, NWFET performance shows high current on/ off ratio (Ion/Ioff) and field effect mobility (mFET) and small SS and Von. Apart from NWFETs, due to limitations of the analyses of nanowire/thin film structures, a bilayer with In2O3 thin film and ZrO2 is fabricated to investigate the conduction mechanism, which is based on the energy band structure. Figure 1a provides a schematic illustration of the fabrication process of the hybrid In2O3 nanowire/ZrO2 thin film FET. Using a conventional single nozzle electrospinning of indium nitrate/PVP solution, indium/poly(vinylpyrrolidone) (PVP) composite fibers are obtained in the form of a fiber mat onto a p+ Si/SiO2 (100 nm) substrate  The substrate is used as gate/gate insulator. Subsequent thermal annealing on a hotplate at 400 degC results in an In2O3 nanowire network that adheres to the substrate (Figure 2b and Figure S1, Supporting Information) During thermal annealing, the decomposition of PVP reduces the size of the indium/PVP fiber and some of the fibers are welded spontaneously to form nodes and branches in the randomly oriented nanowire network. The ZrO2 top layer is coated directly on the nanowire network by a solution process using spin coating and annealing process. Finally, using e beam evaporation, the source and drain electrodes are deposited on top of the In2O3 nanowire/ZrO2 thin film composite (Figure S1, Supporting Information) The diameter of the indium oxide nanowires is a Gaussian distribution, in which the average size of 224 nanowires is 35.24 4.80 nm  All peaks in the X ray diffraction patterns in Figure 2c correspond to cubic In2O3 crystalline structure with Nanowire field effect transistors (NWFETs) are of great interest for future nanoelectronic application such as logic circuits, chemical/biosensors, and memory/display devices. Among various nanowire materials, indium oxide (In2O3) has received much attention because of its chemical stability, high mobility, and low temperature processibility. 1D nanowires featuring unique crystalline structure and distinctive carrier transport characteristics enable outstanding electrical performance.[1] However, when single nanowire is utilized for channel, its complicated growth and transfer processes are considered as an obstacle due to low yield and inconsistency in chemical and electrical properties. On the other hand, multiple nanowire networks have less deviation and enable more reliable device performance with higher yield, suggesting their great potential for electronic devices. Another issue in nanowires is that the substantial number of oxygen related surface states originating from the large surface to volume ratio results in high off current (Ioff) subthreshold swing (SS) turn on voltage (Von) and vulnerability to environmental stimuli. In this context, various studies have reported the passivation of oxide nanowires with organic or inorganic layers.[2] However, such a passivation process requires selective deposition steps including an additional patterning process. The stacking two heterogeneous metal oxide layers, a process frequently used to engineer a channel layer in a thin film transistor, is an attractive method to passivate the surface of a channel. In this bilayer structure, a top semiconducting layer such as InGaZnO, InZnO, or HfInZnO confines a conducting bottom layer and resulting devices demonstrate high mobility and robust gate bias stability.[3] However, this kind of confinement effect is valid only when the thickness of the bottom layer remains thin usually less than 5 nm; otherwise the channel becomes conductive and the device exhibits large negative Von and off current (Ioff) www.MaterialsViews.com www.advelectronicmat.de