nils-herrmann/clean_scirepeval huggingface dataset:
The microbiome in chronic inflammatory airway disease: A threatened species.
Venue: South African medical journal Suid Afrikaanse tydskrif vir geneeskunde

The human body is exposed to a multitude of microbes and infectious organisms throughout life. Many of these organisms colonise the skin, gastrointestinal tract (GIT) and airway. We now recognise that this colonisation includes the lower airway, previously thought to be sterile. These colonising organisms play an important role in disease prevention, including an array of chronic inflammatory conditions that are unrelated to infectious diseases. However, new evidence of immune dysregulation suggests that early colonisation, especially of the GITand airway, by pathogenic micro organisms, has deleterious effects that may contribute to the potential to induce chronic inflammation in young children, which may only express itself in adult life.
Indoor air bacterial communities in Hong Kong households assemble independently of occupant skin microbiomes.
Venue: Environmental microbiology

More than in any other habitat, humans exert a large influence on microbial communities indoors. Frequent contact between occupant skin and indoor surfaces causes indoor surface microbial communities to be largely assembled from and thus closely resemble occupant skin microbiomes. While indoor air and dust are known to also contain many human associated taxa, household air communities have not yet been directly compared with occupant skin microbiomes. We sampled microorganisms from air, surfaces and occupant skin in 19 Hong Kong households and used Illumina sequencing of the V4 hypervariable region of the 16S rRNA gene to investigate the dispersal relationships between the bacterial communities at each site. Our results confirmed that indoor surfaces bear the 'bacterial fingerprint' of household occupant skin. However, while air communities contained abundant human associated taxa and were household specific, air communities in each household did not resemble occupant skin from that household any more than occupant skin from other households. Our results suggest that, at least in Hong Kong, indoor air bacterial communities may be assembled largely from outdoor air and occupant body sites other than skin, and unlike surface communities do not harbour the occupants' skin 'bacterial fingerprint'
Lesion recovery and the bacterial microbiome in two Caribbean gorgonian corals

In the Caribbean, gorgonian corals dominate many coral reefs, while scleractinian coral cover has declined. Gorgonian corals deal with stressors such as lesions caused by wave action, predation, or human activities. In June 2012, artificial wounds were inflicted on branches of the gorgonians Eunicea flexuosa and Pseudoplexaura porosa found at 3 5 m depth on a patch reef (20deg52'5.23''N, 86deg51'58.92''W) near Puerto Morelos, Mexico. Following healing, injured and uninjured branches were collected to determine the effect of lesions on gorgonian biochemistry, symbiosis, microbiome, and immune response. Lesion recovery in E. flexuosa took twice as long as in P. porosa. In both species, tissues at and surrounding the lesions contained significantly higher sclerite content per dry weight but lower protein per surface area. In and around the lesion area, the density of symbiotic dinoflagellates, Symbiodinium spp. was lower than in uninjured branches, although Symbiodinium photochemical efficiency in tissues surrounding the lesion was not affected. The gorgonian species differed in their bacterial microbiome, but the overall bacterial community and dominant bacterial taxa did not differ between injured and uninjured branches, although the prevalence of some less common bacterial groups did vary. The two species exhibited distinct immune responses, whereby different components of the melanization cascade were activated, and exochitinase was mobilized only in E. flexuosa. While the gorgonian species differed in their lesion recovery response, both healed without signs of disease or colonization by fouling organisms. The capacity to recover successfully from injuries may partly explain why gorgonian corals dominate Caribbean coral reefs.
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
Venue: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems

There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place and route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split manufacturing methods. We demonstrate its applicability for both application specified integrated circuits and field programmable gate arrays. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1) the area and power costs of our approach can range between 7.4% 165% and 7% 60% respectively, depending on the design and the attacks targeted; 2) the speed impact can be minimal (close to 0% 3) our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4) our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g. through reverse engineering) and 5) our approach never produces any false positives, i.e. it does not report attacks when the IC operates correctly.
Vulnerability Analysis of a Circuit Layout to Hardware Trojan Insertion
Venue: IEEE Transactions on Information Forensics and Security

While the horizontal integrated circuit design process is extensively practiced, untrusted foundries can impose significant threats on the security of final products. A carefully inserted extra circuitry as a hardware trojan in a circuit layout can interfere with circuit functionality under very rare circumstances with inconsiderable footprints. In this paper, we introduce a novel layout level vulnerability analysis flow to evaluate the susceptibility of a circuit layout's regions to hardware Trojan insertion. We also present several metrics based on a circuit layout to quantify the possibility of hardware Trojan insertion in a specific region of layout. Results of applying our flow to several benchmarks have revealed considerably high vulnerability of circuit layouts to hardware Trojan insertion. Furthermore, several Trojans are implemented and inserted in layout regions with different vulnerabilities to evaluate the effectiveness of our new metrics. Our novel layout level vulnerability analysis flow makes it possible to quantitatively determine the vulnerability of different implementations of a circuit and analyze the susceptibility of each corner of circuit layout to different types of functional Trojans.
Interdiction in practice Hardware Trojan against a high security USB flash drive
Venue: Journal of Cryptographic Engineering

As part of the revelations about the NSA activities, the notion of interdiction has become known to the public: the interception of deliveries to manipulate hardware in a way that backdoors are introduced. Manipulations can occur on the firmware or at hardware level. With respect to hardware, FPGAs are particular interesting targets as they can be altered by manipulating the corresponding bitstream which configures the device. In this paper, we demonstrate the first successful real world FPGA hardware Trojan insertion into a commercial product. On the target device, a FIPS 140 2 level 2 certified USB flash drive from Kingston, the user data are encrypted using AES 256 in XTS mode, and the encryption/decryption is processed by an off the shelf SRAM based FPGA. Our investigation required two reverse engineering steps, related to the proprietary FPGA bitstream and to the firmware of the underlying ARM CPU. In our Trojan insertion scenario, the targeted USB flash drive is intercepted before being delivered to the victim. The physical Trojan insertion requires the manipulation of the SPI flash memory content, which contains the FPGA bitstream as well as the ARM CPU code. The FPGA bitstream manipulation alters the exploited AES 256 algorithm in a way that it turns into a linear function which can be broken with 32 known plaintext ciphertext pairs. After the manipulated USB flash drive has been used by the victim, the attacker is able to obtain all user data from the ciphertexts. Our work indeed highlights the security risks and especially the practical relevance of bitstream modification attacks that became realistic due to FPGA bitstream manipulations.
Design and Validation for FPGA Trust under Hardware Trojan Attacks
Venue: IEEE Transactions on Multi Scale Computing Systems

Field programmable gate arrays (FPGAs) are being increasingly used in a wide range of critical applications, including industrial, automotive, medical, and military systems. Since FPGA vendors are typically fabless, it is more economical to outsource device production to off shore facilities. This introduces many opportunities for the insertion of malicious alterations of FPGA devices in the foundry, referred to as hardware Trojan attacks, that can cause logical and physical malfunctions during field operation. The vulnerability of these devices to hardware attacks raises serious security concerns regarding hardware and design assurance. In this paper, we present a taxonomy of FPGA specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. We also present an efficient Trojan detection method for FPGA based on a combined approach of logic testing and side channel analysis. Finally, we propose a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR) to reliably protect against Trojan circuits of varying forms in FPGA devices. We compare ATMR with the conventional TMR approach. The results demonstrate the advantages of ATMR over TMR with respect to power overhead, while maintaining the same or higher level of security and performances as TMR. Further improvement in overhead associated with ATMR is achieved by exploiting reconfiguration and time sharing of resources.
On Reverse Engineering Based Hardware Trojan Detection
Venue: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems

Due to design and fabrication outsourcing to foundries, the problem of malicious modifications to integrated circuits (ICs) also known as hardware Trojans (HTs) has attracted attention in academia as well as industry. To reduce the risks associated with Trojans, researchers have proposed different approaches to detect them. Among these approaches, test time detection approaches have drawn the greatest attention. Many test time approaches assume the existence of a Trojan free (TF) chip/model also known as "golden model." Prior works suggest using reverse engineering (RE) to identify such TF ICs for the golden model. However, they did not state how to do this efficiently. In fact, RE is a very costly process which consumes lots of time and intensive manual effort. It is also very error prone. In this paper, we propose an innovative and robust RE scheme to identify the TF ICs. We reformulate the Trojan detection problem as clustering problem. We then adapt a widely used machine learning method, {K} means clustering, to solve our problem. Simulation results using state of the art tools on several publicly available circuits show that the proposed approach can detect HTs with high accuracy rate. A comparison of this approach with our previously proposed approach  is also conducted. Both the limitations and application scenarios of the two methods are discussed in detail.
SVM based real time hardware Trojan detection for many core platform
Venue: 2016 17th International Symposium on Quality Electronic Design (ISQED)

Hardware Trojans inserted during design or fabrication time by untrustworthy design house or foundry possesses important security concerns. These Trojans lead to un desired change in functionality of the design and provide easy access to sensitive information. Trojans attacks or malicious activities are triggered based on very rare conditions, which can evade test time Trojan detection but can arise during long hours of field operation. In this paper we propose a run time Trojan detection architecture for a custom many core based on Machine Learning technique. We exploit Support Vector Machine (SVM) supervised machine learning algorithms. The Data set is generated based on many core router behavior under normal and Trojan triggered settings. The paper targets different communication attacks triggered by Hardware Trojans, namely core address spoofing, traffic diversion, route looping attack. Support Vector Machine (SVM) algorithm has detection accuracy in the range of 94% to 97%.We implemented a framework for many core architecture with SVM kernel while triggering Trojans based on two different conditions. To demonstrate the performance of proposed security framework, we implement a bio medical seizure detection application as a case study. The algorithm is mapped on 64 processing cores and it takes 2.1mS to execute whereas with the proposed security framework it requires 4.8mS execution time. The Distributed Attack Detection Framework is implemented with each attack detection module having 2% area overhead.
Automatic Feature Selection of Hardware Layout: A Step toward Robust Hardware Trojan Detection
Venue: J. Electron. Test.

Recently, the problem of hardware Trojan detection has gained a tangible significance in academia and industry. That problem, by its nature, is complex, time consuming and error prone due to design and fabrication outsourcing of hardware circuits to external untrusted foundries. Researchers have proposed different approaches, either destructive or non destructive, to overcome that problem. The destructive approach depends on reverse engineering via decapsulation, delayering and layout identification. This paper presents a first trial of a new approach that can afford an automatic and robust solution for the step of layout identification. The proposed technique takes the underlying digital circuit as input, and automatically determines its basic features using Haar feature extractor. Based on that features, a decision tree is trained to act as a weak classifier, which is later boosted, by making use of AdaBoost learning algorithm, to produce a strong classifier in a chain of cascaded classifiers. Accordingly, a classification model is built up to provide an automatic hardware Trojan location and detection tool. To evaluate the proposed model, ISCAS89 benchmark dataset was used for training and testing. The hardware dataset has been altered deliberately to show different Trojan examples namely, Trojan insertion, Trojan deletion and Trojan parametric inside hardware circuits. By investigating the underlying experimental results, the capabilities of the proposed model are evaluated, and the evaluation shows that the approach can detect different hardware Trojan types in different circuit layouts, with high accuracy rate. The proposed approach is not only automatic, but also robust and promising.
A side channel based power analysis technique for hardware trojan detection using statistical learning approach
Venue: 2016 Thirteenth International Conference on Wireless and Optical Communications Networks (WOCN)

Hardware Trojan (HT) is an intentional and the undesired modification of the integrated circuit (IC) and major security issue for the semiconductor industry. HT alters the normal working of IC, can leak the secret information or may damage the IC permanently. Due to the small size of the devices on IC, detection of trojan is very difficult by normal testing methods. In this paper, a side channel based trojan detection technique using power analysis is used to detect the trojan infected IC. Here a trust hub test bench circuit is used to validate trojan detection technique in which the Trojan is inserted on AES 128 bit crypto core. The trojan detection is improved by analyzing the power of IC without trojan (Golden model) and IC with trojan (Trojan model) and by comparing the mean of power traces of both the IC. Statistical data analysis is performed and statistical parameters of power are calculated which are then used as feature vectors. These feature vectors are reduced by using Principal Component Analysis (PCA) algorithm and then classified using Linear Discriminant Analysis (LDA) which discriminates between the Golden and Trojan model and detects the trojan infected IC from the IC under test with 100% accuracy.
An enhanced classification based golden chips free hardware Trojan detection technique
Venue: 2016 IEEE Asian Hardware Oriented Security and Trust (AsianHOST)

Recently, integrated circuits (ICs) are becoming increasing vulnerable to hardware Trojans. Most of existing works require golden chips to provide references for hardware Trojan detection. However, obtaining a golden chip is extremely difficult or even not exists. This paper presents a novel automated hardware Trojan detection technique based on enhanced two class classification while eliminating the need of golden chips after fabrication. We formulate the Trojan detection problem into a classification problem, and train the algorithms using simulated ICs during IC design flow. The algorithm will form a classifier which can automatically identify Trojan free and Trojan inserted ICs during test time. Moreover, we propose several optional optimized methods to enhance the technique: 1) we propose adaptive iterative optimization of one algorithm by focusing on errors, in which the weight adjusting are based on how successful the algorithm was in the previous iteration; 2) we analyze the misclassified ICs' numbers of certain algorithms and present the matched algorithm pairs; 3) we alter the algorithms to take into account of the costs of making different detection decisions, called cost sensitive detection; 4) we present the suitable algorithm settings against high level of process variations. Experiment results on benchmark circuits show that the proposed technique can detect both known Trojans and various unknown Trojans with high accuracy and recall (90%~100% Since we didn't add any extra circuit to the design, there is no overhead of this approach.
How secure is split manufacturing in preventing hardware trojan?
Venue: 2016 IEEE Asian Hardware Oriented Security and Trust (AsianHOST)

With the trend of outsourcing fabrication, split manufacturing is regarded as a promising way to both provide the high end nodes in untrusted external foundries and protect the design from potential attackers. However, in this work, we show that split manufacturing is not inherently secure. A hardware trojan attacker can still discover necessary information with a simulated annealing based attack approach at the placement level. We further propose a defense approach by moving the insecure gates away from their easily attacked candidate locations. Experimental results on benchmark circuits show the effectiveness of our proposed methods.
Multilevel Inverter Topologies With Reduced Device Count: A Review
Venue: IEEE Transactions on Power Electronics

Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of high power medium voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analyzed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application.
Voltage Stability and Reactive Power Sharing in Inverter Based Microgrids With Consensus Based Distributed Voltage Control
Venue: IEEE Transactions on Control Systems Technology

We propose a consensus based distributed voltage control (DVC) that solves the problem of reactive power sharing in autonomous inverter based microgrids with dominantly inductive power lines and arbitrary electrical topology. Opposed to other control strategies available thus far, the control presented here does guarantee a desired reactive power distribution in steady state while only requiring distributed communication among inverters, i.e. no central computing nor communication unit is needed. For inductive impedance loads and under the assumption of small phase angle differences between the output voltages of the inverters, we prove that the choice of the control parameters uniquely determines the corresponding equilibrium point of the closed loop voltage and reactive power dynamics. In addition, for the case of uniform time constants of the power measurement filters, a necessary and sufficient condition for local exponential stability of that equilibrium point is given. The compatibility of the DVC with the usual frequency droop control for inverters is shown and the performance of the proposed DVC is compared with the usual voltage droop control via simulation of a microgrid based on the Conseil International des Grands Reseaux Electriques (CIGRE) benchmark medium voltage distribution network.
Sensor Less Five Level Packed U Cell (PUC5) Inverter Operating in Stand Alone and Grid Connected Modes
Venue: IEEE Transactions on Industrial Informatics

In this paper, a new mode of operation has been introduced for packed U cell (PUC) inverter. A sensor less voltage control based on redundant switching states is designed for the five level packed U cell (PUC5) inverter, which is integrated into switching process. The sensor less voltage control is in charge of fixing the dc capacitor voltage at half of the dc source value results in generating symmetric five level voltage waveform at the output with low harmonic distortion. The sensor less voltage regulator reduces the complexity of the control system, which makes the proposed converter appealing for industrial applications. An external current controller has been applied for grid connected application of the introduced sensor less PUC5 to inject active and reactive power from inverter to the grid with arbitrary power factor, while the PUC auxiliary dc bus is regulated only by sensor less controller combined with new switching pattern. Experimental results obtained in stand alone and grid connected operating modes of proposed PUC5 inverter prove the fast response and good dynamic performance of the designed sensor less voltage control in balancing the dc capacitor voltage at desired level.