neulab/tldr huggingface dataset:
-munix=93 provides the same predefines as GCC 3.3 and 3.4.  -munix=95 provides additional predefines for "XOPEN_UNIX" and "_XOPEN_SOURCE_EXTENDED", and the startfile unix95.o.  -munix=98 provides additional predefines for "_XOPEN_UNIX", "_XOPEN_SOURCE_EXTENDED", "_INCLUDE__STDC_A1_SOURCE" and "_INCLUDE_XOPEN_SOURCE_500", and the startfile unix98.o.
It is important to note that this option changes the interfaces for various library routines.  It also affects the operational behavior of the C library.  Thus, extreme care is needed in using this option.
Library code that is intended to operate with more than one UNIX standard must test, set and restore the variable "__xpg4_extended_mask" as appropriate.  Most GNU software doesn't provide this capability.
-nolibdld Suppress the generation of link options to search libdld.sl when the -static option is specified on HP-UX 10 and later.
-static The HP-UX implementation of setlocale in libc has a dependency on libdld.sl.  There isn't an archive version of libdld.sl.  Thus, when the -static option is specified, special link options are needed to resolve this dependency.
On HP-UX 10 and later, the GCC driver adds the necessary options to link with libdld.sl when the -static option is specified.  This causes the resulting binary to be dynamic.  On the 64-bit port, the linkers generate dynamic binaries by default in any case.  The -nolibdld option can be used to prevent the GCC driver from adding these link options.
-threads Add support for multithreading with the dce thread library under HP- UX.  This option sets flags for both the preprocessor and linker.
IA-64 Options
These are the -m options defined for the Intel IA-64 architecture.
-mbig-endian Generate code for a big-endian target.  This is the default for HP- UX.
-mlittle-endian Generate code for a little-endian target.  This is the default for AIX5 and GNU/Linux.
-mgnu-as -mno-gnu-as Generate (or don't) code for the GNU assembler.  This is the default.
-mgnu-ld -mno-gnu-ld Generate (or don't) code for the GNU linker.  This is the default.
-mno-pic Generate code that does not use a global pointer register.  The result is not position independent code, and violates the IA-64 ABI.
-mvolatile-asm-stop -mno-volatile-asm-stop Generate (or don't) a stop bit immediately before and after volatile asm statements.
-mregister-names -mno-register-names Generate (or don't) in, loc, and out register names for the stacked registers.  This may make assembler output more readable.
-mno-sdata -msdata Disable (or enable) optimizations that use the small data section. This may be useful for working around optimizer bugs.
-mconstant-gp Generate code that uses a single constant global pointer value.  This is useful when compiling kernel code.
-mauto-pic Generate code that is self-relocatable.  This implies -mconstant-gp. This is useful when compiling firmware code.
-minline-float-divide-min-latency Generate code for inline divides of floating-point values using the minimum latency algorithm.
-minline-float-divide-max-throughput Generate code for inline divides of floating-point values using the maximum throughput algorithm.
-mno-inline-float-divide Do not generate inline code for divides of floating-point values.
-minline-int-divide-min-latency Generate code for inline divides of integer values using the minimum latency algorithm.
-minline-int-divide-max-throughput Generate code for inline divides of integer values using the maximum throughput algorithm.
-mno-inline-int-divide Do not generate inline code for divides of integer values.
-minline-sqrt-min-latency Generate code for inline square roots using the minimum latency algorithm.
-minline-sqrt-max-throughput Generate code for inline square roots using the maximum throughput algorithm.
-mno-inline-sqrt Do not generate inline code for "sqrt".
-mfused-madd -mno-fused-madd Do (don't) generate code that uses the fused multiply/add or multiply/subtract instructions.  The default is to use these instructions.
-mno-dwarf2-asm -mdwarf2-asm Don't (or do) generate assembler code for the DWARF line number debugging info.  This may be useful when not using the GNU assembler.
-mearly-stop-bits -mno-early-stop-bits Allow stop bits to be placed earlier than immediately preceding the instruction that triggered the stop bit.  This can improve instruction scheduling, but does not always do so.
-mtls-size=tls-size Specify bit size of immediate TLS offsets.  Valid values are 14, 22, and 64.
-mtune=cpu-type Tune the instruction scheduling for a particular CPU, Valid values are itanium, itanium1, merced, itanium2, and mckinley.
-milp32 -mlp64 Generate code for a 32-bit or 64-bit environment.  The 32-bit environment sets int, long and pointer to 32 bits.  The 64-bit environment sets int to 32 bits and long and pointer to 64 bits. These are HP-UX specific flags.
-mno-sched-br-data-spec -msched-br-data-spec (Dis/En)able data speculative scheduling before reload.  This results in generation of "ld.a" instructions and the corresponding check instructions ("ld.c" / "chk.a").  The default setting is disabled.
-msched-ar-data-spec -mno-sched-ar-data-spec (En/Dis)able data speculative scheduling after reload.  This results in generation of "ld.a" instructions and the corresponding check instructions ("ld.c" / "chk.a").  The default setting is enabled.
-mno-sched-control-spec -msched-control-spec (Dis/En)able control speculative scheduling.  This feature is available only during region scheduling (i.e. before reload).  This results in generation of the "ld.s" instructions and the corresponding check instructions "chk.s".  The default setting is disabled.
-msched-br-in-data-spec -mno-sched-br-in-data-spec (En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads before reload.  This is effective only with -msched-br-data-spec enabled.  The default setting is enabled.
-msched-ar-in-data-spec -mno-sched-ar-in-data-spec (En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads after reload.  This is effective only with -msched-ar-data-spec enabled.  The default setting is enabled.
-msched-in-control-spec -mno-sched-in-control-spec (En/Dis)able speculative scheduling of the instructions that are dependent on the control speculative loads.  This is effective only with -msched-control-spec enabled.  The default setting is enabled.
-mno-sched-prefer-non-data-spec-insns -msched-prefer-non-data-spec-insns If enabled, data-speculative instructions are chosen for schedule only if there are no other choices at the moment.  This makes the use of the data speculation much more conservative.  The default setting is disabled.
-mno-sched-prefer-non-control-spec-insns -msched-prefer-non-control-spec-insns If enabled, control-speculative instructions are chosen for schedule only if there are no other choices at the moment.  This makes the use of the control speculation much more conservative.  The default setting is disabled.
-mno-sched-count-spec-in-critical-path -msched-count-spec-in-critical-path If enabled, speculative dependencies are considered during computation of the instructions priorities.  This makes the use of the speculation a bit more conservative.  The default setting is disabled.
-msched-spec-ldc Use a simple data speculation check.  This option is on by default.
-msched-control-spec-ldc Use a simple check for control speculation.  This option is on by default.
-msched-stop-bits-after-every-cycle Place a stop bit after every cycle when scheduling.  This option is on by default.
-msched-fp-mem-deps-zero-cost Assume that floating-point stores and loads are not likely to cause a conflict when placed into the same instruction group.  This option is disabled by default.
-msel-sched-dont-check-control-spec Generate checks for control speculation in selective scheduling. This flag is disabled by default.
-msched-max-memory-insns=max-insns Limit on the number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same instruction group. Frequently useful to prevent cache bank conflicts.  The default value is 1.
-msched-max-memory-insns-hard-limit Makes the limit specified by msched-max-memory-insns a hard limit, disallowing more than that number in an instruction group. Otherwise, the limit is "soft", meaning that non-memory operations are preferred when the limit is reached, but memory operations may still be scheduled.
LM32 Options
These -m options are defined for the LatticeMico32 architecture:
-mbarrel-shift-enabled Enable barrel-shift instructions.
-mdivide-enabled Enable divide and modulus instructions.
-mmultiply-enabled Enable multiply instructions.
-msign-extend-enabled Enable sign extend instructions.
-muser-enabled Enable user-defined instructions.
M32C Options
-mcpu=name Select the CPU for which code is generated.  name may be one of r8c for the R8C/Tiny series, m16c for the M16C (up to /60) series, m32cm for the M16C/80 series, or m32c for the M32C/80 series.
-msim Specifies that the program will be run on the simulator.  This causes an alternate runtime library to be linked in which supports, for example, file I/O.  You must not use this option when generating programs that will run on real hardware; you must provide your own runtime library for whatever I/O functions are needed.
-memregs=number Specifies the number of memory-based pseudo-registers GCC uses during code generation.  These pseudo-registers are used like real registers, so there is a tradeoff between GCC's ability to fit the code into available registers, and the performance penalty of using memory instead of registers.  Note that all modules in a program must be compiled with the same value for this option.  Because of that, you must not use this option with GCC's default runtime libraries.
M32R/D Options
These -m options are defined for Renesas M32R/D architectures:
-m32r2 Generate code for the M32R/2.
-m32rx Generate code for the M32R/X.
-m32r Generate code for the M32R.  This is the default.
-mmodel=small Assume all objects live in the lower 16MB of memory (so that their addresses can be loaded with the "ld24" instruction), and assume all subroutines are reachable with the "bl" instruction.  This is the default.
The addressability of a particular object can be set with the "model" attribute.
-mmodel=medium Assume objects may be anywhere in the 32-bit address space (the compiler generates "seth/add3" instructions to load their addresses), and assume all subroutines are reachable with the "bl" instruction.
-mmodel=large Assume objects may be anywhere in the 32-bit address space (the compiler generates "seth/add3" instructions to load their addresses), and assume subroutines may not be reachable with the "bl" instruction (the compiler generates the much slower "seth/add3/jl" instruction sequence).
-msdata=none Disable use of the small data area.  Variables are put into one of ".data", ".bss", or ".rodata" (unless the "section" attribute has been specified).  This is the default.
The small data area consists of sections ".sdata" and ".sbss". Objects may be explicitly put in the small data area with the "section" attribute using one of these sections.
-msdata=sdata Put small global and static data in the small data area, but do not generate special code to reference them.
-msdata=use Put small global and static data in the small data area, and generate special instructions to reference them.
-G num Put global and static objects less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS sections.  The default value of num is 8.  The -msdata option must be set to one of sdata or use for this option to have any effect.
All modules should be compiled with the same -G num value.  Compiling with different values of num may or may not work; if it doesn't the linker gives an error message---incorrect code is not generated.
-mdebug Makes the M32R-specific code in the compiler display some statistics that might help in debugging programs.
-malign-loops Align all loops to a 32-byte boundary.
-mno-align-loops Do not enforce a 32-byte alignment for loops.  This is the default.
-missue-rate=number Issue number instructions per cycle.  number can only be 1 or 2.
-mbranch-cost=number number can only be 1 or 2.  If it is 1 then branches are preferred over conditional code, if it is 2, then the opposite applies.
-mflush-trap=number Specifies the trap number to use to flush the cache.  The default is 12.  Valid numbers are between 0 and 15 inclusive.
-mno-flush-trap Specifies that the cache cannot be flushed by using a trap.
-mflush-func=name Specifies the name of the operating system function to call to flush the cache.  The default is _flush_cache, but a function call is only used if a trap is not available.
-mno-flush-func Indicates that there is no OS function for flushing the cache.
M680x0 Options
These are the -m options defined for M680x0 and ColdFire processors.  The default settings depend on which architecture was selected when the compiler was configured; the defaults for the most common choices are given below.
-march=arch Generate code for a specific M680x0 or ColdFire instruction set architecture.  Permissible values of arch for M680x0 architectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32.  ColdFire architectures are selected according to Freescale's ISA classification and the permissible values are: isaa, isaaplus, isab and isac.
GCC defines a macro "__mcfarch__" whenever it is generating code for a ColdFire target.  The arch in this macro is one of the -march arguments given above.
When used together, -march and -mtune select code that runs on a family of similar processors but that is optimized for a particular microarchitecture.
-mcpu=cpu Generate code for a specific M680x0 or ColdFire processor.  The M680x0 cpus are: 68000, 68010, 68020, 68030, 68040, 68060, 68302, 68332 and cpu32.  The ColdFire cpus are given by the table below, which also classifies the CPUs into families:
Family : -mcpu arguments 51 : 51 51ac 51ag 51cn 51em 51je 51jf 51jg 51jm 51mm 51qe 51qm 5206 : 5202 5204 5206 5206e : 5206e 5208 : 5207 5208 5211a : 5210a 5211a 5213 : 5211 5212 5213 5216 : 5214 5216 52235 : 52230 52231 52232 52233 52234 52235 5225 : 5224 5225 52259 : 52252 52254 52255 52256 52258 52259 5235 : 5232 5233 5234 5235 523x 5249 : 5249 5250 : 5250 5271 : 5270 5271 5272 : 5272 5275 : 5274 5275 5282 : 5280 5281 5282 528x 53017 : 53011 53012 53013 53014 53015 53016 53017 5307 : 5307 5329 : 5327 5328 5329 532x 5373 : 5372 5373 537x 5407 : 5407 5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485
-mcpu=cpu overrides -march=arch if arch is compatible with cpu. Other combinations of -mcpu and -march are rejected.
GCC defines the macro "__mcf_cpu_cpu" when ColdFire target cpu is selected.  It also defines "__mcf_family_family", where the value of family is given by the table above.
-mtune=tune Tune the code for a particular microarchitecture within the constraints set by -march and -mcpu.  The M680x0 microarchitectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32.  The ColdFire microarchitectures are: cfv1, cfv2, cfv3, cfv4 and cfv4e.
You can also use -mtune=68020-40 for code that needs to run relatively well on 68020, 68030 and 68040 targets.  -mtune=68020-60 is similar but includes 68060 targets as well.  These two options select the same tuning decisions as -m68020-40 and -m68020-60 respectively.
GCC defines the macros "__mcarch" and "__mcarch__" when tuning for 680x0 architecture arch.  It also defines "mcarch" unless either -ansi or a non-GNU -std option is used.  If GCC is tuning for a range of architectures, as selected by -mtune=68020-40 or -mtune=68020-60, it defines the macros for every architecture in the range.
GCC also defines the macro "__muarch__" when tuning for ColdFire microarchitecture uarch, where uarch is one of the arguments given above.
-m68000 -mc68000 Generate output for a 68000.  This is the default when the compiler is configured for 68000-based systems.  It is equivalent to -march=68000.
Use this option for microcontrollers with a 68000 or EC000 core, including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
-m68010 Generate output for a 68010.  This is the default when the compiler is configured for 68010-based systems.  It is equivalent to -march=68010.
-m68020 -mc68020 Generate output for a 68020.  This is the default when the compiler is configured for 68020-based systems.  It is equivalent to -march=68020.
-m68030 Generate output for a 68030.  This is the default when the compiler is configured for 68030-based systems.  It is equivalent to -march=68030.
-m68040 Generate output for a 68040.  This is the default when the compiler is configured for 68040-based systems.  It is equivalent to -march=68040.
This option inhibits the use of 68881/68882 instructions that have to be emulated by software on the 68040.  Use this option if your 68040 does not have code to emulate those instructions.
-m68060 Generate output for a 68060.  This is the default when the compiler is configured for 68060-based systems.  It is equivalent to -march=68060.
This option inhibits the use of 68020 and 68881/68882 instructions that have to be emulated by software on the 68060.  Use this option if your 68060 does not have code to emulate those instructions.
-mcpu32 Generate output for a CPU32.  This is the default when the compiler is configured for CPU32-based systems.  It is equivalent to -march=cpu32.
Use this option for microcontrollers with a CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, 68336, 68340, 68341, 68349 and 68360.
-m5200 Generate output for a 520X ColdFire CPU.  This is the default when the compiler is configured for 520X-based systems.  It is equivalent to -mcpu=5206, and is now deprecated in favor of that option.
Use this option for microcontroller with a 5200 core, including the MCF5202, MCF5203, MCF5204 and MCF5206.
-m5206e Generate output for a 5206e ColdFire CPU.  The option is now deprecated in favor of the equivalent -mcpu=5206e.
-m528x Generate output for a member of the ColdFire 528X family.  The option is now deprecated in favor of the equivalent -mcpu=528x.
-m5307 Generate output for a ColdFire 5307 CPU.  The option is now deprecated in favor of the equivalent -mcpu=5307.
-m5407 Generate output for a ColdFire 5407 CPU.  The option is now deprecated in favor of the equivalent -mcpu=5407.
-mcfv4e Generate output for a ColdFire V4e family CPU (e.g. 547x/548x).  This includes use of hardware floating-point instructions.  The option is equivalent to -mcpu=547x, and is now deprecated in favor of that option.
-m68020-40 Generate output for a 68040, without using any of the new instructions.  This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040.  The generated code does use the 68881 instructions that are emulated on the 68040.
The option is equivalent to -march=68020 -mtune=68020-40.
-m68020-60 Generate output for a 68060, without using any of the new instructions.  This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040.  The generated code does use the 68881 instructions that are emulated on the 68060.
The option is equivalent to -march=68020 -mtune=68020-60.
-mhard-float -m68881 Generate floating-point instructions.  This is the default for 68020 and above, and for ColdFire devices that have an FPU.  It defines the macro "__HAVE_68881__" on M680x0 targets and "__mcffpu__" on ColdFire targets.
-msoft-float Do not generate floating-point instructions; use library calls instead.  This is the default for 68000, 68010, and 68832 targets. It is also the default for ColdFire devices that have no FPU.
-mdiv -mno-div Generate (do not generate) ColdFire hardware divide and remainder instructions.  If -march is used without -mcpu, the default is "on" for ColdFire architectures and "off" for M680x0 architectures. Otherwise, the default is taken from the target CPU (either the default CPU, or the one specified by -mcpu).  For example, the default is "off" for -mcpu=5206 and "on" for -mcpu=5206e.
GCC defines the macro "__mcfhwdiv__" when this option is enabled.
-mshort Consider type "int" to be 16 bits wide, like "short int". Additionally, parameters passed on the stack are also aligned to a 16-bit boundary even on targets whose API mandates promotion to 32-bit.
-mno-short Do not consider type "int" to be 16 bits wide.  This is the default.
-mnobitfield -mno-bitfield Do not use the bit-field instructions.  The -m68000, -mcpu32 and -m5200 options imply -mnobitfield.
-mbitfield Do use the bit-field instructions.  The -m68020 option implies -mbitfield.  This is the default if you use a configuration designed for a 68020.
-mrtd Use a different function-calling convention, in which functions that take a fixed number of arguments return with the "rtd" instruction, which pops their arguments while returning.  This saves one instruction in the caller since there is no need to pop the arguments there.
This calling convention is incompatible with the one normally used on Unix, so you cannot use it if you need to call libraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that take variable numbers of arguments (including "printf"); otherwise incorrect code is generated for calls to those functions.
In addition, seriously incorrect code results if you call a function with too many arguments.  (Normally, extra arguments are harmlessly ignored.)
The "rtd" instruction is supported by the 68010, 68020, 68030, 68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
The default is -mno-rtd.
-malign-int -mno-align-int Control whether GCC aligns "int", "long", "long long", "float", "double", and "long double" variables on a 32-bit boundary (-malign-int) or a 16-bit boundary (-mno-align-int).  Aligning variables on 32-bit boundaries produces code that runs somewhat faster on processors with 32-bit busses at the expense of more memory.
Warning: if you use the -malign-int switch, GCC aligns structures containing the above types differently than most published application binary interface specifications for the m68k.
Use the pc-relative addressing mode of the 68000 directly, instead of using a global offset table.  At present, this option implies -fpic, allowing at most a 16-bit offset for pc-relative addressing.  -fPIC is not presently supported with -mpcrel, though this could be supported for 68020 and higher processors.
-mno-strict-align -mstrict-align Do not (do) assume that unaligned memory references are handled by the system.
-msep-data Generate code that allows the data segment to be located in a different area of memory from the text segment.  This allows for execute-in-place in an environment without virtual memory management. This option implies -fPIC.
-mid-shared-library Generate code that supports shared libraries via the library ID method.  This allows for execute-in-place and shared libraries in an environment without virtual memory management.  This option implies -fPIC.
-mshared-library-id=n Specifies the identification number of the ID-based shared library being compiled.  Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library, but is no more space- or time-efficient than omitting this option.
-mxgot -mno-xgot When generating position-independent code for ColdFire, generate code that works if the GOT has more than 8192 entries.  This code is larger and slower than code generated without this option.  On M680x0 processors, this option is not needed; -fPIC suffices.
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k.  Anything larger causes the linker to report an error such as:
relocation truncated to fit: R_68K_GOT16O foobar
If this happens, you should recompile your code with -mxgot.  It should then work with very large GOTs.  However, code generated with -mxgot is less efficient, since it takes 4 instructions to fetch the value of a global symbol.
Note that some linkers, including newer versions of the GNU linker, can create multiple GOTs and sort GOT entries.  If you have such a linker, you should only need to use -mxgot when compiling a single object file that accesses more than 8192 GOT entries.  Very few do.
These options have no effect unless GCC is generating position- independent code.
-mlong-jump-table-offsets Use 32-bit offsets in "switch" tables.  The default is to use 16-bit offsets.
MCore Options
These are the -m options defined for the Motorola M*Core processors.
-mhardlit -mno-hardlit Inline constants into the code stream if it can be done in two instructions or less.
-mdiv -mno-div Use the divide instruction.  (Enabled by default).
-mrelax-immediate -mno-relax-immediate Allow arbitrary-sized immediates in bit operations.
-mwide-bitfields -mno-wide-bitfields Always treat bit-fields as "int"-sized.
-m4byte-functions -mno-4byte-functions Force all functions to be aligned to a 4-byte boundary.
-mcallgraph-data -mno-callgraph-data Emit callgraph information.
-mslow-bytes -mno-slow-bytes Prefer word access when reading byte quantities.
-mlittle-endian -mbig-endian Generate code for a little-endian target.
-m210 -m340 Generate code for the 210 processor.
-mno-lsim Assume that runtime support has been provided and so omit the simulator library (libsim.a) from the linker command line.
-mstack-increment=size Set the maximum amount for a single stack increment operation.  Large values can increase the speed of programs that contain functions that need a large amount of stack space, but they can also trigger a segmentation fault if the stack is extended too much.  The default value is 0x1000.
MeP Options
-mabsdiff Enables the "abs" instruction, which is the absolute difference between two registers.
-mall-opts Enables all the optional instructions---average, multiply, divide, bit operations, leading zero, absolute difference, min/max, clip, and saturation.
-maverage Enables the "ave" instruction, which computes the average of two registers.
-mbased=n Variables of size n bytes or smaller are placed in the ".based" section by default.  Based variables use the $tp register as a base register, and there is a 128-byte limit to the ".based" section.
-mbitops Enables the bit operation instructions---bit test ("btstm"), set ("bsetm"), clear ("bclrm"), invert ("bnotm"), and test-and-set ("tas").
-mc=name Selects which section constant data is placed in.  name may be tiny, near, or far.
-mclip Enables the "clip" instruction.  Note that -mclip is not useful unless you also provide -mminmax.
-mconfig=name Selects one of the built-in core configurations.  Each MeP chip has one or more modules in it; each module has a core CPU and a variety of coprocessors, optional instructions, and peripherals.  The "MeP-Integrator" tool, not part of GCC, provides these configurations through this option; using this option is the same as using all the corresponding command-line options.  The default configuration is default.
-mcop Enables the coprocessor instructions.  By default, this is a 32-bit coprocessor.  Note that the coprocessor is normally enabled via the -mconfig= option.
-mcop32 Enables the 32-bit coprocessor's instructions.
-mcop64 Enables the 64-bit coprocessor's instructions.
-mivc2 Enables IVC2 scheduling.  IVC2 is a 64-bit VLIW coprocessor.
-mdc Causes constant variables to be placed in the ".near" section.
-mdiv Enables the "div" and "divu" instructions.
-meb Generate big-endian code.
-mel Generate little-endian code.
-mio-volatile Tells the compiler that any variable marked with the "io" attribute is to be considered volatile.
-ml Causes variables to be assigned to the ".far" section by default.
-mleadz Enables the "leadz" (leading zero) instruction.
-mm Causes variables to be assigned to the ".near" section by default.
-mminmax Enables the "min" and "max" instructions.
-mmult Enables the multiplication and multiply-accumulate instructions.
-mno-opts Disables all the optional instructions enabled by -mall-opts.
-mrepeat Enables the "repeat" and "erepeat" instructions, used for low- overhead looping.
-ms Causes all variables to default to the ".tiny" section.  Note that there is a 65536-byte limit to this section.  Accesses to these variables use the %gp base register.
-msatur Enables the saturation instructions.  Note that the compiler does not currently generate these itself, but this option is included for compatibility with other tools, like "as".
-msdram Link the SDRAM-based runtime instead of the default ROM-based runtime.
-msim Link the simulator run-time libraries.
-msimnovec Link the simulator runtime libraries, excluding built-in support for reset and exception vectors and tables.
-mtf Causes all functions to default to the ".far" section.  Without this option, functions default to the ".near" section.
-mtiny=n Variables that are n bytes or smaller are allocated to the ".tiny" section.  These variables use the $gp base register.  The default for this option is 4, but note that there's a 65536-byte limit to the ".tiny" section.
MicroBlaze Options
-msoft-float Use software emulation for floating point (default).
-mhard-float Use hardware floating-point instructions.
-mmemcpy Do not optimize block moves, use "memcpy".
-mno-clearbss This option is deprecated.  Use -fno-zero-initialized-in-bss instead.
-mcpu=cpu-type Use features of, and schedule code for, the given CPU.  Supported values are in the format vX.YY.Z, where X is a major version, YY is the minor version, and Z is compatibility code.  Example values are v3.00.a, v4.00.b, v5.00.a, v5.00.b, v6.00.a.
-mxl-soft-mul Use software multiply emulation (default).
-mxl-soft-div Use software emulation for divides (default).
-mxl-barrel-shift Use the hardware barrel shifter.
-mxl-pattern-compare Use pattern compare instructions.
-msmall-divides Use table lookup optimization for small signed integer divisions.
-mxl-stack-check This option is deprecated.  Use -fstack-check instead.
-mxl-gp-opt Use GP-relative ".sdata"/".sbss" sections.
-mxl-multiply-high Use multiply high instructions for high part of 32x32 multiply.
-mxl-float-convert Use hardware floating-point conversion instructions.
-mxl-float-sqrt Use hardware floating-point square root instruction.
-mlittle-endian Generate code for a little-endian target.
-mxl-reorder Use reorder instructions (swap and byte reversed load/store).
-mxl-mode-app-model Select application model app-model.  Valid models are
executable normal executable (default), uses startup code crt0.o.
-mpic-data-is-text-relative Assume that the displacement between the text and data segments is fixed at static link time.  This allows data to be referenced by offset from start of text address instead of GOT since PC- relative addressing is not supported.
xmdstub for use with Xilinx Microprocessor Debugger (XMD) based software intrusive debug agent called xmdstub. This uses startup file crt1.o and sets the start address of the program to 0x800.
bootstrap for applications that are loaded using a bootloader.  This model uses startup file crt2.o which does not contain a processor reset vector handler. This is suitable for transferring control on a processor reset to the bootloader rather than the application.
novectors for applications that do not require any of the MicroBlaze vectors. This option may be useful for applications running within a monitoring application. This model uses crt3.o as a startup file.
Option -xl-mode-app-model is a deprecated alias for -mxl-mode-app- model.
MIPS Options
-EB Generate big-endian code.
-EL Generate little-endian code.  This is the default for mips*el-*-* configurations.
-march=arch Generate code that runs on arch, which can be the name of a generic MIPS ISA, or the name of a particular processor.  The ISA names are: mips1, mips2, mips3, mips4, mips32, mips32r2, mips32r3, mips32r5, mips32r6, mips64, mips64r2, mips64r3, mips64r5 and mips64r6.  The processor names are: 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, 5kc, 5kf, 20kc, 24kc, 24kf2_1, 24kf1_1, 24kec, 24kef2_1, 24kef1_1, 34kc, 34kf2_1, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf1_1, i6400, i6500, interaptiv, loongson2e, loongson2f, loongson3a, gs464, gs464e, gs264e, m4k, m14k, m14kc, m14ke, m14kec, m5100, m5101, octeon, octeon+, octeon2, octeon3, orion, p5600, p6600, r2000, r3000, r3900, r4000, r4400, r4600, r4650, r4700, r5900, r6000, r8000, rm7000, rm9000, r10000, r12000, r14000, r16000, sb1, sr71000, vr4100, vr4111, vr4120, vr4130, vr4300, vr5000, vr5400, vr5500, xlr and xlp.  The special value from-abi selects the most compatible architecture for the selected ABI (that is, mips1 for 32-bit ABIs and mips3 for 64-bit ABIs).
The native Linux/GNU toolchain also supports the value native, which selects the best architecture option for the host processor. -march=native has no effect if GCC does not recognize the processor.
In processor names, a final 000 can be abbreviated as k (for example, -march=r2k).  Prefixes are optional, and vr may be written r.
Names of the form nf2_1 refer to processors with FPUs clocked at half the rate of the core, names of the form nf1_1 refer to processors with FPUs clocked at the same rate as the core, and names of the form nf3_2 refer to processors with FPUs clocked a ratio of 3:2 with respect to the core.  For compatibility reasons, nf is accepted as a synonym for nf2_1 while nx and bfx are accepted as synonyms for nf1_1.
GCC defines two macros based on the value of this option.  The first is "_MIPS_ARCH", which gives the name of target architecture, as a string.  The second has the form "_MIPS_ARCH_foo", where foo is the capitalized value of "_MIPS_ARCH".  For example, -march=r2000 sets "_MIPS_ARCH" to "r2000" and defines the macro "_MIPS_ARCH_R2000".
Note that the "_MIPS_ARCH" macro uses the processor names given above.  In other words, it has the full prefix and does not abbreviate 000 as k.  In the case of from-abi, the macro names the resolved architecture (either "mips1" or "mips3").  It names the default architecture when no -march option is given.
-mtune=arch Optimize for arch.  Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations.  The list of arch values is the same as for -march.
When this option is not used, GCC optimizes for the processor specified by -march.  By using -march and -mtune together, it is possible to generate code that runs on a family of processors, but optimize the code for one particular member of that family.
-mtune defines the macros "_MIPS_TUNE" and "_MIPS_TUNE_foo", which work in the same way as the -march ones described above.
-mips1 Equivalent to -march=mips1.
-mips2 Equivalent to -march=mips2.
-mips3 Equivalent to -march=mips3.
-mips4 Equivalent to -march=mips4.
-mips32 Equivalent to -march=mips32.
-mips32r3 Equivalent to -march=mips32r3.
-mips32r5 Equivalent to -march=mips32r5.
-mips32r6 Equivalent to -march=mips32r6.
-mips64 Equivalent to -march=mips64.
-mips64r2 Equivalent to -march=mips64r2.
-mips64r3 Equivalent to -march=mips64r3.
-mips64r5 Equivalent to -march=mips64r5.
-mips64r6 Equivalent to -march=mips64r6.
-mips16 -mno-mips16 Generate (do not generate) MIPS16 code.  If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.
MIPS16 code generation can also be controlled on a per-function basis by means of "mips16" and "nomips16" attributes.
-mflip-mips16 Generate MIPS16 code on alternating functions.  This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code.
-minterlink-compressed -mno-interlink-compressed Require (do not require) that code using the standard (uncompressed) MIPS ISA be link-compatible with MIPS16 and microMIPS code, and vice versa.
For example, code using the standard ISA encoding cannot jump directly to MIPS16 or microMIPS code; it must either use a call or an indirect jump.  -minterlink-compressed therefore disables direct jumps unless GCC knows that the target of the jump is not compressed.
-minterlink-mips16 -mno-interlink-mips16 Aliases of -minterlink-compressed and -mno-interlink-compressed. These options predate the microMIPS ASE and are retained for backwards compatibility.
-mabi=32 -mabi=o64 -mabi=n32 -mabi=64 -mabi=eabi Generate code for the given ABI.
Note that the EABI has a 32-bit and a 64-bit variant.  GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.
For information about the O64 ABI, see <http://gcc.gnu.org/projects/mipso64-abi.html>.
GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide.  You can select this combination with -mabi=32 -mfp64.  This ABI relies on the "mthc1" and "mfhc1" instructions and is therefore only supported for MIPS32R2, MIPS32R3 and MIPS32R5 processors.
The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers.  For example, scalar floating-point values are returned in $f0 only, not a $f0/$f1 pair. The set of call-saved registers also remains the same in that the even-numbered double-precision registers are saved.
Two additional variants of the o32 ABI are supported to enable a transition from 32-bit to 64-bit registers.  These are FPXX (-mfpxx) and FP64A (-mfp64 -mno-odd-spreg).  The FPXX extension mandates that all code must execute correctly when run using 32-bit or 64-bit registers.  The code can be interlinked with either FP32 or FP64, but not both.  The FP64A extension is similar to the FP64 extension but forbids the use of odd-numbered single-precision registers.  This can be used in conjunction with the "FRE" mode of FPUs in MIPS32R5 processors and allows both FP32 and FP64A code to interlink and run in the same process without changing FPU modes.
-mabicalls -mno-abicalls Generate (do not generate) code that is suitable for SVR4-style dynamic objects.  -mabicalls is the default for SVR4-based systems.
-mshared -mno-shared Generate (do not generate) code that is fully position-independent, and that can therefore be linked into shared libraries.  This option only affects -mabicalls.
All -mabicalls code has traditionally been position-independent, regardless of options like -fPIC and -fpic.  However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols.  It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions.  This mode is selected by -mno-shared.
-mno-shared depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker.  However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects.  Using -mno-shared generally makes executables both smaller and quicker.
-mshared is the default.
-mplt -mno-plt Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations.  This option only affects -mno-shared -mabicalls.  For the n64 ABI, this option has no effect without -msym32.
You can make -mplt the default by configuring GCC with --with-mips-plt.  The default is -mno-plt otherwise.
-mxgot -mno-xgot Lift (do not lift) the usual restrictions on the size of the global offset table.
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with -mxgot.  This works with very large GOTs, although the code is also less efficient, since it takes three instructions to fetch the value of a global symbol.
Note that some linkers can create multiple GOTs.  If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k's worth of GOT entries.  Very few do.
These options have no effect unless GCC is generating position independent code.
-mgp32 Assume that general-purpose registers are 32 bits wide.
-mgp64 Assume that general-purpose registers are 64 bits wide.
-mfp32 Assume that floating-point registers are 32 bits wide.
-mfp64 Assume that floating-point registers are 64 bits wide.
-mfpxx Do not assume the width of floating-point registers.
-mhard-float Use floating-point coprocessor instructions.
-msoft-float Do not use floating-point coprocessor instructions.  Implement floating-point calculations using library calls instead.
-mno-float Equivalent to -msoft-float, but additionally asserts that the program being compiled does not perform any floating-point operations.  This option is presently supported only by some bare-metal MIPS configurations, where it may select a special set of libraries that lack all floating-point support (including, for example, the floating-point "printf" formats).  If code compiled with -mno-float accidentally contains floating-point operations, it is likely to suffer a link-time or run-time failure.
-msingle-float Assume that the floating-point coprocessor only supports single- precision operations.
-mdouble-float Assume that the floating-point coprocessor supports double-precision operations.  This is the default.
-modd-spreg -mno-odd-spreg Enable the use of odd-numbered single-precision floating-point registers for the o32 ABI.  This is the default for processors that are known to support these registers.  When using the o32 FPXX ABI, -mno-odd-spreg is set by default.
-mabs=2008 -mabs=legacy These options control the treatment of the special not-a-number (NaN) IEEE 754 floating-point data with the "abs.fmt" and "neg.fmt" machine instructions.
By default or when -mabs=legacy is used the legacy treatment is selected.  In this case these instructions are considered arithmetic and avoided where correct operation is required and the input operand might be a NaN.  A longer sequence of instructions that manipulate the sign bit of floating-point datum manually is used instead unless the -ffinite-math-only option has also been specified.
The -mabs=2008 option selects the IEEE 754-2008 treatment.  In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN.  These instructions are therefore always used for the respective operations.
-mnan=2008 -mnan=legacy These options control the encoding of the special not-a-number (NaN) IEEE 754 floating-point data.
The -mnan=legacy option selects the legacy encoding.  In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signaling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1.
The -mnan=2008 option selects the IEEE 754-2008 encoding.  In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0.
The default is -mnan=legacy unless GCC has been configured with --with-nan=2008.
-mllsc -mno-llsc Use (do not use) ll, sc, and sync instructions to implement atomic memory built-in functions.  When neither option is specified, GCC uses the instructions if the target architecture supports them.
-mllsc is useful if the runtime environment can emulate the instructions and -mno-llsc can be useful when compiling for nonstandard ISAs.  You can make either option the default by configuring GCC with --with-llsc and --without-llsc respectively. --with-llsc is the default for some configurations; see the installation documentation for details.
-mdsp -mno-dsp Use (do not use) revision 1 of the MIPS DSP ASE. This option defines the preprocessor macro "__mips_dsp".  It also defines "__mips_dsp_rev" to 1.
-mdspr2 -mno-dspr2 Use (do not use) revision 2 of the MIPS DSP ASE. This option defines the preprocessor macros "__mips_dsp" and "__mips_dspr2".  It also defines "__mips_dsp_rev" to 2.
-msmartmips -mno-smartmips Use (do not use) the MIPS SmartMIPS ASE.
-mpaired-single -mno-paired-single Use (do not use) paired-single floating-point instructions. This option requires hardware floating-point support to be enabled.
-mdmx -mno-mdmx Use (do not use) MIPS Digital Media Extension instructions.  This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled.
-mips3d -mno-mips3d Use (do not use) the MIPS-3D ASE.  The option -mips3d implies -mpaired-single.
-mmicromips -mno-micromips Generate (do not generate) microMIPS code.
MicroMIPS code generation can also be controlled on a per-function basis by means of "micromips" and "nomicromips" attributes.
-mmt -mno-mt Use (do not use) MT Multithreading instructions.
-mmcu -mno-mcu Use (do not use) the MIPS MCU ASE instructions.
-meva -mno-eva Use (do not use) the MIPS Enhanced Virtual Addressing instructions.
-mvirt -mno-virt Use (do not use) the MIPS Virtualization (VZ) instructions.
-mxpa -mno-xpa Use (do not use) the MIPS eXtended Physical Address (XPA) instructions.
-mcrc -mno-crc Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions.
-mginv -mno-ginv Use (do not use) the MIPS Global INValidate (GINV) instructions.
-mloongson-mmi -mno-loongson-mmi Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI).
-mloongson-ext -mno-loongson-ext Use (do not use) the MIPS Loongson EXTensions (EXT) instructions.
-mloongson-ext2 -mno-loongson-ext2 Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions.
-mlong64 Force "long" types to be 64 bits wide.  See -mlong32 for an explanation of the default and the way that the pointer size is determined.
-mlong32 Force "long", "int", and pointer types to be 32 bits wide.
The default size of "int"s, "long"s and pointers depends on the ABI. All the supported ABIs use 32-bit "int"s.  The n64 ABI uses 64-bit "long"s, as does the 64-bit EABI; the others use 32-bit "long"s. Pointers are the same size as "long"s, or the same size as integer registers, whichever is smaller.
-msym32 -mno-sym32 Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI.  This option is useful in combination with -mabi=64 and -mno-abicalls because it allows GCC to generate shorter and faster references to symbolic addresses.
-G num Put definitions of externally-visible data in a small data section if that data is no bigger than num bytes.  GCC can then generate more efficient accesses to the data; see -mgpopt for details.
The default -G option depends on the configuration.
-mlocal-sdata -mno-local-sdata Extend (do not extend) the -G behavior to local data too, such as to static variables in C.  -mlocal-sdata is the default for all configurations.
If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with -mno-local-sdata.  You might also want to build large libraries with -mno-local-sdata, so that the libraries leave more room for the main program.
-mextern-sdata -mno-extern-sdata Assume (do not assume) that externally-defined data is in a small data section if the size of that data is within the -G limit. -mextern-sdata is the default for all configurations.
If you compile a module Mod with -mextern-sdata -G num -mgpopt, and Mod references a variable Var that is no bigger than num bytes, you must make sure that Var is placed in a small data section.  If Var is defined by another module, you must either compile that module with a high-enough -G setting or attach a "section" attribute to Var's definition.  If Var is common, you must link the application with a high-enough -G setting.
The easiest way of satisfying these restrictions is to compile and link every module with the same -G option.  However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported -G setting and additionally using -mno-extern-sdata to stop the library from making assumptions about externally-defined data.
-mgpopt -mno-gpopt Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see -G, -mlocal-sdata and -mextern-sdata. -mgpopt is the default for all configurations.
-mno-gpopt is useful for cases where the $gp register might not hold the value of "_gp".  For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines pass an unknown value in $gp.  (In such situations, the boot monitor itself is usually compiled with -G0.)