neulab/tldr huggingface dataset:
-mbe8 -mbe32 When linking a big-endian image select between BE8 and BE32 formats. The option has no effect for little-endian images and is ignored. The default is dependent on the selected target architecture.  For ARMv6 and later architectures the default is BE8, for older architectures the default is BE32.  BE32 format has been deprecated by ARM.
-march=name[+extension...] This specifies the name of the target ARM architecture.  GCC uses this name to determine what kind of instructions it can emit when generating assembly code.  This option can be used in conjunction with or instead of the -mcpu= option.
Permissible names are: armv4t, armv5t, armv5te, armv6, armv6j, armv6k, armv6kz, armv6t2, armv6z, armv6zk, armv7, armv7-a, armv7ve, armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a, armv8.5-a, armv8.6-a, armv7-r, armv8-r, armv6-m, armv6s-m, armv7-m, armv7e-m, armv8-m.base, armv8-m.main, armv8.1-m.main, iwmmxt and iwmmxt2.
Additionally, the following architectures, which lack support for the Thumb execution state, are recognized but support is deprecated: armv4.
Many of the architectures support extensions.  These can be added by appending +extension to the architecture name.  Extension options are processed in order and capabilities accumulate.  An extension will also enable any necessary base extensions upon which it depends.  For example, the +crypto extension will always enable the +simd extension.  The exception to the additive construction is for extensions that are prefixed with +no...: these extensions disable the specified option and any other extensions that may depend on the presence of that extension.
For example, -march=armv7-a+simd+nofp+vfpv4 is equivalent to writing -march=armv7-a+vfpv4 since the +simd option is entirely disabled by the +nofp option that follows it.
Most extension names are generically named, but have an effect that is dependent upon the architecture to which it is applied.  For example, the +simd option can be applied to both armv7-a and armv8-a architectures, but will enable the original ARMv7-A Advanced SIMD (Neon) extensions for armv7-a and the ARMv8-A variant for armv8-a.
The table below lists the supported extensions for each architecture. Architectures not mentioned do not support any extensions.
armv5te armv6 armv6j armv6k armv6kz armv6t2 armv6z armv6zk +fp The VFPv2 floating-point instructions.  The extension +vfpv2 can be used as an alias for this extension.
+nofp Disable the floating-point instructions.
armv7 The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures.
+fp The VFPv3 floating-point instructions, with 16 double- precision registers.  The extension +vfpv3-d16 can be used as an alias for this extension.  Note that floating-point is not supported by the base ARMv7-M architecture, but is compatible with both the ARMv7-A and ARMv7-R architectures.
armv7-a +mp The multiprocessing extension.
+sec The security extension.
+fp The VFPv3 floating-point instructions, with 16 double- precision registers.  The extension +vfpv3-d16 can be used as an alias for this extension.
+simd The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions.  The extensions +neon and +neon-vfpv3 can be used as aliases for this extension.
+vfpv3 The VFPv3 floating-point instructions, with 32 double- precision registers.
+vfpv3-d16-fp16 The VFPv3 floating-point instructions, with 16 double- precision registers and the half-precision floating-point conversion operations.
+vfpv3-fp16 The VFPv3 floating-point instructions, with 32 double- precision registers and the half-precision floating-point conversion operations.
+vfpv4-d16 The VFPv4 floating-point instructions, with 16 double- precision registers.
+vfpv4 The VFPv4 floating-point instructions, with 32 double- precision registers.
+neon-fp16 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision floating-point conversion operations.
+neon-vfpv4 The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions.
+nosimd Disable the Advanced SIMD instructions (does not disable floating point).
+nofp Disable the floating-point and Advanced SIMD instructions.
armv7ve The extended version of the ARMv7-A architecture with support for virtualization.
+fp The VFPv4 floating-point instructions, with 16 double- precision registers.  The extension +vfpv4-d16 can be used as an alias for this extension.
+simd The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions.  The extension +neon-vfpv4 can be used as an alias for this extension.
+vfpv3-d16 The VFPv3 floating-point instructions, with 16 double- precision registers.
+neon The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions.  The extension +neon-vfpv3 can be used as an alias for this extension.
armv8-a +crc The Cyclic Redundancy Check (CRC) instructions.
+simd The ARMv8-A Advanced SIMD and floating-point instructions.
+crypto The cryptographic instructions.
+nocrypto Disable the cryptographic instructions.
+nofp Disable the floating-point, Advanced SIMD and cryptographic instructions.
+sb Speculation Barrier Instruction.
+predres Execution and Data Prediction Restriction Instructions.
armv8.1-a +simd The ARMv8.1-A Advanced SIMD and floating-point instructions.
+crypto The cryptographic instructions.  This also enables the Advanced SIMD and floating-point instructions.
armv8.2-a armv8.3-a +fp16 The half-precision floating-point data processing instructions.  This also enables the Advanced SIMD and floating-point instructions.
+fp16fml The half-precision floating-point fmla extension.  This also enables the half-precision floating-point extension and Advanced SIMD and floating-point instructions.
+simd The ARMv8.1-A Advanced SIMD and floating-point instructions.
+dotprod Enable the Dot Product extension.  This also enables Advanced SIMD instructions.
+nocrypto Disable the cryptographic extension.
+i8mm 8-bit Integer Matrix Multiply instructions.  This also enables Advanced SIMD and floating-point instructions.
+bf16 Brain half-precision floating-point instructions.  This also enables Advanced SIMD and floating-point instructions.
armv8.4-a +fp16 The half-precision floating-point data processing instructions.  This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension.
+simd The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension.
+crypto The cryptographic instructions.  This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension.
armv8.5-a +fp16 The half-precision floating-point data processing instructions.  This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension.
armv8.6-a +fp16 The half-precision floating-point data processing instructions.  This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension.
armv7-r +fp.sp The single-precision VFPv3 floating-point instructions.  The extension +vfpv3xd can be used as an alias for this extension.
+fp The VFPv3 floating-point instructions with 16 double- precision registers.  The extension +vfpv3-d16 can be used as an alias for this extension.
+vfpv3xd-d16-fp16 The single-precision VFPv3 floating-point instructions with 16 double-precision registers and the half-precision floating-point conversion operations.
+vfpv3-d16-fp16 The VFPv3 floating-point instructions with 16 double- precision registers and the half-precision floating-point conversion operations.
+nofp Disable the floating-point extension.
+idiv The ARM-state integer division instructions.
+noidiv Disable the ARM-state integer division extension.
armv7e-m +fp The single-precision VFPv4 floating-point instructions.
+fpv5 The single-precision FPv5 floating-point instructions.
+fp.dp The single- and double-precision FPv5 floating-point instructions.
+nofp Disable the floating-point extensions.
armv8.1-m.main +dsp The DSP instructions.
+mve The M-Profile Vector Extension (MVE) integer instructions.
+mve.fp The M-Profile Vector Extension (MVE) integer and single precision floating-point instructions.
+fp The single-precision floating-point instructions.
+fp.dp The single- and double-precision floating-point instructions.
+cdecp0, +cdecp1, ... , +cdecp7 Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7.
armv8-m.main +dsp The DSP instructions.
+nodsp Disable the DSP extension.
armv8-r +crc The Cyclic Redundancy Check (CRC) instructions.
+fp.sp The single-precision FPv5 floating-point instructions.
-march=native causes the compiler to auto-detect the architecture of the build computer.  At present, this feature is only supported on GNU/Linux, and not all architectures are recognized.  If the auto- detect is unsuccessful the option has no effect.
-mtune=name This option specifies the name of the target ARM processor for which GCC should tune the performance of the code.  For some ARM implementations better performance can be obtained by using this option.  Permissible names are: arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm740t, strongarm, strongarm110, strongarm1100, 0strongarm1110, arm8, arm810, arm9, arm9e, arm920, arm920t, arm922t, arm946e-s, arm966e-s, arm968e-s, arm926ej-s, arm940t, arm9tdmi, arm10tdmi, arm1020t, arm1026ej-s, arm10e, arm1020e, arm1022e, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1156t2-s, arm1156t2f-s, arm1176jz-s, arm1176jzf-s, generic-armv7-a, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, ares, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52, cortex-m0, cortex-m0plus, cortex-m1, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, cortex-m35p, cortex-m55, cortex-x1, cortex-m1.small-multiply, cortex-m0.small-multiply, cortex-m0plus.small-multiply, exynos-m1, marvell-pj4, neoverse-n1, neoverse-n2, neoverse-v1, xscale, iwmmxt, iwmmxt2, ep9312, fa526, fa626, fa606te, fa626te, fmp626, fa726te, xgene1.
Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system.  Permissible names are: cortex-a15.cortex-a7, cortex-a17.cortex-a7, cortex-a57.cortex-a53, cortex-a72.cortex-a53, cortex-a72.cortex-a35, cortex-a73.cortex-a53, cortex-a75.cortex-a55, cortex-a76.cortex-a55.
-mtune=generic-arch specifies that GCC should tune the performance for a blend of processors within architecture arch.  The aim is to generate code that run well on the current most popular processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs.  The effects of this option may change in future GCC versions as CPU models come and go.
-mtune permits the same extension options as -mcpu, but the extension options do not affect the tuning of the generated code.
-mtune=native causes the compiler to auto-detect the CPU of the build computer.  At present, this feature is only supported on GNU/Linux, and not all architectures are recognized.  If the auto-detect is unsuccessful the option has no effect.
-mcpu=name[+extension...] This specifies the name of the target ARM processor.  GCC uses this name to derive the name of the target ARM architecture (as if specified by -march) and the ARM processor type for which to tune for performance (as if specified by -mtune).  Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option.
Many of the supported CPUs implement optional architectural extensions.  Where this is so the architectural extensions are normally enabled by default.  If implementations that lack the extension exist, then the extension syntax can be used to disable those extensions that have been omitted.  For floating-point and Advanced SIMD (Neon) instructions, the settings of the options -mfloat-abi and -mfpu must also be considered: floating-point and Advanced SIMD instructions will only be used if -mfloat-abi is not set to soft; and any setting of -mfpu other than auto will override the available floating-point and SIMD extension instructions.
For example, cortex-a9 can be found in three major configurations: integer only, with just a floating-point unit or with floating-point and Advanced SIMD.  The default is to enable all the instructions, but the extensions +nosimd and +nofp can be used to disable just the SIMD or both the SIMD and floating-point instructions respectively.
Permissible names for this option are the same as those for -mtune.
The following extension options are common to the listed CPUs:
+nodsp Disable the DSP instructions on cortex-m33, cortex-m35p.
+nofp Disables the floating-point instructions on arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, arm926ej-s, arm1026ej-s, cortex-r5, cortex-r7, cortex-r8, cortex-m4, cortex-m7, cortex-m33 and cortex-m35p.  Disables the floating- point and SIMD instructions on generic-armv7-a, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, cortex-a15.cortex-a7, cortex-a17.cortex-a7, cortex-a32, cortex-a35, cortex-a53 and cortex-a55.
+nofp.dp Disables the double-precision component of the floating-point instructions on cortex-r5, cortex-r7, cortex-r8, cortex-r52 and cortex-m7.
+nosimd Disables the SIMD (but not floating-point) instructions on generic-armv7-a, cortex-a5, cortex-a7 and cortex-a9.
+crypto Enables the cryptographic instructions on cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, exynos-m1, xgene1, cortex-a57.cortex-a53, cortex-a72.cortex-a53, cortex-a73.cortex-a35, cortex-a73.cortex-a53 and cortex-a75.cortex-a55.
Additionally the generic-armv7-a pseudo target defaults to VFPv3 with 16 double-precision registers.  It supports the following extension options: mp, sec, vfpv3-d16, vfpv3, vfpv3-d16-fp16, vfpv3-fp16, vfpv4-d16, vfpv4, neon, neon-vfpv3, neon-fp16, neon-vfpv4.  The meanings are the same as for the extensions to -march=armv7-a.
-mcpu=generic-arch is also permissible, and is equivalent to -march=arch -mtune=generic-arch.  See -mtune for more information.
-mcpu=native causes the compiler to auto-detect the CPU of the build computer.  At present, this feature is only supported on GNU/Linux, and not all architectures are recognized.  If the auto-detect is unsuccessful the option has no effect.
-mfpu=name This specifies what floating-point hardware (or hardware emulation) is available on the target.  Permissible names are: auto, vfpv2, vfpv3, vfpv3-fp16, vfpv3-d16, vfpv3-d16-fp16, vfpv3xd, vfpv3xd-fp16, neon-vfpv3, neon-fp16, vfpv4, vfpv4-d16, fpv4-sp-d16, neon-vfpv4, fpv5-d16, fpv5-sp-d16, fp-armv8, neon-fp-armv8 and crypto-neon-fp-armv8.  Note that neon is an alias for neon-vfpv3 and vfp is an alias for vfpv2.
The setting auto is the default and is special.  It causes the compiler to select the floating-point and Advanced SIMD instructions based on the settings of -mcpu and -march.
If the selected floating-point hardware includes the NEON extension (e.g. -mfpu=neon), note that floating-point operations are not generated by GCC's auto-vectorization pass unless -funsafe-math-optimizations is also specified.  This is because NEON hardware does not fully implement the IEEE 754 standard for floating- point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision.
You can also set the fpu name at function level by using the "target("fpu=")" function attributes or pragmas.
-mfp16-format=name Specify the format of the "__fp16" half-precision floating-point type.  Permissible names are none, ieee, and alternative; the default is none, in which case the "__fp16" type is not defined.
-mstructure-size-boundary=n The sizes of all structures and unions are rounded up to a multiple of the number of bits set by this option.  Permissible values are 8, 32 and 64.  The default value varies for different toolchains.  For the COFF targeted toolchain the default value is 8.  A value of 64 is only allowed if the underlying ABI supports it.
Specifying a larger number can produce faster, more efficient code, but can also increase the size of the program.  Different values are potentially incompatible.  Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions.
This option is deprecated.
-mabort-on-noreturn Generate a call to the function "abort" at the end of a "noreturn" function.  It is executed if the function tries to return.
-mlong-calls -mno-long-calls Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register.  This switch is needed if the target function lies outside of the 64-megabyte addressing range of the offset-based version of subroutine call instruction.
Even if this switch is enabled, not all function calls are turned into long calls.  The heuristic is that static functions, functions that have the "short_call" attribute, functions that are inside the scope of a "#pragma no_long_calls" directive, and functions whose definitions have already been compiled within the current compilation unit are not turned into long calls.  The exceptions to this rule are that weak function definitions, functions with the "long_call" attribute or the "section" attribute, and functions that are within the scope of a "#pragma long_calls" directive are always turned into long calls.
This feature is not enabled by default.  Specifying -mno-long-calls restores the default behavior, as does placing the function calls within the scope of a "#pragma long_calls_off" directive.  Note these switches have no effect on how the compiler generates code to handle function calls via function pointers.
-msingle-pic-base Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function.  The runtime system is responsible for initializing this register with an appropriate value before execution begins.
-mpic-register=reg Specify the register to be used for PIC addressing.  For standard PIC base case, the default is any suitable register determined by compiler.  For single PIC base case, the default is R9 if target is EABI based or stack-checking is enabled, otherwise the default is R10.
-mpic-data-is-text-relative Assume that the displacement between the text and data segments is fixed at static link time.  This permits using PC-relative addressing operations to access data known to be in the data segment.  For non- VxWorks RTP targets, this option is enabled by default.  When disabled on such targets, it will enable -msingle-pic-base by default.
-mpoke-function-name Write the name of each function into the text section, directly preceding the function prologue.  The generated code is similar to this:
t0 .ascii "arm_poke_function_name", 0 .align t1 .word 0xff000000 + (t1 - t0) arm_poke_function_name mov     ip, sp stmfd   sp!, {fp, ip, lr, pc} sub     fp, ip, #4
When performing a stack backtrace, code can inspect the value of "pc" stored at "fp + 0".  If the trace function then looks at location "pc - 12" and the top 8 bits are set, then we know that there is a function name embedded immediately preceding this location and has length "((pc[-3]) & 0xff000000)".
-mthumb -marm Select between generating code that executes in ARM and Thumb states. The default for most configurations is to generate code that executes in ARM state, but the default can be changed by configuring GCC with the --with-mode=state configure option.
You can also override the ARM and Thumb mode for each function by using the "target("thumb")" and "target("arm")" function attributes or pragmas.
-mflip-thumb Switch ARM/Thumb modes on alternating functions.  This option is provided for regression testing of mixed Thumb/ARM code generation, and is not intended for ordinary use in compiling code.
-mtpcs-frame Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions.  (A leaf function is one that does not call any other functions.)  The default is -mno-tpcs-frame.
-mtpcs-leaf-frame Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions.  (A leaf function is one that does not call any other functions.)  The default is -mno-apcs-leaf-frame.
-mcallee-super-interworking Gives all externally visible functions in the file being compiled an ARM instruction set header which switches to Thumb mode before executing the rest of the function.  This allows these functions to be called from non-interworking code.  This option is not valid in AAPCS configurations because interworking is enabled by default.
-mcaller-super-interworking Allows calls via function pointers (including virtual functions) to execute correctly regardless of whether the target code has been compiled for interworking or not.  There is a small overhead in the cost of executing a function pointer if this option is enabled.  This option is not valid in AAPCS configurations because interworking is enabled by default.
-mtp=name Specify the access model for the thread local storage pointer.  The valid models are soft, which generates calls to "__aeabi_read_tp", cp15, which fetches the thread pointer from "cp15" directly (supported in the arm6k architecture), and auto, which uses the best available method for the selected processor.  The default setting is auto.
-mtls-dialect=dialect Specify the dialect to use for accessing thread local storage.  Two dialects are supported---gnu and gnu2.  The gnu dialect selects the original GNU scheme for supporting local and global dynamic TLS models.  The gnu2 dialect selects the GNU descriptor scheme, which provides better performance for shared libraries.  The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker and library support.  Initial and local exec TLS models are unaffected by this option and always use the original scheme.
-mword-relocations Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).  This is enabled by default on targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when -fpic or -fPIC is specified. This option conflicts with -mslow-flash-data.
-mfix-cortex-m3-ldrd Some Cortex-M3 cores can cause data corruption when "ldrd" instructions with overlapping destination and base registers are used.  This option avoids generating these instructions.  This option is enabled by default when -mcpu=cortex-m3 is specified.
-munaligned-access -mno-unaligned-access Enables (or disables) reading and writing of 16- and 32- bit values from addresses that are not 16- or 32- bit aligned.  By default unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for ARMv8-M Baseline architectures, and enabled for all other architectures.  If unaligned access is not enabled then words in packed data structures are accessed a byte at a time.
The ARM attribute "Tag_CPU_unaligned_access" is set in the generated object file to either true or false, depending upon the setting of this option.  If unaligned access is enabled then the preprocessor symbol "__ARM_FEATURE_UNALIGNED" is also defined.
-mneon-for-64bits This option is deprecated and has no effect.
-mslow-flash-data Assume loading data from flash is slower than fetching instruction. Therefore literal load is minimized for better performance.  This option is only supported when compiling for ARMv7 M-profile and off by default. It conflicts with -mword-relocations.
-masm-syntax-unified Assume inline assembler is using unified asm syntax.  The default is currently off which implies divided syntax.  This option has no impact on Thumb2. However, this may change in future releases of GCC. Divided syntax should be considered deprecated.
-mrestrict-it Restricts generation of IT blocks to conform to the rules of ARMv8-A. IT blocks can only contain a single 16-bit instruction from a select set of instructions. This option is on by default for ARMv8-A Thumb mode.
-mprint-tune-info Print CPU tuning information as comment in assembler file.  This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code.  This option is disabled by default.
-mpure-code Do not allow constant data to be placed in code sections. Additionally, when compiling for ELF object format give all text sections the ELF processor-specific section attribute "SHF_ARM_PURECODE".  This option is only available when generating non-pic code for M-profile targets.
-mcmse Generate secure code as per the "ARMv8-M Security Extensions: Requirements on Development Tools Engineering Specification", which can be found on <https://developer.arm.com/documentation/ecm0359818/latest/>.
-mfdpic -mno-fdpic Select the FDPIC ABI, which uses 64-bit function descriptors to represent pointers to functions.  When the compiler is configured for "arm-*-uclinuxfdpiceabi" targets, this option is on by default and implies -fPIE if none of the PIC/PIE-related options is provided.  On other targets, it only enables the FDPIC-specific code generation features, and the user should explicitly provide the PIC/PIE-related options as needed.
Note that static linking is not supported because it would still involve the dynamic linker when the program self-relocates.  If such behavior is acceptable, use -static and -Wl,-dynamic-linker options.
The opposite -mno-fdpic option is useful (and required) to build the Linux kernel using the same ("arm-*-uclinuxfdpiceabi") toolchain as the one used to build the userland programs.
AVR Options
These options are defined for AVR implementations:
-mmcu=mcu Specify Atmel AVR instruction set architectures (ISA) or MCU type.
The default for this option is avr2.
GCC supports the following AVR devices and ISAs:
"avr2" "Classic" devices with up to 8 KiB of program memory.  mcu = "attiny22", "attiny26", "at90s2313", "at90s2323", "at90s2333", "at90s2343", "at90s4414", "at90s4433", "at90s4434", "at90c8534", "at90s8515", "at90s8535".
"avr25" "Classic" devices with up to 8 KiB of program memory and with the "MOVW" instruction.  mcu = "attiny13", "attiny13a", "attiny24", "attiny24a", "attiny25", "attiny261", "attiny261a", "attiny2313", "attiny2313a", "attiny43u", "attiny44", "attiny44a", "attiny45", "attiny48", "attiny441", "attiny461", "attiny461a", "attiny4313", "attiny84", "attiny84a", "attiny85", "attiny87", "attiny88", "attiny828", "attiny841", "attiny861", "attiny861a", "ata5272", "ata6616c", "at86rf401".
"avr3" "Classic" devices with 16 KiB up to 64 KiB of program memory. mcu = "at76c711", "at43usb355".
"avr31" "Classic" devices with 128 KiB of program memory.  mcu = "atmega103", "at43usb320".
"avr35" "Classic" devices with 16 KiB up to 64 KiB of program memory and with the "MOVW" instruction.  mcu = "attiny167", "attiny1634", "atmega8u2", "atmega16u2", "atmega32u2", "ata5505", "ata6617c", "ata664251", "at90usb82", "at90usb162".
"avr4" "Enhanced" devices with up to 8 KiB of program memory.  mcu = "atmega48", "atmega48a", "atmega48p", "atmega48pa", "atmega48pb", "atmega8", "atmega8a", "atmega8hva", "atmega88", "atmega88a", "atmega88p", "atmega88pa", "atmega88pb", "atmega8515", "atmega8535", "ata6285", "ata6286", "ata6289", "ata6612c", "at90pwm1", "at90pwm2", "at90pwm2b", "at90pwm3", "at90pwm3b", "at90pwm81".
"avr5" "Enhanced" devices with 16 KiB up to 64 KiB of program memory. mcu = "atmega16", "atmega16a", "atmega16hva", "atmega16hva2", "atmega16hvb", "atmega16hvbrevb", "atmega16m1", "atmega16u4", "atmega161", "atmega162", "atmega163", "atmega164a", "atmega164p", "atmega164pa", "atmega165", "atmega165a", "atmega165p", "atmega165pa", "atmega168", "atmega168a", "atmega168p", "atmega168pa", "atmega168pb", "atmega169", "atmega169a", "atmega169p", "atmega169pa", "atmega32", "atmega32a", "atmega32c1", "atmega32hvb", "atmega32hvbrevb", "atmega32m1", "atmega32u4", "atmega32u6", "atmega323", "atmega324a", "atmega324p", "atmega324pa", "atmega325", "atmega325a", "atmega325p", "atmega325pa", "atmega328", "atmega328p", "atmega328pb", "atmega329", "atmega329a", "atmega329p", "atmega329pa", "atmega3250", "atmega3250a", "atmega3250p", "atmega3250pa", "atmega3290", "atmega3290a", "atmega3290p", "atmega3290pa", "atmega406", "atmega64", "atmega64a", "atmega64c1", "atmega64hve", "atmega64hve2", "atmega64m1", "atmega64rfr2", "atmega640", "atmega644", "atmega644a", "atmega644p", "atmega644pa", "atmega644rfr2", "atmega645", "atmega645a", "atmega645p", "atmega649", "atmega649a", "atmega649p", "atmega6450", "atmega6450a", "atmega6450p", "atmega6490", "atmega6490a", "atmega6490p", "ata5795", "ata5790", "ata5790n", "ata5791", "ata6613c", "ata6614q", "ata5782", "ata5831", "ata8210", "ata8510", "ata5702m322", "at90pwm161", "at90pwm216", "at90pwm316", "at90can32", "at90can64", "at90scr100", "at90usb646", "at90usb647", "at94k", "m3000".
"avr51" "Enhanced" devices with 128 KiB of program memory.  mcu = "atmega128", "atmega128a", "atmega128rfa1", "atmega128rfr2", "atmega1280", "atmega1281", "atmega1284", "atmega1284p", "atmega1284rfr2", "at90can128", "at90usb1286", "at90usb1287".
"avr6" "Enhanced" devices with 3-byte PC, i.e. with more than 128 KiB of program memory.  mcu = "atmega256rfr2", "atmega2560", "atmega2561", "atmega2564rfr2".
"avrxmega2" "XMEGA" devices with more than 8 KiB and up to 64 KiB of program memory.  mcu = "atxmega8e5", "atxmega16a4", "atxmega16a4u", "atxmega16c4", "atxmega16d4", "atxmega16e5", "atxmega32a4", "atxmega32a4u", "atxmega32c3", "atxmega32c4", "atxmega32d3", "atxmega32d4", "atxmega32e5".
"avrxmega3" "XMEGA" devices with up to 64 KiB of combined program memory and RAM, and with program memory visible in the RAM address space. mcu = "attiny202", "attiny204", "attiny212", "attiny214", "attiny402", "attiny404", "attiny406", "attiny412", "attiny414", "attiny416", "attiny417", "attiny804", "attiny806", "attiny807", "attiny814", "attiny816", "attiny817", "attiny1604", "attiny1606", "attiny1607", "attiny1614", "attiny1616", "attiny1617", "attiny3214", "attiny3216", "attiny3217", "atmega808", "atmega809", "atmega1608", "atmega1609", "atmega3208", "atmega3209", "atmega4808", "atmega4809".
"avrxmega4" "XMEGA" devices with more than 64 KiB and up to 128 KiB of program memory.  mcu = "atxmega64a3", "atxmega64a3u", "atxmega64a4u", "atxmega64b1", "atxmega64b3", "atxmega64c3", "atxmega64d3", "atxmega64d4".
"avrxmega5" "XMEGA" devices with more than 64 KiB and up to 128 KiB of program memory and more than 64 KiB of RAM.  mcu = "atxmega64a1", "atxmega64a1u".
"avrxmega6" "XMEGA" devices with more than 128 KiB of program memory.  mcu = "atxmega128a3", "atxmega128a3u", "atxmega128b1", "atxmega128b3", "atxmega128c3", "atxmega128d3", "atxmega128d4", "atxmega192a3", "atxmega192a3u", "atxmega192c3", "atxmega192d3", "atxmega256a3", "atxmega256a3b", "atxmega256a3bu", "atxmega256a3u", "atxmega256c3", "atxmega256d3", "atxmega384c3", "atxmega384d3".
"avrxmega7" "XMEGA" devices with more than 128 KiB of program memory and more than 64 KiB of RAM.  mcu = "atxmega128a1", "atxmega128a1u", "atxmega128a4u".
"avrtiny" "TINY" Tiny core devices with 512 B up to 4 KiB of program memory.  mcu = "attiny4", "attiny5", "attiny9", "attiny10", "attiny20", "attiny40".
"avr1" This ISA is implemented by the minimal AVR core and supported for assembler only.  mcu = "attiny11", "attiny12", "attiny15", "attiny28", "at90s1200".
-mabsdata Assume that all data in static storage can be accessed by LDS / STS instructions.  This option has only an effect on reduced Tiny devices like ATtiny40.  See also the "absdata" AVR Variable Attributes,variable attribute.
-maccumulate-args Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments once in function prologue/epilogue.  Without this option, outgoing arguments are pushed before calling a function and popped afterwards.
Popping the arguments after the function call can be expensive on AVR so that accumulating the stack space might lead to smaller executables because arguments need not be removed from the stack after such a function call.
This option can lead to reduced code size for functions that perform several calls to functions that get their arguments on the stack like calls to printf-like functions.
-mbranch-cost=cost Set the branch costs for conditional branch instructions to cost. Reasonable values for cost are small, non-negative integers. The default branch cost is 0.
-mcall-prologues Functions prologues/epilogues are expanded as calls to appropriate subroutines.  Code size is smaller.
-mdouble=bits -mlong-double=bits Set the size (in bits) of the "double" or "long double" type, respectively.  Possible values for bits are 32 and 64.  Whether or not a specific value for bits is allowed depends on the "--with-double=" and "--with-long-double=" configure options ("https://gcc.gnu.org/install/configure.html#avr"), and the same applies for the default values of the options.
-mgas-isr-prologues Interrupt service routines (ISRs) may use the "__gcc_isr" pseudo instruction supported by GNU Binutils.  If this option is on, the feature can still be disabled for individual ISRs by means of the AVR Function Attributes,,"no_gccisr" function attribute.  This feature is activated per default if optimization is on (but not with -Og, @pxref{Optimize Options}), and if GNU Binutils support PR21683 ("https://sourceware.org/PR21683").
-mint8 Assume "int" to be 8-bit integer.  This affects the sizes of all types: a "char" is 1 byte, an "int" is 1 byte, a "long" is 2 bytes, and "long long" is 4 bytes.  Please note that this option does not conform to the C standards, but it results in smaller code size.
-mmain-is-OS_task Do not save registers in "main".  The effect is the same like attaching attribute AVR Function Attributes,,"OS_task" to "main". It is activated per default if optimization is on.
-mn-flash=num Assume that the flash memory has a size of num times 64 KiB.
-mno-interrupts Generated code is not compatible with hardware interrupts.  Code size is smaller.
-mrelax Try to replace "CALL" resp. "JMP" instruction by the shorter "RCALL" resp. "RJMP" instruction if applicable.  Setting -mrelax just adds the --mlink-relax option to the assembler's command line and the --relax option to the linker's command line.
Jump relaxing is performed by the linker because jump offsets are not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code.
Relaxing must be turned on if linker stubs are needed, see the section on "EIND" and linker stubs below.
-mrmw Assume that the device supports the Read-Modify-Write instructions "XCH", "LAC", "LAS" and "LAT".
-mshort-calls Assume that "RJMP" and "RCALL" can target the whole program memory.
This option is used internally for multilib selection.  It is not an optimization option, and you don't need to set it by hand.
-msp8 Treat the stack pointer register as an 8-bit register, i.e. assume the high byte of the stack pointer is zero.  In general, you don't need to set this option by hand.
This option is used internally by the compiler to select and build multilibs for architectures "avr2" and "avr25".  These architectures mix devices with and without "SPH".  For any setting other than -mmcu=avr2 or -mmcu=avr25 the compiler driver adds or removes this option from the compiler proper's command line, because the compiler then knows if the device or architecture has an 8-bit stack pointer and thus no "SPH" register or not.
-mstrict-X Use address register "X" in a way proposed by the hardware.  This means that "X" is only used in indirect, post-increment or pre- decrement addressing.
Without this option, the "X" register may be used in the same way as "Y" or "Z" which then is emulated by additional instructions.  For example, loading a value with "X+const" addressing with a small non- negative "const < 64" to a register Rn is performed as
adiw r26, const   ; X += const ld   <Rn>, X        ; <Rn> = *X sbiw r26, const   ; X -= const
-mtiny-stack Only change the lower 8 bits of the stack pointer.
-mfract-convert-truncate Allow to use truncation instead of rounding towards zero for fractional fixed-point types.
-nodevicelib Don't link against AVR-LibC's device specific library "lib<mcu>.a".
-nodevicespecs Don't add -specs=device-specs/specs-mcu to the compiler driver's command line.  The user takes responsibility for supplying the sub- processes like compiler proper, assembler and linker with appropriate command line options.  This means that the user has to supply her private device specs file by means of -specs=path-to-specs-file. There is no more need for option -mmcu=mcu.
This option can also serve as a replacement for the older way of specifying custom device-specs files that needed -B some-path to point to a directory which contains a folder named "device-specs" which contains a specs file named "specs-mcu", where mcu was specified by -mmcu=mcu.
-Waddr-space-convert Warn about conversions between address spaces in the case where the resulting address space is not contained in the incoming address space.
-Wmisspelled-isr Warn if the ISR is misspelled, i.e. without __vector prefix.  Enabled by default.
"EIND" and Devices with More Than 128 Ki Bytes of Flash
Pointers in the implementation are 16 bits wide.  The address of a function or label is represented as word address so that indirect jumps and calls can target any code address in the range of 64 Ki words.
In order to facilitate indirect jump on devices with more than 128 Ki bytes of program memory space, there is a special function register called "EIND" that serves as most significant part of the target address when "EICALL" or "EIJMP" instructions are used.
Indirect jumps and calls on these devices are handled as follows by the compiler and are subject to some limitations:
*   The compiler never sets "EIND".
*   The compiler uses "EIND" implicitly in "EICALL"/"EIJMP" instructions or might read "EIND" directly in order to emulate an indirect call/jump by means of a "RET" instruction.
*   The compiler assumes that "EIND" never changes during the startup code or during the application. In particular, "EIND" is not saved/restored in function or interrupt service routine prologue/epilogue.
*   For indirect calls to functions and computed goto, the linker generates stubs. Stubs are jump pads sometimes also called trampolines. Thus, the indirect call/jump jumps to such a stub.  The stub contains a direct jump to the desired address.
*   Linker relaxation must be turned on so that the linker generates the stubs correctly in all situations. See the compiler option -mrelax and the linker option --relax.  There are corner cases where the linker is supposed to generate stubs but aborts without relaxation and without a helpful error message.
*   The default linker script is arranged for code with "EIND = 0".  If code is supposed to work for a setup with "EIND != 0", a custom linker script has to be used in order to place the sections whose name start with ".trampolines" into the segment where "EIND" points to.
*   The startup code from libgcc never sets "EIND".  Notice that startup code is a blend of code from libgcc and AVR-LibC.  For the impact of AVR-LibC on "EIND", see the AVR-LibC user manual ("http://nongnu.org/avr-libc/user-manual/").
*   It is legitimate for user-specific startup code to set up "EIND" early, for example by means of initialization code located in section ".init3". Such code runs prior to general startup code that initializes RAM and calls constructors, but after the bit of startup code from AVR-LibC that sets "EIND" to the segment where the vector table is located.
#include <avr/io.h>
static void __attribute__((section(".init3"),naked,used,no_instrument_function)) init3_set_eind (void) { __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t" "out %i0,r24" :: "n" (&EIND) : "r24","memory"); }
The "__trampolines_start" symbol is defined in the linker script.
*   Stubs are generated automatically by the linker if the following two conditions are met:
-<The address of a label is taken by means of the "gs" modifier> (short for generate stubs) like so:
LDI r24, lo8(gs(<func>)) LDI r25, hi8(gs(<func>))
-<The final location of that label is in a code segment> outside the segment where the stubs are located.
*   The compiler emits such "gs" modifiers for code labels in the following situations:
-<Taking address of a function or code label.> -<Computed goto.> -<If prologue-save function is used, see -mcall-prologues> command-line option.
-<Switch/case dispatch tables. If you do not want such dispatch> tables you can specify the -fno-jump-tables command-line option.
-<C and C++ constructors/destructors called during startup/shutdown.> -<If the tools hit a "gs()" modifier explained above.> *   Jumping to non-symbolic addresses like so is not supported:
int main (void) { /* Call function at word address 0x2 */ return ((int(*)(void)) 0x2)(); }
Instead, a stub has to be set up, i.e. the function has to be called through a symbol ("func_4" in the example):
int main (void) { extern int func_4 (void);
/* Call function at byte address 0x4 */ return func_4(); }
and the application be linked with -Wl,--defsym,func_4=0x4. Alternatively, "func_4" can be defined in the linker script.
Handling of the "RAMPD", "RAMPX", "RAMPY" and "RAMPZ" Special Function Registers
Some AVR devices support memories larger than the 64 KiB range that can be accessed with 16-bit pointers.  To access memory locations outside this 64 KiB range, the content of a "RAMP" register is used as high part of the address: The "X", "Y", "Z" address register is concatenated with the "RAMPX", "RAMPY", "RAMPZ" special function register, respectively, to get a wide address. Similarly, "RAMPD" is used together with direct addressing.
*   The startup code initializes the "RAMP" special function registers with zero.
*   If a AVR Named Address Spaces,named address space other than generic or "__flash" is used, then "RAMPZ" is set as needed before the operation.
*   If the device supports RAM larger than 64 KiB and the compiler needs to change "RAMPZ" to accomplish an operation, "RAMPZ" is reset to zero after the operation.
*   If the device comes with a specific "RAMP" register, the ISR prologue/epilogue saves/restores that SFR and initializes it with zero in case the ISR code might (implicitly) use it.
*   RAM larger than 64 KiB is not supported by GCC for AVR targets.  If you use inline assembler to read from locations outside the 16-bit address range and change one of the "RAMP" registers, you must reset it to zero after the access.
AVR Built-in Macros
GCC defines several built-in macros so that the user code can test for the presence or absence of features.  Almost any of the following built- in macros are deduced from device capabilities and thus triggered by the -mmcu= command-line option.
For even more AVR-specific built-in macros see AVR Named Address Spaces and AVR Built-in Functions.
"__AVR_ARCH__" Build-in macro that resolves to a decimal number that identifies the architecture and depends on the -mmcu=mcu option.  Possible values are:
2, 25, 3, 31, 35, 4, 5, 51, 6
for mcu="avr2", "avr25", "avr3", "avr31", "avr35", "avr4", "avr5", "avr51", "avr6",
respectively and
100, 102, 103, 104, 105, 106, 107
for mcu="avrtiny", "avrxmega2", "avrxmega3", "avrxmega4", "avrxmega5", "avrxmega6", "avrxmega7", respectively.  If mcu specifies a device, this built-in macro is set accordingly. For example, with -mmcu=atmega8 the macro is defined to 4.
"__AVR_Device__" Setting -mmcu=device defines this built-in macro which reflects the device's name. For example, -mmcu=atmega8 defines the built-in macro "__AVR_ATmega8__", -mmcu=attiny261a defines "__AVR_ATtiny261A__", etc.
The built-in macros' names follow the scheme "__AVR_Device__" where Device is the device name as from the AVR user manual. The difference between Device in the built-in macro and device in -mmcu=device is that the latter is always lowercase.
If device is not a device but only a core architecture like avr51, this macro is not defined.
"__AVR_DEVICE_NAME__" Setting -mmcu=device defines this built-in macro to the device's name. For example, with -mmcu=atmega8 the macro is defined to "atmega8".
"__AVR_XMEGA__" The device / architecture belongs to the XMEGA family of devices.
"__AVR_HAVE_ELPM__" The device has the "ELPM" instruction.
"__AVR_HAVE_ELPMX__" The device has the "ELPM Rn,Z" and "ELPM Rn,Z+" instructions.
"__AVR_HAVE_MOVW__" The device has the "MOVW" instruction to perform 16-bit register- register moves.
"__AVR_HAVE_LPMX__" The device has the "LPM Rn,Z" and "LPM Rn,Z+" instructions.
"__AVR_HAVE_MUL__" The device has a hardware multiplier.
"__AVR_HAVE_JMP_CALL__" The device has the "JMP" and "CALL" instructions.  This is the case for devices with more than 8 KiB of program memory.
"__AVR_HAVE_EIJMP_EICALL__" "__AVR_3_BYTE_PC__" The device has the "EIJMP" and "EICALL" instructions.  This is the case for devices with more than 128 KiB of program memory.  This also means that the program counter (PC) is 3 bytes wide.
"__AVR_2_BYTE_PC__" The program counter (PC) is 2 bytes wide. This is the case for devices with up to 128 KiB of program memory.
"__AVR_HAVE_8BIT_SP__" "__AVR_HAVE_16BIT_SP__" The stack pointer (SP) register is treated as 8-bit respectively 16-bit register by the compiler.  The definition of these macros is affected by -mtiny-stack.
"__AVR_HAVE_SPH__" "__AVR_SP8__" The device has the SPH (high part of stack pointer) special function register or has an 8-bit stack pointer, respectively.  The definition of these macros is affected by -mmcu= and in the cases of -mmcu=avr2 and -mmcu=avr25 also by -msp8.
"__AVR_HAVE_RAMPD__" "__AVR_HAVE_RAMPX__" "__AVR_HAVE_RAMPY__" "__AVR_HAVE_RAMPZ__" The device has the "RAMPD", "RAMPX", "RAMPY", "RAMPZ" special function register, respectively.
"__NO_INTERRUPTS__" This macro reflects the -mno-interrupts command-line option.
"__AVR_ERRATA_SKIP__" "__AVR_ERRATA_SKIP_JMP_CALL__" Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit instructions because of a hardware erratum.  Skip instructions are "SBRS", "SBRC", "SBIS", "SBIC" and "CPSE".  The second macro is only defined if "__AVR_HAVE_JMP_CALL__" is also set.
"__AVR_ISA_RMW__" The device has Read-Modify-Write instructions (XCH, LAC, LAS and LAT).
"__AVR_SFR_OFFSET__=offset" Instructions that can address I/O special function registers directly like "IN", "OUT", "SBI", etc. may use a different address as if addressed by an instruction to access RAM like "LD" or "STS". This offset depends on the device architecture and has to be subtracted from the RAM address in order to get the respective I/O address.
"__AVR_SHORT_CALLS__" The -mshort-calls command line option is set.
"__AVR_PM_BASE_ADDRESS__=addr" Some devices support reading from flash memory by means of "LD*" instructions.  The flash memory is seen in the data address space at an offset of "__AVR_PM_BASE_ADDRESS__".  If this macro is not defined, this feature is not available.  If defined, the address space is linear and there is no need to put ".rodata" into RAM.  This is handled by the default linker description file, and is currently available for "avrtiny" and "avrxmega3".  Even more convenient, there is no need to use address spaces like "__flash" or features like attribute "progmem" and "pgm_read_*".
"__WITH_AVRLIBC__" The compiler is configured to be used together with AVR-Libc.  See the --with-avrlibc configure option.
"__HAVE_DOUBLE_MULTILIB__" Defined if -mdouble= acts as a multilib option.
"__HAVE_DOUBLE32__" "__HAVE_DOUBLE64__" Defined if the compiler supports 32-bit double resp. 64-bit double. The actual layout is specified by option -mdouble=.
"__DEFAULT_DOUBLE__" The size in bits of "double" if -mdouble= is not set.  To test the layout of "double" in a program, use the built-in macro "__SIZEOF_DOUBLE__".
"__HAVE_LONG_DOUBLE32__" "__HAVE_LONG_DOUBLE64__" "__HAVE_LONG_DOUBLE_MULTILIB__" "__DEFAULT_LONG_DOUBLE__" Same as above, but for "long double" instead of "double".
"__WITH_DOUBLE_COMPARISON__" Reflects the "--with-double-comparison={tristate|bool|libf7}" configure option ("https://gcc.gnu.org/install/configure.html#avr") and is defined to 2 or 3.