neulab/tldr huggingface dataset:
-mfdiv -mno-fdiv Do or don't use hardware floating-point divide and square root instructions.  This requires the F or D extensions for floating-point registers.  The default is to use them if the specified architecture has these instructions.
-mdiv -mno-div Do or don't use hardware instructions for integer division.  This requires the M extension.  The default is to use them if the specified architecture has these instructions.
-march=ISA-string Generate code for given RISC-V ISA (e.g. rv64im).  ISA strings must be lower-case.  Examples include rv64i, rv32g, rv32e, and rv32imaf.
When -march= is not specified, use the setting from -mcpu.
If both -march and -mcpu= are not specified, the default for this argument is system dependent, users who want a specific architecture extensions should specify one explicitly.
-mcpu=processor-string Use architecture of and optimize the output for the given processor, specified by particular CPU name.  Permissible values for this option are: sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, and sifive-u74.
-mtune=processor-string Optimize the output for the given processor, specified by microarchitecture or particular CPU name.  Permissible values for this option are: rocket, sifive-3-series, sifive-5-series, sifive-7-series, size, and all valid options for -mcpu=.
When -mtune= is not specified, use the setting from -mcpu, the default is rocket if both are not specified.
The size choice is not intended for use by end-users.  This is used when -Os is specified.  It overrides the instruction cost info provided by -mtune=, but does not override the pipeline info.  This helps reduce code size while still giving good performance.
-mpreferred-stack-boundary=num Attempt to keep the stack boundary aligned to a 2 raised to num byte boundary.  If -mpreferred-stack-boundary is not specified, the default is 4 (16 bytes or 128-bits).
Warning: If you use this switch, then you must build all modules with the same value, including any libraries.  This includes the system libraries and startup modules.
-msmall-data-limit=n Put global and static data smaller than n bytes into a special section (on some targets).
-msave-restore -mno-save-restore Do or don't use smaller but slower prologue and epilogue code that uses library function calls.  The default is to use fast inline prologues and epilogues.
-mshorten-memrefs -mno-shorten-memrefs Do or do not attempt to make more use of compressed load/store instructions by replacing a load/store of 'base register + large offset' with a new load/store of 'new base + small offset'.  If the new base gets stored in a compressed register, then the new load/store can be compressed.  Currently targets 32-bit integer load/stores only.
-mstrict-align -mno-strict-align Do not or do generate unaligned memory accesses.  The default is set depending on whether the processor we are optimizing for supports fast unaligned access or not.
-mcmodel=medlow Generate code for the medium-low code model. The program and its statically defined symbols must lie within a single 2 GiB address range and must lie between absolute addresses -2 GiB and +2 GiB. Programs can be statically or dynamically linked. This is the default code model.
-mcmodel=medany Generate code for the medium-any code model. The program and its statically defined symbols must be within any single 2 GiB address range. Programs can be statically or dynamically linked.
-mexplicit-relocs -mno-exlicit-relocs Use or do not use assembler relocation operators when dealing with symbolic addresses.  The alternative is to use assembler macros instead, which may limit optimization.
-mrelax -mno-relax Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. The default is to take advantage of linker relaxations.
-memit-attribute -mno-emit-attribute Emit (do not emit) RISC-V attribute to record extra information into ELF objects.  This feature requires at least binutils 2.32.
-malign-data=type Control how GCC aligns variables and constants of array, structure, or union types.  Supported values for type are xlen which uses x register width as the alignment value, and natural which uses natural alignment.  xlen is the default.
-mbig-endian Generate big-endian code.  This is the default when GCC is configured for a riscv64be-*-* or riscv32be-*-* target.
-mlittle-endian Generate little-endian code.  This is the default when GCC is configured for a riscv64-*-* or riscv32-*-* but not a riscv64be-*-* or riscv32be-*-* target.
-mstack-protector-guard=guard -mstack-protector-guard-reg=reg -mstack-protector-guard-offset=offset Generate stack protection code using canary at guard.  Supported locations are global for a global canary or tls for per-thread canary in the TLS block.
With the latter choice the options -mstack-protector-guard-reg=reg and -mstack-protector-guard-offset=offset furthermore specify which register to use as base register for reading the canary, and from what offset from that base register. There is no default register or offset as this is entirely for use within the Linux kernel.
RL78 Options
-msim Links in additional target libraries to support operation within a simulator.
-mmul=none -mmul=g10 -mmul=g13 -mmul=g14 -mmul=rl78 Specifies the type of hardware multiplication and division support to be used.  The simplest is "none", which uses software for both multiplication and division.  This is the default.  The "g13" value is for the hardware multiply/divide peripheral found on the RL78/G13 (S2 core) targets.  The "g14" value selects the use of the multiplication and division instructions supported by the RL78/G14 (S3 core) parts.  The value "rl78" is an alias for "g14" and the value "mg10" is an alias for "none".
In addition a C preprocessor macro is defined, based upon the setting of this option.  Possible values are: "__RL78_MUL_NONE__", "__RL78_MUL_G13__" or "__RL78_MUL_G14__".
-mcpu=g10 -mcpu=g13 -mcpu=g14 -mcpu=rl78 Specifies the RL78 core to target.  The default is the G14 core, also known as an S3 core or just RL78.  The G13 or S2 core does not have multiply or divide instructions, instead it uses a hardware peripheral for these operations.  The G10 or S1 core does not have register banks, so it uses a different calling convention.
If this option is set it also selects the type of hardware multiply support to use, unless this is overridden by an explicit -mmul=none option on the command line.  Thus specifying -mcpu=g13 enables the use of the G13 hardware multiply peripheral and specifying -mcpu=g10 disables the use of hardware multiplications altogether.
Note, although the RL78/G14 core is the default target, specifying -mcpu=g14 or -mcpu=rl78 on the command line does change the behavior of the toolchain since it also enables G14 hardware multiply support. If these options are not specified on the command line then software multiplication routines will be used even though the code targets the RL78 core.  This is for backwards compatibility with older toolchains which did not have hardware multiply and divide support.
In addition a C preprocessor macro is defined, based upon the setting of this option.  Possible values are: "__RL78_G10__", "__RL78_G13__" or "__RL78_G14__".
-mg10 -mg13 -mg14 -mrl78 These are aliases for the corresponding -mcpu= option.  They are provided for backwards compatibility.
-mallregs Allow the compiler to use all of the available registers.  By default registers "r24..r31" are reserved for use in interrupt handlers. With this option enabled these registers can be used in ordinary functions as well.
-m64bit-doubles -m32bit-doubles Make the "double" data type be 64 bits (-m64bit-doubles) or 32 bits (-m32bit-doubles) in size.  The default is -m32bit-doubles.
-msave-mduc-in-interrupts -mno-save-mduc-in-interrupts Specifies that interrupt handler functions should preserve the MDUC registers.  This is only necessary if normal code might use the MDUC registers, for example because it performs multiplication and division operations.  The default is to ignore the MDUC registers as this makes the interrupt handlers faster.  The target option -mg13 needs to be passed for this to work as this feature is only available on the G13 target (S2 core).  The MDUC registers will only be saved if the interrupt handler performs a multiplication or division operation or it calls another function.
IBM RS/6000 and PowerPC Options
These -m options are defined for the IBM RS/6000 and PowerPC:
-mpowerpc-gpopt -mno-powerpc-gpopt -mpowerpc-gfxopt -mno-powerpc-gfxopt -mpowerpc64 -mno-powerpc64 -mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd -mfprnd -mno-fprnd -mcmpb -mno-cmpb -mhard-dfp -mno-hard-dfp You use these options to specify which instructions are available on the processor you are using.  The default value of these options is determined when configuring GCC.  Specifying the -mcpu=cpu_type overrides the specification of these options.  We recommend you use the -mcpu=cpu_type option rather than the options listed above.
Specifying -mpowerpc-gpopt allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root.  Specifying -mpowerpc-gfxopt allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select.
The -mmfcrf option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture.  The -mpopcntb option allows GCC to generate the popcount and double- precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture.  The -mpopcntd option allows GCC to generate the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture.  The -mfprnd option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture.  The -mcmpb option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture.  The -mhard-dfp option allows GCC to generate the decimal floating-point instructions implemented on some POWER processors.
The -mpowerpc64 option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities.  GCC defaults to -mno-powerpc64.
-mcpu=cpu_type Set architecture type, register usage, and instruction scheduling parameters for machine type cpu_type.  Supported values for cpu_type are 401, 403, 405, 405fp, 440, 440fp, 464, 464fp, 476, 476fp, 505, 601, 602, 603, 603e, 604, 604e, 620, 630, 740, 7400, 7450, 750, 801, 821, 823, 860, 970, 8540, a2, e300c2, e300c3, e500mc, e500mc64, e5500, e6500, ec603e, G3, G4, G5, titan, power3, power4, power5, power5+, power6, power6x, power7, power8, power9, future, powerpc, powerpc64, powerpc64le, rs64, and native.
-mcpu=powerpc, -mcpu=powerpc64, and -mcpu=powerpc64le specify pure 32-bit PowerPC (either endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes.
Specifying native as cpu type detects and selects the architecture option that corresponds to the host processor of the system performing the compilation.  -mcpu=native has no effect if GCC does not recognize the processor.
The other options specify a specific processor.  Code generated under those options runs best on that processor, and may not run at all on others.
The -mcpu options automatically enable or disable the following options:
-maltivec  -mfprnd  -mhard-float  -mmfcrf  -mmultiple -mpopcntb -mpopcntd  -mpowerpc64 -mpowerpc-gpopt  -mpowerpc-gfxopt -mmulhw -mdlmzb  -mmfpgpr  -mvsx -mcrypto  -mhtm  -mpower8-fusion -mpower8-vector -mquad-memory  -mquad-memory-atomic  -mfloat128 -mfloat128-hardware -mprefixed -mpcrel -mmma
The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn't necessarily reflect the actual hardware's capabilities.  If you wish to set an individual option to a particular value, you may specify it after the -mcpu option, like -mcpu=970 -mno-altivec.
On AIX, the -maltivec and -mpowerpc64 options are not enabled or disabled by the -mcpu option at present because AIX does not have full support for these options.  You may still enable or disable them individually if you're sure it'll work in your environment.
-mtune=cpu_type Set the instruction scheduling parameters for machine type cpu_type, but do not set the architecture type or register usage, as -mcpu=cpu_type does.  The same values for cpu_type are used for -mtune as for -mcpu.  If both are specified, the code generated uses the architecture and registers set by -mcpu, but the scheduling parameters set by -mtune.
-mcmodel=small Generate PowerPC64 code for the small model: The TOC is limited to 64k.
-mcmodel=medium Generate PowerPC64 code for the medium model: The TOC and other static data may be up to a total of 4G in size.  This is the default for 64-bit Linux.
-mcmodel=large Generate PowerPC64 code for the large model: The TOC may be up to 4G in size.  Other data and code is only limited by the 64-bit address space.
-maltivec -mno-altivec Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set.  You may also need to set -mabi=altivec to adjust the current ABI with AltiVec ABI enhancements.
When -maltivec is used, the element order for AltiVec intrinsics such as "vec_splat", "vec_extract", and "vec_insert" match array element order corresponding to the endianness of the target.  That is, element zero identifies the leftmost element in a vector register when targeting a big-endian platform, and identifies the rightmost element in a vector register when targeting a little-endian platform.
-mvrsave -mno-vrsave Generate VRSAVE instructions when generating AltiVec code.
-msecure-plt Generate code that allows ld and ld.so to build executables and shared libraries with non-executable ".plt" and ".got" sections. This is a PowerPC 32-bit SYSV ABI option.
-mbss-plt Generate code that uses a BSS ".plt" section that ld.so fills in, and requires ".plt" and ".got" sections that are both writable and executable.  This is a PowerPC 32-bit SYSV ABI option.
-misel -mno-isel This switch enables or disables the generation of ISEL instructions.
-mvsx -mno-vsx Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set.
-mcrypto -mno-crypto Enable the use (disable) of the built-in functions that allow direct access to the cryptographic instructions that were added in version 2.07 of the PowerPC ISA.
-mhtm -mno-htm Enable (disable) the use of the built-in functions that allow direct access to the Hardware Transactional Memory (HTM) instructions that were added in version 2.07 of the PowerPC ISA.
-mpower8-fusion -mno-power8-fusion Generate code that keeps (does not keeps) some integer operations adjacent so that the instructions can be fused together on power8 and later processors.
-mpower8-vector -mno-power8-vector Generate code that uses (does not use) the vector and scalar instructions that were added in version 2.07 of the PowerPC ISA. Also enable the use of built-in functions that allow more direct access to the vector instructions.
-mquad-memory -mno-quad-memory Generate code that uses (does not use) the non-atomic quad word memory instructions.  The -mquad-memory option requires use of 64-bit mode.
-mquad-memory-atomic -mno-quad-memory-atomic Generate code that uses (does not use) the atomic quad word memory instructions.  The -mquad-memory-atomic option requires use of 64-bit mode.
-mfloat128 -mno-float128 Enable/disable the __float128 keyword for IEEE 128-bit floating point and use either software emulation for IEEE 128-bit floating point or hardware instructions.
The VSX instruction set (-mvsx, -mcpu=power7, -mcpu=power8), or -mcpu=power9 must be enabled to use the IEEE 128-bit floating point support.  The IEEE 128-bit floating point support only works on PowerPC Linux systems.
The default for -mfloat128 is enabled on PowerPC Linux systems using the VSX instruction set, and disabled on other systems.
If you use the ISA 3.0 instruction set (-mpower9-vector or -mcpu=power9) on a 64-bit system, the IEEE 128-bit floating point support will also enable the generation of ISA 3.0 IEEE 128-bit floating point instructions.  Otherwise, if you do not specify to generate ISA 3.0 instructions or you are targeting a 32-bit big endian system, IEEE 128-bit floating point will be done with software emulation.
-mfloat128-hardware -mno-float128-hardware Enable/disable using ISA 3.0 hardware instructions to support the __float128 data type.
The default for -mfloat128-hardware is enabled on PowerPC Linux systems using the ISA 3.0 instruction set, and disabled on other systems.
-m32 -m64 Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux).  The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant.  The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for -mpowerpc64.
-mfull-toc -mno-fp-in-toc -mno-sum-in-toc -mminimal-toc Modify generation of the TOC (Table Of Contents), which is created for every executable file.  The -mfull-toc option is selected by default.  In that case, GCC allocates at least one TOC entry for each unique non-automatic variable reference in your program.  GCC also places floating-point constants in the TOC.  However, only 16,384 entries are available in the TOC.
If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the -mno-fp-in-toc and -mno-sum-in-toc options.  -mno-fp-in-toc prevents GCC from putting floating-point constants in the TOC and -mno-sum-in-toc forces GCC to generate code to calculate the sum of an address and a constant at run time instead of putting that sum into the TOC.  You may specify one or both of these options.  Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space.
If you still run out of space in the TOC even when you specify both of these options, specify -mminimal-toc instead.  This option causes GCC to make only one TOC entry for every file.  When you specify this option, GCC produces code that is slower and larger but which uses extremely little TOC space.  You may wish to use this option only on files that contain less frequently-executed code.
-maix64 -maix32 Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit "long" type, and the infrastructure needed to support them. Specifying -maix64 implies -mpowerpc64, while -maix32 disables the 64-bit ABI and implies -mno-powerpc64.  GCC defaults to -maix32.
-mxl-compat -mno-xl-compat Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI.  Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs.  Do not assume that most significant double in 128-bit long double value is properly rounded when comparing values and converting to double.  Use XL symbol names for long double support routines.
The AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared.  IBM XL compilers access floating-point arguments that do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization.
-mpe Support IBM RS/6000 SP Parallel Environment (PE).  Link an application written to use message passing with special startup code to enable the application to run.  The system must have PE installed in the standard location (/usr/lpp/ppe.poe/), or the specs file must be overridden with the -specs= option to specify the appropriate directory location.  The Parallel Environment does not support threads, so the -mpe option and the -pthread option are incompatible.
-malign-natural -malign-power On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option -malign-natural overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option -malign-power instructs GCC to follow the ABI-specified alignment rules.  GCC defaults to the standard alignment defined in the ABI.
On 64-bit Darwin, natural alignment is the default, and -malign-power is not supported.
-msoft-float -mhard-float Generate code that does not use (uses) the floating-point register set.  Software floating-point emulation is provided if you use the -msoft-float option, and pass the option to GCC when linking.
-mmultiple -mno-multiple Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions.  These instructions are generated by default on POWER systems, and not generated on PowerPC systems.  Do not use -mmultiple on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode.  The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode.
-mupdate -mno-update Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location.  These instructions are generated by default.  If you use -mno-update, there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data.
-mavoid-indexed-addresses -mno-avoid-indexed-addresses Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary.  This option is enabled by default when targeting Power6 and disabled otherwise.
-mfused-madd -mno-fused-madd Generate code that uses (does not use) the floating-point multiply and accumulate instructions.  These instructions are generated by default if hardware floating point is used.  The machine-dependent -mfused-madd option is now mapped to the machine-independent -ffp-contract=fast option, and -mno-fused-madd is mapped to -ffp-contract=off.
-mmulhw -mno-mulhw Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.  These instructions are generated by default when targeting those processors.
-mdlmzb -mno-dlmzb Generate code that uses (does not use) the string-search dlmzb instruction on the IBM 405, 440, 464 and 476 processors.  This instruction is generated by default when targeting those processors.
-mno-bit-align -mbit-align On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field.
For example, by default a structure containing nothing but 8 "unsigned" bit-fields of length 1 is aligned to a 4-byte boundary and has a size of 4 bytes.  By using -mno-bit-align, the structure is aligned to a 1-byte boundary and is 1 byte in size.
-mno-strict-align -mstrict-align On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references are handled by the system.
-mrelocatable -mno-relocatable Generate code that allows (does not allow) a static executable to be relocated to a different address at run time.  A simple embedded PowerPC system loader should relocate the entire contents of ".got2" and 4-byte locations listed in the ".fixup" section, a table of 32-bit addresses generated by this option.  For this to work, all objects linked together must be compiled with -mrelocatable or -mrelocatable-lib.  -mrelocatable code aligns the stack to an 8-byte boundary.
-mrelocatable-lib -mno-relocatable-lib Like -mrelocatable, -mrelocatable-lib generates a ".fixup" section to allow static executables to be relocated at run time, but -mrelocatable-lib does not use the smaller stack alignment of -mrelocatable.  Objects compiled with -mrelocatable-lib may be linked with objects compiled with any combination of the -mrelocatable options.
-mno-toc -mtoc On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program.
-mlittle -mlittle-endian On System V.4 and embedded PowerPC systems compile code for the processor in little-endian mode.  The -mlittle-endian option is the same as -mlittle.
-mbig -mbig-endian On System V.4 and embedded PowerPC systems compile code for the processor in big-endian mode.  The -mbig-endian option is the same as -mbig.
-mdynamic-no-pic On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable.  The resulting code is suitable for applications, but not shared libraries.
-mprioritize-restricted-insns=priority This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass.  The argument priority takes the value 0, 1, or 2 to assign no, highest, or second-highest (respectively) priority to dispatch-slot restricted instructions.
-msched-costly-dep=dependence_type This option controls which dependences are considered costly by the target during instruction scheduling.  The argument dependence_type takes one of the following values:
no  No dependence is costly.
all All dependences are costly.
true_store_to_load A true dependence from store to load is costly.
store_to_load Any dependence from store to load is costly.
number Any dependence for which the latency is greater than or equal to number is costly.
-minsert-sched-nops=scheme This option controls which NOP insertion scheme is used during the second scheduling pass.  The argument scheme takes one of the following values:
no  Don't insert NOPs.
pad Pad with NOPs any dispatch group that has vacant issue slots, according to the scheduler's grouping.
regroup_exact Insert NOPs to force costly dependent insns into separate groups. Insert exactly as many NOPs as needed to force an insn to a new group, according to the estimated processor grouping.
number Insert NOPs to force costly dependent insns into separate groups. Insert number NOPs to force an insn to a new group.
-mcall-sysv On System V.4 and embedded PowerPC systems compile code using calling conventions that adhere to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement.  This is the default unless you configured GCC using powerpc-*-eabiaix.
-mcall-sysv-eabi -mcall-eabi Specify both -mcall-sysv and -meabi options.
-mcall-sysv-noeabi Specify both -mcall-sysv and -mno-eabi options.
-mcall-aixdesc On System V.4 and embedded PowerPC systems compile code for the AIX operating system.
-mcall-linux On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system.
-mcall-freebsd On System V.4 and embedded PowerPC systems compile code for the FreeBSD operating system.
-mcall-netbsd On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system.
-mcall-openbsd On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system.
-mtraceback=traceback_type Select the type of traceback table. Valid values for traceback_type are full, part, and no.
-maix-struct-return Return all structures in memory (as specified by the AIX ABI).
-msvr4-struct-return Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI).
-mabi=abi-type Extend the current ABI with a particular extension, or remove such extension.  Valid values are: altivec, no-altivec, ibmlongdouble, ieeelongdouble, elfv1, elfv2, and for AIX: vec-extabi, vec-default.
-mabi=ibmlongdouble Change the current ABI to use IBM extended-precision long double. This is not likely to work if your system defaults to using IEEE extended-precision long double.  If you change the long double type from IEEE extended-precision, the compiler will issue a warning unless you use the -Wno-psabi option.  Requires -mlong-double-128 to be enabled.
-mabi=ieeelongdouble Change the current ABI to use IEEE extended-precision long double. This is not likely to work if your system defaults to using IBM extended-precision long double.  If you change the long double type from IBM extended-precision, the compiler will issue a warning unless you use the -Wno-psabi option.  Requires -mlong-double-128 to be enabled.
-mabi=elfv1 Change the current ABI to use the ELFv1 ABI.  This is the default ABI for big-endian PowerPC 64-bit Linux.  Overriding the default ABI requires special system support and is likely to fail in spectacular ways.
-mabi=elfv2 Change the current ABI to use the ELFv2 ABI.  This is the default ABI for little-endian PowerPC 64-bit Linux.  Overriding the default ABI requires special system support and is likely to fail in spectacular ways.
-mgnu-attribute -mno-gnu-attribute Emit .gnu_attribute assembly directives to set tag/value pairs in a .gnu.attributes section that specify ABI variations in function parameters or return values.
-mprototype -mno-prototype On System V.4 and embedded PowerPC systems assume that all calls to variable argument functions are properly prototyped.  Otherwise, the compiler must insert an instruction before every non-prototyped call to set or clear bit 6 of the condition code register ("CR") to indicate whether floating-point values are passed in the floating- point registers in case the function takes variable arguments.  With -mprototype, only calls to prototyped variable argument functions set or clear the bit.
-msim On embedded PowerPC systems, assume that the startup module is called sim-crt0.o and that the standard C libraries are libsim.a and libc.a. This is the default for powerpc-*-eabisim configurations.
-mmvme On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libmvme.a and libc.a.
-mads On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libads.a and libc.a.
-myellowknife On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libyk.a and libc.a.
-mvxworks On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system.
-memb On embedded PowerPC systems, set the "PPC_EMB" bit in the ELF flags header to indicate that eabi extended relocations are used.
-meabi -mno-eabi On System V.4 and embedded PowerPC systems do (do not) adhere to the Embedded Applications Binary Interface (EABI), which is a set of modifications to the System V.4 specifications.  Selecting -meabi means that the stack is aligned to an 8-byte boundary, a function "__eabi" is called from "main" to set up the EABI environment, and the -msdata option can use both "r2" and "r13" to point to two separate small data areas.  Selecting -mno-eabi means that the stack is aligned to a 16-byte boundary, no EABI initialization function is called from "main", and the -msdata option only uses "r13" to point to a single small data area.  The -meabi option is on by default if you configured GCC using one of the powerpc*-*-eabi* options.
-msdata=eabi On System V.4 and embedded PowerPC systems, put small initialized "const" global and static data in the ".sdata2" section, which is pointed to by register "r2".  Put small initialized non-"const" global and static data in the ".sdata" section, which is pointed to by register "r13".  Put small uninitialized global and static data in the ".sbss" section, which is adjacent to the ".sdata" section.  The -msdata=eabi option is incompatible with the -mrelocatable option. The -msdata=eabi option also sets the -memb option.
-msdata=sysv On System V.4 and embedded PowerPC systems, put small global and static data in the ".sdata" section, which is pointed to by register "r13".  Put small uninitialized global and static data in the ".sbss" section, which is adjacent to the ".sdata" section.  The -msdata=sysv option is incompatible with the -mrelocatable option.
-msdata=default -msdata On System V.4 and embedded PowerPC systems, if -meabi is used, compile code the same as -msdata=eabi, otherwise compile code the same as -msdata=sysv.
-msdata=data On System V.4 and embedded PowerPC systems, put small global data in the ".sdata" section.  Put small uninitialized global data in the ".sbss" section.  Do not use register "r13" to address small data however.  This is the default behavior unless other -msdata options are used.
-msdata=none -mno-sdata On embedded PowerPC systems, put all initialized global and static data in the ".data" section, and all uninitialized data in the ".bss" section.
-mreadonly-in-sdata Put read-only objects in the ".sdata" section as well.  This is the default.
-mblock-move-inline-limit=num Inline all block moves (such as calls to "memcpy" or structure copies) less than or equal to num bytes.  The minimum value for num is 32 bytes on 32-bit targets and 64 bytes on 64-bit targets.  The default value is target-specific.
-mblock-compare-inline-limit=num Generate non-looping inline code for all block compares (such as calls to "memcmp" or structure compares) less than or equal to num bytes. If num is 0, all inline expansion (non-loop and loop) of block compare is disabled. The default value is target-specific.
-mblock-compare-inline-loop-limit=num Generate an inline expansion using loop code for all block compares that are less than or equal to num bytes, but greater than the limit for non-loop inline block compare expansion. If the block length is not constant, at most num bytes will be compared before "memcmp" is called to compare the remainder of the block. The default value is target-specific.
-mstring-compare-inline-limit=num Compare at most num string bytes with inline code.  If the difference or end of string is not found at the end of the inline compare a call to "strcmp" or "strncmp" will take care of the rest of the comparison. The default is 64 bytes.
-G num On embedded PowerPC systems, put global and static items less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS section.  By default, num is 8.  The -G num switch is also passed to the linker.  All modules should be compiled with the same -G num value.
-mregnames -mno-regnames On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms.
-mlongcall -mno-longcall By default assume that all calls are far away so that a longer and more expensive calling sequence is required.  This is required for calls farther than 32 megabytes (33,554,432 bytes) from the current location.  A short call is generated if the compiler knows the call cannot be that far away.  This setting can be overridden by the "shortcall" function attribute, or by "#pragma longcall(0)".
Some linkers are capable of detecting out-of-range calls and generating glue code on the fly.  On these systems, long calls are unnecessary and generate slower code.  As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64.  It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well.
On PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNU linkers, GCC can generate long calls using an inline PLT call sequence (see -mpltseq).  PowerPC with -mbss-plt and PowerPC64 ELFv1 (big-endian) do not support inline PLT calls.
On Darwin/PPC systems, "#pragma longcall" generates "jbsr callee, L42", plus a branch island (glue code).  The two target addresses represent the callee and the branch island.  The Darwin/PPC linker prefers the first address and generates a "bl callee" if the PPC "bl" instruction reaches the callee directly; otherwise, the linker generates "bl L42" to call the branch island.  The branch island is appended to the body of the calling function; it computes the full 32-bit address of the callee and jumps to it.
On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it.
In the future, GCC may ignore all longcall specifications when the linker is known to generate glue.
-mpltseq -mno-pltseq Implement (do not implement) -fno-plt and long calls using an inline PLT call sequence that supports lazy linking and long calls to functions in dlopen'd shared libraries.  Inline PLT calls are only supported on PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNU linkers, and are enabled by default if the support is detected when configuring GCC, and, in the case of 32-bit PowerPC, if GCC is configured with --enable-secureplt.  -mpltseq code and -mbss-plt 32-bit PowerPC relocatable objects may not be linked together.
-mtls-markers -mno-tls-markers Mark (do not mark) calls to "__tls_get_addr" with a relocation specifying the function argument.  The relocation allows the linker to reliably associate function call with argument setup instructions for TLS optimization, which in turn allows GCC to better schedule the sequence.
-mrecip -mno-recip This option enables use of the reciprocal estimate and reciprocal square root estimate instructions with additional Newton-Raphson steps to increase precision instead of doing a divide or square root and divide for floating-point arguments.  You should use the -ffast-math option when using -mrecip (or at least -funsafe-math-optimizations, -ffinite-math-only, -freciprocal-math and -fno-trapping-math).  Note that while the throughput of the sequence is generally higher than the throughput of the non- reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square roots.
-mrecip=opt This option controls which reciprocal estimate instructions may be used.  opt is a comma-separated list of options, which may be preceded by a "!" to invert the option:
all Enable all estimate instructions.
default Enable the default instructions, equivalent to -mrecip.
none Disable all estimate instructions, equivalent to -mno-recip.
div Enable the reciprocal approximation instructions for both single and double precision.
divf Enable the single-precision reciprocal approximation instructions.
divd Enable the double-precision reciprocal approximation instructions.
rsqrt Enable the reciprocal square root approximation instructions for both single and double precision.
rsqrtf Enable the single-precision reciprocal square root approximation instructions.
rsqrtd Enable the double-precision reciprocal square root approximation instructions.
So, for example, -mrecip=all,!rsqrtd enables all of the reciprocal estimate instructions, except for the "FRSQRTE", "XSRSQRTEDP", and "XVRSQRTEDP" instructions which handle the double-precision reciprocal square root calculations.
-mrecip-precision -mno-recip-precision Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI.  Selecting -mcpu=power6, -mcpu=power7 or -mcpu=power8 automatically selects -mrecip-precision.  The double-precision square root estimate instructions are not generated by default on low- precision machines, since they do not provide an estimate that converges after three steps.
-mveclibabi=type Specifies the ABI type to use for vectorizing intrinsics using an external library.  The only type supported at present is mass, which specifies to use IBM's Mathematical Acceleration Subsystem (MASS) libraries for vectorizing intrinsics using external libraries.  GCC currently emits calls to "acosd2", "acosf4", "acoshd2", "acoshf4", "asind2", "asinf4", "asinhd2", "asinhf4", "atan2d2", "atan2f4", "atand2", "atanf4", "atanhd2", "atanhf4", "cbrtd2", "cbrtf4", "cosd2", "cosf4", "coshd2", "coshf4", "erfcd2", "erfcf4", "erfd2", "erff4", "exp2d2", "exp2f4", "expd2", "expf4", "expm1d2", "expm1f4", "hypotd2", "hypotf4", "lgammad2", "lgammaf4", "log10d2", "log10f4", "log1pd2", "log1pf4", "log2d2", "log2f4", "logd2", "logf4", "powd2", "powf4", "sind2", "sinf4", "sinhd2", "sinhf4", "sqrtd2", "sqrtf4", "tand2", "tanf4", "tanhd2", and "tanhf4" when generating code for power7.  Both -ftree-vectorize and -funsafe-math-optimizations must also be enabled.  The MASS libraries must be specified at link time.
-mfriz -mno-friz Generate (do not generate) the "friz" instruction when the -funsafe-math-optimizations option is used to optimize rounding of floating-point values to 64-bit integer and back to floating point. The "friz" instruction does not return the same value if the floating-point number is too large to fit in an integer.
-mpointers-to-nested-functions -mno-pointers-to-nested-functions Generate (do not generate) code to load up the static chain register ("r11") when calling through a pointer on AIX and 64-bit Linux systems where a function pointer points to a 3-word descriptor giving the function address, TOC value to be loaded in register "r2", and static chain value to be loaded in register "r11".  The -mpointers-to-nested-functions is on by default.  You cannot call through pointers to nested functions or pointers to functions compiled in other languages that use the static chain if you use -mno-pointers-to-nested-functions.
-msave-toc-indirect -mno-save-toc-indirect Generate (do not generate) code to save the TOC value in the reserved stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems.  If the TOC value is not saved in the prologue, it is saved just before the call through the pointer.  The -mno-save-toc-indirect option is the default.
-mcompat-align-parm -mno-compat-align-parm Generate (do not generate) code to pass structure parameters with a maximum alignment of 64 bits, for compatibility with older versions of GCC.
Older versions of GCC (prior to 4.9.0) incorrectly did not align a structure parameter on a 128-bit boundary when that structure contained a member requiring 128-bit alignment.  This is corrected in more recent versions of GCC.  This option may be used to generate code that is compatible with functions compiled with older versions of GCC.
The -mno-compat-align-parm option is the default.
-mstack-protector-guard=guard -mstack-protector-guard-reg=reg -mstack-protector-guard-offset=offset -mstack-protector-guard-symbol=symbol Generate stack protection code using canary at guard.  Supported locations are global for global canary or tls for per-thread canary in the TLS block (the default with GNU libc version 2.4 or later).
With the latter choice the options -mstack-protector-guard-reg=reg and -mstack-protector-guard-offset=offset furthermore specify which register to use as base register for reading the canary, and from what offset from that base register. The default for those is as specified in the relevant ABI.  -mstack-protector-guard-symbol=symbol overrides the offset with a symbol reference to a canary in the TLS block.
-mpcrel -mno-pcrel Generate (do not generate) pc-relative addressing when the option -mcpu=future is used.  The -mpcrel option requires that the medium code model (-mcmodel=medium) and prefixed addressing (-mprefixed) options are enabled.
-mprefixed -mno-prefixed Generate (do not generate) addressing modes using prefixed load and store instructions when the option -mcpu=future is used.
-mmma -mno-mma Generate (do not generate) the MMA instructions when the option -mcpu=future is used.
-mblock-ops-unaligned-vsx -mno-block-ops-unaligned-vsx Generate (do not generate) unaligned vsx loads and stores for inline expansion of "memcpy" and "memmove".
RX Options
These command-line options are defined for RX targets:
-m64bit-doubles -m32bit-doubles Make the "double" data type be 64 bits (-m64bit-doubles) or 32 bits (-m32bit-doubles) in size.  The default is -m32bit-doubles.  Note RX floating-point hardware only works on 32-bit values, which is why the default is -m32bit-doubles.
-fpu -nofpu Enables (-fpu) or disables (-nofpu) the use of RX floating-point hardware.  The default is enabled for the RX600 series and disabled for the RX200 series.
Floating-point instructions are only generated for 32-bit floating- point values, however, so the FPU hardware is not used for doubles if the -m64bit-doubles option is used.
Note If the -fpu option is enabled then -funsafe-math-optimizations is also enabled automatically.  This is because the RX FPU instructions are themselves unsafe.
-mcpu=name Selects the type of RX CPU to be targeted.  Currently three types are supported, the generic RX600 and RX200 series hardware and the specific RX610 CPU.  The default is RX600.
The only difference between RX600 and RX610 is that the RX610 does not support the "MVTIPL" instruction.
The RX200 series does not have a hardware floating-point unit and so -nofpu is enabled by default when this type is selected.
-mbig-endian-data -mlittle-endian-data Store data (but not code) in the big-endian format.  The default is -mlittle-endian-data, i.e. to store data in the little-endian format.
-msmall-data-limit=N Specifies the maximum size in bytes of global and static variables which can be placed into the small data area.  Using the small data area can lead to smaller and faster code, but the size of area is limited and it is up to the programmer to ensure that the area does not overflow.  Also when the small data area is used one of the RX's registers (usually "r13") is reserved for use pointing to this area, so it is no longer available for use by the compiler.  This could result in slower and/or larger code if variables are pushed onto the stack instead of being held in this register.
Note, common variables (variables that have not been initialized) and constants are not placed into the small data area as they are assigned to other sections in the output executable.
The default value is zero, which disables this feature.  Note, this feature is not enabled by default with higher optimization levels (-O2 etc) because of the potentially detrimental effects of reserving a register.  It is up to the programmer to experiment and discover whether this feature is of benefit to their program.  See the description of the -mpid option for a description of how the actual register to hold the small data area pointer is chosen.
-msim -mno-sim Use the simulator runtime.  The default is to use the libgloss board- specific runtime.
-mas100-syntax -mno-as100-syntax When generating assembler output use a syntax that is compatible with Renesas's AS100 assembler.  This syntax can also be handled by the GAS assembler, but it has some restrictions so it is not generated by default.
-mmax-constant-size=N Specifies the maximum size, in bytes, of a constant that can be used as an operand in a RX instruction.  Although the RX instruction set does allow constants of up to 4 bytes in length to be used in instructions, a longer value equates to a longer instruction.  Thus in some circumstances it can be beneficial to restrict the size of constants that are used in instructions.  Constants that are too big are instead placed into a constant pool and referenced via register indirection.
The value N can be between 0 and 4.  A value of 0 (the default) or 4 means that constants of any size are allowed.
-mrelax Enable linker relaxation.  Linker relaxation is a process whereby the linker attempts to reduce the size of a program by finding shorter versions of various instructions.  Disabled by default.