neulab/tldr huggingface dataset:
-mint-register=N Specify the number of registers to reserve for fast interrupt handler functions.  The value N can be between 0 and 4.  A value of 1 means that register "r13" is reserved for the exclusive use of fast interrupt handlers.  A value of 2 reserves "r13" and "r12".  A value of 3 reserves "r13", "r12" and "r11", and a value of 4 reserves "r13" through "r10".  A value of 0, the default, does not reserve any registers.
-msave-acc-in-interrupts Specifies that interrupt handler functions should preserve the accumulator register.  This is only necessary if normal code might use the accumulator register, for example because it performs 64-bit multiplications.  The default is to ignore the accumulator as this makes the interrupt handlers faster.
-mpid -mno-pid Enables the generation of position independent data.  When enabled any access to constant data is done via an offset from a base address held in a register.  This allows the location of constant data to be determined at run time without requiring the executable to be relocated, which is a benefit to embedded applications with tight memory constraints.  Data that can be modified is not affected by this option.
Note, using this feature reserves a register, usually "r13", for the constant data base address.  This can result in slower and/or larger code, especially in complicated functions.
The actual register chosen to hold the constant data base address depends upon whether the -msmall-data-limit and/or the -mint-register command-line options are enabled.  Starting with register "r13" and proceeding downwards, registers are allocated first to satisfy the requirements of -mint-register, then -mpid and finally -msmall-data-limit.  Thus it is possible for the small data area register to be "r8" if both -mint-register=4 and -mpid are specified on the command line.
By default this feature is not enabled.  The default can be restored via the -mno-pid command-line option.
-mno-warn-multiple-fast-interrupts -mwarn-multiple-fast-interrupts Prevents GCC from issuing a warning message if it finds more than one fast interrupt handler when it is compiling a file.  The default is to issue a warning for each extra fast interrupt handler found, as the RX only supports one such interrupt.
-mallow-string-insns -mno-allow-string-insns Enables or disables the use of the string manipulation instructions "SMOVF", "SCMPU", "SMOVB", "SMOVU", "SUNTIL" "SWHILE" and also the "RMPA" instruction.  These instructions may prefetch data, which is not safe to do if accessing an I/O register.  (See section 12.2.7 of the RX62N Group User's Manual for more information).
The default is to allow these instructions, but it is not possible for GCC to reliably detect all circumstances where a string instruction might be used to access an I/O register, so their use cannot be disabled automatically.  Instead it is reliant upon the programmer to use the -mno-allow-string-insns option if their program accesses I/O space.
When the instructions are enabled GCC defines the C preprocessor symbol "__RX_ALLOW_STRING_INSNS__", otherwise it defines the symbol "__RX_DISALLOW_STRING_INSNS__".
-mjsr -mno-jsr Use only (or not only) "JSR" instructions to access functions.  This option can be used when code size exceeds the range of "BSR" instructions.  Note that -mno-jsr does not mean to not use "JSR" but instead means that any type of branch may be used.
Note: The generic GCC command-line option -ffixed-reg has special significance to the RX port when used with the "interrupt" function attribute.  This attribute indicates a function intended to process fast interrupts.  GCC ensures that it only uses the registers "r10", "r11", "r12" and/or "r13" and only provided that the normal use of the corresponding registers have been restricted via the -ffixed-reg or -mint-register command-line options.
S/390 and zSeries Options
These are the -m options defined for the S/390 and zSeries architecture.
-mhard-float -msoft-float Use (do not use) the hardware floating-point instructions and registers for floating-point operations.  When -msoft-float is specified, functions in libgcc.a are used to perform floating-point operations.  When -mhard-float is specified, the compiler generates IEEE floating-point instructions.  This is the default.
-mhard-dfp -mno-hard-dfp Use (do not use) the hardware decimal-floating-point instructions for decimal-floating-point operations.  When -mno-hard-dfp is specified, functions in libgcc.a are used to perform decimal-floating-point operations.  When -mhard-dfp is specified, the compiler generates decimal-floating-point hardware instructions.  This is the default for -march=z9-ec or higher.
-mlong-double-64 -mlong-double-128 These switches control the size of "long double" type. A size of 64 bits makes the "long double" type equivalent to the "double" type. This is the default.
-mbackchain -mno-backchain Store (do not store) the address of the caller's frame as backchain pointer into the callee's stack frame.  A backchain may be needed to allow debugging using tools that do not understand DWARF call frame information.  When -mno-packed-stack is in effect, the backchain pointer is stored at the bottom of the stack frame; when -mpacked-stack is in effect, the backchain is placed into the topmost word of the 96/160 byte register save area.
In general, code compiled with -mbackchain is call-compatible with code compiled with -mno-backchain; however, use of the backchain for debugging purposes usually requires that the whole binary is built with -mbackchain.  Note that the combination of -mbackchain, -mpacked-stack and -mhard-float is not supported.  In order to build a linux kernel use -msoft-float.
The default is to not maintain the backchain.
-mpacked-stack -mno-packed-stack Use (do not use) the packed stack layout.  When -mno-packed-stack is specified, the compiler uses the all fields of the 96/160 byte register save area only for their default purpose; unused fields still take up stack space.  When -mpacked-stack is specified, register save slots are densely packed at the top of the register save area; unused space is reused for other purposes, allowing for more efficient use of the available stack space.  However, when -mbackchain is also in effect, the topmost word of the save area is always used to store the backchain, and the return address register is always saved two words below the backchain.
As long as the stack frame backchain is not used, code generated with -mpacked-stack is call-compatible with code generated with -mno-packed-stack.  Note that some non-FSF releases of GCC 2.95 for S/390 or zSeries generated code that uses the stack frame backchain at run time, not just for debugging purposes.  Such code is not call- compatible with code compiled with -mpacked-stack.  Also, note that the combination of -mbackchain, -mpacked-stack and -mhard-float is not supported.  In order to build a linux kernel use -msoft-float.
The default is to not use the packed stack layout.
-msmall-exec -mno-small-exec Generate (or do not generate) code using the "bras" instruction to do subroutine calls.  This only works reliably if the total executable size does not exceed 64k.  The default is to use the "basr" instruction instead, which does not have this limitation.
-m64 -m31 When -m31 is specified, generate code compliant to the GNU/Linux for S/390 ABI.  When -m64 is specified, generate code compliant to the GNU/Linux for zSeries ABI.  This allows GCC in particular to generate 64-bit instructions.  For the s390 targets, the default is -m31, while the s390x targets default to -m64.
-mzarch -mesa When -mzarch is specified, generate code using the instructions available on z/Architecture.  When -mesa is specified, generate code using the instructions available on ESA/390.  Note that -mesa is not possible with -m64.  When generating code compliant to the GNU/Linux for S/390 ABI, the default is -mesa.  When generating code compliant to the GNU/Linux for zSeries ABI, the default is -mzarch.
-mhtm -mno-htm The -mhtm option enables a set of builtins making use of instructions available with the transactional execution facility introduced with the IBM zEnterprise EC12 machine generation S/390 System z Built-in Functions.  -mhtm is enabled by default when using -march=zEC12.
-mvx -mno-vx When -mvx is specified, generate code using the instructions available with the vector extension facility introduced with the IBM z13 machine generation.  This option changes the ABI for some vector type values with regard to alignment and calling conventions.  In case vector type values are being used in an ABI-relevant context a GAS .gnu_attribute command will be added to mark the resulting binary with the ABI used.  -mvx is enabled by default when using -march=z13.
-mzvector -mno-zvector The -mzvector option enables vector language extensions and builtins using instructions available with the vector extension facility introduced with the IBM z13 machine generation.  This option adds support for vector to be used as a keyword to define vector type variables and arguments.  vector is only available when GNU extensions are enabled.  It will not be expanded when requesting strict standard compliance e.g. with -std=c99.  In addition to the GCC low-level builtins -mzvector enables a set of builtins added for compatibility with AltiVec-style implementations like Power and Cell. In order to make use of these builtins the header file vecintrin.h needs to be included.  -mzvector is disabled by default.
-mmvcle -mno-mvcle Generate (or do not generate) code using the "mvcle" instruction to perform block moves.  When -mno-mvcle is specified, use a "mvc" loop instead.  This is the default unless optimizing for size.
-mdebug -mno-debug Print (or do not print) additional debug information when compiling. The default is to not print debug information.
-march=cpu-type Generate code that runs on cpu-type, which is the name of a system representing a certain processor type.  Possible values for cpu-type are z900/arch5, z990/arch6, z9-109, z9-ec/arch7, z10/arch8, z196/arch9, zEC12, z13/arch11, z14/arch12, z15/arch13, and native.
The default is -march=z900.
Specifying native as cpu type can be used to select the best architecture option for the host processor.  -march=native has no effect if GCC does not recognize the processor.
-mtune=cpu-type Tune to cpu-type everything applicable about the generated code, except for the ABI and the set of available instructions.  The list of cpu-type values is the same as for -march.  The default is the value used for -march.
-mtpf-trace -mno-tpf-trace Generate code that adds (does not add) in TPF OS specific branches to trace routines in the operating system.  This option is off by default, even when compiling for the TPF OS.
-mtpf-trace-skip -mno-tpf-trace-skip Generate code that changes (does not change) the default branch targets enabled by -mtpf-trace to point to specialized trace routines providing the ability of selectively skipping function trace entries for the TPF OS.  This option is off by default, even when compiling for the TPF OS and specifying -mtpf-trace.
-mfused-madd -mno-fused-madd Generate code that uses (does not use) the floating-point multiply and accumulate instructions.  These instructions are generated by default if hardware floating point is used.
-mwarn-framesize=framesize Emit a warning if the current function exceeds the given frame size. Because this is a compile-time check it doesn't need to be a real problem when the program runs.  It is intended to identify functions that most probably cause a stack overflow.  It is useful to be used in an environment with limited stack size e.g. the linux kernel.
-mwarn-dynamicstack Emit a warning if the function calls "alloca" or uses dynamically- sized arrays.  This is generally a bad idea with a limited stack size.
-mstack-guard=stack-guard -mstack-size=stack-size If these options are provided the S/390 back end emits additional instructions in the function prologue that trigger a trap if the stack size is stack-guard bytes above the stack-size (remember that the stack on S/390 grows downward).  If the stack-guard option is omitted the smallest power of 2 larger than the frame size of the compiled function is chosen.  These options are intended to be used to help debugging stack overflow problems.  The additionally emitted code causes only little overhead and hence can also be used in production-like systems without greater performance degradation.  The given values have to be exact powers of 2 and stack-size has to be greater than stack-guard without exceeding 64k.  In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by stack-size.  The stack- guard option can only be used in conjunction with stack-size.
-mhotpatch=pre-halfwords,post-halfwords If the hotpatch option is enabled, a "hot-patching" function prologue is generated for all functions in the compilation unit.  The funtion label is prepended with the given number of two-byte NOP instructions (pre-halfwords, maximum 1000000).  After the label, 2 * post- halfwords bytes are appended, using the largest NOP like instructions the architecture allows (maximum 1000000).
If both arguments are zero, hotpatching is disabled.
This option can be overridden for individual functions with the "hotpatch" attribute.
Score Options
These options are defined for Score implementations:
-meb Compile code for big-endian mode.  This is the default.
-mel Compile code for little-endian mode.
-mnhwloop Disable generation of "bcnz" instructions.
-muls Enable generation of unaligned load and store instructions.
-mscore5 Specify the SCORE5 as the target architecture.
-mscore5u Specify the SCORE5U of the target architecture.
-mscore7 Specify the SCORE7 as the target architecture. This is the default.
-mscore7d Specify the SCORE7D as the target architecture.
SH Options
These -m options are defined for the SH implementations:
-m1 Generate code for the SH1.
-m2 Generate code for the SH2.
-m2e Generate code for the SH2e.
-m2a-nofpu Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way that the floating-point unit is not used.
-m2a-single-only Generate code for the SH2a-FPU, in such a way that no double- precision floating-point operations are used.
-m2a-single Generate code for the SH2a-FPU assuming the floating-point unit is in single-precision mode by default.
-m2a Generate code for the SH2a-FPU assuming the floating-point unit is in double-precision mode by default.
-m3 Generate code for the SH3.
-m3e Generate code for the SH3e.
-m4-nofpu Generate code for the SH4 without a floating-point unit.
-m4-single-only Generate code for the SH4 with a floating-point unit that only supports single-precision arithmetic.
-m4-single Generate code for the SH4 assuming the floating-point unit is in single-precision mode by default.
-m4 Generate code for the SH4.
-m4-100 Generate code for SH4-100.
-m4-100-nofpu Generate code for SH4-100 in such a way that the floating-point unit is not used.
-m4-100-single Generate code for SH4-100 assuming the floating-point unit is in single-precision mode by default.
-m4-100-single-only Generate code for SH4-100 in such a way that no double-precision floating-point operations are used.
-m4-200 Generate code for SH4-200.
-m4-200-nofpu Generate code for SH4-200 without in such a way that the floating- point unit is not used.
-m4-200-single Generate code for SH4-200 assuming the floating-point unit is in single-precision mode by default.
-m4-200-single-only Generate code for SH4-200 in such a way that no double-precision floating-point operations are used.
-m4-300 Generate code for SH4-300.
-m4-300-nofpu Generate code for SH4-300 without in such a way that the floating- point unit is not used.
-m4-300-single Generate code for SH4-300 in such a way that no double-precision floating-point operations are used.
-m4-300-single-only Generate code for SH4-300 in such a way that no double-precision floating-point operations are used.
-m4-340 Generate code for SH4-340 (no MMU, no FPU).
-m4-500 Generate code for SH4-500 (no FPU).  Passes -isa=sh4-nofpu to the assembler.
-m4a-nofpu Generate code for the SH4al-dsp, or for a SH4a in such a way that the floating-point unit is not used.
-m4a-single-only Generate code for the SH4a, in such a way that no double-precision floating-point operations are used.
-m4a-single Generate code for the SH4a assuming the floating-point unit is in single-precision mode by default.
-m4a Generate code for the SH4a.
-m4al Same as -m4a-nofpu, except that it implicitly passes -dsp to the assembler.  GCC doesn't generate any DSP instructions at the moment.
-mb Compile code for the processor in big-endian mode.
-ml Compile code for the processor in little-endian mode.
-mdalign Align doubles at 64-bit boundaries.  Note that this changes the calling conventions, and thus some functions from the standard C library do not work unless you recompile it first with -mdalign.
-mbigtable Use 32-bit offsets in "switch" tables.  The default is to use 16-bit offsets.
-mbitops Enable the use of bit manipulation instructions on SH2A.
-mfmovd Enable the use of the instruction "fmovd".  Check -mdalign for alignment constraints.
-mrenesas Comply with the calling conventions defined by Renesas.
-mno-renesas Comply with the calling conventions defined for GCC before the Renesas conventions were available.  This option is the default for all targets of the SH toolchain.
-mnomacsave Mark the "MAC" register as call-clobbered, even if -mrenesas is given.
-mieee -mno-ieee Control the IEEE compliance of floating-point comparisons, which affects the handling of cases where the result of a comparison is unordered.  By default -mieee is implicitly enabled.  If -ffinite-math-only is enabled -mno-ieee is implicitly set, which results in faster floating-point greater-equal and less-equal comparisons.  The implicit settings can be overridden by specifying either -mieee or -mno-ieee.
-minline-ic_invalidate Inline code to invalidate instruction cache entries after setting up nested function trampolines.  This option has no effect if -musermode is in effect and the selected code generation option (e.g. -m4) does not allow the use of the "icbi" instruction.  If the selected code generation option does not allow the use of the "icbi" instruction, and -musermode is not in effect, the inlined code manipulates the instruction cache address array directly with an associative write. This not only requires privileged mode at run time, but it also fails if the cache line had been mapped via the TLB and has become unmapped.
-misize Dump instruction size and location in the assembly code.
-mpadstruct This option is deprecated.  It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI.
-matomic-model=model Sets the model of atomic operations and additional parameters as a comma separated list.  For details on the atomic built-in functions see __atomic Builtins.  The following models and parameters are supported:
none Disable compiler generated atomic sequences and emit library calls for atomic operations.  This is the default if the target is not "sh*-*-linux*".
soft-gusa Generate GNU/Linux compatible gUSA software atomic sequences for the atomic built-in functions.  The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for SH3* and SH4* single-core systems.  This option is enabled by default when the target is "sh*-*-linux*" and SH3* or SH4*.  When the target is SH4A, this option also partially utilizes the hardware atomic instructions "movli.l" and "movco.l" to create more efficient code, unless strict is specified.
soft-tcb Generate software atomic sequences that use a variable in the thread control block.  This is a variation of the gUSA sequences which can also be used on SH1* and SH2* targets.  The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for single-core systems.  When using this model, the gbr-offset= parameter has to be specified as well.
soft-imask Generate software atomic sequences that temporarily disable interrupts by setting "SR.IMASK = 1111".  This model works only when the program runs in privileged mode and is only suitable for single-core systems.  Additional support from the interrupt/exception handling code of the system is not required. This model is enabled by default when the target is "sh*-*-linux*" and SH1* or SH2*.
hard-llcs Generate hardware atomic sequences using the "movli.l" and "movco.l" instructions only.  This is only available on SH4A and is suitable for multi-core systems.  Since the hardware instructions support only 32 bit atomic variables access to 8 or 16 bit variables is emulated with 32 bit accesses.  Code compiled with this option is also compatible with other software atomic model interrupt/exception handling systems if executed on an SH4A system.  Additional support from the interrupt/exception handling code of the system is not required for this model.
gbr-offset= This parameter specifies the offset in bytes of the variable in the thread control block structure that should be used by the generated atomic sequences when the soft-tcb model has been selected.  For other models this parameter is ignored.  The specified value must be an integer multiple of four and in the range 0-1020.
strict This parameter prevents mixed usage of multiple atomic models, even if they are compatible, and makes the compiler generate atomic sequences of the specified model only.
-mtas Generate the "tas.b" opcode for "__atomic_test_and_set".  Notice that depending on the particular hardware and software configuration this can degrade overall performance due to the operand cache line flushes that are implied by the "tas.b" instruction.  On multi-core SH4A processors the "tas.b" instruction must be used with caution since it can result in data corruption for certain cache configurations.
-mprefergot When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table.
-musermode -mno-usermode Don't allow (allow) the compiler generating privileged mode code. Specifying -musermode also implies -mno-inline-ic_invalidate if the inlined code would not work in user mode.  -musermode is the default when the target is "sh*-*-linux*".  If the target is SH1* or SH2* -musermode has no effect, since there is no user mode.
-multcost=number Set the cost to assume for a multiply insn.
-mdiv=strategy Set the division strategy to be used for integer division operations. strategy can be one of:
call-div1 Calls a library function that uses the single-step division instruction "div1" to perform the operation.  Division by zero calculates an unspecified result and does not trap.  This is the default except for SH4, SH2A and SHcompact.
call-fp Calls a library function that performs the operation in double precision floating point.  Division by zero causes a floating- point exception.  This is the default for SHcompact with FPU. Specifying this for targets that do not have a double precision FPU defaults to "call-div1".
call-table Calls a library function that uses a lookup table for small divisors and the "div1" instruction with case distinction for larger divisors.  Division by zero calculates an unspecified result and does not trap.  This is the default for SH4. Specifying this for targets that do not have dynamic shift instructions defaults to "call-div1".
When a division strategy has not been specified the default strategy is selected based on the current target.  For SH2A the default strategy is to use the "divs" and "divu" instructions instead of library function calls.
-maccumulate-outgoing-args Reserve space once for outgoing arguments in the function prologue rather than around each call.  Generally beneficial for performance and size.  Also needed for unwinding to avoid changing the stack frame around conditional code.
-mdivsi3_libfunc=name Set the name of the library function used for 32-bit signed division to name.  This only affects the name used in the call division strategies, and the compiler still expects the same sets of input/output/clobbered registers as if this option were not present.
-mbranch-cost=num Assume num to be the cost for a branch instruction.  Higher numbers make the compiler try to generate more branch-free code if possible. If not specified the value is selected depending on the processor type that is being compiled for.
-mzdcbranch -mno-zdcbranch Assume (do not assume) that zero displacement conditional branch instructions "bt" and "bf" are fast.  If -mzdcbranch is specified, the compiler prefers zero displacement branch code sequences.  This is enabled by default when generating code for SH4 and SH4A.  It can be explicitly disabled by specifying -mno-zdcbranch.
-mcbranch-force-delay-slot Force the usage of delay slots for conditional branches, which stuffs the delay slot with a "nop" if a suitable instruction cannot be found.  By default this option is disabled.  It can be enabled to work around hardware bugs as found in the original SH7055.
-mfsca -mno-fsca Allow or disallow the compiler to emit the "fsca" instruction for sine and cosine approximations.  The option -mfsca must be used in combination with -funsafe-math-optimizations.  It is enabled by default when generating code for SH4A.  Using -mno-fsca disables sine and cosine approximations even if -funsafe-math-optimizations is in effect.
-mfsrra -mno-fsrra Allow or disallow the compiler to emit the "fsrra" instruction for reciprocal square root approximations.  The option -mfsrra must be used in combination with -funsafe-math-optimizations and -ffinite-math-only.  It is enabled by default when generating code for SH4A.  Using -mno-fsrra disables reciprocal square root approximations even if -funsafe-math-optimizations and -ffinite-math-only are in effect.
-mpretend-cmove Prefer zero-displacement conditional branches for conditional move instruction patterns.  This can result in faster code on the SH4 processor.
-mfdpic Generate code using the FDPIC ABI.
Solaris 2 Options
These -m options are supported on Solaris 2:
-mclear-hwcap -mclear-hwcap tells the compiler to remove the hardware capabilities generated by the Solaris assembler.  This is only necessary when object files use ISA extensions not supported by the current machine, but check at runtime whether or not to use them.
-mimpure-text -mimpure-text, used in addition to -shared, tells the compiler to not pass -z text to the linker when linking a shared object.  Using this option, you can link position-dependent code into a shared object.
-mimpure-text suppresses the "relocations remain against allocatable but non-writable sections" linker error message.  However, the necessary relocations trigger copy-on-write, and the shared object is not actually shared across processes.  Instead of using -mimpure-text, you should compile all source code with -fpic or -fPIC.
These switches are supported in addition to the above on Solaris 2:
-pthreads This is a synonym for -pthread.
SPARC Options
These -m options are supported on the SPARC:
-mno-app-regs -mapp-regs Specify -mapp-regs to generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications.  Like the global register 1, each global register 2 through 4 is then treated as an allocable register that is clobbered by function calls. This is the default.
To be fully SVR4 ABI-compliant at the cost of some performance loss, specify -mno-app-regs.  You should compile libraries and system software with this option.
-mflat -mno-flat With -mflat, the compiler does not generate save/restore instructions and uses a "flat" or single register window model.  This model is compatible with the regular register window model.  The local registers and the input registers (0--5) are still treated as "call- saved" registers and are saved on the stack as needed.
With -mno-flat (the default), the compiler generates save/restore instructions (except for leaf functions).  This is the normal operating mode.
-mfpu -mhard-float Generate output containing floating-point instructions.  This is the default.
-mno-fpu -msoft-float Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all SPARC targets.  Normally the facilities of the machine's usual C compiler are used, but this cannot be done directly in cross-compilation.  You must make your own arrangements to provide suitable library functions for cross-compilation.  The embedded targets sparc-*-aout and sparclite-*-* do provide software floating-point support.
-mhard-quad-float Generate output containing quad-word (long double) floating-point instructions.
-msoft-quad-float Generate output containing library calls for quad-word (long double) floating-point instructions.  The functions called are those specified in the SPARC ABI.  This is the default.
As of this writing, there are no SPARC implementations that have hardware support for the quad-word floating-point instructions.  They all invoke a trap handler for one of these instructions, and then the trap handler emulates the effect of the instruction.  Because of the trap handler overhead, this is much slower than calling the ABI library routines.  Thus the -msoft-quad-float option is the default.
-mno-unaligned-doubles -munaligned-doubles Assume that doubles have 8-byte alignment.  This is the default.
With -munaligned-doubles, GCC assumes that doubles have 8-byte alignment only if they are contained in another type, or if they have an absolute address.  Otherwise, it assumes they have 4-byte alignment.  Specifying this option avoids some rare compatibility problems with code generated by other compilers.  It is not the default because it results in a performance loss, especially for floating-point code.
-muser-mode -mno-user-mode Do not generate code that can only run in supervisor mode.  This is relevant only for the "casa" instruction emitted for the LEON3 processor.  This is the default.
-mfaster-structs -mno-faster-structs With -mfaster-structs, the compiler assumes that structures should have 8-byte alignment.  This enables the use of pairs of "ldd" and "std" instructions for copies in structure assignment, in place of twice as many "ld" and "st" pairs.  However, the use of this changed alignment directly violates the SPARC ABI.  Thus, it's intended only for use on targets where the developer acknowledges that their resulting code is not directly in line with the rules of the ABI.
-mstd-struct-return -mno-std-struct-return With -mstd-struct-return, the compiler generates checking code in functions returning structures or unions to detect size mismatches between the two sides of function calls, as per the 32-bit ABI.
The default is -mno-std-struct-return.  This option has no effect in 64-bit mode.
-mlra -mno-lra Enable Local Register Allocation.  This is the default for SPARC since GCC 7 so -mno-lra needs to be passed to get old Reload.
-mcpu=cpu_type Set the instruction set, register set, and instruction scheduling parameters for machine type cpu_type.  Supported values for cpu_type are v7, cypress, v8, supersparc, hypersparc, leon, leon3, leon3v7, sparclite, f930, f934, sparclite86x, sparclet, tsc701, v9, ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, niagara7 and m8.
Native Solaris and GNU/Linux toolchains also support the value native, which selects the best architecture option for the host processor.  -mcpu=native has no effect if GCC does not recognize the processor.
Default instruction scheduling parameters are used for values that select an architecture and not an implementation.  These are v7, v8, sparclite, sparclet, v9.
Here is a list of each supported architecture and their supported implementations.
v7  cypress, leon3v7
v8  supersparc, hypersparc, leon, leon3
sparclite f930, f934, sparclite86x
sparclet tsc701
v9  ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, niagara7, m8
By default (unless configured otherwise), GCC generates code for the V7 variant of the SPARC architecture.  With -mcpu=cypress, the compiler additionally optimizes it for the Cypress CY7C602 chip, as used in the SPARCStation/SPARCServer 3xx series.  This is also appropriate for the older SPARCStation 1, 2, IPX etc.
With -mcpu=v8, GCC generates code for the V8 variant of the SPARC architecture.  The only difference from V7 code is that the compiler emits the integer multiply and integer divide instructions which exist in SPARC-V8 but not in SPARC-V7.  With -mcpu=supersparc, the compiler additionally optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000 series.
With -mcpu=sparclite, GCC generates code for the SPARClite variant of the SPARC architecture.  This adds the integer multiply, integer divide step and scan ("ffs") instructions which exist in SPARClite but not in SPARC-V7.  With -mcpu=f930, the compiler additionally optimizes it for the Fujitsu MB86930 chip, which is the original SPARClite, with no FPU.  With -mcpu=f934, the compiler additionally optimizes it for the Fujitsu MB86934 chip, which is the more recent SPARClite with FPU.
With -mcpu=sparclet, GCC generates code for the SPARClet variant of the SPARC architecture.  This adds the integer multiply, multiply/accumulate, integer divide step and scan ("ffs") instructions which exist in SPARClet but not in SPARC-V7.  With -mcpu=tsc701, the compiler additionally optimizes it for the TEMIC SPARClet chip.
With -mcpu=v9, GCC generates code for the V9 variant of the SPARC architecture.  This adds 64-bit integer and floating-point move instructions, 3 additional floating-point condition code registers and conditional move instructions.  With -mcpu=ultrasparc, the compiler additionally optimizes it for the Sun UltraSPARC I/II/IIi chips.  With -mcpu=ultrasparc3, the compiler additionally optimizes it for the Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips.  With -mcpu=niagara, the compiler additionally optimizes it for Sun UltraSPARC T1 chips.  With -mcpu=niagara2, the compiler additionally optimizes it for Sun UltraSPARC T2 chips. With -mcpu=niagara3, the compiler additionally optimizes it for Sun UltraSPARC T3 chips.  With -mcpu=niagara4, the compiler additionally optimizes it for Sun UltraSPARC T4 chips.  With -mcpu=niagara7, the compiler additionally optimizes it for Oracle SPARC M7 chips.  With -mcpu=m8, the compiler additionally optimizes it for Oracle M8 chips.
-mtune=cpu_type Set the instruction scheduling parameters for machine type cpu_type, but do not set the instruction set or register set that the option -mcpu=cpu_type does.
The same values for -mcpu=cpu_type can be used for -mtune=cpu_type, but the only useful values are those that select a particular CPU implementation.  Those are cypress, supersparc, hypersparc, leon, leon3, leon3v7, f930, f934, sparclite86x, tsc701, ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, niagara7 and m8. With native Solaris and GNU/Linux toolchains, native can also be used.
-mv8plus -mno-v8plus With -mv8plus, GCC generates code for the SPARC-V8+ ABI.  The difference from the V8 ABI is that the global and out registers are considered 64 bits wide.  This is enabled by default on Solaris in 32-bit mode for all SPARC-V9 processors.
-mvis -mno-vis With -mvis, GCC generates code that takes advantage of the UltraSPARC Visual Instruction Set extensions.  The default is -mno-vis.
-mvis2 -mno-vis2 With -mvis2, GCC generates code that takes advantage of version 2.0 of the UltraSPARC Visual Instruction Set extensions.  The default is -mvis2 when targeting a cpu that supports such instructions, such as UltraSPARC-III and later.  Setting -mvis2 also sets -mvis.
-mvis3 -mno-vis3 With -mvis3, GCC generates code that takes advantage of version 3.0 of the UltraSPARC Visual Instruction Set extensions.  The default is -mvis3 when targeting a cpu that supports such instructions, such as niagara-3 and later.  Setting -mvis3 also sets -mvis2 and -mvis.
-mvis4 -mno-vis4 With -mvis4, GCC generates code that takes advantage of version 4.0 of the UltraSPARC Visual Instruction Set extensions.  The default is -mvis4 when targeting a cpu that supports such instructions, such as niagara-7 and later.  Setting -mvis4 also sets -mvis3, -mvis2 and -mvis.
-mvis4b -mno-vis4b With -mvis4b, GCC generates code that takes advantage of version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus the additional VIS instructions introduced in the Oracle SPARC Architecture 2017.  The default is -mvis4b when targeting a cpu that supports such instructions, such as m8 and later.  Setting -mvis4b also sets -mvis4, -mvis3, -mvis2 and -mvis.
-mcbcond -mno-cbcond With -mcbcond, GCC generates code that takes advantage of the UltraSPARC Compare-and-Branch-on-Condition instructions.  The default is -mcbcond when targeting a CPU that supports such instructions, such as Niagara-4 and later.
-mfmaf -mno-fmaf With -mfmaf, GCC generates code that takes advantage of the UltraSPARC Fused Multiply-Add Floating-point instructions.  The default is -mfmaf when targeting a CPU that supports such instructions, such as Niagara-3 and later.
-mfsmuld -mno-fsmuld With -mfsmuld, GCC generates code that takes advantage of the Floating-point Multiply Single to Double (FsMULd) instruction.  The default is -mfsmuld when targeting a CPU supporting the architecture versions V8 or V9 with FPU except -mcpu=leon.
-mpopc -mno-popc With -mpopc, GCC generates code that takes advantage of the UltraSPARC Population Count instruction.  The default is -mpopc when targeting a CPU that supports such an instruction, such as Niagara-2 and later.
-msubxc -mno-subxc With -msubxc, GCC generates code that takes advantage of the UltraSPARC Subtract-Extended-with-Carry instruction.  The default is -msubxc when targeting a CPU that supports such an instruction, such as Niagara-7 and later.
-mfix-at697f Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor).
-mfix-ut699 Enable the documented workarounds for the floating-point errata and the data cache nullify errata of the UT699 processor.
-mfix-ut700 Enable the documented workaround for the back-to-back store errata of the UT699E/UT700 processor.
-mfix-gr712rc Enable the documented workaround for the back-to-back store errata of the GR712RC processor.
These -m options are supported in addition to the above on SPARC-V9 processors in 64-bit environments:
-m32 -m64 Generate code for a 32-bit or 64-bit environment.  The 32-bit environment sets int, long and pointer to 32 bits.  The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.
-mcmodel=which Set the code model to one of
medlow The Medium/Low code model: 64-bit addresses, programs must be linked in the low 32 bits of memory.  Programs can be statically or dynamically linked.
medmid The Medium/Middle code model: 64-bit addresses, programs must be linked in the low 44 bits of memory, the text and data segments must be less than 2GB in size and the data segment must be located within 2GB of the text segment.
medany The Medium/Anywhere code model: 64-bit addresses, programs may be linked anywhere in memory, the text and data segments must be less than 2GB in size and the data segment must be located within 2GB of the text segment.
embmedany The Medium/Anywhere code model for embedded systems: 64-bit addresses, the text and data segments must be less than 2GB in size, both starting anywhere in memory (determined at link time). The global register %g4 points to the base of the data segment. Programs are statically linked and PIC is not supported.
-mmemory-model=mem-model Set the memory model in force on the processor to one of
default The default memory model for the processor and operating system.
rmo Relaxed Memory Order
pso Partial Store Order
tso Total Store Order
sc  Sequential Consistency
These memory models are formally defined in Appendix D of the SPARC-V9 architecture manual, as set in the processor's "PSTATE.MM" field.
-mstack-bias -mno-stack-bias With -mstack-bias, GCC assumes that the stack pointer, and frame pointer if present, are offset by -2047 which must be added back when making stack frame references.  This is the default in 64-bit mode. Otherwise, assume no such offset is present.
Options for System V
These additional options are available on System V Release 4 for compatibility with other compilers on those systems:
-G  Create a shared object.  It is recommended that -symbolic or -shared be used instead.
-Qy Identify the versions of each tool used by the compiler, in a ".ident" assembler directive in the output.
-Qn Refrain from adding ".ident" directives to the output file (this is the default).
-YP,dirs Search the directories dirs, and no others, for libraries specified with -l.
-Ym,dir Look in the directory dir to find the M4 preprocessor.  The assembler uses this option.
TILE-Gx Options
These -m options are supported on the TILE-Gx:
-mcmodel=small Generate code for the small model.  The distance for direct calls is limited to 500M in either direction.  PC-relative addresses are 32 bits.  Absolute addresses support the full address range.
-mcmodel=large Generate code for the large model.  There is no limitation on call distance, pc-relative addresses, or absolute addresses.
-mcpu=name Selects the type of CPU to be targeted.  Currently the only supported type is tilegx.
-m32 -m64 Generate code for a 32-bit or 64-bit environment.  The 32-bit environment sets int, long, and pointer to 32 bits.  The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.
-mbig-endian -mlittle-endian Generate code in big/little endian mode, respectively.
TILEPro Options
These -m options are supported on the TILEPro:
-mcpu=name Selects the type of CPU to be targeted.  Currently the only supported type is tilepro.
-m32 Generate code for a 32-bit environment, which sets int, long, and pointer to 32 bits.  This is the only supported behavior so the flag is essentially ignored.
V850 Options
These -m options are defined for V850 implementations:
-mlong-calls -mno-long-calls Treat all calls as being far away (near).  If calls are assumed to be far away, the compiler always loads the function's address into a register, and calls indirect through the pointer.
-mno-ep -mep Do not optimize (do optimize) basic blocks that use the same index pointer 4 or more times to copy pointer into the "ep" register, and use the shorter "sld" and "sst" instructions.  The -mep option is on by default if you optimize.
-mno-prolog-function -mprolog-function Do not use (do use) external functions to save and restore registers at the prologue and epilogue of a function.  The external functions are slower, but use less code space if more than one function saves the same number of registers.  The -mprolog-function option is on by default if you optimize.
-mspace Try to make the code as small as possible.  At present, this just turns on the -mep and -mprolog-function options.
-mtda=n Put static or global variables whose size is n bytes or less into the tiny data area that register "ep" points to.  The tiny data area can hold up to 256 bytes in total (128 bytes for byte references).
-msda=n Put static or global variables whose size is n bytes or less into the small data area that register "gp" points to.  The small data area can hold up to 64 kilobytes.
-mzda=n Put static or global variables whose size is n bytes or less into the first 32 kilobytes of memory.
-mv850 Specify that the target processor is the V850.
-mv850e3v5 Specify that the target processor is the V850E3V5.  The preprocessor constant "__v850e3v5__" is defined if this option is used.
-mv850e2v4 Specify that the target processor is the V850E3V5.  This is an alias for the -mv850e3v5 option.
-mv850e2v3 Specify that the target processor is the V850E2V3.  The preprocessor constant "__v850e2v3__" is defined if this option is used.
-mv850e2 Specify that the target processor is the V850E2.  The preprocessor constant "__v850e2__" is defined if this option is used.
-mv850e1 Specify that the target processor is the V850E1.  The preprocessor constants "__v850e1__" and "__v850e__" are defined if this option is used.
-mv850es Specify that the target processor is the V850ES.  This is an alias for the -mv850e1 option.
-mv850e Specify that the target processor is the V850E.  The preprocessor constant "__v850e__" is defined if this option is used.
If neither -mv850 nor -mv850e nor -mv850e1 nor -mv850e2 nor -mv850e2v3 nor -mv850e3v5 are defined then a default target processor is chosen and the relevant __v850*__ preprocessor constant is defined.
The preprocessor constants "__v850" and "__v851__" are always defined, regardless of which processor variant is the target.
-mdisable-callt -mno-disable-callt This option suppresses generation of the "CALLT" instruction for the v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 architecture.
This option is enabled by default when the RH850 ABI is in use (see -mrh850-abi), and disabled by default when the GCC ABI is in use.  If "CALLT" instructions are being generated then the C preprocessor symbol "__V850_CALLT__" is defined.
-mrelax -mno-relax Pass on (or do not pass on) the -mrelax command-line option to the assembler.
-mlong-jumps -mno-long-jumps Disable (or re-enable) the generation of PC-relative jump instructions.
-msoft-float -mhard-float Disable (or re-enable) the generation of hardware floating point instructions.  This option is only significant when the target architecture is V850E2V3 or higher.  If hardware floating point instructions are being generated then the C preprocessor symbol "__FPU_OK__" is defined, otherwise the symbol "__NO_FPU__" is defined.
-mloop Enables the use of the e3v5 LOOP instruction.  The use of this instruction is not enabled by default when the e3v5 architecture is selected because its use is still experimental.
-mrh850-abi -mghs Enables support for the RH850 version of the V850 ABI.  This is the default.  With this version of the ABI the following rules apply:
*   Integer sized structures and unions are returned via a memory pointer rather than a register.
*   Large structures and unions (more than 8 bytes in size) are passed by value.
*   Functions are aligned to 16-bit boundaries.
*   The -m8byte-align command-line option is supported.
*   The -mdisable-callt command-line option is enabled by default. The -mno-disable-callt command-line option is not supported.
When this version of the ABI is enabled the C preprocessor symbol "__V850_RH850_ABI__" is defined.
-mgcc-abi Enables support for the old GCC version of the V850 ABI.  With this version of the ABI the following rules apply:
*   Integer sized structures and unions are returned in register "r10".
*   Large structures and unions (more than 8 bytes in size) are passed by reference.
*   Functions are aligned to 32-bit boundaries, unless optimizing for size.
*   The -m8byte-align command-line option is not supported.
*   The -mdisable-callt command-line option is supported but not enabled by default.
When this version of the ABI is enabled the C preprocessor symbol "__V850_GCC_ABI__" is defined.
-m8byte-align -mno-8byte-align Enables support for "double" and "long long" types to be aligned on 8-byte boundaries.  The default is to restrict the alignment of all objects to at most 4-bytes.  When -m8byte-align is in effect the C preprocessor symbol "__V850_8BYTE_ALIGN__" is defined.
-mbig-switch Generate code suitable for big switch tables.  Use this option only if the assembler/linker complain about out of range branches within a switch table.
-mapp-regs This option causes r2 and r5 to be used in the code generated by the compiler.  This setting is the default.
-mno-app-regs This option causes r2 and r5 to be treated as fixed registers.
VAX Options
These -m options are defined for the VAX:
-munix Do not output certain jump instructions ("aobleq" and so on) that the Unix assembler for the VAX cannot handle across long ranges.
-mgnu Do output those jump instructions, on the assumption that the GNU assembler is being used.
-mg Output code for G-format floating-point numbers instead of D-format.
Visium Options
-mdebug A program which performs file I/O and is destined to run on an MCM target should be linked with this option.  It causes the libraries libc.a and libdebug.a to be linked.  The program should be run on the target under the control of the GDB remote debugging stub.