neulab/tldr huggingface dataset:
*   The name of the function.
*   A number of bytes.
*   One or more qualifiers: "static", "dynamic", "bounded".
The qualifier "static" means that the function manipulates the stack statically: a fixed number of bytes are allocated for the frame on function entry and released on function exit; no stack adjustments are otherwise made in the function.  The second field is this fixed number of bytes.
The qualifier "dynamic" means that the function manipulates the stack dynamically: in addition to the static allocation described above, stack adjustments are made in the body of the function, for example to push/pop arguments around function calls.  If the qualifier "bounded" is also present, the amount of these adjustments is bounded at compile time and the second field is an upper bound of the total amount of stack used by the function.  If it is not present, the amount of these adjustments is not bounded at compile time and the second field only represents the bounded part.
-fstats Emit statistics about front-end processing at the end of the compilation.  This option is supported only by the C++ front end, and the information is generally only useful to the G++ development team.
-fdbg-cnt-list Print the name and the counter upper bound for all debug counters.
-fdbg-cnt=counter-value-list Set the internal debug counter lower and upper bound.  counter-value- list is a comma-separated list of name:lower_bound1-upper_bound1 [:lower_bound2-upper_bound2...] tuples which sets the name of the counter and list of closed intervals.  The lower_bound is optional and is zero initialized if not set.  For example, with -fdbg-cnt=dce:2-4:10-11,tail_call:10, "dbg_cnt(dce)" returns true only for second, third, fourth, tenth and eleventh invocation.  For "dbg_cnt(tail_call)" true is returned for first 10 invocations.
-print-file-name=library Print the full absolute name of the library file library that would be used when linking---and don't do anything else.  With this option, GCC does not compile or link anything; it just prints the file name.
-print-multi-directory Print the directory name corresponding to the multilib selected by any other switches present in the command line.  This directory is supposed to exist in GCC_EXEC_PREFIX.
-print-multi-lib Print the mapping from multilib directory names to compiler switches that enable them.  The directory name is separated from the switches by ;, and each switch starts with an @ instead of the -, without spaces between multiple switches.  This is supposed to ease shell processing.
-print-multi-os-directory Print the path to OS libraries for the selected multilib, relative to some lib subdirectory.  If OS libraries are present in the lib subdirectory and no multilibs are used, this is usually just ., if OS libraries are present in libsuffix sibling directories this prints e.g. ../lib64, ../lib or ../lib32, or if OS libraries are present in lib/subdir subdirectories it prints e.g. amd64, sparcv9 or ev6.
-print-multiarch Print the path to OS libraries for the selected multiarch, relative to some lib subdirectory.
-print-prog-name=program Like -print-file-name, but searches for a program such as cpp.
-print-libgcc-file-name Same as -print-file-name=libgcc.a.
This is useful when you use -nostdlib or -nodefaultlibs but you do want to link with libgcc.a.  You can do:
gcc -nostdlib <files>... `gcc -print-libgcc-file-name`
-print-search-dirs Print the name of the configured installation directory and a list of program and library directories gcc searches---and don't do anything else.
This is useful when gcc prints the error message installation problem, cannot exec cpp0: No such file or directory.  To resolve this you either need to put cpp0 and the other compiler components where gcc expects to find them, or you can set the environment variable GCC_EXEC_PREFIX to the directory where you installed them. Don't forget the trailing /.
-print-sysroot Print the target sysroot directory that is used during compilation. This is the target sysroot specified either at configure time or using the --sysroot option, possibly with an extra suffix that depends on compilation options.  If no target sysroot is specified, the option prints nothing.
-print-sysroot-headers-suffix Print the suffix added to the target sysroot when searching for headers, or give an error if the compiler is not configured with such a suffix---and don't do anything else.
-dumpmachine Print the compiler's target machine (for example, i686-pc-linux-gnu)---and don't do anything else.
-dumpversion Print the compiler version (for example, 3.0, 6.3.0 or 7)---and don't do anything else.  This is the compiler version used in filesystem paths and specs. Depending on how the compiler has been configured it can be just a single number (major version), two numbers separated by a dot (major and minor version) or three numbers separated by dots (major, minor and patchlevel version).
-dumpfullversion Print the full compiler version---and don't do anything else. The output is always three numbers separated by dots, major, minor and patchlevel version.
-dumpspecs Print the compiler's built-in specs---and don't do anything else. (This is used when GCC itself is being built.)
Machine-Dependent Options Each target machine supported by GCC can have its own options---for example, to allow you to compile for a particular processor variant or ABI, or to control optimizations specific to that machine.  By convention, the names of machine-specific options start with -m.
Some configurations of the compiler also support additional target- specific options, usually for compatibility with other compilers on the same platform.
AArch64 Options
These options are defined for AArch64 implementations:
-mabi=name Generate code for the specified data model.  Permissible values are ilp32 for SysV-like data model where int, long int and pointers are 32 bits, and lp64 for SysV-like data model where int is 32 bits, but long int and pointers are 64 bits.
The default depends on the specific target configuration.  Note that the LP64 and ILP32 ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.
-mbig-endian Generate big-endian code.  This is the default when GCC is configured for an aarch64_be-*-* target.
-mgeneral-regs-only Generate code which uses only the general-purpose registers.  This will prevent the compiler from using floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler.
-mlittle-endian Generate little-endian code.  This is the default when GCC is configured for an aarch64-*-* but not an aarch64_be-*-* target.
-mcmodel=tiny Generate code for the tiny code model.  The program and its statically defined symbols must be within 1MB of each other. Programs can be statically or dynamically linked.
-mcmodel=small Generate code for the small code model.  The program and its statically defined symbols must be within 4GB of each other. Programs can be statically or dynamically linked.  This is the default code model.
-mcmodel=large Generate code for the large code model.  This makes no assumptions about addresses and sizes of sections.  Programs can be statically linked only.  The -mcmodel=large option is incompatible with -mabi=ilp32, -fpic and -fPIC.
-mstrict-align -mno-strict-align Avoid or allow generating memory accesses that may not be aligned on a natural object boundary as described in the architecture specification.
-momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer Omit or keep the frame pointer in leaf functions.  The former behavior is the default.
-mstack-protector-guard=guard -mstack-protector-guard-reg=reg -mstack-protector-guard-offset=offset Generate stack protection code using canary at guard.  Supported locations are global for a global canary or sysreg for a canary in an appropriate system register.
With the latter choice the options -mstack-protector-guard-reg=reg and -mstack-protector-guard-offset=offset furthermore specify which system register to use as base register for reading the canary, and from what offset from that base register. There is no default register or offset as this is entirely for use within the Linux kernel.
-mtls-dialect=desc Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables.  This is the default.
-mtls-dialect=traditional Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables.
-mtls-size=size Specify bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.  This option requires binutils 2.26 or newer.
-mfix-cortex-a53-835769 -mno-fix-cortex-a53-835769 Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.  This involves inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions.
-mfix-cortex-a53-843419 -mno-fix-cortex-a53-843419 Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.  This erratum workaround is made at link time and this will only pass the corresponding flag to the linker.
-mlow-precision-recip-sqrt -mno-low-precision-recip-sqrt Enable or disable the reciprocal square root approximation.  This option only has an effect if -ffast-math or -funsafe-math-optimizations is used as well.  Enabling this reduces precision of reciprocal square root results to about 16 bits for single precision and to 32 bits for double precision.
-mlow-precision-sqrt -mno-low-precision-sqrt Enable or disable the square root approximation.  This option only has an effect if -ffast-math or -funsafe-math-optimizations is used as well.  Enabling this reduces precision of square root results to about 16 bits for single precision and to 32 bits for double precision.  If enabled, it implies -mlow-precision-recip-sqrt.
-mlow-precision-div -mno-low-precision-div Enable or disable the division approximation.  This option only has an effect if -ffast-math or -funsafe-math-optimizations is used as well.  Enabling this reduces precision of division results to about 16 bits for single precision and to 32 bits for double precision.
-mtrack-speculation -mno-track-speculation Enable or disable generation of additional code to track speculative execution through conditional branches.  The tracking state can then be used by the compiler when expanding calls to "__builtin_speculation_safe_copy" to permit a more efficient code sequence to be generated.
-moutline-atomics -mno-outline-atomics Enable or disable calls to out-of-line helpers to implement atomic operations.  These helpers will, at runtime, determine if the LSE instructions from ARMv8.1-A can be used; if not, they will use the load/store-exclusive instructions that are present in the base ARMv8.0 ISA.
This option is only applicable when compiling for the base ARMv8.0 instruction set.  If using a later revision, e.g. -march=armv8.1-a or -march=armv8-a+lse, the ARMv8.1-Atomics instructions will be used directly.  The same applies when using -mcpu= when the selected cpu supports the lse feature.  This option is on by default.
-march=name Specify the name of the target architecture and, optionally, one or more feature modifiers.  This option has the form -march=arch{+[no]feature}*.
The table below summarizes the permissible values for arch and the features that they enable by default:
arch value : Architecture : Includes by default armv8-a : Armv8-A : +fp, +simd armv8.1-a : Armv8.1-A : armv8-a, +crc, +lse, +rdma armv8.2-a : Armv8.2-A : armv8.1-a armv8.3-a : Armv8.3-A : armv8.2-a, +pauth armv8.4-a : Armv8.4-A : armv8.3-a, +flagm, +fp16fml, +dotprod armv8.5-a : Armv8.5-A : armv8.4-a, +sb, +ssbs, +predres armv8.6-a : Armv8.6-A : armv8.5-a, +bf16, +i8mm armv8-r : Armv8-R : armv8-r
The value native is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture of the host system.  This option has no effect if the compiler is unable to recognize the architecture of the host system,
The permissible values for feature are listed in the sub-section on aarch64-feature-modifiers,,-march and -mcpu Feature Modifiers.  Where conflicting feature modifiers are specified, the right-most feature is used.
GCC uses name to determine what kind of instructions it can emit when generating assembly code.  If -march is specified without either of -mtune or -mcpu also being specified, the code is tuned to perform well across a range of target processors implementing the target architecture.
-mtune=name Specify the name of the target processor for which GCC should tune the performance of the code.  Permissible values for this option are: generic, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a65, cortex-a65ae, cortex-a34, cortex-a78, cortex-a78ae, cortex-a78c, ares, exynos-m1, emag, falkor, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-v1, qdf24xx, saphira, phecda, xgene1, vulcan, octeontx, octeontx81,  octeontx83, octeontx2, octeontx2t98, octeontx2t96 octeontx2t93, octeontx2f95, octeontx2f95n, octeontx2f95mm, a64fx, thunderx, thunderxt88, thunderxt88p1, thunderxt81, tsv110, thunderxt83, thunderx2t99, thunderx3t110, zeus, cortex-a57.cortex-a53, cortex-a72.cortex-a53, cortex-a73.cortex-a35, cortex-a73.cortex-a53, cortex-a75.cortex-a55, cortex-a76.cortex-a55, cortex-r82, cortex-x1, native.
The values cortex-a57.cortex-a53, cortex-a72.cortex-a53, cortex-a73.cortex-a35, cortex-a73.cortex-a53, cortex-a75.cortex-a55, cortex-a76.cortex-a55 specify that GCC should tune for a big.LITTLE system.
Additionally on native AArch64 GNU/Linux systems the value native tunes performance to the host system.  This option has no effect if the compiler is unable to recognize the processor of the host system.
Where none of -mtune=, -mcpu= or -march= are specified, the code is tuned to perform well across a range of target processors.
This option cannot be suffixed by feature modifiers.
-mcpu=name Specify the name of the target processor, optionally suffixed by one or more feature modifiers.  This option has the form -mcpu=cpu{+[no]feature}*, where the permissible values for cpu are the same as those available for -mtune.  The permissible values for feature are documented in the sub-section on aarch64-feature-modifiers,,-march and -mcpu Feature Modifiers.  Where conflicting feature modifiers are specified, the right-most feature is used.
GCC uses name to determine what kind of instructions it can emit when generating assembly code (as if by -march) and to determine the target processor for which to tune for performance (as if by -mtune). Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option.
-moverride=string Override tuning decisions made by the back-end in response to a -mtune= switch.  The syntax, semantics, and accepted values for string in this option are not guaranteed to be consistent across releases.
This option is only intended to be useful when developing GCC.
-mverbose-cost-dump Enable verbose cost model dumping in the debug dump files.  This option is provided for use in debugging the compiler.
-mpc-relative-literal-loads -mno-pc-relative-literal-loads Enable or disable PC-relative literal loads.  With this option literal pools are accessed using a single instruction and emitted after each function.  This limits the maximum size of functions to 1MB.  This is enabled by default for -mcmodel=tiny.
-msign-return-address=scope Select the function scope on which return address signing will be applied.  Permissible values are none, which disables return address signing, non-leaf, which enables pointer signing for functions which are not leaf functions, and all, which enables pointer signing for all functions.  The default value is none. This option has been deprecated by -mbranch-protection.
-mbranch-protection=none|standard|pac-ret[+leaf+b-key]|bti Select the branch protection features to use.  none is the default and turns off all types of branch protection.  standard turns on all types of branch protection features.  If a feature has additional tuning options, then standard sets it to its standard level. pac-ret[+leaf] turns on return address signing to its standard level: signing functions that save the return address to memory (non-leaf functions will practically always do this) using the a-key.  The optional argument leaf can be used to extend the signing to include leaf functions.  The optional argument b-key can be used to sign the functions with the B-key instead of the A-key.  bti turns on branch target identification mechanism.
-mharden-sls=opts Enable compiler hardening against straight line speculation (SLS). opts is a comma-separated list of the following options:
retbr blr
In addition, -mharden-sls=all enables all SLS hardening while -mharden-sls=none disables all SLS hardening.
-msve-vector-bits=bits Specify the number of bits in an SVE vector register.  This option only has an effect when SVE is enabled.
GCC supports two forms of SVE code generation: "vector-length agnostic" output that works with any size of vector register and "vector-length specific" output that allows GCC to make assumptions about the vector length when it is useful for optimization reasons. The possible values of bits are: scalable, 128, 256, 512, 1024 and 2048.  Specifying scalable selects vector-length agnostic output.  At present -msve-vector-bits=128 also generates vector-length agnostic output for big-endian targets.  All other values generate vector- length specific code.  The behavior of these values may change in future releases and no value except scalable should be relied on for producing code that is portable across different hardware SVE vector lengths.
The default is -msve-vector-bits=scalable, which produces vector- length agnostic code.
-march and -mcpu Feature Modifiers
Feature modifiers used with -march and -mcpu can be any of the following and their inverses nofeature:
crc Enable CRC extension.  This is on by default for -march=armv8.1-a.
crypto Enable Crypto extension.  This also enables Advanced SIMD and floating-point instructions.
fp  Enable floating-point instructions.  This is on by default for all possible values for options -march and -mcpu.
simd Enable Advanced SIMD instructions.  This also enables floating-point instructions.  This is on by default for all possible values for options -march and -mcpu.
sve Enable Scalable Vector Extension instructions.  This also enables Advanced SIMD and floating-point instructions.
lse Enable Large System Extension instructions.  This is on by default for -march=armv8.1-a.
rdma Enable Round Double Multiply Accumulate instructions.  This is on by default for -march=armv8.1-a.
fp16 Enable FP16 extension.  This also enables floating-point instructions.
fp16fml Enable FP16 fmla extension.  This also enables FP16 extensions and floating-point instructions. This option is enabled by default for -march=armv8.4-a. Use of this option with architectures prior to Armv8.2-A is not supported.
rcpc Enable the RcPc extension.  This does not change code generation from GCC, but is passed on to the assembler, enabling inline asm statements to use instructions from the RcPc extension.
dotprod Enable the Dot Product extension.  This also enables Advanced SIMD instructions.
aes Enable the Armv8-a aes and pmull crypto extension.  This also enables Advanced SIMD instructions.
sha2 Enable the Armv8-a sha2 crypto extension.  This also enables Advanced SIMD instructions.
sha3 Enable the sha512 and sha3 crypto extension.  This also enables Advanced SIMD instructions. Use of this option with architectures prior to Armv8.2-A is not supported.
sm4 Enable the sm3 and sm4 crypto extension.  This also enables Advanced SIMD instructions.  Use of this option with architectures prior to Armv8.2-A is not supported.
profile Enable the Statistical Profiling extension.  This option is only to enable the extension at the assembler level and does not affect code generation.
rng Enable the Armv8.5-a Random Number instructions.  This option is only to enable the extension at the assembler level and does not affect code generation.
memtag Enable the Armv8.5-a Memory Tagging Extensions.  Use of this option with architectures prior to Armv8.5-A is not supported.
sb  Enable the Armv8-a Speculation Barrier instruction.  This option is only to enable the extension at the assembler level and does not affect code generation.  This option is enabled by default for -march=armv8.5-a.
ssbs Enable the Armv8-a Speculative Store Bypass Safe instruction.  This option is only to enable the extension at the assembler level and does not affect code generation.  This option is enabled by default for -march=armv8.5-a.
predres Enable the Armv8-a Execution and Data Prediction Restriction instructions.  This option is only to enable the extension at the assembler level and does not affect code generation.  This option is enabled by default for -march=armv8.5-a.
sve2 Enable the Armv8-a Scalable Vector Extension 2.  This also enables SVE instructions.
sve2-bitperm Enable SVE2 bitperm instructions.  This also enables SVE2 instructions.
sve2-sm4 Enable SVE2 sm4 instructions.  This also enables SVE2 instructions.
sve2-aes Enable SVE2 aes instructions.  This also enables SVE2 instructions.
sve2-sha3 Enable SVE2 sha3 instructions.  This also enables SVE2 instructions.
tme Enable the Transactional Memory Extension.
i8mm Enable 8-bit Integer Matrix Multiply instructions.  This also enables Advanced SIMD and floating-point instructions.  This option is enabled by default for -march=armv8.6-a.  Use of this option with architectures prior to Armv8.2-A is not supported.
f32mm Enable 32-bit Floating point Matrix Multiply instructions.  This also enables SVE instructions.  Use of this option with architectures prior to Armv8.2-A is not supported.
f64mm Enable 64-bit Floating point Matrix Multiply instructions.  This also enables SVE instructions.  Use of this option with architectures prior to Armv8.2-A is not supported.
bf16 Enable brain half-precision floating-point instructions.  This also enables Advanced SIMD and floating-point instructions.  This option is enabled by default for -march=armv8.6-a.  Use of this option with architectures prior to Armv8.2-A is not supported.
flagm Enable the Flag Manipulation instructions Extension.
pauth Enable the Pointer Authentication Extension.
Feature crypto implies aes, sha2, and simd, which implies fp. Conversely, nofp implies nosimd, which implies nocrypto, noaes and nosha2.
Adapteva Epiphany Options
These -m options are defined for Adapteva Epiphany:
-mhalf-reg-file Don't allocate any register in the range "r32"..."r63".  That allows code to run on hardware variants that lack these registers.
-mprefer-short-insn-regs Preferentially allocate registers that allow short instruction generation.  This can result in increased instruction count, so this may either reduce or increase overall code size.
-mbranch-cost=num Set the cost of branches to roughly num "simple" instructions.  This cost is only a heuristic and is not guaranteed to produce consistent results across releases.
-mcmove Enable the generation of conditional moves.
-mnops=num Emit num NOPs before every other generated instruction.
-mno-soft-cmpsf For single-precision floating-point comparisons, emit an "fsub" instruction and test the flags.  This is faster than a software comparison, but can get incorrect results in the presence of NaNs, or when two different small numbers are compared such that their difference is calculated as zero.  The default is -msoft-cmpsf, which uses slower, but IEEE-compliant, software comparisons.
-mstack-offset=num Set the offset between the top of the stack and the stack pointer. E.g., a value of 8 means that the eight bytes in the range "sp+0...sp+7" can be used by leaf functions without stack allocation. Values other than 8 or 16 are untested and unlikely to work.  Note also that this option changes the ABI; compiling a program with a different stack offset than the libraries have been compiled with generally does not work.  This option can be useful if you want to evaluate if a different stack offset would give you better code, but to actually use a different stack offset to build working programs, it is recommended to configure the toolchain with the appropriate --with-stack-offset=num option.
-mno-round-nearest Make the scheduler assume that the rounding mode has been set to truncating.  The default is -mround-nearest.
-mlong-calls If not otherwise specified by an attribute, assume all calls might be beyond the offset range of the "b" / "bl" instructions, and therefore load the function address into a register before performing a (otherwise direct) call.  This is the default.
-mshort-calls If not otherwise specified by an attribute, assume all direct calls are in the range of the "b" / "bl" instructions, so use these instructions for direct calls.  The default is -mlong-calls.
-msmall16 Assume addresses can be loaded as 16-bit unsigned values.  This does not apply to function addresses for which -mlong-calls semantics are in effect.
-mfp-mode=mode Set the prevailing mode of the floating-point unit.  This determines the floating-point mode that is provided and expected at function call and return time.  Making this mode match the mode you predominantly need at function start can make your programs smaller and faster by avoiding unnecessary mode switches.
mode can be set to one the following values:
caller Any mode at function entry is valid, and retained or restored when the function returns, and when it calls other functions. This mode is useful for compiling libraries or other compilation units you might want to incorporate into different programs with different prevailing FPU modes, and the convenience of being able to use a single object file outweighs the size and speed overhead for any extra mode switching that might be needed, compared with what would be needed with a more specific choice of prevailing FPU mode.
truncate This is the mode used for floating-point calculations with truncating (i.e. round towards zero) rounding mode.  That includes conversion from floating point to integer.
round-nearest This is the mode used for floating-point calculations with round- to-nearest-or-even rounding mode.
int This is the mode used to perform integer calculations in the FPU, e.g.  integer multiply, or integer multiply-and-accumulate.
The default is -mfp-mode=caller
-mno-split-lohi -mno-postinc -mno-postmodify Code generation tweaks that disable, respectively, splitting of 32-bit loads, generation of post-increment addresses, and generation of post-modify addresses.  The defaults are msplit-lohi, -mpost-inc, and -mpost-modify.
-mnovect-double Change the preferred SIMD mode to SImode.  The default is -mvect-double, which uses DImode as preferred SIMD mode.
-max-vect-align=num The maximum alignment for SIMD vector mode types.  num may be 4 or 8. The default is 8.  Note that this is an ABI change, even though many library function interfaces are unaffected if they don't use SIMD vector modes in places that affect size and/or alignment of relevant types.
-msplit-vecmove-early Split vector moves into single word moves before reload.  In theory this can give better register allocation, but so far the reverse seems to be generally the case.
-m1reg-reg Specify a register to hold the constant -1, which makes loading small negative constants and certain bitmasks faster.  Allowable values for reg are r43 and r63, which specify use of that register as a fixed register, and none, which means that no register is used for this purpose.  The default is -m1reg-none.
AMD GCN Options
These options are defined specifically for the AMD GCN port.
-march=gpu -mtune=gpu Set architecture type or tuning for gpu. Supported values for gpu are
fiji Compile for GCN3 Fiji devices (gfx803).
gfx900 Compile for GCN5 Vega 10 devices (gfx900).
gfx906 Compile for GCN5 Vega 20 devices (gfx906).
-mstack-size=bytes Specify how many bytes of stack space will be requested for each GPU thread (wave-front).  Beware that there may be many threads and limited memory available.  The size of the stack allocation may also have an impact on run-time performance.  The default is 32KB when using OpenACC or OpenMP, and 1MB otherwise.
ARC Options
The following options control the architecture variant for which code is being compiled:
-mbarrel-shifter Generate instructions supported by barrel shifter.  This is the default unless -mcpu=ARC601 or -mcpu=ARCEM is in effect.
-mjli-always Force to call a function using jli_s instruction.  This option is valid only for ARCv2 architecture.
-mcpu=cpu Set architecture type, register usage, and instruction scheduling parameters for cpu.  There are also shortcut alias options available for backward compatibility and convenience.  Supported values for cpu are
arc600 Compile for ARC600.  Aliases: -mA6, -mARC600.
arc601 Compile for ARC601.  Alias: -mARC601.
arc700 Compile for ARC700.  Aliases: -mA7, -mARC700.  This is the default when configured with --with-cpu=arc700.
arcem Compile for ARC EM.
archs Compile for ARC HS.
em  Compile for ARC EM CPU with no hardware extensions.
em4 Compile for ARC EM4 CPU.
em4_dmips Compile for ARC EM4 DMIPS CPU.
em4_fpus Compile for ARC EM4 DMIPS CPU with the single-precision floating- point extension.
em4_fpuda Compile for ARC EM4 DMIPS CPU with single-precision floating- point and double assist instructions.
hs  Compile for ARC HS CPU with no hardware extensions except the atomic instructions.
hs34 Compile for ARC HS34 CPU.
hs38 Compile for ARC HS38 CPU.
hs38_linux Compile for ARC HS38 CPU with all hardware extensions on.
arc600_norm Compile for ARC 600 CPU with "norm" instructions enabled.
arc600_mul32x16 Compile for ARC 600 CPU with "norm" and 32x16-bit multiply instructions enabled.
arc600_mul64 Compile for ARC 600 CPU with "norm" and "mul64"-family instructions enabled.
arc601_norm Compile for ARC 601 CPU with "norm" instructions enabled.
arc601_mul32x16 Compile for ARC 601 CPU with "norm" and 32x16-bit multiply instructions enabled.
arc601_mul64 Compile for ARC 601 CPU with "norm" and "mul64"-family instructions enabled.
nps400 Compile for ARC 700 on NPS400 chip.
em_mini Compile for ARC EM minimalist configuration featuring reduced register set.
-mdpfp -mdpfp-compact Generate double-precision FPX instructions, tuned for the compact implementation.
-mdpfp-fast Generate double-precision FPX instructions, tuned for the fast implementation.
-mno-dpfp-lrsr Disable "lr" and "sr" instructions from using FPX extension aux registers.
-mea Generate extended arithmetic instructions.  Currently only "divaw", "adds", "subs", and "sat16" are supported.  Only valid for -mcpu=ARC700.
-mno-mpy Do not generate "mpy"-family instructions for ARC700.  This option is deprecated.
-mmul32x16 Generate 32x16-bit multiply and multiply-accumulate instructions.
-mmul64 Generate "mul64" and "mulu64" instructions.  Only valid for -mcpu=ARC600.
-mnorm Generate "norm" instructions.  This is the default if -mcpu=ARC700 is in effect.
-mspfp -mspfp-compact Generate single-precision FPX instructions, tuned for the compact implementation.
-mspfp-fast Generate single-precision FPX instructions, tuned for the fast implementation.
-msimd Enable generation of ARC SIMD instructions via target-specific builtins.  Only valid for -mcpu=ARC700.
-msoft-float This option ignored; it is provided for compatibility purposes only. Software floating-point code is emitted by default, and this default can overridden by FPX options; -mspfp, -mspfp-compact, or -mspfp-fast for single precision, and -mdpfp, -mdpfp-compact, or -mdpfp-fast for double precision.
-mswap Generate "swap" instructions.
-matomic This enables use of the locked load/store conditional extension to implement atomic memory built-in functions.  Not available for ARC 6xx or ARC EM cores.
-mdiv-rem Enable "div" and "rem" instructions for ARCv2 cores.
-mcode-density Enable code density instructions for ARC EM.  This option is on by default for ARC HS.
-mll64 Enable double load/store operations for ARC HS cores.
-mtp-regno=regno Specify thread pointer register number.
-mmpy-option=multo Compile ARCv2 code with a multiplier design option.  You can specify the option using either a string or numeric value for multo.  wlh1 is the default value.  The recognized values are:
0 none No multiplier available.
1 w   16x16 multiplier, fully pipelined.  The following instructions are enabled: "mpyw" and "mpyuw".
2 wlh1 32x32 multiplier, fully pipelined (1 stage).  The following instructions are additionally enabled: "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".
3 wlh2 32x32 multiplier, fully pipelined (2 stages).  The following instructions are additionally enabled: "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".
4 wlh3 Two 16x16 multipliers, blocking, sequential.  The following instructions are additionally enabled: "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".
5 wlh4 One 16x16 multiplier, blocking, sequential.  The following instructions are additionally enabled: "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".
6 wlh5 One 32x4 multiplier, blocking, sequential.  The following instructions are additionally enabled: "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".
7 plus_dmpy ARC HS SIMD support.
8 plus_macd ARC HS SIMD support.
9 plus_qmacw ARC HS SIMD support.
This option is only available for ARCv2 cores.
-mfpu=fpu Enables support for specific floating-point hardware extensions for ARCv2 cores.  Supported values for fpu are:
fpus Enables support for single-precision floating-point hardware extensions.
fpud Enables support for double-precision floating-point hardware extensions.  The single-precision floating-point extension is also enabled.  Not available for ARC EM.
fpuda Enables support for double-precision floating-point hardware extensions using double-precision assist instructions.  The single-precision floating-point extension is also enabled.  This option is only available for ARC EM.
fpuda_div Enables support for double-precision floating-point hardware extensions using double-precision assist instructions.  The single-precision floating-point, square-root, and divide extensions are also enabled.  This option is only available for ARC EM.
fpuda_fma Enables support for double-precision floating-point hardware extensions using double-precision assist instructions.  The single-precision floating-point and fused multiply and add hardware extensions are also enabled.  This option is only available for ARC EM.
fpuda_all Enables support for double-precision floating-point hardware extensions using double-precision assist instructions.  All single-precision floating-point hardware extensions are also enabled.  This option is only available for ARC EM.
fpus_div Enables support for single-precision floating-point, square-root and divide hardware extensions.
fpud_div Enables support for double-precision floating-point, square-root and divide hardware extensions.  This option includes option fpus_div. Not available for ARC EM.
fpus_fma Enables support for single-precision floating-point and fused multiply and add hardware extensions.
fpud_fma Enables support for double-precision floating-point and fused multiply and add hardware extensions.  This option includes option fpus_fma.  Not available for ARC EM.
fpus_all Enables support for all single-precision floating-point hardware extensions.
fpud_all Enables support for all single- and double-precision floating- point hardware extensions.  Not available for ARC EM.
-mirq-ctrl-saved=register-range, blink, lp_count Specifies general-purposes registers that the processor automatically saves/restores on interrupt entry and exit.  register-range is specified as two registers separated by a dash.  The register range always starts with "r0", the upper limit is "fp" register.  blink and lp_count are optional.  This option is only valid for ARC EM and ARC HS cores.
-mrgf-banked-regs=number Specifies the number of registers replicated in second register bank on entry to fast interrupt.  Fast interrupts are interrupts with the highest priority level P0.  These interrupts save only PC and STATUS32 registers to avoid memory transactions during interrupt entry and exit sequences.  Use this option when you are using fast interrupts in an ARC V2 family processor.  Permitted values are 4, 8, 16, and 32.
-mlpc-width=width Specify the width of the "lp_count" register.  Valid values for width are 8, 16, 20, 24, 28 and 32 bits.  The default width is fixed to 32 bits.  If the width is less than 32, the compiler does not attempt to transform loops in your program to use the zero-delay loop mechanism unless it is known that the "lp_count" register can hold the required loop-counter value.  Depending on the width specified, the compiler and run-time library might continue to use the loop mechanism for various needs.  This option defines macro "__ARC_LPC_WIDTH__" with the value of width.
-mrf16 This option instructs the compiler to generate code for a 16-entry register file.  This option defines the "__ARC_RF16__" preprocessor macro.
-mbranch-index Enable use of "bi" or "bih" instructions to implement jump tables.
The following options are passed through to the assembler, and also define preprocessor macro symbols.
-mdsp-packa Passed down to the assembler to enable the DSP Pack A extensions. Also sets the preprocessor symbol "__Xdsp_packa".  This option is deprecated.
-mdvbf Passed down to the assembler to enable the dual Viterbi butterfly extension.  Also sets the preprocessor symbol "__Xdvbf".  This option is deprecated.
-mlock Passed down to the assembler to enable the locked load/store conditional extension.  Also sets the preprocessor symbol "__Xlock".
-mmac-d16 Passed down to the assembler.  Also sets the preprocessor symbol "__Xxmac_d16".  This option is deprecated.
-mmac-24 Passed down to the assembler.  Also sets the preprocessor symbol "__Xxmac_24".  This option is deprecated.
-mrtsc Passed down to the assembler to enable the 64-bit time-stamp counter extension instruction.  Also sets the preprocessor symbol "__Xrtsc". This option is deprecated.
-mswape Passed down to the assembler to enable the swap byte ordering extension instruction.  Also sets the preprocessor symbol "__Xswape".
-mtelephony Passed down to the assembler to enable dual- and single-operand instructions for telephony.  Also sets the preprocessor symbol "__Xtelephony".  This option is deprecated.
-mxy Passed down to the assembler to enable the XY memory extension.  Also sets the preprocessor symbol "__Xxy".
The following options control how the assembly code is annotated:
-misize Annotate assembler instructions with estimated addresses.
-mannotate-align Explain what alignment considerations lead to the decision to make an instruction short or long.
The following options are passed through to the linker:
-marclinux Passed through to the linker, to specify use of the "arclinux" emulation.  This option is enabled by default in tool chains built for "arc-linux-uclibc" and "arceb-linux-uclibc" targets when profiling is not requested.
-marclinux_prof Passed through to the linker, to specify use of the "arclinux_prof" emulation.  This option is enabled by default in tool chains built for "arc-linux-uclibc" and "arceb-linux-uclibc" targets when profiling is requested.
The following options control the semantics of generated code:
-mlong-calls Generate calls as register indirect calls, thus providing access to the full 32-bit address range.
-mmedium-calls Don't use less than 25-bit addressing range for calls, which is the offset available for an unconditional branch-and-link instruction. Conditional execution of function calls is suppressed, to allow use of the 25-bit range, rather than the 21-bit range with conditional branch-and-link.  This is the default for tool chains built for "arc-linux-uclibc" and "arceb-linux-uclibc" targets.
-G num Put definitions of externally-visible data in a small data section if that data is no bigger than num bytes.  The default value of num is 4 for any ARC configuration, or 8 when we have double load/store operations.
-mno-sdata Do not generate sdata references.  This is the default for tool chains built for "arc-linux-uclibc" and "arceb-linux-uclibc" targets.
-mvolatile-cache Use ordinarily cached memory accesses for volatile references.  This is the default.
-mno-volatile-cache Enable cache bypass for volatile references.
The following options fine tune code generation:
-malign-call Do alignment optimizations for call instructions.
-mauto-modify-reg Enable the use of pre/post modify with register displacement.
-mbbit-peephole Enable bbit peephole2.
-mno-brcc This option disables a target-specific pass in arc_reorg to generate compare-and-branch ("brcc") instructions.  It has no effect on generation of these instructions driven by the combiner pass.
-mcase-vector-pcrel Use PC-relative switch case tables to enable case table shortening. This is the default for -Os.
-mcompact-casesi Enable compact "casesi" pattern.  This is the default for -Os, and only available for ARCv1 cores.  This option is deprecated.
-mno-cond-exec Disable the ARCompact-specific pass to generate conditional execution instructions.
Due to delay slot scheduling and interactions between operand numbers, literal sizes, instruction lengths, and the support for conditional execution, the target-independent pass to generate conditional execution is often lacking, so the ARC port has kept a special pass around that tries to find more conditional execution generation opportunities after register allocation, branch shortening, and delay slot scheduling have been done.  This pass generally, but not always, improves performance and code size, at the cost of extra compilation time, which is why there is an option to switch it off.  If you have a problem with call instructions exceeding their allowable offset range because they are conditionalized, you should consider using -mmedium-calls instead.
-mearly-cbranchsi Enable pre-reload use of the "cbranchsi" pattern.
-mexpand-adddi Expand "adddi3" and "subdi3" at RTL generation time into "add.f", "adc" etc.  This option is deprecated.
-mindexed-loads Enable the use of indexed loads.  This can be problematic because some optimizers then assume that indexed stores exist, which is not the case.
-mlra Enable Local Register Allocation.  This is still experimental for ARC, so by default the compiler uses standard reload (i.e. -mno-lra).
-mlra-priority-none Don't indicate any priority for target registers.
-mlra-priority-compact Indicate target register priority for r0..r3 / r12..r15.
-mlra-priority-noncompact Reduce target register priority for r0..r3 / r12..r15.
-mmillicode When optimizing for size (using -Os), prologues and epilogues that have to save or restore a large number of registers are often shortened by using call to a special function in libgcc; this is referred to as a millicode call.  As these calls can pose performance issues, and/or cause linking issues when linking in a nonstandard way, this option is provided to turn on or off millicode call generation.
-mcode-density-frame This option enable the compiler to emit "enter" and "leave" instructions.  These instructions are only valid for CPUs with code- density feature.
-mmixed-code Tweak register allocation to help 16-bit instruction generation. This generally has the effect of decreasing the average instruction size while increasing the instruction count.
-mq-class Ths option is deprecated.  Enable q instruction alternatives.  This is the default for -Os.
-mRcq Enable Rcq constraint handling.  Most short code generation depends on this.  This is the default.
-mRcw Enable Rcw constraint handling.  Most ccfsm condexec mostly depends on this.  This is the default.
-msize-level=level Fine-tune size optimization with regards to instruction lengths and alignment.  The recognized values for level are:
0   No size optimization.  This level is deprecated and treated like 1.
1   Short instructions are used opportunistically.
2   In addition, alignment of loops and of code after barriers are dropped.
3   In addition, optional data alignment is dropped, and the option Os is enabled.
This defaults to 3 when -Os is in effect.  Otherwise, the behavior when this is not set is equivalent to level 1.
-mtune=cpu Set instruction scheduling parameters for cpu, overriding any implied by -mcpu=.
Supported values for cpu are
ARC600 Tune for ARC600 CPU.
ARC601 Tune for ARC601 CPU.
ARC700 Tune for ARC700 CPU with standard multiplier block.
ARC700-xmac Tune for ARC700 CPU with XMAC block.
ARC725D Tune for ARC725D CPU.
ARC750D Tune for ARC750D CPU.
-mmultcost=num Cost to assume for a multiply instruction, with 4 being equal to a normal instruction.
-munalign-prob-threshold=probability Set probability threshold for unaligning branches.  When tuning for ARC700 and optimizing for speed, branches without filled delay slot are preferably emitted unaligned and long, unless profiling indicates that the probability for the branch to be taken is below probability. The default is (REG_BR_PROB_BASE/2), i.e. 5000.
The following options are maintained for backward compatibility, but are now deprecated and will be removed in a future release:
-margonaut Obsolete FPX.
-mbig-endian -EB Compile code for big-endian targets.  Use of these options is now deprecated.  Big-endian code is supported by configuring GCC to build "arceb-elf32" and "arceb-linux-uclibc" targets, for which big endian is the default.
-mlittle-endian -EL Compile code for little-endian targets.  Use of these options is now deprecated.  Little-endian code is supported by configuring GCC to build "arc-elf32" and "arc-linux-uclibc" targets, for which little endian is the default.
-mbarrel_shifter Replaced by -mbarrel-shifter.
-mdpfp_compact Replaced by -mdpfp-compact.
-mdpfp_fast Replaced by -mdpfp-fast.
-mdsp_packa Replaced by -mdsp-packa.
-mEA Replaced by -mea.
-mmac_24 Replaced by -mmac-24.
-mmac_d16 Replaced by -mmac-d16.
-mspfp_compact Replaced by -mspfp-compact.
-mspfp_fast Replaced by -mspfp-fast.
-mtune=cpu Values arc600, arc601, arc700 and arc700-xmac for cpu are replaced by ARC600, ARC601, ARC700 and ARC700-xmac respectively.
-multcost=num Replaced by -mmultcost.
ARM Options
These -m options are defined for the ARM port:
-mabi=name Generate code for the specified ABI.  Permissible values are: apcs- gnu, atpcs, aapcs, aapcs-linux and iwmmxt.
-mapcs-frame Generate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if this is not strictly necessary for correct execution of the code.  Specifying -fomit-frame-pointer with this option causes the stack frames not to be generated for leaf functions.  The default is -mno-apcs-frame.  This option is deprecated.
-mapcs This is a synonym for -mapcs-frame and is deprecated.
-mthumb-interwork Generate code that supports calling between the ARM and Thumb instruction sets.  Without this option, on pre-v5 architectures, the two instruction sets cannot be reliably used inside one program.  The default is -mno-thumb-interwork, since slightly larger code is generated when -mthumb-interwork is specified.  In AAPCS configurations this option is meaningless.
-mno-sched-prolog Prevent the reordering of instructions in the function prologue, or the merging of those instruction with the instructions in the function's body.  This means that all functions start with a recognizable set of instructions (or in fact one of a choice from a small set of different function prologues), and this information can be used to locate the start of functions inside an executable piece of code.  The default is -msched-prolog.
-mfloat-abi=name Specifies which floating-point ABI to use.  Permissible values are: soft, softfp and hard.
Specifying soft causes GCC to generate output containing library calls for floating-point operations.  softfp allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions.  hard allows generation of floating- point instructions and uses FPU-specific calling conventions.
The default depends on the specific target configuration.  Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.
-mlittle-endian Generate code for a processor running in little-endian mode.  This is the default for all standard configurations.
-mbig-endian Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor.