neulab/tldr huggingface dataset:
-mno-gpopt implies -mno-local-sdata and -mno-extern-sdata.
-membedded-data -mno-embedded-data Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems.
-muninit-const-in-rodata -mno-uninit-const-in-rodata Put uninitialized "const" variables in the read-only data section. This option is only meaningful in conjunction with -membedded-data.
-mcode-readable=setting Specify whether GCC may generate code that reads from executable sections.  There are three possible settings:
-mcode-readable=yes Instructions may freely access executable sections.  This is the default setting.
-mcode-readable=pcrel MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do so.  This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set.  It is also useful on processors that can be configured to have a dual instruction/data SRAM interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM.
-mcode-readable=no Instructions must not access executable sections.  This option can be useful on targets that are configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM.
-msplit-addresses -mno-split-addresses Enable (disable) use of the "%hi()" and "%lo()" assembler relocation operators.  This option has been superseded by -mexplicit-relocs but is retained for backwards compatibility.
-mexplicit-relocs -mno-explicit-relocs Use (do not use) assembler relocation operators when dealing with symbolic addresses.  The alternative, selected by -mno-explicit-relocs, is to use assembler macros instead.
-mexplicit-relocs is the default if GCC was configured to use an assembler that supports relocation operators.
-mcheck-zero-division -mno-check-zero-division Trap (do not trap) on integer division by zero.
The default is -mcheck-zero-division.
-mdivide-traps -mdivide-breaks MIPS systems check for division by zero by generating either a conditional trap or a break instruction.  Using traps results in smaller code, but is only supported on MIPS II and later.  Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal ("SIGFPE").  Use -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force the use of breaks.
The default is usually -mdivide-traps, but this can be overridden at configure time using --with-divide=breaks.  Divide-by-zero checks can be completely disabled using -mno-check-zero-division.
-mload-store-pairs -mno-load-store-pairs Enable (disable) an optimization that pairs consecutive load or store instructions to enable load/store bonding.  This option is enabled by default but only takes effect when the selected architecture is known to support bonding.
-mmemcpy -mno-memcpy Force (do not force) the use of "memcpy" for non-trivial block moves. The default is -mno-memcpy, which allows GCC to inline most constant- sized copies.
-mlong-calls -mno-long-calls Disable (do not disable) use of the "jal" instruction.  Calling functions using "jal" is more efficient but requires the caller and callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code.  The default is -mno-long-calls.
-mmad -mno-mad Enable (disable) use of the "mad", "madu" and "mul" instructions, as provided by the R4650 ISA.
-mimadd -mno-imadd Enable (disable) use of the "madd" and "msub" integer instructions. The default is -mimadd on architectures that support "madd" and "msub" except for the 74k architecture where it was found to generate slower code.
-mfused-madd -mno-fused-madd Enable (disable) use of the floating-point multiply-accumulate instructions, when they are available.  The default is -mfused-madd.
On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit.  This may be undesirable in some circumstances.  On other processors the result is numerically identical to the equivalent computation using separate multiply, add, subtract and negate instructions.
-nocpp Tell the MIPS assembler to not run its preprocessor over user assembler files (with a .s suffix) when assembling them.
-mfix-24k -mno-fix-24k Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the assembler rather than by GCC.
-mfix-r4000 -mno-fix-r4000 Work around certain R4000 CPU errata:
-   A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division.
-   A double-word or a variable shift may give an incorrect result if executed while an integer multiplication is in progress.
-   An integer division may give an incorrect result if started in a delay slot of a taken branch or a jump.
-mfix-r4400 -mno-fix-r4400 Work around certain R4400 CPU errata:
-mfix-r10000 -mno-fix-r10000 Work around certain R10000 errata:
-   "ll"/"sc" sequences may not behave atomically on revisions prior to 3.0.  They may deadlock on revisions 2.6 and earlier.
This option can only be used if the target architecture supports branch-likely instructions.  -mfix-r10000 is the default when -march=r10000 is used; -mno-fix-r10000 is the default otherwise.
-mfix-r5900 -mno-fix-r5900 Do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a "nop" instruction there instead.  The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. The workaround is implemented by the assembler rather than by GCC.
-mfix-rm7000 -mno-fix-rm7000 Work around the RM7000 "dmult"/"dmultu" errata.  The workarounds are implemented by the assembler rather than by GCC.
-mfix-vr4120 -mno-fix-vr4120 Work around certain VR4120 errata:
-   "dmultu" does not always produce the correct result.
-   "div" and "ddiv" do not always produce the correct result if one of the operands is negative.
The workarounds for the division errata rely on special functions in libgcc.a.  At present, these functions are only provided by the "mips64vr*-elf" configurations.
Other VR4120 errata require a NOP to be inserted between certain pairs of instructions.  These errata are handled by the assembler, not by GCC itself.
-mfix-vr4130 Work around the VR4130 "mflo"/"mfhi" errata.  The workarounds are implemented by the assembler rather than by GCC, although GCC avoids using "mflo" and "mfhi" if the VR4130 "macc", "macchi", "dmacc" and "dmacchi" instructions are available instead.
-mfix-sb1 -mno-fix-sb1 Work around certain SB-1 CPU core errata.  (This flag currently works around the SB-1 revision 2 "F1" and "F2" floating-point errata.)
-mr10k-cache-barrier=setting Specify whether GCC should insert cache barriers to avoid the side effects of speculation on R10K processors.
In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the "taken" branch.  It later aborts these instructions if the predicted outcome is wrong.  However, on the R10K, even aborted instructions can have side effects.
This problem only affects kernel stores and, depending on the system, kernel loads.  As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted.  If a DMA operation writes to the same area of memory before the "dirty" line is flushed, the cached data overwrites the DMA-ed data.  See the R10K processor manual for a full description, including other potential problems.
One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted.  -mr10k-cache-barrier=setting controls GCC's implementation of this workaround.  It assumes that aborted accesses to any byte in the following regions does not have side effects:
1.  the memory occupied by the current function's stack frame;
2.  the memory occupied by an incoming stack argument;
3.  the memory occupied by an object with a link-time-constant address.
It is the kernel's responsibility to ensure that speculative accesses to these regions are indeed safe.
If the input program contains a function declaration such as:
void foo (void);
then the implementation of "foo" must allow "j foo" and "jal foo" to be executed speculatively.  GCC honors this restriction for functions it compiles itself.  It expects non-GCC functions (such as hand- written assembly code) to do the same.
The option has three forms:
-mr10k-cache-barrier=load-store Insert a cache barrier before a load or store that might be speculatively executed and that might have side effects even if aborted.
-mr10k-cache-barrier=store Insert a cache barrier before a store that might be speculatively executed and that might have side effects even if aborted.
-mr10k-cache-barrier=none Disable the insertion of cache barriers.  This is the default setting.
-mflush-func=func -mno-flush-func Specifies the function to call to flush the I and D caches, or to not call any such function.  If called, the function must take the same arguments as the common "_flush_func", that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches).  The default depends on the target GCC was configured for, but commonly is either "_flush_func" or "__cpu_flush".
mbranch-cost=num Set the cost of branches to roughly num "simple" instructions.  This cost is only a heuristic and is not guaranteed to produce consistent results across releases.  A zero cost redundantly selects the default, which is based on the -mtune setting.
-mbranch-likely -mno-branch-likely Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture.  By default, Branch Likely instructions may be generated if they are supported by the selected architecture.  An exception is for the MIPS32 and MIPS64 architectures and processors that implement those architectures; for those, Branch Likely instructions are not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use.
-mcompact-branches=never -mcompact-branches=optimal -mcompact-branches=always These options control which form of branches will be generated.  The default is -mcompact-branches=optimal.
The -mcompact-branches=never option ensures that compact branch instructions will never be generated.
The -mcompact-branches=always option ensures that a compact branch instruction will be generated if available.  If a compact branch instruction is not available, a delay slot form of the branch will be used instead.
This option is supported from MIPS Release 6 onwards.
The -mcompact-branches=optimal option will cause a delay slot branch to be used if one is available in the current ISA and the delay slot is successfully filled.  If the delay slot is not filled, a compact branch will be chosen if one is available.
-mfp-exceptions -mno-fp-exceptions Specifies whether FP exceptions are enabled.  This affects how FP instructions are scheduled for some processors.  The default is that FP exceptions are enabled.
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes.  Otherwise, we can only use one FP pipe.
-mvr4130-align -mno-vr4130-align The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned.  When this option is enabled, GCC aligns pairs of instructions that it thinks should execute in parallel.
This option only has an effect when optimizing for the VR4130.  It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3.
-msynci -mno-synci Enable (disable) generation of "synci" instructions on architectures that support it.  The "synci" instructions (if enabled) are generated when "__builtin___clear_cache" is compiled.
This option defaults to -mno-synci, but the default can be overridden by configuring GCC with --with-synci.
When compiling code for single processor systems, it is generally safe to use "synci".  However, on many multi-core (SMP) systems, it does not invalidate the instruction caches on all cores and may lead to undefined behavior.
-mrelax-pic-calls -mno-relax-pic-calls Try to turn PIC calls that are normally dispatched via register $25 into direct calls.  This is only possible if the linker can resolve the destination at link time and if the destination is within range for a direct call.
-mrelax-pic-calls is the default if GCC was configured to use an assembler and a linker that support the ".reloc" assembly directive and -mexplicit-relocs is in effect.  With -mno-explicit-relocs, this optimization can be performed by the assembler and the linker alone without help from the compiler.
-mmcount-ra-address -mno-mcount-ra-address Emit (do not emit) code that allows "_mcount" to modify the calling function's return address.  When enabled, this option extends the usual "_mcount" interface with a new ra-address parameter, which has type "intptr_t *" and is passed in register $12.  "_mcount" can then modify the return address by doing both of the following:
*   Returning the new address in register $31.
*   Storing the new address in "*ra-address", if ra-address is nonnull.
The default is -mno-mcount-ra-address.
-mframe-header-opt -mno-frame-header-opt Enable (disable) frame header optimization in the o32 ABI.  When using the o32 ABI, calling functions will allocate 16 bytes on the stack for the called function to write out register arguments.  When enabled, this optimization will suppress the allocation of the frame header if it can be determined that it is unused.
This optimization is off by default at all optimization levels.
-mlxc1-sxc1 -mno-lxc1-sxc1 When applicable, enable (disable) the generation of "lwxc1", "swxc1", "ldxc1", "sdxc1" instructions.  Enabled by default.
-mmadd4 -mno-madd4 When applicable, enable (disable) the generation of 4-operand "madd.s", "madd.d" and related instructions.  Enabled by default.
MMIX Options
These options are defined for the MMIX:
-mlibfuncs -mno-libfuncs Specify that intrinsic library functions are being compiled, passing all values in registers, no matter the size.
-mepsilon -mno-epsilon Generate floating-point comparison instructions that compare with respect to the "rE" epsilon register.
-mabi=mmixware -mabi=gnu Generate code that passes function parameters and return values that (in the called function) are seen as registers $0 and up, as opposed to the GNU ABI which uses global registers $231 and up.
-mzero-extend -mno-zero-extend When reading data from memory in sizes shorter than 64 bits, use (do not use) zero-extending load instructions by default, rather than sign-extending ones.
-mknuthdiv -mno-knuthdiv Make the result of a division yielding a remainder have the same sign as the divisor.  With the default, -mno-knuthdiv, the sign of the remainder follows the sign of the dividend.  Both methods are arithmetically valid, the latter being almost exclusively used.
-mtoplevel-symbols -mno-toplevel-symbols Prepend (do not prepend) a : to all global symbols, so the assembly code can be used with the "PREFIX" assembly directive.
-melf Generate an executable in the ELF format, rather than the default mmo format used by the mmix simulator.
-mbranch-predict -mno-branch-predict Use (do not use) the probable-branch instructions, when static branch prediction indicates a probable branch.
-mbase-addresses -mno-base-addresses Generate (do not generate) code that uses base addresses.  Using a base address automatically generates a request (handled by the assembler and the linker) for a constant to be set up in a global register.  The register is used for one or more base address requests within the range 0 to 255 from the value held in the register.  The generally leads to short and fast code, but the number of different data items that can be addressed is limited.  This means that a program that uses lots of static data may require -mno-base-addresses.
-msingle-exit -mno-single-exit Force (do not force) generated code to have a single exit point in each function.
MN10300 Options
These -m options are defined for Matsushita MN10300 architectures:
-mmult-bug Generate code to avoid bugs in the multiply instructions for the MN10300 processors.  This is the default.
-mno-mult-bug Do not generate code to avoid bugs in the multiply instructions for the MN10300 processors.
-mam33 Generate code using features specific to the AM33 processor.
-mno-am33 Do not generate code using features specific to the AM33 processor. This is the default.
-mam33-2 Generate code using features specific to the AM33/2.0 processor.
-mam34 Generate code using features specific to the AM34 processor.
-mtune=cpu-type Use the timing characteristics of the indicated CPU type when scheduling instructions.  This does not change the targeted processor type.  The CPU type must be one of mn10300, am33, am33-2 or am34.
-mreturn-pointer-on-d0 When generating a function that returns a pointer, return the pointer in both "a0" and "d0".  Otherwise, the pointer is returned only in "a0", and attempts to call such functions without a prototype result in errors.  Note that this option is on by default; use -mno-return-pointer-on-d0 to disable it.
-mno-crt0 Do not link in the C run-time initialization object file.
-mrelax Indicate to the linker that it should perform a relaxation optimization pass to shorten branches, calls and absolute memory addresses.  This option only has an effect when used on the command line for the final link step.
This option makes symbolic debugging impossible.
-mliw Allow the compiler to generate Long Instruction Word instructions if the target is the AM33 or later.  This is the default.  This option defines the preprocessor macro "__LIW__".
-mno-liw Do not allow the compiler to generate Long Instruction Word instructions.  This option defines the preprocessor macro "__NO_LIW__".
-msetlb Allow the compiler to generate the SETLB and Lcc instructions if the target is the AM33 or later.  This is the default.  This option defines the preprocessor macro "__SETLB__".
-mno-setlb Do not allow the compiler to generate SETLB or Lcc instructions. This option defines the preprocessor macro "__NO_SETLB__".
Moxie Options
-meb Generate big-endian code.  This is the default for moxie-*-* configurations.
-mmul.x Generate mul.x and umul.x instructions.  This is the default for moxiebox-*-* configurations.
MSP430 Options
These options are defined for the MSP430:
-masm-hex Force assembly output to always use hex constants.  Normally such constants are signed decimals, but this option is available for testsuite and/or aesthetic purposes.
-mmcu= Select the MCU to target.  This is used to create a C preprocessor symbol based upon the MCU name, converted to upper case and pre- and post-fixed with __.  This in turn is used by the msp430.h header file to select an MCU-specific supplementary header file.
The option also sets the ISA to use.  If the MCU name is one that is known to only support the 430 ISA then that is selected, otherwise the 430X ISA is selected.  A generic MCU name of msp430 can also be used to select the 430 ISA.  Similarly the generic msp430x MCU name selects the 430X ISA.
In addition an MCU-specific linker script is added to the linker command line.  The script's name is the name of the MCU with .ld appended.  Thus specifying -mmcu=xxx on the gcc command line defines the C preprocessor symbol "__XXX__" and cause the linker to search for a script called xxx.ld.
The ISA and hardware multiply supported for the different MCUs is hard-coded into GCC.  However, an external devices.csv file can be used to extend device support beyond those that have been hard-coded.
GCC searches for the devices.csv file using the following methods in the given precedence order, where the first method takes precendence over the second which takes precedence over the third.
Include path specified with "-I" and "-L" devices.csv will be searched for in each of the directories specified by include paths and linker library search paths.
Path specified by the environment variable MSP430_GCC_INCLUDE_DIR Define the value of the global environment variable MSP430_GCC_INCLUDE_DIR to the full path to the directory containing devices.csv, and GCC will search this directory for devices.csv.  If devices.csv is found, this directory will also be registered as an include path, and linker library path. Header files and linker scripts in this directory can therefore be used without manually specifying "-I" and "-L" on the command line.
The msp430-elf{,bare}/include/devices directory Finally, GCC will examine msp430-elf{,bare}/include/devices from the toolchain root directory.  This directory does not exist in a default installation, but if the user has created it and copied devices.csv there, then the MCU data will be read.  As above, this directory will also be registered as an include path, and linker library path.
If none of the above search methods find devices.csv, then the hard- coded MCU data is used.
-mwarn-mcu -mno-warn-mcu This option enables or disables warnings about conflicts between the MCU name specified by the -mmcu option and the ISA set by the -mcpu option and/or the hardware multiply support set by the -mhwmult option.  It also toggles warnings about unrecognized MCU names.  This option is on by default.
-mcpu= Specifies the ISA to use.  Accepted values are msp430, msp430x and msp430xv2.  This option is deprecated.  The -mmcu= option should be used to select the ISA.
-msim Link to the simulator runtime libraries and linker script.  Overrides any scripts that would be selected by the -mmcu= option.
-mlarge Use large-model addressing (20-bit pointers, 20-bit "size_t").
-msmall Use small-model addressing (16-bit pointers, 16-bit "size_t").
-mrelax This option is passed to the assembler and linker, and allows the linker to perform certain optimizations that cannot be done until the final link.
mhwmult= Describes the type of hardware multiply supported by the target. Accepted values are none for no hardware multiply, 16bit for the original 16-bit-only multiply supported by early MCUs.  32bit for the 16/32-bit multiply supported by later MCUs and f5series for the 16/32-bit multiply supported by F5-series MCUs.  A value of auto can also be given.  This tells GCC to deduce the hardware multiply support based upon the MCU name provided by the -mmcu option.  If no -mmcu option is specified or if the MCU name is not recognized then no hardware multiply support is assumed.  "auto" is the default setting.
Hardware multiplies are normally performed by calling a library routine.  This saves space in the generated code.  When compiling at -O3 or higher however the hardware multiplier is invoked inline. This makes for bigger, but faster code.
The hardware multiply routines disable interrupts whilst running and restore the previous interrupt state when they finish.  This makes them safe to use inside interrupt handlers as well as in normal code.
-minrt Enable the use of a minimum runtime environment - no static initializers or constructors.  This is intended for memory- constrained devices.  The compiler includes special symbols in some objects that tell the linker and runtime which code fragments are required.
-mtiny-printf Enable reduced code size "printf" and "puts" library functions.  The tiny implementations of these functions are not reentrant, so must be used with caution in multi-threaded applications.
Support for streams has been removed and the string to be printed will always be sent to stdout via the "write" syscall.  The string is not buffered before it is sent to write.
This option requires Newlib Nano IO, so GCC must be configured with --enable-newlib-nano-formatted-io.
-mmax-inline-shift= This option takes an integer between 0 and 64 inclusive, and sets the maximum number of inline shift instructions which should be emitted to perform a shift operation by a constant amount.  When this value needs to be exceeded, an mspabi helper function is used instead.  The default value is 4.
This only affects cases where a shift by multiple positions cannot be completed with a single instruction (e.g. all shifts >1 on the 430 ISA).
Shifts of a 32-bit value are at least twice as costly, so the value passed for this option is divided by 2 and the resulting value used instead.
-mcode-region= -mdata-region= These options tell the compiler where to place functions and data that do not have one of the "lower", "upper", "either" or "section" attributes.  Possible values are "lower", "upper", "either" or "any". The first three behave like the corresponding attribute.  The fourth possible value - "any" - is the default.  It leaves placement entirely up to the linker script and how it assigns the standard sections (".text", ".data", etc) to the memory regions.
-msilicon-errata= This option passes on a request to assembler to enable the fixes for the named silicon errata.
-msilicon-errata-warn= This option passes on a request to the assembler to enable warning messages when a silicon errata might need to be applied.
-mwarn-devices-csv -mno-warn-devices-csv Warn if devices.csv is not found or there are problem parsing it (default: on).
NDS32 Options
These options are defined for NDS32 implementations:
-mbig-endian Generate code in big-endian mode.
-mlittle-endian Generate code in little-endian mode.
-mreduced-regs Use reduced-set registers for register allocation.
-mfull-regs Use full-set registers for register allocation.
-mcmov Generate conditional move instructions.
-mno-cmov Do not generate conditional move instructions.
-mext-perf Generate performance extension instructions.
-mno-ext-perf Do not generate performance extension instructions.
-mext-perf2 Generate performance extension 2 instructions.
-mno-ext-perf2 Do not generate performance extension 2 instructions.
-mext-string Generate string extension instructions.
-mno-ext-string Do not generate string extension instructions.
-mv3push Generate v3 push25/pop25 instructions.
-mno-v3push Do not generate v3 push25/pop25 instructions.
-m16-bit Generate 16-bit instructions.
-mno-16-bit Do not generate 16-bit instructions.
-misr-vector-size=num Specify the size of each interrupt vector, which must be 4 or 16.
-mcache-block-size=num Specify the size of each cache block, which must be a power of 2 between 4 and 512.
-march=arch Specify the name of the target architecture.
-mcmodel=code-model Set the code model to one of
small All the data and read-only data segments must be within 512KB addressing space.  The text segment must be within 16MB addressing space.
medium The data segment must be within 512KB while the read-only data segment can be within 4GB addressing space.  The text segment should be still within 16MB addressing space.
large All the text and data segments can be within 4GB addressing space.
-mctor-dtor Enable constructor/destructor feature.
-mrelax Guide linker to relax instructions.
Nios II Options
These are the options defined for the Altera Nios II processor.
-G num Put global and static objects less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS sections.  The default value of num is 8.
-mgpopt=option -mgpopt -mno-gpopt Generate (do not generate) GP-relative accesses.  The following option names are recognized:
none Do not generate GP-relative accesses.
local Generate GP-relative accesses for small data objects that are not external, weak, or uninitialized common symbols.  Also use GP- relative addressing for objects that have been explicitly placed in a small data section via a "section" attribute.
global As for local, but also generate GP-relative accesses for small data objects that are external, weak, or common.  If you use this option, you must ensure that all parts of your program (including libraries) are compiled with the same -G setting.
data Generate GP-relative accesses for all data objects in the program.  If you use this option, the entire data and BSS segments of your program must fit in 64K of memory and you must use an appropriate linker script to allocate them within the addressable range of the global pointer.
all Generate GP-relative addresses for function pointers as well as data pointers.  If you use this option, the entire text, data, and BSS segments of your program must fit in 64K of memory and you must use an appropriate linker script to allocate them within the addressable range of the global pointer.
-mgpopt is equivalent to -mgpopt=local, and -mno-gpopt is equivalent to -mgpopt=none.
The default is -mgpopt except when -fpic or -fPIC is specified to generate position-independent code.  Note that the Nios II ABI does not permit GP-relative accesses from shared libraries.
You may need to specify -mno-gpopt explicitly when building programs that include large amounts of small data, including large GOT data sections.  In this case, the 16-bit offset for GP-relative addressing may not be large enough to allow access to the entire small data section.
-mgprel-sec=regexp This option specifies additional section names that can be accessed via GP-relative addressing.  It is most useful in conjunction with "section" attributes on variable declarations and a custom linker script.  The regexp is a POSIX Extended Regular Expression.
This option does not affect the behavior of the -G option, and the specified sections are in addition to the standard ".sdata" and ".sbss" small-data sections that are recognized by -mgpopt.
-mr0rel-sec=regexp This option specifies names of sections that can be accessed via a 16-bit offset from "r0"; that is, in the low 32K or high 32K of the 32-bit address space.  It is most useful in conjunction with "section" attributes on variable declarations and a custom linker script.  The regexp is a POSIX Extended Regular Expression.
In contrast to the use of GP-relative addressing for small data, zero-based addressing is never generated by default and there are no conventional section names used in standard linker scripts for sections in the low or high areas of memory.
-mel -meb Generate little-endian (default) or big-endian (experimental) code, respectively.
-march=arch This specifies the name of the target Nios II architecture.  GCC uses this name to determine what kind of instructions it can emit when generating assembly code.  Permissible names are: r1, r2.
The preprocessor macro "__nios2_arch__" is available to programs, with value 1 or 2, indicating the targeted ISA level.
-mbypass-cache -mno-bypass-cache Force all load and store instructions to always bypass cache by using I/O variants of the instructions. The default is not to bypass the cache.
-mno-cache-volatile -mcache-volatile Volatile memory access bypass the cache using the I/O variants of the load and store instructions. The default is not to bypass the cache.
-mno-fast-sw-div -mfast-sw-div Do not use table-based fast divide for small numbers. The default is to use the fast divide at -O3 and above.
-mno-hw-mul -mhw-mul -mno-hw-mulx -mhw-mulx -mno-hw-div -mhw-div Enable or disable emitting "mul", "mulx" and "div" family of instructions by the compiler. The default is to emit "mul" and not emit "div" and "mulx".
-mbmx -mno-bmx -mcdx -mno-cdx Enable or disable generation of Nios II R2 BMX (bit manipulation) and CDX (code density) instructions.  Enabling these instructions also requires -march=r2.  Since these instructions are optional extensions to the R2 architecture, the default is not to emit them.
-mcustom-insn=N -mno-custom-insn Each -mcustom-insn=N option enables use of a custom instruction with encoding N when generating code that uses insn.  For example, -mcustom-fadds=253 generates custom instruction 253 for single- precision floating-point add operations instead of the default behavior of using a library call.
The following values of insn are supported.  Except as otherwise noted, floating-point operations are expected to be implemented with normal IEEE 754 semantics and correspond directly to the C operators or the equivalent GCC built-in functions.
Single-precision floating point:
fadds, fsubs, fdivs, fmuls Binary arithmetic operations.
fnegs Unary negation.
fabss Unary absolute value.
fcmpeqs, fcmpges, fcmpgts, fcmples, fcmplts, fcmpnes Comparison operations.
fmins, fmaxs Floating-point minimum and maximum.  These instructions are only generated if -ffinite-math-only is specified.
fsqrts Unary square root operation.
fcoss, fsins, ftans, fatans, fexps, flogs Floating-point trigonometric and exponential functions.  These instructions are only generated if -funsafe-math-optimizations is also specified.
Double-precision floating point:
faddd, fsubd, fdivd, fmuld Binary arithmetic operations.
fnegd Unary negation.
fabsd Unary absolute value.
fcmpeqd, fcmpged, fcmpgtd, fcmpled, fcmpltd, fcmpned Comparison operations.
fmind, fmaxd Double-precision minimum and maximum.  These instructions are only generated if -ffinite-math-only is specified.
fsqrtd Unary square root operation.
fcosd, fsind, ftand, fatand, fexpd, flogd Double-precision trigonometric and exponential functions.  These instructions are only generated if -funsafe-math-optimizations is also specified.
Conversions:
fextsd Conversion from single precision to double precision.
ftruncds Conversion from double precision to single precision.
fixsi, fixsu, fixdi, fixdu Conversion from floating point to signed or unsigned integer types, with truncation towards zero.
round Conversion from single-precision floating point to signed integer, rounding to the nearest integer and ties away from zero. This corresponds to the "__builtin_lroundf" function when -fno-math-errno is used.
floatis, floatus, floatid, floatud Conversion from signed or unsigned integer types to floating- point types.
In addition, all of the following transfer instructions for internal registers X and Y must be provided to use any of the double-precision floating-point instructions.  Custom instructions taking two double- precision source operands expect the first operand in the 64-bit register X.  The other operand (or only operand of a unary operation) is given to the custom arithmetic instruction with the least significant half in source register src1 and the most significant half in src2.  A custom instruction that returns a double-precision result returns the most significant 32 bits in the destination register and the other half in 32-bit register Y.  GCC automatically generates the necessary code sequences to write register X and/or read register Y when double-precision floating-point instructions are used.
fwrx Write src1 into the least significant half of X and src2 into the most significant half of X.
fwry Write src1 into Y.
frdxhi, frdxlo Read the most or least (respectively) significant half of X and store it in dest.
frdy Read the value of Y and store it into dest.
Note that you can gain more local control over generation of Nios II custom instructions by using the "target("custom-insn=N")" and "target("no-custom-insn")" function attributes or pragmas.
-mcustom-fpu-cfg=name This option enables a predefined, named set of custom instruction encodings (see -mcustom-insn above).  Currently, the following sets are defined:
-mcustom-fpu-cfg=60-1 is equivalent to: -mcustom-fmuls=252 -mcustom-fadds=253 -mcustom-fsubs=254 -fsingle-precision-constant
-mcustom-fpu-cfg=60-2 is equivalent to: -mcustom-fmuls=252 -mcustom-fadds=253 -mcustom-fsubs=254 -mcustom-fdivs=255 -fsingle-precision-constant
-mcustom-fpu-cfg=72-3 is equivalent to: -mcustom-floatus=243 -mcustom-fixsi=244 -mcustom-floatis=245 -mcustom-fcmpgts=246 -mcustom-fcmples=249 -mcustom-fcmpeqs=250 -mcustom-fcmpnes=251 -mcustom-fmuls=252 -mcustom-fadds=253 -mcustom-fsubs=254 -mcustom-fdivs=255 -fsingle-precision-constant
-mcustom-fpu-cfg=fph2 is equivalent to: -mcustom-fabss=224 -mcustom-fnegs=225 -mcustom-fcmpnes=226 -mcustom-fcmpeqs=227 -mcustom-fcmpges=228 -mcustom-fcmpgts=229 -mcustom-fcmples=230 -mcustom-fcmplts=231 -mcustom-fmaxs=232 -mcustom-fmins=233 -mcustom-round=248 -mcustom-fixsi=249 -mcustom-floatis=250 -mcustom-fsqrts=251 -mcustom-fmuls=252 -mcustom-fadds=253 -mcustom-fsubs=254 -mcustom-fdivs=255
Custom instruction assignments given by individual -mcustom-insn= options override those given by -mcustom-fpu-cfg=, regardless of the order of the options on the command line.
Note that you can gain more local control over selection of a FPU configuration by using the "target("custom-fpu-cfg=name")" function attribute or pragma.
The name fph2 is an abbreviation for Nios II Floating Point Hardware 2 Component.  Please note that the custom instructions enabled by -mcustom-fmins=233 and -mcustom-fmaxs=234 are only generated if -ffinite-math-only is specified.  The custom instruction enabled by -mcustom-round=248 is only generated if -fno-math-errno is specified. In contrast to the other configurations, -fsingle-precision-constant is not set.
These additional -m options are available for the Altera Nios II ELF (bare-metal) target:
-mhal Link with HAL BSP.  This suppresses linking with the GCC-provided C runtime startup and termination code, and is typically used in conjunction with -msys-crt0= to specify the location of the alternate startup code provided by the HAL BSP.
-msmallc Link with a limited version of the C library, -lsmallc, rather than Newlib.
-msys-crt0=startfile startfile is the file name of the startfile (crt0) to use when linking.  This option is only useful in conjunction with -mhal.
-msys-lib=systemlib systemlib is the library name of the library that provides low-level system calls required by the C library, e.g. "read" and "write". This option is typically used to link with a library provided by a HAL BSP.
Nvidia PTX Options
These options are defined for Nvidia PTX:
-m64 Ignored, but preserved for backward compatibility.  Only 64-bit ABI is supported.
-misa=ISA-string Generate code for given the specified PTX ISA (e.g. sm_35).  ISA strings must be lower-case.  Valid ISA strings include sm_30 and sm_35.  The default ISA is sm_35.
-mmainkernel Link in code for a __main kernel.  This is for stand-alone instead of offloading execution.
-moptimize Apply partitioned execution optimizations.  This is the default when any level of optimization is selected.
-msoft-stack Generate code that does not use ".local" memory directly for stack storage. Instead, a per-warp stack pointer is maintained explicitly. This enables variable-length stack allocation (with variable-length arrays or "alloca"), and when global memory is used for underlying storage, makes it possible to access automatic variables from other threads, or with atomic instructions. This code generation variant is used for OpenMP offloading, but the option is exposed on its own for the purpose of testing the compiler; to generate code suitable for linking into programs using OpenMP offloading, use option -mgomp.
-muniform-simt Switch to code generation variant that allows to execute all threads in each warp, while maintaining memory state and side effects as if only one thread in each warp was active outside of OpenMP SIMD regions.  All atomic operations and calls to runtime (malloc, free, vprintf) are conditionally executed (iff current lane index equals the master lane index), and the register being assigned is copied via a shuffle instruction from the master lane.  Outside of SIMD regions lane 0 is the master; inside, each thread sees itself as the master. Shared memory array "int __nvptx_uni[]" stores all-zeros or all-ones bitmasks for each warp, indicating current mode (0 outside of SIMD regions).  Each thread can bitwise-and the bitmask at position "tid.y" with current lane index to compute the master lane index.
-mgomp Generate code for use in OpenMP offloading: enables -msoft-stack and -muniform-simt options, and selects corresponding multilib variant.
OpenRISC Options
These options are defined for OpenRISC:
-mboard=name Configure a board specific runtime.  This will be passed to the linker for newlib board library linking.  The default is "or1ksim".
-mnewlib This option is ignored; it is for compatibility purposes only.  This used to select linker and preprocessor options for use with newlib.
-msoft-div -mhard-div Select software or hardware divide ("l.div", "l.divu") instructions. This default is hardware divide.
-msoft-mul -mhard-mul Select software or hardware multiply ("l.mul", "l.muli") instructions.  This default is hardware multiply.
-msoft-float -mhard-float Select software or hardware for floating point operations.  The default is software.
-mdouble-float When -mhard-float is selected, enables generation of double-precision floating point instructions.  By default functions from libgcc are used to perform double-precision floating point operations.
-munordered-float When -mhard-float is selected, enables generation of unordered floating point compare and set flag ("lf.sfun*") instructions.  By default functions from libgcc are used to perform unordered floating point compare and set flag operations.
-mcmov Enable generation of conditional move ("l.cmov") instructions.  By default the equivalent will be generated using set and branch.
-mror Enable generation of rotate right ("l.ror") instructions.  By default functions from libgcc are used to perform rotate right operations.
-mrori Enable generation of rotate right with immediate ("l.rori") instructions.  By default functions from libgcc are used to perform rotate right with immediate operations.
-msext Enable generation of sign extension ("l.ext*") instructions.  By default memory loads are used to perform sign extension.
-msfimm Enable generation of compare and set flag with immediate ("l.sf*i") instructions.  By default extra instructions will be generated to store the immediate to a register first.
-mshftimm Enable generation of shift with immediate ("l.srai", "l.srli", "l.slli") instructions.  By default extra instructions will be generated to store the immediate to a register first.
PDP-11 Options
These options are defined for the PDP-11:
-mfpu Use hardware FPP floating point.  This is the default.  (FIS floating point on the PDP-11/40 is not supported.)  Implies -m45.
-msoft-float Do not use hardware floating point.
-mac0 Return floating-point results in ac0 (fr0 in Unix assembler syntax).
-mno-ac0 Return floating-point results in memory.  This is the default.
-m40 Generate code for a PDP-11/40.  Implies -msoft-float -mno-split.
-m45 Generate code for a PDP-11/45.  This is the default.
-m10 Generate code for a PDP-11/10.  Implies -msoft-float -mno-split.
-mint16 -mno-int32 Use 16-bit "int".  This is the default.
-mint32 -mno-int16 Use 32-bit "int".
-msplit Target has split instruction and data space.  Implies -m45.
-munix-asm Use Unix assembler syntax.
-mdec-asm Use DEC assembler syntax.
-mgnu-asm Use GNU assembler syntax.  This is the default.
-mlra Use the new LRA register allocator.  By default, the old "reload" allocator is used.
picoChip Options
These -m options are defined for picoChip implementations:
-mae=ae_type Set the instruction set, register set, and instruction scheduling parameters for array element type ae_type.  Supported values for ae_type are ANY, MUL, and MAC.
-mae=ANY selects a completely generic AE type.  Code generated with this option runs on any of the other AE types.  The code is not as efficient as it would be if compiled for a specific AE type, and some types of operation (e.g., multiplication) do not work properly on all types of AE.
-mae=MUL selects a MUL AE type.  This is the most useful AE type for compiled code, and is the default.
-mae=MAC selects a DSP-style MAC AE.  Code compiled with this option may suffer from poor performance of byte (char) manipulation, since the DSP AE does not provide hardware support for byte load/stores.
-msymbol-as-address Enable the compiler to directly use a symbol name as an address in a load/store instruction, without first loading it into a register. Typically, the use of this option generates larger programs, which run faster than when the option isn't used.  However, the results vary from program to program, so it is left as a user option, rather than being permanently enabled.
-mno-inefficient-warnings Disables warnings about the generation of inefficient code.  These warnings can be generated, for example, when compiling code that performs byte-level memory operations on the MAC AE type.  The MAC AE has no hardware support for byte-level memory operations, so all byte load/stores must be synthesized from word load/store operations. This is inefficient and a warning is generated to indicate that you should rewrite the code to avoid byte operations, or to target an AE type that has the necessary hardware support.  This option disables these warnings.
PowerPC Options
These are listed under
PRU Options
These command-line options are defined for PRU target:
-minrt Link with a minimum runtime environment, with no support for static initializers and constructors.  Using this option can significantly reduce the size of the final ELF binary.  Beware that the compiler could still generate code with static initializers and constructors. It is up to the programmer to ensure that the source program will not use those features.
-mmcu=mcu Specify the PRU MCU variant to use.  Check Newlib for the exact list of supported MCUs.
-mno-relax Make GCC pass the --no-relax command-line option to the linker instead of the --relax option.
-mloop Allow (or do not allow) GCC to use the LOOP instruction.
-mabi=variant Specify the ABI variant to output code for.  -mabi=ti selects the unmodified TI ABI while -mabi=gnu selects a GNU variant that copes more naturally with certain GCC assumptions.  These are the differences:
Function Pointer Size TI ABI specifies that function (code) pointers are 16-bit, whereas GNU supports only 32-bit data and code pointers.
Optional Return Value Pointer Function return values larger than 64 bits are passed by using a hidden pointer as the first argument of the function.  TI ABI, though, mandates that the pointer can be NULL in case the caller is not using the returned value.  GNU always passes and expects a valid return value pointer.
The current -mabi=ti implementation simply raises a compile error when any of the above code constructs is detected.  As a consequence the standard C library cannot be built and it is omitted when linking with -mabi=ti.
Relaxation is a GNU feature and for safety reasons is disabled when using -mabi=ti.  The TI toolchain does not emit relocations for QBBx instructions, so the GNU linker cannot adjust them when shortening adjacent LDI32 pseudo instructions.
RISC-V Options
These command-line options are defined for RISC-V targets:
-mbranch-cost=n Set the cost of branches to roughly n instructions.
-mplt -mno-plt When generating PIC code, do or don't allow the use of PLTs. Ignored for non-PIC.  The default is -mplt.
-mabi=ABI-string Specify integer and floating-point calling convention.  ABI-string contains two parts: the size of integer types and the registers used for floating-point types.  For example -march=rv64ifd -mabi=lp64d means that long and pointers are 64-bit (implicitly defining int to be 32-bit), and that floating-point values up to 64 bits wide are passed in F registers.  Contrast this with -march=rv64ifd -mabi=lp64f, which still allows the compiler to generate code that uses the F and D extensions but only allows floating-point values up to 32 bits long to be passed in registers; or -march=rv64ifd -mabi=lp64, in which no floating-point arguments will be passed in registers.
The default for this argument is system dependent, users who want a specific calling convention should specify one explicitly.  The valid calling conventions are: ilp32, ilp32f, ilp32d, lp64, lp64f, and lp64d.  Some calling conventions are impossible to implement on some ISAs: for example, -march=rv32if -mabi=ilp32d is invalid because the ABI requires 64-bit values be passed in F registers, but F registers are only 32 bits wide.  There is also the ilp32e ABI that can only be used with the rv32e architecture.  This ABI is not well specified at present, and is subject to change.