Repository: sigasi/SigasiProjectCreator

Issue:
Make tests compatible with python 3

Discussion:
coveralls: 
[![Coverage Status](https://coveralls.io/builds/31905399/badge)](https://coveralls.io/builds/31905399)

Coverage remained the same at 82.282% when pulling **bee11e9c0c44849e91097aaeb2644ff9fd1907ee on mderveeuw-si:master** into **0f21eaeda6cee85b4ee17427af00d11c48ae1c8f on sigasi:master**.

tivervac: Running the tests with python 3.8.3 (on mac) I get two warnings that seem suspicious:

```
SigasiProjectCreator on  master [?] via 🐍 v3.8.3 via C py38 ❯ ./test.sh
================================================================== test session starts ==================================================================
platform darwin -- Python 3.8.3, pytest-5.4.3, py-1.9.0, pluggy-0.13.1
rootdir: /Users/titouanvervack/git/SigasiProjectCreator, inifile: pytest.ini, testpaths: tests
plugins: forked-1.2.0, cov-2.10.0, xdist-1.32.0
collected 22 items

tests/ConvertCsvFileToLinksTest.py .                                                                                                              [  4%]
tests/ConvertCsvFileToTreeTest.py .                                                                                                               [  9%]
tests/CreateSigasiProjectFromListOfFilesTest.py .                                                                                                 [ 13%]
tests/LibraryMappingFileCreatorTest.py ...                                                                                                        [ 27%]
tests/ProjectFileCreatorTest.py .....                                                                                                             [ 50%]
tests/SettingsFileWriterTest.py .x..                                                                                                              [ 68%]
tests/SigasiProjectCreatorTest.py .......                                                                                                         [100%]

=================================================================== warnings summary ====================================================================
src/SigasiProjectCreator/Creator.py:173
  /Users/titouanvervack/git/SigasiProjectCreator/src/SigasiProjectCreator/Creator.py:173: DeprecationWarning: invalid escape sequence \.
    vl_ext = re.compile("\.sv[hi]?$|\.v[h]?$", re.IGNORECASE)

src/SigasiProjectCreator/Creator.py:177
  /Users/titouanvervack/git/SigasiProjectCreator/src/SigasiProjectCreator/Creator.py:177: DeprecationWarning: invalid escape sequence \.
    vhdl_ext = re.compile("\.vhd[l]?$", re.IGNORECASE)

-- Docs: https://docs.pytest.org/en/latest/warnings.html

---------- coverage: platform darwin, python 3.8.3-final-0 -----------
Coverage HTML written to dir htmlcov

======================================================= 21 passed, 1 xfailed, 2 warnings in 0.27s =======================================================
```
tivervac: I would also enable python 3.8 in the `.travis.yml`
tivervac: Opening pycharm with python 2.7 in convertHdpProjectToSigasiProject.py#L19
```
The SafeConfigParser class has been renamed to ConfigParser in Python 3.2. This alias will be removed in future versions. Use ConfigParser directly instead. 
```

Patch:
diff --git a/.travis.yml b/.travis.yml
index a137cbe..70d0f85 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,5 +1,7 @@
 language: python
-python: '2.7'
+python:
+  - '2.7'
+  - '3.8'
 install:
   - pip install -r requirements.txt
   - pip install --editable .
diff --git a/README.md b/README.md
index c4f532f..390ef61 100644
--- a/README.md
+++ b/README.md
@@ -11,3 +11,5 @@ See <http://insights.sigasi.com/manual/projectsetup.html> and <http://insights.s
 
 Run `test.sh` to run the tests.
 Files containing tests have to end in `Test`.
+
+The project and all tests run under both Python 2 and 3.
diff --git a/src/SigasiProjectCreator/ArgsAndFileParser.py b/src/SigasiProjectCreator/ArgsAndFileParser.py
index 070cdc0..14d8d7f 100644
--- a/src/SigasiProjectCreator/ArgsAndFileParser.py
+++ b/src/SigasiProjectCreator/ArgsAndFileParser.py
@@ -3,8 +3,8 @@
     :copyright: (c) 2008-2017 Sigasi
     :license: BSD, see LICENSE for more details.
 """
-from optparse import OptionParser
 import os
+from optparse import OptionParser
 
 
 class ArgsAndFileParser:
diff --git a/src/SigasiProjectCreator/ConverterHelper.py b/src/SigasiProjectCreator/ConverterHelper.py
index 9ae5027..5f72f99 100644
--- a/src/SigasiProjectCreator/ConverterHelper.py
+++ b/src/SigasiProjectCreator/ConverterHelper.py
@@ -6,8 +6,9 @@
 import os
 import platform
 import subprocess
-from SigasiProjectCreator import SigasiProjectCreator
-from ArgsAndFileParser import ArgsAndFileParser
+
+from SigasiProjectCreator.Creator import SigasiProjectCreator
+from SigasiProjectCreator.ArgsAndFileParser import ArgsAndFileParser
 
 
 def get_parts(pth):
diff --git a/src/SigasiProjectCreator/SigasiProjectCreator.py b/src/SigasiProjectCreator/Creator.py
similarity index 97%
rename from src/SigasiProjectCreator/SigasiProjectCreator.py
rename to src/SigasiProjectCreator/Creator.py
index 92e06c9..4f1d34b 100644
--- a/src/SigasiProjectCreator/SigasiProjectCreator.py
+++ b/src/SigasiProjectCreator/Creator.py
@@ -3,12 +3,14 @@
     :copyright: (c) 2008-2017 Sigasi
     :license: BSD, see LICENSE for more details.
 """
-from string import Template
-import VhdlVersion
-import VerilogVersion
 import os
 import re
-import SettingsFileWriter
+from string import Template
+
+from SigasiProjectCreator import VhdlVersion
+from SigasiProjectCreator import VerilogVersion
+from SigasiProjectCreator import SettingsFileWriter
+
 
 __VERSION_ERROR = Template('''Only ${versions} is/are allowed as ${lang} version number.''')
 
@@ -168,11 +170,11 @@ ${links}\t</linkedResources>
         self.__add_default_links()
 
     def is_verilog(self):
-        vl_ext = re.compile("\.sv[hi]?$|\.v[h]?$", re.IGNORECASE)
+        vl_ext = re.compile(r"\.sv[hi]?$|\.v[h]?$", re.IGNORECASE)
         return any([vl_ext.search(l[1]) for l in self.__links])
 
     def is_vhdl(self):
-        vhdl_ext = re.compile("\.vhd[l]?$", re.IGNORECASE)
+        vhdl_ext = re.compile(r"\.vhd[l]?$", re.IGNORECASE)
         # VHDL is the default
         return not self.is_verilog() or any([vhdl_ext.search(l[1]) for l in self.__links])
 
diff --git a/src/SigasiProjectCreator/SettingsFileWriter.py b/src/SigasiProjectCreator/SettingsFileWriter.py
index 29cf873..0ce0e01 100644
--- a/src/SigasiProjectCreator/SettingsFileWriter.py
+++ b/src/SigasiProjectCreator/SettingsFileWriter.py
@@ -3,5 +3,5 @@ import os
 
 def write(destination, name, content):
     library_mapping_file = os.path.abspath(os.path.join(destination, name))
-    with open(library_mapping_file, "w") as f:
-        f.write(content)
+    with open(library_mapping_file, "wb") as f:
+        f.write(content.encode())
diff --git a/src/SigasiProjectCreator/convertCsvFileToLinks.py b/src/SigasiProjectCreator/convertCsvFileToLinks.py
index 7b1daf9..8ae6906 100755
--- a/src/SigasiProjectCreator/convertCsvFileToLinks.py
+++ b/src/SigasiProjectCreator/convertCsvFileToLinks.py
@@ -5,10 +5,11 @@
     :license: BSD, see LICENSE for more details.
 """
 import os
-import CsvParser
-from SigasiProjectCreator import SigasiProjectCreator
-from ArgsAndFileParser import ArgsAndFileParser
-import VhdlVersion
+
+from SigasiProjectCreator.Creator import SigasiProjectCreator
+from SigasiProjectCreator.ArgsAndFileParser import ArgsAndFileParser
+from SigasiProjectCreator import CsvParser
+from SigasiProjectCreator import VhdlVersion
 
 
 def get_file_name(entry):
@@ -22,7 +23,7 @@ def main():
 
     creator = SigasiProjectCreator(project_name, VhdlVersion.NINETY_THREE)
 
-    for path, library in entries.iteritems():
+    for path, library in entries.items():
         file_name = get_file_name(path)
         link_type = os.path.isdir(path)
         creator.add_link(file_name, os.path.abspath(path), link_type)
diff --git a/src/SigasiProjectCreator/convertCsvFileToTree.py b/src/SigasiProjectCreator/convertCsvFileToTree.py
index 4332b6c..9355fab 100755
--- a/src/SigasiProjectCreator/convertCsvFileToTree.py
+++ b/src/SigasiProjectCreator/convertCsvFileToTree.py
@@ -4,8 +4,8 @@
     :copyright: (c) 2008-2017 Sigasi
     :license: BSD, see LICENSE for more details.
 """
-import CsvParser
-import ConverterHelper
+from SigasiProjectCreator import CsvParser
+from SigasiProjectCreator import ConverterHelper
 
 
 def main():
diff --git a/src/SigasiProjectCreator/convertHdpProjectToSigasiProject.py b/src/SigasiProjectCreator/convertHdpProjectToSigasiProject.py
old mode 100755
new mode 100644
index be970b3..0dbf08d
--- a/src/SigasiProjectCreator/convertHdpProjectToSigasiProject.py
+++ b/src/SigasiProjectCreator/convertHdpProjectToSigasiProject.py
@@ -4,8 +4,9 @@
     :copyright: (c) 2008-2017 Sigasi
     :license: BSD, see LICENSE for more details.
 """
-import ConfigParser
-import ConverterHelper
+from configparser import ConfigParser
+
+from SigasiProjectCreator import ConverterHelper
 
 usage = """usage: %prog project-name hdp-file [destination]
 
@@ -15,7 +16,7 @@ example: %prog MyProjectName myproject.hdp
 
 
 def parse_hdp_file(hdp_file):
-    config = ConfigParser.SafeConfigParser()
+    config = ConfigParser()
     config.read(hdp_file)
     entries = config.items("hdl")
     return {lib: path for path, lib in entries}
diff --git a/src/SigasiProjectCreator/convertXilinxISEToSigasiProject.py b/src/SigasiProjectCreator/convertXilinxISEToSigasiProject.py
index e091ff0..625931f 100644
--- a/src/SigasiProjectCreator/convertXilinxISEToSigasiProject.py
+++ b/src/SigasiProjectCreator/convertXilinxISEToSigasiProject.py
@@ -4,9 +4,10 @@
     :copyright: (c) 2008-2017 Sigasi
     :license: BSD, see LICENSE for more details.
 """
-import ConverterHelper
 import xml.etree.ElementTree as eT
 
+from SigasiProjectCreator import ConverterHelper
+
 usage = """usage: %prog project-name Xilinx-file [destination]
 
 destination is the current directory by default
diff --git a/src/SigasiProjectCreator/createSigasiProjectFromListOfFiles.py b/src/SigasiProjectCreator/createSigasiProjectFromListOfFiles.py
index 08ba678..a645376 100755
--- a/src/SigasiProjectCreator/createSigasiProjectFromListOfFiles.py
+++ b/src/SigasiProjectCreator/createSigasiProjectFromListOfFiles.py
@@ -5,9 +5,10 @@
     :license: BSD, see LICENSE for more details.
 """
 import os
-from ArgsAndFileParser import ArgsAndFileParser
-from SigasiProjectCreator import SigasiProjectCreator
-import VhdlVersion
+
+from SigasiProjectCreator.ArgsAndFileParser import ArgsAndFileParser
+from SigasiProjectCreator.Creator import SigasiProjectCreator
+from SigasiProjectCreator import VhdlVersion
 
 usage = """usage: %prog project-name hdl-file hdl-file...
 


Test patch:
diff --git a/tests/CreateSigasiProjectFromListOfFilesTest.py b/tests/CreateSigasiProjectFromListOfFilesTest.py
index 390296e..0477238 100644
--- a/tests/CreateSigasiProjectFromListOfFilesTest.py
+++ b/tests/CreateSigasiProjectFromListOfFilesTest.py
@@ -34,3 +34,4 @@ class CreateSigasiProjectFromListOfFilesTest(unittest.TestCase):
         sigasiProjectCreator.main()
         result = filecmp.dircmp(list_dir, self.temp_dir)
         self.assertTrue(not result.report())
+        os.chdir(wd)
diff --git a/tests/LibraryMappingFileCreatorTest.py b/tests/LibraryMappingFileCreatorTest.py
index 4efb64e..475c3e8 100644
--- a/tests/LibraryMappingFileCreatorTest.py
+++ b/tests/LibraryMappingFileCreatorTest.py
@@ -5,7 +5,7 @@
 """
 import unittest
 
-from SigasiProjectCreator.SigasiProjectCreator import LibraryMappingFileCreator
+from SigasiProjectCreator.Creator import LibraryMappingFileCreator
 from string import Template
 
 
diff --git a/tests/ProjectFileCreatorTest.py b/tests/ProjectFileCreatorTest.py
index 17b8c87..8d9cf76 100644
--- a/tests/ProjectFileCreatorTest.py
+++ b/tests/ProjectFileCreatorTest.py
@@ -5,7 +5,7 @@
 """
 import unittest
 
-from SigasiProjectCreator.SigasiProjectCreator import ProjectFileCreator
+from SigasiProjectCreator.Creator import ProjectFileCreator
 from string import Template
 
 test_template = Template('''<?xml version="1.0" encoding="UTF-8"?>
diff --git a/tests/SettingsFileWriterTest.py b/tests/SettingsFileWriterTest.py
index 7486a92..72d331a 100644
--- a/tests/SettingsFileWriterTest.py
+++ b/tests/SettingsFileWriterTest.py
@@ -61,4 +61,4 @@ class SettingsFileWriterTest(unittest.TestCase):
         self.assertTrue(os.path.isfile(path))
         with open(path, 'rb') as f:
             read = f.read(content.__len__())
-            self.assertEqual(content, read)
+            self.assertEqual(content, read.decode('utf-8'))
diff --git a/tests/SigasiProjectCreatorTest.py b/tests/SigasiProjectCreatorTest.py
index 367aabc..0e3fcaa 100644
--- a/tests/SigasiProjectCreatorTest.py
+++ b/tests/SigasiProjectCreatorTest.py
@@ -5,10 +5,10 @@
 """
 import unittest
 
-import SigasiProjectCreator.SigasiProjectCreator as sPC
+import SigasiProjectCreator.Creator as sPC
 import SigasiProjectCreator.VerilogVersion as VerilogVersion
 import SigasiProjectCreator.VhdlVersion as VhdlVersion
-from SigasiProjectCreator.SigasiProjectCreator import SigasiProjectCreator
+from SigasiProjectCreator.Creator import SigasiProjectCreator
 
 
 class SigasiProjectCreatorTest(unittest.TestCase):
@@ -21,7 +21,7 @@ class SigasiProjectCreatorTest(unittest.TestCase):
             sPC.check_hdl_versions(None, None)
         self.assertTrue(
             '''Only 93, 2002, 2008 is/are allowed as VHDL version number.
-Only v2005 is/are allowed as Verilog version number.''' in exc.exception)
+Only v2005 is/are allowed as Verilog version number.''' == str(exc.exception))
 
     def test_check_hdl_versions_vhdl_none(self):
         sPC.check_hdl_versions(None, VerilogVersion.TWENTY_O_FIVE)
@@ -35,16 +35,16 @@ Only v2005 is/are allowed as Verilog version number.''' in exc.exception)
     def test_check_hdl_versions_vhdl_wrong(self):
         with self.assertRaises(ValueError) as exc:
             sPC.check_hdl_versions(VerilogVersion.TWENTY_O_FIVE, VerilogVersion.TWENTY_O_FIVE)
-        self.assertTrue("Only 93, 2002, 2008 is/are allowed as VHDL version number." in exc.exception)
+        self.assertTrue("Only 93, 2002, 2008 is/are allowed as VHDL version number." == str(exc.exception))
 
     def test_check_hdl_versions_verilog_wrong(self):
         with self.assertRaises(ValueError) as exc:
             sPC.check_hdl_versions(VhdlVersion.NINETY_THREE, VhdlVersion.NINETY_THREE)
-        self.assertTrue("Only v2005 is/are allowed as Verilog version number." in exc.exception)
+        self.assertTrue("Only v2005 is/are allowed as Verilog version number." == str(exc.exception))
 
     def test_check_hdl_versions_both_wrong(self):
         with self.assertRaises(ValueError) as exc:
             sPC.check_hdl_versions(VerilogVersion.TWENTY_O_FIVE, VhdlVersion.NINETY_THREE)
         self.assertTrue(
             '''Only 93, 2002, 2008 is/are allowed as VHDL version number.
-Only v2005 is/are allowed as Verilog version number.''' in exc.exception)
+Only v2005 is/are allowed as Verilog version number.''' == str(exc.exception))