Repository: chipsalliance/caliptra-sw
Pull request #475 (2023-07-14 18:58:52)

Updated hw-latest/caliptra-rtl to e40aae85b50bd54a732c65da1d8aa49c98d46369
Removed caliptra-rtl-fpga.


Patch:
diff --git a/.gitignore b/.gitignore
index b363a6fa..8f80cd58 100644
--- a/.gitignore
+++ b/.gitignore
@@ -13,4 +13,11 @@
 
 # Files created by tests
 rom/dev/caliptra_idevid_csr.der
-rom/dev/caliptra_ldevid_cert.der
\ No newline at end of file
+rom/dev/caliptra_ldevid_cert.der
+
+# Files created by FPGA build
+hw-latest/fpga/.Xil/
+hw-latest/fpga/caliptra_build/
+hw-latest/fpga/build_fpga.log
+hw-latest/fpga/vivado*.jou
+hw-latest/fpga/vivado*.log
diff --git a/.gitmodules b/.gitmodules
index c754031e..aad4ce9b 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -9,6 +9,3 @@
 	path = runtime/dpe
 	url = https://github.com/chipsalliance/caliptra-dpe.git
 	branch = main
-[submodule "hw-latest/caliptra-rtl-fpga"]
-	path = hw-latest/caliptra-rtl-fpga
-	url = https://github.com/chipsalliance/caliptra-rtl
diff --git a/drivers/src/soc_ifc.rs b/drivers/src/soc_ifc.rs
index 5ce7e5b5..541d8105 100644
--- a/drivers/src/soc_ifc.rs
+++ b/drivers/src/soc_ifc.rs
@@ -79,7 +79,7 @@ impl SocIfc {
     /// * None
     pub fn flow_status_set_idevid_csr_ready(&mut self) {
         let soc_ifc = self.soc_ifc.regs_mut();
-        soc_ifc.cptra_flow_status().write(|w| w.status(0x0800_0000));
+        soc_ifc.cptra_flow_status().write(|w| w.status(0x0100_0000));
     }
 
     /// Set ready for firmware
diff --git a/hw-model/src/lib.rs b/hw-model/src/lib.rs
index 5833fc6c..9727ecfb 100644
--- a/hw-model/src/lib.rs
+++ b/hw-model/src/lib.rs
@@ -785,6 +785,7 @@ mod tests {
     #[test]
     fn test_apb() {
         let mut model = caliptra_hw_model::new_unbooted(InitParams {
+            rom: &gen_image_hi(),
             ..Default::default()
         })
         .unwrap();
@@ -816,6 +817,7 @@ mod tests {
     fn test_mbox() {
         // Same as test_apb, but uses higher-level register interface
         let mut model = caliptra_hw_model::new_unbooted(InitParams {
+            rom: &gen_image_hi(),
             ..Default::default()
         })
         .unwrap();
@@ -834,6 +836,7 @@ mod tests {
     /// Violate the mailbox protocol by having the sender trying to write to mailbox in execute state.
     fn test_mbox_negative() {
         let mut model = caliptra_hw_model::new_unbooted(InitParams {
+            rom: &gen_image_hi(),
             ..Default::default()
         })
         .unwrap();
diff --git a/registers/src/csrng.rs b/registers/src/csrng.rs
index e9005552..18e90d14 100644
--- a/registers/src/csrng.rs
+++ b/registers/src/csrng.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/doe.rs b/registers/src/doe.rs
index c56936f6..53bf969a 100644
--- a/registers/src/doe.rs
+++ b/registers/src/doe.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/dv.rs b/registers/src/dv.rs
index 357d2928..bec7f1c0 100644
--- a/registers/src/dv.rs
+++ b/registers/src/dv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/ecc.rs b/registers/src/ecc.rs
index 16d52774..9951489a 100644
--- a/registers/src/ecc.rs
+++ b/registers/src/ecc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/entropy_src.rs b/registers/src/entropy_src.rs
index 07390846..48a27062 100644
--- a/registers/src/entropy_src.rs
+++ b/registers/src/entropy_src.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/hmac.rs b/registers/src/hmac.rs
index ddab1ef0..b933285e 100644
--- a/registers/src/hmac.rs
+++ b/registers/src/hmac.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/kv.rs b/registers/src/kv.rs
index c7b12874..15eb2e67 100644
--- a/registers/src/kv.rs
+++ b/registers/src/kv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/lib.rs b/registers/src/lib.rs
index d2e0544a..0356304a 100644
--- a/registers/src/lib.rs
+++ b/registers/src/lib.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![no_std]
 #![allow(clippy::erasing_op)]
diff --git a/registers/src/mbox.rs b/registers/src/mbox.rs
index bb989b3d..64a9db10 100644
--- a/registers/src/mbox.rs
+++ b/registers/src/mbox.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/pv.rs b/registers/src/pv.rs
index f16a5db2..176eaeea 100644
--- a/registers/src/pv.rs
+++ b/registers/src/pv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/sha256.rs b/registers/src/sha256.rs
index c161e109..90bb4aab 100644
--- a/registers/src/sha256.rs
+++ b/registers/src/sha256.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/sha512.rs b/registers/src/sha512.rs
index ee351e42..b15c085f 100644
--- a/registers/src/sha512.rs
+++ b/registers/src/sha512.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -222,9 +222,11 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ///
     /// Read value: [`u32`]; Write value: [`u32`]
     #[inline(always)]
-    pub fn gen_pcr_hash_nonce(&self) -> ureg::RegRef<crate::sha512::meta::GenPcrHashNonce, &TMmio> {
+    pub fn gen_pcr_hash_nonce(
+        &self,
+    ) -> ureg::Array<8, ureg::RegRef<crate::sha512::meta::GenPcrHashNonce, &TMmio>> {
         unsafe {
-            ureg::RegRef::new_with_mmio(
+            ureg::Array::new_with_mmio(
                 self.ptr.wrapping_add(0x610 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
@@ -237,7 +239,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     pub fn gen_pcr_hash_ctrl(&self) -> ureg::RegRef<crate::sha512::meta::GenPcrHashCtrl, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x614 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x630 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -251,7 +253,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ) -> ureg::RegRef<crate::sha512::meta::GenPcrHashStatus, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x618 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x634 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -265,7 +267,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ) -> ureg::Array<12, ureg::RegRef<crate::sha512::meta::GenPcrHashDigest, &TMmio>> {
         unsafe {
             ureg::Array::new_with_mmio(
-                self.ptr.wrapping_add(0x61c / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x638 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
diff --git a/registers/src/sha512_acc.rs b/registers/src/sha512_acc.rs
index 12b3b6a4..d7e9d606 100644
--- a/registers/src/sha512_acc.rs
+++ b/registers/src/sha512_acc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/soc_ifc.rs b/registers/src/soc_ifc.rs
index b6730ff2..569cce56 100644
--- a/registers/src/soc_ifc.rs
+++ b/registers/src/soc_ifc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -1414,12 +1414,28 @@ impl<TMmio: ureg::Mmio> IntrBlockRfBlock<TMmio> {
     ///
     /// Read value: [`u32`]; Write value: [`u32`]
     #[inline(always)]
+    pub fn notif_scan_mode_intr_count_r(
+        &self,
+    ) -> ureg::RegRef<crate::soc_ifc::meta::IntrBlockRfNotifScanModeIntrCountR, &TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x18c / core::mem::size_of::<u32>()),
+                core::borrow::Borrow::borrow(&self.mmio),
+            )
+        }
+    }
+    /// Provides statistics about the number of events that have
+    /// occurred.
+    /// Will not overflow ('incrsaturate').
+    ///
+    /// Read value: [`u32`]; Write value: [`u32`]
+    #[inline(always)]
     pub fn notif_soc_req_lock_intr_count_r(
         &self,
     ) -> ureg::RegRef<crate::soc_ifc::meta::IntrBlockRfNotifSocReqLockIntrCountR, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x18c / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x190 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -1435,7 +1451,7 @@ impl<TMmio: ureg::Mmio> IntrBlockRfBlock<TMmio> {
     ) -> ureg::RegRef<crate::soc_ifc::meta::IntrBlockRfNotifGenInToggleIntrCountR, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x190 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x194 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -1684,12 +1700,33 @@ impl<TMmio: ureg::Mmio> IntrBlockRfBlock<TMmio> {
     ///
     /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`]
     #[inline(always)]
+    pub fn notif_scan_mode_intr_count_incr_r(
+        &self,
+    ) -> ureg::RegRef<crate::soc_ifc::meta::IntrBlockRfNotifScanModeIntrCountIncrR, &TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x22c / core::mem::size_of::<u32>()),
+                core::borrow::Borrow::borrow(&self.mmio),
+            )
+        }
+    }
+    /// Trigger the event counter to increment based on observing
+    /// the rising edge of an interrupt event input from the
+    /// Hardware. The same input signal that causes an interrupt
+    /// event to be set (sticky) also causes this signal to pulse
+    /// for 1 clock cycle, resulting in the event counter
+    /// incrementing by 1 for every interrupt event.
+    /// This is implemented as a down-counter (1-bit) that will
+    /// decrement immediately on being set - resulting in a pulse
+    ///
+    /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`]
+    #[inline(always)]
     pub fn notif_soc_req_lock_intr_count_incr_r(
         &self,
     ) -> ureg::RegRef<crate::soc_ifc::meta::IntrBlockRfNotifSocReqLockIntrCountIncrR, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x22c / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x230 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -1710,7 +1747,7 @@ impl<TMmio: ureg::Mmio> IntrBlockRfBlock<TMmio> {
     ) -> ureg::RegRef<crate::soc_ifc::meta::IntrBlockRfNotifGenInToggleIntrCountIncrR, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x230 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x234 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -1818,7 +1855,12 @@ pub mod regs {
         ///
         #[inline(always)]
         pub fn status(&self) -> u32 {
-            (self.0 >> 0) & 0xfffffff
+            (self.0 >> 0) & 0x1ffffff
+        }
+        /// Boot FSM State
+        #[inline(always)]
+        pub fn boot_fsm_ps(&self) -> u32 {
+            (self.0 >> 25) & 7
         }
         /// Indicates Caliptra is ready for Firmware Download
         #[inline(always)]
@@ -1865,7 +1907,7 @@ pub mod regs {
         ///
         #[inline(always)]
         pub fn status(self, val: u32) -> Self {
-            Self((self.0 & !(0xfffffff << 0)) | ((val & 0xfffffff) << 0))
+            Self((self.0 & !(0x1ffffff << 0)) | ((val & 0x1ffffff) << 0))
         }
         /// Indicates Caliptra is ready for Firmware Download
         #[inline(always)]
@@ -1996,11 +2038,6 @@ pub mod regs {
         pub fn nmi_pin(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
-        ///
-        #[inline(always)]
-        pub fn rsvd(&self) -> u32 {
-            (self.0 >> 3) & 0x1fffffff
-        }
         /// Construct a WriteVal that can be used to modify the contents of this register value.
         #[inline(always)]
         pub fn modify(self) -> CptraHwErrorFatalWriteVal {
@@ -2037,11 +2074,6 @@ pub mod regs {
         pub fn nmi_pin(self, val: bool) -> Self {
             Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
         }
-        ///
-        #[inline(always)]
-        pub fn rsvd(self, val: u32) -> Self {
-            Self((self.0 & !(0x1fffffff << 3)) | ((val & 0x1fffffff) << 3))
-        }
     }
     impl From<u32> for CptraHwErrorFatalWriteVal {
         #[inline(always)]
@@ -2073,11 +2105,6 @@ pub mod regs {
         pub fn mbox_ecc_unc(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
-        ///
-        #[inline(always)]
-        pub fn rsvd(&self) -> u32 {
-            (self.0 >> 3) & 0x1fffffff
-        }
         /// Construct a WriteVal that can be used to modify the contents of this register value.
         #[inline(always)]
         pub fn modify(self) -> CptraHwErrorNonFatalWriteVal {
@@ -2114,11 +2141,6 @@ pub mod regs {
         pub fn mbox_ecc_unc(self, val: bool) -> Self {
             Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
         }
-        ///
-        #[inline(always)]
-        pub fn rsvd(self, val: u32) -> Self {
-            Self((self.0 & !(0x1fffffff << 3)) | ((val & 0x1fffffff) << 3))
-        }
     }
     impl From<u32> for CptraHwErrorNonFatalWriteVal {
         #[inline(always)]
@@ -3138,11 +3160,6 @@ pub mod regs {
         pub fn mask_nmi_pin(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
-        ///
-        #[inline(always)]
-        pub fn mask_rsvd(&self) -> u32 {
-            (self.0 >> 3) & 0x1fffffff
-        }
         /// Construct a WriteVal that can be used to modify the contents of this register value.
         #[inline(always)]
         pub fn modify(self) -> InternalHwErrorFatalMaskWriteVal {
@@ -3179,11 +3196,6 @@ pub mod regs {
         pub fn mask_nmi_pin(self, val: bool) -> Self {
             Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
         }
-        ///
-        #[inline(always)]
-        pub fn mask_rsvd(self, val: u32) -> Self {
-            Self((self.0 & !(0x1fffffff << 3)) | ((val & 0x1fffffff) << 3))
-        }
     }
     impl From<u32> for InternalHwErrorFatalMaskWriteVal {
         #[inline(always)]
@@ -3215,11 +3227,6 @@ pub mod regs {
         pub fn mask_mbox_ecc_unc(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
-        ///
-        #[inline(always)]
-        pub fn mask_rsvd(&self) -> u32 {
-            (self.0 >> 3) & 0x1fffffff
-        }
         /// Construct a WriteVal that can be used to modify the contents of this register value.
         #[inline(always)]
         pub fn modify(self) -> InternalHwErrorNonFatalMaskWriteVal {
@@ -3256,11 +3263,6 @@ pub mod regs {
         pub fn mask_mbox_ecc_unc(self, val: bool) -> Self {
             Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
         }
-        ///
-        #[inline(always)]
-        pub fn mask_rsvd(self, val: u32) -> Self {
-            Self((self.0 & !(0x1fffffff << 3)) | ((val & 0x1fffffff) << 3))
-        }
     }
     impl From<u32> for InternalHwErrorNonFatalMaskWriteVal {
         #[inline(always)]
@@ -3339,15 +3341,20 @@ pub mod regs {
         pub fn notif_debug_locked_en(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
+        /// Enable bit for Scan mode
+        #[inline(always)]
+        pub fn notif_scan_mode_en(&self) -> bool {
+            ((self.0 >> 3) & 1) != 0
+        }
         /// Enable bit for SoC requested the mailbox while locked
         #[inline(always)]
         pub fn notif_soc_req_lock_en(&self) -> bool {
-            ((self.0 >> 3) & 1) != 0
+            ((self.0 >> 4) & 1) != 0
         }
         /// Enable bit for Generic Input Wires Toggle
         #[inline(always)]
         pub fn notif_gen_in_toggle_en(&self) -> bool {
-            ((self.0 >> 4) & 1) != 0
+            ((self.0 >> 5) & 1) != 0
         }
         /// Construct a WriteVal that can be used to modify the contents of this register value.
         #[inline(always)]
@@ -3385,15 +3392,20 @@ pub mod regs {
         pub fn notif_debug_locked_en(self, val: bool) -> Self {
             Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
         }
+        /// Enable bit for Scan mode
+        #[inline(always)]
+        pub fn notif_scan_mode_en(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        }
         /// Enable bit for SoC requested the mailbox while locked
         #[inline(always)]
         pub fn notif_soc_req_lock_en(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
         }
         /// Enable bit for Generic Input Wires Toggle
         #[inline(always)]
         pub fn notif_gen_in_toggle_en(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
         }
     }
     impl From<u32> for NotifIntrEnTWriteVal {
@@ -3426,15 +3438,20 @@ pub mod regs {
         pub fn notif_debug_locked_sts(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
+        /// Scan mode status bit
+        #[inline(always)]
+        pub fn notif_scan_mode_sts(&self) -> bool {
+            ((self.0 >> 3) & 1) != 0
+        }
         /// SoC requested the mailbox while locked status bit
         #[inline(always)]
         pub fn notif_soc_req_lock_sts(&self) -> bool {
-            ((self.0 >> 3) & 1) != 0
+            ((self.0 >> 4) & 1) != 0
         }
         /// Generic Input Wires Toggle status bit
         #[inline(always)]
         pub fn notif_gen_in_toggle_sts(&self) -> bool {
-            ((self.0 >> 4) & 1) != 0
+            ((self.0 >> 5) & 1) != 0
         }
         /// Construct a WriteVal that can be used to modify the contents of this register value.
         #[inline(always)]
@@ -3472,15 +3489,20 @@ pub mod regs {
         pub fn notif_debug_locked_sts(self, val: bool) -> Self {
             Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
         }
+        /// Scan mode status bit
+        #[inline(always)]
+        pub fn notif_scan_mode_sts(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        }
         /// SoC requested the mailbox while locked status bit
         #[inline(always)]
         pub fn notif_soc_req_lock_sts(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
         }
         /// Generic Input Wires Toggle status bit
         #[inline(always)]
         pub fn notif_gen_in_toggle_sts(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
         }
     }
     impl From<u32> for NotifIntrTWriteVal {
@@ -3513,15 +3535,20 @@ pub mod regs {
         pub fn notif_debug_locked_trig(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
+        /// Scan mode trigger bit
+        #[inline(always)]
+        pub fn notif_scan_mode_trig(&self) -> bool {
+            ((self.0 >> 3) & 1) != 0
+        }
         /// SoC requested the mailbox while locked trigger bit
         #[inline(always)]
         pub fn notif_soc_req_lock_trig(&self) -> bool {
-            ((self.0 >> 3) & 1) != 0
+            ((self.0 >> 4) & 1) != 0
         }
         /// Generic Input Wires Toggle trigger bit
         #[inline(always)]
         pub fn notif_gen_in_toggle_trig(&self) -> bool {
-            ((self.0 >> 4) & 1) != 0
+            ((self.0 >> 5) & 1) != 0
         }
         /// Construct a WriteVal that can be used to modify the contents of this register value.
         #[inline(always)]
@@ -3559,15 +3586,20 @@ pub mod regs {
         pub fn notif_debug_locked_trig(self, val: bool) -> Self {
             Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
         }
+        /// Scan mode trigger bit
+        #[inline(always)]
+        pub fn notif_scan_mode_trig(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        }
         /// SoC requested the mailbox while locked trigger bit
         #[inline(always)]
         pub fn notif_soc_req_lock_trig(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
         }
         /// Generic Input Wires Toggle trigger bit
         #[inline(always)]
         pub fn notif_gen_in_toggle_trig(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
         }
     }
     impl From<u32> for NotifIntrTrigTWriteVal {
@@ -3846,6 +3878,7 @@ pub mod meta {
     pub type IntrBlockRfNotifCmdAvailIntrCountR = ureg::ReadWriteReg32<0, u32, u32>;
     pub type IntrBlockRfNotifMboxEccCorIntrCountR = ureg::ReadWriteReg32<0, u32, u32>;
     pub type IntrBlockRfNotifDebugLockedIntrCountR = ureg::ReadWriteReg32<0, u32, u32>;
+    pub type IntrBlockRfNotifScanModeIntrCountR = ureg::ReadWriteReg32<0, u32, u32>;
     pub type IntrBlockRfNotifSocReqLockIntrCountR = ureg::ReadWriteReg32<0, u32, u32>;
     pub type IntrBlockRfNotifGenInToggleIntrCountR = ureg::ReadWriteReg32<0, u32, u32>;
     pub type IntrBlockRfErrorInternalIntrCountIncrR =
@@ -3870,6 +3903,8 @@ pub mod meta {
         ureg::ReadOnlyReg32<crate::sha512_acc::regs::IntrCountIncrTReadVal>;
     pub type IntrBlockRfNotifDebugLockedIntrCountIncrR =
         ureg::ReadOnlyReg32<crate::sha512_acc::regs::IntrCountIncrTReadVal>;
+    pub type IntrBlockRfNotifScanModeIntrCountIncrR =
+        ureg::ReadOnlyReg32<crate::sha512_acc::regs::IntrCountIncrTReadVal>;
     pub type IntrBlockRfNotifSocReqLockIntrCountIncrR =
         ureg::ReadOnlyReg32<crate::sha512_acc::regs::IntrCountIncrTReadVal>;
     pub type IntrBlockRfNotifGenInToggleIntrCountIncrR =
diff --git a/registers/src/soc_ifc_trng.rs b/registers/src/soc_ifc_trng.rs
index 6978b00e..06f05f68 100644
--- a/registers/src/soc_ifc_trng.rs
+++ b/registers/src/soc_ifc_trng.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/spi_host.rs b/registers/src/spi_host.rs
index 9b11354b..ed5aa29c 100644
--- a/registers/src/spi_host.rs
+++ b/registers/src/spi_host.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/registers/src/uart.rs b/registers/src/uart.rs
index 1ee8c2e6..85c8a6ef 100644
--- a/registers/src/uart.rs
+++ b/registers/src/uart.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+// generated by caliptra_registers_generator with caliptra-rtl repo at e40aae85b50bd54a732c65da1d8aa49c98d46369
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/sw-emulator/lib/periph/src/soc_reg.rs b/sw-emulator/lib/periph/src/soc_reg.rs
index 8ac15dfd..bfecc876 100644
--- a/sw-emulator/lib/periph/src/soc_reg.rs
+++ b/sw-emulator/lib/periph/src/soc_reg.rs
@@ -108,9 +108,10 @@ register_bitfields! [
 
     /// Flow Status
     FlowStatus [
-        STATUS OFFSET(0) NUMBITS(26) [],
-        LDEVID_CERT_READY OFFSET(26) NUMBITS(1) [],
-        IDEVID_CSR_READY OFFSET(27) NUMBITS(1) [],
+        STATUS OFFSET(0) NUMBITS(23) [],
+        LDEVID_CERT_READY OFFSET(23) NUMBITS(1) [],
+        IDEVID_CSR_READY OFFSET(24) NUMBITS(1) [],
+        BOOT_FSM_PS OFFSET(25) NUMBITS(3) [],
         READY_FOR_FW OFFSET(28) NUMBITS(1) [],
         READY_FOR_RT OFFSET(29) NUMBITS(1) [],
         READY_FOR_FUSES OFFSET(30) NUMBITS(1) [],


Test patch:
diff --git a/drivers/test-fw/src/bin/status_reporter_tests.rs b/drivers/test-fw/src/bin/status_reporter_tests.rs
index c8f759ea..6940dbdb 100644
--- a/drivers/test-fw/src/bin/status_reporter_tests.rs
+++ b/drivers/test-fw/src/bin/status_reporter_tests.rs
@@ -36,7 +36,7 @@ fn test_report_idevid_csr_ready() {
     SocIfc::new(soc_ifc).flow_status_set_idevid_csr_ready();
     let soc_ifc = unsafe { SocIfcReg::new() };
     assert_eq!(
-        0x0800_0000,
+        0x0100_0000,
         soc_ifc.regs().cptra_flow_status().read().status()
     );
 }
diff --git a/hw-latest/caliptra-rtl b/hw-latest/caliptra-rtl
index 61fb5bd9..e40aae85 160000
--- a/hw-latest/caliptra-rtl
+++ b/hw-latest/caliptra-rtl
@@ -1,1 +1,1 @@
-Subproject commit 61fb5bd9eff399947f6e8621bdb1de03ff06e1b8
+Subproject commit e40aae85b50bd54a732c65da1d8aa49c98d46369
diff --git a/hw-latest/caliptra-rtl-fpga b/hw-latest/caliptra-rtl-fpga
deleted file mode 160000
index d334c84a..00000000
--- a/hw-latest/caliptra-rtl-fpga
+++ /dev/null
@@ -1,1 +0,0 @@
-Subproject commit d334c84a0e513a3d66a51078f020a414a2c86a67
diff --git a/hw-latest/fpga/fpga_configuration.tcl b/hw-latest/fpga/fpga_configuration.tcl
index ddf6f499..e2780172 100644
--- a/hw-latest/fpga/fpga_configuration.tcl
+++ b/hw-latest/fpga/fpga_configuration.tcl
@@ -6,7 +6,7 @@ file mkdir $outputDir
 file mkdir $packageDir
 
 # Path to rtl
-set rtlDir ../caliptra-rtl-fpga
+set rtlDir ../caliptra-rtl
 
 # Simplistic processing of command line arguments to enable different features
 # Defaults:
@@ -101,9 +101,6 @@ remove_files [ glob $rtlDir/src/ecc/rtl/ecc_ram_tdp_file.sv ]
 # Key Vault is very large. Replacing KV with a version with the minimum number of entries.
 remove_files [ glob $rtlDir/src/keyvault/rtl/kv_reg.sv ]
 
-# Add ICCM/DCCM definitions from testbench
-add_files [ glob $rtlDir/src/integration/tb/caliptra_veer_sram_export.sv ]
-
 # Add FPGA specific sources
 add_files [ glob ./src/*.sv]
 add_files [ glob ./src/*.v]
@@ -111,10 +108,6 @@ add_files [ glob ./src/*.v]
 # Mark all Verilog sources as SystemVerilog because some of them have SystemVerilog syntax.
 set_property file_type SystemVerilog [get_files *.v]
 
-# sha512_param.sv is actually a header that gets included. Issue #38.
-# Error without this: "Cannot open include file 'sha512_param.sv"
-set_property file_type {Verilog Header} [get_files  $rtlDir/src/sha512/rtl/sha512_param.sv]
-
 # Exception: caliptra_package_top.v needs to be Verilog to be included in a Block Diagram.
 set_property file_type Verilog [get_files  ./src/caliptra_package_top.v]
 
@@ -264,5 +257,5 @@ if {$BUILD} {
   launch_runs impl_1 -jobs 10
   wait_on_runs impl_1
   open_run impl_1
-  write_bitstream -bin_file /tmp/caliptra_fpga
+  write_bitstream -bin_file $outputDir/caliptra_fpga
 }
diff --git a/hw-latest/fpga/src/caliptra_veer_sram_export.sv b/hw-latest/fpga/src/caliptra_veer_sram_export.sv
new file mode 100644
index 00000000..c1ea5dd4
--- /dev/null
+++ b/hw-latest/fpga/src/caliptra_veer_sram_export.sv
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+import el2_pkg::*;
+module caliptra_veer_sram_export #(
+    `include "el2_param.vh"
+) (
+    el2_mem_if.top el2_mem_export
+);
+
+
+//////////////////////////////////////////////////////
+// DCCM
+//
+if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
+`define EL2_LOCAL_DCCM_RAM_TEST_PORTS    .TEST1   (1'b0   ), \
+                                         .RME     (1'b0   ), \
+                                         .RM      (4'b0000), \
+                                         .LS      (1'b0   ), \
+                                         .DS      (1'b0   ), \
+                                         .SD      (1'b0   ), \
+                                         .TEST_RNM(1'b0   ), \
+                                         .BC1     (1'b0   ), \
+                                         .BC2     (1'b0   ), \
+
+localparam DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS));  // Depth of memory bank
+// 8 Banks, 16KB each (2048 x 72)
+for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
+`ifdef VERILATOR
+
+        el2_ram #(DCCM_INDEX_DEPTH,39)  ram (
+                                  // Primary ports
+                                  .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                  .CLK (el2_mem_export.clk                                            ),
+                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                  .ROP (                                                              ),
+                                  // These are used by SoC
+                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                  .*
+                                  );
+`else
+
+      if (DCCM_INDEX_DEPTH == 32768) begin : dccm
+         ram_32768x39  dccm_bank (
+                                  // Primary ports
+                                  .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                  .CLK (el2_mem_export.clk                                            ),
+                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                  .ROP (                                                              ),
+                                  // These are used by SoC
+                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                  .*
+                                  );
+      end
+      else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
+         ram_16384x39  dccm_bank (
+                                  // Primary ports
+                                  .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                  .CLK (el2_mem_export.clk                                            ),
+                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                  .ROP (                                                              ),
+                                  // These are used by SoC
+                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                  .*
+                                  );
+      end
+      else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
+         ram_8192x39  dccm_bank (
+                                 // Primary ports
+                                 .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                 .CLK (el2_mem_export.clk                                            ),
+                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .ROP (                                                              ),
+                                 // These are used by SoC
+                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                 .*
+                                 );
+      end
+      else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
+         ram_4096x39  dccm_bank (
+                                 // Primary ports
+                                 .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                 .CLK (el2_mem_export.clk                                            ),
+                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .ROP (                                                              ),
+                                 // These are used by SoC
+                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                 .*
+                                 );
+      end
+      else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
+         ram_3072x39  dccm_bank (
+                                 // Primary ports
+                                 .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                 .CLK (el2_mem_export.clk                                            ),
+                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .ROP (                                                              ),
+                                 // These are used by SoC
+                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                 .*
+                                 );
+      end
+      else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
+         ram_2048x39  dccm_bank (
+                                 // Primary ports
+                                 .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                 .CLK (el2_mem_export.clk                                            ),
+                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .ROP (                                                              ),
+                                 // These are used by SoC
+                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                 .*
+                                 );
+      end
+      else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
+         ram_1024x39  dccm_bank (
+                                 // Primary ports
+                                 .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                 .CLK (el2_mem_export.clk                                            ),
+                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .ROP (                                                              ),
+                                 // These are used by SoC
+                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                 .*
+                                 );
+      end
+      else if (DCCM_INDEX_DEPTH == 512) begin : dccm
+         ram_512x39  dccm_bank (
+                                // Primary ports
+                                .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                .CLK (el2_mem_export.clk                                            ),
+                                .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                .ROP (                                                              ),
+                                // These are used by SoC
+                                `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                .*
+                                );
+      end
+      else if (DCCM_INDEX_DEPTH == 256) begin : dccm
+         ram_256x39  dccm_bank (
+                                // Primary ports
+                                .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                .CLK (el2_mem_export.clk                                            ),
+                                .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                .ROP (                                                              ),
+                                // These are used by SoC
+                                `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                .*
+                                );
+      end
+      else if (DCCM_INDEX_DEPTH == 128) begin : dccm
+         ram_128x39  dccm_bank (
+                                // Primary ports
+                                .ME  (el2_mem_export.dccm_clken[i]                                  ),
+                                .CLK (el2_mem_export.clk                                            ),
+                                .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
+                                .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
+                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                .ROP (                                                              ),
+                                // These are used by SoC
+                                `EL2_LOCAL_DCCM_RAM_TEST_PORTS
+                                .*
+                                );
+      end
+`endif
+end : dccm_loop
+end :Gen_dccm_enable
+
+
+//////////////////////////////////////////////////////
+// ICCM
+//
+if (pt.ICCM_ENABLE) begin : Gen_iccm_enable
+for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
+ `ifdef VERILATOR
+
+    el2_ram #(.depth(1<<pt.ICCM_INDEX_BITS), .width(39)) iccm_bank (
+                                     // Primary ports
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+ `else
+
+     if (pt.ICCM_INDEX_BITS == 6 ) begin : iccm
+               ram_64x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+
+   else if (pt.ICCM_INDEX_BITS == 7 ) begin : iccm
+               ram_128x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+
+     else if (pt.ICCM_INDEX_BITS == 8 ) begin : iccm
+               ram_256x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+     else if (pt.ICCM_INDEX_BITS == 9 ) begin : iccm
+               ram_512x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+     else if (pt.ICCM_INDEX_BITS == 10 ) begin : iccm
+               ram_1024x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+     else if (pt.ICCM_INDEX_BITS == 11 ) begin : iccm
+               ram_2048x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+     else if (pt.ICCM_INDEX_BITS == 12 ) begin : iccm
+               ram_4096x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+     else if (pt.ICCM_INDEX_BITS == 13 ) begin : iccm
+               ram_8192x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+     else if (pt.ICCM_INDEX_BITS == 14 ) begin : iccm
+               ram_16384x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+     else begin : iccm
+               ram_32768x39 iccm_bank (
+                                     // Primary ports
+                                     .CLK (el2_mem_export.clk                       ),
+                                     .ME  (el2_mem_export.iccm_clken[i]             ),
+                                     .WE  (el2_mem_export.iccm_wren_bank[i]         ),
+                                     .ADR (el2_mem_export.iccm_addr_bank[i]         ),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .ROP (                                         ),
+                                     // These are used by SoC
+                                     .TEST1   (1'b0   ),
+                                     .RME     (1'b0   ),
+                                     .RM      (4'b0000),
+                                     .LS      (1'b0   ),
+                                     .DS      (1'b0   ),
+                                     .SD      (1'b0   ) ,
+                                     .TEST_RNM(1'b0   ),
+                                     .BC1     (1'b0   ),
+                                     .BC2     (1'b0   )
+
+                                      );
+     end // block: iccm
+`endif
+end : iccm_loop
+end : Gen_iccm_enable
+
+
+endmodule
diff --git a/hw-latest/fpga/src/caliptra_wrapper_top.sv b/hw-latest/fpga/src/caliptra_wrapper_top.sv
index 8ce7fdb1..8e620474 100755
--- a/hw-latest/fpga/src/caliptra_wrapper_top.sv
+++ b/hw-latest/fpga/src/caliptra_wrapper_top.sv
@@ -126,9 +126,11 @@ caliptra_top caliptra_top_dut (
     .PWDATA(PWDATA),
     .PWRITE(PWRITE),
 
-    .qspi_clk_o(),
-    .qspi_cs_no(),
-    .qspi_d_io(),
+    .qspi_clk_o (),
+    .qspi_cs_no (),
+    .qspi_d_i   (),
+    .qspi_d_o   (),
+    .qspi_d_en_o(),
 
     .el2_mem_export(el2_mem_export),
 
diff --git a/rom/dev/tests/helpers.rs b/rom/dev/tests/helpers.rs
index 0a416c04..53abe07f 100644
--- a/rom/dev/tests/helpers.rs
+++ b/rom/dev/tests/helpers.rs
@@ -50,7 +50,7 @@ pub fn get_data<'a>(to_match: &str, haystack: &'a str) -> &'a str {
 }
 
 pub fn get_csr(hw: &mut DefaultHwModel) -> Result<Vec<u8>, ModelError> {
-    hw.step_until(|m| m.soc_ifc().cptra_flow_status().read().status() == 0x0800_0000);
+    hw.step_until(|m| m.soc_ifc().cptra_flow_status().read().status() == 0x0100_0000);
     let mut txn = hw.wait_for_mailbox_receive()?;
     let result = mem::take(&mut txn.req.data);
     txn.respond_success();