Repository: tetratelabs/wazero
Pull request #1661 (2023-08-25 01:58:50)

wazevo: passes float_misc, memory bitwise spectests
#1496 



Patch:
diff --git a/internal/engine/wazevo/backend/isa/arm64/instr.go b/internal/engine/wazevo/backend/isa/arm64/instr.go
index 6c680784..5015a8a0 100644
--- a/internal/engine/wazevo/backend/isa/arm64/instr.go
+++ b/internal/engine/wazevo/backend/isa/arm64/instr.go
@@ -99,6 +99,7 @@ var defKinds = [numInstructionKinds]defKind{
 	movFromVec:      defKindRD,
 	vecMisc:         defKindRD,
 	vecLanes:        defKindRD,
+	vecRRR:          defKindRD,
 	intToFpu:        defKindRD,
 }
 
@@ -199,6 +200,7 @@ var useKinds = [numInstructionKinds]useKind{
 	movFromVec:      useKindRN,
 	vecMisc:         useKindRN,
 	vecLanes:        useKindRN,
+	vecRRR:          useKindRNRM,
 	intToFpu:        useKindRN,
 }
 
@@ -724,6 +726,13 @@ func (i *instruction) asVecLanes(op vecOp, rd, rn operand, arr vecArrangement) {
 	i.u2 = uint64(arr)
 }
 
+func (i *instruction) asVecRRR(op vecOp, rd, rn, rm operand, arr vecArrangement) {
+	i.kind = vecRRR
+	i.u1 = uint64(op)
+	i.rn, i.rd, i.rm = rn, rd, rm
+	i.u2 = uint64(arr)
+}
+
 func (i *instruction) isCopy() bool {
 	op := i.kind
 	return op == mov64 || op == mov32 || op == fpuMov64 || op == fpuMov128
@@ -981,7 +990,12 @@ func (i *instruction) String() (str string) {
 	case vecMiscNarrow:
 		panic("TODO")
 	case vecRRR:
-		panic("TODO")
+		str = fmt.Sprintf("%s %s, %s, %s",
+			vecOp(i.u1),
+			formatVRegVec(i.rd.nr(), vecArrangement(i.u2), vecIndexNone),
+			formatVRegVec(i.rn.nr(), vecArrangement(i.u2), vecIndexNone),
+			formatVRegVec(i.rm.nr(), vecArrangement(i.u2), vecIndexNone),
+		)
 	case vecMisc:
 		str = fmt.Sprintf("%s %s, %s",
 			vecOp(i.u1),
@@ -1401,6 +1415,8 @@ func (b vecOp) String() string {
 		return "cnt"
 	case vecOpUaddlv:
 		return "uaddlv"
+	case vecOpBit:
+		return "bit"
 	}
 	panic(int(b))
 }
@@ -1408,6 +1424,7 @@ func (b vecOp) String() string {
 const (
 	vecOpCnt vecOp = iota
 	vecOpUaddlv
+	vecOpBit
 )
 
 // bitOp determines the type of bitwise operation. Instructions whose kind is one of
@@ -1439,10 +1456,11 @@ const (
 	fpuUniOpNeg fpuUniOp = iota
 	fpuUniOpCvt32To64
 	fpuUniOpSqrt
-	fpuUniOpPlus
-	fpuUniOpMinus
-	fpuUniOpZero
-	fpuUniOpNearest
+	fpuUniOpRoundPlus
+	fpuUniOpRoundMinus
+	fpuUniOpRoundZero
+	fpuUniOpRoundNearest
+	fpuUniOpAbs
 )
 
 // String implements the fmt.Stringer.
@@ -1454,14 +1472,16 @@ func (f fpuUniOp) String() string {
 		return "fcvt"
 	case fpuUniOpSqrt:
 		return "fsqrt"
-	case fpuUniOpPlus:
+	case fpuUniOpRoundPlus:
 		return "frintp"
-	case fpuUniOpMinus:
+	case fpuUniOpRoundMinus:
 		return "frintm"
-	case fpuUniOpZero:
+	case fpuUniOpRoundZero:
 		return "frintz"
-	case fpuUniOpNearest:
+	case fpuUniOpRoundNearest:
 		return "frintn"
+	case fpuUniOpAbs:
+		return "fabs"
 	}
 	panic(int(f))
 }
diff --git a/internal/engine/wazevo/backend/isa/arm64/instr_encoding.go b/internal/engine/wazevo/backend/isa/arm64/instr_encoding.go
index 11fa31c1..fd9fd313 100644
--- a/internal/engine/wazevo/backend/isa/arm64/instr_encoding.go
+++ b/internal/engine/wazevo/backend/isa/arm64/instr_encoding.go
@@ -266,11 +266,45 @@ func (i *instruction) encode(c backend.Compiler) {
 			regNumberInEncoding[i.rn.realReg()],
 			i.u3 == 1,
 		))
+	case vecRRR:
+		c.Emit4Bytes(encodeVecRRR(
+			vecOp(i.u1),
+			regNumberInEncoding[i.rd.realReg()],
+			regNumberInEncoding[i.rn.realReg()],
+			regNumberInEncoding[i.rm.realReg()],
+			vecArrangement(i.u2),
+		))
 	default:
 		panic(i.String())
 	}
 }
 
+// encodeVecRRR encodes as either "Advanced SIMD three *" in
+// https://developer.arm.com/documentation/ddi0596/2020-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en
+func encodeVecRRR(op vecOp, rd, rn, rm uint32, arr vecArrangement) uint32 {
+	switch op {
+	case vecOpBit:
+		var q uint32
+		switch arr {
+		case vecArrangement8B:
+			q = 0b0
+		case vecArrangement16B:
+			q = 0b1
+		default:
+			panic("BUG")
+		}
+		return encodeAdvancedSIMDThreeSame(rd, rn, rm, 0b00011, 0b10, 0b1, q)
+	default:
+		panic("TODO")
+	}
+}
+
+// encodeAdvancedSIMDThreeSame encodes as "Advanced SIMD three same" in
+// https://developer.arm.com/documentation/ddi0596/2020-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en
+func encodeAdvancedSIMDThreeSame(rd, rn, rm, opcode, size, U, Q uint32) uint32 {
+	return Q<<30 | U<<29 | 0b111<<25 | size<<22 | 0b1<<21 | rm<<16 | opcode<<11 | 0b1<<10 | rn<<5 | rd
+}
+
 // encodeFloatDataOneSource encodes as "Floating-point data-processing (1 source)" in
 // https://developer.arm.com/documentation/ddi0596/2020-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en#simd-dp
 func encodeFloatDataOneSource(op fpuUniOp, rd, rn uint32, dst64bit bool) uint32 {
@@ -288,26 +322,31 @@ func encodeFloatDataOneSource(op fpuUniOp, rd, rn uint32, dst64bit bool) uint32
 		if dst64bit {
 			ptype = 0b01
 		}
-	case fpuUniOpPlus:
+	case fpuUniOpRoundPlus:
 		opcode = 0b001001
 		if dst64bit {
 			ptype = 0b01
 		}
-	case fpuUniOpMinus:
+	case fpuUniOpRoundMinus:
 		opcode = 0b001010
 		if dst64bit {
 			ptype = 0b01
 		}
-	case fpuUniOpZero:
+	case fpuUniOpRoundZero:
 		opcode = 0b001011
 		if dst64bit {
 			ptype = 0b01
 		}
-	case fpuUniOpNearest:
+	case fpuUniOpRoundNearest:
 		opcode = 0b001000
 		if dst64bit {
 			ptype = 0b01
 		}
+	case fpuUniOpAbs:
+		opcode = 0b000001
+		if dst64bit {
+			ptype = 0b01
+		}
 	default:
 		panic("BUG")
 	}
diff --git a/internal/engine/wazevo/backend/isa/arm64/lower_instr.go b/internal/engine/wazevo/backend/isa/arm64/lower_instr.go
index b42d893d..d20eef18 100644
--- a/internal/engine/wazevo/backend/isa/arm64/lower_instr.go
+++ b/internal/engine/wazevo/backend/isa/arm64/lower_instr.go
@@ -8,6 +8,7 @@ package arm64
 
 import (
 	"fmt"
+	"math"
 
 	"github.com/tetratelabs/wazero/internal/engine/wazevo/backend/regalloc"
 	"github.com/tetratelabs/wazero/internal/engine/wazevo/ssa"
@@ -235,21 +236,57 @@ func (m *machine) LowerInstr(instr *ssa.Instruction) {
 	case ssa.OpcodeSqrt:
 		m.lowerFpuUniOp(fpuUniOpSqrt, instr.Arg(), instr.Return())
 	case ssa.OpcodeCeil:
-		m.lowerFpuUniOp(fpuUniOpPlus, instr.Arg(), instr.Return())
+		m.lowerFpuUniOp(fpuUniOpRoundPlus, instr.Arg(), instr.Return())
 	case ssa.OpcodeFloor:
-		m.lowerFpuUniOp(fpuUniOpMinus, instr.Arg(), instr.Return())
+		m.lowerFpuUniOp(fpuUniOpRoundMinus, instr.Arg(), instr.Return())
 	case ssa.OpcodeTrunc:
-		m.lowerFpuUniOp(fpuUniOpZero, instr.Arg(), instr.Return())
+		m.lowerFpuUniOp(fpuUniOpRoundZero, instr.Arg(), instr.Return())
 	case ssa.OpcodeNearest:
-		m.lowerFpuUniOp(fpuUniOpNearest, instr.Arg(), instr.Return())
+		m.lowerFpuUniOp(fpuUniOpRoundNearest, instr.Arg(), instr.Return())
+	case ssa.OpcodeFabs:
+		m.lowerFpuUniOp(fpuUniOpAbs, instr.Arg(), instr.Return())
 	case ssa.OpcodeBitcast:
 		m.lowerBitcast(instr)
+	case ssa.OpcodeFcopysign:
+		x, y := instr.BinaryData()
+		m.lowerFcopysign(x, y, instr.Return())
 	default:
 		panic("TODO: lowering " + instr.Opcode().String())
 	}
 	m.FlushPendingInstructions()
 }
 
+func (m *machine) lowerFcopysign(x, y, ret ssa.Value) {
+	rn := m.getOperand_NR(m.compiler.ValueDefinition(x), extModeNone)
+	rm := m.getOperand_NR(m.compiler.ValueDefinition(y), extModeNone)
+	tmpF := operandNR(m.compiler.AllocateVReg(regalloc.RegTypeFloat))
+
+	// This is exactly the same code emitted by GCC for "__builtin_copysign":
+	//
+	//    mov     x0, -9223372036854775808
+	//    fmov    d2, x0
+	//    vbit    v0.8b, v1.8b, v2.8b
+	//
+
+	setMSB := m.allocateInstr()
+	if x.Type() == ssa.TypeF32 {
+		m.lowerConstantI32(tmpRegVReg, math.MinInt32)
+		setMSB.asMovToVec(tmpF, operandNR(tmpRegVReg), vecArrangementS, vecIndex(0))
+	} else {
+		m.lowerConstantI64(tmpRegVReg, math.MinInt64)
+		setMSB.asMovToVec(tmpF, operandNR(tmpRegVReg), vecArrangementD, vecIndex(0))
+	}
+	m.insert(setMSB)
+
+	vbit := m.allocateInstr()
+	vbit.asVecRRR(vecOpBit, rn, rm, tmpF, vecArrangement8B)
+	m.insert(vbit)
+
+	mov := m.allocateInstr()
+	mov.asFpuMov64(m.compiler.VRegOf(ret), rn.nr())
+	m.insert(mov)
+}
+
 func (m *machine) lowerBitcast(instr *ssa.Instruction) {
 	v, dstType := instr.BitcastData()
 	srcType := v.Type()
diff --git a/internal/engine/wazevo/frontend/lower.go b/internal/engine/wazevo/frontend/lower.go
index ac2fd6ad..a54d9ff6 100644
--- a/internal/engine/wazevo/frontend/lower.go
+++ b/internal/engine/wazevo/frontend/lower.go
@@ -436,6 +436,14 @@ func (c *Compiler) lowerOpcode(op wasm.Opcode) {
 		x := state.pop()
 		v := builder.AllocateInstruction().AsFabs(x).Insert(builder).Return()
 		state.push(v)
+	case wasm.OpcodeF32Copysign, wasm.OpcodeF64Copysign:
+		if state.unreachable {
+			return
+		}
+		y, x := state.pop(), state.pop()
+		v := builder.AllocateInstruction().AsFcopysign(x, y).Insert(builder).Return()
+		state.push(v)
+
 	case wasm.OpcodeF32Ceil, wasm.OpcodeF64Ceil:
 		if state.unreachable {
 			return
@@ -503,6 +511,38 @@ func (c *Compiler) lowerOpcode(op wasm.Opcode) {
 			Insert(builder).Return()
 		state.push(reinterpret)
 
+	case wasm.OpcodeI32DivS, wasm.OpcodeI64DivS:
+		if state.unreachable {
+			return
+		}
+		y, x := state.pop(), state.pop()
+		result := builder.AllocateInstruction().AsSDiv(x, y).Insert(builder).Return()
+		state.push(result)
+
+	case wasm.OpcodeI32DivU, wasm.OpcodeI64DivU:
+		if state.unreachable {
+			return
+		}
+		y, x := state.pop(), state.pop()
+		result := builder.AllocateInstruction().AsUDiv(x, y).Insert(builder).Return()
+		state.push(result)
+
+	case wasm.OpcodeI32RemS, wasm.OpcodeI64RemS:
+		if state.unreachable {
+			return
+		}
+		y, x := state.pop(), state.pop()
+		result := builder.AllocateInstruction().AsSRem(x, y).Insert(builder).Return()
+		state.push(result)
+
+	case wasm.OpcodeI32RemU, wasm.OpcodeI64RemU:
+		if state.unreachable {
+			return
+		}
+		y, x := state.pop(), state.pop()
+		result := builder.AllocateInstruction().AsURem(x, y).Insert(builder).Return()
+		state.push(result)
+
 	case wasm.OpcodeI32And, wasm.OpcodeI64And:
 		if state.unreachable {
 			return
diff --git a/internal/engine/wazevo/ssa/instructions.go b/internal/engine/wazevo/ssa/instructions.go
index 55e58b04..b98053b1 100644
--- a/internal/engine/wazevo/ssa/instructions.go
+++ b/internal/engine/wazevo/ssa/instructions.go
@@ -877,6 +877,10 @@ var instructionSideEffects = [opcodeEnd]sideEffect{
 	OpcodeFloor:              sideEffectFalse,
 	OpcodeTrunc:              sideEffectFalse,
 	OpcodeNearest:            sideEffectFalse,
+	OpcodeSdiv:               sideEffectFalse,
+	OpcodeUdiv:               sideEffectFalse,
+	OpcodeFabs:               sideEffectFalse,
+	OpcodeFcopysign:          sideEffectFalse,
 }
 
 // HasSideEffects returns true if this instruction has side effects.
@@ -891,6 +895,7 @@ func (i *Instruction) HasSideEffects() bool {
 // instructionReturnTypes provides the function to determine the return types of an instruction.
 var instructionReturnTypes = [opcodeEnd]returnTypesFn{
 	OpcodeBand:      returnTypesFnSingle,
+	OpcodeFcopysign: returnTypesFnSingle,
 	OpcodeBitcast:   returnTypesFnSingle,
 	OpcodeBor:       returnTypesFnSingle,
 	OpcodeBxor:      returnTypesFnSingle,
@@ -898,6 +903,8 @@ var instructionReturnTypes = [opcodeEnd]returnTypesFn{
 	OpcodeRotr:      returnTypesFnSingle,
 	OpcodeIshl:      returnTypesFnSingle,
 	OpcodeSshr:      returnTypesFnSingle,
+	OpcodeSdiv:      returnTypesFnSingle,
+	OpcodeUdiv:      returnTypesFnSingle,
 	OpcodeUshr:      returnTypesFnSingle,
 	OpcodeJump:      returnTypesFnNoReturns,
 	OpcodeUndefined: returnTypesFnNoReturns,
@@ -906,6 +913,7 @@ var instructionReturnTypes = [opcodeEnd]returnTypesFn{
 	OpcodeSExtend:   returnTypesFnSingle,
 	OpcodeUExtend:   returnTypesFnSingle,
 	OpcodeIreduce:   returnTypesFnSingle,
+	OpcodeFabs:      returnTypesFnSingle,
 	OpcodeSqrt:      returnTypesFnSingle,
 	OpcodeCeil:      returnTypesFnSingle,
 	OpcodeFloor:     returnTypesFnSingle,
@@ -1107,6 +1115,42 @@ func (i *Instruction) AsFcmp(x, y Value, c FloatCmpCond) {
 	i.typ = TypeI32
 }
 
+// AsSDiv initializes this instruction as an integer bitwise and instruction with OpcodeSdiv.
+func (i *Instruction) AsSDiv(x, y Value) *Instruction {
+	i.opcode = OpcodeSdiv
+	i.v = x
+	i.v2 = y
+	i.typ = x.Type()
+	return i
+}
+
+// AsUDiv initializes this instruction as an integer bitwise and instruction with OpcodeUdiv.
+func (i *Instruction) AsUDiv(x, y Value) *Instruction {
+	i.opcode = OpcodeUdiv
+	i.v = x
+	i.v2 = y
+	i.typ = x.Type()
+	return i
+}
+
+// AsSRem initializes this instruction as an integer bitwise and instruction with OpcodeSrem.
+func (i *Instruction) AsSRem(x, y Value) *Instruction {
+	i.opcode = OpcodeSrem
+	i.v = x
+	i.v2 = y
+	i.typ = x.Type()
+	return i
+}
+
+// AsURem initializes this instruction as an integer bitwise and instruction with OpcodeUrem.
+func (i *Instruction) AsURem(x, y Value) *Instruction {
+	i.opcode = OpcodeUrem
+	i.v = x
+	i.v2 = y
+	i.typ = x.Type()
+	return i
+}
+
 // AsBand initializes this instruction as an integer bitwise and instruction with OpcodeBand.
 func (i *Instruction) AsBand(x, amount Value) {
 	i.opcode = OpcodeBand
@@ -1467,6 +1511,15 @@ func (i *Instruction) AsFabs(x Value) *Instruction {
 	return i
 }
 
+// AsFcopysign initializes this instruction as an instruction with OpcodeFcopysign.
+func (i *Instruction) AsFcopysign(x, y Value) *Instruction {
+	i.opcode = OpcodeFcopysign
+	i.v = x
+	i.v2 = y
+	i.typ = x.Type()
+	return i
+}
+
 // AsCeil initializes this instruction as an instruction with OpcodeCeil.
 func (i *Instruction) AsCeil(x Value) *Instruction {
 	i.opcode = OpcodeCeil
@@ -1681,7 +1734,8 @@ func (i *Instruction) Format(b Builder) string {
 			}
 		}
 		instSuffix += "]"
-	case OpcodeBand, OpcodeBor, OpcodeBxor, OpcodeRotr, OpcodeRotl, OpcodeIshl, OpcodeSshr, OpcodeUshr:
+	case OpcodeBand, OpcodeBor, OpcodeBxor, OpcodeRotr, OpcodeRotl, OpcodeIshl, OpcodeSshr, OpcodeUshr,
+		OpcodeSdiv, OpcodeUdiv, OpcodeFcopysign:
 		instSuffix = fmt.Sprintf(" %s, %s", i.v.Format(b), i.v2.Format(b))
 	case OpcodeUndefined:
 	case OpcodeClz, OpcodeCtz, OpcodePopcnt, OpcodeFneg, OpcodeFcvtFromSint, OpcodeFcvtFromUint, OpcodeFpromote,


Test patch:
diff --git a/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go b/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go
index 348bd05e..2c47a27b 100644
--- a/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go
+++ b/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go
@@ -19,6 +19,12 @@ func TestInstruction_encode(t *testing.T) {
 		setup func(*instruction)
 		want  string
 	}{
+		{want: "411ca32e", setup: func(i *instruction) {
+			i.asVecRRR(vecOpBit, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B)
+		}},
+		{want: "411ca36e", setup: func(i *instruction) {
+			i.asVecRRR(vecOpBit, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B)
+		}},
 		{want: "4100839a", setup: func(i *instruction) { i.asCSel(operandNR(x1VReg), operandNR(x2VReg), operandNR(x3VReg), eq, true) }},
 		{want: "4110839a", setup: func(i *instruction) { i.asCSel(operandNR(x1VReg), operandNR(x2VReg), operandNR(x3VReg), ne, true) }},
 		{want: "4100831a", setup: func(i *instruction) { i.asCSel(operandNR(x1VReg), operandNR(x2VReg), operandNR(x3VReg), eq, false) }},
@@ -519,28 +525,28 @@ func TestInstruction_encode(t *testing.T) {
 			i.asFpuRR(fpuUniOpSqrt, operandNR(v1VReg), operandNR(v2VReg), true)
 		}},
 		{want: "41c0241e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpPlus, operandNR(v1VReg), operandNR(v2VReg), false)
+			i.asFpuRR(fpuUniOpRoundPlus, operandNR(v1VReg), operandNR(v2VReg), false)
 		}},
 		{want: "41c0641e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpPlus, operandNR(v1VReg), operandNR(v2VReg), true)
+			i.asFpuRR(fpuUniOpRoundPlus, operandNR(v1VReg), operandNR(v2VReg), true)
 		}},
 		{want: "4140251e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpMinus, operandNR(v1VReg), operandNR(v2VReg), false)
+			i.asFpuRR(fpuUniOpRoundMinus, operandNR(v1VReg), operandNR(v2VReg), false)
 		}},
 		{want: "4140651e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpMinus, operandNR(v1VReg), operandNR(v2VReg), true)
+			i.asFpuRR(fpuUniOpRoundMinus, operandNR(v1VReg), operandNR(v2VReg), true)
 		}},
 		{want: "41c0251e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpZero, operandNR(v1VReg), operandNR(v2VReg), false)
+			i.asFpuRR(fpuUniOpRoundZero, operandNR(v1VReg), operandNR(v2VReg), false)
 		}},
 		{want: "41c0651e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpZero, operandNR(v1VReg), operandNR(v2VReg), true)
+			i.asFpuRR(fpuUniOpRoundZero, operandNR(v1VReg), operandNR(v2VReg), true)
 		}},
 		{want: "4140241e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpNearest, operandNR(v1VReg), operandNR(v2VReg), false)
+			i.asFpuRR(fpuUniOpRoundNearest, operandNR(v1VReg), operandNR(v2VReg), false)
 		}},
 		{want: "4140641e", setup: func(i *instruction) {
-			i.asFpuRR(fpuUniOpNearest, operandNR(v1VReg), operandNR(v2VReg), true)
+			i.asFpuRR(fpuUniOpRoundNearest, operandNR(v1VReg), operandNR(v2VReg), true)
 		}},
 		{want: "4140611e", setup: func(i *instruction) { i.asFpuRR(fpuUniOpNeg, operandNR(v1VReg), operandNR(v2VReg), true) }},
 		{want: "4201231e4201631e4201239e4201639e4201221e4201621e4201229e4201629e", setup: func(i *instruction) {
diff --git a/internal/engine/wazevo/e2e_test.go b/internal/engine/wazevo/e2e_test.go
index d4bfa161..544dd502 100644
--- a/internal/engine/wazevo/e2e_test.go
+++ b/internal/engine/wazevo/e2e_test.go
@@ -56,18 +56,24 @@ func TestSpectestV1(t *testing.T) {
 		{name: "endianness"},
 		{name: "exports"},
 		{name: "f32"},
+		{name: "f32_bitwise"},
 		{name: "f32_cmp"},
 		{name: "f64"},
+		{name: "f64_bitwise"},
 		{name: "f64_cmp"},
 		//{name: "fac"},
 		//{name: "float_exprs"},
 		{name: "float_literals"},
+		{name: "float_memory"},
+		{name: "float_misc"},
 		{name: "func"},
 		{name: "func_ptrs"},
 		{name: "forward"},
 		{name: "globals"},
 		{name: "if"},
 		{name: "imports"},
+		{name: "inline-module"},
+		//{name: "i32"},
 		//{name: "int_exprs"},
 		//{name: "int_literals"},
 		{name: "labels"},