Repository: tetratelabs/wazero
Pull request #1800 (2023-10-19 04:47:12)

wazevo(backend): makes VRegID continuous
#1496 


Patch:
diff --git a/internal/engine/wazevo/backend/compiler.go b/internal/engine/wazevo/backend/compiler.go
index 04bb9683..9622a992 100644
--- a/internal/engine/wazevo/backend/compiler.go
+++ b/internal/engine/wazevo/backend/compiler.go
@@ -23,7 +23,7 @@ func newCompiler(ctx context.Context, mach Machine, builder ssa.Builder) *compil
 
 	c := &compiler{
 		mach: mach, ssaBuilder: builder,
-		nextVRegID: 0,
+		nextVRegID: regalloc.VRegIDNonReservedBegin,
 		regAlloc:   regalloc.NewAllocator(mach.RegisterInfo(registerSetDebug)),
 	}
 	mach.SetCompiler(c)
@@ -290,7 +290,7 @@ func (c *compiler) AllocateVReg(typ ssa.Type) regalloc.VReg {
 // Init implements Compiler.Init.
 func (c *compiler) Init() {
 	c.currentGID = 0
-	c.nextVRegID = 0
+	c.nextVRegID = regalloc.VRegIDNonReservedBegin
 	c.returnVRegs = c.returnVRegs[:0]
 	c.mach.Reset()
 	c.varEdges = c.varEdges[:0]
diff --git a/internal/engine/wazevo/backend/regalloc/reg.go b/internal/engine/wazevo/backend/regalloc/reg.go
index b05edb6c..2c5f55b2 100644
--- a/internal/engine/wazevo/backend/regalloc/reg.go
+++ b/internal/engine/wazevo/backend/regalloc/reg.go
@@ -2,7 +2,6 @@ package regalloc
 
 import (
 	"fmt"
-	"math"
 
 	"github.com/tetratelabs/wazero/internal/engine/wazevo/ssa"
 )
@@ -31,7 +30,7 @@ func FromRealReg(r RealReg, typ RegType) VReg {
 	if rid > vRegIDReservedForRealNum {
 		panic(fmt.Sprintf("invalid real reg %d", r))
 	}
-	return VReg(vRegIDReservedForRealBegin + VRegID(r)).SetRealReg(r).SetRegType(typ)
+	return VReg(r).SetRealReg(r).SetRegType(typ)
 }
 
 // SetRealReg sets the RealReg of this VReg and returns the updated VReg.
@@ -65,11 +64,10 @@ type RealReg byte
 const RealRegInvalid RealReg = 0
 
 const (
-	vRegIDInvalid              VRegID = 1 << 31
-	vRegIDReservedForRealEnd          = vRegIDInvalid - 1
-	vRegIDReservedForRealBegin        = vRegIDReservedForRealEnd - vRegIDReservedForRealNum
-	vRegIDReservedForRealNum          = math.MaxUint8
-	VRegInvalid                       = VReg(vRegIDInvalid)
+	vRegIDInvalid            VRegID = 1 << 31
+	VRegIDNonReservedBegin          = vRegIDReservedForRealNum
+	vRegIDReservedForRealNum VRegID = 128
+	VRegInvalid                     = VReg(vRegIDInvalid)
 )
 
 // String implements fmt.Stringer.
@@ -85,7 +83,7 @@ func (r RealReg) String() string {
 // String implements fmt.Stringer.
 func (v VReg) String() string {
 	if v.IsRealReg() {
-		return fmt.Sprintf("r%d", v.ID()-vRegIDReservedForRealBegin)
+		return fmt.Sprintf("r%d", v.ID())
 	}
 	return fmt.Sprintf("v%d?", v.ID())
 }


Test patch:
diff --git a/internal/engine/wazevo/backend/backend_test.go b/internal/engine/wazevo/backend/backend_test.go
index 6ea9289b..3d93f801 100644
--- a/internal/engine/wazevo/backend/backend_test.go
+++ b/internal/engine/wazevo/backend/backend_test.go
@@ -84,14 +84,14 @@ L1 (SSA Block: blk0):
 			name: "consts", m: testcases.Constants.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	ldr d5?, #8; b 16; data.f64 64.000000
-	mov v1.8b, v5?.8b
-	ldr s4?, #8; b 8; data.f32 32.000000
-	mov v0.8b, v4?.8b
-	orr x3?, xzr, #0x2
-	mov x1, x3?
-	orr w2?, wzr, #0x1
-	mov x0, x2?
+	ldr d133?, #8; b 16; data.f64 64.000000
+	mov v1.8b, v133?.8b
+	ldr s132?, #8; b 8; data.f32 32.000000
+	mov v0.8b, v132?.8b
+	orr x131?, xzr, #0x2
+	mov x1, x131?
+	orr w130?, wzr, #0x1
+	mov x0, x130?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -111,11 +111,11 @@ L1 (SSA Block: blk0):
 			name: "add sub params return", m: testcases.AddSubParamsReturn.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, x3
-	add w4?, w2?, w3?
-	sub w5?, w4?, w2?
-	mov x0, x5?
+	mov x130?, x2
+	mov x131?, x3
+	add w132?, w130?, w131?
+	sub w133?, w132?, w130?
+	mov x0, x133?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -133,26 +133,26 @@ L1 (SSA Block: blk0):
 			name: "locals params", m: testcases.LocalsParams.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov v3?.8b, v0.8b
-	mov v4?.8b, v1.8b
-	add x5?, x2?, x2?
-	sub x6?, x5?, x2?
-	fadd s7?, s3?, s3?
-	fsub s8?, s7?, s3?
-	fmul s9?, s8?, s3?
-	fdiv s10?, s9?, s3?
-	fmax s11?, s10?, s3?
-	fmin s12?, s11?, s3?
-	fadd d13?, d4?, d4?
-	fsub d14?, d13?, d4?
-	fmul d15?, d14?, d4?
-	fdiv d16?, d15?, d4?
-	fmax d17?, d16?, d4?
-	fmin d18?, d17?, d4?
-	mov v1.8b, v18?.8b
-	mov v0.8b, v12?.8b
-	mov x0, x6?
+	mov x130?, x2
+	mov v131?.8b, v0.8b
+	mov v132?.8b, v1.8b
+	add x133?, x130?, x130?
+	sub x134?, x133?, x130?
+	fadd s135?, s131?, s131?
+	fsub s136?, s135?, s131?
+	fmul s137?, s136?, s131?
+	fdiv s138?, s137?, s131?
+	fmax s139?, s138?, s131?
+	fmin s140?, s139?, s131?
+	fadd d141?, d132?, d132?
+	fsub d142?, d141?, d132?
+	fmul d143?, d142?, d132?
+	fdiv d144?, d143?, d132?
+	fmax d145?, d144?, d132?
+	fmin d146?, d145?, d132?
+	mov v1.8b, v146?.8b
+	mov v0.8b, v140?.8b
+	mov x0, x134?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -182,10 +182,10 @@ L1 (SSA Block: blk0):
 			name: "local_param_return", m: testcases.LocalParamReturn.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, xzr
-	mov x1, x3?
-	mov x0, x2?
+	mov x130?, x2
+	mov x131?, xzr
+	mov x1, x131?
+	mov x0, x130?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -203,10 +203,10 @@ L1 (SSA Block: blk0):
 			name: "swap_param_and_return", m: testcases.SwapParamAndReturn.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, x3
-	mov x1, x2?
-	mov x0, x3?
+	mov x130?, x2
+	mov x131?, x3
+	mov x1, x130?
+	mov x0, x131?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -224,11 +224,11 @@ L1 (SSA Block: blk0):
 			name: "swap_params_and_return", m: testcases.SwapParamsAndReturn.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, x3
+	mov x130?, x2
+	mov x131?, x3
 L2 (SSA Block: blk1):
-	mov x1, x2?
-	mov x0, x3?
+	mov x1, x130?
+	mov x0, x131?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -264,19 +264,19 @@ L2 (SSA Block: blk1):
 			name: "block_br_if", m: testcases.BlockBrIf.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x0?, x0
-	mov x3?, xzr
-	cbz w3?, (L2)
+	mov x128?, x0
+	mov x131?, xzr
+	cbz w131?, (L2)
 L3 (SSA Block: blk1):
 	ret
 L2 (SSA Block: blk2):
-	movz x4?, #0x3, lsl 0
-	str w4?, [x0?]
-	mov x5?, sp
-	str x5?, [x0?, #0x38]
-	adr x6?, #0x0
-	str x6?, [x0?, #0x30]
-	exit_sequence x0?
+	movz x132?, #0x3, lsl 0
+	str w132?, [x128?]
+	mov x133?, sp
+	str x133?, [x128?, #0x38]
+	adr x134?, #0x0
+	str x134?, [x128?, #0x30]
+	exit_sequence x128?
 `,
 			afterFinalizeARM64: `
 L1 (SSA Block: blk0):
@@ -317,15 +317,15 @@ L2 (SSA Block: blk1):
 			name: "loop_with_param_results", m: testcases.LoopBrWithParamResults.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
+	mov x130?, x2
 L2 (SSA Block: blk1):
-	orr w5?, wzr, #0x1
-	cbz w5?, (L3)
+	orr w133?, wzr, #0x1
+	cbz w133?, (L3)
 L4 (SSA Block: blk4):
 	b L2
 L3 (SSA Block: blk3):
 L5 (SSA Block: blk2):
-	mov x0, x2?
+	mov x0, x130?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -350,8 +350,8 @@ L5 (SSA Block: blk2):
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
 L2 (SSA Block: blk1):
-	orr w3?, wzr, #0x1
-	cbz w3?, (L3)
+	orr w131?, wzr, #0x1
+	cbz w131?, (L3)
 L4 (SSA Block: blk4):
 	b L2
 L3 (SSA Block: blk3):
@@ -396,8 +396,8 @@ L2 (SSA Block: blk1):
 			// Instead, we can do it during the code generation phase where we actually resolve the label offsets.
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x3?, xzr
-	cbnz w3?, L2
+	mov x131?, xzr
+	cbnz w131?, L2
 L3 (SSA Block: blk2):
 	b L4
 L2 (SSA Block: blk1):
@@ -423,8 +423,8 @@ L4 (SSA Block: blk3):
 			name: "if_else", m: testcases.IfElse.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x3?, xzr
-	cbnz w3?, L2
+	mov x131?, xzr
+	cbnz w131?, L2
 L3 (SSA Block: blk2):
 	ret
 L2 (SSA Block: blk1):
@@ -452,16 +452,16 @@ L4 (SSA Block: blk3):
 			name: "single_predecessor_local_refs", m: testcases.SinglePredecessorLocalRefs.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x4?, xzr
-	cbnz w4?, L2
+	mov x132?, xzr
+	cbnz w132?, L2
 L3 (SSA Block: blk2):
 L4 (SSA Block: blk3):
-	mov x2?, xzr
-	mov x0, x2?
+	mov x130?, xzr
+	mov x0, x130?
 	ret
 L2 (SSA Block: blk1):
-	mov x3?, xzr
-	mov x0, x3?
+	mov x131?, xzr
+	mov x0, x131?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -487,16 +487,16 @@ L2 (SSA Block: blk1):
 			name: "multi_predecessor_local_ref", m: testcases.MultiPredecessorLocalRef.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, x3
-	cbnz w2?, L2
+	mov x130?, x2
+	mov x131?, x3
+	cbnz w130?, L2
 L3 (SSA Block: blk2):
-	mov x4?, x3?
+	mov x132?, x131?
 	b L4
 L2 (SSA Block: blk1):
-	mov x4?, x2?
+	mov x132?, x130?
 L4 (SSA Block: blk3):
-	mov x0, x4?
+	mov x0, x132?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -519,9 +519,9 @@ L4 (SSA Block: blk3):
 			name: "reference_value_from_unsealed_block", m: testcases.ReferenceValueFromUnsealedBlock.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
+	mov x130?, x2
 L2 (SSA Block: blk1):
-	mov x0, x2?
+	mov x0, x130?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -539,16 +539,16 @@ L2 (SSA Block: blk1):
 			name: "reference_value_from_unsealed_block2", m: testcases.ReferenceValueFromUnsealedBlock2.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
+	mov x130?, x2
 L2 (SSA Block: blk1):
-	cbz w2?, (L3)
+	cbz w130?, (L3)
 L4 (SSA Block: blk5):
 	b L2
 L3 (SSA Block: blk4):
 L5 (SSA Block: blk3):
 L6 (SSA Block: blk2):
-	mov x3?, xzr
-	mov x0, x3?
+	mov x131?, xzr
+	mov x0, x131?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -573,16 +573,16 @@ L6 (SSA Block: blk2):
 			// TODO: we should be able to invert cbnz in so that L2 can end with fallthrough. investigate builder.LayoutBlocks function.
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, x2?
+	mov x130?, x2
+	mov x131?, x130?
 L2 (SSA Block: blk1):
-	cbnz w3?, L4
+	cbnz w131?, L4
 	b L3
 L4 (SSA Block: blk5):
 	ret
 L3 (SSA Block: blk4):
 L5 (SSA Block: blk3):
-	orr w3?, wzr, #0x1
+	orr w131?, wzr, #0x1
 	b L2
 `,
 			afterFinalizeARM64: `
@@ -607,30 +607,30 @@ L5 (SSA Block: blk3):
 			name: "call", m: testcases.Call.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x0?, x0
-	mov x1?, x1
-	str x1?, [x0?, #0x8]
-	mov x0, x0?
-	mov x1, x1?
+	mov x128?, x0
+	mov x129?, x1
+	str x129?, [x128?, #0x8]
+	mov x0, x128?
+	mov x1, x129?
 	bl f1
-	mov x2?, x0
-	str x1?, [x0?, #0x8]
-	mov x0, x0?
-	mov x1, x1?
-	mov x2, x2?
-	movz w3?, #0x5, lsl 0
-	mov x3, x3?
+	mov x130?, x0
+	str x129?, [x128?, #0x8]
+	mov x0, x128?
+	mov x1, x129?
+	mov x2, x130?
+	movz w131?, #0x5, lsl 0
+	mov x3, x131?
 	bl f2
-	mov x4?, x0
-	str x1?, [x0?, #0x8]
-	mov x0, x0?
-	mov x1, x1?
-	mov x2, x4?
+	mov x132?, x0
+	str x129?, [x128?, #0x8]
+	mov x0, x128?
+	mov x1, x129?
+	mov x2, x132?
 	bl f3
-	mov x5?, x0
-	mov x6?, x1
-	mov x1, x6?
-	mov x0, x5?
+	mov x133?, x0
+	mov x134?, x1
+	mov x1, x134?
+	mov x0, x133?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -674,55 +674,55 @@ L1 (SSA Block: blk0):
 			name: "call_many_params", m: testcases.CallManyParams.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x0?, x0
-	mov x1?, x1
-	mov x2?, x2
-	mov x3?, x3
-	mov v4?.8b, v0.8b
-	mov v5?.8b, v1.8b
-	str x1?, [x0?, #0x8]
-	mov x0, x0?
-	mov x1, x1?
-	mov x2, x2?
-	mov x3, x3?
-	mov v0.8b, v4?.8b
-	mov v1.8b, v5?.8b
-	mov x4, x2?
-	mov x5, x3?
-	mov v2.8b, v4?.8b
-	mov v3.8b, v5?.8b
-	mov x6, x2?
-	mov x7, x3?
-	mov v4.8b, v4?.8b
-	mov v5.8b, v5?.8b
-	str w2?, [sp, #-0xd0]
-	str x3?, [sp, #-0xc8]
-	mov v6.8b, v4?.8b
-	mov v7.8b, v5?.8b
-	str w2?, [sp, #-0xc0]
-	str x3?, [sp, #-0xb8]
-	str s4?, [sp, #-0xb0]
-	str d5?, [sp, #-0xa8]
-	str w2?, [sp, #-0xa0]
-	str x3?, [sp, #-0x98]
-	str s4?, [sp, #-0x90]
-	str d5?, [sp, #-0x88]
-	str w2?, [sp, #-0x80]
-	str x3?, [sp, #-0x78]
-	str s4?, [sp, #-0x70]
-	str d5?, [sp, #-0x68]
-	str w2?, [sp, #-0x60]
-	str x3?, [sp, #-0x58]
-	str s4?, [sp, #-0x50]
-	str d5?, [sp, #-0x48]
-	str w2?, [sp, #-0x40]
-	str x3?, [sp, #-0x38]
-	str s4?, [sp, #-0x30]
-	str d5?, [sp, #-0x28]
-	str w2?, [sp, #-0x20]
-	str x3?, [sp, #-0x18]
-	str s4?, [sp, #-0x10]
-	str d5?, [sp, #-0x8]
+	mov x128?, x0
+	mov x129?, x1
+	mov x130?, x2
+	mov x131?, x3
+	mov v132?.8b, v0.8b
+	mov v133?.8b, v1.8b
+	str x129?, [x128?, #0x8]
+	mov x0, x128?
+	mov x1, x129?
+	mov x2, x130?
+	mov x3, x131?
+	mov v0.8b, v132?.8b
+	mov v1.8b, v133?.8b
+	mov x4, x130?
+	mov x5, x131?
+	mov v2.8b, v132?.8b
+	mov v3.8b, v133?.8b
+	mov x6, x130?
+	mov x7, x131?
+	mov v4.8b, v132?.8b
+	mov v5.8b, v133?.8b
+	str w130?, [sp, #-0xd0]
+	str x131?, [sp, #-0xc8]
+	mov v6.8b, v132?.8b
+	mov v7.8b, v133?.8b
+	str w130?, [sp, #-0xc0]
+	str x131?, [sp, #-0xb8]
+	str s132?, [sp, #-0xb0]
+	str d133?, [sp, #-0xa8]
+	str w130?, [sp, #-0xa0]
+	str x131?, [sp, #-0x98]
+	str s132?, [sp, #-0x90]
+	str d133?, [sp, #-0x88]
+	str w130?, [sp, #-0x80]
+	str x131?, [sp, #-0x78]
+	str s132?, [sp, #-0x70]
+	str d133?, [sp, #-0x68]
+	str w130?, [sp, #-0x60]
+	str x131?, [sp, #-0x58]
+	str s132?, [sp, #-0x50]
+	str d133?, [sp, #-0x48]
+	str w130?, [sp, #-0x40]
+	str x131?, [sp, #-0x38]
+	str s132?, [sp, #-0x30]
+	str d133?, [sp, #-0x28]
+	str w130?, [sp, #-0x20]
+	str x131?, [sp, #-0x18]
+	str s132?, [sp, #-0x10]
+	str d133?, [sp, #-0x8]
 	bl f1
 	ret
 `,
@@ -785,100 +785,100 @@ L1 (SSA Block: blk0):
 			name: "call_many_returns", m: testcases.CallManyReturns.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x0?, x0
-	mov x1?, x1
-	mov x2?, x2
-	mov x3?, x3
-	mov v4?.8b, v0.8b
-	mov v5?.8b, v1.8b
-	str x1?, [x0?, #0x8]
-	mov x0, x0?
-	mov x1, x1?
-	mov x2, x2?
-	mov x3, x3?
-	mov v0.8b, v4?.8b
-	mov v1.8b, v5?.8b
+	mov x128?, x0
+	mov x129?, x1
+	mov x130?, x2
+	mov x131?, x3
+	mov v132?.8b, v0.8b
+	mov v133?.8b, v1.8b
+	str x129?, [x128?, #0x8]
+	mov x0, x128?
+	mov x1, x129?
+	mov x2, x130?
+	mov x3, x131?
+	mov v0.8b, v132?.8b
+	mov v1.8b, v133?.8b
 	bl f1
-	mov x6?, x0
-	mov x7?, x1
-	mov v8?.8b, v0.8b
-	mov v9?.8b, v1.8b
-	mov x10?, x2
-	mov x11?, x3
-	mov v12?.8b, v2.8b
-	mov v13?.8b, v3.8b
-	mov x14?, x4
-	mov x15?, x5
-	mov v16?.8b, v4.8b
-	mov v17?.8b, v5.8b
-	mov x18?, x6
-	mov x19?, x7
-	mov v20?.8b, v6.8b
-	mov v21?.8b, v7.8b
-	ldr w22?, [sp, #-0xc0]
-	ldr x23?, [sp, #-0xb8]
-	ldr s24?, [sp, #-0xb0]
-	ldr d25?, [sp, #-0xa8]
-	ldr w26?, [sp, #-0xa0]
-	ldr x27?, [sp, #-0x98]
-	ldr s28?, [sp, #-0x90]
-	ldr d29?, [sp, #-0x88]
-	ldr w30?, [sp, #-0x80]
-	ldr x31?, [sp, #-0x78]
-	ldr s32?, [sp, #-0x70]
-	ldr d33?, [sp, #-0x68]
-	ldr w34?, [sp, #-0x60]
-	ldr x35?, [sp, #-0x58]
-	ldr s36?, [sp, #-0x50]
-	ldr d37?, [sp, #-0x48]
-	ldr w38?, [sp, #-0x40]
-	ldr x39?, [sp, #-0x38]
-	ldr s40?, [sp, #-0x30]
-	ldr d41?, [sp, #-0x28]
-	ldr w42?, [sp, #-0x20]
-	ldr x43?, [sp, #-0x18]
-	ldr s44?, [sp, #-0x10]
-	ldr d45?, [sp, #-0x8]
-	str d45?, [#ret_space, #0xb8]
-	str s44?, [#ret_space, #0xb0]
-	str x43?, [#ret_space, #0xa8]
-	str w42?, [#ret_space, #0xa0]
-	str d41?, [#ret_space, #0x98]
-	str s40?, [#ret_space, #0x90]
-	str x39?, [#ret_space, #0x88]
-	str w38?, [#ret_space, #0x80]
-	str d37?, [#ret_space, #0x78]
-	str s36?, [#ret_space, #0x70]
-	str x35?, [#ret_space, #0x68]
-	str w34?, [#ret_space, #0x60]
-	str d33?, [#ret_space, #0x58]
-	str s32?, [#ret_space, #0x50]
-	str x31?, [#ret_space, #0x48]
-	str w30?, [#ret_space, #0x40]
-	str d29?, [#ret_space, #0x38]
-	str s28?, [#ret_space, #0x30]
-	str x27?, [#ret_space, #0x28]
-	str w26?, [#ret_space, #0x20]
-	str d25?, [#ret_space, #0x18]
-	str s24?, [#ret_space, #0x10]
-	str x23?, [#ret_space, #0x8]
-	str w22?, [#ret_space, #0x0]
-	mov v7.8b, v21?.8b
-	mov v6.8b, v20?.8b
-	mov x7, x19?
-	mov x6, x18?
-	mov v5.8b, v17?.8b
-	mov v4.8b, v16?.8b
-	mov x5, x15?
-	mov x4, x14?
-	mov v3.8b, v13?.8b
-	mov v2.8b, v12?.8b
-	mov x3, x11?
-	mov x2, x10?
-	mov v1.8b, v9?.8b
-	mov v0.8b, v8?.8b
-	mov x1, x7?
-	mov x0, x6?
+	mov x134?, x0
+	mov x135?, x1
+	mov v136?.8b, v0.8b
+	mov v137?.8b, v1.8b
+	mov x138?, x2
+	mov x139?, x3
+	mov v140?.8b, v2.8b
+	mov v141?.8b, v3.8b
+	mov x142?, x4
+	mov x143?, x5
+	mov v144?.8b, v4.8b
+	mov v145?.8b, v5.8b
+	mov x146?, x6
+	mov x147?, x7
+	mov v148?.8b, v6.8b
+	mov v149?.8b, v7.8b
+	ldr w150?, [sp, #-0xc0]
+	ldr x151?, [sp, #-0xb8]
+	ldr s152?, [sp, #-0xb0]
+	ldr d153?, [sp, #-0xa8]
+	ldr w154?, [sp, #-0xa0]
+	ldr x155?, [sp, #-0x98]
+	ldr s156?, [sp, #-0x90]
+	ldr d157?, [sp, #-0x88]
+	ldr w158?, [sp, #-0x80]
+	ldr x159?, [sp, #-0x78]
+	ldr s160?, [sp, #-0x70]
+	ldr d161?, [sp, #-0x68]
+	ldr w162?, [sp, #-0x60]
+	ldr x163?, [sp, #-0x58]
+	ldr s164?, [sp, #-0x50]
+	ldr d165?, [sp, #-0x48]
+	ldr w166?, [sp, #-0x40]
+	ldr x167?, [sp, #-0x38]
+	ldr s168?, [sp, #-0x30]
+	ldr d169?, [sp, #-0x28]
+	ldr w170?, [sp, #-0x20]
+	ldr x171?, [sp, #-0x18]
+	ldr s172?, [sp, #-0x10]
+	ldr d173?, [sp, #-0x8]
+	str d173?, [#ret_space, #0xb8]
+	str s172?, [#ret_space, #0xb0]
+	str x171?, [#ret_space, #0xa8]
+	str w170?, [#ret_space, #0xa0]
+	str d169?, [#ret_space, #0x98]
+	str s168?, [#ret_space, #0x90]
+	str x167?, [#ret_space, #0x88]
+	str w166?, [#ret_space, #0x80]
+	str d165?, [#ret_space, #0x78]
+	str s164?, [#ret_space, #0x70]
+	str x163?, [#ret_space, #0x68]
+	str w162?, [#ret_space, #0x60]
+	str d161?, [#ret_space, #0x58]
+	str s160?, [#ret_space, #0x50]
+	str x159?, [#ret_space, #0x48]
+	str w158?, [#ret_space, #0x40]
+	str d157?, [#ret_space, #0x38]
+	str s156?, [#ret_space, #0x30]
+	str x155?, [#ret_space, #0x28]
+	str w154?, [#ret_space, #0x20]
+	str d153?, [#ret_space, #0x18]
+	str s152?, [#ret_space, #0x10]
+	str x151?, [#ret_space, #0x8]
+	str w150?, [#ret_space, #0x0]
+	mov v7.8b, v149?.8b
+	mov v6.8b, v148?.8b
+	mov x7, x147?
+	mov x6, x146?
+	mov v5.8b, v145?.8b
+	mov v4.8b, v144?.8b
+	mov x5, x143?
+	mov x4, x142?
+	mov v3.8b, v141?.8b
+	mov v2.8b, v140?.8b
+	mov x3, x139?
+	mov x2, x138?
+	mov v1.8b, v137?.8b
+	mov v0.8b, v136?.8b
+	mov x1, x135?
+	mov x0, x134?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -957,22 +957,22 @@ L1 (SSA Block: blk0):
 			m:    testcases.IntegerExtensions.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, x3
-	sxtw x4?, w2?
-	uxtw x5?, w2?
-	sxtb x6?, w3?
-	sxth x7?, w3?
-	sxtw x8?, w3?
-	sxtb w9?, w2?
-	sxth w10?, w2?
-	mov x6, x10?
-	mov x5, x9?
-	mov x4, x8?
-	mov x3, x7?
-	mov x2, x6?
-	mov x1, x5?
-	mov x0, x4?
+	mov x130?, x2
+	mov x131?, x3
+	sxtw x132?, w130?
+	uxtw x133?, w130?
+	sxtb x134?, w131?
+	sxth x135?, w131?
+	sxtw x136?, w131?
+	sxtb w137?, w130?
+	sxth w138?, w130?
+	mov x6, x138?
+	mov x5, x137?
+	mov x4, x136?
+	mov x3, x135?
+	mov x2, x134?
+	mov x1, x133?
+	mov x0, x132?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -997,28 +997,28 @@ L1 (SSA Block: blk0):
 			name: "integer bit counts", m: testcases.IntegerBitCounts.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov x3?, x3
-	clz w4?, w2?
-	rbit w17?, w2?
-	clz w5?, w17?
-	ins v14?.d[0], x2?
-	cnt v15?.16b, v14?.16b
-	uaddlv h16?, v15?.8b
-	mov x6?, v16?.d[0]
-	clz x7?, x3?
-	rbit x13?, x3?
-	clz x8?, x13?
-	ins v10?.d[0], x3?
-	cnt v11?.16b, v10?.16b
-	uaddlv h12?, v11?.8b
-	mov x9?, v12?.d[0]
-	mov x5, x9?
-	mov x4, x8?
-	mov x3, x7?
-	mov x2, x6?
-	mov x1, x5?
-	mov x0, x4?
+	mov x130?, x2
+	mov x131?, x3
+	clz w132?, w130?
+	rbit w145?, w130?
+	clz w133?, w145?
+	ins v142?.d[0], x130?
+	cnt v143?.16b, v142?.16b
+	uaddlv h144?, v143?.8b
+	mov x134?, v144?.d[0]
+	clz x135?, x131?
+	rbit x141?, x131?
+	clz x136?, x141?
+	ins v138?.d[0], x131?
+	cnt v139?.16b, v138?.16b
+	uaddlv h140?, v139?.8b
+	mov x137?, v140?.d[0]
+	mov x5, x137?
+	mov x4, x136?
+	mov x3, x135?
+	mov x2, x134?
+	mov x1, x133?
+	mov x0, x132?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -1312,128 +1312,128 @@ L1 (SSA Block: blk0):
 			m:    testcases.ManyMiddleValues.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	mov v3?.8b, v0.8b
-	orr w161?, wzr, #0x1
-	madd w5?, w2?, w161?, wzr
-	orr w160?, wzr, #0x2
-	madd w7?, w2?, w160?, wzr
-	orr w159?, wzr, #0x3
-	madd w9?, w2?, w159?, wzr
-	orr w158?, wzr, #0x4
-	madd w11?, w2?, w158?, wzr
-	movz w157?, #0x5, lsl 0
-	madd w13?, w2?, w157?, wzr
-	orr w156?, wzr, #0x6
-	madd w15?, w2?, w156?, wzr
-	orr w155?, wzr, #0x7
-	madd w17?, w2?, w155?, wzr
-	orr w154?, wzr, #0x8
-	madd w19?, w2?, w154?, wzr
-	movz w153?, #0x9, lsl 0
-	madd w21?, w2?, w153?, wzr
-	movz w152?, #0xa, lsl 0
-	madd w23?, w2?, w152?, wzr
-	movz w151?, #0xb, lsl 0
-	madd w25?, w2?, w151?, wzr
-	orr w150?, wzr, #0xc
-	madd w27?, w2?, w150?, wzr
-	movz w149?, #0xd, lsl 0
-	madd w29?, w2?, w149?, wzr
-	orr w148?, wzr, #0xe
-	madd w31?, w2?, w148?, wzr
-	orr w147?, wzr, #0xf
-	madd w33?, w2?, w147?, wzr
-	orr w146?, wzr, #0x10
-	madd w35?, w2?, w146?, wzr
-	movz w145?, #0x11, lsl 0
-	madd w37?, w2?, w145?, wzr
-	movz w144?, #0x12, lsl 0
-	madd w39?, w2?, w144?, wzr
-	movz w143?, #0x13, lsl 0
-	madd w41?, w2?, w143?, wzr
-	movz w142?, #0x14, lsl 0
-	madd w43?, w2?, w142?, wzr
-	add w44?, w41?, w43?
-	add w45?, w39?, w44?
-	add w46?, w37?, w45?
-	add w47?, w35?, w46?
-	add w48?, w33?, w47?
-	add w49?, w31?, w48?
-	add w50?, w29?, w49?
-	add w51?, w27?, w50?
-	add w52?, w25?, w51?
-	add w53?, w23?, w52?
-	add w54?, w21?, w53?
-	add w55?, w19?, w54?
-	add w56?, w17?, w55?
-	add w57?, w15?, w56?
-	add w58?, w13?, w57?
-	add w59?, w11?, w58?
-	add w60?, w9?, w59?
-	add w61?, w7?, w60?
-	add w62?, w5?, w61?
-	ldr s141?, #8; b 8; data.f32 1.000000
-	fmul s64?, s3?, s141?
-	ldr s140?, #8; b 8; data.f32 2.000000
-	fmul s66?, s3?, s140?
-	ldr s139?, #8; b 8; data.f32 3.000000
-	fmul s68?, s3?, s139?
-	ldr s138?, #8; b 8; data.f32 4.000000
-	fmul s70?, s3?, s138?
-	ldr s137?, #8; b 8; data.f32 5.000000
-	fmul s72?, s3?, s137?
-	ldr s136?, #8; b 8; data.f32 6.000000
-	fmul s74?, s3?, s136?
-	ldr s135?, #8; b 8; data.f32 7.000000
-	fmul s76?, s3?, s135?
-	ldr s134?, #8; b 8; data.f32 8.000000
-	fmul s78?, s3?, s134?
-	ldr s133?, #8; b 8; data.f32 9.000000
-	fmul s80?, s3?, s133?
-	ldr s132?, #8; b 8; data.f32 10.000000
-	fmul s82?, s3?, s132?
-	ldr s131?, #8; b 8; data.f32 11.000000
-	fmul s84?, s3?, s131?
-	ldr s130?, #8; b 8; data.f32 12.000000
-	fmul s86?, s3?, s130?
-	ldr s129?, #8; b 8; data.f32 13.000000
-	fmul s88?, s3?, s129?
-	ldr s128?, #8; b 8; data.f32 14.000000
-	fmul s90?, s3?, s128?
-	ldr s127?, #8; b 8; data.f32 15.000000
-	fmul s92?, s3?, s127?
-	ldr s126?, #8; b 8; data.f32 16.000000
-	fmul s94?, s3?, s126?
-	ldr s125?, #8; b 8; data.f32 17.000000
-	fmul s96?, s3?, s125?
-	ldr s124?, #8; b 8; data.f32 18.000000
-	fmul s98?, s3?, s124?
-	ldr s123?, #8; b 8; data.f32 19.000000
-	fmul s100?, s3?, s123?
-	ldr s122?, #8; b 8; data.f32 20.000000
-	fmul s102?, s3?, s122?
-	fadd s103?, s100?, s102?
-	fadd s104?, s98?, s103?
-	fadd s105?, s96?, s104?
-	fadd s106?, s94?, s105?
-	fadd s107?, s92?, s106?
-	fadd s108?, s90?, s107?
-	fadd s109?, s88?, s108?
-	fadd s110?, s86?, s109?
-	fadd s111?, s84?, s110?
-	fadd s112?, s82?, s111?
-	fadd s113?, s80?, s112?
-	fadd s114?, s78?, s113?
-	fadd s115?, s76?, s114?
-	fadd s116?, s74?, s115?
-	fadd s117?, s72?, s116?
-	fadd s118?, s70?, s117?
-	fadd s119?, s68?, s118?
-	fadd s120?, s66?, s119?
-	fadd s121?, s64?, s120?
-	mov v0.8b, v121?.8b
-	mov x0, x62?
+	mov x130?, x2
+	mov v131?.8b, v0.8b
+	orr w289?, wzr, #0x1
+	madd w133?, w130?, w289?, wzr
+	orr w288?, wzr, #0x2
+	madd w135?, w130?, w288?, wzr
+	orr w287?, wzr, #0x3
+	madd w137?, w130?, w287?, wzr
+	orr w286?, wzr, #0x4
+	madd w139?, w130?, w286?, wzr
+	movz w285?, #0x5, lsl 0
+	madd w141?, w130?, w285?, wzr
+	orr w284?, wzr, #0x6
+	madd w143?, w130?, w284?, wzr
+	orr w283?, wzr, #0x7
+	madd w145?, w130?, w283?, wzr
+	orr w282?, wzr, #0x8
+	madd w147?, w130?, w282?, wzr
+	movz w281?, #0x9, lsl 0
+	madd w149?, w130?, w281?, wzr
+	movz w280?, #0xa, lsl 0
+	madd w151?, w130?, w280?, wzr
+	movz w279?, #0xb, lsl 0
+	madd w153?, w130?, w279?, wzr
+	orr w278?, wzr, #0xc
+	madd w155?, w130?, w278?, wzr
+	movz w277?, #0xd, lsl 0
+	madd w157?, w130?, w277?, wzr
+	orr w276?, wzr, #0xe
+	madd w159?, w130?, w276?, wzr
+	orr w275?, wzr, #0xf
+	madd w161?, w130?, w275?, wzr
+	orr w274?, wzr, #0x10
+	madd w163?, w130?, w274?, wzr
+	movz w273?, #0x11, lsl 0
+	madd w165?, w130?, w273?, wzr
+	movz w272?, #0x12, lsl 0
+	madd w167?, w130?, w272?, wzr
+	movz w271?, #0x13, lsl 0
+	madd w169?, w130?, w271?, wzr
+	movz w270?, #0x14, lsl 0
+	madd w171?, w130?, w270?, wzr
+	add w172?, w169?, w171?
+	add w173?, w167?, w172?
+	add w174?, w165?, w173?
+	add w175?, w163?, w174?
+	add w176?, w161?, w175?
+	add w177?, w159?, w176?
+	add w178?, w157?, w177?
+	add w179?, w155?, w178?
+	add w180?, w153?, w179?
+	add w181?, w151?, w180?
+	add w182?, w149?, w181?
+	add w183?, w147?, w182?
+	add w184?, w145?, w183?
+	add w185?, w143?, w184?
+	add w186?, w141?, w185?
+	add w187?, w139?, w186?
+	add w188?, w137?, w187?
+	add w189?, w135?, w188?
+	add w190?, w133?, w189?
+	ldr s269?, #8; b 8; data.f32 1.000000
+	fmul s192?, s131?, s269?
+	ldr s268?, #8; b 8; data.f32 2.000000
+	fmul s194?, s131?, s268?
+	ldr s267?, #8; b 8; data.f32 3.000000
+	fmul s196?, s131?, s267?
+	ldr s266?, #8; b 8; data.f32 4.000000
+	fmul s198?, s131?, s266?
+	ldr s265?, #8; b 8; data.f32 5.000000
+	fmul s200?, s131?, s265?
+	ldr s264?, #8; b 8; data.f32 6.000000
+	fmul s202?, s131?, s264?
+	ldr s263?, #8; b 8; data.f32 7.000000
+	fmul s204?, s131?, s263?
+	ldr s262?, #8; b 8; data.f32 8.000000
+	fmul s206?, s131?, s262?
+	ldr s261?, #8; b 8; data.f32 9.000000
+	fmul s208?, s131?, s261?
+	ldr s260?, #8; b 8; data.f32 10.000000
+	fmul s210?, s131?, s260?
+	ldr s259?, #8; b 8; data.f32 11.000000
+	fmul s212?, s131?, s259?
+	ldr s258?, #8; b 8; data.f32 12.000000
+	fmul s214?, s131?, s258?
+	ldr s257?, #8; b 8; data.f32 13.000000
+	fmul s216?, s131?, s257?
+	ldr s256?, #8; b 8; data.f32 14.000000
+	fmul s218?, s131?, s256?
+	ldr s255?, #8; b 8; data.f32 15.000000
+	fmul s220?, s131?, s255?
+	ldr s254?, #8; b 8; data.f32 16.000000
+	fmul s222?, s131?, s254?
+	ldr s253?, #8; b 8; data.f32 17.000000
+	fmul s224?, s131?, s253?
+	ldr s252?, #8; b 8; data.f32 18.000000
+	fmul s226?, s131?, s252?
+	ldr s251?, #8; b 8; data.f32 19.000000
+	fmul s228?, s131?, s251?
+	ldr s250?, #8; b 8; data.f32 20.000000
+	fmul s230?, s131?, s250?
+	fadd s231?, s228?, s230?
+	fadd s232?, s226?, s231?
+	fadd s233?, s224?, s232?
+	fadd s234?, s222?, s233?
+	fadd s235?, s220?, s234?
+	fadd s236?, s218?, s235?
+	fadd s237?, s216?, s236?
+	fadd s238?, s214?, s237?
+	fadd s239?, s212?, s238?
+	fadd s240?, s210?, s239?
+	fadd s241?, s208?, s240?
+	fadd s242?, s206?, s241?
+	fadd s243?, s204?, s242?
+	fadd s244?, s202?, s243?
+	fadd s245?, s200?, s244?
+	fadd s246?, s198?, s245?
+	fadd s247?, s196?, s246?
+	fadd s248?, s194?, s247?
+	fadd s249?, s192?, s248?
+	mov v0.8b, v249?.8b
+	mov x0, x190?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -1604,19 +1604,19 @@ L1 (SSA Block: blk0):
 			name: "imported_function_call", m: testcases.ImportedFunctionCall.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x0?, x0
-	mov x1?, x1
-	mov x2?, x2
-	str x1?, [x0?, #0x8]
-	ldr x3?, [x1?, #0x8]
-	ldr x4?, [x1?, #0x10]
-	mov x0, x0?
-	mov x1, x4?
-	mov x2, x2?
-	mov x3, x2?
-	bl x3?
-	mov x5?, x0
-	mov x0, x5?
+	mov x128?, x0
+	mov x129?, x1
+	mov x130?, x2
+	str x129?, [x128?, #0x8]
+	ldr x131?, [x129?, #0x8]
+	ldr x132?, [x129?, #0x10]
+	mov x0, x128?
+	mov x1, x132?
+	mov x2, x130?
+	mov x3, x130?
+	bl x131?
+	mov x133?, x0
+	mov x0, x133?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -1638,26 +1638,26 @@ L1 (SSA Block: blk0):
 			name: "memory_load_basic", m: testcases.MemoryLoadBasic.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x0?, x0
-	mov x1?, x1
-	mov x2?, x2
-	uxtw x4?, w2?
-	ldr w5?, [x1?, #0x10]
-	add x6?, x4?, #0x4
-	subs xzr, x5?, x6?
+	mov x128?, x0
+	mov x129?, x1
+	mov x130?, x2
+	uxtw x132?, w130?
+	ldr w133?, [x129?, #0x10]
+	add x134?, x132?, #0x4
+	subs xzr, x133?, x134?
 	b.hs L2
-	movz x12?, #0x4, lsl 0
-	str w12?, [x0?]
-	mov x13?, sp
-	str x13?, [x0?, #0x38]
-	adr x14?, #0x0
-	str x14?, [x0?, #0x30]
-	exit_sequence x0?
+	movz x140?, #0x4, lsl 0
+	str w140?, [x128?]
+	mov x141?, sp
+	str x141?, [x128?, #0x38]
+	adr x142?, #0x0
+	str x142?, [x128?, #0x30]
+	exit_sequence x128?
 L2:
-	ldr x8?, [x1?, #0x8]
-	add x11?, x8?, x4?
-	ldr w10?, [x11?]
-	mov x0, x10?
+	ldr x136?, [x129?, #0x8]
+	add x139?, x136?, x132?
+	ldr w138?, [x139?]
+	mov x0, x138?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -1838,36 +1838,36 @@ L2:
 			m:    testcases.GlobalsMutable.Module,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x0?, x0
-	mov x1?, x1
-	ldr x2?, [x1?, #0x8]
-	ldr w3?, [x2?, #0x8]
-	ldr x4?, [x1?, #0x10]
-	ldr x5?, [x4?, #0x8]
-	ldr x6?, [x1?, #0x18]
-	ldr s7?, [x6?, #0x8]
-	ldr x8?, [x1?, #0x20]
-	ldr d9?, [x8?, #0x8]
-	str x1?, [x0?, #0x8]
-	mov x0, x0?
-	mov x1, x1?
+	mov x128?, x0
+	mov x129?, x1
+	ldr x130?, [x129?, #0x8]
+	ldr w131?, [x130?, #0x8]
+	ldr x132?, [x129?, #0x10]
+	ldr x133?, [x132?, #0x8]
+	ldr x134?, [x129?, #0x18]
+	ldr s135?, [x134?, #0x8]
+	ldr x136?, [x129?, #0x20]
+	ldr d137?, [x136?, #0x8]
+	str x129?, [x128?, #0x8]
+	mov x0, x128?
+	mov x1, x129?
 	bl f1
-	ldr x10?, [x1?, #0x8]
-	ldr w11?, [x10?, #0x8]
-	ldr x12?, [x1?, #0x10]
-	ldr x13?, [x12?, #0x8]
-	ldr x14?, [x1?, #0x18]
-	ldr s15?, [x14?, #0x8]
-	ldr x16?, [x1?, #0x20]
-	ldr d17?, [x16?, #0x8]
-	mov v3.8b, v17?.8b
-	mov v2.8b, v15?.8b
-	mov x3, x13?
-	mov x2, x11?
-	mov v1.8b, v9?.8b
-	mov v0.8b, v7?.8b
-	mov x1, x5?
-	mov x0, x3?
+	ldr x138?, [x129?, #0x8]
+	ldr w139?, [x138?, #0x8]
+	ldr x140?, [x129?, #0x10]
+	ldr x141?, [x140?, #0x8]
+	ldr x142?, [x129?, #0x18]
+	ldr s143?, [x142?, #0x8]
+	ldr x144?, [x129?, #0x20]
+	ldr d145?, [x144?, #0x8]
+	mov v3.8b, v145?.8b
+	mov v2.8b, v143?.8b
+	mov x3, x141?
+	mov x2, x139?
+	mov v1.8b, v137?.8b
+	mov v0.8b, v135?.8b
+	mov x1, x133?
+	mov x0, x131?
 	ret
 `,
 			afterFinalizeARM64: `
@@ -1920,19 +1920,19 @@ L1 (SSA Block: blk0):
 			targetIndex: 1,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x1?, x1
-	ldr x3?, [x1?, #0x8]
-	orr w13?, wzr, #0x1
-	str w13?, [x3?, #0x8]
-	ldr x5?, [x1?, #0x10]
-	orr x12?, xzr, #0x2
-	str x12?, [x5?, #0x8]
-	ldr x7?, [x1?, #0x18]
-	ldr s11?, #8; b 8; data.f32 3.000000
-	str s11?, [x7?, #0x8]
-	ldr x9?, [x1?, #0x20]
-	ldr d10?, #8; b 16; data.f64 4.000000
-	str d10?, [x9?, #0x8]
+	mov x129?, x1
+	ldr x131?, [x129?, #0x8]
+	orr w141?, wzr, #0x1
+	str w141?, [x131?, #0x8]
+	ldr x133?, [x129?, #0x10]
+	orr x140?, xzr, #0x2
+	str x140?, [x133?, #0x8]
+	ldr x135?, [x129?, #0x18]
+	ldr s139?, #8; b 8; data.f32 3.000000
+	str s139?, [x135?, #0x8]
+	ldr x137?, [x129?, #0x20]
+	ldr d138?, #8; b 16; data.f64 4.000000
+	str d138?, [x137?, #0x8]
 	ret
 `,
 			afterFinalizeARM64: `
@@ -1962,42 +1962,42 @@ L1 (SSA Block: blk0):
 			targetIndex: 0,
 			afterLoweringARM64: `
 L1 (SSA Block: blk0):
-	mov x2?, x2
-	orr w9?, wzr, #0x6
-	subs wzr, w2?, w9?
-	csel w10?, w9?, w2?, hs
-	br_table_sequence x10?, [L2, L3, L4, L5, L6, L7, L8]
+	mov x130?, x2
+	orr w137?, wzr, #0x6
+	subs wzr, w130?, w137?
+	csel w138?, w137?, w130?, hs
+	br_table_sequence x138?, [L2, L3, L4, L5, L6, L7, L8]
 L2 (SSA Block: blk7):
 	b L9
 L3 (SSA Block: blk8):
 L10 (SSA Block: blk5):
-	orr w3?, wzr, #0xc
-	mov x0, x3?
+	orr w131?, wzr, #0xc
+	mov x0, x131?
 	ret
 L4 (SSA Block: blk9):
 L11 (SSA Block: blk4):
-	movz w4?, #0xd, lsl 0
-	mov x0, x4?
+	movz w132?, #0xd, lsl 0
+	mov x0, x132?
 	ret
 L5 (SSA Block: blk10):
 L12 (SSA Block: blk3):
-	orr w5?, wzr, #0xe
-	mov x0, x5?
+	orr w133?, wzr, #0xe
+	mov x0, x133?
 	ret
 L6 (SSA Block: blk11):
 L13 (SSA Block: blk2):
-	orr w6?, wzr, #0xf
-	mov x0, x6?
+	orr w134?, wzr, #0xf
+	mov x0, x134?
 	ret
 L7 (SSA Block: blk12):
 L14 (SSA Block: blk1):
-	orr w7?, wzr, #0x10
-	mov x0, x7?
+	orr w135?, wzr, #0x10
+	mov x0, x135?
 	ret
 L8 (SSA Block: blk13):
 L9 (SSA Block: blk6):
-	movz w8?, #0xb, lsl 0
-	mov x0, x8?
+	movz w136?, #0xb, lsl 0
+	mov x0, x136?
 	ret
 `,
 			afterFinalizeARM64: `
diff --git a/internal/engine/wazevo/backend/isa/arm64/lower_constant_test.go b/internal/engine/wazevo/backend/isa/arm64/lower_constant_test.go
index 92cc5efc..34383c81 100644
--- a/internal/engine/wazevo/backend/isa/arm64/lower_constant_test.go
+++ b/internal/engine/wazevo/backend/isa/arm64/lower_constant_test.go
@@ -19,10 +19,10 @@ func TestMachine_lowerConstant(t *testing.T) {
 
 		vr := m.lowerConstant(ssaConstInstr)
 		machInstr := getPendingInstr(m)
-		require.Equal(t, regalloc.VRegID(0), vr.ID())
+		require.Equal(t, regalloc.VRegIDNonReservedBegin, vr.ID())
 		require.Equal(t, regalloc.RegTypeInt, vr.RegType())
 		require.Equal(t, mov64, machInstr.kind)
-		require.Equal(t, "mov x0?, xzr", formatEmittedInstructionsInCurrentBlock(m))
+		require.Equal(t, "mov x128?, xzr", formatEmittedInstructionsInCurrentBlock(m))
 	})
 
 	t.Run("zero i64", func(t *testing.T) {
@@ -33,10 +33,10 @@ func TestMachine_lowerConstant(t *testing.T) {
 
 		vr := m.lowerConstant(ssaConstInstr)
 		machInstr := getPendingInstr(m)
-		require.Equal(t, regalloc.VRegID(0), vr.ID())
+		require.Equal(t, regalloc.VRegIDNonReservedBegin, vr.ID())
 		require.Equal(t, regalloc.RegTypeInt, vr.RegType())
 		require.Equal(t, mov64, machInstr.kind)
-		require.Equal(t, "mov x0?, xzr", formatEmittedInstructionsInCurrentBlock(m))
+		require.Equal(t, "mov x128?, xzr", formatEmittedInstructionsInCurrentBlock(m))
 	})
 
 	t.Run("TypeF32", func(t *testing.T) {
@@ -47,12 +47,12 @@ func TestMachine_lowerConstant(t *testing.T) {
 
 		vr := m.lowerConstant(ssaConstInstr)
 		machInstr := getPendingInstr(m)
-		require.Equal(t, regalloc.VRegID(0), vr.ID())
+		require.Equal(t, regalloc.VRegIDNonReservedBegin, vr.ID())
 		require.Equal(t, regalloc.RegTypeFloat, vr.RegType())
 		require.Equal(t, loadFpuConst32, machInstr.kind)
 		require.Equal(t, uint64(math.Float32bits(1.1234)), machInstr.u1)
 
-		require.Equal(t, "ldr s0?, #8; b 8; data.f32 1.123400", formatEmittedInstructionsInCurrentBlock(m))
+		require.Equal(t, "ldr s128?, #8; b 8; data.f32 1.123400", formatEmittedInstructionsInCurrentBlock(m))
 	})
 
 	t.Run("TypeF64", func(t *testing.T) {
@@ -63,12 +63,12 @@ func TestMachine_lowerConstant(t *testing.T) {
 
 		vr := m.lowerConstant(ssaConstInstr)
 		machInstr := getPendingInstr(m)
-		require.Equal(t, regalloc.VRegID(0), vr.ID())
+		require.Equal(t, regalloc.VRegIDNonReservedBegin, vr.ID())
 		require.Equal(t, regalloc.RegTypeFloat, vr.RegType())
 		require.Equal(t, loadFpuConst64, machInstr.kind)
 		require.Equal(t, math.Float64bits(-9471.2), machInstr.u1)
 
-		require.Equal(t, "ldr d0?, #8; b 16; data.f64 -9471.200000", formatEmittedInstructionsInCurrentBlock(m))
+		require.Equal(t, "ldr d128?, #8; b 16; data.f64 -9471.200000", formatEmittedInstructionsInCurrentBlock(m))
 	})
 }
 
diff --git a/internal/engine/wazevo/backend/regalloc/reg_test.go b/internal/engine/wazevo/backend/regalloc/reg_test.go
index ba311e61..7c48200a 100644
--- a/internal/engine/wazevo/backend/regalloc/reg_test.go
+++ b/internal/engine/wazevo/backend/regalloc/reg_test.go
@@ -23,5 +23,5 @@ func TestVReg_String(t *testing.T) {
 func Test_FromRealReg(t *testing.T) {
 	r := FromRealReg(5, RegTypeInt)
 	require.Equal(t, RealReg(5), r.RealReg())
-	require.Equal(t, VRegID(vRegIDReservedForRealBegin+5), r.ID())
+	require.Equal(t, VRegID(5), r.ID())
 }