Repository: tetratelabs/wazero
Pull request #1741 (2023-10-01 23:17:41)

wazevo(arm64): make rd come first in asALUBitmaskImm
for consistency 

#1496 


Patch:
diff --git a/internal/engine/wazevo/backend/isa/arm64/instr.go b/internal/engine/wazevo/backend/isa/arm64/instr.go
index e48b51cf..f0d6138d 100644
--- a/internal/engine/wazevo/backend/isa/arm64/instr.go
+++ b/internal/engine/wazevo/backend/isa/arm64/instr.go
@@ -694,7 +694,7 @@ func (i *instruction) asALUShift(aluOp aluOp, rd, rn, rm operand, dst64bit bool)
 	}
 }
 
-func (i *instruction) asALUBitmaskImm(aluOp aluOp, rn, rd regalloc.VReg, imm uint64, dst64bit bool) {
+func (i *instruction) asALUBitmaskImm(aluOp aluOp, rd, rn regalloc.VReg, imm uint64, dst64bit bool) {
 	i.kind = aluRRBitmaskImm
 	i.u1 = uint64(aluOp)
 	i.rn, i.rd = operandNR(rn), operandNR(rd)
diff --git a/internal/engine/wazevo/backend/isa/arm64/lower_constant.go b/internal/engine/wazevo/backend/isa/arm64/lower_constant.go
index ff3fc9fe..c2b156ad 100644
--- a/internal/engine/wazevo/backend/isa/arm64/lower_constant.go
+++ b/internal/engine/wazevo/backend/isa/arm64/lower_constant.go
@@ -109,7 +109,7 @@ func (m *machine) lowerConstantI64(dst regalloc.VReg, c int64) {
 
 func (m *machine) lowerConstViaBitMaskImmediate(c uint64, dst regalloc.VReg, b64 bool) {
 	instr := m.allocateInstr()
-	instr.asALUBitmaskImm(aluOpOrr, xzrVReg, dst, c, b64)
+	instr.asALUBitmaskImm(aluOpOrr, dst, xzrVReg, c, b64)
 	m.insert(instr)
 }
 
diff --git a/internal/engine/wazevo/backend/isa/arm64/lower_instr.go b/internal/engine/wazevo/backend/isa/arm64/lower_instr.go
index 236e72e7..1fac1dc1 100644
--- a/internal/engine/wazevo/backend/isa/arm64/lower_instr.go
+++ b/internal/engine/wazevo/backend/isa/arm64/lower_instr.go
@@ -587,7 +587,7 @@ func (m *machine) lowerVShift(op ssa.Opcode, rd, rn, rm operand, arr vecArrangem
 	tmp := operandNR(m.compiler.AllocateVReg(regalloc.RegTypeFloat))
 
 	and := m.allocateInstr()
-	and.asALUBitmaskImm(aluOpAnd, rm.nr(), tmp.nr(), uint64(modulo), false)
+	and.asALUBitmaskImm(aluOpAnd, tmp.nr(), rm.nr(), uint64(modulo), false)
 	m.insert(and)
 
 	if op != ssa.OpcodeVIshl {


Test patch:
diff --git a/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go b/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go
index 8c849e87..574ca40a 100644
--- a/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go
+++ b/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go
@@ -1087,61 +1087,61 @@ func TestInstruction_encode(t *testing.T) {
 		{want: "5255f5f2", setup: func(i *instruction) { i.asMOVK(x18VReg, 0xaaaa, 3, true) }},
 		{want: "5255b552", setup: func(i *instruction) { i.asMOVZ(x18VReg, 0xaaaa, 1, false) }},
 		{want: "5255f5d2", setup: func(i *instruction) { i.asMOVZ(x18VReg, 0xaaaa, 3, true) }},
-		{want: "4f020012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x1, false) }},
-		{want: "4f0a0012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x7, false) }},
-		{want: "4f0e0012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0xf, false) }},
-		{want: "4f120012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x1f, false) }},
-		{want: "4f160012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x3f, false) }},
-		{want: "4f021112", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x8000, false) }},
-		{want: "4f721f12", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x3ffffffe, false) }},
-		{want: "4f7a1f12", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0xfffffffe, false) }},
-		{want: "4f024092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x1, true) }},
-		{want: "4f0a4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x7, true) }},
-		{want: "4f0e4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0xf, true) }},
-		{want: "4f124092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x1f, true) }},
-		{want: "4f164092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x3f, true) }},
-		{want: "4f4e4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0xfffff, true) }},
-		{want: "4f7e7092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0xffffffff0000, true) }},
-		{want: "4f7a4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x7fffffff, true) }},
-		{want: "4f767f92", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0x7ffffffe, true) }},
-		{want: "4fba7f92", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x18VReg, x15VReg, 0xfffffffffffe, true) }},
-		{want: "4f020032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x1, false) }},
-		{want: "4f0a0032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x7, false) }},
-		{want: "4f0e0032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0xf, false) }},
-		{want: "4f120032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x1f, false) }},
-		{want: "4f160032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x3f, false) }},
-		{want: "4f021132", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x8000, false) }},
-		{want: "4f721f32", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x3ffffffe, false) }},
-		{want: "4f7a1f32", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0xfffffffe, false) }},
-		{want: "4f0240b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x1, true) }},
-		{want: "4f0a40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x7, true) }},
-		{want: "4f0e40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0xf, true) }},
-		{want: "4f1240b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x1f, true) }},
-		{want: "4f1640b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x3f, true) }},
-		{want: "4f4e40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0xfffff, true) }},
-		{want: "4f7e70b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0xffffffff0000, true) }},
-		{want: "4f7a40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x7fffffff, true) }},
-		{want: "4f767fb2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0x7ffffffe, true) }},
-		{want: "4fba7fb2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, x15VReg, 0xfffffffffffe, true) }},
-		{want: "4f020052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x1, false) }},
-		{want: "4f0a0052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x7, false) }},
-		{want: "4f0e0052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0xf, false) }},
-		{want: "4f120052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x1f, false) }},
-		{want: "4f160052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x3f, false) }},
-		{want: "4f021152", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x8000, false) }},
-		{want: "4f721f52", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x3ffffffe, false) }},
-		{want: "4f7a1f52", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0xfffffffe, false) }},
-		{want: "4f0240d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x1, true) }},
-		{want: "4f0a40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x7, true) }},
-		{want: "4f0e40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0xf, true) }},
-		{want: "4f1240d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x1f, true) }},
-		{want: "4f1640d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x3f, true) }},
-		{want: "4f4e40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0xfffff, true) }},
-		{want: "4f7e70d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0xffffffff0000, true) }},
-		{want: "4f7a40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x7fffffff, true) }},
-		{want: "4f767fd2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0x7ffffffe, true) }},
-		{want: "4fba7fd2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x18VReg, x15VReg, 0xfffffffffffe, true) }},
-		{want: "f20300b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, xzrVReg, x18VReg, 0x100000001, true) }},
+		{want: "4f020012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1, false) }},
+		{want: "4f0a0012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7, false) }},
+		{want: "4f0e0012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xf, false) }},
+		{want: "4f120012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1f, false) }},
+		{want: "4f160012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x3f, false) }},
+		{want: "4f021112", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x8000, false) }},
+		{want: "4f721f12", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x3ffffffe, false) }},
+		{want: "4f7a1f12", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xfffffffe, false) }},
+		{want: "4f024092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1, true) }},
+		{want: "4f0a4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7, true) }},
+		{want: "4f0e4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xf, true) }},
+		{want: "4f124092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1f, true) }},
+		{want: "4f164092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x3f, true) }},
+		{want: "4f4e4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xfffff, true) }},
+		{want: "4f7e7092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xffffffff0000, true) }},
+		{want: "4f7a4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7fffffff, true) }},
+		{want: "4f767f92", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7ffffffe, true) }},
+		{want: "4fba7f92", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xfffffffffffe, true) }},
+		{want: "4f020032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1, false) }},
+		{want: "4f0a0032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7, false) }},
+		{want: "4f0e0032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xf, false) }},
+		{want: "4f120032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1f, false) }},
+		{want: "4f160032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x3f, false) }},
+		{want: "4f021132", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x8000, false) }},
+		{want: "4f721f32", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x3ffffffe, false) }},
+		{want: "4f7a1f32", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xfffffffe, false) }},
+		{want: "4f0240b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1, true) }},
+		{want: "4f0a40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7, true) }},
+		{want: "4f0e40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xf, true) }},
+		{want: "4f1240b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1f, true) }},
+		{want: "4f1640b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x3f, true) }},
+		{want: "4f4e40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xfffff, true) }},
+		{want: "4f7e70b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xffffffff0000, true) }},
+		{want: "4f7a40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7fffffff, true) }},
+		{want: "4f767fb2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7ffffffe, true) }},
+		{want: "4fba7fb2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xfffffffffffe, true) }},
+		{want: "4f020052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1, false) }},
+		{want: "4f0a0052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7, false) }},
+		{want: "4f0e0052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xf, false) }},
+		{want: "4f120052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1f, false) }},
+		{want: "4f160052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x3f, false) }},
+		{want: "4f021152", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x8000, false) }},
+		{want: "4f721f52", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x3ffffffe, false) }},
+		{want: "4f7a1f52", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xfffffffe, false) }},
+		{want: "4f0240d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1, true) }},
+		{want: "4f0a40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7, true) }},
+		{want: "4f0e40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xf, true) }},
+		{want: "4f1240d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1f, true) }},
+		{want: "4f1640d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x3f, true) }},
+		{want: "4f4e40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xfffff, true) }},
+		{want: "4f7e70d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xffffffff0000, true) }},
+		{want: "4f7a40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7fffffff, true) }},
+		{want: "4f767fd2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7ffffffe, true) }},
+		{want: "4fba7fd2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xfffffffffffe, true) }},
+		{want: "f20300b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, xzrVReg, 0x100000001, true) }},
 		{want: "f21fbf0e", setup: func(i *instruction) { i.asFpuMov64(v18VReg, v31VReg) }},
 		{want: "f21fbf4e", setup: func(i *instruction) { i.asFpuMov128(v18VReg, v31VReg) }},
 		{want: "40a034ab", setup: func(i *instruction) {