Repository: tetratelabs/wazero
Pull request #587 (2022-05-23 06:59:49)

Follows go style for arm64 constants.
Signed-off-by: Anuraag Agrawal <anuraaga@gmail.com>

Similar to #586 

This also removes two instructions that were unused, `RNG` and `UXTW`, which didn't have corresponding instructions in the arm64 specification.


Patch:
diff --git a/internal/asm/arm64/consts.go b/internal/asm/arm64/consts.go
index f235597a..05f3f92b 100644
--- a/internal/asm/arm64/consts.go
+++ b/internal/asm/arm64/consts.go
@@ -9,22 +9,38 @@ import (
 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm
 // See https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/condition-codes-1-condition-flags-and-codes
 const (
-	COND_EQ asm.ConditionalRegisterState = asm.ConditionalRegisterStateUnset + 1 + iota
-	COND_NE
-	COND_HS
-	COND_LO
-	COND_MI
-	COND_PL
-	COND_VS
-	COND_VC
-	COND_HI
-	COND_LS
-	COND_GE
-	COND_LT
-	COND_GT
-	COND_LE
-	COND_AL
-	COND_NV
+	// CondEQ is the eq (equal) condition code
+	CondEQ asm.ConditionalRegisterState = asm.ConditionalRegisterStateUnset + 1 + iota
+	// CondNE is the ne (not equal) condition code
+	CondNE
+	// CondHS is the hs (unsigned higher or same) condition code
+	CondHS
+	// CondLO is the lo (unsigned lower) condition code
+	CondLO
+	// CondMI is the mi (negative) condition code
+	CondMI
+	// CondPL is the pl (positive or zero) condition code
+	CondPL
+	// CondVS is the vs (signed overflow) condition code
+	CondVS
+	// CondVC is the vc (no signed overflow) condition code
+	CondVC
+	// CondHI is the hi (unsigned higher) condition code
+	CondHI
+	// CondLS is the ls (unsigned lower or same) condition code
+	CondLS
+	// CondGE is the ge (signed greater than or equal) condition code
+	CondGE
+	// CondLT is the lt (signed less than) condition code
+	CondLT
+	// CondGT is the gt (signed greater than) condition code
+	CondGT
+	// CondLE is the le (signed less than or equal) condition code
+	CondLE
+	// CondAL is the al (always executed) condition code
+	CondAL
+	// CondNV has the same meaning as CondAL
+	CondNV
 )
 
 // Arm64-specific registers.
@@ -34,305 +50,389 @@ const (
 const (
 	// Integer registers.
 
-	REG_R0 asm.Register = asm.NilRegister + 1 + iota
-	REG_R1
-	REG_R2
-	REG_R3
-	REG_R4
-	REG_R5
-	REG_R6
-	REG_R7
-	REG_R8
-	REG_R9
-	REG_R10
-	REG_R11
-	REG_R12
-	REG_R13
-	REG_R14
-	REG_R15
-	REG_R16
-	REG_R17
-	REG_R18
-	REG_R19
-	REG_R20
-	REG_R21
-	REG_R22
-	REG_R23
-	REG_R24
-	REG_R25
-	REG_R26
-	REG_R27
-	REG_R28
-	REG_R29
-	REG_R30
-	REGZERO
+	// RegR0 is the R0 register
+	RegR0 asm.Register = asm.NilRegister + 1 + iota
+	// RegR1 is the R1 register
+	RegR1
+	// RegR2 is the R2 register
+	RegR2
+	// RegR3 is the R3 register
+	RegR3
+	// RegR4 is the R4 register
+	RegR4
+	// RegR5 is the R5 register
+	RegR5
+	// RegR6 is the R6 register
+	RegR6
+	// RegR7 is the R7 register
+	RegR7
+	// RegR8 is the R8 register
+	RegR8
+	// RegR9 is the R9 register
+	RegR9
+	// RegR10 is the R10 register
+	RegR10
+	// RegR11 is the R11 register
+	RegR11
+	// RegR12 is the R12 register
+	RegR12
+	// RegR13 is the R13 register
+	RegR13
+	// RegR14 is the R14 register
+	RegR14
+	// RegR15 is the R15 register
+	RegR15
+	// RegR16 is the R16 register
+	RegR16
+	// RegR17 is the R17 register
+	RegR17
+	// RegR18 is the R18 register
+	RegR18
+	// RegR19 is the R19 register
+	RegR19
+	// RegR20 is the R20 register
+	RegR20
+	// RegR21 is the R21 register
+	RegR21
+	// RegR22 is the R22 register
+	RegR22
+	// RegR23 is the R23 register
+	RegR23
+	// RegR24 is the R24 register
+	RegR24
+	// RegR25 is the R25 register
+	RegR25
+	// RegR26 is the R26 register
+	RegR26
+	// RegR27 is the R27 register
+	RegR27
+	// RegR28 is the R28 register
+	RegR28
+	// RegR29 is the R29 register
+	RegR29
+	// RegR30 is the R30 register
+	RegR30
+	// RegRZR is the RZR register (read-only, always returning zero)
+	RegRZR
 
 	// Scalar floating point registers.
 
-	REG_V0
-	REG_V1
-	REG_V2
-	REG_V3
-	REG_V4
-	REG_V5
-	REG_V6
-	REG_V7
-	REG_V8
-	REG_V9
-	REG_V10
-	REG_V11
-	REG_V12
-	REG_V13
-	REG_V14
-	REG_V15
-	REG_V16
-	REG_V17
-	REG_V18
-	REG_V19
-	REG_V20
-	REG_V21
-	REG_V22
-	REG_V23
-	REG_V24
-	REG_V25
-	REG_V26
-	REG_V27
-	REG_V28
-	REG_V29
-	REG_V30
-	REG_V31
+	// RegV0 is the V0 register
+	RegV0
+	// RegV1 is the V1 register
+	RegV1
+	// RegV2 is the V2 register
+	RegV2
+	// RegV3 is the V3 register
+	RegV3
+	// RegV4 is the V4 register
+	RegV4
+	// RegV5 is the V5 register
+	RegV5
+	// RegV6 is the V6 register
+	RegV6
+	// RegV7 is the V7 register
+	RegV7
+	// RegV8 is the V8 register
+	RegV8
+	// RegV9 is the V9 register
+	RegV9
+	// RegV10 is the V10 register
+	RegV10
+	// RegV11 is the V11 register
+	RegV11
+	// RegV12 is the V12 register
+	RegV12
+	// RegV13 is the V13 register
+	RegV13
+	// RegV14 is the V14 register
+	RegV14
+	// RegV15 is the V15 register
+	RegV15
+	// RegV16 is the V16 register
+	RegV16
+	// RegV17 is the V17 register
+	RegV17
+	// RegV18 is the V18 register
+	RegV18
+	// RegV19 is the V19 register
+	RegV19
+	// RegV20 is the V20 register
+	RegV20
+	// RegV21 is the V21 register
+	RegV21
+	// RegV22 is the V22 register
+	RegV22
+	// RegV23 is the V23 register
+	RegV23
+	// RegV24 is the V24 register
+	RegV24
+	// RegV25 is the V25 register
+	RegV25
+	// RegV26 is the V26 register
+	RegV26
+	// RegV27 is the V27 register
+	RegV27
+	// RegV28 is the V28 register
+	RegV28
+	// RegV29 is the V29 register
+	RegV29
+	// RegV30 is the V30 register
+	RegV30
+	// RegV31 is the V31 register
+	RegV31
 
 	// Floating point status register.
 
-	REG_FPSR
+	// RegFPSR is the FPSR register
+	RegFPSR
 
 	// Assign each conditional register state to the unique register ID.
 	// This is to reduce the size of NodeImpl struct without having dedicated field
 	// for conditional register state which would not be used by most nodes.
+	// This is taking advantage of the fact that conditional operations are always
+	// on a single register and condition code, and never two registers.
 
-	REG_COND_EQ
-	REG_COND_NE
-	REG_COND_HS
-	REG_COND_LO
-	REG_COND_MI
-	REG_COND_PL
-	REG_COND_VS
-	REG_COND_VC
-	REG_COND_HI
-	REG_COND_LS
-	REG_COND_GE
-	REG_COND_LT
-	REG_COND_GT
-	REG_COND_LE
-	REG_COND_AL
-	REG_COND_NV
+	// RegCondEQ encodes CondEQ into a field that would otherwise store a register
+	RegCondEQ
+	// RegCondNE encodes CondNE into a field that would otherwise store a register
+	RegCondNE
+	// RegCondHS encodes CondHS into a field that would otherwise store a register
+	RegCondHS
+	// RegCondLO encodes CondLO into a field that would otherwise store a register
+	RegCondLO
+	// RegCondMI encodes CondMI into a field that would otherwise store a register
+	RegCondMI
+	// RegCondPL encodes CondPL into a field that would otherwise store a register
+	RegCondPL
+	// RegCondVS encodes CondVS into a field that would otherwise store a register
+	RegCondVS
+	// RegCondVC encodes CondVC into a field that would otherwise store a register
+	RegCondVC
+	// RegCondHI encodes CondHI into a field that would otherwise store a register
+	RegCondHI
+	// RegCondLS encodes CondLS into a field that would otherwise store a register
+	RegCondLS
+	// RegCondGE encodes CondGE into a field that would otherwise store a register
+	RegCondGE
+	// RegCondLT encodes CondLT into a field that would otherwise store a register
+	RegCondLT
+	// RegCondGT encodes CondGT into a field that would otherwise store a register
+	RegCondGT
+	// RegCondLE encodes CondLE into a field that would otherwise store a register
+	RegCondLE
+	// RegCondAL encodes CondAL into a field that would otherwise store a register
+	RegCondAL
+	// RegCondNV encodes CondNV into a field that would otherwise store a register
+	RegCondNV
 )
 
 // conditionalRegisterStateToRegister cast a conditional register to its unique register ID.
-// See the comment on REG_COND_EQ above.
+// See the comment on RegCondEQ above.
 func conditionalRegisterStateToRegister(c asm.ConditionalRegisterState) asm.Register {
 	switch c {
-	case COND_EQ:
-		return REG_COND_EQ
-	case COND_NE:
-		return REG_COND_NE
-	case COND_HS:
-		return REG_COND_HS
-	case COND_LO:
-		return REG_COND_LO
-	case COND_MI:
-		return REG_COND_MI
-	case COND_PL:
-		return REG_COND_PL
-	case COND_VS:
-		return REG_COND_VS
-	case COND_VC:
-		return REG_COND_VC
-	case COND_HI:
-		return REG_COND_HI
-	case COND_LS:
-		return REG_COND_LS
-	case COND_GE:
-		return REG_COND_GE
-	case COND_LT:
-		return REG_COND_LT
-	case COND_GT:
-		return REG_COND_GT
-	case COND_LE:
-		return REG_COND_LE
-	case COND_AL:
-		return REG_COND_AL
-	case COND_NV:
-		return REG_COND_NV
+	case CondEQ:
+		return RegCondEQ
+	case CondNE:
+		return RegCondNE
+	case CondHS:
+		return RegCondHS
+	case CondLO:
+		return RegCondLO
+	case CondMI:
+		return RegCondMI
+	case CondPL:
+		return RegCondPL
+	case CondVS:
+		return RegCondVS
+	case CondVC:
+		return RegCondVC
+	case CondHI:
+		return RegCondHI
+	case CondLS:
+		return RegCondLS
+	case CondGE:
+		return RegCondGE
+	case CondLT:
+		return RegCondLT
+	case CondGT:
+		return RegCondGT
+	case CondLE:
+		return RegCondLE
+	case CondAL:
+		return RegCondAL
+	case CondNV:
+		return RegCondNV
 	}
 	return asm.NilRegister
 }
 
+// RegisterName returns the name of a given register
 func RegisterName(r asm.Register) string {
 	switch r {
 	case asm.NilRegister:
 		return "nil"
-	case REG_R0:
+	case RegR0:
 		return "R0"
-	case REG_R1:
+	case RegR1:
 		return "R1"
-	case REG_R2:
+	case RegR2:
 		return "R2"
-	case REG_R3:
+	case RegR3:
 		return "R3"
-	case REG_R4:
+	case RegR4:
 		return "R4"
-	case REG_R5:
+	case RegR5:
 		return "R5"
-	case REG_R6:
+	case RegR6:
 		return "R6"
-	case REG_R7:
+	case RegR7:
 		return "R7"
-	case REG_R8:
+	case RegR8:
 		return "R8"
-	case REG_R9:
+	case RegR9:
 		return "R9"
-	case REG_R10:
+	case RegR10:
 		return "R10"
-	case REG_R11:
+	case RegR11:
 		return "R11"
-	case REG_R12:
+	case RegR12:
 		return "R12"
-	case REG_R13:
+	case RegR13:
 		return "R13"
-	case REG_R14:
+	case RegR14:
 		return "R14"
-	case REG_R15:
+	case RegR15:
 		return "R15"
-	case REG_R16:
+	case RegR16:
 		return "R16"
-	case REG_R17:
+	case RegR17:
 		return "R17"
-	case REG_R18:
+	case RegR18:
 		return "R18"
-	case REG_R19:
+	case RegR19:
 		return "R19"
-	case REG_R20:
+	case RegR20:
 		return "R20"
-	case REG_R21:
+	case RegR21:
 		return "R21"
-	case REG_R22:
+	case RegR22:
 		return "R22"
-	case REG_R23:
+	case RegR23:
 		return "R23"
-	case REG_R24:
+	case RegR24:
 		return "R24"
-	case REG_R25:
+	case RegR25:
 		return "R25"
-	case REG_R26:
+	case RegR26:
 		return "R26"
-	case REG_R27:
+	case RegR27:
 		return "R27"
-	case REG_R28:
+	case RegR28:
 		return "R28"
-	case REG_R29:
+	case RegR29:
 		return "R29"
-	case REG_R30:
+	case RegR30:
 		return "R30"
-	case REGZERO:
-		return "ZERO"
-	case REG_V0:
+	case RegRZR:
+		return "RZR"
+	case RegV0:
 		return "V0"
-	case REG_V1:
+	case RegV1:
 		return "V1"
-	case REG_V2:
+	case RegV2:
 		return "V2"
-	case REG_V3:
+	case RegV3:
 		return "V3"
-	case REG_V4:
+	case RegV4:
 		return "V4"
-	case REG_V5:
+	case RegV5:
 		return "V5"
-	case REG_V6:
+	case RegV6:
 		return "V6"
-	case REG_V7:
+	case RegV7:
 		return "V7"
-	case REG_V8:
+	case RegV8:
 		return "V8"
-	case REG_V9:
+	case RegV9:
 		return "V9"
-	case REG_V10:
+	case RegV10:
 		return "V10"
-	case REG_V11:
+	case RegV11:
 		return "V11"
-	case REG_V12:
+	case RegV12:
 		return "V12"
-	case REG_V13:
+	case RegV13:
 		return "V13"
-	case REG_V14:
+	case RegV14:
 		return "V14"
-	case REG_V15:
+	case RegV15:
 		return "V15"
-	case REG_V16:
+	case RegV16:
 		return "V16"
-	case REG_V17:
+	case RegV17:
 		return "V17"
-	case REG_V18:
+	case RegV18:
 		return "V18"
-	case REG_V19:
+	case RegV19:
 		return "V19"
-	case REG_V20:
+	case RegV20:
 		return "V20"
-	case REG_V21:
+	case RegV21:
 		return "V21"
-	case REG_V22:
+	case RegV22:
 		return "V22"
-	case REG_V23:
+	case RegV23:
 		return "V23"
-	case REG_V24:
+	case RegV24:
 		return "V24"
-	case REG_V25:
+	case RegV25:
 		return "V25"
-	case REG_V26:
+	case RegV26:
 		return "V26"
-	case REG_V27:
+	case RegV27:
 		return "V27"
-	case REG_V28:
+	case RegV28:
 		return "V28"
-	case REG_V29:
+	case RegV29:
 		return "V29"
-	case REG_V30:
+	case RegV30:
 		return "V30"
-	case REG_V31:
+	case RegV31:
 		return "V31"
-	case REG_FPSR:
+	case RegFPSR:
 		return "FPSR"
-	case REG_COND_EQ:
+	case RegCondEQ:
 		return "COND_EQ"
-	case REG_COND_NE:
+	case RegCondNE:
 		return "COND_NE"
-	case REG_COND_HS:
+	case RegCondHS:
 		return "COND_HS"
-	case REG_COND_LO:
+	case RegCondLO:
 		return "COND_LO"
-	case REG_COND_MI:
+	case RegCondMI:
 		return "COND_MI"
-	case REG_COND_PL:
+	case RegCondPL:
 		return "COND_PL"
-	case REG_COND_VS:
+	case RegCondVS:
 		return "COND_VS"
-	case REG_COND_VC:
+	case RegCondVC:
 		return "COND_VC"
-	case REG_COND_HI:
+	case RegCondHI:
 		return "COND_HI"
-	case REG_COND_LS:
+	case RegCondLS:
 		return "COND_LS"
-	case REG_COND_GE:
+	case RegCondGE:
 		return "COND_GE"
-	case REG_COND_LT:
+	case RegCondLT:
 		return "COND_LT"
-	case REG_COND_GT:
+	case RegCondGT:
 		return "COND_GT"
-	case REG_COND_LE:
+	case RegCondLE:
 		return "COND_LE"
-	case REG_COND_AL:
+	case RegCondAL:
 		return "COND_AL"
-	case REG_COND_NV:
+	case RegCondNV:
 		return "COND_NV"
 	}
 	return "UNKNOWN"
@@ -343,152 +443,296 @@ func RegisterName(r asm.Register) string {
 // Note: This only defines arm64 instructions used by wazero's compiler.
 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm
 const (
+	// NOP is the NOP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NOP
 	NOP asm.Instruction = iota
+	// RET is the RET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RET
 	RET
+	// ADD is the ADD instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register-
 	ADD
+	// ADDS is the ADDS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADDS--shifted-register-
 	ADDS
+	// ADDW is the ADD instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register-
 	ADDW
+	// ADR is the ADR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADR
 	ADR
+	// AND is the AND instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--shifted-register-
 	AND
+	// ANDW is the AND instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--register-
 	ANDW
+	// ASR is the ASR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register-
 	ASR
+	// ASRW is the ASR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register-
 	ASRW
+	// B is the B instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B
 	B
+	// BEQ is the B.cond instruction with CondEQ. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BEQ
+	// BGE is the B.cond instruction with CondGE. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BGE
+	// BGT is the B.cond instruction with CondGT. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BGT
+	// BHI is the B.cond instruction with CondHI. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BHI
+	// BHS is the B.cond instruction with CondHS. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BHS
+	// BLE is the B.cond instruction with CondLE. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BLE
+	// BLO is the B.cond instruction with CondLO. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BLO
+	// BLS is the B.cond instruction with CondLS. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BLS
+	// BLT is the B.cond instruction with CondLT. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BLT
+	// BMI is the B.cond instruction with CondMI. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BMI
+	// BPL is the B.cond instruction with CondPL. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BPL
+	// BNE is the B.cond instruction with CondNE. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BNE
+	// BVS is the B.cond instruction with CondVS. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond
 	BVS
+	// CLZ is the CLZ instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ
 	CLZ
+	// CLZW is the CLZ instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ
 	CLZW
+	// CMP is the CMP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register-
 	CMP
+	// CMPW is the CMP instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register-
 	CMPW
+	// CSET is the CSET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CSET
 	CSET
+	// EOR is the EOR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register-
 	EOR
+	// EORW is the EOR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register-
 	EORW
+	// FABSD is the FABS instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar-
 	FABSD
+	// FABSS is the FABS instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar-
 	FABSS
+	// FADDD is the FADD instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar-
 	FADDD
+	// FADDS is the FADD instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar-
 	FADDS
+	// FCMPD is the FCMP instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP
 	FCMPD
+	// FCMPS is the FCMP instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP
 	FCMPS
+	// FCVTDS is the FCVT instruction, for single to double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT
 	FCVTDS
+	// FCVTSD is the FCVT instruction, for double to single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT
 	FCVTSD
+	// FCVTZSD is the FCVTZS instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer-
 	FCVTZSD
+	// FCVTZSD is the FCVTZS instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer-
 	FCVTZSDW
+	// FCVTZSS is the FCVTZS instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer-
 	FCVTZSS
+	// FCVTZSSW is the FCVTZS instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer-
 	FCVTZSSW
+	// FCVTZUD is the FCVTZU instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer-
 	FCVTZUD
+	// FCVTZUDW is the FCVTZU instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer-
 	FCVTZUDW
+	// FCVTZUS is the FCVTZU instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer-
 	FCVTZUS
+	// FCVTZUSW is the FCVTZU instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer-
 	FCVTZUSW
+	// FDIVD is the FDIV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar-
 	FDIVD
+	// FDIVS is the FDIV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar-
 	FDIVS
+	// FMAXD is the FMAX instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar-
 	FMAXD
+	// FMAXS is the FMAX instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar-
 	FMAXS
+	// FMIND is the FMIN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar-
 	FMIND
+	// FMINS is the FMIN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar-
 	FMINS
+	// FMOVD is the FMOV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register-
 	FMOVD
+	// FMOVS is the FMOV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register-
 	FMOVS
+	// FMULD is the FMUL instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar-
 	FMULD
+	// FMULS is the FMUL instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar-
 	FMULS
+	// FNEGD is the FNEG instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar-
 	FNEGD
+	// FNEGS is the FNEG instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar-
 	FNEGS
+	// FRINTMD is the FRINTM instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar-
 	FRINTMD
+	// FRINTMS is the FRINTM instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar-
 	FRINTMS
+	// FRINTND is the FRINTN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar-
 	FRINTND
+	// FRINTNS is the FRINTN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar-
 	FRINTNS
+	// FRINTPD is the FRINTP instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar-
 	FRINTPD
+	// FRINTPS is the FRINTP instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar-
 	FRINTPS
+	// FRINTZD is the FRINTZ instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar-
 	FRINTZD
+	// FRINTZS is the FRINTZ instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar-
 	FRINTZS
+	// FSQRTD is the FSQRT instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar-
 	FSQRTD
+	// FSQRTS is the FSQRT instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar-
 	FSQRTS
+	// FSUBD is the FSUB instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar-
 	FSUBD
+	// FSUBS is the FSUB instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar-
 	FSUBS
+	// LSL is the LSL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register-
 	LSL
+	// LSLW is the LSL instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register-
 	LSLW
+	// LSR is the LSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register-
 	LSR
+	// LSRW is the LSR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register-
 	LSRW
+	// MOVB loads or stores a signed byte. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register-
 	MOVB
+	// MOVBU loads a byte. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--register-
 	MOVBU
+	// MOVD loads or stores a register, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDR--register-
 	MOVD
+	// MOVH loads or stores a signed halfword. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register-
 	MOVH
+	// MOVHU loads a halfword. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--register-
 	MOVHU
+	// MOVW loads or stores a signed word, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSW--register-
 	MOVW
+	// MOVWU loads a word, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDR--register-
 	MOVWU
+	// MRS is the MRS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MRS
 	MRS
+	// MSR is the MSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSR--register-
 	MSR
+	// MSUB is the MSUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB
 	MSUB
+	// MSUBW is the MSUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB
 	MSUBW
+	// MUL is the MUL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL
 	MUL
+	// MULW is the MUL instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL
 	MULW
+	// NEG is the NEG instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG
 	NEG
+	// NEGW is the NEG instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG
 	NEGW
+	// ORR is the ORR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register-
 	ORR
+	// ORRW is the ORR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register-
 	ORRW
+	// RBIT is the RBIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT
 	RBIT
+	// RBITW is the RBIT instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT
 	RBITW
-	RNG
+	// ROR is the ROR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register-
 	ROR
+	// RORW is the RORW instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register-
 	RORW
+	// SCVTFD is the SCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer-
 	SCVTFD
+	// SCVTFS is the SCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer-
 	SCVTFS
+	// SCVTFWD is the SCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer-
 	SCVTFWD
+	// SCVTFWS is the SCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer-
 	SCVTFWS
+	// SDIV is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV
 	SDIV
+	// SDIVW is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV
 	SDIVW
+	// SUB is the SUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register-
 	SUB
+	// SUBS is the SUBS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUBS--shifted-register-
 	SUBS
+	// SUBW is the SUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register-
 	SUBW
+	// SXTB is the SXTB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB
 	SXTB
+	// SXTBW is the SXTB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB
 	SXTBW
+	// SXTH is the SXTH instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH
 	SXTH
+	// SXTHW is the SXTH instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH
 	SXTHW
+	// SXTW is the SXTW instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTW
 	SXTW
+	// UCVTFD is the UCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer-
 	UCVTFD
+	// UCVTFS is the UCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer-
 	UCVTFS
+	// UCVTFWD is the UCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer-
 	UCVTFWD
+	// UCVTFWS is the UCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer-
 	UCVTFWS
+	// UDIV is the UDIV instruction .https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV
 	UDIV
+	// UDVIW is the UDIV instruction, in 64-bit mode.https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV
 	UDIVW
-	UXTW
 
 	// Vector instructions.
+
+	// VBIT is the BIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/BIT--vector-
 	VBIT
+	// VCNT is the CNT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/CNT--vector-
 	VCNT
+	// VMOV is the MOV instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/MOV--vector-
 	VMOV
+	// VUADDLV is the UADDLV instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/UADDLV--vector-
 	VUADDLV
+	// VLD1 is the LD1 instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/LD1--vector--single-structure-
 	VLD1
+	// VST1 is the ST1 instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/ST1--vector--single-structure-
 	VST1
+	// VADD is the ADD instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/ADD--vector-
 	VADD
+	// VFADDS is the FADD instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector-
 	VFADDS
+	// VFADDD is the FADD instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector-
 	VFADDD
 )
 
+// VectorArrangement is the arrangement of data within a vector register.
 type VectorArrangement byte
 
 const (
+	// VectorArrangmentNone is an arrangement indicating no data is stored.
 	VectorArrangementNone VectorArrangement = iota
+	// VectorArrangement8B is an arrangement of 8 bytes (64-bit vector)
 	VectorArrangement8B
+	// VectorArrangement16B is an arrangement of 16 bytes (128-bit vector)
 	VectorArrangement16B
+	// VectorArrangement4H is an arrangement of 4 halfwords (64-bit vector)
 	VectorArrangement4H
+	// VectorArrangement8H is an arrangement of 8 halfwords (128-bit vector)
 	VectorArrangement8H
+	// VectorArrangement2S is an arrangement of 2 words (64-bit vector)
 	VectorArrangement2S
+	// VectorArrangement4S is an arrangement of 4 words (128-bit vector)
 	VectorArrangement4S
+	// VectorArrangement1D is an arrangement of 1 doubleword (64-bit vector)
 	VectorArrangement1D
+	// VectorArrangement2D is an arrangement of 2 doublewords (128-bit vector)
 	VectorArrangement2D
+
+	// Assign each vector size specifier to a vector arrangement ID.
+	// Instructions can only have an arrangement or a size specifier, but not both, so it
+	// simplifies the internal representation of vector instructions by being able to
+	// store either into the same field.
+
+	// VectorArrangementB is a size specifier of byte
 	VectorArrangementB
+	// VectorArrangementH is a size specifier of halfword
 	VectorArrangementH
+	// VectorArrangementS is a size specifier of word
 	VectorArrangementS
+	// VectorArrangementD is a size specifier of doubleword
 	VectorArrangementD
 )
 
@@ -524,8 +768,10 @@ func (v VectorArrangement) String() (ret string) {
 	return
 }
 
+// VectorIndex is the index of an element of a vector register
 type VectorIndex byte
 
+// InstructionName returns the name of the given instruction
 func InstructionName(i asm.Instruction) string {
 	switch i {
 	case NOP:
@@ -716,8 +962,6 @@ func InstructionName(i asm.Instruction) string {
 		return "RBIT"
 	case RBITW:
 		return "RBITW"
-	case RNG:
-		return "RNG"
 	case ROR:
 		return "ROR"
 	case RORW:
@@ -762,8 +1006,6 @@ func InstructionName(i asm.Instruction) string {
 		return "UDIV"
 	case UDIVW:
 		return "UDIVW"
-	case UXTW:
-		return "UXTW"
 	case VBIT:
 		return "VBIT"
 	case VCNT:
diff --git a/internal/asm/arm64/impl.go b/internal/asm/arm64/impl.go
index c1703741..b1e7b0ef 100644
--- a/internal/asm/arm64/impl.go
+++ b/internal/asm/arm64/impl.go
@@ -845,37 +845,37 @@ func (a *AssemblerImpl) EncodeRegisterToRegister(n *NodeImpl) (err error) {
 		// https://developer.arm.com/documentation/den0024/a/CHDEEABE
 		var conditionalBits byte
 		switch n.SrcReg {
-		case REG_COND_EQ:
+		case RegCondEQ:
 			conditionalBits = 0b0001
-		case REG_COND_NE:
+		case RegCondNE:
 			conditionalBits = 0b0000
-		case REG_COND_HS:
+		case RegCondHS:
 			conditionalBits = 0b0011
-		case REG_COND_LO:
+		case RegCondLO:
 			conditionalBits = 0b0010
-		case REG_COND_MI:
+		case RegCondMI:
 			conditionalBits = 0b0101
-		case REG_COND_PL:
+		case RegCondPL:
 			conditionalBits = 0b0100
-		case REG_COND_VS:
+		case RegCondVS:
 			conditionalBits = 0b0111
-		case REG_COND_VC:
+		case RegCondVC:
 			conditionalBits = 0b0110
-		case REG_COND_HI:
+		case RegCondHI:
 			conditionalBits = 0b1001
-		case REG_COND_LS:
+		case RegCondLS:
 			conditionalBits = 0b1000
-		case REG_COND_GE:
+		case RegCondGE:
 			conditionalBits = 0b1011
-		case REG_COND_LT:
+		case RegCondLT:
 			conditionalBits = 0b1010
-		case REG_COND_GT:
+		case RegCondGT:
 			conditionalBits = 0b1101
-		case REG_COND_LE:
+		case RegCondLE:
 			conditionalBits = 0b1100
-		case REG_COND_AL:
+		case RegCondAL:
 			conditionalBits = 0b1111
-		case REG_COND_NV:
+		case RegCondNV:
 			conditionalBits = 0b1110
 		}
 
@@ -1063,7 +1063,7 @@ func (a *AssemblerImpl) EncodeRegisterToRegister(n *NodeImpl) (err error) {
 		}
 
 		srcRegBits, dstRegBits := registerBits(n.SrcReg), registerBits(n.DstReg)
-		if n.SrcReg == REGZERO && inst == MOVD {
+		if n.SrcReg == RegRZR && inst == MOVD {
 			// If this is 64-bit mov from zero register, then we encode this as MOVK.
 			// See "Move wide (immediate)" in
 			// https://developer.arm.com/documentation/ddi0602/2021-06/Index-by-Encoding/Data-Processing----Immediate
@@ -1089,7 +1089,7 @@ func (a *AssemblerImpl) EncodeRegisterToRegister(n *NodeImpl) (err error) {
 		}
 
 	case MRS:
-		if n.SrcReg != REG_FPSR {
+		if n.SrcReg != RegFPSR {
 			return fmt.Errorf("MRS has only support for FPSR register as a src but got %s", RegisterName(n.SrcReg))
 		}
 
@@ -1104,7 +1104,7 @@ func (a *AssemblerImpl) EncodeRegisterToRegister(n *NodeImpl) (err error) {
 		})
 
 	case MSR:
-		if n.DstReg != REG_FPSR {
+		if n.DstReg != RegFPSR {
 			return fmt.Errorf("MSR has only support for FPSR register as a dst but got %s", RegisterName(n.SrcReg))
 		}
 
@@ -1225,13 +1225,13 @@ func (a *AssemblerImpl) EncodeRegisterToRegister(n *NodeImpl) (err error) {
 			sf<<7 | 0b0_0_0_11110,
 		})
 
-	case SXTB, SXTBW, SXTH, SXTHW, SXTW, UXTW:
+	case SXTB, SXTBW, SXTH, SXTHW, SXTW:
 		if err = checkRegisterToRegisterType(n.SrcReg, n.DstReg, true, true); err != nil {
 			return
 		}
 
 		srcRegBits, dstRegBits := registerBits(n.SrcReg), registerBits(n.DstReg)
-		if n.SrcReg == REGZERO {
+		if n.SrcReg == RegRZR {
 			// If the source is zero register, we encode as MOV dst, zero.
 			var sf byte
 			if inst == MOVD {
@@ -1545,7 +1545,7 @@ func (a *AssemblerImpl) EncodeRegisterAndConstToNone(n *NodeImpl) (err error) {
 	// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CMP--immediate---Compare--immediate---an-alias-of-SUBS--immediate--?lang=en
 	if n.SrcConst < 0 || n.SrcConst > 4095 {
 		return fmt.Errorf("immediate for CMP must fit in 0 to 4095 but got %d", n.SrcConst)
-	} else if n.SrcReg == REGZERO {
+	} else if n.SrcReg == RegRZR {
 		return errors.New("zero register is not supported for CMP (immediate)")
 	}
 
@@ -2699,22 +2699,22 @@ func (a *AssemblerImpl) EncodeVectorRegisterToVectorRegister(n *NodeImpl) error
 var zeroRegisterBits byte = 0b11111
 
 func isIntRegister(r asm.Register) bool {
-	return REG_R0 <= r && r <= REGZERO
+	return RegR0 <= r && r <= RegRZR
 }
 
 func isVectorRegister(r asm.Register) bool {
-	return REG_V0 <= r && r <= REG_V31
+	return RegV0 <= r && r <= RegV31
 }
 
 func isConditionalRegister(r asm.Register) bool {
-	return REG_COND_EQ <= r && r <= REG_COND_NV
+	return RegCondEQ <= r && r <= RegCondNV
 }
 
 func intRegisterBits(r asm.Register) (ret byte, err error) {
 	if !isIntRegister(r) {
 		err = fmt.Errorf("%s is not integer", RegisterName(r))
 	} else {
-		ret = byte(r - REG_R0)
+		ret = byte(r - RegR0)
 	}
 	return
 }
@@ -2723,16 +2723,16 @@ func vectorRegisterBits(r asm.Register) (ret byte, err error) {
 	if !isVectorRegister(r) {
 		err = fmt.Errorf("%s is not float", RegisterName(r))
 	} else {
-		ret = byte(r - REG_V0)
+		ret = byte(r - RegV0)
 	}
 	return
 }
 
 func registerBits(r asm.Register) (ret byte) {
 	if isIntRegister(r) {
-		ret = byte(r - REG_R0)
+		ret = byte(r - RegR0)
 	} else {
-		ret = byte(r - REG_V0)
+		ret = byte(r - RegV0)
 	}
 	return
 }
diff --git a/internal/engine/compiler/impl_arm64.go b/internal/engine/compiler/impl_arm64.go
index 75c3f7f4..3621740c 100644
--- a/internal/engine/compiler/impl_arm64.go
+++ b/internal/engine/compiler/impl_arm64.go
@@ -49,41 +49,41 @@ func newArm64Compiler(ir *wazeroir.CompilationResult) (compiler, error) {
 
 var (
 	arm64UnreservedVectorRegisters = []asm.Register{
-		arm64.REG_V0, arm64.REG_V1, arm64.REG_V2, arm64.REG_V3,
-		arm64.REG_V4, arm64.REG_V5, arm64.REG_V6, arm64.REG_V7, arm64.REG_V8,
-		arm64.REG_V9, arm64.REG_V10, arm64.REG_V11, arm64.REG_V12, arm64.REG_V13,
-		arm64.REG_V14, arm64.REG_V15, arm64.REG_V16, arm64.REG_V17, arm64.REG_V18,
-		arm64.REG_V19, arm64.REG_V20, arm64.REG_V21, arm64.REG_V22, arm64.REG_V23,
-		arm64.REG_V24, arm64.REG_V25, arm64.REG_V26, arm64.REG_V27, arm64.REG_V28,
-		arm64.REG_V29, arm64.REG_V30, arm64.REG_V31,
+		arm64.RegV0, arm64.RegV1, arm64.RegV2, arm64.RegV3,
+		arm64.RegV4, arm64.RegV5, arm64.RegV6, arm64.RegV7, arm64.RegV8,
+		arm64.RegV9, arm64.RegV10, arm64.RegV11, arm64.RegV12, arm64.RegV13,
+		arm64.RegV14, arm64.RegV15, arm64.RegV16, arm64.RegV17, arm64.RegV18,
+		arm64.RegV19, arm64.RegV20, arm64.RegV21, arm64.RegV22, arm64.RegV23,
+		arm64.RegV24, arm64.RegV25, arm64.RegV26, arm64.RegV27, arm64.RegV28,
+		arm64.RegV29, arm64.RegV30, arm64.RegV31,
 	}
 
 	// Note (see arm64 section in https://go.dev/doc/asm):
-	// * REG_R18 is reserved as a platform register, and we don't use it in Compiler.
-	// * REG_R28 is reserved for Goroutine by Go runtime, and we don't use it in Compiler.
+	// * RegR18 is reserved as a platform register, and we don't use it in Compiler.
+	// * RegR28 is reserved for Goroutine by Go runtime, and we don't use it in Compiler.
 	arm64UnreservedGeneralPurposeRegisters = []asm.Register{ // nolint
-		arm64.REG_R3, arm64.REG_R4, arm64.REG_R5, arm64.REG_R6, arm64.REG_R7, arm64.REG_R8,
-		arm64.REG_R9, arm64.REG_R10, arm64.REG_R11, arm64.REG_R12, arm64.REG_R13,
-		arm64.REG_R14, arm64.REG_R15, arm64.REG_R16, arm64.REG_R17, arm64.REG_R19,
-		arm64.REG_R20, arm64.REG_R21, arm64.REG_R22, arm64.REG_R23, arm64.REG_R24,
-		arm64.REG_R25, arm64.REG_R26, arm64.REG_R29, arm64.REG_R30,
+		arm64.RegR3, arm64.RegR4, arm64.RegR5, arm64.RegR6, arm64.RegR7, arm64.RegR8,
+		arm64.RegR9, arm64.RegR10, arm64.RegR11, arm64.RegR12, arm64.RegR13,
+		arm64.RegR14, arm64.RegR15, arm64.RegR16, arm64.RegR17, arm64.RegR19,
+		arm64.RegR20, arm64.RegR21, arm64.RegR22, arm64.RegR23, arm64.RegR24,
+		arm64.RegR25, arm64.RegR26, arm64.RegR29, arm64.RegR30,
 	}
 )
 
 const (
 	// arm64ReservedRegisterForCallEngine holds the pointer to callEngine instance (i.e. *callEngine as uintptr)
-	arm64ReservedRegisterForCallEngine = arm64.REG_R0
+	arm64ReservedRegisterForCallEngine = arm64.RegR0
 	// arm64ReservedRegisterForStackBasePointerAddress holds stack base pointer's address (callEngine.stackBasePointer) in the current function call.
-	arm64ReservedRegisterForStackBasePointerAddress = arm64.REG_R1
+	arm64ReservedRegisterForStackBasePointerAddress = arm64.RegR1
 	// arm64ReservedRegisterForMemory holds the pointer to the memory slice's data (i.e. &memory.Buffer[0] as uintptr).
-	arm64ReservedRegisterForMemory = arm64.REG_R2
+	arm64ReservedRegisterForMemory = arm64.RegR2
 	// arm64ReservedRegisterForTemporary is the temporary register which is available at any point of execution, but its content shouldn't be supposed to live beyond the single operation.
 	// Note: we choose R27 as that is the temporary register used in Go's assembler.
-	arm64ReservedRegisterForTemporary = arm64.REG_R27
+	arm64ReservedRegisterForTemporary = arm64.RegR27
 )
 
 var (
-	arm64CallingConventionModuleInstanceAddressRegister = arm64.REG_R29
+	arm64CallingConventionModuleInstanceAddressRegister = arm64.RegR29
 )
 
 const (
@@ -96,7 +96,7 @@ const (
 )
 
 func isZeroRegister(r asm.Register) bool {
-	return r == arm64.REGZERO
+	return r == arm64.RegRZR
 }
 
 func (c *arm64Compiler) addStaticData(d []byte) {
@@ -309,7 +309,7 @@ func (c *arm64Compiler) compileReturnFunction() error {
 	c.assembler.CompileRegisterToMemory(arm64.MOVD, callFramePointerReg, arm64ReservedRegisterForCallEngine, callEngineGlobalContextCallFrameStackPointerOffset)
 
 	// Next we compare the decremented call frame stack pointer with zero.
-	c.assembler.CompileTwoRegistersToNone(arm64.CMP, callFramePointerReg, arm64.REGZERO)
+	c.assembler.CompileTwoRegistersToNone(arm64.CMP, callFramePointerReg, arm64.RegRZR)
 
 	// If the values are identical, we return back to the Go code with returned status.
 	brIfNotEqual := c.assembler.CompileJump(arm64.BNE)
@@ -392,7 +392,7 @@ func (c *arm64Compiler) compileExitFromNativeCode(status nativeCallStatusCode) {
 		c.assembler.CompileRegisterToMemory(arm64.MOVWU, arm64ReservedRegisterForTemporary, arm64ReservedRegisterForCallEngine, callEngineExitContextnativeCallStatusCodeOffset)
 	} else {
 		// If the status == 0, we use zero register to store zero.
-		c.assembler.CompileRegisterToMemory(arm64.MOVWU, arm64.REGZERO, arm64ReservedRegisterForCallEngine, callEngineExitContextnativeCallStatusCodeOffset)
+		c.assembler.CompileRegisterToMemory(arm64.MOVWU, arm64.RegRZR, arm64ReservedRegisterForCallEngine, callEngineExitContextnativeCallStatusCodeOffset)
 	}
 
 	// The return address to the Go code is stored in archContext.compilerReturnAddress which
@@ -653,31 +653,31 @@ func (c *arm64Compiler) compileBrIf(o *wazeroir.OperationBrIf) error {
 		// https://developer.arm.com/documentation/dui0801/a/Condition-Codes/Condition-code-suffixes
 		// Here we represent the conditional codes by using arm64.COND_** registers, and that means the
 		// conditional jump can be performed if we use arm64.B**.
-		// For example, if we have arm64.COND_EQ on cond, that means we performed compileEq right before
+		// For example, if we have arm64.CondEQ on cond, that means we performed compileEq right before
 		// this compileBrIf and BrIf can be achieved by arm64.BEQ.
 		var brInst asm.Instruction
 		switch cond.conditionalRegister {
-		case arm64.COND_EQ:
+		case arm64.CondEQ:
 			brInst = arm64.BEQ
-		case arm64.COND_NE:
+		case arm64.CondNE:
 			brInst = arm64.BNE
-		case arm64.COND_HS:
+		case arm64.CondHS:
 			brInst = arm64.BHS
-		case arm64.COND_LO:
+		case arm64.CondLO:
 			brInst = arm64.BLO
-		case arm64.COND_MI:
+		case arm64.CondMI:
 			brInst = arm64.BMI
-		case arm64.COND_HI:
+		case arm64.CondHI:
 			brInst = arm64.BHI
-		case arm64.COND_LS:
+		case arm64.CondLS:
 			brInst = arm64.BLS
-		case arm64.COND_GE:
+		case arm64.CondGE:
 			brInst = arm64.BGE
-		case arm64.COND_LT:
+		case arm64.CondLT:
 			brInst = arm64.BLT
-		case arm64.COND_GT:
+		case arm64.CondGT:
 			brInst = arm64.BGT
-		case arm64.COND_LE:
+		case arm64.CondLE:
 			brInst = arm64.BLE
 		default:
 			// BUG: This means that we use the cond.conditionalRegister somewhere in this file,
@@ -693,7 +693,7 @@ func (c *arm64Compiler) compileBrIf(o *wazeroir.OperationBrIf) error {
 		}
 		// Compare the value with zero register. Note that the value is ensured to be i32 by function validation phase,
 		// so we use CMPW (32-bit compare) here.
-		c.assembler.CompileTwoRegistersToNone(arm64.CMPW, cond.register, arm64.REGZERO)
+		c.assembler.CompileTwoRegistersToNone(arm64.CMPW, cond.register, arm64.RegRZR)
 
 		conditionalBR = c.assembler.CompileJump(arm64.BNE)
 
@@ -792,7 +792,7 @@ func (c *arm64Compiler) compileBrTable(o *wazeroir.OperationBrTable) error {
 		c.markRegisterUsed(reg)
 
 		// Zero the value on a picked register.
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, reg)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, reg)
 	}
 
 	tmpReg, err := c.allocateRegister(registerTypeGeneralPurpose)
@@ -1150,7 +1150,7 @@ func (c *arm64Compiler) compileCallIndirect(o *wazeroir.OperationCallIndirect) e
 		c.markRegisterUsed(reg)
 
 		// Zero the value on a picked register.
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, reg)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, reg)
 	}
 
 	tmp, err := c.allocateRegister(registerTypeGeneralPurpose)
@@ -1210,7 +1210,7 @@ func (c *arm64Compiler) compileCallIndirect(o *wazeroir.OperationCallIndirect) e
 	c.assembler.CompileMemoryToRegister(arm64.MOVD, offset.register, 0, offset.register)
 
 	// Check if the value of table[offset] equals zero, meaning that the target element is uninitialized.
-	c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.REGZERO, offset.register)
+	c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, offset.register)
 	brIfInitialized := c.assembler.CompileJump(arm64.BNE)
 	c.compileExitFromNativeCode(nativeCallStatusCodeInvalidTableAccess)
 
@@ -1316,7 +1316,7 @@ func (c *arm64Compiler) compileSelect() error {
 
 	if isZeroRegister(x1.register) && isZeroRegister(x2.register) {
 		// If both values are zero, the result is always zero.
-		c.pushRuntimeValueLocationOnRegister(arm64.REGZERO, x1.valueType)
+		c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType)
 		c.markRegisterUnused(cv.register)
 		return nil
 	}
@@ -1325,7 +1325,7 @@ func (c *arm64Compiler) compileSelect() error {
 	// no matter which of original x1 or x2 is selected.
 	//
 	// If x1 is currently on zero register, we cannot place the result because
-	// "MOV arm64.REGZERO x2.register" results in arm64.REGZERO regardless of the value.
+	// "MOV arm64.RegRZR x2.register" results in arm64.RegRZR regardless of the value.
 	// So we explicitly assign a general purpose register to x1 here.
 	if isZeroRegister(x1.register) {
 		// Mark x2 and cv's registers are used so they won't be chosen.
@@ -1337,12 +1337,12 @@ func (c *arm64Compiler) compileSelect() error {
 		}
 		x1.setRegister(x1Reg)
 		// And zero our the picked register.
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, x1Reg)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, x1Reg)
 	}
 
 	// At this point, x1 is non-zero register, and x2 is either general purpose or zero register.
 
-	c.assembler.CompileTwoRegistersToNone(arm64.CMPW, arm64.REGZERO, cv.register)
+	c.assembler.CompileTwoRegistersToNone(arm64.CMPW, arm64.RegRZR, cv.register)
 	brIfNotZero := c.assembler.CompileJump(arm64.BNE)
 
 	// If cv == 0, we move the value of x2 to the x1.register.
@@ -1464,7 +1464,7 @@ func (c *arm64Compiler) compileSub(o *wazeroir.OperationSub) error {
 
 	// If both of registers are zeros, this can be nop and push the zero register.
 	if isZeroRegister(x1.register) && isZeroRegister(x2.register) {
-		c.pushRuntimeValueLocationOnRegister(arm64.REGZERO, x1.valueType)
+		c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType)
 		return nil
 	}
 
@@ -1506,7 +1506,7 @@ func (c *arm64Compiler) compileMul(o *wazeroir.OperationMul) error {
 
 	// Multiplication can be done by putting a zero register if one of operands is zero.
 	if isZeroRegister(x1.register) || isZeroRegister(x2.register) {
-		c.pushRuntimeValueLocationOnRegister(arm64.REGZERO, x1.valueType)
+		c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType)
 		return nil
 	}
 
@@ -1732,7 +1732,7 @@ func (c *arm64Compiler) compileIntegerDivPrecheck(is32Bit, isSigned bool, divide
 		movInst = arm64.MOVD
 		minValueOffsetInVM = arm64CallEngineArchContextMinimum64BitSignedIntOffset
 	}
-	c.assembler.CompileTwoRegistersToNone(cmpInst, arm64.REGZERO, divisor)
+	c.assembler.CompileTwoRegistersToNone(cmpInst, arm64.RegRZR, divisor)
 
 	// If it is zero, we exit with nativeCallStatusIntegerDivisionByZero.
 	brIfDivisorNonZero := c.assembler.CompileJump(arm64.BNE)
@@ -1811,7 +1811,7 @@ func (c *arm64Compiler) compileRem(o *wazeroir.OperationRem) error {
 	}
 
 	// We check the divisor value equals zero.
-	c.assembler.CompileTwoRegistersToNone(cmpInst, arm64.REGZERO, divisorReg)
+	c.assembler.CompileTwoRegistersToNone(cmpInst, arm64.RegRZR, divisorReg)
 
 	// If it is zero, we exit with nativeCallStatusIntegerDivisionByZero.
 	brIfDivisorNonZero := c.assembler.CompileJump(arm64.BNE)
@@ -1854,7 +1854,7 @@ func (c *arm64Compiler) compileAnd(o *wazeroir.OperationAnd) error {
 	// If either of the registers x1 or x2 is zero,
 	// the result will always be zero.
 	if isZeroRegister(x1.register) || isZeroRegister(x2.register) {
-		c.pushRuntimeValueLocationOnRegister(arm64.REGZERO, x1.valueType)
+		c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType)
 		return nil
 	}
 
@@ -2195,7 +2195,7 @@ func (c *arm64Compiler) compileI32WrapFromI64() error {
 // compileITruncFromF implements compiler.compileITruncFromF for the arm64 architecture.
 func (c *arm64Compiler) compileITruncFromF(o *wazeroir.OperationITruncFromF) error {
 	// Clear the floating point status register (FPSR).
-	c.assembler.CompileRegisterToRegister(arm64.MSR, arm64.REGZERO, arm64.REG_FPSR)
+	c.assembler.CompileRegisterToRegister(arm64.MSR, arm64.RegRZR, arm64.RegFPSR)
 
 	var vt runtimeValueType
 	var convinst asm.Instruction
@@ -2242,7 +2242,7 @@ func (c *arm64Compiler) compileITruncFromF(o *wazeroir.OperationITruncFromF) err
 	if !o.NonTrapping {
 		// Obtain the floating point status register value into the general purpose register,
 		// so that we can check if the conversion resulted in undefined behavior.
-		c.assembler.CompileRegisterToRegister(arm64.MRS, arm64.REG_FPSR, arm64ReservedRegisterForTemporary)
+		c.assembler.CompileRegisterToRegister(arm64.MRS, arm64.RegFPSR, arm64ReservedRegisterForTemporary)
 		// Check if the conversion was undefined by comparing the status with 1.
 		// See https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/FPSR--Floating-point-Status-Register
 		c.assembler.CompileRegisterAndConstToNone(arm64.CMP, arm64ReservedRegisterForTemporary, 1)
@@ -2447,9 +2447,9 @@ func (c *arm64Compiler) emitEqOrNe(isEq bool, unsignedType wazeroir.UnsignedType
 	c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register)
 
 	// Push the comparison result as a conditional register value.
-	cond := arm64.COND_NE
+	cond := arm64.CondNE
 	if isEq {
-		cond = arm64.COND_EQ
+		cond = arm64.CondEQ
 	}
 	c.locationStack.pushRuntimeValueLocationOnConditionalRegister(cond)
 	return nil
@@ -2470,10 +2470,10 @@ func (c *arm64Compiler) compileEqz(o *wazeroir.OperationEqz) error {
 		inst = arm64.CMP
 	}
 
-	c.assembler.CompileTwoRegistersToNone(inst, arm64.REGZERO, x1.register)
+	c.assembler.CompileTwoRegistersToNone(inst, arm64.RegRZR, x1.register)
 
 	// Push the comparison result as a conditional register value.
-	c.locationStack.pushRuntimeValueLocationOnConditionalRegister(arm64.COND_EQ)
+	c.locationStack.pushRuntimeValueLocationOnConditionalRegister(arm64.CondEQ)
 	return nil
 }
 
@@ -2489,22 +2489,22 @@ func (c *arm64Compiler) compileLt(o *wazeroir.OperationLt) error {
 	switch o.Type {
 	case wazeroir.SignedTypeUint32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_LO
+		conditionalRegister = arm64.CondLO
 	case wazeroir.SignedTypeUint64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_LO
+		conditionalRegister = arm64.CondLO
 	case wazeroir.SignedTypeInt32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_LT
+		conditionalRegister = arm64.CondLT
 	case wazeroir.SignedTypeInt64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_LT
+		conditionalRegister = arm64.CondLT
 	case wazeroir.SignedTypeFloat32:
 		inst = arm64.FCMPS
-		conditionalRegister = arm64.COND_MI
+		conditionalRegister = arm64.CondMI
 	case wazeroir.SignedTypeFloat64:
 		inst = arm64.FCMPD
-		conditionalRegister = arm64.COND_MI
+		conditionalRegister = arm64.CondMI
 	}
 
 	c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register)
@@ -2526,22 +2526,22 @@ func (c *arm64Compiler) compileGt(o *wazeroir.OperationGt) error {
 	switch o.Type {
 	case wazeroir.SignedTypeUint32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_HI
+		conditionalRegister = arm64.CondHI
 	case wazeroir.SignedTypeUint64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_HI
+		conditionalRegister = arm64.CondHI
 	case wazeroir.SignedTypeInt32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_GT
+		conditionalRegister = arm64.CondGT
 	case wazeroir.SignedTypeInt64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_GT
+		conditionalRegister = arm64.CondGT
 	case wazeroir.SignedTypeFloat32:
 		inst = arm64.FCMPS
-		conditionalRegister = arm64.COND_GT
+		conditionalRegister = arm64.CondGT
 	case wazeroir.SignedTypeFloat64:
 		inst = arm64.FCMPD
-		conditionalRegister = arm64.COND_GT
+		conditionalRegister = arm64.CondGT
 	}
 
 	c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register)
@@ -2563,22 +2563,22 @@ func (c *arm64Compiler) compileLe(o *wazeroir.OperationLe) error {
 	switch o.Type {
 	case wazeroir.SignedTypeUint32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_LS
+		conditionalRegister = arm64.CondLS
 	case wazeroir.SignedTypeUint64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_LS
+		conditionalRegister = arm64.CondLS
 	case wazeroir.SignedTypeInt32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_LE
+		conditionalRegister = arm64.CondLE
 	case wazeroir.SignedTypeInt64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_LE
+		conditionalRegister = arm64.CondLE
 	case wazeroir.SignedTypeFloat32:
 		inst = arm64.FCMPS
-		conditionalRegister = arm64.COND_LS
+		conditionalRegister = arm64.CondLS
 	case wazeroir.SignedTypeFloat64:
 		inst = arm64.FCMPD
-		conditionalRegister = arm64.COND_LS
+		conditionalRegister = arm64.CondLS
 	}
 
 	c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register)
@@ -2600,22 +2600,22 @@ func (c *arm64Compiler) compileGe(o *wazeroir.OperationGe) error {
 	switch o.Type {
 	case wazeroir.SignedTypeUint32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_HS
+		conditionalRegister = arm64.CondHS
 	case wazeroir.SignedTypeUint64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_HS
+		conditionalRegister = arm64.CondHS
 	case wazeroir.SignedTypeInt32:
 		inst = arm64.CMPW
-		conditionalRegister = arm64.COND_GE
+		conditionalRegister = arm64.CondGE
 	case wazeroir.SignedTypeInt64:
 		inst = arm64.CMP
-		conditionalRegister = arm64.COND_GE
+		conditionalRegister = arm64.CondGE
 	case wazeroir.SignedTypeFloat32:
 		inst = arm64.FCMPS
-		conditionalRegister = arm64.COND_GE
+		conditionalRegister = arm64.CondGE
 	case wazeroir.SignedTypeFloat64:
 		inst = arm64.FCMPD
-		conditionalRegister = arm64.COND_GE
+		conditionalRegister = arm64.CondGE
 	}
 
 	c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register)
@@ -2819,7 +2819,7 @@ func (c *arm64Compiler) compileMemoryAccessOffsetSetup(offsetArg uint32, targetS
 		if err != nil {
 			return
 		}
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, offsetRegister)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, offsetRegister)
 	}
 
 	if offsetConst := int64(offsetArg) + targetSizeInBytes; offsetConst <= math.MaxUint32 {
@@ -2981,7 +2981,7 @@ func (c *arm64Compiler) compileIntConstant(is32bit bool, value uint64) error {
 	}
 
 	if value == 0 {
-		c.pushRuntimeValueLocationOnRegister(arm64.REGZERO, vt)
+		c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, vt)
 	} else {
 		// Take a register to load the value.
 		reg, err := c.allocateRegister(registerTypeGeneralPurpose)
@@ -3018,7 +3018,7 @@ func (c *arm64Compiler) compileFloatConstant(is32bit bool, value uint64) error {
 		return err
 	}
 
-	tmpReg := arm64.REGZERO
+	tmpReg := arm64.RegRZR
 	if value != 0 {
 		tmpReg = arm64ReservedRegisterForTemporary
 		var inst asm.Instruction
@@ -3076,7 +3076,7 @@ func (c *arm64Compiler) compileInitImpl(isTable bool, index, tableIndex uint32)
 		if err != nil {
 			return err
 		}
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, sourceOffset.register)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, sourceOffset.register)
 	}
 	c.markRegisterUsed(sourceOffset.register)
 
@@ -3089,7 +3089,7 @@ func (c *arm64Compiler) compileInitImpl(isTable bool, index, tableIndex uint32)
 		if err != nil {
 			return err
 		}
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, destinationOffset.register)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, destinationOffset.register)
 	}
 	c.markRegisterUsed(destinationOffset.register)
 
@@ -3166,7 +3166,7 @@ func (c *arm64Compiler) compileInitImpl(isTable bool, index, tableIndex uint32)
 
 	if !isZeroRegister(copySize.register) {
 		// If the size equals zero, we can skip the entire instructions beflow.
-		c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.REGZERO, copySize.register)
+		c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, copySize.register)
 		skipCopyJump := c.assembler.CompileJump(arm64.BEQ)
 
 		var movInst asm.Instruction
@@ -3242,9 +3242,9 @@ func (c *arm64Compiler) compileDataDrop(o *wazeroir.OperationDataDrop) error {
 	c.compileLoadDataInstanceAddress(o.DataIndex, tmp)
 
 	// Clears the content of DataInstance[o.DataIndex] (== []byte type).
-	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REGZERO, tmp, 0)
-	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REGZERO, tmp, 8)
-	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REGZERO, tmp, 16)
+	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegRZR, tmp, 0)
+	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegRZR, tmp, 8)
+	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegRZR, tmp, 16)
 	return nil
 }
 
@@ -3294,7 +3294,7 @@ func (c *arm64Compiler) compileCopyImpl(isTable bool, srcTableIndex, dstTableInd
 		if err != nil {
 			return err
 		}
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, sourceOffset.register)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, sourceOffset.register)
 	}
 	c.markRegisterUsed(sourceOffset.register)
 
@@ -3307,7 +3307,7 @@ func (c *arm64Compiler) compileCopyImpl(isTable bool, srcTableIndex, dstTableInd
 		if err != nil {
 			return err
 		}
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, destinationOffset.register)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, destinationOffset.register)
 	}
 	c.markRegisterUsed(destinationOffset.register)
 
@@ -3388,7 +3388,7 @@ func (c *arm64Compiler) compileCopyImpl(isTable bool, srcTableIndex, dstTableInd
 
 	// If the size equals zero, we can skip the entire instructions beflow.
 	if !isZeroRegister(copySize.register) {
-		c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.REGZERO, copySize.register)
+		c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, copySize.register)
 		skipCopyJump := c.assembler.CompileJump(arm64.BEQ)
 
 		// If source offet < destination offset: for (i = size-1; i >= 0; i--) dst[i] = src[i];
@@ -3562,7 +3562,7 @@ func (c *arm64Compiler) compileFillImpl(isTable bool, tableIndex uint32) error {
 		if err != nil {
 			return err
 		}
-		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.REGZERO, destinationOffset.register)
+		c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, destinationOffset.register)
 	}
 	c.markRegisterUsed(destinationOffset.register)
 
@@ -3606,7 +3606,7 @@ func (c *arm64Compiler) compileFillImpl(isTable bool, tableIndex uint32) error {
 	c.assembler.SetJumpTargetOnNext(destinationBoundsOK)
 
 	// If the size equals zero, we can skip the entire instructions beflow.
-	c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.REGZERO, fillSize.register)
+	c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, fillSize.register)
 	skipCopyJump := c.assembler.CompileJump(arm64.BEQ)
 
 	// destinationOffset -= size.
@@ -3685,9 +3685,9 @@ func (c *arm64Compiler) compileElemDrop(o *wazeroir.OperationElemDrop) error {
 	c.compileLoadElemInstanceAddress(o.ElemIndex, tmp)
 
 	// Clears the content of ElementInstances[o.ElemIndex] (== []interface{} type).
-	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REGZERO, tmp, 0)
-	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REGZERO, tmp, 8)
-	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REGZERO, tmp, 16)
+	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegRZR, tmp, 0)
+	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegRZR, tmp, 8)
+	c.assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegRZR, tmp, 16)
 	return nil
 }
 
diff --git a/internal/engine/compiler/impl_vec_arm64.go b/internal/engine/compiler/impl_vec_arm64.go
index 4e855112..7ec7a949 100644
--- a/internal/engine/compiler/impl_vec_arm64.go
+++ b/internal/engine/compiler/impl_vec_arm64.go
@@ -17,7 +17,7 @@ func (c *arm64Compiler) compileConstV128(o *wazeroir.OperationConstV128) error {
 	// Moves the lower 64-bits as a scalar float.
 	var intReg = arm64ReservedRegisterForTemporary
 	if o.Lo == 0 {
-		intReg = arm64.REGZERO
+		intReg = arm64.RegRZR
 	} else {
 		c.assembler.CompileConstToRegister(arm64.MOVD, int64(o.Lo), arm64ReservedRegisterForTemporary)
 	}
@@ -26,7 +26,7 @@ func (c *arm64Compiler) compileConstV128(o *wazeroir.OperationConstV128) error {
 	// Then, insert the higher bits with VMOV (translated as "ins" instruction).
 	intReg = arm64ReservedRegisterForTemporary
 	if o.Hi == 0 {
-		intReg = arm64.REGZERO
+		intReg = arm64.RegRZR
 	} else {
 		c.assembler.CompileConstToRegister(arm64.MOVD, int64(o.Hi), arm64ReservedRegisterForTemporary)
 	}


Test patch:
diff --git a/internal/asm/arm64/impl_test.go b/internal/asm/arm64/impl_test.go
index f3f51e24..7e0b0c37 100644
--- a/internal/asm/arm64/impl_test.go
+++ b/internal/asm/arm64/impl_test.go
@@ -37,11 +37,11 @@ func TestNodeImpl_String(t *testing.T) {
 			exp: "NOP",
 		},
 		{
-			in:  &NodeImpl{Instruction: BEQ, Types: OperandTypesNoneToRegister, DstReg: REG_R1},
+			in:  &NodeImpl{Instruction: BEQ, Types: OperandTypesNoneToRegister, DstReg: RegR1},
 			exp: "BEQ R1",
 		},
 		{
-			in:  &NodeImpl{Instruction: BNE, Types: OperandTypesNoneToMemory, DstReg: REG_R1, DstConst: 0x1234},
+			in:  &NodeImpl{Instruction: BNE, Types: OperandTypesNoneToMemory, DstReg: RegR1, DstConst: 0x1234},
 			exp: "BNE [R1 + 0x1234]",
 		},
 		{
@@ -49,81 +49,81 @@ func TestNodeImpl_String(t *testing.T) {
 			exp: "BNE {NOP}",
 		},
 		{
-			in:  &NodeImpl{Instruction: ADD, Types: OperandTypesRegisterToRegister, SrcReg: REG_V0, DstReg: REG_V10},
+			in:  &NodeImpl{Instruction: ADD, Types: OperandTypesRegisterToRegister, SrcReg: RegV0, DstReg: RegV10},
 			exp: "ADD V0, V10",
 		},
 		{
 			in: &NodeImpl{Instruction: ADD, Types: OperandTypesLeftShiftedRegisterToRegister,
-				SrcReg: REG_R0, SrcReg2: REG_R11, SrcConst: 4, DstReg: REG_R10},
+				SrcReg: RegR0, SrcReg2: RegR11, SrcConst: 4, DstReg: RegR10},
 			exp: "ADD (R0, R11 << 4), R10",
 		},
 		{
-			in:  &NodeImpl{Instruction: ADD, Types: OperandTypesTwoRegistersToRegister, SrcReg: REG_R0, SrcReg2: REG_R8, DstReg: REG_R10},
+			in:  &NodeImpl{Instruction: ADD, Types: OperandTypesTwoRegistersToRegister, SrcReg: RegR0, SrcReg2: RegR8, DstReg: RegR10},
 			exp: "ADD (R0, R8), R10",
 		},
 		{
 			in: &NodeImpl{Instruction: MSUB, Types: OperandTypesThreeRegistersToRegister,
-				SrcReg: REG_R0, SrcReg2: REG_R8, DstReg: REG_R10, DstReg2: REG_R1},
+				SrcReg: RegR0, SrcReg2: RegR8, DstReg: RegR10, DstReg2: RegR1},
 			exp: "MSUB (R0, R8, R10), R1)",
 		},
 		{
-			in:  &NodeImpl{Instruction: CMPW, Types: OperandTypesTwoRegistersToNone, SrcReg: REG_R0, SrcReg2: REG_R8},
+			in:  &NodeImpl{Instruction: CMPW, Types: OperandTypesTwoRegistersToNone, SrcReg: RegR0, SrcReg2: RegR8},
 			exp: "CMPW (R0, R8)",
 		},
 		{
-			in:  &NodeImpl{Instruction: CMP, Types: OperandTypesRegisterAndConstToNone, SrcReg: REG_R0, SrcConst: 0x123},
+			in:  &NodeImpl{Instruction: CMP, Types: OperandTypesRegisterAndConstToNone, SrcReg: RegR0, SrcConst: 0x123},
 			exp: "CMP (R0, 0x123)",
 		},
 		{
-			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesRegisterToMemory, SrcReg: REG_R0, DstReg: REG_R8, DstConst: 0x123},
+			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesRegisterToMemory, SrcReg: RegR0, DstReg: RegR8, DstConst: 0x123},
 			exp: "MOVD R0, [R8 + 0x123]",
 		},
 		{
-			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesRegisterToMemory, SrcReg: REG_R0, DstReg: REG_R8, DstReg2: REG_R6},
+			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesRegisterToMemory, SrcReg: RegR0, DstReg: RegR8, DstReg2: RegR6},
 			exp: "MOVD R0, [R8 + R6]",
 		},
 		{
-			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesMemoryToRegister, SrcReg: REG_R0, SrcConst: 0x123, DstReg: REG_R8},
+			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesMemoryToRegister, SrcReg: RegR0, SrcConst: 0x123, DstReg: RegR8},
 			exp: "MOVD [R0 + 0x123], R8",
 		},
 		{
-			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesMemoryToRegister, SrcReg: REG_R0, SrcReg2: REG_R6, DstReg: REG_R8},
+			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesMemoryToRegister, SrcReg: RegR0, SrcReg2: RegR6, DstReg: RegR8},
 			exp: "MOVD [R0 + R6], R8",
 		},
 		{
-			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesConstToRegister, SrcConst: 0x123, DstReg: REG_R8},
+			in:  &NodeImpl{Instruction: MOVD, Types: OperandTypesConstToRegister, SrcConst: 0x123, DstReg: RegR8},
 			exp: "MOVD 0x123, R8",
 		},
 		{
-			in:  &NodeImpl{Instruction: VCNT, Types: OperandTypesSIMDByteToSIMDByte, SrcReg: REG_V1, DstReg: REG_V2},
+			in:  &NodeImpl{Instruction: VCNT, Types: OperandTypesSIMDByteToSIMDByte, SrcReg: RegV1, DstReg: RegV2},
 			exp: "VCNT V1.B8, V2.B8",
 		},
 		{
-			in:  &NodeImpl{Instruction: VUADDLV, Types: OperandTypesSIMDByteToRegister, SrcReg: REG_V1, DstReg: REG_V2},
+			in:  &NodeImpl{Instruction: VUADDLV, Types: OperandTypesSIMDByteToRegister, SrcReg: RegV1, DstReg: RegV2},
 			exp: "VUADDLV V1.B8, V2",
 		},
 		{
-			in:  &NodeImpl{Instruction: VBIT, Types: OperandTypesTwoSIMDBytesToSIMDByteRegister, SrcReg: REG_V1, SrcReg2: REG_V2, DstReg: REG_V3},
+			in:  &NodeImpl{Instruction: VBIT, Types: OperandTypesTwoSIMDBytesToSIMDByteRegister, SrcReg: RegV1, SrcReg2: RegV2, DstReg: RegV3},
 			exp: "VBIT (V1.B8, V2.B8), V3.B8",
 		},
 		{
 			in: &NodeImpl{Instruction: VLD1, Types: OperandTypesMemoryToVectorRegister,
-				SrcReg: REG_R1, DstReg: REG_V29, VectorArrangement: VectorArrangement2S},
+				SrcReg: RegR1, DstReg: RegV29, VectorArrangement: VectorArrangement2S},
 			exp: "VLD1 [R1], V29.2S",
 		},
 		{
 			in: &NodeImpl{Instruction: VST1, Types: OperandTypesVectorRegisterToMemory,
-				DstReg: REG_R1, SrcReg: REG_V29, VectorArrangement: VectorArrangement2S},
+				DstReg: RegR1, SrcReg: RegV29, VectorArrangement: VectorArrangement2S},
 			exp: "VST1 V29.2S, [R1]",
 		},
 		{
 			in: &NodeImpl{Instruction: VMOV, Types: OperandTypesRegisterToVectorRegister,
-				SrcReg: REG_R1, DstReg: REG_V29, VectorArrangement: VectorArrangement2D, VectorIndex: 1},
+				SrcReg: RegR1, DstReg: RegV29, VectorArrangement: VectorArrangement2D, VectorIndex: 1},
 			exp: "VMOV R1, V29.2D[1]",
 		},
 		{
 			in: &NodeImpl{Instruction: VCNT, Types: OperandTypesVectorRegisterToVectorRegister,
-				SrcReg: REG_V3, DstReg: REG_V29, VectorArrangement: VectorArrangement2D, VectorIndex: 1},
+				SrcReg: RegV3, DstReg: RegV29, VectorArrangement: VectorArrangement2D, VectorIndex: 1},
 			exp: "VCNT V3.V3, V29.V3",
 		},
 	}
@@ -135,7 +135,7 @@ func TestNodeImpl_String(t *testing.T) {
 }
 
 func TestAssemblerImpl_addNode(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
+	a := NewAssemblerImpl(RegR10)
 
 	root := &NodeImpl{}
 	a.addNode(root)
@@ -152,7 +152,7 @@ func TestAssemblerImpl_addNode(t *testing.T) {
 }
 
 func TestAssemblerImpl_newNode(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
+	a := NewAssemblerImpl(RegR10)
 	actual := a.newNode(MOVD, OperandTypesMemoryToRegister)
 	require.Equal(t, MOVD, actual.Instruction)
 	require.Equal(t, OperandTypeMemory, actual.Types.src)
@@ -162,7 +162,7 @@ func TestAssemblerImpl_newNode(t *testing.T) {
 }
 
 func TestAssemblerImpl_CompileStandAlone(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
+	a := NewAssemblerImpl(RegR10)
 	a.CompileStandAlone(RET)
 	actualNode := a.Current
 	require.Equal(t, RET, actualNode.Instruction)
@@ -171,53 +171,53 @@ func TestAssemblerImpl_CompileStandAlone(t *testing.T) {
 }
 
 func TestAssemblerImpl_CompileConstToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileConstToRegister(MOVD, 1000, REG_R10)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileConstToRegister(MOVD, 1000, RegR10)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
 	require.Equal(t, int64(1000), actualNode.SrcConst)
-	require.Equal(t, REG_R10, actualNode.DstReg)
+	require.Equal(t, RegR10, actualNode.DstReg)
 	require.Equal(t, OperandTypeConst, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func TestAssemblerImpl_CompileRegisterToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileRegisterToRegister(MOVD, REG_R15, REG_R27)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileRegisterToRegister(MOVD, RegR15, RegR27)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
-	require.Equal(t, REG_R15, actualNode.SrcReg)
-	require.Equal(t, REG_R27, actualNode.DstReg)
+	require.Equal(t, RegR15, actualNode.SrcReg)
+	require.Equal(t, RegR27, actualNode.DstReg)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func TestAssemblerImpl_CompileMemoryToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileMemoryToRegister(MOVD, REG_R15, 100, REG_R27)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileMemoryToRegister(MOVD, RegR15, 100, RegR27)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
-	require.Equal(t, REG_R15, actualNode.SrcReg)
+	require.Equal(t, RegR15, actualNode.SrcReg)
 	require.Equal(t, int64(100), actualNode.SrcConst)
-	require.Equal(t, REG_R27, actualNode.DstReg)
+	require.Equal(t, RegR27, actualNode.DstReg)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func TestAssemblerImpl_CompileRegisterToMemory(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileRegisterToMemory(MOVD, REG_R15, REG_R27, 100)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileRegisterToMemory(MOVD, RegR15, RegR27, 100)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
-	require.Equal(t, REG_R15, actualNode.SrcReg)
-	require.Equal(t, REG_R27, actualNode.DstReg)
+	require.Equal(t, RegR15, actualNode.SrcReg)
+	require.Equal(t, RegR27, actualNode.DstReg)
 	require.Equal(t, int64(100), actualNode.DstConst)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.dst)
 }
 
 func TestAssemblerImpl_CompileJump(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
+	a := NewAssemblerImpl(RegR10)
 	a.CompileJump(B)
 	actualNode := a.Current
 	require.Equal(t, B, actualNode.Instruction)
@@ -226,196 +226,196 @@ func TestAssemblerImpl_CompileJump(t *testing.T) {
 }
 
 func TestAssemblerImpl_CompileJumpToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileJumpToRegister(BNE, REG_R27)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileJumpToRegister(BNE, RegR27)
 	actualNode := a.Current
 	require.Equal(t, BNE, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.DstReg)
+	require.Equal(t, RegR27, actualNode.DstReg)
 	require.Equal(t, OperandTypeNone, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func TestAssemblerImpl_CompileJumpToMemory(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileJumpToMemory(BNE, REG_R27)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileJumpToMemory(BNE, RegR27)
 	actualNode := a.Current
 	require.Equal(t, BNE, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.DstReg)
+	require.Equal(t, RegR27, actualNode.DstReg)
 	require.Equal(t, OperandTypeNone, actualNode.Types.src)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.dst)
 }
 
 func TestAssemblerImpl_CompileReadInstructionAddress(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileReadInstructionAddress(REG_R10, RET)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileReadInstructionAddress(RegR10, RET)
 	actualNode := a.Current
 	require.Equal(t, ADR, actualNode.Instruction)
-	require.Equal(t, REG_R10, actualNode.DstReg)
+	require.Equal(t, RegR10, actualNode.DstReg)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 	require.Equal(t, RET, actualNode.readInstructionAddressBeforeTargetInstruction)
 }
 
 func Test_CompileMemoryWithRegisterOffsetToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileMemoryWithRegisterOffsetToRegister(MOVD, REG_R27, REG_R10, REG_R0)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileMemoryWithRegisterOffsetToRegister(MOVD, RegR27, RegR10, RegR0)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.SrcReg2)
-	require.Equal(t, REG_R0, actualNode.DstReg)
+	require.Equal(t, RegR27, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.SrcReg2)
+	require.Equal(t, RegR0, actualNode.DstReg)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func Test_CompileRegisterToMemoryWithRegisterOffset(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileRegisterToMemoryWithRegisterOffset(MOVD, REG_R27, REG_R10, REG_R0)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileRegisterToMemoryWithRegisterOffset(MOVD, RegR27, RegR10, RegR0)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.DstReg)
-	require.Equal(t, REG_R0, actualNode.DstReg2)
+	require.Equal(t, RegR27, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.DstReg)
+	require.Equal(t, RegR0, actualNode.DstReg2)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.dst)
 }
 
 func Test_CompileTwoRegistersToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileTwoRegistersToRegister(MOVD, REG_R27, REG_R10, REG_R0)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileTwoRegistersToRegister(MOVD, RegR27, RegR10, RegR0)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.SrcReg2)
-	require.Equal(t, REG_R0, actualNode.DstReg)
+	require.Equal(t, RegR27, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.SrcReg2)
+	require.Equal(t, RegR0, actualNode.DstReg)
 	require.Equal(t, OperandTypeTwoRegisters, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func Test_CompileThreeRegistersToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileThreeRegistersToRegister(MOVD, REG_R27, REG_R10, REG_R0, REG_R28)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileThreeRegistersToRegister(MOVD, RegR27, RegR10, RegR0, RegR28)
 	actualNode := a.Current
 	require.Equal(t, MOVD, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.SrcReg2)
-	require.Equal(t, REG_R0, actualNode.DstReg)
-	require.Equal(t, REG_R28, actualNode.DstReg2)
+	require.Equal(t, RegR27, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.SrcReg2)
+	require.Equal(t, RegR0, actualNode.DstReg)
+	require.Equal(t, RegR28, actualNode.DstReg2)
 	require.Equal(t, OperandTypeThreeRegisters, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func Test_CompileTwoRegistersToNone(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileTwoRegistersToNone(CMP, REG_R27, REG_R10)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileTwoRegistersToNone(CMP, RegR27, RegR10)
 	actualNode := a.Current
 	require.Equal(t, CMP, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.SrcReg2)
+	require.Equal(t, RegR27, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.SrcReg2)
 	require.Equal(t, OperandTypeTwoRegisters, actualNode.Types.src)
 	require.Equal(t, OperandTypeNone, actualNode.Types.dst)
 }
 
 func Test_CompileRegisterAndConstToNone(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileRegisterAndConstToNone(CMP, REG_R27, 10)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileRegisterAndConstToNone(CMP, RegR27, 10)
 	actualNode := a.Current
 	require.Equal(t, CMP, actualNode.Instruction)
-	require.Equal(t, REG_R27, actualNode.SrcReg)
+	require.Equal(t, RegR27, actualNode.SrcReg)
 	require.Equal(t, int64(10), actualNode.SrcConst)
 	require.Equal(t, OperandTypeRegisterAndConst, actualNode.Types.src)
 	require.Equal(t, OperandTypeNone, actualNode.Types.dst)
 }
 
 func Test_CompileLeftShiftedRegisterToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileLeftShiftedRegisterToRegister(ADD, REG_R27, 10, REG_R28, REG_R5)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileLeftShiftedRegisterToRegister(ADD, RegR27, 10, RegR28, RegR5)
 	actualNode := a.Current
 	require.Equal(t, ADD, actualNode.Instruction)
-	require.Equal(t, REG_R28, actualNode.SrcReg)
-	require.Equal(t, REG_R27, actualNode.SrcReg2)
+	require.Equal(t, RegR28, actualNode.SrcReg)
+	require.Equal(t, RegR27, actualNode.SrcReg2)
 	require.Equal(t, int64(10), actualNode.SrcConst)
-	require.Equal(t, REG_R5, actualNode.DstReg)
+	require.Equal(t, RegR5, actualNode.DstReg)
 	require.Equal(t, OperandTypeLeftShiftedRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func Test_CompileSIMDByteToSIMDByte(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileSIMDByteToSIMDByte(VCNT, REG_V0, REG_V2)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileSIMDByteToSIMDByte(VCNT, RegV0, RegV2)
 	actualNode := a.Current
 	require.Equal(t, VCNT, actualNode.Instruction)
-	require.Equal(t, REG_V0, actualNode.SrcReg)
-	require.Equal(t, REG_V2, actualNode.DstReg)
+	require.Equal(t, RegV0, actualNode.SrcReg)
+	require.Equal(t, RegV2, actualNode.DstReg)
 	require.Equal(t, OperandTypeSIMDByte, actualNode.Types.src)
 	require.Equal(t, OperandTypeSIMDByte, actualNode.Types.dst)
 }
 
 func Test_CompileTwoSIMDBytesToSIMDByteRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileTwoSIMDBytesToSIMDByteRegister(VBIT, REG_V0, REG_V10, REG_V2)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileTwoSIMDBytesToSIMDByteRegister(VBIT, RegV0, RegV10, RegV2)
 	actualNode := a.Current
 	require.Equal(t, VBIT, actualNode.Instruction)
-	require.Equal(t, REG_V0, actualNode.SrcReg)
-	require.Equal(t, REG_V10, actualNode.SrcReg2)
-	require.Equal(t, REG_V2, actualNode.DstReg)
+	require.Equal(t, RegV0, actualNode.SrcReg)
+	require.Equal(t, RegV10, actualNode.SrcReg2)
+	require.Equal(t, RegV2, actualNode.DstReg)
 	require.Equal(t, OperandTypeTwoSIMDBytes, actualNode.Types.src)
 	require.Equal(t, OperandTypeSIMDByte, actualNode.Types.dst)
 }
 
 func Test_CompileSIMDByteToRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileSIMDByteToRegister(VUADDLV, REG_V0, REG_V10)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileSIMDByteToRegister(VUADDLV, RegV0, RegV10)
 	actualNode := a.Current
 	require.Equal(t, VUADDLV, actualNode.Instruction)
-	require.Equal(t, REG_V0, actualNode.SrcReg)
-	require.Equal(t, REG_V10, actualNode.DstReg)
+	require.Equal(t, RegV0, actualNode.SrcReg)
+	require.Equal(t, RegV10, actualNode.DstReg)
 	require.Equal(t, OperandTypeSIMDByte, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func Test_CompileConditionalRegisterSet(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileConditionalRegisterSet(COND_NE, REG_R10)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileConditionalRegisterSet(CondNE, RegR10)
 	actualNode := a.Current
 	require.Equal(t, CSET, actualNode.Instruction)
-	require.Equal(t, REG_COND_NE, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.DstReg)
+	require.Equal(t, RegCondNE, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.DstReg)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.dst)
 }
 
 func Test_CompileMemoryToVectorRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileMemoryToVectorRegister(VMOV, REG_R10, REG_V3, VectorArrangement1D)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileMemoryToVectorRegister(VMOV, RegR10, RegV3, VectorArrangement1D)
 	actualNode := a.Current
 	require.Equal(t, VMOV, actualNode.Instruction)
-	require.Equal(t, REG_R10, actualNode.SrcReg)
-	require.Equal(t, REG_V3, actualNode.DstReg)
+	require.Equal(t, RegR10, actualNode.SrcReg)
+	require.Equal(t, RegV3, actualNode.DstReg)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.src)
 	require.Equal(t, OperandTypeVectorRegister, actualNode.Types.dst)
 	require.Equal(t, VectorArrangement1D, actualNode.VectorArrangement)
 }
 
 func Test_CompileVectorRegisterToMemory(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileVectorRegisterToMemory(VMOV, REG_V3, REG_R10, VectorArrangement1D)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileVectorRegisterToMemory(VMOV, RegV3, RegR10, VectorArrangement1D)
 	actualNode := a.Current
 	require.Equal(t, VMOV, actualNode.Instruction)
-	require.Equal(t, REG_V3, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.DstReg)
+	require.Equal(t, RegV3, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.DstReg)
 	require.Equal(t, OperandTypeVectorRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeMemory, actualNode.Types.dst)
 	require.Equal(t, VectorArrangement1D, actualNode.VectorArrangement)
 }
 
 func Test_CompileRegisterToVectorRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileRegisterToVectorRegister(VMOV, REG_V3, REG_R10, VectorArrangement1D, 10)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileRegisterToVectorRegister(VMOV, RegV3, RegR10, VectorArrangement1D, 10)
 	actualNode := a.Current
 	require.Equal(t, VMOV, actualNode.Instruction)
-	require.Equal(t, REG_V3, actualNode.SrcReg)
-	require.Equal(t, REG_R10, actualNode.DstReg)
+	require.Equal(t, RegV3, actualNode.SrcReg)
+	require.Equal(t, RegR10, actualNode.DstReg)
 	require.Equal(t, OperandTypeRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeVectorRegister, actualNode.Types.dst)
 	require.Equal(t, VectorArrangement1D, actualNode.VectorArrangement)
@@ -423,12 +423,12 @@ func Test_CompileRegisterToVectorRegister(t *testing.T) {
 }
 
 func Test_CompileVectorRegisterToVectorRegister(t *testing.T) {
-	a := NewAssemblerImpl(REG_R10)
-	a.CompileVectorRegisterToVectorRegister(VMOV, REG_V3, REG_V10, VectorArrangement1D)
+	a := NewAssemblerImpl(RegR10)
+	a.CompileVectorRegisterToVectorRegister(VMOV, RegV3, RegV10, VectorArrangement1D)
 	actualNode := a.Current
 	require.Equal(t, VMOV, actualNode.Instruction)
-	require.Equal(t, REG_V3, actualNode.SrcReg)
-	require.Equal(t, REG_V10, actualNode.DstReg)
+	require.Equal(t, RegV3, actualNode.SrcReg)
+	require.Equal(t, RegV10, actualNode.DstReg)
 	require.Equal(t, OperandTypeVectorRegister, actualNode.Types.src)
 	require.Equal(t, OperandTypeVectorRegister, actualNode.Types.dst)
 	require.Equal(t, VectorArrangement1D, actualNode.VectorArrangement)
@@ -440,25 +440,25 @@ func Test_checkRegisterToRegisterType(t *testing.T) {
 		requireSrcInt, requireDstInt bool
 		expErr                       string
 	}{
-		{src: REG_R10, dst: REG_R30, requireSrcInt: true, requireDstInt: true, expErr: ""},
-		{src: REG_R10, dst: REG_R30, requireSrcInt: false, requireDstInt: true, expErr: "src requires float register but got R10"},
-		{src: REG_R10, dst: REG_R30, requireSrcInt: false, requireDstInt: false, expErr: "src requires float register but got R10"},
-		{src: REG_R10, dst: REG_R30, requireSrcInt: true, requireDstInt: false, expErr: "dst requires float register but got R30"},
-
-		{src: REG_R10, dst: REG_V30, requireSrcInt: true, requireDstInt: false, expErr: ""},
-		{src: REG_R10, dst: REG_V30, requireSrcInt: false, requireDstInt: true, expErr: "src requires float register but got R10"},
-		{src: REG_R10, dst: REG_V30, requireSrcInt: false, requireDstInt: false, expErr: "src requires float register but got R10"},
-		{src: REG_R10, dst: REG_V30, requireSrcInt: true, requireDstInt: true, expErr: "dst requires int register but got V30"},
-
-		{src: REG_V10, dst: REG_R30, requireSrcInt: false, requireDstInt: true, expErr: ""},
-		{src: REG_V10, dst: REG_R30, requireSrcInt: true, requireDstInt: true, expErr: "src requires int register but got V10"},
-		{src: REG_V10, dst: REG_R30, requireSrcInt: true, requireDstInt: false, expErr: "src requires int register but got V10"},
-		{src: REG_V10, dst: REG_R30, requireSrcInt: false, requireDstInt: false, expErr: "dst requires float register but got R30"},
-
-		{src: REG_V10, dst: REG_V30, requireSrcInt: false, requireDstInt: false, expErr: ""},
-		{src: REG_V10, dst: REG_V30, requireSrcInt: true, requireDstInt: false, expErr: "src requires int register but got V10"},
-		{src: REG_V10, dst: REG_V30, requireSrcInt: true, requireDstInt: true, expErr: "src requires int register but got V10"},
-		{src: REG_V10, dst: REG_V30, requireSrcInt: false, requireDstInt: true, expErr: "dst requires int register but got V30"},
+		{src: RegR10, dst: RegR30, requireSrcInt: true, requireDstInt: true, expErr: ""},
+		{src: RegR10, dst: RegR30, requireSrcInt: false, requireDstInt: true, expErr: "src requires float register but got R10"},
+		{src: RegR10, dst: RegR30, requireSrcInt: false, requireDstInt: false, expErr: "src requires float register but got R10"},
+		{src: RegR10, dst: RegR30, requireSrcInt: true, requireDstInt: false, expErr: "dst requires float register but got R30"},
+
+		{src: RegR10, dst: RegV30, requireSrcInt: true, requireDstInt: false, expErr: ""},
+		{src: RegR10, dst: RegV30, requireSrcInt: false, requireDstInt: true, expErr: "src requires float register but got R10"},
+		{src: RegR10, dst: RegV30, requireSrcInt: false, requireDstInt: false, expErr: "src requires float register but got R10"},
+		{src: RegR10, dst: RegV30, requireSrcInt: true, requireDstInt: true, expErr: "dst requires int register but got V30"},
+
+		{src: RegV10, dst: RegR30, requireSrcInt: false, requireDstInt: true, expErr: ""},
+		{src: RegV10, dst: RegR30, requireSrcInt: true, requireDstInt: true, expErr: "src requires int register but got V10"},
+		{src: RegV10, dst: RegR30, requireSrcInt: true, requireDstInt: false, expErr: "src requires int register but got V10"},
+		{src: RegV10, dst: RegR30, requireSrcInt: false, requireDstInt: false, expErr: "dst requires float register but got R30"},
+
+		{src: RegV10, dst: RegV30, requireSrcInt: false, requireDstInt: false, expErr: ""},
+		{src: RegV10, dst: RegV30, requireSrcInt: true, requireDstInt: false, expErr: "src requires int register but got V10"},
+		{src: RegV10, dst: RegV30, requireSrcInt: true, requireDstInt: true, expErr: "src requires int register but got V10"},
+		{src: RegV10, dst: RegV30, requireSrcInt: false, requireDstInt: true, expErr: "dst requires int register but got V30"},
 	}
 
 	for _, tt := range tests {
@@ -494,7 +494,7 @@ func Test_validateMemoryOffset(t *testing.T) {
 }
 
 func TestAssemblerImpl_EncodeVectorRegisterToVectorRegister(t *testing.T) {
-	x1, x2 := REG_V2, REG_V10
+	x1, x2 := RegV2, RegV10
 	tests := []struct {
 		inst asm.Instruction
 		exp  []byte
diff --git a/internal/integration_test/asm/arm64_debug/golang_asm.go b/internal/integration_test/asm/arm64_debug/golang_asm.go
index 52f7f850..6ee9fd18 100644
--- a/internal/integration_test/asm/arm64_debug/golang_asm.go
+++ b/internal/integration_test/asm/arm64_debug/golang_asm.go
@@ -277,7 +277,7 @@ func (a *assemblerGoAsmImpl) CompileConditionalRegisterSet(cond asm.ConditionalR
 }
 
 // simdRegisterForScalarFloatRegister returns SIMD register which corresponds to the given scalar float register.
-// In other words, this returns: REG_F0 -> REG_V0, REG_F1 -> REG_V1, ...., REG_F31 -> REG_V31.
+// In other words, this returns: REG_F0 -> RegV0, REG_F1 -> RegV1, ...., REG_F31 -> RegV31.
 func simdRegisterForScalarFloatRegister(freg int16) int16 {
 	return freg + (arm64.REG_F31 - arm64.REG_F0) + 1
 }
@@ -445,126 +445,126 @@ var castAsGolangAsmArrangement = [...]int16{
 
 // castAsGolangAsmConditionalRegister maps the conditional states to golang-asm specific conditional state register values.
 var castAsGolangAsmConditionalRegister = [...]int16{
-	asm_arm64.COND_EQ: arm64.COND_EQ,
-	asm_arm64.COND_NE: arm64.COND_NE,
-	asm_arm64.COND_HS: arm64.COND_HS,
-	asm_arm64.COND_LO: arm64.COND_LO,
-	asm_arm64.COND_MI: arm64.COND_MI,
-	asm_arm64.COND_PL: arm64.COND_PL,
-	asm_arm64.COND_VS: arm64.COND_VS,
-	asm_arm64.COND_VC: arm64.COND_VC,
-	asm_arm64.COND_HI: arm64.COND_HI,
-	asm_arm64.COND_LS: arm64.COND_LS,
-	asm_arm64.COND_GE: arm64.COND_GE,
-	asm_arm64.COND_LT: arm64.COND_LT,
-	asm_arm64.COND_GT: arm64.COND_GT,
-	asm_arm64.COND_LE: arm64.COND_LE,
-	asm_arm64.COND_AL: arm64.COND_AL,
-	asm_arm64.COND_NV: arm64.COND_NV,
+	asm_arm64.CondEQ: arm64.COND_EQ,
+	asm_arm64.CondNE: arm64.COND_NE,
+	asm_arm64.CondHS: arm64.COND_HS,
+	asm_arm64.CondLO: arm64.COND_LO,
+	asm_arm64.CondMI: arm64.COND_MI,
+	asm_arm64.CondPL: arm64.COND_PL,
+	asm_arm64.CondVS: arm64.COND_VS,
+	asm_arm64.CondVC: arm64.COND_VC,
+	asm_arm64.CondHI: arm64.COND_HI,
+	asm_arm64.CondLS: arm64.COND_LS,
+	asm_arm64.CondGE: arm64.COND_GE,
+	asm_arm64.CondLT: arm64.COND_LT,
+	asm_arm64.CondGT: arm64.COND_GT,
+	asm_arm64.CondLE: arm64.COND_LE,
+	asm_arm64.CondAL: arm64.COND_AL,
+	asm_arm64.CondNV: arm64.COND_NV,
 }
 
 var castAsGolangAsVectorRegister = [...]int16{
-	asm_arm64.REG_V0:  arm64.REG_V0,
-	asm_arm64.REG_V1:  arm64.REG_V1,
-	asm_arm64.REG_V2:  arm64.REG_V2,
-	asm_arm64.REG_V3:  arm64.REG_V3,
-	asm_arm64.REG_V4:  arm64.REG_V4,
-	asm_arm64.REG_V5:  arm64.REG_V5,
-	asm_arm64.REG_V6:  arm64.REG_V6,
-	asm_arm64.REG_V7:  arm64.REG_V7,
-	asm_arm64.REG_V8:  arm64.REG_V8,
-	asm_arm64.REG_V9:  arm64.REG_V9,
-	asm_arm64.REG_V10: arm64.REG_V10,
-	asm_arm64.REG_V11: arm64.REG_V11,
-	asm_arm64.REG_V12: arm64.REG_V12,
-	asm_arm64.REG_V13: arm64.REG_V13,
-	asm_arm64.REG_V14: arm64.REG_V14,
-	asm_arm64.REG_V15: arm64.REG_V15,
-	asm_arm64.REG_V16: arm64.REG_V16,
-	asm_arm64.REG_V17: arm64.REG_V17,
-	asm_arm64.REG_V18: arm64.REG_V18,
-	asm_arm64.REG_V19: arm64.REG_V19,
-	asm_arm64.REG_V20: arm64.REG_V20,
-	asm_arm64.REG_V21: arm64.REG_V21,
-	asm_arm64.REG_V22: arm64.REG_V22,
-	asm_arm64.REG_V23: arm64.REG_V23,
-	asm_arm64.REG_V24: arm64.REG_V24,
-	asm_arm64.REG_V25: arm64.REG_V25,
-	asm_arm64.REG_V26: arm64.REG_V26,
-	asm_arm64.REG_V27: arm64.REG_V27,
-	asm_arm64.REG_V28: arm64.REG_V28,
-	asm_arm64.REG_V29: arm64.REG_V29,
-	asm_arm64.REG_V30: arm64.REG_V30,
-	asm_arm64.REG_V31: arm64.REG_V31,
+	asm_arm64.RegV0:  arm64.REG_V0,
+	asm_arm64.RegV1:  arm64.REG_V1,
+	asm_arm64.RegV2:  arm64.REG_V2,
+	asm_arm64.RegV3:  arm64.REG_V3,
+	asm_arm64.RegV4:  arm64.REG_V4,
+	asm_arm64.RegV5:  arm64.REG_V5,
+	asm_arm64.RegV6:  arm64.REG_V6,
+	asm_arm64.RegV7:  arm64.REG_V7,
+	asm_arm64.RegV8:  arm64.REG_V8,
+	asm_arm64.RegV9:  arm64.REG_V9,
+	asm_arm64.RegV10: arm64.REG_V10,
+	asm_arm64.RegV11: arm64.REG_V11,
+	asm_arm64.RegV12: arm64.REG_V12,
+	asm_arm64.RegV13: arm64.REG_V13,
+	asm_arm64.RegV14: arm64.REG_V14,
+	asm_arm64.RegV15: arm64.REG_V15,
+	asm_arm64.RegV16: arm64.REG_V16,
+	asm_arm64.RegV17: arm64.REG_V17,
+	asm_arm64.RegV18: arm64.REG_V18,
+	asm_arm64.RegV19: arm64.REG_V19,
+	asm_arm64.RegV20: arm64.REG_V20,
+	asm_arm64.RegV21: arm64.REG_V21,
+	asm_arm64.RegV22: arm64.REG_V22,
+	asm_arm64.RegV23: arm64.REG_V23,
+	asm_arm64.RegV24: arm64.REG_V24,
+	asm_arm64.RegV25: arm64.REG_V25,
+	asm_arm64.RegV26: arm64.REG_V26,
+	asm_arm64.RegV27: arm64.REG_V27,
+	asm_arm64.RegV28: arm64.REG_V28,
+	asm_arm64.RegV29: arm64.REG_V29,
+	asm_arm64.RegV30: arm64.REG_V30,
+	asm_arm64.RegV31: arm64.REG_V31,
 }
 
 // castAsGolangAsmRegister maps the registers to golang-asm specific registers values.
 var castAsGolangAsmRegister = [...]int16{
-	asm_arm64.REG_R0:   arm64.REG_R0,
-	asm_arm64.REG_R1:   arm64.REG_R1,
-	asm_arm64.REG_R2:   arm64.REG_R2,
-	asm_arm64.REG_R3:   arm64.REG_R3,
-	asm_arm64.REG_R4:   arm64.REG_R4,
-	asm_arm64.REG_R5:   arm64.REG_R5,
-	asm_arm64.REG_R6:   arm64.REG_R6,
-	asm_arm64.REG_R7:   arm64.REG_R7,
-	asm_arm64.REG_R8:   arm64.REG_R8,
-	asm_arm64.REG_R9:   arm64.REG_R9,
-	asm_arm64.REG_R10:  arm64.REG_R10,
-	asm_arm64.REG_R11:  arm64.REG_R11,
-	asm_arm64.REG_R12:  arm64.REG_R12,
-	asm_arm64.REG_R13:  arm64.REG_R13,
-	asm_arm64.REG_R14:  arm64.REG_R14,
-	asm_arm64.REG_R15:  arm64.REG_R15,
-	asm_arm64.REG_R16:  arm64.REG_R16,
-	asm_arm64.REG_R17:  arm64.REG_R17,
-	asm_arm64.REG_R18:  arm64.REG_R18,
-	asm_arm64.REG_R19:  arm64.REG_R19,
-	asm_arm64.REG_R20:  arm64.REG_R20,
-	asm_arm64.REG_R21:  arm64.REG_R21,
-	asm_arm64.REG_R22:  arm64.REG_R22,
-	asm_arm64.REG_R23:  arm64.REG_R23,
-	asm_arm64.REG_R24:  arm64.REG_R24,
-	asm_arm64.REG_R25:  arm64.REG_R25,
-	asm_arm64.REG_R26:  arm64.REG_R26,
-	asm_arm64.REG_R27:  arm64.REG_R27,
-	asm_arm64.REG_R28:  arm64.REG_R28,
-	asm_arm64.REG_R29:  arm64.REG_R29,
-	asm_arm64.REG_R30:  arm64.REG_R30,
-	asm_arm64.REGZERO:  arm64.REGZERO,
-	asm_arm64.REG_V0:   arm64.REG_F0,
-	asm_arm64.REG_V1:   arm64.REG_F1,
-	asm_arm64.REG_V2:   arm64.REG_F2,
-	asm_arm64.REG_V3:   arm64.REG_F3,
-	asm_arm64.REG_V4:   arm64.REG_F4,
-	asm_arm64.REG_V5:   arm64.REG_F5,
-	asm_arm64.REG_V6:   arm64.REG_F6,
-	asm_arm64.REG_V7:   arm64.REG_F7,
-	asm_arm64.REG_V8:   arm64.REG_F8,
-	asm_arm64.REG_V9:   arm64.REG_F9,
-	asm_arm64.REG_V10:  arm64.REG_F10,
-	asm_arm64.REG_V11:  arm64.REG_F11,
-	asm_arm64.REG_V12:  arm64.REG_F12,
-	asm_arm64.REG_V13:  arm64.REG_F13,
-	asm_arm64.REG_V14:  arm64.REG_F14,
-	asm_arm64.REG_V15:  arm64.REG_F15,
-	asm_arm64.REG_V16:  arm64.REG_F16,
-	asm_arm64.REG_V17:  arm64.REG_F17,
-	asm_arm64.REG_V18:  arm64.REG_F18,
-	asm_arm64.REG_V19:  arm64.REG_F19,
-	asm_arm64.REG_V20:  arm64.REG_F20,
-	asm_arm64.REG_V21:  arm64.REG_F21,
-	asm_arm64.REG_V22:  arm64.REG_F22,
-	asm_arm64.REG_V23:  arm64.REG_F23,
-	asm_arm64.REG_V24:  arm64.REG_F24,
-	asm_arm64.REG_V25:  arm64.REG_F25,
-	asm_arm64.REG_V26:  arm64.REG_F26,
-	asm_arm64.REG_V27:  arm64.REG_F27,
-	asm_arm64.REG_V28:  arm64.REG_F28,
-	asm_arm64.REG_V29:  arm64.REG_F29,
-	asm_arm64.REG_V30:  arm64.REG_F30,
-	asm_arm64.REG_V31:  arm64.REG_F31,
-	asm_arm64.REG_FPSR: arm64.REG_FPSR,
+	asm_arm64.RegR0:   arm64.REG_R0,
+	asm_arm64.RegR1:   arm64.REG_R1,
+	asm_arm64.RegR2:   arm64.REG_R2,
+	asm_arm64.RegR3:   arm64.REG_R3,
+	asm_arm64.RegR4:   arm64.REG_R4,
+	asm_arm64.RegR5:   arm64.REG_R5,
+	asm_arm64.RegR6:   arm64.REG_R6,
+	asm_arm64.RegR7:   arm64.REG_R7,
+	asm_arm64.RegR8:   arm64.REG_R8,
+	asm_arm64.RegR9:   arm64.REG_R9,
+	asm_arm64.RegR10:  arm64.REG_R10,
+	asm_arm64.RegR11:  arm64.REG_R11,
+	asm_arm64.RegR12:  arm64.REG_R12,
+	asm_arm64.RegR13:  arm64.REG_R13,
+	asm_arm64.RegR14:  arm64.REG_R14,
+	asm_arm64.RegR15:  arm64.REG_R15,
+	asm_arm64.RegR16:  arm64.REG_R16,
+	asm_arm64.RegR17:  arm64.REG_R17,
+	asm_arm64.RegR18:  arm64.REG_R18,
+	asm_arm64.RegR19:  arm64.REG_R19,
+	asm_arm64.RegR20:  arm64.REG_R20,
+	asm_arm64.RegR21:  arm64.REG_R21,
+	asm_arm64.RegR22:  arm64.REG_R22,
+	asm_arm64.RegR23:  arm64.REG_R23,
+	asm_arm64.RegR24:  arm64.REG_R24,
+	asm_arm64.RegR25:  arm64.REG_R25,
+	asm_arm64.RegR26:  arm64.REG_R26,
+	asm_arm64.RegR27:  arm64.REG_R27,
+	asm_arm64.RegR28:  arm64.REG_R28,
+	asm_arm64.RegR29:  arm64.REG_R29,
+	asm_arm64.RegR30:  arm64.REG_R30,
+	asm_arm64.RegRZR:  arm64.REGZERO,
+	asm_arm64.RegV0:   arm64.REG_F0,
+	asm_arm64.RegV1:   arm64.REG_F1,
+	asm_arm64.RegV2:   arm64.REG_F2,
+	asm_arm64.RegV3:   arm64.REG_F3,
+	asm_arm64.RegV4:   arm64.REG_F4,
+	asm_arm64.RegV5:   arm64.REG_F5,
+	asm_arm64.RegV6:   arm64.REG_F6,
+	asm_arm64.RegV7:   arm64.REG_F7,
+	asm_arm64.RegV8:   arm64.REG_F8,
+	asm_arm64.RegV9:   arm64.REG_F9,
+	asm_arm64.RegV10:  arm64.REG_F10,
+	asm_arm64.RegV11:  arm64.REG_F11,
+	asm_arm64.RegV12:  arm64.REG_F12,
+	asm_arm64.RegV13:  arm64.REG_F13,
+	asm_arm64.RegV14:  arm64.REG_F14,
+	asm_arm64.RegV15:  arm64.REG_F15,
+	asm_arm64.RegV16:  arm64.REG_F16,
+	asm_arm64.RegV17:  arm64.REG_F17,
+	asm_arm64.RegV18:  arm64.REG_F18,
+	asm_arm64.RegV19:  arm64.REG_F19,
+	asm_arm64.RegV20:  arm64.REG_F20,
+	asm_arm64.RegV21:  arm64.REG_F21,
+	asm_arm64.RegV22:  arm64.REG_F22,
+	asm_arm64.RegV23:  arm64.REG_F23,
+	asm_arm64.RegV24:  arm64.REG_F24,
+	asm_arm64.RegV25:  arm64.REG_F25,
+	asm_arm64.RegV26:  arm64.REG_F26,
+	asm_arm64.RegV27:  arm64.REG_F27,
+	asm_arm64.RegV28:  arm64.REG_F28,
+	asm_arm64.RegV29:  arm64.REG_F29,
+	asm_arm64.RegV30:  arm64.REG_F30,
+	asm_arm64.RegV31:  arm64.REG_F31,
+	asm_arm64.RegFPSR: arm64.REG_FPSR,
 }
 
 // castAsGolangAsmInstruction maps the instructions to golang-asm specific instructions values.
@@ -685,7 +685,6 @@ var castAsGolangAsmInstruction = [...]obj.As{
 	asm_arm64.UCVTFWS:  arm64.AUCVTFWS,
 	asm_arm64.UDIV:     arm64.AUDIV,
 	asm_arm64.UDIVW:    arm64.AUDIVW,
-	asm_arm64.UXTW:     arm64.AUXTW,
 	asm_arm64.VBIT:     arm64.AVBIT,
 	asm_arm64.VCNT:     arm64.AVCNT,
 	asm_arm64.VUADDLV:  arm64.AVUADDLV,
diff --git a/internal/integration_test/asm/arm64_debug/impl_test.go b/internal/integration_test/asm/arm64_debug/impl_test.go
index b6265776..e63c47dd 100644
--- a/internal/integration_test/asm/arm64_debug/impl_test.go
+++ b/internal/integration_test/asm/arm64_debug/impl_test.go
@@ -37,11 +37,11 @@ func TestAssemblerImpl_encodeNoneToNone(t *testing.T) {
 }
 
 var intRegisters = []asm.Register{
-	arm64.REG_R0, arm64.REG_R1, arm64.REG_R2, arm64.REG_R3, arm64.REG_R4, arm64.REG_R5, arm64.REG_R6,
-	arm64.REG_R7, arm64.REG_R8, arm64.REG_R9, arm64.REG_R10, arm64.REG_R11, arm64.REG_R12, arm64.REG_R13,
-	arm64.REG_R14, arm64.REG_R15, arm64.REG_R16, arm64.REG_R17, arm64.REG_R18, arm64.REG_R19, arm64.REG_R20,
-	arm64.REG_R21, arm64.REG_R22, arm64.REG_R23, arm64.REG_R24, arm64.REG_R25, arm64.REG_R26, arm64.REG_R27,
-	arm64.REG_R28, arm64.REG_R29, arm64.REG_R30,
+	arm64.RegR0, arm64.RegR1, arm64.RegR2, arm64.RegR3, arm64.RegR4, arm64.RegR5, arm64.RegR6,
+	arm64.RegR7, arm64.RegR8, arm64.RegR9, arm64.RegR10, arm64.RegR11, arm64.RegR12, arm64.RegR13,
+	arm64.RegR14, arm64.RegR15, arm64.RegR16, arm64.RegR17, arm64.RegR18, arm64.RegR19, arm64.RegR20,
+	arm64.RegR21, arm64.RegR22, arm64.RegR23, arm64.RegR24, arm64.RegR25, arm64.RegR26, arm64.RegR27,
+	arm64.RegR28, arm64.RegR29, arm64.RegR30,
 }
 
 func TestAssemblerImpl_EncodeJumpToRegister(t *testing.T) {
@@ -59,7 +59,7 @@ func TestAssemblerImpl_EncodeJumpToRegister(t *testing.T) {
 				expErr: "invalid destination register: nil is not integer",
 			},
 			{
-				n:      &arm64.NodeImpl{Instruction: arm64.RET, DstReg: arm64.REG_V0},
+				n:      &arm64.NodeImpl{Instruction: arm64.RET, DstReg: arm64.RegV0},
 				expErr: "invalid destination register: V0 is not integer",
 			},
 		}
@@ -112,27 +112,27 @@ func TestAssemblerImpl_EncodeLeftShiftedRegisterToRegister(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.SUB, Types: arm64.OperandTypesLeftShiftedRegisterToRegister,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "SUB is unsupported for from:left-shifted-register,to:register type",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADD,
-					SrcConst: -1, SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcConst: -1, SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "shift amount must fit in unsigned 6-bit integer (0-64) but got -1",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADD,
-					SrcConst: -1, SrcReg: arm64.REG_V0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcConst: -1, SrcReg: arm64.RegV0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "V0 is not integer",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADD,
-					SrcConst: -1, SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_V0, DstReg: arm64.REG_R0},
+					SrcConst: -1, SrcReg: arm64.RegR0, SrcReg2: arm64.RegV0, DstReg: arm64.RegR0},
 				expErr: "V0 is not integer",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADD,
-					SrcConst: -1, SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_V0},
+					SrcConst: -1, SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegV0},
 				expErr: "V0 is not integer",
 			},
 		}
@@ -151,52 +151,52 @@ func TestAssemblerImpl_EncodeLeftShiftedRegisterToRegister(t *testing.T) {
 		shiftNum                      int64
 	}{
 		{
-			srcReg:        arm64.REG_R0,
-			shiftedSrcReg: arm64.REG_R29,
+			srcReg:        arm64.RegR0,
+			shiftedSrcReg: arm64.RegR29,
 			shiftNum:      1,
-			dstReg:        arm64.REG_R21,
+			dstReg:        arm64.RegR21,
 		},
 		{
-			srcReg:        arm64.REG_R0,
-			shiftedSrcReg: arm64.REG_R29,
+			srcReg:        arm64.RegR0,
+			shiftedSrcReg: arm64.RegR29,
 			shiftNum:      2,
-			dstReg:        arm64.REG_R21,
+			dstReg:        arm64.RegR21,
 		},
 		{
-			srcReg:        arm64.REG_R0,
-			shiftedSrcReg: arm64.REG_R29,
+			srcReg:        arm64.RegR0,
+			shiftedSrcReg: arm64.RegR29,
 			shiftNum:      8,
-			dstReg:        arm64.REG_R21,
+			dstReg:        arm64.RegR21,
 		},
 		{
-			srcReg:        arm64.REG_R29,
-			shiftedSrcReg: arm64.REG_R0,
+			srcReg:        arm64.RegR29,
+			shiftedSrcReg: arm64.RegR0,
 			shiftNum:      16,
-			dstReg:        arm64.REG_R21,
+			dstReg:        arm64.RegR21,
 		},
 		{
-			srcReg:        arm64.REG_R29,
-			shiftedSrcReg: arm64.REG_R0,
+			srcReg:        arm64.RegR29,
+			shiftedSrcReg: arm64.RegR0,
 			shiftNum:      64,
-			dstReg:        arm64.REG_R21,
+			dstReg:        arm64.RegR21,
 		},
 		{
-			srcReg:        arm64.REGZERO,
-			shiftedSrcReg: arm64.REG_R0,
+			srcReg:        arm64.RegRZR,
+			shiftedSrcReg: arm64.RegR0,
 			shiftNum:      64,
-			dstReg:        arm64.REG_R21,
+			dstReg:        arm64.RegR21,
 		},
 		{
-			srcReg:        arm64.REGZERO,
-			shiftedSrcReg: arm64.REGZERO,
+			srcReg:        arm64.RegRZR,
+			shiftedSrcReg: arm64.RegRZR,
 			shiftNum:      64,
-			dstReg:        arm64.REG_R21,
+			dstReg:        arm64.RegR21,
 		},
 		{
-			srcReg:        arm64.REGZERO,
-			shiftedSrcReg: arm64.REGZERO,
+			srcReg:        arm64.RegRZR,
+			shiftedSrcReg: arm64.RegRZR,
 			shiftNum:      64,
-			dstReg:        arm64.REGZERO,
+			dstReg:        arm64.RegRZR,
 		},
 	}
 
@@ -233,17 +233,17 @@ func TestAssemblerImpl_EncodeTwoRegistersToNone(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.SUB, Types: arm64.OperandTypesTwoRegistersToNone,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "SUB is unsupported for from:two-registers,to:none type",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.CMP,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_V0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegV0},
 				expErr: "V0 is not integer",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.FCMPS,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_V0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegV0},
 				expErr: "R0 is not float",
 			},
 		}
@@ -256,8 +256,8 @@ func TestAssemblerImpl_EncodeTwoRegistersToNone(t *testing.T) {
 		}
 	})
 
-	intRegs := []asm.Register{arm64.REGZERO, arm64.REG_R0, arm64.REG_R10, arm64.REG_R30}
-	floatRegs := []asm.Register{arm64.REG_V0, arm64.REG_V12, arm64.REG_V31}
+	intRegs := []asm.Register{arm64.RegRZR, arm64.RegR0, arm64.RegR10, arm64.RegR30}
+	floatRegs := []asm.Register{arm64.RegV0, arm64.RegV12, arm64.RegV31}
 	tests := []struct {
 		instruction asm.Instruction
 		regs        []asm.Register
@@ -294,7 +294,7 @@ func TestAssemblerImpl_EncodeTwoRegistersToNone(t *testing.T) {
 }
 
 func TestAssemblerImpl_EncodeThreeRegistersToRegister(t *testing.T) {
-	intRegs := []asm.Register{arm64.REGZERO, arm64.REG_R1, arm64.REG_R10, arm64.REG_R30}
+	intRegs := []asm.Register{arm64.RegRZR, arm64.RegR1, arm64.RegR10, arm64.RegR30}
 	for _, inst := range []asm.Instruction{arm64.MSUB, arm64.MSUBW} {
 		inst := inst
 		t.Run(arm64.InstructionName(inst), func(t *testing.T) {
@@ -334,7 +334,7 @@ func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADR, Types: arm64.OperandTypesRegisterToRegister,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "ADR is unsupported for from:register,to:register type",
 			},
 		}
@@ -347,10 +347,10 @@ func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) {
 		}
 	})
 
-	intRegs := []asm.Register{arm64.REGZERO, arm64.REG_R1, arm64.REG_R10, arm64.REG_R30}
+	intRegs := []asm.Register{arm64.RegRZR, arm64.RegR1, arm64.RegR10, arm64.RegR30}
 	intRegsWithoutZero := intRegs[1:]
-	conditionalRegs := []asm.Register{arm64.REG_COND_EQ, arm64.REG_COND_NE, arm64.REG_COND_HS, arm64.REG_COND_LO, arm64.REG_COND_MI, arm64.REG_COND_PL, arm64.REG_COND_VS, arm64.REG_COND_VC, arm64.REG_COND_HI, arm64.REG_COND_LS, arm64.REG_COND_GE, arm64.REG_COND_LT, arm64.REG_COND_GT, arm64.REG_COND_LE, arm64.REG_COND_AL, arm64.REG_COND_NV}
-	floatRegs := []asm.Register{arm64.REG_V0, arm64.REG_V15, arm64.REG_V31}
+	conditionalRegs := []asm.Register{arm64.RegCondEQ, arm64.RegCondNE, arm64.RegCondHS, arm64.RegCondLO, arm64.RegCondMI, arm64.RegCondPL, arm64.RegCondVS, arm64.RegCondVC, arm64.RegCondHI, arm64.RegCondLS, arm64.RegCondGE, arm64.RegCondLT, arm64.RegCondGT, arm64.RegCondLE, arm64.RegCondAL, arm64.RegCondNV}
+	floatRegs := []asm.Register{arm64.RegV0, arm64.RegV15, arm64.RegV31}
 
 	tests := []struct {
 		inst             asm.Instruction
@@ -404,8 +404,8 @@ func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) {
 		{inst: arm64.FMOVS, srcRegs: floatRegs, dstRegs: intRegs},
 		{inst: arm64.MOVD, srcRegs: intRegs, dstRegs: intRegsWithoutZero},
 		{inst: arm64.MOVWU, srcRegs: intRegs, dstRegs: intRegs},
-		{inst: arm64.MRS, srcRegs: []asm.Register{arm64.REG_FPSR}, dstRegs: intRegs},
-		{inst: arm64.MSR, srcRegs: intRegs, dstRegs: []asm.Register{arm64.REG_FPSR}},
+		{inst: arm64.MRS, srcRegs: []asm.Register{arm64.RegFPSR}, dstRegs: intRegs},
+		{inst: arm64.MSR, srcRegs: intRegs, dstRegs: []asm.Register{arm64.RegFPSR}},
 		{inst: arm64.MUL, srcRegs: intRegs, dstRegs: intRegs},
 		{inst: arm64.MULW, srcRegs: intRegs, dstRegs: intRegs},
 		{inst: arm64.NEG, srcRegs: intRegs, dstRegs: intRegs},
@@ -470,7 +470,7 @@ func TestAssemblerImpl_EncodeTwoRegistersToRegister(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADR, Types: arm64.OperandTypesTwoRegistersToRegister,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "ADR is unsupported for from:two-registers,to:register type",
 			},
 		}
@@ -483,8 +483,8 @@ func TestAssemblerImpl_EncodeTwoRegistersToRegister(t *testing.T) {
 		}
 	})
 
-	intRegs := []asm.Register{arm64.REGZERO, arm64.REG_R1, arm64.REG_R10, arm64.REG_R30}
-	floatRegs := []asm.Register{arm64.REG_V0, arm64.REG_V15, arm64.REG_V31}
+	intRegs := []asm.Register{arm64.RegRZR, arm64.RegR1, arm64.RegR10, arm64.RegR30}
+	floatRegs := []asm.Register{arm64.RegV0, arm64.RegV15, arm64.RegV31}
 
 	tests := []struct {
 		inst             asm.Instruction
@@ -549,17 +549,17 @@ func TestAssemblerImpl_EncodeRegisterAndConstToNone(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADR, Types: arm64.OperandTypesRegisterAndConstToNone,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "ADR is unsupported for from:register-and-const,to:none type",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.CMP, Types: arm64.OperandTypesRegisterAndConstToNone,
-					SrcReg: arm64.REG_R0, SrcConst: 12345},
+					SrcReg: arm64.RegR0, SrcConst: 12345},
 				expErr: "immediate for CMP must fit in 0 to 4095 but got 12345",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.CMP, Types: arm64.OperandTypesRegisterAndConstToNone,
-					SrcReg: arm64.REGZERO, SrcConst: 123},
+					SrcReg: arm64.RegRZR, SrcConst: 123},
 				expErr: "zero register is not supported for CMP (immediate)",
 			},
 		}
@@ -573,7 +573,7 @@ func TestAssemblerImpl_EncodeRegisterAndConstToNone(t *testing.T) {
 	})
 
 	const inst = arm64.CMP
-	for _, reg := range []asm.Register{arm64.REG_R1, arm64.REG_R10, arm64.REG_R30} {
+	for _, reg := range []asm.Register{arm64.RegR1, arm64.RegR10, arm64.RegR30} {
 		for _, c := range []int64{0, 10, 100, 300, 4095} {
 			reg, c := reg, c
 			t.Run(fmt.Sprintf("%s, %d", arm64.RegisterName(reg), c), func(t *testing.T) {
@@ -605,15 +605,15 @@ func TestAssemblerImpl_EncodeConstToRegister(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.ADR, Types: arm64.OperandTypesConstToRegister,
-					SrcReg: arm64.REG_R0, SrcReg2: arm64.REG_R0, DstReg: arm64.REG_R0},
+					SrcReg: arm64.RegR0, SrcReg2: arm64.RegR0, DstReg: arm64.RegR0},
 				expErr: "ADR is unsupported for from:const,to:register type",
 			},
 			{
-				n:      &arm64.NodeImpl{Instruction: arm64.LSR, Types: arm64.OperandTypesConstToRegister, DstReg: arm64.REG_R0},
+				n:      &arm64.NodeImpl{Instruction: arm64.LSR, Types: arm64.OperandTypesConstToRegister, DstReg: arm64.RegR0},
 				expErr: "LSR with zero constant should be optimized out",
 			},
 			{
-				n:      &arm64.NodeImpl{Instruction: arm64.LSL, Types: arm64.OperandTypesConstToRegister, DstReg: arm64.REG_R0},
+				n:      &arm64.NodeImpl{Instruction: arm64.LSL, Types: arm64.OperandTypesConstToRegister, DstReg: arm64.RegR0},
 				expErr: "LSL with zero constant should be optimized out",
 			},
 		}
@@ -731,8 +731,8 @@ func TestAssemblerImpl_EncodeConstToRegister(t *testing.T) {
 		tc := tt
 		t.Run(arm64.InstructionName(tc.inst), func(t *testing.T) {
 			for _, r := range []asm.Register{
-				arm64.REG_R0, arm64.REG_R10,
-				arm64.REG_R30,
+				arm64.RegR0, arm64.RegR10,
+				arm64.RegR30,
 			} {
 				r := r
 				t.Run(arm64.RegisterName(r), func(t *testing.T) {
@@ -743,12 +743,12 @@ func TestAssemblerImpl_EncodeConstToRegister(t *testing.T) {
 						}
 						for _, c := range cs {
 							t.Run(fmt.Sprintf("0x%x", uint64(c)), func(t *testing.T) {
-								goasm := newGoasmAssembler(t, arm64.REG_R27)
+								goasm := newGoasmAssembler(t, arm64.RegR27)
 								goasm.CompileConstToRegister(tc.inst, c, r)
 								expected, err := goasm.Assemble()
 								require.NoError(t, err)
 
-								a := arm64.NewAssemblerImpl(arm64.REG_R27)
+								a := arm64.NewAssemblerImpl(arm64.RegR27)
 								err = a.EncodeConstToRegister(&arm64.NodeImpl{Instruction: tc.inst, SrcConst: c, DstReg: r})
 								require.NoError(t, err)
 
@@ -785,7 +785,7 @@ func TestAssemblerImpl_EncodeSIMDByteToSIMDByte(t *testing.T) {
 
 	const inst = arm64.VCNT
 	t.Run(arm64.InstructionName(inst), func(t *testing.T) {
-		floatRegs := []asm.Register{arm64.REG_V0, arm64.REG_V10, arm64.REG_V21, arm64.REG_V31}
+		floatRegs := []asm.Register{arm64.RegV0, arm64.RegV10, arm64.RegV21, arm64.RegV31}
 		for _, src := range floatRegs {
 			for _, dst := range floatRegs {
 				src, dst := src, dst
@@ -795,7 +795,7 @@ func TestAssemblerImpl_EncodeSIMDByteToSIMDByte(t *testing.T) {
 					expected, err := goasm.Assemble()
 					require.NoError(t, err)
 
-					a := arm64.NewAssemblerImpl(arm64.REG_R27)
+					a := arm64.NewAssemblerImpl(arm64.RegR27)
 					err = a.EncodeSIMDByteToSIMDByte(&arm64.NodeImpl{Instruction: inst, SrcReg: src, DstReg: dst})
 					require.NoError(t, err)
 
@@ -830,7 +830,7 @@ func TestAssemblerImpl_EncodeSIMDByteToRegister(t *testing.T) {
 
 	const inst = arm64.VUADDLV
 	t.Run(arm64.InstructionName(inst), func(t *testing.T) {
-		floatRegs := []asm.Register{arm64.REG_V0, arm64.REG_V10, arm64.REG_V21, arm64.REG_V31}
+		floatRegs := []asm.Register{arm64.RegV0, arm64.RegV10, arm64.RegV21, arm64.RegV31}
 		for _, src := range floatRegs {
 			for _, dst := range floatRegs {
 				src, dst := src, dst
@@ -840,7 +840,7 @@ func TestAssemblerImpl_EncodeSIMDByteToRegister(t *testing.T) {
 					expected, err := goasm.Assemble()
 					require.NoError(t, err)
 
-					a := arm64.NewAssemblerImpl(arm64.REG_R27)
+					a := arm64.NewAssemblerImpl(arm64.RegR27)
 					err = a.EncodeSIMDByteToRegister(&arm64.NodeImpl{Instruction: inst, SrcReg: src, DstReg: dst})
 					require.NoError(t, err)
 
@@ -879,12 +879,12 @@ func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) {
 		32760*2 - 16, 1 << 27, 1 << 30, 1<<30 + 8, 1<<30 - 8, 1<<30 + 16, 1<<30 - 16, 1<<31 - 8,
 	}
 	intRegs := []asm.Register{
-		arm64.REG_R0, arm64.REG_R16,
-		arm64.REG_R30,
+		arm64.RegR0, arm64.RegR16,
+		arm64.RegR30,
 	}
 	floatRegs := []asm.Register{
-		arm64.REG_V0, arm64.REG_V10,
-		arm64.REG_V30,
+		arm64.RegV0, arm64.RegV10,
+		arm64.RegV30,
 	}
 	tests := []struct {
 		inst    asm.Instruction
@@ -911,7 +911,7 @@ func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) {
 								Instruction: tc.inst, SrcReg: srcReg, DstReg: baseReg, DstConst: offset}
 							t.Run(n.String(), func(t *testing.T) {
 								goasm := newGoasmAssembler(t, asm.NilRegister)
-								a := arm64.NewAssemblerImpl(arm64.REG_R27)
+								a := arm64.NewAssemblerImpl(arm64.RegR27)
 
 								for _, assembler := range []arm64.Assembler{goasm, a} {
 									assembler.CompileRegisterToMemory(n.Instruction, n.SrcReg, n.DstReg, n.DstConst)
@@ -928,7 +928,7 @@ func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) {
 						}
 					})
 					t.Run("register offset", func(t *testing.T) {
-						for _, offsetReg := range []asm.Register{arm64.REG_R8, arm64.REG_R18} {
+						for _, offsetReg := range []asm.Register{arm64.RegR8, arm64.RegR18} {
 							n := &arm64.NodeImpl{Types: arm64.OperandTypesRegisterToMemory,
 								Instruction: tc.inst, SrcReg: srcReg, DstReg: baseReg, DstReg2: offsetReg}
 							t.Run(n.String(), func(t *testing.T) {
@@ -937,7 +937,7 @@ func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) {
 								expected, err := goasm.Assemble()
 								require.NoError(t, err)
 
-								a := arm64.NewAssemblerImpl(arm64.REG_R27)
+								a := arm64.NewAssemblerImpl(arm64.RegR27)
 								err = a.EncodeRegisterToMemory(n)
 								require.NoError(t, err)
 								actual := a.Bytes()
@@ -979,12 +979,12 @@ func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) {
 		1<<12<<8 - 8,
 	}
 	intRegs := []asm.Register{
-		arm64.REG_R0, arm64.REG_R16,
-		arm64.REG_R30,
+		arm64.RegR0, arm64.RegR16,
+		arm64.RegR30,
 	}
 	floatRegs := []asm.Register{
-		arm64.REG_V0, arm64.REG_V10,
-		arm64.REG_V30,
+		arm64.RegV0, arm64.RegV10,
+		arm64.RegV30,
 	}
 	tests := []struct {
 		inst    asm.Instruction
@@ -1013,7 +1013,7 @@ func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) {
 								Instruction: tc.inst, SrcReg: baseReg, SrcConst: offset, DstReg: dstReg}
 							t.Run(n.String(), func(t *testing.T) {
 								goasm := newGoasmAssembler(t, asm.NilRegister)
-								a := arm64.NewAssemblerImpl(arm64.REG_R27)
+								a := arm64.NewAssemblerImpl(arm64.RegR27)
 
 								for _, assembler := range []arm64.Assembler{goasm, a} {
 									assembler.CompileMemoryToRegister(n.Instruction, n.SrcReg, n.SrcConst, n.DstReg)
@@ -1030,7 +1030,7 @@ func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) {
 						}
 					})
 					t.Run("register offset", func(t *testing.T) {
-						for _, offsetReg := range []asm.Register{arm64.REG_R8, arm64.REG_R18} {
+						for _, offsetReg := range []asm.Register{arm64.RegR8, arm64.RegR18} {
 							n := &arm64.NodeImpl{Types: arm64.OperandTypesMemoryToRegister,
 								Instruction: tc.inst, SrcReg: baseReg, SrcReg2: offsetReg, DstReg: dstReg}
 							t.Run(n.String(), func(t *testing.T) {
@@ -1039,7 +1039,7 @@ func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) {
 								expected, err := goasm.Assemble()
 								require.NoError(t, err)
 
-								a := arm64.NewAssemblerImpl(arm64.REG_R27)
+								a := arm64.NewAssemblerImpl(arm64.RegR27)
 								err = a.EncodeMemoryToRegister(n)
 								require.NoError(t, err)
 								actual := a.Bytes()
@@ -1056,7 +1056,7 @@ func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) {
 func TestAssemblerImpl_encodeReadInstructionAddress(t *testing.T) {
 	t.Run("ok", func(t *testing.T) {
 		const targetBeforeInstruction = arm64.RET
-		for _, dstReg := range []asm.Register{arm64.REG_R19, arm64.REG_R23} {
+		for _, dstReg := range []asm.Register{arm64.RegR19, arm64.RegR23} {
 			dstReg := dstReg
 			t.Run(arm64.RegisterName(dstReg), func(t *testing.T) {
 				goasm := newGoasmAssembler(t, asm.NilRegister)
@@ -1064,9 +1064,9 @@ func TestAssemblerImpl_encodeReadInstructionAddress(t *testing.T) {
 
 				for _, assembler := range []arm64.Assembler{a, goasm} {
 					assembler.CompileReadInstructionAddress(dstReg, targetBeforeInstruction)
-					assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.REG_R10) // Dummy
-					assembler.CompileJumpToRegister(targetBeforeInstruction, arm64.REG_R25)
-					assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.REG_R10) // Target.
+					assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.RegR10) // Dummy
+					assembler.CompileJumpToRegister(targetBeforeInstruction, arm64.RegR25)
+					assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.RegR10) // Target.
 				}
 
 				actual, err := a.Assemble()
@@ -1079,16 +1079,16 @@ func TestAssemblerImpl_encodeReadInstructionAddress(t *testing.T) {
 	})
 	t.Run("not found", func(t *testing.T) {
 		a := arm64.NewAssemblerImpl(asm.NilRegister)
-		a.CompileReadInstructionAddress(arm64.REG_R27, arm64.NOP)
-		a.CompileConstToRegister(arm64.MOVD, 1000, arm64.REG_R10)
+		a.CompileReadInstructionAddress(arm64.RegR27, arm64.NOP)
+		a.CompileConstToRegister(arm64.MOVD, 1000, arm64.RegR10)
 		_, err := a.Assemble()
 		require.EqualError(t, err, "BUG: target instruction NOP not found for ADR")
 	})
 	t.Run("offset too large", func(t *testing.T) {
 		a := arm64.NewAssemblerImpl(asm.NilRegister)
-		a.CompileReadInstructionAddress(arm64.REG_R27, arm64.RET)
-		a.CompileJumpToRegister(arm64.RET, arm64.REG_R25)
-		a.CompileConstToRegister(arm64.MOVD, 1000, arm64.REG_R10)
+		a.CompileReadInstructionAddress(arm64.RegR27, arm64.RET)
+		a.CompileJumpToRegister(arm64.RET, arm64.RegR25)
+		a.CompileConstToRegister(arm64.MOVD, 1000, arm64.RegR10)
 
 		for n := a.Root; n != nil; n = n.Next {
 			n.OffsetInBinaryField = uint64(a.Buf.Len())
@@ -1174,15 +1174,15 @@ func TestAssemblerImpl_EncodeRelativeJump(t *testing.T) {
 
 					for _, assembler := range []arm64.Assembler{a, goasm} {
 						for i := 0; i < tc.instructionsInPreamble; i++ {
-							assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.REG_R10)
+							assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.RegR10)
 						}
 						backwardTarget := assembler.CompileStandAlone(arm64.NOP)
 						for i := 0; i < tc.instructionsBeforeBranch; i++ {
-							assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.REG_R10)
+							assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.RegR10)
 						}
 						br := assembler.CompileJump(inst)
 						for i := 0; i < tc.instructionsAfterBranch; i++ {
-							assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.REG_R10)
+							assembler.CompileConstToRegister(arm64.MOVD, 1000, arm64.RegR10)
 						}
 						fowardTarget := assembler.CompileStandAlone(arm64.NOP)
 
@@ -1208,14 +1208,14 @@ func TestAssemblerImpl_EncodeRelativeJump(t *testing.T) {
 // the one of Go's assembler.
 func TestAssemblerImpl_multipleLargeOffest(t *testing.T) {
 	goasm := newGoasmAssembler(t, asm.NilRegister)
-	a := arm64.NewAssemblerImpl(arm64.REG_R27)
+	a := arm64.NewAssemblerImpl(arm64.RegR27)
 
 	for _, assembler := range []arm64.Assembler{a, goasm} {
 		for i := 0; i < 10000; i++ {
 			// This will be put into const pool, but the callback won't be set for it.
-			assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REG_R11, arm64.REG_R12, 0xfff0+int64(i*8))
+			assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegR11, arm64.RegR12, 0xfff0+int64(i*8))
 			// This will also set the call back for it.
-			assembler.CompileRegisterToMemory(arm64.MOVD, arm64.REG_R11, arm64.REG_R12, (0xfff0+int64(i*8)<<16+8)%(1<<31))
+			assembler.CompileRegisterToMemory(arm64.MOVD, arm64.RegR11, arm64.RegR12, (0xfff0+int64(i*8)<<16+8)%(1<<31))
 		}
 	}
 
@@ -1247,7 +1247,7 @@ func TestAssemblerImpl_EncodeTwoSIMDBytesToSIMDByteRegister(t *testing.T) {
 	})
 
 	for _, inst := range []asm.Instruction{arm64.VBIT} {
-		regs := []asm.Register{arm64.REG_V0, arm64.REG_V10, arm64.REG_V30}
+		regs := []asm.Register{arm64.RegV0, arm64.RegV10, arm64.RegV30}
 		for _, src1 := range regs {
 			for _, src2 := range regs {
 				for _, dst := range regs {
@@ -1259,7 +1259,7 @@ func TestAssemblerImpl_EncodeTwoSIMDBytesToSIMDByteRegister(t *testing.T) {
 						expected, err := goasm.Assemble()
 						require.NoError(t, err)
 
-						a := arm64.NewAssemblerImpl(arm64.REG_R27)
+						a := arm64.NewAssemblerImpl(arm64.RegR27)
 						err = a.EncodeTwoSIMDBytesToSIMDByteRegister(n)
 						require.NoError(t, err)
 						actual := a.Bytes()
@@ -1279,32 +1279,32 @@ func TestAssemblerImpl_EncodeVectorRegisterToVectorRegister(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.B,
-					SrcReg: arm64.REG_V21,
-					DstReg: arm64.REG_V21,
+					SrcReg: arm64.RegV21,
+					DstReg: arm64.RegV21,
 					Types:  arm64.OperandTypesVectorRegisterToVectorRegister,
 				},
 				expErr: "B is unsupported for from:vector-register,to:vector-register type",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.VMOV,
-					SrcReg: arm64.REG_V21,
-					DstReg: arm64.REG_V21,
+					SrcReg: arm64.RegV21,
+					DstReg: arm64.RegV21,
 					Types:  arm64.OperandTypesVectorRegisterToVectorRegister,
 				},
 				expErr: "unsupported arrangement for VMOV: unknown",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.VADD,
-					SrcReg: arm64.REG_V21,
-					DstReg: arm64.REG_V21,
+					SrcReg: arm64.RegV21,
+					DstReg: arm64.RegV21,
 					Types:  arm64.OperandTypesVectorRegisterToVectorRegister,
 				},
 				expErr: "unsupported arrangement for VADD: unknown",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.VADD,
-					SrcReg:            arm64.REG_V21,
-					DstReg:            arm64.REG_V21,
+					SrcReg:            arm64.RegV21,
+					DstReg:            arm64.RegV21,
 					Types:             arm64.OperandTypesVectorRegisterToVectorRegister,
 					VectorArrangement: arm64.VectorArrangement1D,
 				},
@@ -1320,7 +1320,7 @@ func TestAssemblerImpl_EncodeVectorRegisterToVectorRegister(t *testing.T) {
 		}
 	})
 
-	vectorRegs := []asm.Register{arm64.REG_V10, arm64.REG_V2, arm64.REG_V30}
+	vectorRegs := []asm.Register{arm64.RegV10, arm64.RegV2, arm64.RegV30}
 	tests := []struct {
 		inst asm.Instruction
 		arr  arm64.VectorArrangement
@@ -1368,16 +1368,16 @@ func TestAssemblerImpl_EncodeMemoryToVectorRegister(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.B,
-					SrcReg: arm64.REG_R1,
-					DstReg: arm64.REG_V21,
+					SrcReg: arm64.RegR1,
+					DstReg: arm64.RegV21,
 					Types:  arm64.OperandTypesMemoryToVectorRegister,
 				},
 				expErr: "B is unsupported for from:memory,to:vector-register type",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.VLD1,
-					SrcReg: arm64.REG_R1,
-					DstReg: arm64.REG_V21,
+					SrcReg: arm64.RegR1,
+					DstReg: arm64.RegV21,
 					Types:  arm64.OperandTypesMemoryToVectorRegister,
 				},
 				expErr: "unsupported arrangement for VLD1: unknown",
@@ -1392,8 +1392,8 @@ func TestAssemblerImpl_EncodeMemoryToVectorRegister(t *testing.T) {
 		}
 	})
 
-	regs := []asm.Register{arm64.REG_R0, arm64.REG_R5, arm64.REG_R30}
-	vectorRegs := []asm.Register{arm64.REG_V10, arm64.REG_V2}
+	regs := []asm.Register{arm64.RegR0, arm64.RegR5, arm64.RegR30}
+	vectorRegs := []asm.Register{arm64.RegV10, arm64.RegV2}
 	arrangements := []arm64.VectorArrangement{
 		arm64.VectorArrangement8B,
 		arm64.VectorArrangement16B,
@@ -1443,16 +1443,16 @@ func TestAssemblerImpl_EncodeVectorRegisterToMemory(t *testing.T) {
 		}{
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.B,
-					SrcReg: arm64.REG_V21,
-					DstReg: arm64.REG_R1,
+					SrcReg: arm64.RegV21,
+					DstReg: arm64.RegR1,
 					Types:  arm64.OperandTypesVectorRegisterToMemory,
 				},
 				expErr: "B is unsupported for from:vector-register,to:memory type",
 			},
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.VST1,
-					SrcReg: arm64.REG_V21,
-					DstReg: arm64.REG_R1,
+					SrcReg: arm64.RegV21,
+					DstReg: arm64.RegR1,
 					Types:  arm64.OperandTypesVectorRegisterToMemory,
 				},
 				expErr: "unsupported arrangement for VST1: unknown",
@@ -1467,8 +1467,8 @@ func TestAssemblerImpl_EncodeVectorRegisterToMemory(t *testing.T) {
 		}
 	})
 
-	regs := []asm.Register{arm64.REG_R0, arm64.REG_R5, arm64.REG_R30}
-	vectorRegs := []asm.Register{arm64.REG_V10, arm64.REG_V2}
+	regs := []asm.Register{arm64.RegR0, arm64.RegR5, arm64.RegR30}
+	vectorRegs := []asm.Register{arm64.RegV10, arm64.RegV2}
 	arrangements := []arm64.VectorArrangement{
 		arm64.VectorArrangement8B,
 		arm64.VectorArrangement16B,
@@ -1531,8 +1531,8 @@ func TestAssemblerImpl_EncodeRegisterToVectorRegister(t *testing.T) {
 			{
 				n: &arm64.NodeImpl{Instruction: arm64.VMOV,
 					Types:       arm64.OperandTypesRegisterToVectorRegister,
-					SrcReg:      arm64.REG_R0,
-					DstReg:      arm64.REG_V3,
+					SrcReg:      arm64.RegR0,
+					DstReg:      arm64.RegV3,
 					VectorIndex: 0, VectorArrangement: arm64.VectorArrangement1D,
 				},
 				expErr: "unsupported arrangement for VMOV: 1D",
@@ -1547,8 +1547,8 @@ func TestAssemblerImpl_EncodeRegisterToVectorRegister(t *testing.T) {
 		}
 	})
 
-	regs := []asm.Register{arm64.REG_R0, arm64.REG_R10, arm64.REG_R30}
-	vectorRegs := []asm.Register{arm64.REG_V0, arm64.REG_V10, arm64.REG_V30}
+	regs := []asm.Register{arm64.RegR0, arm64.RegR10, arm64.RegR30}
+	vectorRegs := []asm.Register{arm64.RegV0, arm64.RegV10, arm64.RegV30}
 
 	tests := []struct {
 		inst        asm.Instruction
@@ -1617,38 +1617,38 @@ func TestAssemblerImpl_EncodeRegisterToVectorRegister(t *testing.T) {
 
 func conditionalRegisterToState(r asm.Register) asm.ConditionalRegisterState {
 	switch r {
-	case arm64.REG_COND_EQ:
-		return arm64.COND_EQ
-	case arm64.REG_COND_NE:
-		return arm64.COND_NE
-	case arm64.REG_COND_HS:
-		return arm64.COND_HS
-	case arm64.REG_COND_LO:
-		return arm64.COND_LO
-	case arm64.REG_COND_MI:
-		return arm64.COND_MI
-	case arm64.REG_COND_PL:
-		return arm64.COND_PL
-	case arm64.REG_COND_VS:
-		return arm64.COND_VS
-	case arm64.REG_COND_VC:
-		return arm64.COND_VC
-	case arm64.REG_COND_HI:
-		return arm64.COND_HI
-	case arm64.REG_COND_LS:
-		return arm64.COND_LS
-	case arm64.REG_COND_GE:
-		return arm64.COND_GE
-	case arm64.REG_COND_LT:
-		return arm64.COND_LT
-	case arm64.REG_COND_GT:
-		return arm64.COND_GT
-	case arm64.REG_COND_LE:
-		return arm64.COND_LE
-	case arm64.REG_COND_AL:
-		return arm64.COND_AL
-	case arm64.REG_COND_NV:
-		return arm64.COND_NV
+	case arm64.RegCondEQ:
+		return arm64.CondEQ
+	case arm64.RegCondNE:
+		return arm64.CondNE
+	case arm64.RegCondHS:
+		return arm64.CondHS
+	case arm64.RegCondLO:
+		return arm64.CondLO
+	case arm64.RegCondMI:
+		return arm64.CondMI
+	case arm64.RegCondPL:
+		return arm64.CondPL
+	case arm64.RegCondVS:
+		return arm64.CondVS
+	case arm64.RegCondVC:
+		return arm64.CondVC
+	case arm64.RegCondHI:
+		return arm64.CondHI
+	case arm64.RegCondLS:
+		return arm64.CondLS
+	case arm64.RegCondGE:
+		return arm64.CondGE
+	case arm64.RegCondLT:
+		return arm64.CondLT
+	case arm64.RegCondGT:
+		return arm64.CondGT
+	case arm64.RegCondLE:
+		return arm64.CondLE
+	case arm64.RegCondAL:
+		return arm64.CondAL
+	case arm64.RegCondNV:
+		return arm64.CondNV
 	}
 	return asm.ConditionalRegisterStateUnset
 }