Repository: tetratelabs/wazero
Pull request #2054 (2024-02-13 18:56:50)

wazevo(amd64): passes simd_conversions


Patch:
diff --git a/internal/engine/wazevo/backend/isa/amd64/instr.go b/internal/engine/wazevo/backend/isa/amd64/instr.go
index 6b8c29f4..3ce12455 100644
--- a/internal/engine/wazevo/backend/isa/amd64/instr.go
+++ b/internal/engine/wazevo/backend/isa/amd64/instr.go
@@ -1429,6 +1429,7 @@ const (
 	sseOpcodeCmpss
 	sseOpcodeCmpsd
 	sseOpcodeCvtdq2ps
+	sseOpcodeCvtdq2pd
 	sseOpcodeCvtsd2ss
 	sseOpcodeCvtsd2si
 	sseOpcodeCvtsi2ss
@@ -1577,6 +1578,9 @@ const (
 	sseOpcodeXorps
 	sseOpcodeXorpd
 	sseOpcodePmulhrsw
+	sseOpcodeUnpcklps
+	sseOpcodeCvtps2pd
+	sseOpcodeCvtpd2ps
 )
 
 func (s sseOpcode) String() string {
@@ -1617,6 +1621,8 @@ func (s sseOpcode) String() string {
 		return "cmpsd"
 	case sseOpcodeCvtdq2ps:
 		return "cvtdq2ps"
+	case sseOpcodeCvtdq2pd:
+		return "cvtdq2pd"
 	case sseOpcodeCvtsd2ss:
 		return "cvtsd2ss"
 	case sseOpcodeCvtsd2si:
@@ -1913,6 +1919,12 @@ func (s sseOpcode) String() string {
 		return "xorpd"
 	case sseOpcodePmulhrsw:
 		return "pmulhrsw"
+	case sseOpcodeUnpcklps:
+		return "unpcklps"
+	case sseOpcodeCvtps2pd:
+		return "cvtps2pd"
+	case sseOpcodeCvtpd2ps:
+		return "cvtpd2ps"
 	default:
 		panic("BUG")
 	}
diff --git a/internal/engine/wazevo/backend/isa/amd64/instr_encoding.go b/internal/engine/wazevo/backend/isa/amd64/instr_encoding.go
index 820acfe7..d097b6ac 100644
--- a/internal/engine/wazevo/backend/isa/amd64/instr_encoding.go
+++ b/internal/engine/wazevo/backend/isa/amd64/instr_encoding.go
@@ -163,8 +163,6 @@ func (i *instruction) encode(c backend.Compiler) (needsLabelResolution bool) {
 			legPrex, opcode, opcodeNum = legacyPrefixes0x66, 0x0F3815, 3
 		case sseOpcodeCvttps2dq:
 			legPrex, opcode, opcodeNum = legacyPrefixes0xF3, 0x0F5B, 2
-		case sseOpcodeCvtdq2ps:
-			legPrex, opcode, opcodeNum = legacyPrefixesNone, 0x0F5B, 2
 		case sseOpcodeDivps:
 			legPrex, opcode, opcodeNum = legacyPrefixesNone, 0x0F5E, 2
 		case sseOpcodeDivpd:
@@ -325,6 +323,8 @@ func (i *instruction) encode(c backend.Compiler) (needsLabelResolution bool) {
 			legPrex, opcode, opcodeNum = legacyPrefixes0x66, 0x0F57, 2
 		case sseOpcodePmulhrsw:
 			legPrex, opcode, opcodeNum = legacyPrefixes0x66, 0x0F380B, 3
+		case sseOpcodeUnpcklps:
+			legPrex, opcode, opcodeNum = legacyPrefixesNone, 0x0F14, 2
 		default:
 			panic(fmt.Sprintf("Unsupported sseOpcode: %s", op))
 		}
@@ -445,6 +445,14 @@ func (i *instruction) encode(c backend.Compiler) (needsLabelResolution bool) {
 			prefix, opcode, opcodeNum = legacyPrefixesNone, 0x0F57, 2
 		case sseOpcodeXorpd:
 			prefix, opcode, opcodeNum = legacyPrefixes0x66, 0x0F57, 2
+		case sseOpcodeCvtdq2ps:
+			prefix, opcode, opcodeNum = legacyPrefixesNone, 0x0F5B, 2
+		case sseOpcodeCvtdq2pd:
+			prefix, opcode, opcodeNum = legacyPrefixes0xF3, 0x0FE6, 2
+		case sseOpcodeCvtps2pd:
+			prefix, opcode, opcodeNum = legacyPrefixesNone, 0x0F5A, 2
+		case sseOpcodeCvtpd2ps:
+			prefix, opcode, opcodeNum = legacyPrefixes0x66, 0x0F5A, 2
 		default:
 			panic(fmt.Sprintf("Unsupported sseOpcode: %s", op))
 		}
diff --git a/internal/engine/wazevo/backend/isa/amd64/machine.go b/internal/engine/wazevo/backend/isa/amd64/machine.go
index ba3fe6b5..54de4f10 100644
--- a/internal/engine/wazevo/backend/isa/amd64/machine.go
+++ b/internal/engine/wazevo/backend/isa/amd64/machine.go
@@ -23,15 +23,17 @@ func NewBackend() backend.Machine {
 		asNop,
 	)
 	return &machine{
-		ectx:                          ectx,
-		cpuFeatures:                   platform.CpuFeatures,
-		regAlloc:                      regalloc.NewAllocator(regInfo),
-		spillSlots:                    map[regalloc.VRegID]int64{},
-		amodePool:                     wazevoapi.NewPool[amode](nil),
-		swizzleMaskConstIndex:         -1,
-		sqmulRoundSatIndex:            -1,
-		i8x16SHLMaskTableIndex:        -1,
-		i8x16LogicalSHRMaskTableIndex: -1,
+		ectx:                               ectx,
+		cpuFeatures:                        platform.CpuFeatures,
+		regAlloc:                           regalloc.NewAllocator(regInfo),
+		spillSlots:                         map[regalloc.VRegID]int64{},
+		amodePool:                          wazevoapi.NewPool[amode](nil),
+		constSwizzleMaskConstIndex:         -1,
+		constSqmulRoundSatIndex:            -1,
+		constI8x16SHLMaskTableIndex:        -1,
+		constI8x16LogicalSHRMaskTableIndex: -1,
+		constF64x2CvtFromIMaskIndex:        -1,
+		constTwop52Index:                   -1,
 	}
 }
 
@@ -62,8 +64,9 @@ type (
 		jmpTableTargets [][]uint32
 		consts          []_const
 
-		swizzleMaskConstIndex, sqmulRoundSatIndex,
-		i8x16SHLMaskTableIndex, i8x16LogicalSHRMaskTableIndex int
+		constSwizzleMaskConstIndex, constSqmulRoundSatIndex,
+		constI8x16SHLMaskTableIndex, constI8x16LogicalSHRMaskTableIndex,
+		constF64x2CvtFromIMaskIndex, constTwop52Index int
 	}
 
 	_const struct {
@@ -82,6 +85,20 @@ type (
 	labelPosition = backend.LabelPosition[instruction]
 )
 
+func (m *machine) getOrAllocateConstLabel(i *int, _var []byte) backend.Label {
+	index := *i
+	if index == -1 {
+		label := m.allocateLabel()
+		index = len(m.consts)
+		m.consts = append(m.consts, _const{
+			_var:  _var,
+			label: label,
+		})
+		*i = index
+	}
+	return m.consts[index].label.L
+}
+
 // Reset implements backend.Machine.
 func (m *machine) Reset() {
 	m.consts = m.consts[:0]
@@ -106,10 +123,12 @@ func (m *machine) Reset() {
 
 	m.amodePool.Reset()
 	m.jmpTableTargets = m.jmpTableTargets[:0]
-	m.swizzleMaskConstIndex = -1
-	m.sqmulRoundSatIndex = -1
-	m.i8x16SHLMaskTableIndex = -1
-	m.i8x16LogicalSHRMaskTableIndex = -1
+	m.constSwizzleMaskConstIndex = -1
+	m.constSqmulRoundSatIndex = -1
+	m.constI8x16SHLMaskTableIndex = -1
+	m.constI8x16LogicalSHRMaskTableIndex = -1
+	m.constF64x2CvtFromIMaskIndex = -1
+	m.constTwop52Index = -1
 }
 
 // ExecutableContext implements backend.Machine.
@@ -819,6 +838,30 @@ func (m *machine) LowerInstr(instr *ssa.Instruction) {
 		ptr, offset, lane := instr.LoadSplatData()
 		m.lowerLoadSplat(ptr, offset, instr.Return(), lane)
 
+	case ssa.OpcodeVFcvtFromUint, ssa.OpcodeVFcvtFromSint:
+		x, lane := instr.ArgWithLane()
+		m.lowerVFcvtFromInt(x, instr.Return(), lane, op == ssa.OpcodeVFcvtFromSint)
+
+	case ssa.OpcodeVFcvtToSintSat, ssa.OpcodeVFcvtToUintSat:
+		x, lane := instr.ArgWithLane()
+		m.lowerVFcvtToIntSat(x, instr.Return(), lane, op == ssa.OpcodeVFcvtToSintSat)
+
+	case ssa.OpcodeSnarrow, ssa.OpcodeUnarrow:
+		x, y, lane := instr.Arg2WithLane()
+		m.lowerNarrow(x, y, instr.Return(), lane, op == ssa.OpcodeSnarrow)
+
+	case ssa.OpcodeFvpromoteLow:
+		x := instr.Arg()
+		src := m.getOperand_Mem_Reg(m.c.ValueDefinition(x))
+		dst := m.c.VRegOf(instr.Return())
+		m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeCvtps2pd, src, dst))
+
+	case ssa.OpcodeFvdemote:
+		x := instr.Arg()
+		src := m.getOperand_Mem_Reg(m.c.ValueDefinition(x))
+		dst := m.c.VRegOf(instr.Return())
+		m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeCvtpd2ps, src, dst))
+
 	case ssa.OpcodeVIabs:
 		m.lowerVIabs(instr)
 	case ssa.OpcodeVIpopcnt:
@@ -2987,34 +3030,6 @@ func (m *machine) lowerVbnot(instr *ssa.Instruction) {
 	m.copyTo(tmp, rd)
 }
 
-var sqmulRoundSat = [16]byte{
-	0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
-	0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
-}
-
-func (m *machine) lowerSqmulRoundSat(x, y, ret ssa.Value) {
-	// See https://github.com/WebAssembly/simd/pull/365 for the following logic.
-	maskIndex := m.sqmulRoundSatIndex
-	if maskIndex < 0 {
-		maskIndex = len(m.consts)
-		m.consts = append(m.consts, _const{_var: sqmulRoundSat[:], label: m.allocateLabel()})
-		m.sqmulRoundSatIndex = maskIndex
-	}
-
-	tmp := m.c.AllocateVReg(ssa.TypeV128)
-	loadMask := m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, newOperandMem(m.newAmodeRipRel(m.consts[maskIndex].label.L)), tmp)
-	m.insert(loadMask)
-
-	xx, yy := m.getOperand_Reg(m.c.ValueDefinition(x)), m.getOperand_Mem_Reg(m.c.ValueDefinition(y))
-	tmpX := m.copyToTmp(xx.reg())
-
-	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePmulhrsw, yy, tmpX))
-	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePcmpeqd, newOperandReg(tmpX), tmp))
-	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePxor, newOperandReg(tmp), tmpX))
-
-	m.copyTo(tmpX, m.c.VRegOf(ret))
-}
-
 func (m *machine) lowerSplat(x, ret ssa.Value, lane ssa.VecLane) {
 	tmpDst := m.c.AllocateVReg(ssa.TypeV128)
 	m.insert(m.allocateInstr().asDefineUninitializedReg(tmpDst))
@@ -3101,118 +3116,6 @@ func (m *machine) lowerShuffle(x, y ssa.Value, lo, hi uint64, ret ssa.Value) {
 	m.copyTo(tmpY, m.c.VRegOf(ret))
 }
 
-var swizzleMask = [16]byte{
-	0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
-	0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
-}
-
-func (m *machine) lowerSwizzle(x, y ssa.Value, ret ssa.Value) {
-	maskIndex := m.swizzleMaskConstIndex
-	if maskIndex < 0 {
-		label := m.allocateLabel()
-		maskIndex = len(m.consts)
-		m.consts = append(m.consts, _const{
-			_var:  swizzleMask[:],
-			label: label,
-		})
-	}
-	masklabel := m.consts[maskIndex].label
-
-	// Load mask to maskReg.
-	maskReg := m.c.AllocateVReg(ssa.TypeV128)
-	loadMask := m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, newOperandMem(m.newAmodeRipRel(masklabel.L)), maskReg)
-	m.insert(loadMask)
-
-	// Copy x and y to tmp registers.
-	xx := m.getOperand_Reg(m.c.ValueDefinition(x))
-	tmpDst := m.copyToTmp(xx.reg())
-	yy := m.getOperand_Reg(m.c.ValueDefinition(y))
-	tmpX := m.copyToTmp(yy.reg())
-
-	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePaddusb, newOperandReg(maskReg), tmpX))
-	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePshufb, newOperandReg(tmpX), tmpDst))
-
-	// Copy the result to the destination register.
-	m.copyTo(tmpDst, m.c.VRegOf(ret))
-}
-
-func (m *machine) lowerInsertLane(x, y ssa.Value, index byte, ret ssa.Value, lane ssa.VecLane) {
-	// Copy x to tmp.
-	tmpDst := m.c.AllocateVReg(ssa.TypeV128)
-	m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, m.getOperand_Mem_Reg(m.c.ValueDefinition(x)), tmpDst))
-
-	yy := m.getOperand_Reg(m.c.ValueDefinition(y))
-	switch lane {
-	case ssa.VecLaneI8x16:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrb, index, yy, tmpDst))
-	case ssa.VecLaneI16x8:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrw, index, yy, tmpDst))
-	case ssa.VecLaneI32x4:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrd, index, yy, tmpDst))
-	case ssa.VecLaneI64x2:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrq, index, yy, tmpDst))
-	case ssa.VecLaneF32x4:
-		// In INSERTPS instruction, the destination index is encoded at 4 and 5 bits of the argument.
-		// See https://www.felixcloutier.com/x86/insertps
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodeInsertps, index<<4, yy, tmpDst))
-	case ssa.VecLaneF64x2:
-		if index == 0 {
-			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovsd, yy, tmpDst))
-		} else {
-			m.insert(m.allocateInstr().asXmmRmR(sseOpcodeMovlhps, yy, tmpDst))
-		}
-	default:
-		panic(fmt.Sprintf("invalid lane type: %s", lane))
-	}
-
-	m.copyTo(tmpDst, m.c.VRegOf(ret))
-}
-
-func (m *machine) lowerExtractLane(x ssa.Value, index byte, signed bool, ret ssa.Value, lane ssa.VecLane) {
-	// Pextr variants are used to extract a lane from a vector register.
-	xx := m.getOperand_Reg(m.c.ValueDefinition(x))
-
-	tmpDst := m.c.AllocateVReg(ret.Type())
-	m.insert(m.allocateInstr().asDefineUninitializedReg(tmpDst))
-	switch lane {
-	case ssa.VecLaneI8x16:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrb, index, xx, tmpDst))
-		if signed {
-			m.insert(m.allocateInstr().asMovsxRmR(extModeBL, newOperandReg(tmpDst), tmpDst))
-		} else {
-			m.insert(m.allocateInstr().asMovzxRmR(extModeBL, newOperandReg(tmpDst), tmpDst))
-		}
-	case ssa.VecLaneI16x8:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrw, index, xx, tmpDst))
-		if signed {
-			m.insert(m.allocateInstr().asMovsxRmR(extModeWL, newOperandReg(tmpDst), tmpDst))
-		} else {
-			m.insert(m.allocateInstr().asMovzxRmR(extModeWL, newOperandReg(tmpDst), tmpDst))
-		}
-	case ssa.VecLaneI32x4:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrd, index, xx, tmpDst))
-	case ssa.VecLaneI64x2:
-		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrq, index, xx, tmpDst))
-	case ssa.VecLaneF32x4:
-		if index == 0 {
-			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovss, xx, tmpDst))
-		} else {
-			m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePshufd, index, xx, tmpDst))
-		}
-	case ssa.VecLaneF64x2:
-		if index == 0 {
-			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovsd, xx, tmpDst))
-		} else {
-			m.copyTo(xx.reg(), tmpDst)
-			m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePshufd, 0b00_00_11_10, newOperandReg(tmpDst), tmpDst))
-		}
-	default:
-		panic(fmt.Sprintf("invalid lane type: %s", lane))
-	}
-
-	m.copyTo(tmpDst, m.c.VRegOf(ret))
-}
-
 func (m *machine) lowerVbBinOp(op sseOpcode, x, y, ret ssa.Value) {
 	rn := m.getOperand_Reg(m.c.ValueDefinition(x))
 	rm := m.getOperand_Mem_Reg(m.c.ValueDefinition(y))
diff --git a/internal/engine/wazevo/backend/isa/amd64/machine_vec.go b/internal/engine/wazevo/backend/isa/amd64/machine_vec.go
index 8beb0a08..501ce9e6 100644
--- a/internal/engine/wazevo/backend/isa/amd64/machine_vec.go
+++ b/internal/engine/wazevo/backend/isa/amd64/machine_vec.go
@@ -6,6 +6,132 @@ import (
 	"github.com/tetratelabs/wazero/internal/engine/wazevo/ssa"
 )
 
+var swizzleMask = [16]byte{
+	0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
+	0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
+}
+
+func (m *machine) lowerSwizzle(x, y ssa.Value, ret ssa.Value) {
+	masklabel := m.getOrAllocateConstLabel(&m.constSwizzleMaskConstIndex, swizzleMask[:])
+
+	// Load mask to maskReg.
+	maskReg := m.c.AllocateVReg(ssa.TypeV128)
+	loadMask := m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, newOperandMem(m.newAmodeRipRel(masklabel)), maskReg)
+	m.insert(loadMask)
+
+	// Copy x and y to tmp registers.
+	xx := m.getOperand_Reg(m.c.ValueDefinition(x))
+	tmpDst := m.copyToTmp(xx.reg())
+	yy := m.getOperand_Reg(m.c.ValueDefinition(y))
+	tmpX := m.copyToTmp(yy.reg())
+
+	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePaddusb, newOperandReg(maskReg), tmpX))
+	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePshufb, newOperandReg(tmpX), tmpDst))
+
+	// Copy the result to the destination register.
+	m.copyTo(tmpDst, m.c.VRegOf(ret))
+}
+
+func (m *machine) lowerInsertLane(x, y ssa.Value, index byte, ret ssa.Value, lane ssa.VecLane) {
+	// Copy x to tmp.
+	tmpDst := m.c.AllocateVReg(ssa.TypeV128)
+	m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, m.getOperand_Mem_Reg(m.c.ValueDefinition(x)), tmpDst))
+
+	yy := m.getOperand_Reg(m.c.ValueDefinition(y))
+	switch lane {
+	case ssa.VecLaneI8x16:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrb, index, yy, tmpDst))
+	case ssa.VecLaneI16x8:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrw, index, yy, tmpDst))
+	case ssa.VecLaneI32x4:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrd, index, yy, tmpDst))
+	case ssa.VecLaneI64x2:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePinsrq, index, yy, tmpDst))
+	case ssa.VecLaneF32x4:
+		// In INSERTPS instruction, the destination index is encoded at 4 and 5 bits of the argument.
+		// See https://www.felixcloutier.com/x86/insertps
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodeInsertps, index<<4, yy, tmpDst))
+	case ssa.VecLaneF64x2:
+		if index == 0 {
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovsd, yy, tmpDst))
+		} else {
+			m.insert(m.allocateInstr().asXmmRmR(sseOpcodeMovlhps, yy, tmpDst))
+		}
+	default:
+		panic(fmt.Sprintf("invalid lane type: %s", lane))
+	}
+
+	m.copyTo(tmpDst, m.c.VRegOf(ret))
+}
+
+func (m *machine) lowerExtractLane(x ssa.Value, index byte, signed bool, ret ssa.Value, lane ssa.VecLane) {
+	// Pextr variants are used to extract a lane from a vector register.
+	xx := m.getOperand_Reg(m.c.ValueDefinition(x))
+
+	tmpDst := m.c.AllocateVReg(ret.Type())
+	m.insert(m.allocateInstr().asDefineUninitializedReg(tmpDst))
+	switch lane {
+	case ssa.VecLaneI8x16:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrb, index, xx, tmpDst))
+		if signed {
+			m.insert(m.allocateInstr().asMovsxRmR(extModeBL, newOperandReg(tmpDst), tmpDst))
+		} else {
+			m.insert(m.allocateInstr().asMovzxRmR(extModeBL, newOperandReg(tmpDst), tmpDst))
+		}
+	case ssa.VecLaneI16x8:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrw, index, xx, tmpDst))
+		if signed {
+			m.insert(m.allocateInstr().asMovsxRmR(extModeWL, newOperandReg(tmpDst), tmpDst))
+		} else {
+			m.insert(m.allocateInstr().asMovzxRmR(extModeWL, newOperandReg(tmpDst), tmpDst))
+		}
+	case ssa.VecLaneI32x4:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrd, index, xx, tmpDst))
+	case ssa.VecLaneI64x2:
+		m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePextrq, index, xx, tmpDst))
+	case ssa.VecLaneF32x4:
+		if index == 0 {
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovss, xx, tmpDst))
+		} else {
+			m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePshufd, index, xx, tmpDst))
+		}
+	case ssa.VecLaneF64x2:
+		if index == 0 {
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovsd, xx, tmpDst))
+		} else {
+			m.copyTo(xx.reg(), tmpDst)
+			m.insert(m.allocateInstr().asXmmRmRImm(sseOpcodePshufd, 0b00_00_11_10, newOperandReg(tmpDst), tmpDst))
+		}
+	default:
+		panic(fmt.Sprintf("invalid lane type: %s", lane))
+	}
+
+	m.copyTo(tmpDst, m.c.VRegOf(ret))
+}
+
+var sqmulRoundSat = [16]byte{
+	0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
+	0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
+}
+
+func (m *machine) lowerSqmulRoundSat(x, y, ret ssa.Value) {
+	// See https://github.com/WebAssembly/simd/pull/365 for the following logic.
+	maskLabel := m.getOrAllocateConstLabel(&m.constSqmulRoundSatIndex, sqmulRoundSat[:])
+
+	tmp := m.c.AllocateVReg(ssa.TypeV128)
+	loadMask := m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, newOperandMem(m.newAmodeRipRel(maskLabel)), tmp)
+	m.insert(loadMask)
+
+	xx, yy := m.getOperand_Reg(m.c.ValueDefinition(x)), m.getOperand_Mem_Reg(m.c.ValueDefinition(y))
+	tmpX := m.copyToTmp(xx.reg())
+
+	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePmulhrsw, yy, tmpX))
+	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePcmpeqd, newOperandReg(tmpX), tmp))
+	m.insert(m.allocateInstr().asXmmRmR(sseOpcodePxor, newOperandReg(tmp), tmpX))
+
+	m.copyTo(tmpX, m.c.VRegOf(ret))
+}
+
 func (m *machine) lowerVUshr(x, y, ret ssa.Value, lane ssa.VecLane) {
 	switch lane {
 	case ssa.VecLaneI8x16:
@@ -45,19 +171,9 @@ func (m *machine) lowerVUshri8x16(x, y, ret ssa.Value) {
 	m.insert(m.allocateInstr().asGprToXmm(sseOpcodeMovd, newOperandReg(tmpGpReg), vecTmp, false))
 	m.insert(m.allocateInstr().asXmmRmiReg(sseOpcodePsrlw, newOperandReg(vecTmp), xx))
 
-	maskTableLabelIndex := m.i8x16LogicalSHRMaskTableIndex
-	if maskTableLabelIndex < 0 {
-		label := m.allocateLabel()
-		maskTableLabelIndex = len(m.consts)
-		m.consts = append(m.consts, _const{
-			_var:  i8x16LogicalSHRMaskTable[:],
-			label: label,
-		})
-		m.i8x16LogicalSHRMaskTableIndex = maskTableLabelIndex
-	}
-
+	maskTableLabel := m.getOrAllocateConstLabel(&m.constI8x16LogicalSHRMaskTableIndex, i8x16LogicalSHRMaskTable[:])
 	base := m.c.AllocateVReg(ssa.TypeI64)
-	lea := m.allocateInstr().asLEA(newOperandLabel(m.consts[maskTableLabelIndex].label.L), base)
+	lea := m.allocateInstr().asLEA(newOperandLabel(maskTableLabel), base)
 	m.insert(lea)
 
 	// Shift tmpGpReg by 4 to multiply the shift amount by 16.
@@ -233,19 +349,9 @@ func (m *machine) lowerVIshl(x, y, ret ssa.Value, lane ssa.VecLane) {
 	m.insert(m.allocateInstr().asXmmRmiReg(shiftOp, newOperandReg(tmpVec), xx))
 
 	if isI8x16 {
-		maskTableLabelIndex := m.i8x16SHLMaskTableIndex
-		if maskTableLabelIndex < 0 {
-			label := m.allocateLabel()
-			maskTableLabelIndex = len(m.consts)
-			m.consts = append(m.consts, _const{
-				_var:  i8x16SHLMaskTable[:],
-				label: label,
-			})
-			m.i8x16SHLMaskTableIndex = maskTableLabelIndex
-		}
-
+		maskTableLabel := m.getOrAllocateConstLabel(&m.constI8x16SHLMaskTableIndex, i8x16SHLMaskTable[:])
 		base := m.c.AllocateVReg(ssa.TypeI64)
-		lea := m.allocateInstr().asLEA(newOperandLabel(m.consts[maskTableLabelIndex].label.L), base)
+		lea := m.allocateInstr().asLEA(newOperandLabel(maskTableLabel), base)
 		m.insert(lea)
 
 		// Shift tmpGpReg by 4 to multiply the shift amount by 16.
@@ -402,3 +508,134 @@ func (m *machine) lowerLoadSplat(ptr ssa.Value, offset uint32, ret ssa.Value, la
 
 	m.copyTo(tmpDst, m.c.VRegOf(ret))
 }
+
+var f64x2CvtFromIMask = [16]byte{
+	0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+}
+
+func (m *machine) lowerVFcvtFromInt(x, ret ssa.Value, lane ssa.VecLane, signed bool) {
+	switch lane {
+	case ssa.VecLaneF32x4:
+		if signed {
+			xx := m.getOperand_Mem_Reg(m.c.ValueDefinition(x))
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeCvtdq2ps, xx, m.c.VRegOf(ret)))
+		} else {
+			xx := m.getOperand_Reg(m.c.ValueDefinition(x))
+			// Copy the value to two temporary registers.
+			tmp := m.copyToTmp(xx.reg())
+			tmp2 := m.copyToTmp(xx.reg())
+
+			// Clear the higher 16 bits of each 32-bit element.
+			m.insert(m.allocateInstr().asXmmRmiReg(sseOpcodePslld, newOperandImm32(0xa), tmp))
+			m.insert(m.allocateInstr().asXmmRmiReg(sseOpcodePsrld, newOperandImm32(0xa), tmp))
+
+			// Subtract the higher 16-bits from vr == clear the lower 16-bits of vr.
+			m.insert(m.allocateInstr().asXmmRmR(sseOpcodePsubd, newOperandReg(tmp), tmp2))
+
+			// Convert the lower 16-bits in tmp.
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeCvtdq2ps, newOperandReg(tmp), tmp))
+
+			// Left shift by one and convert vr, meaning that halved conversion result of higher 16-bits in vr.
+			m.insert(m.allocateInstr().asXmmRmiReg(sseOpcodePsrld, newOperandImm32(1), tmp2))
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeCvtdq2ps, newOperandReg(tmp2), tmp2))
+
+			// Double the converted halved higher 16bits.
+			m.insert(m.allocateInstr().asXmmRmR(sseOpcodeAddps, newOperandReg(tmp2), tmp2))
+
+			// Get the conversion result by add tmp (holding lower 16-bit conversion) into vr.
+			m.insert(m.allocateInstr().asXmmRmR(sseOpcodeAddps, newOperandReg(tmp), tmp2))
+
+			m.copyTo(tmp2, m.c.VRegOf(ret))
+		}
+	case ssa.VecLaneF64x2:
+		if signed {
+			xx := m.getOperand_Mem_Reg(m.c.ValueDefinition(x))
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeCvtdq2pd, xx, m.c.VRegOf(ret)))
+		} else {
+			maskReg := m.c.AllocateVReg(ssa.TypeV128)
+			maskLabel := m.getOrAllocateConstLabel(&m.constF64x2CvtFromIMaskIndex, f64x2CvtFromIMask[:])
+			// maskReg = [0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, newOperandMem(m.newAmodeRipRel(maskLabel)), maskReg))
+
+			_xx := m.getOperand_Reg(m.c.ValueDefinition(x))
+			xx := m.copyToTmp(_xx.reg())
+
+			// Given that we have xx = [d1, d2, d3, d4], this results in
+			//	xx = [d1, [0x00, 0x00, 0x30, 0x43], d2, [0x00, 0x00, 0x30, 0x43]]
+			//     = [float64(uint32(d1)) + 0x1.0p52, float64(uint32(d2)) + 0x1.0p52]
+			//     ^See https://stackoverflow.com/questions/13269523/can-all-32-bit-ints-be-exactly-represented-as-a-double
+			m.insert(m.allocateInstr().asXmmRmR(sseOpcodeUnpcklps, newOperandReg(maskReg), xx))
+
+			// maskReg = [float64(0x1.0p52), float64(0x1.0p52)]
+			maskLabel = m.getOrAllocateConstLabel(&m.constTwop52Index, twop52[:])
+			m.insert(m.allocateInstr().asXmmUnaryRmR(sseOpcodeMovdqu, newOperandMem(m.newAmodeRipRel(maskLabel)), maskReg))
+
+			// Now, we get the result as
+			// 	xx = [float64(uint32(d1)), float64(uint32(d2))]
+			// because the following equality always satisfies:
+			//  float64(0x1.0p52 + float64(uint32(x))) - float64(0x1.0p52 + float64(uint32(y))) = float64(uint32(x)) - float64(uint32(y))
+			m.insert(m.allocateInstr().asXmmRmR(sseOpcodeSubpd, newOperandReg(maskReg), xx))
+
+			m.copyTo(xx, m.c.VRegOf(ret))
+		}
+	default:
+		panic(fmt.Sprintf("invalid lane type: %s", lane))
+	}
+}
+
+var (
+	// i32sMaxOnF64x2 holds math.MaxInt32(=2147483647.0) on two f64 lanes.
+	i32sMaxOnF64x2 = [16]byte{ //nolint:unused
+		0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xdf, 0x41, // float64(2147483647.0)
+		0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xdf, 0x41, // float64(2147483647.0)
+	}
+
+	// i32sMaxOnF64x2 holds math.MaxUint32(=4294967295.0) on two f64 lanes.
+	i32uMaxOnF64x2 = [16]byte{ //nolint:unused
+		0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xef, 0x41, // float64(4294967295.0)
+		0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xef, 0x41, // float64(4294967295.0)
+	}
+
+	// twop52 holds two float64(0x1.0p52) on two f64 lanes. 0x1.0p52 is special in the sense that
+	// with this exponent, the mantissa represents a corresponding uint32 number, and arithmetics,
+	// like addition or subtraction, the resulted floating point holds exactly the same
+	// bit representations in 32-bit integer on its mantissa.
+	//
+	// Note: the name twop52 is common across various compiler ecosystem.
+	// 	E.g. https://github.com/llvm/llvm-project/blob/92ab024f81e5b64e258b7c3baaf213c7c26fcf40/compiler-rt/lib/builtins/floatdidf.c#L28
+	// 	E.g. https://opensource.apple.com/source/clang/clang-425.0.24/src/projects/compiler-rt/lib/floatdidf.c.auto.html
+	twop52 = [16]byte{
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, // float64(0x1.0p52)
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, // float64(0x1.0p52)
+	}
+)
+
+func (m *machine) lowerVFcvtToIntSat(x, ret ssa.Value, lane ssa.VecLane, signed bool) {
+	panic("TODO")
+}
+
+func (m *machine) lowerNarrow(x, y, ret ssa.Value, lane ssa.VecLane, signed bool) {
+	_xx := m.getOperand_Reg(m.c.ValueDefinition(x))
+	xx := m.copyToTmp(_xx.reg())
+	yy := m.getOperand_Mem_Reg(m.c.ValueDefinition(y))
+
+	var sseOp sseOpcode
+	switch lane {
+	case ssa.VecLaneI16x8:
+		if signed {
+			sseOp = sseOpcodePacksswb
+		} else {
+			sseOp = sseOpcodePackuswb
+		}
+	case ssa.VecLaneI32x4:
+		if signed {
+			sseOp = sseOpcodePackssdw
+		} else {
+			sseOp = sseOpcodePackusdw
+		}
+	default:
+		panic(fmt.Sprintf("invalid lane type: %s", lane))
+	}
+	m.insert(m.allocateInstr().asXmmRmR(sseOp, yy, xx))
+	m.copyTo(xx, m.c.VRegOf(ret))
+}
diff --git a/internal/engine/wazevo/frontend/lower.go b/internal/engine/wazevo/frontend/lower.go
index 6f197434..aeea2c7e 100644
--- a/internal/engine/wazevo/frontend/lower.go
+++ b/internal/engine/wazevo/frontend/lower.go
@@ -4,6 +4,7 @@ import (
 	"encoding/binary"
 	"fmt"
 	"math"
+	"runtime"
 	"strings"
 
 	"github.com/tetratelabs/wazero/api"
@@ -2869,10 +2870,13 @@ func (c *Compiler) lowerCurrentOpcode() {
 				break
 			}
 			v1 := state.pop()
-			v1w := builder.AllocateInstruction().
-				AsWiden(v1, ssa.VecLaneI32x4, vecOp == wasm.OpcodeVecF64x2ConvertLowI32x4S, true).Insert(builder).Return()
+			if runtime.GOARCH == "arm64" {
+				// TODO: this is weird. fix.
+				v1 = builder.AllocateInstruction().
+					AsWiden(v1, ssa.VecLaneI32x4, vecOp == wasm.OpcodeVecF64x2ConvertLowI32x4S, true).Insert(builder).Return()
+			}
 			ret := builder.AllocateInstruction().
-				AsVFcvtFromInt(v1w, ssa.VecLaneF64x2, vecOp == wasm.OpcodeVecF64x2ConvertLowI32x4S).
+				AsVFcvtFromInt(v1, ssa.VecLaneF64x2, vecOp == wasm.OpcodeVecF64x2ConvertLowI32x4S).
 				Insert(builder).Return()
 			state.push(ret)
 		case wasm.OpcodeVecI8x16NarrowI16x8S, wasm.OpcodeVecI8x16NarrowI16x8U:
diff --git a/internal/engine/wazevo/ssa/instructions.go b/internal/engine/wazevo/ssa/instructions.go
index 31e14042..0fc4288a 100644
--- a/internal/engine/wazevo/ssa/instructions.go
+++ b/internal/engine/wazevo/ssa/instructions.go
@@ -436,9 +436,11 @@ const (
 	OpcodeVFcvtToSintSat
 
 	// OpcodeVFcvtFromUint converts a floating point value from an unsigned integer: `v = FcvtFromUint.lane x` on vector.
+	// x is always a 32-bit integer lane, and the result is either a 32-bit or 64-bit floating point-sized vector.
 	OpcodeVFcvtFromUint
 
 	// OpcodeVFcvtFromSint converts a floating point value from a signed integer: `v = VFcvtFromSint.lane x` on vector.
+	// x is always a 32-bit integer lane, and the result is either a 32-bit or 64-bit floating point-sized vector.
 	OpcodeVFcvtFromSint
 
 	// OpcodeImul performs an integer multiplication: `v = Imul x, y`.


Test patch:
diff --git a/internal/engine/wazevo/backend/isa/amd64/instr_encoding_test.go b/internal/engine/wazevo/backend/isa/amd64/instr_encoding_test.go
index a8cdb29c..22662506 100644
--- a/internal/engine/wazevo/backend/isa/amd64/instr_encoding_test.go
+++ b/internal/engine/wazevo/backend/isa/amd64/instr_encoding_test.go
@@ -380,7 +380,6 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "f3450f589d00000002",
 			wantFormat: "addss 33554432(%r13), %xmm11",
 		},
-		// addsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAddsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f58c1",
@@ -412,421 +411,356 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "f2440f589d00000002",
 			wantFormat: "addsd 33554432(%rbp), %xmm11",
 		},
-		// addps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAddps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f58c1",
 			wantFormat: "addps %xmm1, %xmm0",
 		},
-		// addpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAddpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f58c1",
 			wantFormat: "addpd %xmm1, %xmm0",
 		},
-		// addss
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAddss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f58c1",
 			wantFormat: "addss %xmm1, %xmm0",
 		},
-		// addsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAddsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f58c1",
 			wantFormat: "addsd %xmm1, %xmm0",
 		},
-		// andps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAndps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f54c1",
 			wantFormat: "andps %xmm1, %xmm0",
 		},
-		// andpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAndpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f54c1",
 			wantFormat: "andpd %xmm1, %xmm0",
 		},
-		// andnps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAndnps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f55c1",
 			wantFormat: "andnps %xmm1, %xmm0",
 		},
-		// andnpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeAndnpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f55c1",
 			wantFormat: "andnpd %xmm1, %xmm0",
 		},
-		// blendvpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeBlendvpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3815c1",
 			wantFormat: "blendvpd %xmm1, %xmm0",
 		},
-		// blendvps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeBlendvps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3814c1",
 			wantFormat: "blendvps %xmm1, %xmm0",
 		},
-		// cvttps2dq
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeCvttps2dq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f5bc1",
 			wantFormat: "cvttps2dq %xmm1, %xmm0",
 		},
-		// cvtdq2ps
 		{
-			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeCvtdq2ps, newOperandReg(xmm1VReg), xmm0VReg) },
+			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeCvtdq2ps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f5bc1",
 			wantFormat: "cvtdq2ps %xmm1, %xmm0",
 		},
-		// divps
+		{
+			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeCvtdq2pd, newOperandReg(xmm1VReg), xmm0VReg) },
+			want:       "f30fe6c1",
+			wantFormat: "cvtdq2pd %xmm1, %xmm0",
+		},
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeDivps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f5ec1",
 			wantFormat: "divps %xmm1, %xmm0",
 		},
-		// divpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeDivpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f5ec1",
 			wantFormat: "divpd %xmm1, %xmm0",
 		},
-		// divss
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeDivss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f5ec1",
 			wantFormat: "divss %xmm1, %xmm0",
 		},
-		// divsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeDivsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f5ec1",
 			wantFormat: "divsd %xmm1, %xmm0",
 		},
-		// maxps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMaxps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f5fc1",
 			wantFormat: "maxps %xmm1, %xmm0",
 		},
-		// maxpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMaxpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f5fc1",
 			wantFormat: "maxpd %xmm1, %xmm0",
 		},
-		// maxss
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMaxss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f5fc1",
 			wantFormat: "maxss %xmm1, %xmm0",
 		},
-		// maxsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMaxsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f5fc1",
 			wantFormat: "maxsd %xmm1, %xmm0",
 		},
-		// minps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMinps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f5dc1",
 			wantFormat: "minps %xmm1, %xmm0",
 		},
-		// paddsw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddsw, newOperandReg(xmm7VReg), xmm6VReg) },
 			want:       "660fedf7",
 			wantFormat: "paddsw %xmm7, %xmm6",
 		},
-		// paddusb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddusb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fdcc1",
 			wantFormat: "paddusb %xmm1, %xmm0",
 		},
-		// paddusw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddusw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fddc1",
 			wantFormat: "paddusw %xmm1, %xmm0",
 		},
-		// pand
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePand, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fdbc1",
 			wantFormat: "pand %xmm1, %xmm0",
 		},
-		// pandn
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePandn, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fdfc1",
 			wantFormat: "pandn %xmm1, %xmm0",
 		},
-		// pavgb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePavgb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fe0c1",
 			wantFormat: "pavgb %xmm1, %xmm0",
 		},
-		// pavgw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePavgw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fe3c1",
 			wantFormat: "pavgw %xmm1, %xmm0",
 		},
-		// pcmpeqb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpeqb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f74c1",
 			wantFormat: "pcmpeqb %xmm1, %xmm0",
 		},
-		// pcmpeqw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpeqw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f75c1",
 			wantFormat: "pcmpeqw %xmm1, %xmm0",
 		},
-		// pcmpeqd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpeqd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f76c1",
 			wantFormat: "pcmpeqd %xmm1, %xmm0",
 		},
-		// pcmpeqq
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpeqq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3829c1",
 			wantFormat: "pcmpeqq %xmm1, %xmm0",
 		},
-		// pcmpgtb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpgtb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f64c1",
 			wantFormat: "pcmpgtb %xmm1, %xmm0",
 		},
-		// pcmpgtw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpgtw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f65c1",
 			wantFormat: "pcmpgtw %xmm1, %xmm0",
 		},
-		// pcmpgtd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpgtd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f66c1",
 			wantFormat: "pcmpgtd %xmm1, %xmm0",
 		},
-		// pcmpgtq
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePcmpgtq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3837c1",
 			wantFormat: "pcmpgtq %xmm1, %xmm0",
 		},
-		// pmaddwd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmaddwd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ff5c1",
 			wantFormat: "pmaddwd %xmm1, %xmm0",
 		},
-		// pmaxsb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmaxsb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f383cc1",
 			wantFormat: "pmaxsb %xmm1, %xmm0",
 		},
-		// pmaxsw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmaxsw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660feec1",
 			wantFormat: "pmaxsw %xmm1, %xmm0",
 		},
-		// pmaxsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmaxsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f383dc1",
 			wantFormat: "pmaxsd %xmm1, %xmm0",
 		},
-		// pmaxub
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmaxub, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fdec1",
 			wantFormat: "pmaxub %xmm1, %xmm0",
 		},
-		// pmaxuw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmaxuw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f383ec1",
 			wantFormat: "pmaxuw %xmm1, %xmm0",
 		},
-		// pmaxud
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmaxud, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f383fc1",
 			wantFormat: "pmaxud %xmm1, %xmm0",
 		},
-		// pminsb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePminsb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3838c1",
 			wantFormat: "pminsb %xmm1, %xmm0",
 		},
-		// pminsw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePminsw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660feac1",
 			wantFormat: "pminsw %xmm1, %xmm0",
 		},
-		// pminsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePminsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3839c1",
 			wantFormat: "pminsd %xmm1, %xmm0",
 		},
-		// pminub
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePminub, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fdac1",
 			wantFormat: "pminub %xmm1, %xmm0",
 		},
-		// pminuw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePminuw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f383ac1",
 			wantFormat: "pminuw %xmm1, %xmm0",
 		},
-		// pminud
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePminud, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f383bc1",
 			wantFormat: "pminud %xmm1, %xmm0",
 		},
-		// pmulld
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmulld, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3840c1",
 			wantFormat: "pmulld %xmm1, %xmm0",
 		},
-		// pmullw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmullw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fd5c1",
 			wantFormat: "pmullw %xmm1, %xmm0",
 		},
-		// pmuludq
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePmuludq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ff4c1",
 			wantFormat: "pmuludq %xmm1, %xmm0",
 		},
-		// por
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePor, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660febc1",
 			wantFormat: "por %xmm1, %xmm0",
 		},
-		// pshufb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePshufb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3800c1",
 			wantFormat: "pshufb %xmm1, %xmm0",
 		},
-		// psubb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ff8c1",
 			wantFormat: "psubb %xmm1, %xmm0",
 		},
-		// psubd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ffac1",
 			wantFormat: "psubd %xmm1, %xmm0",
 		},
-		// psubq
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ffbc1",
 			wantFormat: "psubq %xmm1, %xmm0",
 		},
-		// psubw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ff9c1",
 			wantFormat: "psubw %xmm1, %xmm0",
 		},
-		// psubsb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubsb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fe8c1",
 			wantFormat: "psubsb %xmm1, %xmm0",
 		},
-		// psubsw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubsw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fe9c1",
 			wantFormat: "psubsw %xmm1, %xmm0",
 		},
-		// psubusb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubusb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fd8c1",
 			wantFormat: "psubusb %xmm1, %xmm0",
 		},
-		// psubusw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePsubusw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fd9c1",
 			wantFormat: "psubusw %xmm1, %xmm0",
 		},
-		// punpckhbw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePunpckhbw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f68c1",
 			wantFormat: "punpckhbw %xmm1, %xmm0",
 		},
-		// punpcklbw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePunpcklbw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f60c1",
 			wantFormat: "punpcklbw %xmm1, %xmm0",
 		},
-		// pxor
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePxor, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fefc1",
 			wantFormat: "pxor %xmm1, %xmm0",
 		},
-		// subps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeSubps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f5cc1",
 			wantFormat: "subps %xmm1, %xmm0",
 		},
-		// subpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeSubpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f5cc1",
 			wantFormat: "subpd %xmm1, %xmm0",
 		},
-		// subss
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeSubss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f5cc1",
 			wantFormat: "subss %xmm1, %xmm0",
 		},
-		// subsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeSubsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f5cc1",
 			wantFormat: "subsd %xmm1, %xmm0",
 		},
-		// xorps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeXorps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f57c1",
@@ -837,7 +771,6 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "0f57c1",
 			wantFormat: "xorps %xmm1, %xmm0",
 		},
-		// xorpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeXorpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f57c1",
@@ -848,163 +781,136 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "660f57c1",
 			wantFormat: "xorpd %xmm1, %xmm0",
 		},
-		// minpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMinpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f5dc1",
 			wantFormat: "minpd %xmm1, %xmm0",
 		},
-		// minss
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMinss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f5dc1",
 			wantFormat: "minss %xmm1, %xmm0",
 		},
-		// minsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMinsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f5dc1",
 			wantFormat: "minsd %xmm1, %xmm0",
 		},
-		// movlhps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMovlhps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f16c1",
 			wantFormat: "movlhps %xmm1, %xmm0",
 		},
-		// movsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMovsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f10c1",
 			wantFormat: "movsd %xmm1, %xmm0",
 		},
-		// mulps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMulps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f59c1",
 			wantFormat: "mulps %xmm1, %xmm0",
 		},
-		// mulpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMulpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f59c1",
 			wantFormat: "mulpd %xmm1, %xmm0",
 		},
-		// mulss
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMulss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f59c1",
 			wantFormat: "mulss %xmm1, %xmm0",
 		},
-		// mulsd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeMulsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f59c1",
 			wantFormat: "mulsd %xmm1, %xmm0",
 		},
-		// orpd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeOrpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f56c1",
 			wantFormat: "orpd %xmm1, %xmm0",
 		},
-		// orps
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeOrps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f56c1",
 			wantFormat: "orps %xmm1, %xmm0",
 		},
-		// packssdw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePackssdw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f6bc1",
 			wantFormat: "packssdw %xmm1, %xmm0",
 		},
-		// packsswb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePacksswb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f63c1",
 			wantFormat: "packsswb %xmm1, %xmm0",
 		},
-		// packusdw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePackusdw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f382bc1",
 			wantFormat: "packusdw %xmm1, %xmm0",
 		},
-		// packuswb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePackuswb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f67c1",
 			wantFormat: "packuswb %xmm1, %xmm0",
 		},
-		// paddb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ffcc1",
 			wantFormat: "paddb %xmm1, %xmm0",
 		},
-		// paddd
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ffec1",
 			wantFormat: "paddd %xmm1, %xmm0",
 		},
-		// paddq
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fd4c1",
 			wantFormat: "paddq %xmm1, %xmm0",
 		},
-		// paddw
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660ffdc1",
 			wantFormat: "paddw %xmm1, %xmm0",
 		},
-		// paddsb
 		{
 			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodePaddsb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660fecc1",
 			wantFormat: "paddsb %xmm1, %xmm0",
 		},
-		// cvtss2sd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeCvtss2sd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f5ac1",
 			wantFormat: "cvtss2sd %xmm1, %xmm0",
 		},
-		// cvtsd2ss
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeCvtsd2ss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f5ac1",
 			wantFormat: "cvtsd2ss %xmm1, %xmm0",
 		},
-		// movaps
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovaps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f28c1",
 			wantFormat: "movaps %xmm1, %xmm0",
 		},
-		// movapd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovapd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f28c1",
 			wantFormat: "movapd %xmm1, %xmm0",
 		},
-		// movdqa
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovdqa, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f6fc1",
 			wantFormat: "movdqa %xmm1, %xmm0",
 		},
-		// movdqu
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovdqu, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f6fc1",
 			wantFormat: "movdqu %xmm1, %xmm0",
 		},
-		// movsd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f10c1",
@@ -1017,7 +923,6 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "f2410f10442410",
 			wantFormat: "movsd 16(%r12), %xmm0",
 		},
-		// movss
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f10c1",
@@ -1030,91 +935,76 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "f3450f10bc24a0000000",
 			wantFormat: "movss 160(%r12), %xmm15",
 		},
-		// movups
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovups, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f10c1",
 			wantFormat: "movups %xmm1, %xmm0",
 		},
-		// movupd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeMovupd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f10c1",
 			wantFormat: "movupd %xmm1, %xmm0",
 		},
-		// pabsb
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePabsb, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f381cc1",
 			wantFormat: "pabsb %xmm1, %xmm0",
 		},
-		// pabsw
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePabsw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f381dc1",
 			wantFormat: "pabsw %xmm1, %xmm0",
 		},
-		// pabsd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePabsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f381ec1",
 			wantFormat: "pabsd %xmm1, %xmm0",
 		},
-		// pmovsxbd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovsxbd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3821c1",
 			wantFormat: "pmovsxbd %xmm1, %xmm0",
 		},
-		// pmovsxbw
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovsxbw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3820c1",
 			wantFormat: "pmovsxbw %xmm1, %xmm0",
 		},
-		// pmovsxbq
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovsxbq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3822c1",
 			wantFormat: "pmovsxbq %xmm1, %xmm0",
 		},
-		// pmovsxwd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovsxwd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3823c1",
 			wantFormat: "pmovsxwd %xmm1, %xmm0",
 		},
-		// pmovsxwq
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovsxwq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3824c1",
 			wantFormat: "pmovsxwq %xmm1, %xmm0",
 		},
-		// pmovsxdq
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovsxdq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3825c1",
 			wantFormat: "pmovsxdq %xmm1, %xmm0",
 		},
-		// pmovzxbd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovzxbd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3831c1",
 			wantFormat: "pmovzxbd %xmm1, %xmm0",
 		},
-		// pmovzxbw
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovzxbw, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3830c1",
 			wantFormat: "pmovzxbw %xmm1, %xmm0",
 		},
-		// pmovzxbq
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovzxbq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3832c1",
 			wantFormat: "pmovzxbq %xmm1, %xmm0",
 		},
-		// pmovzxwd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovzxwd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3833c1",
@@ -1141,37 +1031,31 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "66440f38339d00000002",
 			wantFormat: "pmovzxwd 33554432(%rbp), %xmm11",
 		},
-		// pmovzxwq
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovzxwq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3834c1",
 			wantFormat: "pmovzxwq %xmm1, %xmm0",
 		},
-		// pmovzxdq
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodePmovzxdq, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f3835c1",
 			wantFormat: "pmovzxdq %xmm1, %xmm0",
 		},
-		// sqrtps
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeSqrtps, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "0f51c1",
 			wantFormat: "sqrtps %xmm1, %xmm0",
 		},
-		// sqrtpd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeSqrtpd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "660f51c1",
 			wantFormat: "sqrtpd %xmm1, %xmm0",
 		},
-		// sqrtss
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeSqrtss, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f30f51c1",
 			wantFormat: "sqrtss %xmm1, %xmm0",
 		},
-		// sqrtsd
 		{
 			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeSqrtsd, newOperandReg(xmm1VReg), xmm0VReg) },
 			want:       "f20f51c1",
@@ -4125,6 +4009,21 @@ func TestInstruction_format_encode(t *testing.T) {
 			want:       "660f380bc1",
 			wantFormat: "pmulhrsw %xmm1, %xmm0",
 		},
+		{
+			setup:      func(i *instruction) { i.asXmmRmR(sseOpcodeUnpcklps, newOperandReg(xmm1VReg), xmm0VReg) },
+			want:       "0f14c1",
+			wantFormat: "unpcklps %xmm1, %xmm0",
+		},
+		{
+			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeCvtps2pd, newOperandReg(xmm1VReg), xmm0VReg) },
+			want:       "0f5ac1",
+			wantFormat: "cvtps2pd %xmm1, %xmm0",
+		},
+		{
+			setup:      func(i *instruction) { i.asXmmUnaryRmR(sseOpcodeCvtpd2ps, newOperandReg(xmm15VReg), xmm0VReg) },
+			want:       "66410f5ac7",
+			wantFormat: "cvtpd2ps %xmm15, %xmm0",
+		},
 	} {
 		tc := tc
 		t.Run(tc.wantFormat, func(t *testing.T) {
diff --git a/internal/engine/wazevo/e2e_test.go b/internal/engine/wazevo/e2e_test.go
index 7d563322..5783c780 100644
--- a/internal/engine/wazevo/e2e_test.go
+++ b/internal/engine/wazevo/e2e_test.go
@@ -1510,7 +1510,7 @@ func TestSpectestV2(t *testing.T) {
 		{"simd_bit_shift"},
 		{"simd_bitwise"},
 		{"simd_const"},
-		//{"simd_conversions"},
+		{"simd_conversions"},
 		{"simd_i8x16_arith"},
 		{"simd_i8x16_arith2"},
 		{"simd_i8x16_sat_arith"},