Repository: amaranth-lang/amaranth
Pull request #1167 (2024-02-28 09:06:42)

lib.io: Add missing __repr__ to signature type.


Patch:
diff --git a/amaranth/lib/io.py b/amaranth/lib/io.py
index 2a179ec..09058d2 100644
--- a/amaranth/lib/io.py
+++ b/amaranth/lib/io.py
@@ -114,6 +114,10 @@ class Pin(wiring.PureInterface):
                     self.dir == other.dir and
                     self.xdr == other.xdr)
 
+        def __repr__(self):
+            xdr = f", xdr={self.xdr}" if self.xdr != 0 else ""
+            return f"Pin.Signature({self.width}, dir={self.dir!r}{xdr})"
+
         def create(self, *, path=None, src_loc_at=0):
             return Pin(self.width, self.dir, xdr=self.xdr, path=path, src_loc_at=1 + src_loc_at)
 
@@ -128,11 +132,11 @@ class Pin(wiring.PureInterface):
     @property
     def width(self):
         return self.signature.width
-    
+
     @property
     def dir(self):
         return self.signature.dir
-    
+
     @property
     def xdr(self):
         return self.signature.xdr
diff --git a/amaranth/lib/memory.py b/amaranth/lib/memory.py
index a1a69f2..9cd4687 100644
--- a/amaranth/lib/memory.py
+++ b/amaranth/lib/memory.py
@@ -110,6 +110,12 @@ class WritePort:
         def granularity(self):
             return self._granularity
 
+        def __eq__(self, other):
+            return (type(self) is type(other) and
+                    self.addr_width == other.addr_width and
+                    self.shape == other.shape and
+                    self.granularity == other.granularity)
+
         def __repr__(self):
             granularity = f", granularity={self.granularity}" if self.granularity is not None else ""
             return f"WritePort.Signature(addr_width={self.addr_width}, shape={self.shape}{granularity})"
@@ -213,6 +219,11 @@ class ReadPort:
         def shape(self):
             return self._shape
 
+        def __eq__(self, other):
+            return (type(self) is type(other) and
+                    self.addr_width == other.addr_width and
+                    self.shape == other.shape)
+
         def __repr__(self):
             return f"ReadPort.Signature(addr_width={self.addr_width}, shape={self.shape})"
 


Test patch:
diff --git a/tests/test_lib_io.py b/tests/test_lib_io.py
index ae41c07..1c82b1f 100644
--- a/tests/test_lib_io.py
+++ b/tests/test_lib_io.py
@@ -199,6 +199,16 @@ class PinSignatureDDRTestCase(PinSignatureTestCase):
         })
 
 
+class PinSignatureReprCase(FHDLTestCase):
+    def test_repr(self):
+        sig_0 = Pin.Signature(1, dir="i")
+        self.assertRepr(sig_0, "Pin.Signature(1, dir='i')")
+        sig_0 = Pin.Signature(2, dir="o", xdr=1)
+        self.assertRepr(sig_0, "Pin.Signature(2, dir='o', xdr=1)")
+        sig_0 = Pin.Signature(3, dir="io", xdr=2)
+        self.assertRepr(sig_0, "Pin.Signature(3, dir='io', xdr=2)")
+
+
 class PinTestCase(FHDLTestCase):
     def test_attributes(self):
         pin = Pin(2, dir="io", xdr=2)
@@ -208,4 +218,3 @@ class PinTestCase(FHDLTestCase):
         self.assertEqual(pin.signature.width, 2)
         self.assertEqual(pin.signature.dir,   "io")
         self.assertEqual(pin.signature.xdr,   2)
-
diff --git a/tests/test_lib_memory.py b/tests/test_lib_memory.py
index 917097f..eb7512b 100644
--- a/tests/test_lib_memory.py
+++ b/tests/test_lib_memory.py
@@ -83,6 +83,16 @@ class WritePortTestCase(FHDLTestCase):
                 "^Granularity must divide data array length$"):
             WritePort.Signature(addr_width=2, shape=ArrayLayout(8, 8), granularity=3)
 
+    def test_signature_eq(self):
+        sig = WritePort.Signature(addr_width=2, shape=8)
+        self.assertEqual(sig, WritePort.Signature(addr_width=2, shape=8))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=7))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=1, shape=8))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=8, granularity=8))
+        sig = WritePort.Signature(addr_width=2, shape=8, granularity=4)
+        self.assertEqual(sig, WritePort.Signature(addr_width=2, shape=8, granularity=4))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=8, granularity=8))
+
     def test_constructor(self):
         signature = WritePort.Signature(shape=MyStruct, addr_width=4)
         port = WritePort(signature, memory=None, domain="sync")
@@ -171,6 +181,13 @@ class ReadPortTestCase(FHDLTestCase):
                 "^`addr_width` must be a non-negative int, not -2$"):
             ReadPort.Signature(addr_width=-2, shape=8)
 
+    def test_signature_eq(self):
+        sig = ReadPort.Signature(addr_width=2, shape=8)
+        self.assertEqual(sig, ReadPort.Signature(addr_width=2, shape=8))
+        self.assertNotEqual(sig, ReadPort.Signature(addr_width=2, shape=7))
+        self.assertNotEqual(sig, ReadPort.Signature(addr_width=1, shape=8))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=8))
+
     def test_constructor(self):
         signature = ReadPort.Signature(shape=MyStruct, addr_width=4)
         port = ReadPort(signature, memory=None, domain="sync")