Repository: amaranth-lang/amaranth
Pull request #1139 (2024-02-13 23:47:29)

hdl._dsl: fix using 0-width `Switch` with integer keys. [0.4 backport]
Depends on #1137.

codecov[bot]: ## [Codecov](https://app.codecov.io/gh/amaranth-lang/amaranth/pull/1139?src=pr&el=h1&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=amaranth-lang) Report
All modified and coverable lines are covered by tests :white_check_mark:
> Comparison is base [(`fd4ba36`)](https://app.codecov.io/gh/amaranth-lang/amaranth/commit/fd4ba36edf7eb530c20937620b6e1e6ff327a6b0?el=desc&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=amaranth-lang) 83.85% compared to head [(`18d5f2b`)](https://app.codecov.io/gh/amaranth-lang/amaranth/pull/1139?src=pr&el=desc&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=amaranth-lang) 83.83%.


<details><summary>Additional details and impacted files</summary>


```diff
@@            Coverage Diff             @@
##           v0.4.x    #1139      +/-   ##
==========================================
- Coverage   83.85%   83.83%   -0.03%     
==========================================
  Files          55       55              
  Lines        8110     8112       +2     
  Branches     1981     1982       +1     
==========================================
  Hits         6801     6801              
- Misses       1096     1098       +2     
  Partials      213      213              
```



</details>

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Patch:
diff --git a/amaranth/hdl/dsl.py b/amaranth/hdl/dsl.py
index 92dd679..839aa71 100644
--- a/amaranth/hdl/dsl.py
+++ b/amaranth/hdl/dsl.py
@@ -331,6 +331,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
                                       "expression, not {!r}"
                                       .format(pattern)) from e
                 pattern_len = bits_for(pattern.value)
+                if pattern.value == 0:
+                    pattern_len = 0
                 if pattern_len > len(switch_data["test"]):
                     warnings.warn("Case pattern '{!r}' ({}'{:b}) is wider than switch value "
                                   "(which has width {}); comparison will never be true"


Test patch:
diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py
index 44001d0..ff3e9fc 100644
--- a/tests/test_hdl_dsl.py
+++ b/tests/test_hdl_dsl.py
@@ -494,6 +494,21 @@ class DSLTestCase(FHDLTestCase):
         )
         """)
 
+    def test_Switch_zero_width(self):
+        m = Module()
+        s = Signal(0)
+        with m.Switch(s):
+            with m.Case(0):
+                m.d.comb += self.c1.eq(1)
+        m._flush()
+        self.assertRepr(m._statements, """
+        (
+            (switch (sig s)
+                (case (eq (sig c1) (const 1'd1)))
+            )
+        )
+        """)
+
     def test_Case_bits_wrong(self):
         m = Module()
         with m.Switch(self.w1):