Repository: bytecodealliance/wasmtime
Pull request #7242 (2023-10-14 03:50:11)

Minor logging tweaks
Some things I noticed from #7239 which are very much not critical but I figure might be nice-to-haves:

* Move the logging configuration to the `wasmtime-cli-flags` crate with the other logging configuration to keep it in one place.
* Remove `pretty_env_logger` since `tracing-subscriber` probably supplants it.
* Don't explicitly inherit env vars in tests since that happens automatically with `Command`.

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Patch:
diff --git a/Cargo.lock b/Cargo.lock
index 3b6e0bb5a..9046254b1 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -3393,7 +3393,6 @@ dependencies = [
  "tempfile",
  "test-programs-artifacts",
  "tokio",
- "tracing-subscriber",
  "walkdir",
  "wasm-encoder",
  "wasmparser",
@@ -3423,8 +3422,8 @@ dependencies = [
  "clap",
  "file-per-thread-logger",
  "humantime 2.1.0",
- "pretty_env_logger 0.5.0",
  "rayon",
+ "tracing-subscriber",
  "wasmtime",
 ]
 
diff --git a/Cargo.toml b/Cargo.toml
index ec36b875e..8ca8a729c 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -39,7 +39,6 @@ wasmtime-runtime = { workspace = true }
 clap = { workspace = true, features = ["color", "suggestions", "derive"] }
 anyhow = { workspace = true }
 target-lexicon = { workspace = true }
-tracing-subscriber = { workspace = true }
 once_cell = { workspace = true }
 listenfd = "1.0.0"
 wat = { workspace = true }
diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index 40db1f184..000121887 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -241,13 +241,6 @@
       (addr Reg)
       (v Reg)
       (ty Type))
-    ;; an integer compare.
-    (Icmp
-      (cc IntCC)
-      (rd WritableReg)
-      (a ValueRegs)
-      (b ValueRegs)
-      (ty Type))
     (FcvtToInt
       (is_sat bool)
       (rd WritableReg)
@@ -1191,6 +1184,12 @@
 (rule (rv_andi rs1 imm)
   (alu_rr_imm12 (AluOPRRI.Andi) rs1 imm))
 
+;; Helper for emitting the `slt` ("Set Less Than") instruction.
+;; rd ← rs1 < rs2
+(decl rv_slt (XReg XReg) XReg)
+(rule (rv_slt rs1 rs2)
+  (alu_rrr (AluOPRRR.Slt) rs1 rs2))
+
 ;; Helper for emitting the `sltu` ("Set Less Than Unsigned") instruction.
 ;; rd ← rs1 < rs2
 (decl rv_sltu (XReg XReg) XReg)
@@ -1203,6 +1202,12 @@
 (rule (rv_snez rs1)
   (rv_sltu (zero_reg) rs1))
 
+;; Helper for emiting the `slti` ("Set Less Than Immediate") instruction.
+;; rd ← rs1 < imm
+(decl rv_slti (XReg Imm12) XReg)
+(rule (rv_slti rs1 imm)
+  (alu_rr_imm12 (AluOPRRI.Slti) rs1 imm))
+
 ;; Helper for emiting the `sltiu` ("Set Less Than Immediate Unsigned") instruction.
 ;; rd ← rs1 < imm
 (decl rv_sltiu (XReg Imm12) XReg)
@@ -1786,6 +1791,10 @@
 (decl imm12_const_add (i32 i32) Imm12)
 (extern constructor imm12_const_add imm12_const_add)
 
+;; Performs a fallible add of the `Imm12` value and the 32-bit value provided.
+(decl pure partial imm12_add (Imm12 i32) Imm12)
+(extern constructor imm12_add imm12_add)
+
 (decl imm12_and (Imm12 u64) Imm12)
 (extern constructor imm12_and imm12_and)
 
@@ -2667,10 +2676,6 @@
       (high XReg (rv_sub high_tmp borrow)))
     (value_regs low high)))
 
-;; int scalar zero regs.
-(decl int_zero_reg (Type) ValueRegs)
-(extern constructor int_zero_reg int_zero_reg)
-
 ;; Consume a CmpResult, producing a branch on its result.
 (decl cond_br (IntegerCompare CondBrTarget CondBrTarget) SideEffectNoResult)
 (rule (cond_br cmp then else)
@@ -2739,7 +2744,7 @@
 ;; This is used in `Select` and `brif` for example to generate conditional
 ;; branches. The returned comparison, when taken, represents that `Value` is
 ;; nonzero. When not taken the input `Value` is zero.
-(decl lower_int_compare (Value) IntegerCompare)
+(decl is_nonzero_cmp (Value) IntegerCompare)
 
 ;; Base case - convert to a "truthy" value and compare it against zero.
 ;;
@@ -2750,46 +2755,72 @@
 ;; Additionally the base 64-bit ISA has a single instruction for sign-extending
 ;; from 32 to 64-bits which makes that a bit cheaper if used.
 ;; of registers sign-extend the results.
-(rule 0 (lower_int_compare val @ (value_type (fits_in_64 _)))
+(rule 0 (is_nonzero_cmp val @ (value_type (fits_in_64 _)))
   (cmp_nez (sext val)))
-(rule 1 (lower_int_compare val @ (value_type $I8))
+(rule 1 (is_nonzero_cmp val @ (value_type $I8))
   (cmp_nez (zext val)))
-(rule 1 (lower_int_compare val @ (value_type $I128))
+(rule 1 (is_nonzero_cmp val @ (value_type $I128))
   (cmp_nez (rv_or (value_regs_get val 0) (value_regs_get val 1))))
 
-;; If the input value is itself an `icmp` we can avoid generating the result of
-;; the `icmp` and instead move the comparison directly into the `IntegerCompare`
-;; that's returned. Note that comparisons compare full registers so
-;; sign-extension according to the integer comparison performed here is
-;; required.
+;; If the input value is itself an `icmp` or `fcmp` we can avoid generating the
+;; result of the comparison and instead move the comparison directly into the
+;; `IntegerCompare` that's returned.
+(rule 2 (is_nonzero_cmp (maybe_uextend (icmp cc a b @ (value_type (fits_in_64 _)))))
+  (icmp_to_int_compare cc a b))
+(rule 2 (is_nonzero_cmp (maybe_uextend (fcmp cc a @ (value_type ty) b)))
+  (fcmp_to_float_compare cc ty a b))
+
+;; Creates an `IntegerCompare` from an `icmp` node's parts. This will extend
+;; values as necessary to their full register width to perform the
+;; comparison. The returned `IntegerCompare` is suitable to use in conditional
+;; branches for example.
+;;
+;; Note that this should ideally only be used when the `IntegerCompare` returned
+;; is fed into a branch. If `IntegerCompare` is materialized this will miss out
+;; on optimizations to compare against constants using some native instructions.
+(decl icmp_to_int_compare (IntCC Value Value) IntegerCompare)
+(rule 0 (icmp_to_int_compare cc a b @ (value_type (fits_in_64 in_ty)))
+  (int_compare cc (put_value_in_reg_for_icmp cc a) (put_value_in_reg_for_icmp cc b)))
+(rule 1 (icmp_to_int_compare cc a b @ (value_type $I128))
+  (cmp_nez (lower_icmp_i128 cc a b)))
+
+;; Places a `Value` into a full register width to prepare for a comparison
+;; using `IntCC`.
 ;;
-;; Also note that as a small optimization `Equal` and `NotEqual` use
-;; sign-extension for 32-bit values since the same result is produced with
-;; either zero-or-sign extension and many values are already sign-extended given
-;; the RV64 instruction set (e.g. `addw` adds 32-bit values and sign extends),
-;; theoretically resulting in more efficient codegen.
-(rule 2 (lower_int_compare (maybe_uextend (icmp cc a b @ (value_type (fits_in_64 in_ty)))))
-  (int_compare cc (zext a) (zext b)))
-(rule 3 (lower_int_compare (maybe_uextend (icmp cc a b @ (value_type (fits_in_64 in_ty)))))
+;; This is largely a glorified means of choosing sign-extension or
+;; zero-extension for the `Value` input.
+(decl put_value_in_reg_for_icmp (IntCC Value) XReg)
+
+;; Base cases, use the `cc` to determine whether to zero or sign extend.
+(rule 0 (put_value_in_reg_for_icmp cc val)
+  (zext val))
+(rule 1 (put_value_in_reg_for_icmp cc val)
   (if (signed_cond_code cc))
-  (int_compare cc (sext a) (sext b)))
-(rule 4 (lower_int_compare (maybe_uextend (icmp cc @ (IntCC.Equal) a b @ (value_type $I32))))
-  (int_compare cc (sext a) (sext b)))
-(rule 4 (lower_int_compare (maybe_uextend (icmp cc @ (IntCC.NotEqual) a b @ (value_type $I32))))
-  (int_compare cc (sext a) (sext b)))
-
-;; If the input is an `fcmp` then the `FCmp` return value is directly
-;; convertible to `IntegerCompare` which can shave off an instruction from the
-;; fallback lowering above.
-(rule 2 (lower_int_compare (maybe_uextend (fcmp cc a @ (value_type ty) b)))
-  (emit_fcmp cc ty a b))
+  (sext val))
+
+;; For equality and inequality favor sign extension since it's generally
+;; easier to perform sign extension on RV64 via native instructions. For 8-bit
+;; types though use zero-extension since that's a single instruction `and`.
+(rule 2 (put_value_in_reg_for_icmp (IntCC.Equal) val @ (value_type (fits_in_64 _)))
+  (sext val))
+(rule 2 (put_value_in_reg_for_icmp (IntCC.NotEqual) val @ (value_type (fits_in_64 _)))
+  (sext val))
+(rule 3 (put_value_in_reg_for_icmp (IntCC.Equal) val @ (value_type $I8))
+  (zext val))
+(rule 3 (put_value_in_reg_for_icmp (IntCC.NotEqual) val @ (value_type $I8))
+  (zext val))
+
+;; As a special case use `x0` directly if a constant is 0.
+(rule 4 (put_value_in_reg_for_icmp _ (i64_from_iconst 0))
+  (zero_reg))
+
 
 (decl partial lower_branch (Inst MachLabelSlice) Unit)
 (rule (lower_branch (jump _) (single_target label))
       (emit_side_effect (rv_j label)))
 
 (rule (lower_branch (brif v _ _) (two_targets then else))
-  (emit_side_effect (cond_br (lower_int_compare v) then else)))
+  (emit_side_effect (cond_br (is_nonzero_cmp v) then else)))
 
 (decl lower_br_table (Reg MachLabelSlice) Unit)
 (extern constructor lower_br_table lower_br_table)
@@ -2943,8 +2974,9 @@
 (extern constructor sp_reg sp_reg)
 
 ;; Helper for creating the zero register.
-(decl zero_reg () Reg)
+(decl zero_reg () XReg)
 (extern constructor zero_reg zero_reg)
+(extern extractor zero_reg is_zero_reg)
 
 (decl value_regs_zero () ValueRegs)
 (rule (value_regs_zero)
@@ -2956,67 +2988,64 @@
 
 ;;;; Helpers for floating point comparisons ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(decl is_not_nan (Type FReg) XReg)
-(rule (is_not_nan ty a) (rv_feq ty a a))
-
-(decl ordered (Type FReg FReg) XReg)
-(rule (ordered ty a b) (rv_and (is_not_nan ty a) (is_not_nan ty b)))
-
-(type FCmp (enum
+(type FloatCompare (enum
   ;; The comparison succeeded if `r` is one
   (One (r XReg))
   ;; The comparison succeeded if `r` is zero
   (Zero (r XReg))
 ))
 
-(decl fcmp_invert (FCmp) FCmp)
-(rule (fcmp_invert (FCmp.One r)) (FCmp.Zero r))
-(rule (fcmp_invert (FCmp.Zero r)) (FCmp.One r))
+(decl float_compare_invert (FloatCompare) FloatCompare)
+(rule (float_compare_invert (FloatCompare.One r)) (FloatCompare.Zero r))
+(rule (float_compare_invert (FloatCompare.Zero r)) (FloatCompare.One r))
 
-(decl fcmp_to_compare (FCmp) IntegerCompare)
-(rule (fcmp_to_compare (FCmp.One r)) (cmp_nez r))
-(rule (fcmp_to_compare (FCmp.Zero r)) (cmp_eqz r))
-(convert FCmp IntegerCompare fcmp_to_compare)
+(decl float_to_int_compare (FloatCompare) IntegerCompare)
+(rule (float_to_int_compare (FloatCompare.One r)) (cmp_nez r))
+(rule (float_to_int_compare (FloatCompare.Zero r)) (cmp_eqz r))
+(convert FloatCompare IntegerCompare float_to_int_compare)
 
 ;; Compare two floating point numbers and return a zero/non-zero result.
-(decl emit_fcmp (FloatCC Type FReg FReg) FCmp)
+(decl fcmp_to_float_compare (FloatCC Type FReg FReg) FloatCompare)
 
 ;; Direct codegen for unordered comparisons is not that efficient, so invert
 ;; the comparison to get an ordered comparison and generate that. Then invert
 ;; the result to produce the final fcmp result.
-(rule 0 (emit_fcmp cc ty a b)
+(rule 0 (fcmp_to_float_compare cc ty a b)
   (if-let $true (floatcc_unordered cc))
-  (fcmp_invert (emit_fcmp (floatcc_complement cc) ty a b)))
+  (float_compare_invert (fcmp_to_float_compare (floatcc_complement cc) ty a b)))
 
 ;; a is not nan && b is not nan
-(rule 1 (emit_fcmp (FloatCC.Ordered) ty a b)
-  (FCmp.One (ordered ty a b)))
+(rule 1 (fcmp_to_float_compare (FloatCC.Ordered) ty a b)
+  (FloatCompare.One (rv_and (is_not_nan ty a) (is_not_nan ty b))))
+
+(decl is_not_nan (Type FReg) XReg)
+(rule (is_not_nan ty a) (rv_feq ty a a))
 
 ;; a == b
-(rule 1 (emit_fcmp (FloatCC.Equal) ty a b)
-  (FCmp.One (rv_feq ty a b)))
+(rule 1 (fcmp_to_float_compare (FloatCC.Equal) ty a b)
+  (FloatCompare.One (rv_feq ty a b)))
 
 ;; a != b
 ;; == !(a == b)
-(rule 1 (emit_fcmp (FloatCC.NotEqual) ty a b)
-  (FCmp.Zero (rv_feq ty a b)))
+(rule 1 (fcmp_to_float_compare (FloatCC.NotEqual) ty a b)
+  (FloatCompare.Zero (rv_feq ty a b)))
 
 ;; a < b || a > b
-(rule 1 (emit_fcmp (FloatCC.OrderedNotEqual) ty a b)
-  (FCmp.One (rv_or (rv_flt ty a b) (rv_fgt ty a b))))
+(rule 1 (fcmp_to_float_compare (FloatCC.OrderedNotEqual) ty a b)
+  (FloatCompare.One (rv_or (rv_flt ty a b) (rv_fgt ty a b))))
 
 ;; a < b
-(rule 1 (emit_fcmp (FloatCC.LessThan) ty a b)
-  (FCmp.One (rv_flt ty a b)))
+(rule 1 (fcmp_to_float_compare (FloatCC.LessThan) ty a b)
+  (FloatCompare.One (rv_flt ty a b)))
 
 ;; a <= b
-(rule 1 (emit_fcmp (FloatCC.LessThanOrEqual) ty a b)
-  (FCmp.One (rv_fle ty a b)))
+(rule 1 (fcmp_to_float_compare (FloatCC.LessThanOrEqual) ty a b)
+  (FloatCompare.One (rv_fle ty a b)))
 
 ;; a > b
-(rule 1 (emit_fcmp (FloatCC.GreaterThan) ty a b)
-  (FCmp.One (rv_fgt ty a b)))
+(rule 1 (fcmp_to_float_compare (FloatCC.GreaterThan) ty a b)
+  (FloatCompare.One (rv_fgt ty a b)))
 
 ;; a >= b
-(rule 1 (emit_fcmp (FloatCC.GreaterThanOrEqual) ty a b)
-  (FCmp.One (rv_fge ty a b)))
+(rule 1 (fcmp_to_float_compare (FloatCC.GreaterThanOrEqual) ty a b)
+  (FloatCompare.One (rv_fge ty a b)))
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index da7845de7..c96113b36 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -217,104 +217,6 @@ impl Inst {
         insts
     }
 
-    pub(crate) fn lower_br_icmp(
-        cc: IntCC,
-        a: ValueRegs<Reg>,
-        b: ValueRegs<Reg>,
-        taken: CondBrTarget,
-        not_taken: CondBrTarget,
-        ty: Type,
-    ) -> SmallInstVec<Inst> {
-        let mut insts = SmallInstVec::new();
-        if ty.bits() <= 64 {
-            let rs1 = a.only_reg().unwrap();
-            let rs2 = b.only_reg().unwrap();
-            let inst = Inst::CondBr {
-                taken,
-                not_taken,
-                kind: IntegerCompare { kind: cc, rs1, rs2 },
-            };
-            insts.push(inst);
-            return insts;
-        }
-        // compare i128
-        let low = |cc: IntCC| -> IntegerCompare {
-            IntegerCompare {
-                rs1: a.regs()[0],
-                rs2: b.regs()[0],
-                kind: cc,
-            }
-        };
-        let high = |cc: IntCC| -> IntegerCompare {
-            IntegerCompare {
-                rs1: a.regs()[1],
-                rs2: b.regs()[1],
-                kind: cc,
-            }
-        };
-        match cc {
-            IntCC::Equal => {
-                // if high part not equal,
-                // then we can go to not_taken otherwise fallthrough.
-                insts.push(Inst::CondBr {
-                    taken: not_taken,
-                    not_taken: CondBrTarget::Fallthrough,
-                    kind: high(IntCC::NotEqual),
-                });
-                // the rest part.
-                insts.push(Inst::CondBr {
-                    taken,
-                    not_taken,
-                    kind: low(IntCC::Equal),
-                });
-            }
-
-            IntCC::NotEqual => {
-                // if the high part not equal ,
-                // we know the whole must be not equal,
-                // we can goto the taken part , otherwise fallthrought.
-                insts.push(Inst::CondBr {
-                    taken,
-                    not_taken: CondBrTarget::Fallthrough, //  no branch
-                    kind: high(IntCC::NotEqual),
-                });
-
-                insts.push(Inst::CondBr {
-                    taken,
-                    not_taken,
-                    kind: low(IntCC::NotEqual),
-                });
-            }
-            IntCC::SignedGreaterThanOrEqual
-            | IntCC::SignedLessThanOrEqual
-            | IntCC::UnsignedGreaterThanOrEqual
-            | IntCC::UnsignedLessThanOrEqual
-            | IntCC::SignedGreaterThan
-            | IntCC::SignedLessThan
-            | IntCC::UnsignedLessThan
-            | IntCC::UnsignedGreaterThan => {
-                //
-                insts.push(Inst::CondBr {
-                    taken,
-                    not_taken: CondBrTarget::Fallthrough,
-                    kind: high(cc.without_equal()),
-                });
-                //
-                insts.push(Inst::CondBr {
-                    taken: not_taken,
-                    not_taken: CondBrTarget::Fallthrough,
-                    kind: high(IntCC::NotEqual),
-                });
-                insts.push(Inst::CondBr {
-                    taken,
-                    not_taken,
-                    kind: low(cc.unsigned()),
-                });
-            }
-        }
-        insts
-    }
-
     /// Returns Some(VState) if this insturction is expecting a specific vector state
     /// before emission.
     fn expected_vstate(&self) -> Option<&VState> {
@@ -358,7 +260,6 @@ impl Inst {
             | Inst::Atomic { .. }
             | Inst::Select { .. }
             | Inst::AtomicCas { .. }
-            | Inst::Icmp { .. }
             | Inst::FcvtToInt { .. }
             | Inst::RawData { .. }
             | Inst::AtomicStore { .. }
@@ -1776,29 +1677,6 @@ impl Inst {
             &Inst::EBreak => {
                 sink.put4(0x00100073);
             }
-            &Inst::Icmp { cc, rd, a, b, ty } => {
-                let label_true = sink.get_label();
-                let label_false = sink.get_label();
-                let label_end = sink.get_label();
-
-                Inst::lower_br_icmp(
-                    cc,
-                    a,
-                    b,
-                    CondBrTarget::Label(label_true),
-                    CondBrTarget::Label(label_false),
-                    ty,
-                )
-                .into_iter()
-                .for_each(|i| i.emit(&[], sink, emit_info, state));
-
-                sink.bind_label(label_true, &mut state.ctrl_plane);
-                Inst::load_imm12(rd, Imm12::ONE).emit(&[], sink, emit_info, state);
-                Inst::gen_jump(label_end).emit(&[], sink, emit_info, state);
-                sink.bind_label(label_false, &mut state.ctrl_plane);
-                Inst::load_imm12(rd, Imm12::ZERO).emit(&[], sink, emit_info, state);
-                sink.bind_label(label_end, &mut state.ctrl_plane);
-            }
             &Inst::AtomicCas {
                 offset,
                 t0,
@@ -2008,22 +1886,23 @@ impl Inst {
                         }
                         .iter()
                         .for_each(|i| i.emit(&[], sink, emit_info, state));
-                        Inst::lower_br_icmp(
-                            match op {
-                                crate::ir::AtomicRmwOp::Umin => IntCC::UnsignedLessThan,
-                                crate::ir::AtomicRmwOp::Umax => IntCC::UnsignedGreaterThan,
-                                crate::ir::AtomicRmwOp::Smin => IntCC::SignedLessThan,
-                                crate::ir::AtomicRmwOp::Smax => IntCC::SignedGreaterThan,
-                                _ => unreachable!(),
+
+                        Inst::CondBr {
+                            taken: CondBrTarget::Label(label_select_dst),
+                            not_taken: CondBrTarget::Fallthrough,
+                            kind: IntegerCompare {
+                                kind: match op {
+                                    crate::ir::AtomicRmwOp::Umin => IntCC::UnsignedLessThan,
+                                    crate::ir::AtomicRmwOp::Umax => IntCC::UnsignedGreaterThan,
+                                    crate::ir::AtomicRmwOp::Smin => IntCC::SignedLessThan,
+                                    crate::ir::AtomicRmwOp::Smax => IntCC::SignedGreaterThan,
+                                    _ => unreachable!(),
+                                },
+                                rs1: dst.to_reg(),
+                                rs2: x,
                             },
-                            ValueRegs::one(dst.to_reg()),
-                            ValueRegs::one(x),
-                            CondBrTarget::Label(label_select_dst),
-                            CondBrTarget::Fallthrough,
-                            ty,
-                        )
-                        .iter()
-                        .for_each(|i| i.emit(&[], sink, emit_info, state));
+                        }
+                        .emit(&[], sink, emit_info, state);
                         // here we select x.
                         Inst::gen_move(t0, x, I64).emit(&[], sink, emit_info, state);
                         Inst::gen_jump(label_select_done).emit(&[], sink, emit_info, state);
@@ -3471,20 +3350,6 @@ impl Inst {
 
             Inst::EBreak => self,
 
-            Inst::Icmp {
-                cc,
-                rd,
-                ref a,
-                ref b,
-                ty,
-            } => Inst::Icmp {
-                cc,
-                a: alloc_value_regs(a, allocs),
-                b: alloc_value_regs(b, allocs),
-                rd: allocs.next_writable(rd),
-                ty,
-            },
-
             Inst::AtomicCas {
                 offset,
                 t0,
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index 12d00c319..f291e47fc 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -557,12 +557,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             collector.reg_early_def(dst);
         }
 
-        &Inst::Icmp { rd, a, b, .. } => {
-            collector.reg_uses(a.regs());
-            collector.reg_uses(b.regs());
-            collector.reg_def(rd);
-        }
-
         &Inst::FcvtToInt { rd, rs, tmp, .. } => {
             collector.reg_use(rs);
             collector.reg_early_def(tmp);
@@ -1266,12 +1260,6 @@ impl Inst {
                     ty, dst, e, v, addr, t0, offset,
                 )
             }
-            &Inst::Icmp { cc, rd, a, b, ty } => {
-                let a = format_regs(a.regs(), allocs);
-                let b = format_regs(b.regs(), allocs);
-                let rd = format_reg(rd.to_reg(), allocs);
-                format!("{} {},{},{}##ty={}", cc.to_static_str(), rd, a, b, ty)
-            }
             &Inst::BrTable {
                 index,
                 tmp1,
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index 5106ee4fa..bb120d894 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -1483,7 +1483,7 @@
 ;; and selecting based on that result.
 (rule 0 (lower (has_type (ty_scalar_float ty) (fmin x y)))
   (let (;; Check if both inputs are not nan.
-        (is_ordered FCmp (emit_fcmp (FloatCC.Ordered) ty x y))
+        (is_ordered FloatCompare (fcmp_to_float_compare (FloatCC.Ordered) ty x y))
         ;; `fadd` returns a nan if any of the inputs is a NaN.
         (nan FReg (rv_fadd ty x y))
         (min FReg (rv_fmin ty x y)))
@@ -1509,7 +1509,7 @@
 ;; and selecting based on that result.
 (rule 0 (lower (has_type (ty_scalar_float ty) (fmax x y)))
   (let (;; Check if both inputs are not nan.
-        (is_ordered FCmp (emit_fcmp (FloatCC.Ordered) ty x y))
+        (is_ordered FloatCompare (fcmp_to_float_compare (FloatCC.Ordered) ty x y))
         ;; `fadd` returns a NaN if any of the inputs is a NaN.
         (nan FReg (rv_fadd ty x y))
         (max FReg (rv_fmax ty x y)))
@@ -1548,16 +1548,16 @@
 
 ;;;;;  Rules for `select`;;;;;;;;;
 (rule 0 (lower (has_type (ty_int_ref_scalar_64 _) (select c x y)))
-  (gen_select_xreg (lower_int_compare c) x y))
+  (gen_select_xreg (is_nonzero_cmp c) x y))
 
 (rule 1 (lower (has_type $I128 (select c x y)))
-  (gen_select_regs (lower_int_compare c) x y))
+  (gen_select_regs (is_nonzero_cmp c) x y))
 
 (rule 2 (lower (has_type (ty_vec_fits_in_register _) (select c x y)))
-  (gen_select_vreg (lower_int_compare c) x y))
+  (gen_select_vreg (is_nonzero_cmp c) x y))
 
 (rule 3 (lower (has_type (ty_scalar_float _) (select c x y)))
-  (gen_select_freg (lower_int_compare c) x y))
+  (gen_select_freg (is_nonzero_cmp c) x y))
 
 ;;;;;  Rules for `bitselect`;;;;;;;;;
 
@@ -1625,7 +1625,7 @@
     (gen_select_xreg (cmp_gt x y) x y)))
 
 (rule 1 (lower (has_type $I128 (smax x y)))
-  (gen_select_regs (cmp_nez (gen_icmp (IntCC.SignedGreaterThan) x y $I128)) x y))
+  (gen_select_regs (icmp_to_int_compare (IntCC.SignedGreaterThan) x y) x y))
 
 (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (smax x y)))
   (rv_vmax_vv x y (unmasked) ty))
@@ -1644,7 +1644,7 @@
     (gen_select_xreg (cmp_lt x y) x y)))
 
 (rule 1 (lower (has_type $I128 (smin x y)))
-  (gen_select_regs (cmp_nez (gen_icmp (IntCC.SignedLessThan) x y $I128)) x y))
+  (gen_select_regs (icmp_to_int_compare (IntCC.SignedLessThan) x y) x y))
 
 (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (smin x y)))
   (rv_vmin_vv x y (unmasked) ty))
@@ -1663,7 +1663,7 @@
     (gen_select_xreg (cmp_gtu x y) x y)))
 
 (rule 1 (lower (has_type $I128 (umax x y)))
-  (gen_select_regs (cmp_nez (gen_icmp (IntCC.UnsignedGreaterThan) x y $I128)) x y))
+  (gen_select_regs (icmp_to_int_compare (IntCC.UnsignedGreaterThan) x y) x y))
 
 (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (umax x y)))
   (rv_vmaxu_vv x y (unmasked) ty))
@@ -1682,7 +1682,7 @@
     (gen_select_xreg (cmp_ltu x y) x y)))
 
 (rule 1 (lower (has_type $I128 (umin x y)))
-  (gen_select_regs (cmp_nez (gen_icmp (IntCC.UnsignedLessThan) x y $I128)) x y))
+  (gen_select_regs (icmp_to_int_compare (IntCC.UnsignedLessThan) x y) x y))
 
 (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (umin x y)))
   (rv_vminu_vv x y (unmasked) ty))
@@ -1827,35 +1827,154 @@
 
 ;;;;;  Rules for `icmp`;;;;;;;;;
 
-(decl gen_icmp (IntCC ValueRegs ValueRegs Type) XReg)
-(rule
-  (gen_icmp cc x y ty)
-  (let
-    ((result WritableXReg (temp_writable_xreg))
-      (_ Unit (emit (MInst.Icmp cc result x y ty))))
-    result))
-
-(rule 0 (lower (icmp cc x @ (value_type (ty_int ty)) y))
-  (gen_icmp cc (zext x) (zext y) ty))
-
-(rule 1 (lower (icmp cc x @ (value_type (ty_int ty)) y))
-  (if (signed_cond_code cc))
-  (gen_icmp cc (sext x) (sext y) ty))
-
-(rule 2 (lower (icmp cc x @ (value_type $I128) y))
-  (gen_icmp cc x y $I128))
-
-(rule 3 (lower (icmp cc x @ (value_type (ty_vec_fits_in_register ty)) y))
+;; 8-64 bit comparisons. Mostly fall back onto `IntegerCompare` and then
+;; materializing that, but before that happens try to match some
+;; constant-related patterns
+
+(rule 0 (lower (icmp cc x @ (value_type (fits_in_64 ty)) y))
+  (lower_icmp cc x y))
+
+(decl lower_icmp (IntCC Value Value) XReg)
+(rule 0 (lower_icmp cc x y)
+  (lower_int_compare (icmp_to_int_compare cc x y)))
+
+;; a == $imm => seqz(xori(..))
+(rule 1 (lower_icmp (IntCC.Equal) x y)
+  (if-let (i64_from_iconst (i64_nonzero (imm12_from_i64 imm))) y)
+  (rv_seqz (rv_xori (sext x) imm)))
+(rule 2 (lower_icmp (IntCC.Equal) x y)
+  (if-let (i64_from_iconst (i64_nonzero (imm12_from_i64 imm))) x)
+  (rv_seqz (rv_xori (sext y) imm)))
+
+;; a != $imm => snez(xori(..))
+(rule 1 (lower_icmp (IntCC.NotEqual) x y)
+  (if-let (i64_from_iconst (i64_nonzero (imm12_from_i64 imm))) y)
+  (rv_snez (rv_xori (sext x) imm)))
+(rule 2 (lower_icmp (IntCC.NotEqual) x y)
+  (if-let (i64_from_iconst (i64_nonzero (imm12_from_i64 imm))) x)
+  (rv_snez (rv_xori (sext y) imm)))
+
+;; a < $imm => slti(..)
+(rule 1 (lower_icmp (IntCC.SignedLessThan) x y)
+  (if-let (i64_from_iconst (i64_nonzero (imm12_from_i64 imm))) y)
+  (rv_slti (sext x) imm))
+(rule 1 (lower_icmp (IntCC.SignedGreaterThan) x y)
+  (if-let (i64_from_iconst (i64_nonzero (imm12_from_i64 imm))) x)
+  (rv_slti (sext y) imm))
+(rule 1 (lower_icmp (IntCC.UnsignedLessThan) x y)
+  (if-let (u64_from_iconst (u64_nonzero (imm12_from_u64 imm))) y)
+  (rv_sltiu (zext x) imm))
+(rule 1 (lower_icmp (IntCC.UnsignedGreaterThan) x y)
+  (if-let (u64_from_iconst (u64_nonzero (imm12_from_u64 imm))) x)
+  (rv_sltiu (zext y) imm))
+
+;; a >= $imm => !(a < $imm)
+(rule 2 (lower_icmp cc @ (IntCC.SignedGreaterThanOrEqual) x y)
+  (if-let (i64_from_iconst (i64_nonzero (imm12_from_i64 _))) y)
+  (rv_xori (lower_icmp (intcc_complement cc) x y) (imm12_const 1)))
+(rule 2 (lower_icmp cc @ (IntCC.UnsignedGreaterThanOrEqual) x y)
+  (if-let (u64_from_iconst (u64_nonzero (imm12_from_u64 _))) y)
+  (rv_xori (lower_icmp (intcc_complement cc) x y) (imm12_const 1)))
+
+;; Materializes an `IntegerCompare` bundle directly into an `XReg` with a 0
+;; or 1 value.
+(decl lower_int_compare (IntegerCompare) XReg)
+
+;; x == y => x ^ y == 0
+(rule 0 (lower_int_compare (int_compare_decompose (IntCC.Equal) x y))
+  (rv_seqz (rv_xor x y)))
+(rule 1 (lower_int_compare (int_compare_decompose (IntCC.Equal) x (zero_reg)))
+  (rv_seqz x))
+(rule 2 (lower_int_compare (int_compare_decompose (IntCC.Equal) (zero_reg) y))
+  (rv_seqz y))
+;; x != y => x ^ y != 0
+(rule 0 (lower_int_compare (int_compare_decompose (IntCC.NotEqual) x y))
+  (rv_snez (rv_xor x y)))
+(rule 1 (lower_int_compare (int_compare_decompose (IntCC.NotEqual) x (zero_reg)))
+  (rv_snez x))
+(rule 2 (lower_int_compare (int_compare_decompose (IntCC.NotEqual) (zero_reg) x))
+  (rv_snez x))
+;; x < y => x < y
+(rule (lower_int_compare (int_compare_decompose (IntCC.SignedLessThan) x y))
+  (rv_slt x y))
+(rule (lower_int_compare (int_compare_decompose (IntCC.UnsignedLessThan) x y))
+  (rv_sltu x y))
+;; x > y => y < x
+(rule (lower_int_compare (int_compare_decompose (IntCC.SignedGreaterThan) x y))
+  (rv_slt y x))
+(rule (lower_int_compare (int_compare_decompose (IntCC.UnsignedGreaterThan) x y))
+  (rv_sltu y x))
+;; x <= y => !(y < x)
+(rule (lower_int_compare (int_compare_decompose (IntCC.SignedLessThanOrEqual) x y))
+  (rv_xori (rv_slt y x) (imm12_const 1)))
+(rule (lower_int_compare (int_compare_decompose (IntCC.UnsignedLessThanOrEqual) x y))
+  (rv_xori (rv_sltu y x) (imm12_const 1)))
+;; x >= y => !(x < y)
+(rule (lower_int_compare (int_compare_decompose (IntCC.SignedGreaterThanOrEqual) x y))
+  (rv_xori (rv_slt x y) (imm12_const 1)))
+(rule (lower_int_compare (int_compare_decompose (IntCC.UnsignedGreaterThanOrEqual) x y))
+  (rv_xori (rv_sltu x y) (imm12_const 1)))
+
+;; 128-bit comparisons.
+;;
+;; Currently only `==`, `!=`, and `<` are implemented, and everything else
+;; delegates to one of those.
+
+(rule 20 (lower (icmp cc x @ (value_type $I128) y))
+  (lower_icmp_i128 cc x y))
+
+(decl lower_icmp_i128 (IntCC ValueRegs ValueRegs) XReg)
+(rule 0 (lower_icmp_i128 (IntCC.Equal) x y)
+  (let ((lo XReg (rv_xor (value_regs_get x 0) (value_regs_get y 0)))
+        (hi XReg (rv_xor (value_regs_get x 1) (value_regs_get y 1))))
+    (rv_seqz (rv_or lo hi))))
+(rule 0 (lower_icmp_i128 (IntCC.NotEqual) x y)
+  (let ((lo XReg (rv_xor (value_regs_get x 0) (value_regs_get y 0)))
+        (hi XReg (rv_xor (value_regs_get x 1) (value_regs_get y 1))))
+    (rv_snez (rv_or lo hi))))
+
+;; swap args for `>` to use `<` instead
+(rule 0 (lower_icmp_i128 cc @ (IntCC.SignedGreaterThan) x y)
+  (lower_icmp_i128 (intcc_swap_args cc) y x))
+(rule 0 (lower_icmp_i128 cc @ (IntCC.UnsignedGreaterThan) x y)
+  (lower_icmp_i128 (intcc_swap_args cc) y x))
+
+;; complement `=`-related conditions to get ones that don't use `=`.
+(rule 0 (lower_icmp_i128 cc @ (IntCC.SignedLessThanOrEqual) x y)
+  (rv_xori (lower_icmp_i128 (intcc_complement cc) x y) (imm12_const 1)))
+(rule 0 (lower_icmp_i128 cc @ (IntCC.SignedGreaterThanOrEqual) x y)
+  (rv_xori (lower_icmp_i128 (intcc_complement cc) x y) (imm12_const 1)))
+(rule 0 (lower_icmp_i128 cc @ (IntCC.UnsignedLessThanOrEqual) x y)
+  (rv_xori (lower_icmp_i128 (intcc_complement cc) x y) (imm12_const 1)))
+(rule 0 (lower_icmp_i128 cc @ (IntCC.UnsignedGreaterThanOrEqual) x y)
+  (rv_xori (lower_icmp_i128 (intcc_complement cc) x y) (imm12_const 1)))
+
+;; Compare both the bottom and upper halves of the 128-bit values. If
+;; the top half is equal use the bottom comparison, otherwise use the upper
+;; comparison. Note that the lower comparison is always unsigned since if it's
+;; used the top halves are all zeros and the semantic values are positive.
+(rule 1 (lower_icmp_i128 cc x y)
+  (if-let (IntCC.UnsignedLessThan) (intcc_unsigned cc))
+  (let ((x_lo Reg (value_regs_get x 0))
+        (x_hi Reg (value_regs_get x 1))
+        (y_lo Reg (value_regs_get y 0))
+        (y_hi Reg (value_regs_get y 1))
+        (top_cmp XReg (lower_int_compare (int_compare cc x_hi y_hi)))
+        (bottom_cmp XReg (rv_sltu x_lo y_lo)))
+    (gen_select_xreg (cmp_eqz (rv_xor x_hi y_hi)) bottom_cmp top_cmp)))
+
+;; vector icmp comparisons
+
+(rule 30 (lower (icmp cc x @ (value_type (ty_vec_fits_in_register ty)) y))
   (gen_expand_mask ty (gen_icmp_mask ty cc x y)))
 
-
 ;;;;;  Rules for `fcmp`;;;;;;;;;
 (rule 0 (lower (fcmp cc x @ (value_type (ty_scalar_float ty)) y))
-  (lower_fcmp (emit_fcmp cc ty x y)))
+  (lower_float_compare (fcmp_to_float_compare cc ty x y)))
 
-(decl lower_fcmp (FCmp) XReg)
-(rule (lower_fcmp (FCmp.One r)) r)
-(rule (lower_fcmp (FCmp.Zero r)) (rv_seqz r))
+(decl lower_float_compare (FloatCompare) XReg)
+(rule (lower_float_compare (FloatCompare.One r)) r)
+(rule (lower_float_compare (FloatCompare.Zero r)) (rv_seqz r))
 
 (rule 1 (lower (fcmp cc x @ (value_type (ty_vec_fits_in_register ty)) y))
   (gen_expand_mask ty (gen_fcmp_mask ty cc x y)))
diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
index b106cd77f..d4d449d0e 100644
--- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
@@ -181,14 +181,6 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
             link_reg()
         }
     }
-    fn int_zero_reg(&mut self, ty: Type) -> ValueRegs {
-        assert!(ty.is_int(), "{:?}", ty);
-        if ty.bits() == 128 {
-            ValueRegs::two(self.zero_reg(), self.zero_reg())
-        } else {
-            ValueRegs::one(self.zero_reg())
-        }
-    }
 
     fn label_to_br_target(&mut self, label: MachLabel) -> CondBrTarget {
         CondBrTarget::Label(label)
@@ -292,8 +284,15 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
         writable_zero_reg()
     }
     #[inline]
-    fn zero_reg(&mut self) -> Reg {
-        zero_reg()
+    fn zero_reg(&mut self) -> XReg {
+        XReg::new(zero_reg()).unwrap()
+    }
+    fn is_zero_reg(&mut self, reg: XReg) -> Option<()> {
+        if reg == self.zero_reg() {
+            Some(())
+        } else {
+            None
+        }
     }
     #[inline]
     fn imm_from_bits(&mut self, val: u64) -> Imm12 {
@@ -326,6 +325,9 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
     fn imm12_const_add(&mut self, val: i32, add: i32) -> Imm12 {
         Imm12::maybe_from_i64((val + add) as i64).unwrap()
     }
+    fn imm12_add(&mut self, val: Imm12, add: i32) -> Option<Imm12> {
+        Imm12::maybe_from_i64((i32::from(val.as_i16()) + add).into())
+    }
 
     //
     fn gen_shamt(&mut self, ty: Type, shamt: XReg) -> ValueRegs {
diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle
index f6a5bde75..54b3649da 100644
--- a/cranelift/codegen/src/isa/s390x/inst.isle
+++ b/cranelift/codegen/src/isa/s390x/inst.isle
@@ -1539,11 +1539,6 @@
 (decl pure partial i64_nonequal (i64 i64) i64)
 (extern constructor i64_nonequal i64_nonequal)
 
-(decl pure partial i64_nonzero (i64) i64)
-(rule (i64_nonzero x)
-      (if (i64_nonequal x 0))
-      x)
-
 (decl pure partial i64_not_neg1 (i64) i64)
 (rule (i64_not_neg1 x)
       (if (i64_nonequal x -1))
diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs
index 4353ae388..bd4db5b19 100644
--- a/cranelift/codegen/src/isle_prelude.rs
+++ b/cranelift/codegen/src/isle_prelude.rs
@@ -164,6 +164,10 @@ macro_rules! isle_common_prelude_methods {
             0 == value
         }
 
+        fn i64_is_zero(&mut self, value: i64) -> bool {
+            0 == value
+        }
+
         #[inline]
         fn u64_is_odd(&mut self, x: u64) -> bool {
             x & 1 == 1
diff --git a/cranelift/codegen/src/prelude.isle b/cranelift/codegen/src/prelude.isle
index 5f389dbc9..997af7a84 100644
--- a/cranelift/codegen/src/prelude.isle
+++ b/cranelift/codegen/src/prelude.isle
@@ -213,12 +213,18 @@
 (decl u64_is_zero (bool) u64)
 (extern extractor infallible u64_is_zero u64_is_zero)
 
+(decl i64_is_zero (bool) i64)
+(extern extractor infallible i64_is_zero i64_is_zero)
+
 (decl u64_zero () u64)
 (extractor (u64_zero) (u64_is_zero $true))
 
 (decl u64_nonzero (u64) u64)
 (extractor (u64_nonzero x) (and (u64_is_zero $false) x))
 
+(decl i64_nonzero (i64) i64)
+(extractor (i64_nonzero x) (and (i64_is_zero $false) x))
+
 (decl pure u64_is_odd (u64) bool)
 (extern constructor u64_is_odd u64_is_odd)
 
diff --git a/cranelift/fuzzgen/src/function_generator.rs b/cranelift/fuzzgen/src/function_generator.rs
index 752065b47..4b0e7a071 100644
--- a/cranelift/fuzzgen/src/function_generator.rs
+++ b/cranelift/fuzzgen/src/function_generator.rs
@@ -131,7 +131,14 @@ fn insert_stack_load(
 ) -> Result<()> {
     let typevar = rets[0];
     let type_size = typevar.bytes();
-    let (slot, slot_size) = fgen.stack_slot_with_size(type_size)?;
+    let (slot, slot_size, category) = fgen.stack_slot_with_size(type_size)?;
+
+    // `stack_load` doesen't support setting MemFlags, and it does not set any
+    // alias analysis bits, so we can only emit it for `Other` slots.
+    if category != AACategory::Other {
+        return Err(arbitrary::Error::IncorrectFormat.into());
+    }
+
     let offset = fgen.u.int_in_range(0..=(slot_size - type_size))? as i32;
 
     let val = builder.ins().stack_load(typevar, slot, offset);
@@ -150,7 +157,15 @@ fn insert_stack_store(
 ) -> Result<()> {
     let typevar = args[0];
     let type_size = typevar.bytes();
-    let (slot, slot_size) = fgen.stack_slot_with_size(type_size)?;
+
+    let (slot, slot_size, category) = fgen.stack_slot_with_size(type_size)?;
+
+    // `stack_store` doesen't support setting MemFlags, and it does not set any
+    // alias analysis bits, so we can only emit it for `Other` slots.
+    if category != AACategory::Other {
+        return Err(arbitrary::Error::IncorrectFormat.into());
+    }
+
     let offset = fgen.u.int_in_range(0..=(slot_size - type_size))? as i32;
 
     let arg0 = fgen.get_variable_of_type(typevar)?;
@@ -1118,6 +1133,45 @@ enum BlockTerminatorKind {
     TailCallIndirect,
 }
 
+/// Alias Analysis Category
+///
+/// Our alias analysis pass supports 4 categories of accesses to distinguish
+/// different regions. The "Other" region is the general case, and is the default
+/// Although they have highly suggestive names there is no difference between any
+/// of the categories.
+///
+/// We assign each stack slot a category when we first generate them, and then
+/// ensure that all accesses to that stack slot are correctly tagged. We already
+/// ensure that memory accesses never cross stack slots, so there is no risk
+/// of a memory access being tagged with the wrong category.
+#[derive(Debug, PartialEq, Clone, Copy)]
+enum AACategory {
+    Other,
+    Heap,
+    Table,
+    VmCtx,
+}
+
+impl AACategory {
+    pub fn all() -> &'static [Self] {
+        &[
+            AACategory::Other,
+            AACategory::Heap,
+            AACategory::Table,
+            AACategory::VmCtx,
+        ]
+    }
+
+    pub fn update_memflags(&self, flags: &mut MemFlags) {
+        match self {
+            AACategory::Other => {}
+            AACategory::Heap => flags.set_heap(),
+            AACategory::Table => flags.set_table(),
+            AACategory::VmCtx => flags.set_vmctx(),
+        }
+    }
+}
+
 #[derive(Default)]
 struct Resources {
     vars: HashMap<Type, Vec<Variable>>,
@@ -1125,7 +1179,10 @@ struct Resources {
     blocks_without_params: Vec<Block>,
     block_terminators: Vec<BlockTerminator>,
     func_refs: Vec<(Signature, SigRef, FuncRef)>,
-    stack_slots: Vec<(StackSlot, StackSize)>,
+    /// This field is required to be sorted by stack slot size at all times.
+    /// We use this invariant when searching for stack slots with a given size.
+    /// See [FunctionGenerator::stack_slot_with_size]
+    stack_slots: Vec<(StackSlot, StackSize, AACategory)>,
     usercalls: Vec<(UserExternalName, Signature)>,
     libcalls: Vec<LibCall>,
 }
@@ -1208,11 +1265,11 @@ where
     }
 
     /// Finds a stack slot with size of at least n bytes
-    fn stack_slot_with_size(&mut self, n: u32) -> Result<(StackSlot, StackSize)> {
+    fn stack_slot_with_size(&mut self, n: u32) -> Result<(StackSlot, StackSize, AACategory)> {
         let first = self
             .resources
             .stack_slots
-            .partition_point(|&(_slot, size)| size < n);
+            .partition_point(|&(_slot, size, _category)| size < n);
         Ok(*self.u.choose(&self.resources.stack_slots[first..])?)
     }
 
@@ -1233,11 +1290,11 @@ where
         builder: &mut FunctionBuilder,
         min_size: u32,
         aligned: bool,
-    ) -> Result<(Value, u32)> {
+    ) -> Result<(Value, u32, AACategory)> {
         // TODO: Currently our only source of addresses is stack_addr, but we
         // should add global_value, symbol_value eventually
-        let (addr, available_size) = {
-            let (ss, slot_size) = self.stack_slot_with_size(min_size)?;
+        let (addr, available_size, category) = {
+            let (ss, slot_size, category) = self.stack_slot_with_size(min_size)?;
 
             // stack_slot_with_size guarantees that slot_size >= min_size
             let max_offset = slot_size - min_size;
@@ -1249,7 +1306,7 @@ where
 
             let base_addr = builder.ins().stack_addr(I64, ss, offset as i32);
             let available_size = slot_size.saturating_sub(offset);
-            (base_addr, available_size)
+            (base_addr, available_size, category)
         };
 
         // TODO: Insert a bunch of amode opcodes here to modify the address!
@@ -1257,7 +1314,7 @@ where
         // Now that we have an address and a size, we just choose a random offset to return to the
         // caller. Preserving min_size bytes.
         let max_offset = available_size.saturating_sub(min_size);
-        Ok((addr, max_offset))
+        Ok((addr, max_offset, category))
     }
 
     // Generates an address and memflags for a load or store.
@@ -1297,7 +1354,11 @@ where
             flags.set_notrap();
         }
 
-        let (address, max_offset) = self.generate_load_store_address(builder, min_size, aligned)?;
+        let (address, max_offset, category) =
+            self.generate_load_store_address(builder, min_size, aligned)?;
+
+        // Set the Alias Analysis bits on the memflags
+        category.update_memflags(&mut flags);
 
         // Pick an offset to pass into the load/store.
         let offset = if aligned {
@@ -1533,12 +1594,16 @@ where
             let bytes = self.param(&self.config.static_stack_slot_size)? as u32;
             let ss_data = StackSlotData::new(StackSlotKind::ExplicitSlot, bytes);
             let slot = builder.create_sized_stack_slot(ss_data);
-            self.resources.stack_slots.push((slot, bytes));
+
+            // Generate one Alias Analysis Category for each slot
+            let category = *self.u.choose(AACategory::all())?;
+
+            self.resources.stack_slots.push((slot, bytes, category));
         }
 
         self.resources
             .stack_slots
-            .sort_unstable_by_key(|&(_slot, bytes)| bytes);
+            .sort_unstable_by_key(|&(_slot, bytes, _category)| bytes);
 
         Ok(())
     }
@@ -1551,7 +1616,7 @@ where
         let i64_zero = builder.ins().iconst(I64, 0);
         let i128_zero = builder.ins().uextend(I128, i64_zero);
 
-        for &(slot, init_size) in self.resources.stack_slots.iter() {
+        for &(slot, init_size, category) in self.resources.stack_slots.iter() {
             let mut size = init_size;
 
             // Insert the largest available store for the remaining size.
@@ -1564,7 +1629,16 @@ where
                     sz if sz / 2 > 0 => (i16_zero, 2),
                     _ => (i8_zero, 1),
                 };
-                builder.ins().stack_store(val, slot, offset);
+                let addr = builder.ins().stack_addr(I64, slot, offset);
+
+                // Each stack slot has an associated category, that means we have to set the
+                // correct memflags for it. So we can't use `stack_store` directly.
+                let mut flags = MemFlags::new();
+                flags.set_notrap();
+                category.update_memflags(&mut flags);
+
+                builder.ins().store(flags, val, addr, 0);
+
                 size -= filled;
             }
         }
diff --git a/crates/cli-flags/Cargo.toml b/crates/cli-flags/Cargo.toml
index e15b4d14f..725c76267 100644
--- a/crates/cli-flags/Cargo.toml
+++ b/crates/cli-flags/Cargo.toml
@@ -12,7 +12,7 @@ edition.workspace = true
 anyhow = { workspace = true }
 clap = { workspace = true }
 file-per-thread-logger = { workspace = true }
-pretty_env_logger = { workspace = true }
+tracing-subscriber = { workspace = true }
 rayon = "1.5.0"
 wasmtime = { workspace = true }
 humantime = "2.0.0"
diff --git a/crates/cli-flags/src/lib.rs b/crates/cli-flags/src/lib.rs
index db5ba3abc..13efde1dc 100644
--- a/crates/cli-flags/src/lib.rs
+++ b/crates/cli-flags/src/lib.rs
@@ -5,7 +5,9 @@
 
 use anyhow::Result;
 use clap::Parser;
+use std::io::IsTerminal;
 use std::time::Duration;
+use tracing_subscriber::{EnvFilter, FmtSubscriber};
 use wasmtime::Config;
 
 pub mod opt;
@@ -328,7 +330,13 @@ impl CommonOptions {
             let prefix = "wasmtime.dbg.";
             init_file_per_thread_logger(prefix);
         } else {
-            pretty_env_logger::init();
+            let mut b = FmtSubscriber::builder()
+                .with_writer(std::io::stderr)
+                .with_env_filter(EnvFilter::from_env("WASMTIME_LOG"));
+            if std::io::stderr().is_terminal() {
+                b = b.with_ansi(true);
+            }
+            b.init();
         }
     }
 
diff --git a/src/bin/wasmtime.rs b/src/bin/wasmtime.rs
index 6e289a74b..46868b3ac 100644
--- a/src/bin/wasmtime.rs
+++ b/src/bin/wasmtime.rs
@@ -82,16 +82,6 @@ impl Wasmtime {
 }
 
 fn main() -> Result<()> {
-    use std::io::IsTerminal;
-    use tracing_subscriber::{EnvFilter, FmtSubscriber};
-
-    let mut b = FmtSubscriber::builder()
-        .with_writer(std::io::stderr)
-        .with_env_filter(EnvFilter::from_env("WASMTIME_LOG"));
-    if std::io::stderr().is_terminal() {
-        b = b.with_ansi(true);
-    }
-    b.init();
     Wasmtime::parse().execute()
 }
 


Test patch:
diff --git a/cranelift/filetests/filetests/isa/riscv64/brif.clif b/cranelift/filetests/filetests/isa/riscv64/brif.clif
index 8f61a5982..aee445604 100644
--- a/cranelift/filetests/filetests/isa/riscv64/brif.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/brif.clif
@@ -234,10 +234,10 @@ block2:
 ; block0:
 ;   mv a3,a1
 ;   slli a5,a0,48
-;   srli a1,a5,48
+;   srai a1,a5,48
 ;   mv a5,a3
 ;   slli a3,a5,48
-;   srli a5,a3,48
+;   srai a5,a3,48
 ;   bne a1,a5,taken(label2),not_taken(label1)
 ; block1:
 ;   li a0,0
@@ -250,10 +250,10 @@ block2:
 ; block0: ; offset 0x0
 ;   mv a3, a1
 ;   slli a5, a0, 0x30
-;   srli a1, a5, 0x30
+;   srai a1, a5, 0x30
 ;   mv a5, a3
 ;   slli a3, a5, 0x30
-;   srli a5, a3, 0x30
+;   srai a5, a3, 0x30
 ;   bne a1, a5, 0xc
 ; block1: ; offset 0x1c
 ;   mv a0, zero
@@ -350,7 +350,10 @@ block2:
 
 ; VCode:
 ; block0:
-;   sgt a1,[a0,a1],[a2,a3]##ty=i128
+;   slt a5,a3,a1
+;   sltu a4,a2,a0
+;   xor a0,a3,a1
+;   select a1,a4,a5##condition=(a0 eq zero)
 ;   bne a1,zero,taken(label2),not_taken(label1)
 ; block1:
 ;   li a0,0
@@ -361,17 +364,18 @@ block2:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a1, zero, 1
+;   slt a5, a3, a1
+;   sltu a4, a2, a0
+;   xor a0, a3, a1
+;   bnez a0, 0xc
+;   mv a1, a4
 ;   j 8
-;   mv a1, zero
+;   mv a1, a5
 ;   bnez a1, 0xc
-; block1: ; offset 0x1c
+; block1: ; offset 0x20
 ;   mv a0, zero
 ;   ret
-; block2: ; offset 0x24
+; block2: ; offset 0x28
 ;   addi a0, zero, 1
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/condbr.clif b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
index c9c93c201..9ac16eec1 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condbr.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
@@ -10,15 +10,14 @@ block0(v0: i64, v1: i64):
 
 ; VCode:
 ; block0:
-;   eq a0,a0,a1##ty=i64
+;   xor a3,a0,a1
+;   seqz a0,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a0, a1, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a3, a0, a1
+;   seqz a0, a3
 ;   ret
 
 function %icmp_eq_i128(i128, i128) -> i8 {
@@ -29,16 +28,18 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   eq a0,[a0,a1],[a2,a3]##ty=i128
+;   xor a5,a0,a2
+;   xor a1,a1,a3
+;   or a3,a5,a1
+;   seqz a0,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 0x10
-;   bne a0, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a5, a0, a2
+;   xor a1, a1, a3
+;   or a3, a5, a1
+;   seqz a0, a3
 ;   ret
 
 function %icmp_ne_i128(i128, i128) -> i8 {
@@ -49,16 +50,18 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ne a0,[a0,a1],[a2,a3]##ty=i128
+;   xor a5,a0,a2
+;   xor a1,a1,a3
+;   or a3,a5,a1
+;   sltu a0,zero,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 8
-;   beq a0, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a5, a0, a2
+;   xor a1, a1, a3
+;   or a3, a5, a1
+;   snez a0, a3
 ;   ret
 
 function %icmp_slt_i128(i128, i128) -> i8 {
@@ -69,17 +72,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   slt a0,[a0,a1],[a2,a3]##ty=i128
+;   slt a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a0,a2,a5##condition=(a3 eq zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a0, zero, 1
+;   slt a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 0xc
+;   mv a0, a2
 ;   j 8
-;   mv a0, zero
+;   mv a0, a5
 ;   ret
 
 function %icmp_ult_i128(i128, i128) -> i8 {
@@ -90,17 +97,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ult a0,[a0,a1],[a2,a3]##ty=i128
+;   sltu a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a0,a2,a5##condition=(a3 eq zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a0, zero, 1
+;   sltu a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 0xc
+;   mv a0, a2
 ;   j 8
-;   mv a0, zero
+;   mv a0, a5
 ;   ret
 
 function %icmp_sle_i128(i128, i128) -> i8 {
@@ -111,17 +122,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   sle a0,[a0,a1],[a2,a3]##ty=i128
+;   slt a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a0,a5,1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   slt a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a0, a5, 1
 ;   ret
 
 function %icmp_ule_i128(i128, i128) -> i8 {
@@ -132,17 +147,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ule a0,[a0,a1],[a2,a3]##ty=i128
+;   sltu a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a0,a5,1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   sltu a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a0, a5, 1
 ;   ret
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
@@ -153,17 +172,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   sgt a0,[a0,a1],[a2,a3]##ty=i128
+;   slt a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a0,a2,a5##condition=(a3 eq zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a0, zero, 1
+;   slt a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 0xc
+;   mv a0, a2
 ;   j 8
-;   mv a0, zero
+;   mv a0, a5
 ;   ret
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
@@ -174,17 +197,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ugt a0,[a0,a1],[a2,a3]##ty=i128
+;   sltu a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a0,a2,a5##condition=(a3 eq zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a0, zero, 1
+;   sltu a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 0xc
+;   mv a0, a2
 ;   j 8
-;   mv a0, zero
+;   mv a0, a5
 ;   ret
 
 function %icmp_sge_i128(i128, i128) -> i8 {
@@ -195,17 +222,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   sge a0,[a0,a1],[a2,a3]##ty=i128
+;   slt a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a0,a5,1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   slt a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a0, a5, 1
 ;   ret
 
 function %icmp_uge_i128(i128, i128) -> i8 {
@@ -216,17 +247,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   uge a0,[a0,a1],[a2,a3]##ty=i128
+;   sltu a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a0,a5,1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   sltu a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a0, a5, 1
 ;   ret
 
 function %f(i64, i64) -> i64 {
@@ -326,7 +361,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   eq a5,[a0,a1],[a2,a3]##ty=i128
+;   xor a5,a0,a2
+;   xor a1,a1,a3
+;   or a3,a5,a1
+;   seqz a5,a3
 ;   bne a5,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
@@ -337,12 +375,11 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 0x10
-;   bne a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-; block1: ; offset 0x14
+;   xor a5, a0, a2
+;   xor a1, a1, a3
+;   or a3, a5, a1
+;   seqz a5, a3
+; block1: ; offset 0x10
 ;   ret
 
 function %i128_bricmp_ne(i128, i128) {
@@ -356,7 +393,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   ne a5,[a0,a1],[a2,a3]##ty=i128
+;   xor a5,a0,a2
+;   xor a1,a1,a3
+;   or a3,a5,a1
+;   sltu a5,zero,a3
 ;   bne a5,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
@@ -367,12 +407,11 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 8
-;   beq a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-; block1: ; offset 0x14
+;   xor a5, a0, a2
+;   xor a1, a1, a3
+;   or a3, a5, a1
+;   snez a5, a3
+; block1: ; offset 0x10
 ;   ret
 
 function %i128_bricmp_slt(i128, i128) {
@@ -386,7 +425,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   slt a5,[a0,a1],[a2,a3]##ty=i128
+;   slt a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a5,a2,a5##condition=(a3 eq zero)
 ;   bne a5,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
@@ -397,13 +439,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-; block1: ; offset 0x18
+;   slt a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 8
+;   mv a5, a2
+; block1: ; offset 0x14
 ;   ret
 
 function %i128_bricmp_ult(i128, i128) {
@@ -417,7 +458,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   ult a5,[a0,a1],[a2,a3]##ty=i128
+;   sltu a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a5,a2,a5##condition=(a3 eq zero)
 ;   bne a5,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
@@ -428,13 +472,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-; block1: ; offset 0x18
+;   sltu a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 8
+;   mv a5, a2
+; block1: ; offset 0x14
 ;   ret
 
 function %i128_bricmp_sle(i128, i128) {
@@ -448,8 +491,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   sle a5,[a0,a1],[a2,a3]##ty=i128
-;   bne a5,zero,taken(label1),not_taken(label2)
+;   slt a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a1,a5,1
+;   bne a1,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -459,12 +506,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
+;   slt a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a1, a5, 1
 ; block1: ; offset 0x18
 ;   ret
 
@@ -479,8 +526,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   ule a5,[a0,a1],[a2,a3]##ty=i128
-;   bne a5,zero,taken(label1),not_taken(label2)
+;   sltu a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a1,a5,1
+;   bne a1,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -490,12 +541,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
+;   sltu a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a1, a5, 1
 ; block1: ; offset 0x18
 ;   ret
 
@@ -510,7 +561,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   sgt a5,[a0,a1],[a2,a3]##ty=i128
+;   slt a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a5,a2,a5##condition=(a3 eq zero)
 ;   bne a5,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
@@ -521,13 +575,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-; block1: ; offset 0x18
+;   slt a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 8
+;   mv a5, a2
+; block1: ; offset 0x14
 ;   ret
 
 function %i128_bricmp_ugt(i128, i128) {
@@ -541,7 +594,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   ugt a5,[a0,a1],[a2,a3]##ty=i128
+;   sltu a5,a3,a1
+;   sltu a2,a2,a0
+;   xor a3,a3,a1
+;   select a5,a2,a5##condition=(a3 eq zero)
 ;   bne a5,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
@@ -552,13 +608,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-; block1: ; offset 0x18
+;   sltu a5, a3, a1
+;   sltu a2, a2, a0
+;   xor a3, a3, a1
+;   bnez a3, 8
+;   mv a5, a2
+; block1: ; offset 0x14
 ;   ret
 
 function %i128_bricmp_sge(i128, i128) {
@@ -572,8 +627,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   sge a5,[a0,a1],[a2,a3]##ty=i128
-;   bne a5,zero,taken(label1),not_taken(label2)
+;   slt a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a1,a5,1
+;   bne a1,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -583,12 +642,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
+;   slt a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a1, a5, 1
 ; block1: ; offset 0x18
 ;   ret
 
@@ -603,8 +662,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   uge a5,[a0,a1],[a2,a3]##ty=i128
-;   bne a5,zero,taken(label1),not_taken(label2)
+;   sltu a5,a1,a3
+;   sltu a2,a0,a2
+;   xor a3,a1,a3
+;   select a5,a2,a5##condition=(a3 eq zero)
+;   xori a1,a5,1
+;   bne a1,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -614,12 +677,12 @@ block1:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
+;   sltu a5, a1, a3
+;   sltu a2, a0, a2
+;   xor a3, a1, a3
+;   bnez a3, 8
+;   mv a5, a2
+;   xori a1, a5, 1
 ; block1: ; offset 0x18
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/condops.clif b/cranelift/filetests/filetests/isa/riscv64/condops.clif
index 6dbba5087..0866873b2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condops.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condops.clif
@@ -38,21 +38,18 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   li a5,42
-;   andi a3,a0,255
-;   andi a5,a5,255
-;   eq a0,a3,a5##ty=i8
+;   slli a2,a0,56
+;   srai a4,a2,56
+;   xori a0,a4,42
+;   seqz a0,a0
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a5, zero, 0x2a
-;   andi a3, a0, 0xff
-;   andi a5, a5, 0xff
-;   bne a3, a5, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   slli a2, a0, 0x38
+;   srai a4, a2, 0x38
+;   xori a0, a4, 0x2a
+;   seqz a0, a0
 ;   ret
 
 function %h(i8, i8, i8) -> i8 {
diff --git a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
index bbb8be09d..49ef59eb2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
@@ -12,26 +12,445 @@ block0:
 
 ; VCode:
 ; block0:
-;   lui a5,-2
-;   addi a1,a5,-564
-;   slli a2,a1,48
-;   srli a4,a2,48
-;   slli a0,a1,48
-;   srli a2,a0,48
-;   ne a0,a4,a2##ty=i16
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   lui a5, 0xffffe
-;   addi a1, a5, -0x234
-;   slli a2, a1, 0x30
-;   srli a4, a2, 0x30
-;   slli a0, a1, 0x30
-;   srli a2, a0, 0x30
-;   beq a4, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   lui a0,-2
+;   addi a2,a0,-564
+;   slli a3,a2,48
+;   srai a4,a3,48
+;   slli a0,a2,48
+;   srai a2,a0,48
+;   xor a4,a4,a2
+;   sltu a0,zero,a4
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a0, 0xffffe
+;   addi a2, a0, -0x234
+;   slli a3, a2, 0x30
+;   srai a4, a3, 0x30
+;   slli a0, a2, 0x30
+;   srai a2, a0, 0x30
+;   xor a4, a4, a2
+;   snez a0, a4
+;   ret
+
+function %seq_const0(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm eq v0, 0
+    return v2
+}
+
+; VCode:
+; block0:
+;   seqz a0,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   seqz a0, a0
+;   ret
+
+function %sne_const0(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ne v0, 0
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltu a0,zero,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   snez a0, a0
+;   ret
+
+function %slt_const0(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm slt v0, 0
+    return v2
+}
+
+; VCode:
+; block0:
+;   slt a0,a0,zero
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   sltz a0, a0
+;   ret
+
+function %sgt_const0(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm sgt v0, 0
+    return v2
+}
+
+; VCode:
+; block0:
+;   slt a0,zero,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   sgtz a0, a0
+;   ret
+
+function %ult_const0(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ult v0, 0
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltu a0,a0,zero
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   sltu a0, a0, zero
+;   ret
+
+function %ugt_const0(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ugt v0, 0
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltu a0,zero,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   snez a0, a0
+;   ret
+
+function %seq_const1(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm eq v0, 1
+    return v2
+}
+
+; VCode:
+; block0:
+;   xori a2,a0,1
+;   seqz a0,a2
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   xori a2, a0, 1
+;   seqz a0, a2
+;   ret
+
+function %sne_const1(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ne v0, 1
+    return v2
+}
+
+; VCode:
+; block0:
+;   xori a2,a0,1
+;   sltu a0,zero,a2
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   xori a2, a0, 1
+;   snez a0, a2
+;   ret
+
+function %slt_const1(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm slt v0, 1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti a0,a0,1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   slti a0, a0, 1
+;   ret
+
+function %sgt_const1(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm sgt v0, 1
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a3,1
+;   slt a0,a3,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 1
+;   slt a0, a3, a0
+;   ret
+
+function %ult_const1(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ult v0, 1
+    return v2
+}
+
+; VCode:
+; block0:
+;   seqz a0,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   seqz a0, a0
+;   ret
+
+function %ugt_const1(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ugt v0, 1
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a3,1
+;   sltu a0,a3,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 1
+;   sltu a0, a3, a0
+;   ret
+
+function %seq_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm eq v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   xori a2,a0,2
+;   seqz a0,a2
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   xori a2, a0, 2
+;   seqz a0, a2
+;   ret
+
+function %sne_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ne v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   xori a2,a0,2
+;   sltu a0,zero,a2
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   xori a2, a0, 2
+;   snez a0, a2
+;   ret
+
+function %slt_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm slt v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti a0,a0,2
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   slti a0, a0, 2
+;   ret
+
+function %sgt_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm sgt v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a3,2
+;   slt a0,a3,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 2
+;   slt a0, a3, a0
+;   ret
+
+function %ult_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ult v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltiu a0,a0,2
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   sltiu a0, a0, 2
+;   ret
+
+function %ugt_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ugt v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a3,2
+;   sltu a0,a3,a0
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 2
+;   sltu a0, a3, a0
+;   ret
+
+function %sle_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm sle v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a4,2
+;   slt a3,a4,a0
+;   xori a0,a3,1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 2
+;   slt a3, a4, a0
+;   xori a0, a3, 1
+;   ret
+
+function %sle_const_2046(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm sle v0, 2046
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a4,2046
+;   slt a3,a4,a0
+;   xori a0,a3,1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 0x7fe
+;   slt a3, a4, a0
+;   xori a0, a3, 1
+;   ret
+
+function %sle_const_2047(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm sle v0, 2047
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a4,2047
+;   slt a3,a4,a0
+;   xori a0,a3,1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 0x7ff
+;   slt a3, a4, a0
+;   xori a0, a3, 1
+;   ret
+
+function %sge_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm sge v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti a2,a0,2
+;   xori a0,a2,1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   slti a2, a0, 2
+;   xori a0, a2, 1
+;   ret
+
+function %ule_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm ule v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   li a4,2
+;   sltu a3,a4,a0
+;   xori a0,a3,1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 2
+;   sltu a3, a4, a0
+;   xori a0, a3, 1
+;   ret
+
+function %uge_const2(i64) -> i8 system_v {
+block0(v0: i64):
+    v2 = icmp_imm uge v0, 2
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltiu a2,a0,2
+;   xori a0,a2,1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   sltiu a2, a0, 2
+;   xori a0, a2, 1
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/return-call.clif b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
index 7eb4190dd..fe723381d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/return-call.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
@@ -155,21 +155,14 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   li a5,0
-;   andi a3,s1,255
-;   andi a5,a5,255
-;   eq s1,a3,a5##ty=i8
+;   andi a2,s1,255
+;   seqz s1,a2
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv a5, zero
-;   andi a3, s1, 0xff
-;   andi a5, a5, 0xff
-;   bne a3, a5, 0xc
-;   addi s1, zero, 1
-;   j 8
-;   mv s1, zero
+;   andi a2, s1, 0xff
+;   seqz s1, a2
 ;   ret
 
 function %call_i8(i8) -> i8 tail {
diff --git a/cranelift/filetests/filetests/isa/riscv64/select-float.clif b/cranelift/filetests/filetests/isa/riscv64/select-float.clif
index 3e1b7ffce..684fd934f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/select-float.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/select-float.clif
@@ -65,9 +65,9 @@ block0(v0: i16, v1: f32, v2: f32):
 ; block0:
 ;   li a3,42
 ;   slli a5,a0,48
-;   srli a1,a5,48
+;   srai a1,a5,48
 ;   slli a3,a3,48
-;   srli a5,a3,48
+;   srai a5,a3,48
 ;   select fa0,fa0,fa1##condition=(a1 eq a5)
 ;   ret
 ;
@@ -75,9 +75,9 @@ block0(v0: i16, v1: f32, v2: f32):
 ; block0: ; offset 0x0
 ;   addi a3, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srli a1, a5, 0x30
+;   srai a1, a5, 0x30
 ;   slli a3, a3, 0x30
-;   srli a5, a3, 0x30
+;   srai a5, a3, 0x30
 ;   beq a1, a5, 8
 ;   fmv.d fa0, fa1
 ;   ret
@@ -94,9 +94,9 @@ block0(v0: i16, v1: f64, v2: f64):
 ; block0:
 ;   li a3,42
 ;   slli a5,a0,48
-;   srli a1,a5,48
+;   srai a1,a5,48
 ;   slli a3,a3,48
-;   srli a5,a3,48
+;   srai a5,a3,48
 ;   select fa0,fa0,fa1##condition=(a1 eq a5)
 ;   ret
 ;
@@ -104,9 +104,9 @@ block0(v0: i16, v1: f64, v2: f64):
 ; block0: ; offset 0x0
 ;   addi a3, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srli a1, a5, 0x30
+;   srai a1, a5, 0x30
 ;   slli a3, a3, 0x30
-;   srli a5, a3, 0x30
+;   srai a5, a3, 0x30
 ;   beq a1, a5, 8
 ;   fmv.d fa0, fa1
 ;   ret
@@ -214,21 +214,23 @@ block0(v0: i128, v1: f32, v2: f32):
 
 ; VCode:
 ; block0:
-;   li a2,42
-;   li a3,0
-;   eq a2,[a0,a1],[a2,a3]##ty=i128
+;   li a5,42
+;   li a2,0
+;   xor a3,a0,a5
+;   xor a4,a1,a2
+;   or a0,a3,a4
+;   seqz a2,a0
 ;   select fa0,fa0,fa1##condition=(a2 ne zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a2, zero, 0x2a
-;   mv a3, zero
-;   bne a1, a3, 0x10
-;   bne a0, a2, 0xc
-;   addi a2, zero, 1
-;   j 8
+;   addi a5, zero, 0x2a
 ;   mv a2, zero
+;   xor a3, a0, a5
+;   xor a4, a1, a2
+;   or a0, a3, a4
+;   seqz a2, a0
 ;   bnez a2, 8
 ;   fmv.d fa0, fa1
 ;   ret
@@ -244,21 +246,23 @@ block0(v0: i128, v1: f64, v2: f64):
 
 ; VCode:
 ; block0:
-;   li a2,42
-;   li a3,0
-;   eq a2,[a0,a1],[a2,a3]##ty=i128
+;   li a5,42
+;   li a2,0
+;   xor a3,a0,a5
+;   xor a4,a1,a2
+;   or a0,a3,a4
+;   seqz a2,a0
 ;   select fa0,fa0,fa1##condition=(a2 ne zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a2, zero, 0x2a
-;   mv a3, zero
-;   bne a1, a3, 0x10
-;   bne a0, a2, 0xc
-;   addi a2, zero, 1
-;   j 8
+;   addi a5, zero, 0x2a
 ;   mv a2, zero
+;   xor a3, a0, a5
+;   xor a4, a1, a2
+;   or a0, a3, a4
+;   seqz a2, a0
 ;   bnez a2, 8
 ;   fmv.d fa0, fa1
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/select.clif b/cranelift/filetests/filetests/isa/riscv64/select.clif
index 1a7a6b98c..eb3cec98d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/select.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/select.clif
@@ -180,9 +180,9 @@ block0(v0: i16, v1: i8, v2: i8):
 ; block0:
 ;   li a3,42
 ;   slli a5,a0,48
-;   srli a4,a5,48
+;   srai a4,a5,48
 ;   slli a3,a3,48
-;   srli a5,a3,48
+;   srai a5,a3,48
 ;   select a0,a1,a2##condition=(a4 eq a5)
 ;   ret
 ;
@@ -190,9 +190,9 @@ block0(v0: i16, v1: i8, v2: i8):
 ; block0: ; offset 0x0
 ;   addi a3, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srli a4, a5, 0x30
+;   srai a4, a5, 0x30
 ;   slli a3, a3, 0x30
-;   srli a5, a3, 0x30
+;   srai a5, a3, 0x30
 ;   bne a4, a5, 0xc
 ;   mv a0, a1
 ;   j 8
@@ -211,9 +211,9 @@ block0(v0: i16, v1: i16, v2: i16):
 ; block0:
 ;   li a3,42
 ;   slli a5,a0,48
-;   srli a4,a5,48
+;   srai a4,a5,48
 ;   slli a3,a3,48
-;   srli a5,a3,48
+;   srai a5,a3,48
 ;   select a0,a1,a2##condition=(a4 eq a5)
 ;   ret
 ;
@@ -221,9 +221,9 @@ block0(v0: i16, v1: i16, v2: i16):
 ; block0: ; offset 0x0
 ;   addi a3, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srli a4, a5, 0x30
+;   srai a4, a5, 0x30
 ;   slli a3, a3, 0x30
-;   srli a5, a3, 0x30
+;   srai a5, a3, 0x30
 ;   bne a4, a5, 0xc
 ;   mv a0, a1
 ;   j 8
@@ -242,9 +242,9 @@ block0(v0: i16, v1: i32, v2: i32):
 ; block0:
 ;   li a3,42
 ;   slli a5,a0,48
-;   srli a4,a5,48
+;   srai a4,a5,48
 ;   slli a3,a3,48
-;   srli a5,a3,48
+;   srai a5,a3,48
 ;   select a0,a1,a2##condition=(a4 eq a5)
 ;   ret
 ;
@@ -252,9 +252,9 @@ block0(v0: i16, v1: i32, v2: i32):
 ; block0: ; offset 0x0
 ;   addi a3, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srli a4, a5, 0x30
+;   srai a4, a5, 0x30
 ;   slli a3, a3, 0x30
-;   srli a5, a3, 0x30
+;   srai a5, a3, 0x30
 ;   bne a4, a5, 0xc
 ;   mv a0, a1
 ;   j 8
@@ -273,9 +273,9 @@ block0(v0: i16, v1: i64, v2: i64):
 ; block0:
 ;   li a3,42
 ;   slli a5,a0,48
-;   srli a4,a5,48
+;   srai a4,a5,48
 ;   slli a3,a3,48
-;   srli a5,a3,48
+;   srai a5,a3,48
 ;   select a0,a1,a2##condition=(a4 eq a5)
 ;   ret
 ;
@@ -283,9 +283,9 @@ block0(v0: i16, v1: i64, v2: i64):
 ; block0: ; offset 0x0
 ;   addi a3, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srli a4, a5, 0x30
+;   srai a4, a5, 0x30
 ;   slli a3, a3, 0x30
-;   srli a5, a3, 0x30
+;   srai a5, a3, 0x30
 ;   bne a4, a5, 0xc
 ;   mv a0, a1
 ;   j 8
@@ -312,9 +312,9 @@ block0(v0: i16, v1: i128, v2: i128):
 ;   mv t0,a1
 ;   li s6,42
 ;   slli a1,a0,48
-;   srli a5,a1,48
+;   srai a5,a1,48
 ;   slli a0,s6,48
-;   srli s7,a0,48
+;   srai s7,a0,48
 ;   select [a0,a1],[t0,a2],[a3,a4]##condition=(a5 eq s7)
 ;   add sp,+16
 ;   ld s6,-8(sp)
@@ -337,9 +337,9 @@ block0(v0: i16, v1: i128, v2: i128):
 ;   mv t0, a1
 ;   addi s6, zero, 0x2a
 ;   slli a1, a0, 0x30
-;   srli a5, a1, 0x30
+;   srai a5, a1, 0x30
 ;   slli a0, s6, 0x30
-;   srli s7, a0, 0x30
+;   srai s7, a0, 0x30
 ;   bne a5, s7, 0x10
 ;   mv a0, t0
 ;   mv a1, a2
@@ -679,21 +679,23 @@ block0(v0: i128, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   li a5,0
-;   eq a4,[a0,a1],[a4,a5]##ty=i128
+;   li a5,42
+;   li a4,0
+;   xor a5,a0,a5
+;   xor a4,a1,a4
+;   or a0,a5,a4
+;   seqz a4,a0
 ;   select a0,a2,a3##condition=(a4 ne zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
+;   addi a5, zero, 0x2a
 ;   mv a4, zero
+;   xor a5, a0, a5
+;   xor a4, a1, a4
+;   or a0, a5, a4
+;   seqz a4, a0
 ;   beqz a4, 0xc
 ;   mv a0, a2
 ;   j 8
@@ -711,21 +713,23 @@ block0(v0: i128, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   li a5,0
-;   eq a4,[a0,a1],[a4,a5]##ty=i128
+;   li a5,42
+;   li a4,0
+;   xor a5,a0,a5
+;   xor a4,a1,a4
+;   or a0,a5,a4
+;   seqz a4,a0
 ;   select a0,a2,a3##condition=(a4 ne zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
+;   addi a5, zero, 0x2a
 ;   mv a4, zero
+;   xor a5, a0, a5
+;   xor a4, a1, a4
+;   or a0, a5, a4
+;   seqz a4, a0
 ;   beqz a4, 0xc
 ;   mv a0, a2
 ;   j 8
@@ -743,21 +747,23 @@ block0(v0: i128, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   li a5,0
-;   eq a4,[a0,a1],[a4,a5]##ty=i128
+;   li a5,42
+;   li a4,0
+;   xor a5,a0,a5
+;   xor a4,a1,a4
+;   or a0,a5,a4
+;   seqz a4,a0
 ;   select a0,a2,a3##condition=(a4 ne zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
+;   addi a5, zero, 0x2a
 ;   mv a4, zero
+;   xor a5, a0, a5
+;   xor a4, a1, a4
+;   or a0, a5, a4
+;   seqz a4, a0
 ;   beqz a4, 0xc
 ;   mv a0, a2
 ;   j 8
@@ -775,21 +781,23 @@ block0(v0: i128, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   li a5,0
-;   eq a4,[a0,a1],[a4,a5]##ty=i128
+;   li a5,42
+;   li a4,0
+;   xor a5,a0,a5
+;   xor a4,a1,a4
+;   or a0,a5,a4
+;   seqz a4,a0
 ;   select a0,a2,a3##condition=(a4 ne zero)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
+;   addi a5, zero, 0x2a
 ;   mv a4, zero
+;   xor a5, a0, a5
+;   xor a4, a1, a4
+;   or a0, a5, a4
+;   seqz a4, a0
 ;   beqz a4, 0xc
 ;   mv a0, a2
 ;   j 8
@@ -810,20 +818,23 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s4,-8(sp)
-;   sd s5,-16(sp)
-;   sd s6,-24(sp)
+;   sd s7,-8(sp)
+;   sd s8,-16(sp)
+;   sd s9,-24(sp)
 ;   add sp,-32
 ; block0:
-;   li s5,42
-;   li s6,0
-;   eq a0,[a0,a1],[s5,s6]##ty=i128
-;   select [s4,a1],[a2,a3],[a4,a5]##condition=(a0 ne zero)
-;   mv a0,s4
+;   li s8,42
+;   li s9,0
+;   xor a0,a0,s8
+;   xor a1,a1,s9
+;   or a0,a0,a1
+;   seqz a0,a0
+;   select [s7,a1],[a2,a3],[a4,a5]##condition=(a0 ne zero)
+;   mv a0,s7
 ;   add sp,+32
-;   ld s4,-8(sp)
-;   ld s5,-16(sp)
-;   ld s6,-24(sp)
+;   ld s7,-8(sp)
+;   ld s8,-16(sp)
+;   ld s9,-24(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -835,29 +846,28 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s4, -8(sp)
-;   sd s5, -0x10(sp)
-;   sd s6, -0x18(sp)
+;   sd s7, -8(sp)
+;   sd s8, -0x10(sp)
+;   sd s9, -0x18(sp)
 ;   addi sp, sp, -0x20
 ; block1: ; offset 0x20
-;   addi s5, zero, 0x2a
-;   mv s6, zero
-;   bne a1, s6, 0x10
-;   bne a0, s5, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   addi s8, zero, 0x2a
+;   mv s9, zero
+;   xor a0, a0, s8
+;   xor a1, a1, s9
+;   or a0, a0, a1
+;   seqz a0, a0
 ;   beqz a0, 0x10
-;   mv s4, a2
+;   mv s7, a2
 ;   mv a1, a3
 ;   j 0xc
-;   mv s4, a4
+;   mv s7, a4
 ;   mv a1, a5
-;   mv a0, s4
+;   mv a0, s7
 ;   addi sp, sp, 0x20
-;   ld s4, -8(sp)
-;   ld s5, -0x10(sp)
-;   ld s6, -0x18(sp)
+;   ld s7, -8(sp)
+;   ld s8, -0x10(sp)
+;   ld s9, -0x18(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
index d10455421..60c5438e7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
@@ -12,11 +12,10 @@ block0(v0: i8, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   mv a3,a0
-;   li a0,42
-;   andi a4,a3,255
-;   andi a0,a0,255
-;   eq a3,a4,a0##ty=i8
+;   slli a3,a0,56
+;   srai a5,a3,56
+;   xori a3,a5,42
+;   seqz a3,a3
 ;   sub a3,zero,a3
 ;   and a4,a1,a3
 ;   not a0,a3
@@ -26,14 +25,10 @@ block0(v0: i8, v1: i8, v2: i8):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv a3, a0
-;   addi a0, zero, 0x2a
-;   andi a4, a3, 0xff
-;   andi a0, a0, 0xff
-;   bne a4, a0, 0xc
-;   addi a3, zero, 1
-;   j 8
-;   mv a3, zero
+;   slli a3, a0, 0x38
+;   srai a5, a3, 0x38
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
 ;   neg a3, a3
 ;   and a4, a1, a3
 ;   not a0, a3
@@ -51,11 +46,10 @@ block0(v0: i8, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   mv a3,a0
-;   li a0,42
-;   andi a4,a3,255
-;   andi a0,a0,255
-;   eq a3,a4,a0##ty=i8
+;   slli a3,a0,56
+;   srai a5,a3,56
+;   xori a3,a5,42
+;   seqz a3,a3
 ;   sub a3,zero,a3
 ;   and a4,a1,a3
 ;   not a0,a3
@@ -65,14 +59,10 @@ block0(v0: i8, v1: i16, v2: i16):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv a3, a0
-;   addi a0, zero, 0x2a
-;   andi a4, a3, 0xff
-;   andi a0, a0, 0xff
-;   bne a4, a0, 0xc
-;   addi a3, zero, 1
-;   j 8
-;   mv a3, zero
+;   slli a3, a0, 0x38
+;   srai a5, a3, 0x38
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
 ;   neg a3, a3
 ;   and a4, a1, a3
 ;   not a0, a3
@@ -90,11 +80,10 @@ block0(v0: i8, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   mv a3,a0
-;   li a0,42
-;   andi a4,a3,255
-;   andi a0,a0,255
-;   eq a3,a4,a0##ty=i8
+;   slli a3,a0,56
+;   srai a5,a3,56
+;   xori a3,a5,42
+;   seqz a3,a3
 ;   sub a3,zero,a3
 ;   and a4,a1,a3
 ;   not a0,a3
@@ -104,14 +93,10 @@ block0(v0: i8, v1: i32, v2: i32):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv a3, a0
-;   addi a0, zero, 0x2a
-;   andi a4, a3, 0xff
-;   andi a0, a0, 0xff
-;   bne a4, a0, 0xc
-;   addi a3, zero, 1
-;   j 8
-;   mv a3, zero
+;   slli a3, a0, 0x38
+;   srai a5, a3, 0x38
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
 ;   neg a3, a3
 ;   and a4, a1, a3
 ;   not a0, a3
@@ -129,11 +114,10 @@ block0(v0: i8, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   mv a3,a0
-;   li a0,42
-;   andi a4,a3,255
-;   andi a0,a0,255
-;   eq a3,a4,a0##ty=i8
+;   slli a3,a0,56
+;   srai a5,a3,56
+;   xori a3,a5,42
+;   seqz a3,a3
 ;   sub a3,zero,a3
 ;   and a4,a1,a3
 ;   not a0,a3
@@ -143,14 +127,10 @@ block0(v0: i8, v1: i64, v2: i64):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv a3, a0
-;   addi a0, zero, 0x2a
-;   andi a4, a3, 0xff
-;   andi a0, a0, 0xff
-;   bne a4, a0, 0xc
-;   addi a3, zero, 1
-;   j 8
-;   mv a3, zero
+;   slli a3, a0, 0x38
+;   srai a5, a3, 0x38
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
 ;   neg a3, a3
 ;   and a4, a1, a3
 ;   not a0, a3
@@ -174,11 +154,10 @@ block0(v0: i8, v1: i128, v2: i128):
 ;   sd s10,-8(sp)
 ;   add sp,-16
 ; block0:
-;   mv a5,a0
-;   li a0,42
-;   andi a5,a5,255
-;   andi a0,a0,255
-;   eq a5,a5,a0##ty=i8
+;   slli a5,a0,56
+;   srai a5,a5,56
+;   xori a5,a5,42
+;   seqz a5,a5
 ;   sub a5,zero,a5
 ;   and a0,a1,a5
 ;   and a2,a2,a5
@@ -204,14 +183,10 @@ block0(v0: i8, v1: i128, v2: i128):
 ;   sd s10, -8(sp)
 ;   addi sp, sp, -0x10
 ; block1: ; offset 0x18
-;   mv a5, a0
-;   addi a0, zero, 0x2a
-;   andi a5, a5, 0xff
-;   andi a0, a0, 0xff
-;   bne a5, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
+;   slli a5, a0, 0x38
+;   srai a5, a5, 0x38
+;   xori a5, a5, 0x2a
+;   seqz a5, a5
 ;   neg a5, a5
 ;   and a0, a1, a5
 ;   and a2, a2, a5
@@ -238,35 +213,28 @@ block0(v0: i16, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,48
-;   srli a0,a4,48
-;   slli a3,a3,48
-;   srli a4,a3,48
-;   eq a0,a0,a4##ty=i16
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli a3,a0,48
+;   srai a5,a3,48
+;   xori a3,a5,42
+;   seqz a3,a3
+;   sub a3,zero,a3
+;   and a4,a1,a3
+;   not a0,a3
+;   and a2,a2,a0
+;   or a0,a4,a2
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x30
-;   srli a0, a4, 0x30
-;   slli a3, a3, 0x30
-;   srli a4, a3, 0x30
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli a3, a0, 0x30
+;   srai a5, a3, 0x30
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
+;   neg a3, a3
+;   and a4, a1, a3
+;   not a0, a3
+;   and a2, a2, a0
+;   or a0, a4, a2
 ;   ret
 
 function %f(i16, i16, i16) -> i16 {
@@ -279,35 +247,28 @@ block0(v0: i16, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,48
-;   srli a0,a4,48
-;   slli a3,a3,48
-;   srli a4,a3,48
-;   eq a0,a0,a4##ty=i16
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli a3,a0,48
+;   srai a5,a3,48
+;   xori a3,a5,42
+;   seqz a3,a3
+;   sub a3,zero,a3
+;   and a4,a1,a3
+;   not a0,a3
+;   and a2,a2,a0
+;   or a0,a4,a2
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x30
-;   srli a0, a4, 0x30
-;   slli a3, a3, 0x30
-;   srli a4, a3, 0x30
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli a3, a0, 0x30
+;   srai a5, a3, 0x30
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
+;   neg a3, a3
+;   and a4, a1, a3
+;   not a0, a3
+;   and a2, a2, a0
+;   or a0, a4, a2
 ;   ret
 
 function %f(i16, i32, i32) -> i32 {
@@ -320,35 +281,28 @@ block0(v0: i16, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,48
-;   srli a0,a4,48
-;   slli a3,a3,48
-;   srli a4,a3,48
-;   eq a0,a0,a4##ty=i16
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli a3,a0,48
+;   srai a5,a3,48
+;   xori a3,a5,42
+;   seqz a3,a3
+;   sub a3,zero,a3
+;   and a4,a1,a3
+;   not a0,a3
+;   and a2,a2,a0
+;   or a0,a4,a2
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x30
-;   srli a0, a4, 0x30
-;   slli a3, a3, 0x30
-;   srli a4, a3, 0x30
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli a3, a0, 0x30
+;   srai a5, a3, 0x30
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
+;   neg a3, a3
+;   and a4, a1, a3
+;   not a0, a3
+;   and a2, a2, a0
+;   or a0, a4, a2
 ;   ret
 
 function %f(i16, i64, i64) -> i64 {
@@ -361,35 +315,28 @@ block0(v0: i16, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,48
-;   srli a0,a4,48
-;   slli a3,a3,48
-;   srli a4,a3,48
-;   eq a0,a0,a4##ty=i16
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli a3,a0,48
+;   srai a5,a3,48
+;   xori a3,a5,42
+;   seqz a3,a3
+;   sub a3,zero,a3
+;   and a4,a1,a3
+;   not a0,a3
+;   and a2,a2,a0
+;   or a0,a4,a2
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x30
-;   srli a0, a4, 0x30
-;   slli a3, a3, 0x30
-;   srli a4, a3, 0x30
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli a3, a0, 0x30
+;   srai a5, a3, 0x30
+;   xori a3, a5, 0x2a
+;   seqz a3, a3
+;   neg a3, a3
+;   and a4, a1, a3
+;   not a0, a3
+;   and a2, a2, a0
+;   or a0, a4, a2
 ;   ret
 
 function %f(i16, i128, i128) -> i128 {
@@ -405,26 +352,24 @@ block0(v0: i16, v1: i128, v2: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s6,-8(sp)
+;   sd s10,-8(sp)
 ;   add sp,-16
 ; block0:
-;   li a5,42
-;   slli a0,a0,48
-;   srli a0,a0,48
-;   slli a5,a5,48
-;   srli a5,a5,48
-;   eq a0,a0,a5##ty=i16
-;   sub s6,zero,a0
-;   and a0,a1,s6
-;   and a5,a2,s6
-;   not a2,s6
-;   not a1,s6
-;   and a2,a3,a2
-;   and a1,a4,a1
-;   or a0,a0,a2
-;   or a1,a5,a1
+;   slli a5,a0,48
+;   srai a5,a5,48
+;   xori a5,a5,42
+;   seqz a5,a5
+;   sub a5,zero,a5
+;   and a0,a1,a5
+;   and a2,a2,a5
+;   not s10,a5
+;   not a1,a5
+;   and a3,a3,s10
+;   and a4,a4,a1
+;   or a0,a0,a3
+;   or a1,a2,a4
 ;   add sp,+16
-;   ld s6,-8(sp)
+;   ld s10,-8(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -436,29 +381,24 @@ block0(v0: i16, v1: i128, v2: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s6, -8(sp)
+;   sd s10, -8(sp)
 ;   addi sp, sp, -0x10
 ; block1: ; offset 0x18
-;   addi a5, zero, 0x2a
-;   slli a0, a0, 0x30
-;   srli a0, a0, 0x30
-;   slli a5, a5, 0x30
-;   srli a5, a5, 0x30
-;   bne a0, a5, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg s6, a0
-;   and a0, a1, s6
-;   and a5, a2, s6
-;   not a2, s6
-;   not a1, s6
-;   and a2, a3, a2
-;   and a1, a4, a1
-;   or a0, a0, a2
-;   or a1, a5, a1
+;   slli a5, a0, 0x30
+;   srai a5, a5, 0x30
+;   xori a5, a5, 0x2a
+;   seqz a5, a5
+;   neg a5, a5
+;   and a0, a1, a5
+;   and a2, a2, a5
+;   not s10, a5
+;   not a1, a5
+;   and a3, a3, s10
+;   and a4, a4, a1
+;   or a0, a0, a3
+;   or a1, a2, a4
 ;   addi sp, sp, 0x10
-;   ld s6, -8(sp)
+;   ld s10, -8(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -474,35 +414,26 @@ block0(v0: i32, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,32
-;   srli a0,a4,32
-;   slli a3,a3,32
-;   srli a4,a3,32
-;   eq a0,a0,a4##ty=i32
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w a3,a0
+;   xori a5,a3,42
+;   seqz a3,a5
+;   sub a4,zero,a3
+;   and a3,a1,a4
+;   not a5,a4
+;   and a1,a2,a5
+;   or a0,a3,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x20
-;   srli a0, a4, 0x20
-;   slli a3, a3, 0x20
-;   srli a4, a3, 0x20
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w a3, a0
+;   xori a5, a3, 0x2a
+;   seqz a3, a5
+;   neg a4, a3
+;   and a3, a1, a4
+;   not a5, a4
+;   and a1, a2, a5
+;   or a0, a3, a1
 ;   ret
 
 function %f(i32, i16, i16) -> i16 {
@@ -515,35 +446,26 @@ block0(v0: i32, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,32
-;   srli a0,a4,32
-;   slli a3,a3,32
-;   srli a4,a3,32
-;   eq a0,a0,a4##ty=i32
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w a3,a0
+;   xori a5,a3,42
+;   seqz a3,a5
+;   sub a4,zero,a3
+;   and a3,a1,a4
+;   not a5,a4
+;   and a1,a2,a5
+;   or a0,a3,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x20
-;   srli a0, a4, 0x20
-;   slli a3, a3, 0x20
-;   srli a4, a3, 0x20
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w a3, a0
+;   xori a5, a3, 0x2a
+;   seqz a3, a5
+;   neg a4, a3
+;   and a3, a1, a4
+;   not a5, a4
+;   and a1, a2, a5
+;   or a0, a3, a1
 ;   ret
 
 function %f(i32, i32, i32) -> i32 {
@@ -556,35 +478,26 @@ block0(v0: i32, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,32
-;   srli a0,a4,32
-;   slli a3,a3,32
-;   srli a4,a3,32
-;   eq a0,a0,a4##ty=i32
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w a3,a0
+;   xori a5,a3,42
+;   seqz a3,a5
+;   sub a4,zero,a3
+;   and a3,a1,a4
+;   not a5,a4
+;   and a1,a2,a5
+;   or a0,a3,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x20
-;   srli a0, a4, 0x20
-;   slli a3, a3, 0x20
-;   srli a4, a3, 0x20
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w a3, a0
+;   xori a5, a3, 0x2a
+;   seqz a3, a5
+;   neg a4, a3
+;   and a3, a1, a4
+;   not a5, a4
+;   and a1, a2, a5
+;   or a0, a3, a1
 ;   ret
 
 function %f(i32, i64, i64) -> i64 {
@@ -597,35 +510,26 @@ block0(v0: i32, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli a4,a0,32
-;   srli a0,a4,32
-;   slli a3,a3,32
-;   srli a4,a3,32
-;   eq a0,a0,a4##ty=i32
-;   sub a4,zero,a0
-;   and a0,a1,a4
-;   not a3,a4
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w a3,a0
+;   xori a5,a3,42
+;   seqz a3,a5
+;   sub a4,zero,a3
+;   and a3,a1,a4
+;   not a5,a4
+;   and a1,a2,a5
+;   or a0,a3,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli a4, a0, 0x20
-;   srli a0, a4, 0x20
-;   slli a3, a3, 0x20
-;   srli a4, a3, 0x20
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a4, a0
-;   and a0, a1, a4
-;   not a3, a4
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w a3, a0
+;   xori a5, a3, 0x2a
+;   seqz a3, a5
+;   neg a4, a3
+;   and a3, a1, a4
+;   not a5, a4
+;   and a1, a2, a5
+;   or a0, a3, a1
 ;   ret
 
 function %f(i32, i128, i128) -> i128 {
@@ -637,67 +541,35 @@ block0(v0: i32, v1: i128, v2: i128):
 }
 
 ; VCode:
-;   add sp,-16
-;   sd ra,8(sp)
-;   sd fp,0(sp)
-;   mv fp,sp
-;   sd s6,-8(sp)
-;   add sp,-16
 ; block0:
-;   li a5,42
-;   slli a0,a0,32
-;   srli a0,a0,32
-;   slli a5,a5,32
-;   srli a5,a5,32
-;   eq a0,a0,a5##ty=i32
-;   sub s6,zero,a0
-;   and a0,a1,s6
-;   and a5,a2,s6
-;   not a2,s6
-;   not a1,s6
+;   sext.w a5,a0
+;   xori a5,a5,42
+;   seqz a5,a5
+;   sub a0,zero,a5
+;   and a5,a1,a0
+;   and a1,a2,a0
+;   not a2,a0
+;   not a0,a0
 ;   and a2,a3,a2
-;   and a1,a4,a1
-;   or a0,a0,a2
-;   or a1,a5,a1
-;   add sp,+16
-;   ld s6,-8(sp)
-;   ld ra,8(sp)
-;   ld fp,0(sp)
-;   add sp,+16
+;   and a3,a4,a0
+;   or a0,a5,a2
+;   or a1,a1,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi sp, sp, -0x10
-;   sd ra, 8(sp)
-;   sd s0, 0(sp)
-;   mv s0, sp
-;   sd s6, -8(sp)
-;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   addi a5, zero, 0x2a
-;   slli a0, a0, 0x20
-;   srli a0, a0, 0x20
-;   slli a5, a5, 0x20
-;   srli a5, a5, 0x20
-;   bne a0, a5, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg s6, a0
-;   and a0, a1, s6
-;   and a5, a2, s6
-;   not a2, s6
-;   not a1, s6
+;   sext.w a5, a0
+;   xori a5, a5, 0x2a
+;   seqz a5, a5
+;   neg a0, a5
+;   and a5, a1, a0
+;   and a1, a2, a0
+;   not a2, a0
+;   not a0, a0
 ;   and a2, a3, a2
-;   and a1, a4, a1
-;   or a0, a0, a2
-;   or a1, a5, a1
-;   addi sp, sp, 0x10
-;   ld s6, -8(sp)
-;   ld ra, 8(sp)
-;   ld s0, 0(sp)
-;   addi sp, sp, 0x10
+;   and a3, a4, a0
+;   or a0, a5, a2
+;   or a1, a1, a3
 ;   ret
 
 function %f(i64, i8, i8) -> i8 {
@@ -710,9 +582,9 @@ block0(v0: i64, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   eq a4,a0,a4##ty=i64
-;   sub a0,zero,a4
+;   xori a3,a0,42
+;   seqz a5,a3
+;   sub a0,zero,a5
 ;   and a3,a1,a0
 ;   not a4,a0
 ;   and a0,a2,a4
@@ -721,12 +593,9 @@ block0(v0: i64, v1: i8, v2: i8):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   neg a0, a4
+;   xori a3, a0, 0x2a
+;   seqz a5, a3
+;   neg a0, a5
 ;   and a3, a1, a0
 ;   not a4, a0
 ;   and a0, a2, a4
@@ -743,9 +612,9 @@ block0(v0: i64, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   eq a4,a0,a4##ty=i64
-;   sub a0,zero,a4
+;   xori a3,a0,42
+;   seqz a5,a3
+;   sub a0,zero,a5
 ;   and a3,a1,a0
 ;   not a4,a0
 ;   and a0,a2,a4
@@ -754,12 +623,9 @@ block0(v0: i64, v1: i16, v2: i16):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   neg a0, a4
+;   xori a3, a0, 0x2a
+;   seqz a5, a3
+;   neg a0, a5
 ;   and a3, a1, a0
 ;   not a4, a0
 ;   and a0, a2, a4
@@ -776,9 +642,9 @@ block0(v0: i64, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   eq a4,a0,a4##ty=i64
-;   sub a0,zero,a4
+;   xori a3,a0,42
+;   seqz a5,a3
+;   sub a0,zero,a5
 ;   and a3,a1,a0
 ;   not a4,a0
 ;   and a0,a2,a4
@@ -787,12 +653,9 @@ block0(v0: i64, v1: i32, v2: i32):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   neg a0, a4
+;   xori a3, a0, 0x2a
+;   seqz a5, a3
+;   neg a0, a5
 ;   and a3, a1, a0
 ;   not a4, a0
 ;   and a0, a2, a4
@@ -809,9 +672,9 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li a4,42
-;   eq a4,a0,a4##ty=i64
-;   sub a0,zero,a4
+;   xori a3,a0,42
+;   seqz a5,a3
+;   sub a0,zero,a5
 ;   and a3,a1,a0
 ;   not a4,a0
 ;   and a0,a2,a4
@@ -820,12 +683,9 @@ block0(v0: i64, v1: i64, v2: i64):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a4, zero, 0x2a
-;   bne a0, a4, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   neg a0, a4
+;   xori a3, a0, 0x2a
+;   seqz a5, a3
+;   neg a0, a5
 ;   and a3, a1, a0
 ;   not a4, a0
 ;   and a0, a2, a4
@@ -849,8 +709,8 @@ block0(v0: i64, v1: i128, v2: i128):
 ;   add sp,-16
 ; block0:
 ;   mv s11,a1
-;   li a5,42
-;   eq a5,a0,a5##ty=i64
+;   xori a5,a0,42
+;   seqz a5,a5
 ;   sub a1,zero,a5
 ;   mv a5,s11
 ;   and a5,a5,a1
@@ -878,11 +738,8 @@ block0(v0: i64, v1: i128, v2: i128):
 ;   addi sp, sp, -0x10
 ; block1: ; offset 0x18
 ;   mv s11, a1
-;   addi a5, zero, 0x2a
-;   bne a0, a5, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
+;   xori a5, a0, 0x2a
+;   seqz a5, a5
 ;   neg a1, a5
 ;   mv a5, s11
 ;   and a5, a5, a1
@@ -913,28 +770,30 @@ block0(v0: i128, v1: i8, v2: i8):
 ; block0:
 ;   li a4,42
 ;   li a5,0
-;   eq a0,[a0,a1],[a4,a5]##ty=i128
+;   xor a0,a0,a4
+;   xor a4,a1,a5
+;   or a4,a0,a4
+;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a4,a2,a5
-;   not a0,a5
-;   and a2,a3,a0
-;   or a0,a4,a2
+;   and a1,a2,a5
+;   not a4,a5
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a4, zero, 0x2a
 ;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a0, a0, a4
+;   xor a4, a1, a5
+;   or a4, a0, a4
+;   seqz a0, a4
 ;   neg a5, a0
-;   and a4, a2, a5
-;   not a0, a5
-;   and a2, a3, a0
-;   or a0, a4, a2
+;   and a1, a2, a5
+;   not a4, a5
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i16, i16) -> i16 {
@@ -950,28 +809,30 @@ block0(v0: i128, v1: i16, v2: i16):
 ; block0:
 ;   li a4,42
 ;   li a5,0
-;   eq a0,[a0,a1],[a4,a5]##ty=i128
+;   xor a0,a0,a4
+;   xor a4,a1,a5
+;   or a4,a0,a4
+;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a4,a2,a5
-;   not a0,a5
-;   and a2,a3,a0
-;   or a0,a4,a2
+;   and a1,a2,a5
+;   not a4,a5
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a4, zero, 0x2a
 ;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a0, a0, a4
+;   xor a4, a1, a5
+;   or a4, a0, a4
+;   seqz a0, a4
 ;   neg a5, a0
-;   and a4, a2, a5
-;   not a0, a5
-;   and a2, a3, a0
-;   or a0, a4, a2
+;   and a1, a2, a5
+;   not a4, a5
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i32, i32) -> i32 {
@@ -987,28 +848,30 @@ block0(v0: i128, v1: i32, v2: i32):
 ; block0:
 ;   li a4,42
 ;   li a5,0
-;   eq a0,[a0,a1],[a4,a5]##ty=i128
+;   xor a0,a0,a4
+;   xor a4,a1,a5
+;   or a4,a0,a4
+;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a4,a2,a5
-;   not a0,a5
-;   and a2,a3,a0
-;   or a0,a4,a2
+;   and a1,a2,a5
+;   not a4,a5
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a4, zero, 0x2a
 ;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a0, a0, a4
+;   xor a4, a1, a5
+;   or a4, a0, a4
+;   seqz a0, a4
 ;   neg a5, a0
-;   and a4, a2, a5
-;   not a0, a5
-;   and a2, a3, a0
-;   or a0, a4, a2
+;   and a1, a2, a5
+;   not a4, a5
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i64, i64) -> i64 {
@@ -1024,28 +887,30 @@ block0(v0: i128, v1: i64, v2: i64):
 ; block0:
 ;   li a4,42
 ;   li a5,0
-;   eq a0,[a0,a1],[a4,a5]##ty=i128
+;   xor a0,a0,a4
+;   xor a4,a1,a5
+;   or a4,a0,a4
+;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a4,a2,a5
-;   not a0,a5
-;   and a2,a3,a0
-;   or a0,a4,a2
+;   and a1,a2,a5
+;   not a4,a5
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a4, zero, 0x2a
 ;   mv a5, zero
-;   bne a1, a5, 0x10
-;   bne a0, a4, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a0, a0, a4
+;   xor a4, a1, a5
+;   or a4, a0, a4
+;   seqz a0, a4
 ;   neg a5, a0
-;   and a4, a2, a5
-;   not a0, a5
-;   and a2, a3, a0
-;   or a0, a4, a2
+;   and a1, a2, a5
+;   not a4, a5
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i128, i128) -> i128 {
@@ -1058,38 +923,63 @@ block0(v0: i128, v1: i128, v2: i128):
 }
 
 ; VCode:
+;   add sp,-16
+;   sd ra,8(sp)
+;   sd fp,0(sp)
+;   mv fp,sp
+;   sd s7,-8(sp)
+;   add sp,-16
 ; block0:
-;   li t0,42
-;   li t1,0
-;   eq a0,[a0,a1],[t0,t1]##ty=i128
-;   sub a1,zero,a0
-;   and a0,a2,a1
-;   and a2,a3,a1
-;   not a3,a1
-;   not a1,a1
-;   and a3,a4,a3
-;   and a4,a5,a1
-;   or a0,a0,a3
-;   or a1,a2,a4
+;   li a6,42
+;   li a7,0
+;   xor a0,a0,a6
+;   xor a1,a1,a7
+;   or a0,a0,a1
+;   seqz a0,a0
+;   sub s7,zero,a0
+;   and a1,a2,s7
+;   and a2,a3,s7
+;   not a0,s7
+;   not a3,s7
+;   and a0,a4,a0
+;   and a3,a5,a3
+;   or a0,a1,a0
+;   or a1,a2,a3
+;   add sp,+16
+;   ld s7,-8(sp)
+;   ld ra,8(sp)
+;   ld fp,0(sp)
+;   add sp,+16
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t0, zero, 0x2a
-;   mv t1, zero
-;   bne a1, t1, 0x10
-;   bne a0, t0, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   neg a1, a0
-;   and a0, a2, a1
-;   and a2, a3, a1
-;   not a3, a1
-;   not a1, a1
-;   and a3, a4, a3
-;   and a4, a5, a1
-;   or a0, a0, a3
-;   or a1, a2, a4
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   mv s0, sp
+;   sd s7, -8(sp)
+;   addi sp, sp, -0x10
+; block1: ; offset 0x18
+;   addi a6, zero, 0x2a
+;   mv a7, zero
+;   xor a0, a0, a6
+;   xor a1, a1, a7
+;   or a0, a0, a1
+;   seqz a0, a0
+;   neg s7, a0
+;   and a1, a2, s7
+;   and a2, a3, s7
+;   not a0, s7
+;   not a3, s7
+;   and a0, a4, a0
+;   and a3, a5, a3
+;   or a0, a1, a0
+;   or a1, a2, a3
+;   addi sp, sp, 0x10
+;   ld s7, -8(sp)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif
index 25812fb06..c0b3b3215 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif
@@ -89,15 +89,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   sgt a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   slt a5,a3,a1
+;   sltu a4,a2,a0
+;   mv s7,a0
+;   xor a0,a3,a1
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -109,25 +115,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   slt a5, a3, a1
+;   sltu a4, a2, a0
+;   mv s7, a0
+;   xor a0, a3, a1
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/smax.clif b/cranelift/filetests/filetests/isa/riscv64/smax.clif
index 271ab6bdd..42f63cd0f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smax.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smax.clif
@@ -107,15 +107,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   sgt a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   slt a5,a3,a1
+;   sltu a4,a2,a0
+;   mv s7,a0
+;   xor a0,a3,a1
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -127,25 +133,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   slt a5, a3, a1
+;   sltu a4, a2, a0
+;   mv s7, a0
+;   xor a0, a3, a1
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif
index fa67cb0d9..facfb611a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif
@@ -89,15 +89,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   slt a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   slt a5,a1,a3
+;   sltu a4,a0,a2
+;   mv s7,a0
+;   xor a0,a1,a3
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -109,25 +115,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   slt a5, a1, a3
+;   sltu a4, a0, a2
+;   mv s7, a0
+;   xor a0, a1, a3
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/smin.clif b/cranelift/filetests/filetests/isa/riscv64/smin.clif
index 92ed89a5b..235ddcb9c 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smin.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smin.clif
@@ -107,15 +107,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   slt a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   slt a5,a1,a3
+;   sltu a4,a0,a2
+;   mv s7,a0
+;   xor a0,a1,a3
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -127,25 +133,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   slt a5, a1, a3
+;   sltu a4, a0, a2
+;   mv s7, a0
+;   xor a0, a1, a3
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif
index 1eb8f37ba..ac0f999e0 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif
@@ -93,15 +93,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   ugt a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   sltu a5,a3,a1
+;   sltu a4,a2,a0
+;   mv s7,a0
+;   xor a0,a3,a1
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -113,25 +119,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   sltu a5, a3, a1
+;   sltu a4, a2, a0
+;   mv s7, a0
+;   xor a0, a3, a1
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/umax.clif b/cranelift/filetests/filetests/isa/riscv64/umax.clif
index a2eb42d2e..fa55e3692 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umax.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umax.clif
@@ -107,15 +107,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   ugt a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   sltu a5,a3,a1
+;   sltu a4,a2,a0
+;   mv s7,a0
+;   xor a0,a3,a1
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -127,25 +133,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   sltu a5, a3, a1
+;   sltu a4, a2, a0
+;   mv s7, a0
+;   xor a0, a3, a1
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif
index 2a2d522b5..e7895cabe 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif
@@ -93,15 +93,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   ult a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   sltu a5,a1,a3
+;   sltu a4,a0,a2
+;   mv s7,a0
+;   xor a0,a1,a3
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -113,25 +119,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   sltu a5, a1, a3
+;   sltu a4, a0, a2
+;   mv s7, a0
+;   xor a0, a1, a3
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/umin.clif b/cranelift/filetests/filetests/isa/riscv64/umin.clif
index 74eb80d45..85d51fb39 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umin.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umin.clif
@@ -107,15 +107,21 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s3,-8(sp)
+;   sd s7,-8(sp)
+;   sd s9,-16(sp)
 ;   add sp,-16
 ; block0:
-;   ult a5,[a0,a1],[a2,a3]##ty=i128
-;   mv a4,a0
-;   mv s3,a1
-;   select [a0,a1],[a4,s3],[a2,a3]##condition=(a5 ne zero)
+;   sltu a5,a1,a3
+;   sltu a4,a0,a2
+;   mv s7,a0
+;   xor a0,a1,a3
+;   mv s9,a1
+;   select a5,a4,a5##condition=(a0 eq zero)
+;   mv a4,s7
+;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
 ;   add sp,+16
-;   ld s3,-8(sp)
+;   ld s7,-8(sp)
+;   ld s9,-16(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -127,25 +133,27 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   sd s3, -8(sp)
+;   sd s7, -8(sp)
+;   sd s9, -0x10(sp)
 ;   addi sp, sp, -0x10
-; block1: ; offset 0x18
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   mv a4, a0
-;   mv s3, a1
+; block1: ; offset 0x1c
+;   sltu a5, a1, a3
+;   sltu a4, a0, a2
+;   mv s7, a0
+;   xor a0, a1, a3
+;   mv s9, a1
+;   bnez a0, 8
+;   mv a5, a4
+;   mv a4, s7
 ;   beqz a5, 0x10
 ;   mv a0, a4
-;   mv a1, s3
+;   mv a1, s9
 ;   j 0xc
 ;   mv a0, a2
 ;   mv a1, a3
 ;   addi sp, sp, 0x10
-;   ld s3, -8(sp)
+;   ld s7, -8(sp)
+;   ld s9, -0x10(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 9fd4382f2..ba167eddf 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -45,7 +45,7 @@
 ;;   srli a5,a3,32
 ;;   ld a4,8(a2)
 ;;   addi a4,a4,-4
-;;   ugt a0,a5,a4##ty=i64
+;;   sltu a0,a4,a5
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a5
 ;;   li a5,0
@@ -65,7 +65,7 @@
 ;;   srli a5,a3,32
 ;;   ld a4,8(a1)
 ;;   addi a4,a4,-4
-;;   ugt a0,a5,a4##ty=i64
+;;   sltu a0,a4,a5
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a5
 ;;   li a5,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index c69f80841..994cff4df 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -47,7 +47,7 @@
 ;;   lui a5,-1
 ;;   addi a5,a5,-4
 ;;   add a4,a4,a5
-;;   ugt a4,a3,a4##ty=i64
+;;   sltu a4,a4,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   lui a3,1
@@ -71,7 +71,7 @@
 ;;   lui a4,-1
 ;;   addi a4,a4,-4
 ;;   add a2,a2,a4
-;;   ugt a2,a3,a2##ty=i64
+;;   sltu a2,a2,a3
 ;;   ld a4,0(a1)
 ;;   add a3,a4,a3
 ;;   lui a4,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 4518fae7e..ea77f187d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -49,7 +49,7 @@
 ;;   add a4,a5,a0
 ;;   trap_if heap_oob##(a4 ult a5)
 ;;   ld a0,8(a2)
-;;   ugt a0,a4,a0##ty=i64
+;;   sltu a0,a0,a4
 ;;   ld a2,0(a2)
 ;;   add a5,a2,a5
 ;;   lui a4,65535
@@ -76,7 +76,7 @@
 ;;   add a4,a5,a0
 ;;   trap_if heap_oob##(a4 ult a5)
 ;;   ld a0,8(a1)
-;;   ugt a0,a4,a0##ty=i64
+;;   sltu a0,a0,a4
 ;;   ld a1,0(a1)
 ;;   add a5,a1,a5
 ;;   lui a4,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 10d13ecfa..195c5ac3d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,17 +42,18 @@
 ;; function u0:0:
 ;; block0:
 ;;   slli a3,a0,32
-;;   srli a4,a3,32
-;;   ld a3,8(a2)
-;;   uge a5,a4,a3##ty=i64
-;;   ld a3,0(a2)
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a5
-;;   and a2,a4,a5
-;;   not a4,a5
-;;   and a5,a3,a4
-;;   or a2,a2,a5
+;;   srli a5,a3,32
+;;   ld a4,8(a2)
+;;   sltu a3,a5,a4
+;;   xori a0,a3,1
+;;   ld a4,0(a2)
+;;   add a4,a4,a5
+;;   li a5,0
+;;   sub a0,zero,a0
+;;   and a2,a5,a0
+;;   not a5,a0
+;;   and a0,a4,a5
+;;   or a2,a2,a0
 ;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
@@ -60,19 +61,20 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a2,a0,32
-;;   srli a4,a2,32
-;;   ld a3,8(a1)
-;;   uge a5,a4,a3##ty=i64
-;;   ld a3,0(a1)
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a5
-;;   and a1,a4,a5
-;;   not a4,a5
-;;   and a5,a3,a4
-;;   or a1,a1,a5
-;;   lbu a0,0(a1)
+;;   slli a3,a0,32
+;;   srli a5,a3,32
+;;   ld a4,8(a1)
+;;   sltu a3,a5,a4
+;;   xori a0,a3,1
+;;   ld a4,0(a1)
+;;   add a4,a4,a5
+;;   li a5,0
+;;   sub a0,zero,a0
+;;   and a2,a5,a0
+;;   not a5,a0
+;;   and a0,a4,a5
+;;   or a2,a2,a0
+;;   lbu a0,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index fccf05dea..43c5420c6 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -47,7 +47,7 @@
 ;;   lui a5,-1
 ;;   addi a5,a5,-1
 ;;   add a4,a4,a5
-;;   ugt a4,a3,a4##ty=i64
+;;   sltu a4,a4,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   lui a3,1
@@ -71,7 +71,7 @@
 ;;   lui a4,-1
 ;;   addi a4,a4,-1
 ;;   add a2,a2,a4
-;;   ugt a2,a3,a2##ty=i64
+;;   sltu a2,a2,a3
 ;;   ld a4,0(a1)
 ;;   add a3,a4,a3
 ;;   lui a4,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 89a40e68f..beff93305 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -47,7 +47,7 @@
 ;;   add a4,a3,a4
 ;;   trap_if heap_oob##(a4 ult a3)
 ;;   ld a5,8(a2)
-;;   ugt a4,a4,a5##ty=i64
+;;   sltu a4,a5,a4
 ;;   ld a5,0(a2)
 ;;   add a3,a5,a3
 ;;   lui a2,65535
@@ -72,7 +72,7 @@
 ;;   add a2,a3,a2
 ;;   trap_if heap_oob##(a2 ult a3)
 ;;   ld a4,8(a1)
-;;   ugt a4,a2,a4##ty=i64
+;;   sltu a4,a4,a2
 ;;   ld a5,0(a1)
 ;;   add a3,a5,a3
 ;;   lui a2,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 3b519bbb3..3b1224187 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a3,a0,32
 ;;   srli a4,a3,32
 ;;   ld a3,8(a2)
-;;   ugt a5,a4,a3##ty=i64
+;;   sltu a5,a3,a4
 ;;   ld a3,0(a2)
 ;;   add a3,a3,a4
 ;;   li a4,0
@@ -63,7 +63,7 @@
 ;;   slli a2,a0,32
 ;;   srli a4,a2,32
 ;;   ld a3,8(a1)
-;;   ugt a5,a4,a3##ty=i64
+;;   sltu a5,a3,a4
 ;;   ld a3,0(a1)
 ;;   add a3,a3,a4
 ;;   li a4,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 01043e5f4..2e3e7ff87 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a4,a0,32
 ;;   srli a0,a4,32
 ;;   ld a5,8(a2)
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
 ;;   lui a2,1
@@ -65,7 +65,7 @@
 ;;   slli a4,a0,32
 ;;   srli a0,a4,32
 ;;   ld a5,8(a1)
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
 ;;   lui a1,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 90d3740da..a84eec913 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a5,a0,32
 ;;   srli a3,a5,32
 ;;   ld a0,8(a2)
-;;   ugt a0,a3,a0##ty=i64
+;;   sltu a0,a0,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   lui a5,65535
@@ -66,7 +66,7 @@
 ;;   slli a5,a0,32
 ;;   srli a2,a5,32
 ;;   ld a0,8(a1)
-;;   ugt a0,a2,a0##ty=i64
+;;   sltu a0,a0,a2
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a2
 ;;   lui a5,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 6f7cd8d86..34d3c2fd2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,17 +42,18 @@
 ;; function u0:0:
 ;; block0:
 ;;   slli a3,a0,32
-;;   srli a4,a3,32
-;;   ld a3,8(a2)
-;;   uge a5,a4,a3##ty=i64
-;;   ld a3,0(a2)
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a5
-;;   and a2,a4,a5
-;;   not a4,a5
-;;   and a5,a3,a4
-;;   or a2,a2,a5
+;;   srli a5,a3,32
+;;   ld a4,8(a2)
+;;   sltu a3,a5,a4
+;;   xori a0,a3,1
+;;   ld a4,0(a2)
+;;   add a4,a4,a5
+;;   li a5,0
+;;   sub a0,zero,a0
+;;   and a2,a5,a0
+;;   not a5,a0
+;;   and a0,a4,a5
+;;   or a2,a2,a0
 ;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
@@ -60,19 +61,20 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a2,a0,32
-;;   srli a4,a2,32
-;;   ld a3,8(a1)
-;;   uge a5,a4,a3##ty=i64
-;;   ld a3,0(a1)
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a5
-;;   and a1,a4,a5
-;;   not a4,a5
-;;   and a5,a3,a4
-;;   or a1,a1,a5
-;;   lbu a0,0(a1)
+;;   slli a3,a0,32
+;;   srli a5,a3,32
+;;   ld a4,8(a1)
+;;   sltu a3,a5,a4
+;;   xori a0,a3,1
+;;   ld a4,0(a1)
+;;   add a4,a4,a5
+;;   li a5,0
+;;   sub a0,zero,a0
+;;   and a2,a5,a0
+;;   not a5,a0
+;;   and a0,a4,a5
+;;   or a2,a2,a0
+;;   lbu a0,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 2821b9d17..da2afc375 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a4,a0,32
 ;;   srli a0,a4,32
 ;;   ld a5,8(a2)
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
 ;;   lui a2,1
@@ -65,7 +65,7 @@
 ;;   slli a4,a0,32
 ;;   srli a0,a4,32
 ;;   ld a5,8(a1)
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
 ;;   lui a1,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 577b90de6..590e58f0a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a5,a0,32
 ;;   srli a3,a5,32
 ;;   ld a0,8(a2)
-;;   ugt a0,a3,a0##ty=i64
+;;   sltu a0,a0,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   lui a5,65535
@@ -66,7 +66,7 @@
 ;;   slli a5,a0,32
 ;;   srli a2,a5,32
 ;;   ld a0,8(a1)
-;;   ugt a0,a2,a0##ty=i64
+;;   sltu a0,a0,a2
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a2
 ;;   lui a5,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index b7787b57f..6adb604a3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -43,7 +43,7 @@
 ;; block0:
 ;;   ld a3,8(a2)
 ;;   addi a3,a3,-4
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
@@ -61,7 +61,7 @@
 ;; block0:
 ;;   ld a2,8(a1)
 ;;   addi a2,a2,-4
-;;   ugt a3,a0,a2##ty=i64
+;;   sltu a3,a2,a0
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a0
 ;;   li a4,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 34b82dfcf..3bdbeae34 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -45,7 +45,7 @@
 ;;   lui a5,-1
 ;;   addi a4,a5,-4
 ;;   add a3,a3,a4
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
 ;;   lui a2,1
@@ -67,7 +67,7 @@
 ;;   lui a5,-1
 ;;   addi a3,a5,-4
 ;;   add a2,a2,a3
-;;   ugt a2,a0,a2##ty=i64
+;;   sltu a2,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
 ;;   lui a1,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index c547318ad..7c4543ebf 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -47,7 +47,7 @@
 ;;   add a3,a0,a4
 ;;   trap_if heap_oob##(a3 ult a0)
 ;;   ld a4,8(a2)
-;;   ugt a3,a3,a4##ty=i64
+;;   sltu a3,a4,a3
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
 ;;   lui a2,65535
@@ -72,7 +72,7 @@
 ;;   add a2,a0,a4
 ;;   trap_if heap_oob##(a2 ult a0)
 ;;   ld a3,8(a1)
-;;   ugt a3,a2,a3##ty=i64
+;;   sltu a3,a3,a2
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
 ;;   lui a2,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 027b78d3d..0efa4f99d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,16 +42,17 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   uge a3,a0,a3##ty=i64
+;;   sltu a3,a0,a3
+;;   xori a3,a3,1
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
-;;   sub a3,zero,a3
-;;   and a5,a4,a3
-;;   not a3,a3
-;;   and a3,a2,a3
-;;   or a5,a5,a3
-;;   sb a1,0(a5)
+;;   sub a5,zero,a3
+;;   and a0,a4,a5
+;;   not a3,a5
+;;   and a4,a2,a3
+;;   or a0,a0,a4
+;;   sb a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
@@ -59,16 +60,17 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   uge a2,a0,a2##ty=i64
-;;   ld a1,0(a1)
-;;   add a1,a1,a0
-;;   li a3,0
-;;   sub a4,zero,a2
-;;   and a5,a3,a4
-;;   not a2,a4
-;;   and a3,a1,a2
-;;   or a5,a5,a3
-;;   lbu a0,0(a5)
+;;   sltu a2,a0,a2
+;;   xori a3,a2,1
+;;   ld a2,0(a1)
+;;   add a2,a2,a0
+;;   li a4,0
+;;   sub a5,zero,a3
+;;   and a0,a4,a5
+;;   not a3,a5
+;;   and a4,a2,a3
+;;   or a0,a0,a4
+;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 08ab99c2d..7173df6a2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -45,7 +45,7 @@
 ;;   lui a5,-1
 ;;   addi a4,a5,-1
 ;;   add a3,a3,a4
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
 ;;   lui a2,1
@@ -67,7 +67,7 @@
 ;;   lui a5,-1
 ;;   addi a3,a5,-1
 ;;   add a2,a2,a3
-;;   ugt a2,a0,a2##ty=i64
+;;   sltu a2,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
 ;;   lui a1,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 22a96a6ad..03b506de0 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,7 +45,7 @@
 ;;   add a3,a0,a3
 ;;   trap_if heap_oob##(a3 ult a0)
 ;;   ld a4,8(a2)
-;;   ugt a3,a3,a4##ty=i64
+;;   sltu a3,a4,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   lui a0,65535
@@ -68,7 +68,7 @@
 ;;   add a2,a0,a2
 ;;   trap_if heap_oob##(a2 ult a0)
 ;;   ld a3,8(a1)
-;;   ugt a2,a2,a3##ty=i64
+;;   sltu a2,a3,a2
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
 ;;   lui a0,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 8fedb3e30..e979425c8 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
@@ -59,7 +59,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   ugt a2,a0,a2##ty=i64
+;;   sltu a2,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
 ;;   li a3,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index c28aad9f1..c4222e3b4 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
 ;;   lui a5,1
@@ -61,7 +61,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a3,8(a1)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
 ;;   lui a5,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index ae2034045..859bf515f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a4,8(a2)
-;;   ugt a4,a0,a4##ty=i64
+;;   sltu a4,a4,a0
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   lui a3,65535
@@ -62,7 +62,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a4,8(a1)
-;;   ugt a4,a0,a4##ty=i64
+;;   sltu a4,a4,a0
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   lui a3,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 83d06e5f4..f07ab4fd0 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,16 +42,17 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   uge a3,a0,a3##ty=i64
+;;   sltu a3,a0,a3
+;;   xori a3,a3,1
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
-;;   sub a3,zero,a3
-;;   and a5,a4,a3
-;;   not a3,a3
-;;   and a3,a2,a3
-;;   or a5,a5,a3
-;;   sb a1,0(a5)
+;;   sub a5,zero,a3
+;;   and a0,a4,a5
+;;   not a3,a5
+;;   and a4,a2,a3
+;;   or a0,a0,a4
+;;   sb a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
@@ -59,16 +60,17 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   uge a2,a0,a2##ty=i64
-;;   ld a1,0(a1)
-;;   add a1,a1,a0
-;;   li a3,0
-;;   sub a4,zero,a2
-;;   and a5,a3,a4
-;;   not a2,a4
-;;   and a3,a1,a2
-;;   or a5,a5,a3
-;;   lbu a0,0(a5)
+;;   sltu a2,a0,a2
+;;   xori a3,a2,1
+;;   ld a2,0(a1)
+;;   add a2,a2,a0
+;;   li a4,0
+;;   sub a5,zero,a3
+;;   and a0,a4,a5
+;;   not a3,a5
+;;   and a4,a2,a3
+;;   or a0,a0,a4
+;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 01ef715b0..a6025c9f4 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
 ;;   lui a5,1
@@ -61,7 +61,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a3,8(a1)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
 ;;   lui a5,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 63f670506..f145cd59b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a4,8(a2)
-;;   ugt a4,a0,a4##ty=i64
+;;   sltu a4,a4,a0
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   lui a3,65535
@@ -62,7 +62,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a4,8(a1)
-;;   ugt a4,a0,a4##ty=i64
+;;   sltu a4,a4,a0
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   lui a3,65535
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 2a05a2b2b..6c9f95e11 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli a5,a3,32
 ;;   lui a3,65536
 ;;   addi a0,a3,-4
-;;   ugt a0,a5,a0##ty=i64
+;;   sltu a0,a0,a5
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a5
 ;;   li a5,0
@@ -63,7 +63,7 @@
 ;;   srli a5,a3,32
 ;;   lui a3,65536
 ;;   addi a0,a3,-4
-;;   ugt a0,a5,a0##ty=i64
+;;   sltu a0,a0,a5
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a5
 ;;   li a5,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 7226d3aed..eb11c6b63 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli a3,a5,32
 ;;   lui a5,65535
 ;;   addi a4,a5,-4
-;;   ugt a0,a3,a4##ty=i64
+;;   sltu a0,a4,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   lui a3,1
@@ -65,7 +65,7 @@
 ;;   srli a2,a5,32
 ;;   lui a5,65535
 ;;   addi a3,a5,-4
-;;   ugt a0,a2,a3##ty=i64
+;;   sltu a0,a3,a2
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a2
 ;;   lui a2,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 1bcdace5b..27e8e0ab9 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli a5,a3,32
 ;;   lui a3,65536
 ;;   addi a0,a3,-1
-;;   ugt a0,a5,a0##ty=i64
+;;   sltu a0,a0,a5
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a5
 ;;   li a5,0
@@ -63,7 +63,7 @@
 ;;   srli a5,a3,32
 ;;   lui a3,65536
 ;;   addi a0,a3,-1
-;;   ugt a0,a5,a0##ty=i64
+;;   sltu a0,a0,a5
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a5
 ;;   li a5,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 259243c2a..dda7c67f2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli a3,a5,32
 ;;   lui a5,65535
 ;;   addi a4,a5,-1
-;;   ugt a0,a3,a4##ty=i64
+;;   sltu a0,a4,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   lui a3,1
@@ -65,7 +65,7 @@
 ;;   srli a2,a5,32
 ;;   lui a5,65535
 ;;   addi a3,a5,-1
-;;   ugt a0,a2,a3##ty=i64
+;;   sltu a0,a3,a2
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a2
 ;;   lui a2,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index e6c5a9493..750ec5218 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65536
 ;;   addi a3,a3,-4
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a2,65536
 ;;   addi a3,a2,-4
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a0
 ;;   li a4,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index a3cf5dc1e..fd8115156 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-4
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   lui a0,1
@@ -61,7 +61,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-4
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   lui a0,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 35e0c379a..f1c507233 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65536
 ;;   addi a3,a3,-1
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a2,65536
 ;;   addi a3,a2,-1
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a0
 ;;   li a4,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 05cb5d9cb..724f21d94 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-1
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   lui a0,1
@@ -61,7 +61,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-1
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   lui a0,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 1300e0e52..50f72079b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65536
 ;;   addi a3,a3,-4
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a2,65536
 ;;   addi a3,a2,-4
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a0
 ;;   li a4,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 6b7acc5ca..0a91b43fc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-4
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   lui a0,1
@@ -61,7 +61,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-4
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   lui a0,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index d882575d6..522b63438 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65536
 ;;   addi a3,a3,-1
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   li a4,0
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a2,65536
 ;;   addi a3,a2,-1
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a0
 ;;   li a4,0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index f10b7d2e8..51445a070 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-1
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   lui a0,1
@@ -61,7 +61,7 @@
 ;; block0:
 ;;   lui a3,65535
 ;;   addi a5,a3,-1
-;;   ugt a4,a0,a5##ty=i64
+;;   sltu a4,a5,a0
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   lui a0,1
diff --git a/cranelift/filetests/filetests/isa/riscv64/zca.clif b/cranelift/filetests/filetests/isa/riscv64/zca.clif
index b49fd2d63..982dadb85 100644
--- a/cranelift/filetests/filetests/isa/riscv64/zca.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/zca.clif
@@ -535,6 +535,43 @@ block0:
 ;   c.addi16sp sp, 0x10
 ;   c.jr ra
 
+function %c_addi4spn_512() -> i64 {
+  ss0 = explicit_slot 1024
+
+block0:
+  v0 = stack_addr.i64 ss0+512
+  return v0
+}
+
+; VCode:
+;   add sp,-16
+;   sd ra,8(sp)
+;   sd fp,0(sp)
+;   mv fp,sp
+;   add sp,-1024
+; block0:
+;   load_addr a0,512(nominal_sp)
+;   add sp,+1024
+;   ld ra,8(sp)
+;   ld fp,0(sp)
+;   add sp,+16
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   c.addi16sp sp, -0x10
+;   c.sdsp ra, 8(sp)
+;   c.sdsp s0, 0(sp)
+;   c.mv s0, sp
+;   addi sp, sp, -0x400
+; block1: ; offset 0xc
+;   c.addi4spn a0, sp, 0x200
+;   addi sp, sp, 0x400
+;   c.ldsp ra, 8(sp)
+;   c.ldsp s0, 0(sp)
+;   c.addi16sp sp, 0x10
+;   c.jr ra
+
 function %c_li() -> i64 {
 block0:
   v0 = iconst.i64 1
diff --git a/cranelift/filetests/filetests/runtests/i128-icmp.clif b/cranelift/filetests/filetests/runtests/i128-icmp.clif
index 75559b4b9..8db45d6bc 100644
--- a/cranelift/filetests/filetests/runtests/i128-icmp.clif
+++ b/cranelift/filetests/filetests/runtests/i128-icmp.clif
@@ -21,6 +21,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_eq_i128(0xDECAFFFF_C0FFEEEE_C0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE_C0FFEEEE_DECAFFFF) == 1
 ; run: %icmp_eq_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF, 0x00000000_00000001_00000000_00000001) == 0
 ; run: %icmp_eq_i128(0x00000000_00000001_FFFFFFFF_FFFFFFFF, 0x00000000_00000001_00000000_00000001) == 0
+; run: %icmp_eq_i128(0xffffffff_ffffffff, 0) == 0
 
 ; This is a regression test for aarch64, see: https://github.com/bytecodealliance/wasmtime/issues/4705
 ; run: %icmp_eq_i128(36893488147419103231, 0) == 0
@@ -40,6 +41,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_ne_i128(0xDECAFFFF_C0FFEEEE_C0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE_C0FFEEEE_DECAFFFF) == 0
 ; run: %icmp_ne_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF, 0x00000000_00000001_00000000_00000001) == 1
 ; run: %icmp_ne_i128(0x00000000_00000001_FFFFFFFF_FFFFFFFF, 0x00000000_00000001_00000000_00000001) == 1
+; run: %icmp_ne_i128(0xffffffff_ffffffff, 0) == 1
 
 
 
@@ -57,6 +59,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_slt_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 1
 ; run: %icmp_slt_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 1
 ; run: %icmp_slt_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 0
+; run: %icmp_slt_i128(0xffffffff_ffffffff, 0) == 0
 
 
 function %icmp_ult_i128(i128, i128) -> i8 {
@@ -73,6 +76,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_ult_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 1
 ; run: %icmp_ult_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 1
 ; run: %icmp_ult_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 0
+; run: %icmp_ult_i128(0xffffffff_ffffffff, 0) == 0
 
 
 function %icmp_sle_i128(i128, i128) -> i8 {
@@ -89,6 +93,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_sle_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 1
 ; run: %icmp_sle_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 1
 ; run: %icmp_sle_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 0
+; run: %icmp_sle_i128(0xffffffff_ffffffff, 0) == 0
 
 
 function %icmp_ule_i128(i128, i128) -> i8 {
@@ -105,6 +110,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_ule_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 1
 ; run: %icmp_ule_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 1
 ; run: %icmp_ule_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 0
+; run: %icmp_ule_i128(0xffffffff_ffffffff, 0) == 0
 
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
@@ -121,6 +127,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_sgt_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 0
 ; run: %icmp_sgt_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 0
 ; run: %icmp_sgt_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 1
+; run: %icmp_sgt_i128(0xffffffff_ffffffff, 0) == 1
 
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
@@ -137,6 +144,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_ugt_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 0
 ; run: %icmp_ugt_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 0
 ; run: %icmp_ugt_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 1
+; run: %icmp_ugt_i128(0xffffffff_ffffffff, 0) == 1
 
 
 function %icmp_sge_i128(i128, i128) -> i8 {
@@ -153,6 +161,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_sge_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 0
 ; run: %icmp_sge_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 0
 ; run: %icmp_sge_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 1
+; run: %icmp_sge_i128(0xffffffff_ffffffff, 0) == 1
 
 
 function %icmp_uge_i128(i128, i128) -> i8 {
@@ -169,6 +178,7 @@ block0(v0: i128, v1: i128):
 ; run: %icmp_uge_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFD, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 0
 ; run: %icmp_uge_i128(0xC0FFEEEE_C0FFEEEE_00000000_00000000, 0xDECAFFFF_DECAFFFF_00000000_00000000) == 0
 ; run: %icmp_uge_i128(0xDECAFFFF_DECAFFFF_00000000_00000000, 0xC0FFEEEE_C0FFEEEE_00000000_00000000) == 1
+; run: %icmp_uge_i128(0xffffffff_ffffffff, 0) == 1
 
 
 ; Icmp Imm Tests
diff --git a/cranelift/filetests/filetests/runtests/icmp-uge.clif b/cranelift/filetests/filetests/runtests/icmp-uge.clif
index 72ef20767..0459baf43 100644
--- a/cranelift/filetests/filetests/runtests/icmp-uge.clif
+++ b/cranelift/filetests/filetests/runtests/icmp-uge.clif
@@ -53,3 +53,13 @@ block0(v0: i64, v1: i64):
 ; run: %icmp_uge_i64(0, 1) == 0
 ; run: %icmp_uge_i64(-5, -1) == 0
 ; run: %icmp_uge_i64(1, -1) == 0
+
+
+function %constant_inputs() -> i8 {
+block0:
+    v9 = iconst.i8 128
+    v11 = iconst.i8 0
+    v17 = icmp uge v9, v11
+    return v17
+}
+; run: %constant_inputs() == 1
diff --git a/cranelift/filetests/filetests/runtests/icmp-ugt.clif b/cranelift/filetests/filetests/runtests/icmp-ugt.clif
index 3d2d33056..274444262 100644
--- a/cranelift/filetests/filetests/runtests/icmp-ugt.clif
+++ b/cranelift/filetests/filetests/runtests/icmp-ugt.clif
@@ -53,3 +53,13 @@ block0(v0: i64, v1: i64):
 ; run: %icmp_ugt_i64(0, 1) == 0
 ; run: %icmp_ugt_i64(-5, -1) == 0
 ; run: %icmp_ugt_i64(1, -1) == 0
+
+
+function %icmp_ugt_const() -> i8  {
+block0:
+    v11 = iconst.i8 196
+    v17 = icmp ugt v11, v11
+    return v17
+}
+
+; run: %icmp_ugt_const() == 0
diff --git a/tests/all/cli_tests.rs b/tests/all/cli_tests.rs
index a114e2a3e..997738cdd 100644
--- a/tests/all/cli_tests.rs
+++ b/tests/all/cli_tests.rs
@@ -32,7 +32,7 @@ pub fn get_wasmtime_command() -> Result<Command> {
     // If we're running tests with a "runner" then we might be doing something
     // like cross-emulation, so spin up the emulator rather than the tests
     // itself, which may not be natively executable.
-    let mut cmd = if let Some((_, runner)) = runner {
+    let cmd = if let Some((_, runner)) = runner {
         let mut parts = runner.split_whitespace();
         let mut cmd = Command::new(parts.next().unwrap());
         for arg in parts {
@@ -44,10 +44,6 @@ pub fn get_wasmtime_command() -> Result<Command> {
         Command::new(&me)
     };
 
-    if let Ok(val) = std::env::var("WASMTIME_LOG") {
-        cmd.env("WASMTIME_LOG", val);
-    }
-
     Ok(cmd)
 }