Repository: bytecodealliance/wasmtime
Pull request #8311 (2024-04-05 22:26:28)

cranelift/riscv64: Remove unused type parameters from address modes
This backend copied the general style of the aarch64 backend's address modes but has no use for a type field in address modes. Just delete them.

Between this and #8308, there are no types in target dependent address modes now. The next step is to delete them from the target independent `StackAMode` as well.


Patch:
diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs
index 7f5903dac..94b5897b6 100644
--- a/cranelift/codegen/src/isa/aarch64/abi.rs
+++ b/cranelift/codegen/src/isa/aarch64/abi.rs
@@ -36,9 +36,9 @@ impl Into<AMode> for StackAMode {
     fn into(self) -> AMode {
         match self {
             // Argument area begins after saved frame pointer + return address.
-            StackAMode::ArgOffset(off, ty) => AMode::FPOffset { off: off + 16, ty },
-            StackAMode::NominalSPOffset(off, ty) => AMode::NominalSPOffset { off, ty },
-            StackAMode::SPOffset(off, ty) => AMode::SPOffset { off, ty },
+            StackAMode::ArgOffset(off, _ty) => AMode::FPOffset { off: off + 16 },
+            StackAMode::NominalSPOffset(off, _ty) => AMode::NominalSPOffset { off },
+            StackAMode::SPOffset(off, _ty) => AMode::SPOffset { off },
         }
     }
 }
@@ -471,7 +471,6 @@ impl ABIMachineSpec for AArch64MachineDeps {
         let mem = AMode::RegOffset {
             rn: base,
             off: offset as i64,
-            ty,
         };
         Inst::gen_load(into_reg, mem, ty, MemFlags::trusted())
     }
@@ -480,7 +479,6 @@ impl ABIMachineSpec for AArch64MachineDeps {
         let mem = AMode::RegOffset {
             rn: base,
             off: offset as i64,
-            ty,
         };
         Inst::gen_store(mem, from_reg, ty, MemFlags::trusted())
     }
@@ -1190,7 +1188,7 @@ impl AArch64MachineDeps {
             insts.extend(Self::gen_sp_reg_adjust(-(guard_size as i32)));
 
             insts.push(Inst::gen_store(
-                AMode::SPOffset { off: 0, ty: I8 },
+                AMode::SPOffset { off: 0 },
                 zero_reg(),
                 I32,
                 MemFlags::trusted(),
diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle
index 51107ab36..f706f8048 100644
--- a/cranelift/codegen/src/isa/aarch64/inst.isle
+++ b/cranelift/codegen/src/isa/aarch64/inst.isle
@@ -1119,15 +1119,13 @@
         ;; Register plus register offset, scaled by type's size.
         (RegScaled
          (rn Reg)
-         (rm Reg)
-         (ty Type))
+         (rm Reg))
 
         ;; Register plus register offset, scaled by type's size, with index
         ;; sign- or zero-extended first.
         (RegScaledExtended
          (rn Reg)
          (rm Reg)
-         (ty Type)
          (extendop ExtendOp))
 
         ;; Register plus register offset, with index sign- or zero-extended
@@ -1157,18 +1155,15 @@
         ;; offsets with multiple instructions as necessary during code emission.
         (RegOffset
          (rn Reg)
-         (off i64)
-         (ty Type))
+         (off i64))
 
         ;; Offset from the stack pointer.
         (SPOffset
-         (off i64)
-         (ty Type))
+         (off i64))
 
         ;; Offset from the frame pointer.
         (FPOffset
-         (off i64)
-         (ty Type))
+         (off i64))
 
         ;; A reference to a constant which is placed outside of the function's
         ;; body, typically at the end.
@@ -1188,8 +1183,7 @@
         ;; clobber pushes. See the diagram in the documentation for
         ;; [crate::isa::aarch64::abi](the ABI module) for more details.
         (NominalSPOffset
-         (off i64)
-         (ty Type))))
+         (off i64))))
 
 ;; A memory argument to a load/store-pair.
 (type PairAMode (enum
@@ -3169,18 +3163,18 @@
 ;; first and then if that succeeds afterwards try to find an extend.
 (rule 6 (amode_no_more_iconst ty (iadd x (ishl y (iconst (u64_from_imm64 n)))) offset)
         (if-let $true (u64_eq (ty_bytes ty) (u64_shl 1 n)))
-        (amode_reg_scaled (amode_add x offset) y ty))
+        (amode_reg_scaled (amode_add x offset) y))
 (rule 7 (amode_no_more_iconst ty (iadd (ishl y (iconst (u64_from_imm64 n))) x) offset)
         (if-let $true (u64_eq (ty_bytes ty) (u64_shl 1 n)))
-        (amode_reg_scaled (amode_add x offset) y ty))
+        (amode_reg_scaled (amode_add x offset) y))
 
-(decl amode_reg_scaled (Reg Value Type) AMode)
-(rule 0 (amode_reg_scaled base index ty)
-        (AMode.RegScaled base index ty))
-(rule 1 (amode_reg_scaled base (uextend index @ (value_type $I32)) ty)
-        (AMode.RegScaledExtended base index ty (ExtendOp.UXTW)))
-(rule 2 (amode_reg_scaled base (sextend index @ (value_type $I32)) ty)
-        (AMode.RegScaledExtended base index ty (ExtendOp.SXTW)))
+(decl amode_reg_scaled (Reg Value) AMode)
+(rule 0 (amode_reg_scaled base index)
+        (AMode.RegScaled base index))
+(rule 1 (amode_reg_scaled base (uextend index @ (value_type $I32)))
+        (AMode.RegScaledExtended base index (ExtendOp.UXTW)))
+(rule 1 (amode_reg_scaled base (sextend index @ (value_type $I32)))
+        (AMode.RegScaledExtended base index (ExtendOp.SXTW)))
 
 ;; Helper to add a 32-bit signed immediate to the register provided. This will
 ;; select an appropriate `add` instruction to use.
@@ -3519,7 +3513,7 @@
             ;; the frame record that corresponds to the current subroutine on
             ;; the stack; the presence of the record is guaranteed by the
             ;; `preserve_frame_pointers` setting.
-            (addr AMode (AMode.FPOffset 8 $I64))
+            (addr AMode (AMode.FPOffset 8))
             (_ Unit (emit (MInst.ULoad64 dst addr (mem_flags_trusted)))))
            dst))
 
@@ -3529,7 +3523,7 @@
       ;; the frame record. Furthermore, we can use LR as a scratch register
       ;; because the function will set it to the return address immediately
       ;; before returning.
-      (let ((addr AMode (AMode.FPOffset 8 $I64))
+      (let ((addr AMode (AMode.FPOffset 8))
             (lr WritableReg (writable_link_reg))
             (_ Unit (emit (MInst.ULoad64 lr addr (mem_flags_trusted))))
             (_ Unit (emit (MInst.Xpaclri))))
diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs
index a9f185bf6..3375215d2 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/args.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs
@@ -138,11 +138,10 @@ impl AMode {
 
     /// Memory reference using `reg1 + sizeof(ty) * reg2` as an address, with `reg2` sign- or
     /// zero-extended as per `op`.
-    pub fn reg_plus_reg_scaled_extended(reg1: Reg, reg2: Reg, ty: Type, op: ExtendOp) -> AMode {
+    pub fn reg_plus_reg_scaled_extended(reg1: Reg, reg2: Reg, op: ExtendOp) -> AMode {
         AMode::RegScaledExtended {
             rn: reg1,
             rm: reg2,
-            ty,
             extendop: op,
         }
     }
@@ -162,20 +161,13 @@ impl AMode {
                 rn: allocs.next(rn),
                 rm: allocs.next(rm),
             },
-            &AMode::RegScaled { rn, rm, ty } => AMode::RegScaled {
+            &AMode::RegScaled { rn, rm } => AMode::RegScaled {
                 rn: allocs.next(rn),
                 rm: allocs.next(rm),
-                ty,
             },
-            &AMode::RegScaledExtended {
-                rn,
-                rm,
-                ty,
-                extendop,
-            } => AMode::RegScaledExtended {
+            &AMode::RegScaledExtended { rn, rm, extendop } => AMode::RegScaledExtended {
                 rn: allocs.next(rn),
                 rm: allocs.next(rm),
-                ty,
                 extendop,
             },
             &AMode::RegExtended { rn, rm, extendop } => AMode::RegExtended {
@@ -183,10 +175,9 @@ impl AMode {
                 rm: allocs.next(rm),
                 extendop,
             },
-            &AMode::RegOffset { rn, off, ty } => AMode::RegOffset {
+            &AMode::RegOffset { rn, off } => AMode::RegOffset {
                 rn: allocs.next(rn),
                 off,
-                ty,
             },
             &AMode::SPPreIndexed { .. }
             | &AMode::SPPostIndexed { .. }
@@ -385,19 +376,20 @@ impl PrettyPrint for MemLabel {
     }
 }
 
-fn shift_for_type(ty: Type) -> usize {
-    match ty.bytes() {
+fn shift_for_type(size_bytes: u8) -> usize {
+    match size_bytes {
         1 => 0,
         2 => 1,
         4 => 2,
         8 => 3,
         16 => 4,
-        _ => panic!("unknown type: {}", ty),
+        _ => panic!("unknown type size: {size_bytes}"),
     }
 }
 
 impl PrettyPrint for AMode {
-    fn pretty_print(&self, _: u8, allocs: &mut AllocationConsumer<'_>) -> String {
+    fn pretty_print(&self, size_bytes: u8, allocs: &mut AllocationConsumer<'_>) -> String {
+        debug_assert!(size_bytes != 0);
         match self {
             &AMode::Unscaled { rn, simm9 } => {
                 let reg = pretty_print_reg(rn, allocs);
@@ -410,7 +402,7 @@ impl PrettyPrint for AMode {
             }
             &AMode::UnsignedOffset { rn, uimm12 } => {
                 let reg = pretty_print_reg(rn, allocs);
-                if uimm12.value != 0 {
+                if uimm12.value() != 0 {
                     let uimm12 = uimm12.pretty_print(8, allocs);
                     format!("[{}, {}]", reg, uimm12)
                 } else {
@@ -422,19 +414,14 @@ impl PrettyPrint for AMode {
                 let r2 = pretty_print_reg(rm, allocs);
                 format!("[{}, {}]", r1, r2)
             }
-            &AMode::RegScaled { rn, rm, ty } => {
+            &AMode::RegScaled { rn, rm } => {
                 let r1 = pretty_print_reg(rn, allocs);
                 let r2 = pretty_print_reg(rm, allocs);
-                let shift = shift_for_type(ty);
+                let shift = shift_for_type(size_bytes);
                 format!("[{}, {}, LSL #{}]", r1, r2, shift)
             }
-            &AMode::RegScaledExtended {
-                rn,
-                rm,
-                ty,
-                extendop,
-            } => {
-                let shift = shift_for_type(ty);
+            &AMode::RegScaledExtended { rn, rm, extendop } => {
+                let shift = shift_for_type(size_bytes);
                 let size = match extendop {
                     ExtendOp::SXTW | ExtendOp::UXTW => OperandSize::Size32,
                     _ => OperandSize::Size64,
diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
index b02fe200e..df840e5b1 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -15,13 +15,14 @@ use crate::trace;
 pub fn mem_finalize(
     sink: Option<&mut MachBuffer<Inst>>,
     mem: &AMode,
+    access_ty: Type,
     state: &EmitState,
 ) -> (SmallVec<[Inst; 4]>, AMode) {
     match mem {
-        &AMode::RegOffset { off, ty, .. }
-        | &AMode::SPOffset { off, ty }
-        | &AMode::FPOffset { off, ty }
-        | &AMode::NominalSPOffset { off, ty } => {
+        &AMode::RegOffset { off, .. }
+        | &AMode::SPOffset { off }
+        | &AMode::FPOffset { off }
+        | &AMode::NominalSPOffset { off } => {
             let basereg = match mem {
                 &AMode::RegOffset { rn, .. } => rn,
                 &AMode::SPOffset { .. } | &AMode::NominalSPOffset { .. } => stack_reg(),
@@ -45,7 +46,7 @@ pub fn mem_finalize(
             if let Some(simm9) = SImm9::maybe_from_i64(off) {
                 let mem = AMode::Unscaled { rn: basereg, simm9 };
                 (smallvec![], mem)
-            } else if let Some(uimm12) = UImm12Scaled::maybe_from_i64(off, ty) {
+            } else if let Some(uimm12) = UImm12Scaled::maybe_from_i64(off, access_ty) {
                 let mem = AMode::UnsignedOffset {
                     rn: basereg,
                     uimm12,
@@ -979,7 +980,8 @@ impl MachInstEmit for Inst {
             | &Inst::FpuLoad128 { rd, ref mem, flags } => {
                 let rd = allocs.next_writable(rd);
                 let mem = mem.with_allocs(&mut allocs);
-                let (mem_insts, mem) = mem_finalize(Some(sink), &mem, state);
+                let access_ty = self.mem_type().unwrap();
+                let (mem_insts, mem) = mem_finalize(Some(sink), &mem, access_ty, state);
 
                 for inst in mem_insts.into_iter() {
                     inst.emit(&[], sink, emit_info, state);
@@ -991,17 +993,17 @@ impl MachInstEmit for Inst {
                 // This is the base opcode (top 10 bits) for the "unscaled
                 // immediate" form (Unscaled). Other addressing modes will OR in
                 // other values for bits 24/25 (bits 1/2 of this constant).
-                let (op, bits) = match self {
-                    &Inst::ULoad8 { .. } => (0b0011100001, 8),
-                    &Inst::SLoad8 { .. } => (0b0011100010, 8),
-                    &Inst::ULoad16 { .. } => (0b0111100001, 16),
-                    &Inst::SLoad16 { .. } => (0b0111100010, 16),
-                    &Inst::ULoad32 { .. } => (0b1011100001, 32),
-                    &Inst::SLoad32 { .. } => (0b1011100010, 32),
-                    &Inst::ULoad64 { .. } => (0b1111100001, 64),
-                    &Inst::FpuLoad32 { .. } => (0b1011110001, 32),
-                    &Inst::FpuLoad64 { .. } => (0b1111110001, 64),
-                    &Inst::FpuLoad128 { .. } => (0b0011110011, 128),
+                let op = match self {
+                    Inst::ULoad8 { .. } => 0b0011100001,
+                    Inst::SLoad8 { .. } => 0b0011100010,
+                    Inst::ULoad16 { .. } => 0b0111100001,
+                    Inst::SLoad16 { .. } => 0b0111100010,
+                    Inst::ULoad32 { .. } => 0b1011100001,
+                    Inst::SLoad32 { .. } => 0b1011100010,
+                    Inst::ULoad64 { .. } => 0b1111100001,
+                    Inst::FpuLoad32 { .. } => 0b1011110001,
+                    Inst::FpuLoad64 { .. } => 0b1111110001,
+                    Inst::FpuLoad128 { .. } => 0b0011110011,
                     _ => unreachable!(),
                 };
 
@@ -1017,9 +1019,6 @@ impl MachInstEmit for Inst {
                     }
                     &AMode::UnsignedOffset { rn, uimm12 } => {
                         let reg = allocs.next(rn);
-                        if uimm12.value() != 0 {
-                            assert_eq!(bits, ty_bits(uimm12.scale_ty()));
-                        }
                         sink.put4(enc_ldst_uimm12(op, uimm12, reg, rd));
                     }
                     &AMode::RegReg { rn, rm } => {
@@ -1029,11 +1028,9 @@ impl MachInstEmit for Inst {
                             op, r1, r2, /* scaled = */ false, /* extendop = */ None, rd,
                         ));
                     }
-                    &AMode::RegScaled { rn, rm, ty }
-                    | &AMode::RegScaledExtended { rn, rm, ty, .. } => {
+                    &AMode::RegScaled { rn, rm } | &AMode::RegScaledExtended { rn, rm, .. } => {
                         let r1 = allocs.next(rn);
                         let r2 = allocs.next(rm);
-                        assert_eq!(bits, ty_bits(ty));
                         let extendop = match &mem {
                             &AMode::RegScaled { .. } => None,
                             &AMode::RegScaledExtended { extendop, .. } => Some(extendop),
@@ -1123,20 +1120,21 @@ impl MachInstEmit for Inst {
             | &Inst::FpuStore128 { rd, ref mem, flags } => {
                 let rd = allocs.next(rd);
                 let mem = mem.with_allocs(&mut allocs);
-                let (mem_insts, mem) = mem_finalize(Some(sink), &mem, state);
+                let access_ty = self.mem_type().unwrap();
+                let (mem_insts, mem) = mem_finalize(Some(sink), &mem, access_ty, state);
 
                 for inst in mem_insts.into_iter() {
                     inst.emit(&[], sink, emit_info, state);
                 }
 
-                let (op, bits) = match self {
-                    &Inst::Store8 { .. } => (0b0011100000, 8),
-                    &Inst::Store16 { .. } => (0b0111100000, 16),
-                    &Inst::Store32 { .. } => (0b1011100000, 32),
-                    &Inst::Store64 { .. } => (0b1111100000, 64),
-                    &Inst::FpuStore32 { .. } => (0b1011110000, 32),
-                    &Inst::FpuStore64 { .. } => (0b1111110000, 64),
-                    &Inst::FpuStore128 { .. } => (0b0011110010, 128),
+                let op = match self {
+                    Inst::Store8 { .. } => 0b0011100000,
+                    Inst::Store16 { .. } => 0b0111100000,
+                    Inst::Store32 { .. } => 0b1011100000,
+                    Inst::Store64 { .. } => 0b1111100000,
+                    Inst::FpuStore32 { .. } => 0b1011110000,
+                    Inst::FpuStore64 { .. } => 0b1111110000,
+                    Inst::FpuStore128 { .. } => 0b0011110010,
                     _ => unreachable!(),
                 };
 
@@ -1152,9 +1150,6 @@ impl MachInstEmit for Inst {
                     }
                     &AMode::UnsignedOffset { rn, uimm12 } => {
                         let reg = allocs.next(rn);
-                        if uimm12.value() != 0 {
-                            assert_eq!(bits, ty_bits(uimm12.scale_ty()));
-                        }
                         sink.put4(enc_ldst_uimm12(op, uimm12, reg, rd));
                     }
                     &AMode::RegReg { rn, rm } => {
@@ -1164,7 +1159,7 @@ impl MachInstEmit for Inst {
                             op, r1, r2, /* scaled = */ false, /* extendop = */ None, rd,
                         ));
                     }
-                    &AMode::RegScaled { rn, rm, .. } | &AMode::RegScaledExtended { rn, rm, .. } => {
+                    &AMode::RegScaled { rn, rm } | &AMode::RegScaledExtended { rn, rm, .. } => {
                         let r1 = allocs.next(rn);
                         let r2 = allocs.next(rm);
                         let extendop = match &mem {
@@ -3341,7 +3336,6 @@ impl MachInstEmit for Inst {
                     mem: AMode::reg_plus_reg_scaled_extended(
                         rtmp1.to_reg(),
                         rtmp2.to_reg(),
-                        I32,
                         ExtendOp::UXTW,
                     ),
                     flags: MemFlags::trusted(),
@@ -3436,7 +3430,7 @@ impl MachInstEmit for Inst {
             &Inst::LoadAddr { rd, ref mem } => {
                 let rd = allocs.next_writable(rd);
                 let mem = mem.with_allocs(&mut allocs);
-                let (mem_insts, mem) = mem_finalize(Some(sink), &mem, state);
+                let (mem_insts, mem) = mem_finalize(Some(sink), &mem, I8, state);
                 for inst in mem_insts.into_iter() {
                     inst.emit(&[], sink, emit_info, state);
                 }
@@ -3874,7 +3868,6 @@ fn emit_return_call_common_sequence(
             rd: tmp2,
             mem: AMode::SPOffset {
                 off: i64::from(i * 8),
-                ty: types::I64,
             },
             flags: ir::MemFlags::trusted(),
         }
@@ -3886,7 +3879,6 @@ fn emit_return_call_common_sequence(
             rd: tmp2.to_reg(),
             mem: AMode::FPOffset {
                 off: fp_to_callee_sp + i64::from(i * 8),
-                ty: types::I64,
             },
             flags: ir::MemFlags::trusted(),
         }
diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs
index cd8a2aa76..b87209dda 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs
@@ -220,9 +220,9 @@ impl SImm9 {
 #[derive(Clone, Copy, Debug)]
 pub struct UImm12Scaled {
     /// The value.
-    pub value: u16,
+    value: u16,
     /// multiplied by the size of this type
-    pub scale_ty: Type,
+    scale_ty: Type,
 }
 
 impl UImm12Scaled {
@@ -257,11 +257,6 @@ impl UImm12Scaled {
     pub fn value(&self) -> u32 {
         self.value as u32
     }
-
-    /// The value type which is the scaling base.
-    pub fn scale_ty(&self) -> Type {
-        self.scale_ty
-    }
 }
 
 /// A shifted immediate value in 'imm12' format: supports 12 bits, shifted
diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index 82fdccab8..e1447d60a 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -367,6 +367,32 @@ impl Inst {
             }
         }
     }
+
+    /// What type does this load or store instruction access in memory? When
+    /// uimm12 encoding is used, the size of this type is the amount that
+    /// immediate offsets are scaled by.
+    pub fn mem_type(&self) -> Option<Type> {
+        match self {
+            Inst::ULoad8 { .. } => Some(I8),
+            Inst::SLoad8 { .. } => Some(I8),
+            Inst::ULoad16 { .. } => Some(I16),
+            Inst::SLoad16 { .. } => Some(I16),
+            Inst::ULoad32 { .. } => Some(I32),
+            Inst::SLoad32 { .. } => Some(I32),
+            Inst::ULoad64 { .. } => Some(I64),
+            Inst::FpuLoad32 { .. } => Some(F32),
+            Inst::FpuLoad64 { .. } => Some(F64),
+            Inst::FpuLoad128 { .. } => Some(I8X16),
+            Inst::Store8 { .. } => Some(I8),
+            Inst::Store16 { .. } => Some(I16),
+            Inst::Store32 { .. } => Some(I32),
+            Inst::Store64 { .. } => Some(I64),
+            Inst::FpuStore32 { .. } => Some(F32),
+            Inst::FpuStore64 { .. } => Some(F64),
+            Inst::FpuStore128 { .. } => Some(I8X16),
+            _ => None,
+        }
+    }
 }
 
 //=============================================================================
@@ -1211,8 +1237,8 @@ impl MachInst for Inst {
 //=============================================================================
 // Pretty-printing of instructions.
 
-fn mem_finalize_for_show(mem: &AMode, state: &EmitState) -> (String, AMode) {
-    let (mem_insts, mem) = mem_finalize(None, mem, state);
+fn mem_finalize_for_show(mem: &AMode, access_ty: Type, state: &EmitState) -> (String, String) {
+    let (mem_insts, mem) = mem_finalize(None, mem, access_ty, state);
     let mut mem_str = mem_insts
         .into_iter()
         .map(|inst| {
@@ -1224,6 +1250,7 @@ fn mem_finalize_for_show(mem: &AMode, state: &EmitState) -> (String, AMode) {
         mem_str += " ; ";
     }
 
+    let mem = mem.pretty_print(access_ty.bytes() as u8, &mut AllocationConsumer::new(&[]));
     (mem_str, mem)
 }
 
@@ -1411,8 +1438,8 @@ impl Inst {
 
                 let rd = pretty_print_ireg(rd.to_reg(), size, allocs);
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
 
                 format!("{}{} {}, {}", mem_str, op, rd, mem)
             }
@@ -1438,8 +1465,8 @@ impl Inst {
 
                 let rd = pretty_print_ireg(rd, size, allocs);
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
 
                 format!("{}{} {}, {}", mem_str, op, rd, mem)
             }
@@ -1822,45 +1849,45 @@ impl Inst {
             &Inst::FpuLoad32 { rd, ref mem, .. } => {
                 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size32, allocs);
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
                 format!("{}ldr {}, {}", mem_str, rd, mem)
             }
             &Inst::FpuLoad64 { rd, ref mem, .. } => {
                 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64, allocs);
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
                 format!("{}ldr {}, {}", mem_str, rd, mem)
             }
             &Inst::FpuLoad128 { rd, ref mem, .. } => {
                 let rd = pretty_print_reg(rd.to_reg(), allocs);
                 let rd = "q".to_string() + &rd[1..];
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
                 format!("{}ldr {}, {}", mem_str, rd, mem)
             }
             &Inst::FpuStore32 { rd, ref mem, .. } => {
                 let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size32, allocs);
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
                 format!("{}str {}, {}", mem_str, rd, mem)
             }
             &Inst::FpuStore64 { rd, ref mem, .. } => {
                 let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size64, allocs);
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
                 format!("{}str {}, {}", mem_str, rd, mem)
             }
             &Inst::FpuStore128 { rd, ref mem, .. } => {
                 let rd = pretty_print_reg(rd, allocs);
                 let rd = "q".to_string() + &rd[1..];
                 let mem = mem.with_allocs(allocs);
-                let (mem_str, mem) = mem_finalize_for_show(&mem, state);
-                let mem = mem.pretty_print_default();
+                let access_ty = self.mem_type().unwrap();
+                let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
                 format!("{}str {}, {}", mem_str, rd, mem)
             }
             &Inst::FpuLoadP64 {
@@ -2771,7 +2798,7 @@ impl Inst {
                 // of the existing legalization framework).
                 let rd = allocs.next_writable(rd);
                 let mem = mem.with_allocs(allocs);
-                let (mem_insts, mem) = mem_finalize(None, &mem, state);
+                let (mem_insts, mem) = mem_finalize(None, &mem, I8, state);
                 let mut ret = String::new();
                 for inst in mem_insts.into_iter() {
                     ret.push_str(
diff --git a/cranelift/codegen/src/isa/aarch64/pcc.rs b/cranelift/codegen/src/isa/aarch64/pcc.rs
index e17daffd4..cdc6ca42e 100644
--- a/cranelift/codegen/src/isa/aarch64/pcc.rs
+++ b/cranelift/codegen/src/isa/aarch64/pcc.rs
@@ -38,7 +38,8 @@ pub(crate) fn check(
     inst_idx: InsnIndex,
     state: &mut FactFlowState,
 ) -> PccResult<()> {
-    trace!("Checking facts on inst: {:?}", vcode[inst_idx]);
+    let inst = &vcode[inst_idx];
+    trace!("Checking facts on inst: {:?}", inst);
 
     // We only persist flag state for one instruction, because we
     // can't exhaustively enumerate all flags-effecting ops; so take
@@ -47,28 +48,29 @@ pub(crate) fn check(
     let cmp_flags = state.cmp_flags.take();
     trace!(" * with cmp_flags = {cmp_flags:?}");
 
-    match vcode[inst_idx] {
+    match *inst {
         Inst::Args { .. } => {
             // Defs on the args have "axiomatic facts": we trust the
             // ABI code to pass through the values unharmed, so the
             // facts given to us in the CLIF should still be true.
             Ok(())
         }
-        Inst::ULoad8 { rd, ref mem, flags } | Inst::SLoad8 { rd, ref mem, flags } => {
-            check_load(ctx, Some(rd.to_reg()), flags, mem, vcode, I8)
+        Inst::ULoad8 { rd, ref mem, flags }
+        | Inst::SLoad8 { rd, ref mem, flags }
+        | Inst::ULoad16 { rd, ref mem, flags }
+        | Inst::SLoad16 { rd, ref mem, flags }
+        | Inst::ULoad32 { rd, ref mem, flags }
+        | Inst::SLoad32 { rd, ref mem, flags }
+        | Inst::ULoad64 { rd, ref mem, flags } => {
+            let access_ty = inst.mem_type().unwrap();
+            check_load(ctx, Some(rd.to_reg()), flags, mem, vcode, access_ty)
         }
-        Inst::ULoad16 { rd, ref mem, flags } | Inst::SLoad16 { rd, ref mem, flags } => {
-            check_load(ctx, Some(rd.to_reg()), flags, mem, vcode, I16)
+        Inst::FpuLoad32 { ref mem, flags, .. }
+        | Inst::FpuLoad64 { ref mem, flags, .. }
+        | Inst::FpuLoad128 { ref mem, flags, .. } => {
+            let access_ty = inst.mem_type().unwrap();
+            check_load(ctx, None, flags, mem, vcode, access_ty)
         }
-        Inst::ULoad32 { rd, ref mem, flags } | Inst::SLoad32 { rd, ref mem, flags } => {
-            check_load(ctx, Some(rd.to_reg()), flags, mem, vcode, I32)
-        }
-        Inst::ULoad64 { rd, ref mem, flags } => {
-            check_load(ctx, Some(rd.to_reg()), flags, mem, vcode, I64)
-        }
-        Inst::FpuLoad32 { ref mem, flags, .. } => check_load(ctx, None, flags, mem, vcode, F32),
-        Inst::FpuLoad64 { ref mem, flags, .. } => check_load(ctx, None, flags, mem, vcode, F64),
-        Inst::FpuLoad128 { ref mem, flags, .. } => check_load(ctx, None, flags, mem, vcode, I8X16),
         Inst::LoadP64 { ref mem, flags, .. } => check_load_pair(ctx, flags, mem, vcode, 16),
         Inst::FpuLoadP64 { ref mem, flags, .. } => check_load_pair(ctx, flags, mem, vcode, 16),
         Inst::FpuLoadP128 { ref mem, flags, .. } => check_load_pair(ctx, flags, mem, vcode, 32),
@@ -82,14 +84,18 @@ pub(crate) fn check(
             ..
         } => check_load_addr(ctx, flags, rn, vcode, access_ty),
 
-        Inst::Store8 { rd, ref mem, flags } => check_store(ctx, Some(rd), flags, mem, vcode, I8),
-        Inst::Store16 { rd, ref mem, flags } => check_store(ctx, Some(rd), flags, mem, vcode, I16),
-        Inst::Store32 { rd, ref mem, flags } => check_store(ctx, Some(rd), flags, mem, vcode, I32),
-        Inst::Store64 { rd, ref mem, flags } => check_store(ctx, Some(rd), flags, mem, vcode, I64),
-        Inst::FpuStore32 { ref mem, flags, .. } => check_store(ctx, None, flags, mem, vcode, F32),
-        Inst::FpuStore64 { ref mem, flags, .. } => check_store(ctx, None, flags, mem, vcode, F64),
-        Inst::FpuStore128 { ref mem, flags, .. } => {
-            check_store(ctx, None, flags, mem, vcode, I8X16)
+        Inst::Store8 { rd, ref mem, flags }
+        | Inst::Store16 { rd, ref mem, flags }
+        | Inst::Store32 { rd, ref mem, flags }
+        | Inst::Store64 { rd, ref mem, flags } => {
+            let access_ty = inst.mem_type().unwrap();
+            check_store(ctx, Some(rd), flags, mem, vcode, access_ty)
+        }
+        Inst::FpuStore32 { ref mem, flags, .. }
+        | Inst::FpuStore64 { ref mem, flags, .. }
+        | Inst::FpuStore128 { ref mem, flags, .. } => {
+            let access_ty = inst.mem_type().unwrap();
+            check_store(ctx, None, flags, mem, vcode, access_ty)
         }
         Inst::StoreP64 { ref mem, flags, .. } => check_store_pair(ctx, flags, mem, vcode, 16),
         Inst::FpuStoreP64 { ref mem, flags, .. } => check_store_pair(ctx, flags, mem, vcode, 16),
@@ -444,19 +450,14 @@ fn check_addr<'a>(
             trace!("rn = {rn:?} rm = {rm:?} sum = {sum:?}");
             check(&sum, ty)
         }
-        &AMode::RegScaled { rn, rm, ty } => {
+        &AMode::RegScaled { rn, rm } => {
             let rn = get_fact_or_default(vcode, rn, 64);
             let rm = get_fact_or_default(vcode, rm, 64);
             let rm_scaled = fail_if_missing(ctx.scale(&rm, 64, ty.bytes()))?;
             let sum = fail_if_missing(ctx.add(&rn, &rm_scaled, 64))?;
             check(&sum, ty)
         }
-        &AMode::RegScaledExtended {
-            rn,
-            rm,
-            ty,
-            extendop,
-        } => {
+        &AMode::RegScaledExtended { rn, rm, extendop } => {
             let rn = get_fact_or_default(vcode, rn, 64);
             let rm = get_fact_or_default(vcode, rm, 64);
             let rm_extended = fail_if_missing(extend_fact(ctx, &rm, extendop))?;
@@ -485,7 +486,7 @@ fn check_addr<'a>(
             // 32760 (= 4095 * 8) for I64s. The `UImm12Scaled` type
             // stores the *scaled* value, so we don't need to multiply
             // (again) by the type's size here.
-            let offset: u64 = uimm12.value.into();
+            let offset: u64 = uimm12.value().into();
             // This `unwrap()` will always succeed because the value
             // will always be positive and much smaller than
             // `i64::MAX` (see above).
diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs
index a497c72e1..8f99caa69 100644
--- a/cranelift/codegen/src/isa/riscv64/abi.rs
+++ b/cranelift/codegen/src/isa/riscv64/abi.rs
@@ -301,12 +301,12 @@ impl ABIMachineSpec for Riscv64MachineDeps {
     }
 
     fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
-        let mem = AMode::RegOffset(base, offset as i64, ty);
+        let mem = AMode::RegOffset(base, offset as i64);
         Inst::gen_load(into_reg, mem, ty, MemFlags::trusted())
     }
 
     fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
-        let mem = AMode::RegOffset(base, offset as i64, ty);
+        let mem = AMode::RegOffset(base, offset as i64);
         Inst::gen_store(mem, from_reg, ty, MemFlags::trusted())
     }
 
@@ -359,13 +359,13 @@ impl ABIMachineSpec for Riscv64MachineDeps {
             // mv   fp,sp        ;; set fp to sp.
             insts.extend(Self::gen_sp_reg_adjust(-16));
             insts.push(Inst::gen_store(
-                AMode::SPOffset(8, I64),
+                AMode::SPOffset(8),
                 link_reg(),
                 I64,
                 MemFlags::trusted(),
             ));
             insts.push(Inst::gen_store(
-                AMode::SPOffset(0, I64),
+                AMode::SPOffset(0),
                 fp_reg(),
                 I64,
                 MemFlags::trusted(),
@@ -399,13 +399,13 @@ impl ABIMachineSpec for Riscv64MachineDeps {
         if frame_layout.setup_area_size > 0 {
             insts.push(Inst::gen_load(
                 writable_link_reg(),
-                AMode::SPOffset(8, I64),
+                AMode::SPOffset(8),
                 I64,
                 MemFlags::trusted(),
             ));
             insts.push(Inst::gen_load(
                 writable_fp_reg(),
-                AMode::SPOffset(0, I64),
+                AMode::SPOffset(0),
                 I64,
                 MemFlags::trusted(),
             ));
@@ -488,7 +488,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
                     });
                 }
                 insts.push(Inst::gen_store(
-                    AMode::SPOffset(-(cur_offset as i64), ty),
+                    AMode::SPOffset(-(cur_offset as i64)),
                     real_reg_to_reg(reg.to_reg()),
                     ty,
                     MemFlags::trusted(),
@@ -521,7 +521,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
             };
             insts.push(Inst::gen_load(
                 Writable::from_reg(real_reg_to_reg(reg.to_reg())),
-                AMode::SPOffset(-cur_offset, ty),
+                AMode::SPOffset(-cur_offset),
                 ty,
                 MemFlags::trusted(),
             ));
@@ -1096,7 +1096,7 @@ impl Riscv64MachineDeps {
             });
 
             insts.push(Inst::gen_store(
-                AMode::SPOffset(0, I8),
+                AMode::SPOffset(0),
                 zero_reg(),
                 I32,
                 MemFlags::trusted(),
diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index 3cc710196..b77e66922 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -2280,19 +2280,19 @@
     (writable_reg_to_reg sum)))
 
 ;; Generates a AMode that points to a register plus an offset.
-(decl gen_reg_offset_amode (Reg i64 Type) AMode)
+(decl gen_reg_offset_amode (Reg i64) AMode)
 (extern constructor gen_reg_offset_amode gen_reg_offset_amode)
 
 ;; Generates a AMode that an offset from the stack pointer.
-(decl gen_sp_offset_amode (i64 Type) AMode)
+(decl gen_sp_offset_amode (i64) AMode)
 (extern constructor gen_sp_offset_amode gen_sp_offset_amode)
 
 ;; Generates a AMode that an offset from the frame pointer.
-(decl gen_fp_offset_amode (i64 Type) AMode)
+(decl gen_fp_offset_amode (i64) AMode)
 (extern constructor gen_fp_offset_amode gen_fp_offset_amode)
 
 ;; Generates an AMode that points to a stack slot + offset.
-(decl gen_stack_slot_amode (StackSlot i64 Type) AMode)
+(decl gen_stack_slot_amode (StackSlot i64) AMode)
 (extern constructor gen_stack_slot_amode gen_stack_slot_amode)
 
 ;; Generates a AMode that points to a constant in the constant pool.
@@ -2302,41 +2302,41 @@
 
 
 ;; Tries to match a Value + Offset into an AMode
-(decl amode (Value i32 Type) AMode)
-(rule 0 (amode addr offset ty) (amode_inner addr offset ty))
+(decl amode (Value i32) AMode)
+(rule 0 (amode addr offset) (amode_inner addr offset))
 
 ;; If we are adding a constant offset with an iadd we can instead make that
 ;; offset part of the amode offset.
 ;;
 ;; We can't recurse into `amode` again since that could cause stack overflows.
 ;; See: https://github.com/bytecodealliance/wasmtime/pull/6968
-(rule 1 (amode (iadd addr (iconst (simm32 y))) offset ty)
+(rule 1 (amode (iadd addr (iconst (simm32 y))) offset)
   (if-let new_offset (s32_add_fallible y offset))
-  (amode_inner addr new_offset ty))
-(rule 2 (amode (iadd (iconst (simm32 x)) addr) offset ty)
+  (amode_inner addr new_offset))
+(rule 2 (amode (iadd (iconst (simm32 x)) addr) offset)
   (if-let new_offset (s32_add_fallible x offset))
-  (amode_inner addr new_offset ty))
+  (amode_inner addr new_offset))
 
 
 ;; These are the normal rules for generating an AMode.
-(decl amode_inner (Value i32 Type) AMode)
+(decl amode_inner (Value i32) AMode)
 
 ;; In the simplest case we just lower into a Reg+Offset
-(rule 0 (amode_inner r @ (value_type (ty_addr64 _)) offset ty)
-  (gen_reg_offset_amode r offset ty))
+(rule 0 (amode_inner r @ (value_type (ty_addr64 _)) offset)
+  (gen_reg_offset_amode r offset))
 
 ;; If the value is a `get_frame_pointer`, we can just use the offset from that.
-(rule 1 (amode_inner (get_frame_pointer) offset ty)
-  (gen_fp_offset_amode offset ty))
+(rule 1 (amode_inner (get_frame_pointer) offset)
+  (gen_fp_offset_amode offset))
 
 ;; If the value is a `get_stack_pointer`, we can just use the offset from that.
-(rule 1 (amode_inner (get_stack_pointer) offset ty)
-  (gen_sp_offset_amode offset ty))
+(rule 1 (amode_inner (get_stack_pointer) offset)
+  (gen_sp_offset_amode offset))
 
 ;; Similarly if the value is a `stack_addr` we can also turn that into an sp offset.
-(rule 1 (amode_inner (stack_addr ss ss_offset) amode_offset ty)
+(rule 1 (amode_inner (stack_addr ss ss_offset) amode_offset)
   (if-let combined_offset (s32_add_fallible ss_offset amode_offset))
-  (gen_stack_slot_amode ss combined_offset ty))
+  (gen_stack_slot_amode ss combined_offset))
 
 
 
diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs
index f90168f54..9a9fe4d8f 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/args.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs
@@ -80,12 +80,12 @@ newtype_of_reg!(VReg, WritableVReg, |reg| reg.class() == RegClass::Vector);
 pub enum AMode {
     /// Arbitrary offset from a register. Converted to generation of large
     /// offsets with multiple instructions as necessary during code emission.
-    RegOffset(Reg, i64, Type),
+    RegOffset(Reg, i64),
     /// Offset from the stack pointer.
-    SPOffset(i64, Type),
+    SPOffset(i64),
 
     /// Offset from the frame pointer.
-    FPOffset(i64, Type),
+    FPOffset(i64),
 
     /// Offset from the "nominal stack pointer", which is where the real SP is
     /// just after stack and spill slots are allocated in the function prologue.
@@ -99,7 +99,7 @@ pub enum AMode {
     /// SP" is where the actual SP is after the function prologue and before
     /// clobber pushes. See the diagram in the documentation for
     /// [crate::isa::riscv64::abi](the ABI module) for more details.
-    NominalSPOffset(i64, Type),
+    NominalSPOffset(i64),
 
     /// A reference to a constant which is placed outside of the function's
     /// body, typically at the end.
@@ -112,7 +112,7 @@ pub enum AMode {
 impl AMode {
     pub(crate) fn with_allocs(self, allocs: &mut AllocationConsumer<'_>) -> Self {
         match self {
-            AMode::RegOffset(reg, offset, ty) => AMode::RegOffset(allocs.next(reg), offset, ty),
+            AMode::RegOffset(reg, offset) => AMode::RegOffset(allocs.next(reg), offset),
             AMode::SPOffset(..)
             | AMode::FPOffset(..)
             | AMode::NominalSPOffset(..)
@@ -146,10 +146,10 @@ impl AMode {
 
     pub(crate) fn get_offset_with_state(&self, state: &EmitState) -> i64 {
         match self {
-            &AMode::NominalSPOffset(offset, _) => offset + state.virtual_sp_offset,
-            &AMode::RegOffset(_, offset, ..) => offset,
-            &AMode::SPOffset(offset, _) => offset,
-            &AMode::FPOffset(offset, _) => offset,
+            &AMode::NominalSPOffset(offset) => offset + state.virtual_sp_offset,
+            &AMode::RegOffset(_, offset) => offset,
+            &AMode::SPOffset(offset) => offset,
+            &AMode::FPOffset(offset) => offset,
             &AMode::Const(_) | &AMode::Label(_) => 0,
         }
     }
@@ -200,9 +200,9 @@ impl Into<AMode> for StackAMode {
     fn into(self) -> AMode {
         match self {
             // Argument area begins after saved lr + fp.
-            StackAMode::ArgOffset(offset, ty) => AMode::FPOffset(offset + 16, ty),
-            StackAMode::SPOffset(offset, ty) => AMode::SPOffset(offset, ty),
-            StackAMode::NominalSPOffset(offset, ty) => AMode::NominalSPOffset(offset, ty),
+            StackAMode::ArgOffset(offset, _ty) => AMode::FPOffset(offset + 16),
+            StackAMode::SPOffset(offset, _ty) => AMode::SPOffset(offset),
+            StackAMode::NominalSPOffset(offset, _ty) => AMode::NominalSPOffset(offset),
         }
     }
 }
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index c4f32c58b..06578d9e5 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -1951,7 +1951,7 @@ impl Inst {
                         rd,
                         op: LoadOP::Ld,
                         flags: MemFlags::trusted(),
-                        from: AMode::RegOffset(rd.to_reg(), 0, I64),
+                        from: AMode::RegOffset(rd.to_reg(), 0),
                     }
                     .emit_uncompressed(sink, emit_info, state, start_off);
                 } else {
@@ -2083,7 +2083,7 @@ impl Inst {
                     rd: rd,
                     op: LoadOP::from_type(ty),
                     flags: MemFlags::new(),
-                    from: AMode::RegOffset(p, 0, ty),
+                    from: AMode::RegOffset(p, 0),
                 }
                 .emit(&[], sink, emit_info, state);
                 Inst::Fence {
@@ -2099,7 +2099,7 @@ impl Inst {
                 }
                 .emit(&[], sink, emit_info, state);
                 Inst::Store {
-                    to: AMode::RegOffset(p, 0, ty),
+                    to: AMode::RegOffset(p, 0),
                     op: StoreOP::from_type(ty),
                     flags: MemFlags::new(),
                     src,
@@ -2599,7 +2599,7 @@ impl Inst {
                 }
                 .emit(&[], sink, emit_info, state);
                 Inst::Store {
-                    to: AMode::RegOffset(spilltmp_reg2(), 0, I8),
+                    to: AMode::RegOffset(spilltmp_reg2(), 0),
                     op: StoreOP::Sb,
                     flags: MemFlags::new(),
                     src: zero_reg(),
@@ -3404,12 +3404,12 @@ fn emit_return_call_common_sequence(
 
     Inst::gen_load(
         writable_link_reg(),
-        AMode::FPOffset(8, I64),
+        AMode::FPOffset(8),
         I64,
         MemFlags::trusted(),
     )
     .emit(&[], sink, emit_info, state);
-    Inst::gen_load(tmp1, AMode::FPOffset(0, I64), I64, MemFlags::trusted()).emit(
+    Inst::gen_load(tmp1, AMode::FPOffset(0), I64, MemFlags::trusted()).emit(
         &[],
         sink,
         emit_info,
@@ -3422,7 +3422,7 @@ fn emit_return_call_common_sequence(
         // space.
         Inst::gen_load(
             tmp2,
-            AMode::SPOffset(i64::from(i * 8), types::I64),
+            AMode::SPOffset(i64::from(i * 8)),
             types::I64,
             ir::MemFlags::trusted(),
         )
@@ -3431,7 +3431,7 @@ fn emit_return_call_common_sequence(
         // Store it to its final destination on the stack, overwriting our
         // current frame.
         Inst::gen_store(
-            AMode::FPOffset(fp_to_callee_sp + i64::from(i * 8), types::I64),
+            AMode::FPOffset(fp_to_callee_sp + i64::from(i * 8)),
             tmp2.to_reg(),
             types::I64,
             ir::MemFlags::trusted(),
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index 5891cbbe0..a0abd498d 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -1979,41 +1979,41 @@
 
 ;;;;;  Rules for `uload8`;;;;;;;;;
 (rule (lower (uload8 flags addr offset))
-  (gen_load (amode addr offset $I8) (LoadOP.Lbu) flags))
+  (gen_load (amode addr offset) (LoadOP.Lbu) flags))
 
 ;;;;;  Rules for `sload8`;;;;;;;;;
 (rule (lower (sload8 flags addr offset))
-  (gen_load (amode addr offset $I8) (LoadOP.Lb) flags))
+  (gen_load (amode addr offset) (LoadOP.Lb) flags))
 
 ;;;;;  Rules for `uload16`;;;;;;;;;
 (rule (lower (uload16 flags addr offset))
-  (gen_load (amode addr offset $I16) (LoadOP.Lhu) flags))
+  (gen_load (amode addr offset) (LoadOP.Lhu) flags))
 
 ;;;;;  Rules for `iload16`;;;;;;;;;
 (rule (lower (sload16 flags addr offset))
-  (gen_load (amode addr offset $I16) (LoadOP.Lh) flags))
+  (gen_load (amode addr offset) (LoadOP.Lh) flags))
 
 ;;;;;  Rules for `uload32`;;;;;;;;;
 (rule (lower (uload32 flags addr offset))
-  (gen_load (amode addr offset $I32) (LoadOP.Lwu) flags))
+  (gen_load (amode addr offset) (LoadOP.Lwu) flags))
 
 ;;;;;  Rules for `sload32`;;;;;;;;;
 (rule (lower (sload32 flags addr offset))
-  (gen_load (amode addr offset $I32) (LoadOP.Lw) flags))
+  (gen_load (amode addr offset) (LoadOP.Lw) flags))
 
 ;;;;;  Rules for `load`;;;;;;;;;
 (rule (lower (has_type ty (load flags addr offset)))
-  (gen_load (amode addr offset ty) (load_op ty) flags))
+  (gen_load (amode addr offset) (load_op ty) flags))
 
 (rule 1 (lower (has_type $I128 (load flags addr offset)))
   (if-let offset_plus_8 (s32_add_fallible offset 8))
-  (let ((lo XReg (gen_load (amode addr offset $I64) (LoadOP.Ld) flags))
-        (hi XReg (gen_load (amode addr offset_plus_8 $I64) (LoadOP.Ld) flags)))
+  (let ((lo XReg (gen_load (amode addr offset) (LoadOP.Ld) flags))
+        (hi XReg (gen_load (amode addr offset_plus_8) (LoadOP.Ld) flags)))
     (value_regs lo hi)))
 
 (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (load flags addr offset)))
   (let ((eew VecElementWidth (element_width_from_type ty))
-        (amode AMode (amode addr offset ty)))
+        (amode AMode (amode addr offset)))
     (vec_load eew (VecAMode.UnitStride amode) flags (unmasked) ty)))
 
 ;;;;;  Rules for Load + Extend Combos ;;;;;;;;;
@@ -2039,52 +2039,52 @@
 
 ;;;;;  Rules for `uload8x8`;;;;;;;;;;
 (rule (lower (has_type (ty_vec_fits_in_register ty @ $I16X8) (uload8x8 flags addr offset)))
-  (gen_load64_extend ty (ExtendOp.Zero) flags (amode addr offset ty)))
+  (gen_load64_extend ty (ExtendOp.Zero) flags (amode addr offset)))
 
 ;;;;;  Rules for `uload16x4`;;;;;;;;;
 (rule (lower (has_type (ty_vec_fits_in_register ty @ $I32X4) (uload16x4 flags addr offset)))
-  (gen_load64_extend ty (ExtendOp.Zero) flags (amode addr offset ty)))
+  (gen_load64_extend ty (ExtendOp.Zero) flags (amode addr offset)))
 
 ;;;;;  Rules for `uload32x2`;;;;;;;;;
 (rule (lower (has_type (ty_vec_fits_in_register ty @ $I64X2) (uload32x2 flags addr offset)))
-  (gen_load64_extend ty (ExtendOp.Zero) flags (amode addr offset ty)))
+  (gen_load64_extend ty (ExtendOp.Zero) flags (amode addr offset)))
 
 ;;;;;  Rules for `sload8x8`;;;;;;;;;;
 (rule (lower (has_type (ty_vec_fits_in_register ty @ $I16X8) (sload8x8 flags addr offset)))
-  (gen_load64_extend ty (ExtendOp.Signed) flags (amode addr offset ty)))
+  (gen_load64_extend ty (ExtendOp.Signed) flags (amode addr offset)))
 
 ;;;;;  Rules for `sload16x4`;;;;;;;;;
 (rule (lower (has_type (ty_vec_fits_in_register ty @ $I32X4) (sload16x4 flags addr offset)))
-  (gen_load64_extend ty (ExtendOp.Signed) flags (amode addr offset ty)))
+  (gen_load64_extend ty (ExtendOp.Signed) flags (amode addr offset)))
 
 ;;;;;  Rules for `sload32x2`;;;;;;;;;
 (rule (lower (has_type (ty_vec_fits_in_register ty @ $I64X2) (sload32x2 flags addr offset)))
-  (gen_load64_extend ty (ExtendOp.Signed) flags (amode addr offset ty)))
+  (gen_load64_extend ty (ExtendOp.Signed) flags (amode addr offset)))
 
 ;;;;;  Rules for `istore8`;;;;;;;;;
 (rule (lower (istore8 flags src addr offset))
-  (gen_store (amode addr offset $I8) (StoreOP.Sb) flags src))
+  (gen_store (amode addr offset) (StoreOP.Sb) flags src))
 
 ;;;;;  Rules for `istore16`;;;;;;;;;
 (rule (lower (istore16 flags src addr offset))
-  (gen_store (amode addr offset $I16) (StoreOP.Sh) flags src))
+  (gen_store (amode addr offset) (StoreOP.Sh) flags src))
 
 ;;;;;  Rules for `istore32`;;;;;;;;;
 (rule (lower (istore32 flags src addr offset))
-  (gen_store (amode addr offset $I32) (StoreOP.Sw) flags src))
+  (gen_store (amode addr offset) (StoreOP.Sw) flags src))
 
 ;;;;;  Rules for `store`;;;;;;;;;
 (rule (lower (store flags src @ (value_type ty) addr offset))
-  (gen_store (amode addr offset ty) (store_op ty) flags src))
+  (gen_store (amode addr offset) (store_op ty) flags src))
 
 (rule 1 (lower (store flags src @ (value_type $I128) addr offset))
   (if-let offset_plus_8 (s32_add_fallible offset 8))
-  (let ((_ InstOutput (gen_store (amode addr offset $I64) (StoreOP.Sd) flags (value_regs_get src 0))))
-    (gen_store (amode addr offset_plus_8 $I64) (StoreOP.Sd) flags (value_regs_get src 1))))
+  (let ((_ InstOutput (gen_store (amode addr offset) (StoreOP.Sd) flags (value_regs_get src 0))))
+    (gen_store (amode addr offset_plus_8) (StoreOP.Sd) flags (value_regs_get src 1))))
 
 (rule 2 (lower (store flags src @ (value_type (ty_vec_fits_in_register ty)) addr offset))
   (let ((eew VecElementWidth (element_width_from_type ty))
-        (amode AMode (amode addr offset ty)))
+        (amode AMode (amode addr offset)))
     (vec_store eew (VecAMode.UnitStride amode) src flags (unmasked) ty)))
 
 
diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
index 261a8f435..065b74631 100644
--- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
@@ -177,7 +177,7 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
                 rd: tmp,
                 op: LoadOP::Ld,
                 flags: MemFlags::trusted(),
-                from: AMode::FPOffset(8, I64),
+                from: AMode::FPOffset(8),
             });
             tmp.to_reg()
         } else {
@@ -385,24 +385,24 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
         self.backend.isa_flags.has_zbs()
     }
 
-    fn gen_reg_offset_amode(&mut self, base: Reg, offset: i64, ty: Type) -> AMode {
-        AMode::RegOffset(base, offset, ty)
+    fn gen_reg_offset_amode(&mut self, base: Reg, offset: i64) -> AMode {
+        AMode::RegOffset(base, offset)
     }
 
-    fn gen_sp_offset_amode(&mut self, offset: i64, ty: Type) -> AMode {
-        AMode::SPOffset(offset, ty)
+    fn gen_sp_offset_amode(&mut self, offset: i64) -> AMode {
+        AMode::SPOffset(offset)
     }
 
-    fn gen_fp_offset_amode(&mut self, offset: i64, ty: Type) -> AMode {
-        AMode::FPOffset(offset, ty)
+    fn gen_fp_offset_amode(&mut self, offset: i64) -> AMode {
+        AMode::FPOffset(offset)
     }
 
-    fn gen_stack_slot_amode(&mut self, ss: StackSlot, offset: i64, ty: Type) -> AMode {
+    fn gen_stack_slot_amode(&mut self, ss: StackSlot, offset: i64) -> AMode {
         // Offset from beginning of stackslot area, which is at nominal SP (see
         // [MemArg::NominalSPOffset] for more details on nominal SP tracking).
         let stack_off = self.lower_ctx.abi().sized_stackslot_offsets()[ss] as i64;
         let sp_off: i64 = stack_off + offset;
-        AMode::NominalSPOffset(sp_off, ty)
+        AMode::NominalSPOffset(sp_off)
     }
 
     fn gen_const_amode(&mut self, c: VCodeConstant) -> AMode {
diff --git a/winch/codegen/src/isa/aarch64/address.rs b/winch/codegen/src/isa/aarch64/address.rs
index 11521e5ce..02b1680d6 100644
--- a/winch/codegen/src/isa/aarch64/address.rs
+++ b/winch/codegen/src/isa/aarch64/address.rs
@@ -137,7 +137,6 @@ impl TryFrom<Address> for AMode {
             Offset { base, offset } => Ok(AMode::RegOffset {
                 rn: base.into(),
                 off: offset,
-                ty: types::I64,
             }),
         }
     }


Test patch:
diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
index 3a0a81324..d470ed901 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
@@ -1551,7 +1551,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(2),
                 rm: xreg(3),
-                ty: I16,
             },
             flags: MemFlags::trusted(),
         },
@@ -1588,7 +1587,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(20),
                 rm: xreg(20),
-                ty: I16,
             },
             flags: MemFlags::trusted(),
         },
@@ -1625,7 +1623,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(2),
                 rm: xreg(12),
-                ty: I32,
             },
             flags: MemFlags::trusted(),
         },
@@ -1662,7 +1659,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(5),
                 rm: xreg(1),
-                ty: I32,
             },
             flags: MemFlags::trusted(),
         },
@@ -1735,7 +1731,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(2),
                 rm: xreg(3),
-                ty: I64,
             },
             flags: MemFlags::trusted(),
         },
@@ -1748,7 +1743,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaledExtended {
                 rn: xreg(2),
                 rm: xreg(3),
-                ty: I64,
                 extendop: ExtendOp::SXTW,
             },
             flags: MemFlags::trusted(),
@@ -1805,7 +1799,7 @@ fn test_aarch64_binemit() {
     insns.push((
         Inst::ULoad64 {
             rd: writable_xreg(1),
-            mem: AMode::FPOffset { off: 32768, ty: I8 },
+            mem: AMode::FPOffset { off: 32768 },
             flags: MemFlags::trusted(),
         },
         "100090D2A1EB70F8",
@@ -1814,10 +1808,7 @@ fn test_aarch64_binemit() {
     insns.push((
         Inst::ULoad64 {
             rd: writable_xreg(1),
-            mem: AMode::FPOffset {
-                off: -32768,
-                ty: I8,
-            },
+            mem: AMode::FPOffset { off: -32768 },
             flags: MemFlags::trusted(),
         },
         "F0FF8F92A1EB70F8",
@@ -1826,10 +1817,7 @@ fn test_aarch64_binemit() {
     insns.push((
         Inst::ULoad64 {
             rd: writable_xreg(1),
-            mem: AMode::FPOffset {
-                off: 1048576,
-                ty: I8,
-            }, // 2^20
+            mem: AMode::FPOffset { off: 1048576 }, // 2^20
             flags: MemFlags::trusted(),
         },
         "1002A0D2A1EB70F8",
@@ -1838,10 +1826,7 @@ fn test_aarch64_binemit() {
     insns.push((
         Inst::ULoad64 {
             rd: writable_xreg(1),
-            mem: AMode::FPOffset {
-                off: 1048576 + 1,
-                ty: I8,
-            }, // 2^20 + 1
+            mem: AMode::FPOffset { off: 1048576 + 1 }, // 2^20 + 1
             flags: MemFlags::trusted(),
         },
         "300080521002A072A1EB70F8",
@@ -1854,7 +1839,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegOffset {
                 rn: xreg(7),
                 off: 8,
-                ty: I64,
             },
             flags: MemFlags::trusted(),
         },
@@ -1868,7 +1852,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegOffset {
                 rn: xreg(7),
                 off: 1024,
-                ty: I64,
             },
             flags: MemFlags::trusted(),
         },
@@ -1882,7 +1865,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegOffset {
                 rn: xreg(7),
                 off: 1048576,
-                ty: I64,
             },
             flags: MemFlags::trusted(),
         },
@@ -2004,7 +1986,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(2),
                 rm: xreg(3),
-                ty: I64,
             },
             flags: MemFlags::trusted(),
         },
@@ -2017,7 +1998,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaledExtended {
                 rn: xreg(2),
                 rm: xreg(3),
-                ty: I64,
                 extendop: ExtendOp::UXTW,
             },
             flags: MemFlags::trusted(),
@@ -6692,7 +6672,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(8),
                 rm: xreg(9),
-                ty: F32,
             },
             flags: MemFlags::trusted(),
         },
@@ -6706,7 +6685,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(8),
                 rm: xreg(9),
-                ty: F64,
             },
             flags: MemFlags::trusted(),
         },
@@ -6720,7 +6698,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(8),
                 rm: xreg(9),
-                ty: I128,
             },
             flags: MemFlags::trusted(),
         },
@@ -6770,7 +6747,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(8),
                 rm: xreg(9),
-                ty: F32,
             },
             flags: MemFlags::trusted(),
         },
@@ -6784,7 +6760,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(8),
                 rm: xreg(9),
-                ty: F64,
             },
             flags: MemFlags::trusted(),
         },
@@ -6798,7 +6773,6 @@ fn test_aarch64_binemit() {
             mem: AMode::RegScaled {
                 rn: xreg(8),
                 rm: xreg(9),
-                ty: I128,
             },
             flags: MemFlags::trusted(),
         },
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
index 6949043ff..6a258db30 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
@@ -631,7 +631,7 @@ fn test_riscv64_binemit() {
             rd: writable_a0(),
             op: LoadOP::Lb,
             flags: MemFlags::new(),
-            from: AMode::RegOffset(a1(), 100, I8),
+            from: AMode::RegOffset(a1(), 100),
         },
         "lb a0,100(a1)",
         0x6458503,
@@ -641,7 +641,7 @@ fn test_riscv64_binemit() {
             rd: writable_a0(),
             op: LoadOP::Lh,
             flags: MemFlags::new(),
-            from: AMode::RegOffset(a1(), 100, I16),
+            from: AMode::RegOffset(a1(), 100),
         },
         "lh a0,100(a1)",
         0x6459503,
@@ -652,7 +652,7 @@ fn test_riscv64_binemit() {
             rd: writable_a0(),
             op: LoadOP::Lw,
             flags: MemFlags::new(),
-            from: AMode::RegOffset(a1(), 100, I32),
+            from: AMode::RegOffset(a1(), 100),
         },
         "lw a0,100(a1)",
         0x645a503,
@@ -663,7 +663,7 @@ fn test_riscv64_binemit() {
             rd: writable_a0(),
             op: LoadOP::Ld,
             flags: MemFlags::new(),
-            from: AMode::RegOffset(a1(), 100, I64),
+            from: AMode::RegOffset(a1(), 100),
         },
         "ld a0,100(a1)",
         0x645b503,
@@ -673,7 +673,7 @@ fn test_riscv64_binemit() {
             rd: Writable::from_reg(fa0()),
             op: LoadOP::Flw,
             flags: MemFlags::new(),
-            from: AMode::RegOffset(a1(), 100, I64),
+            from: AMode::RegOffset(a1(), 100),
         },
         "flw fa0,100(a1)",
         0x645a507,
@@ -684,14 +684,14 @@ fn test_riscv64_binemit() {
             rd: Writable::from_reg(fa0()),
             op: LoadOP::Fld,
             flags: MemFlags::new(),
-            from: AMode::RegOffset(a1(), 100, I64),
+            from: AMode::RegOffset(a1(), 100),
         },
         "fld fa0,100(a1)",
         0x645b507,
     ));
     insns.push(TestUnit::new(
         Inst::Store {
-            to: AMode::SPOffset(100, I8),
+            to: AMode::SPOffset(100),
             op: StoreOP::Sb,
             flags: MemFlags::new(),
             src: a0(),
@@ -701,7 +701,7 @@ fn test_riscv64_binemit() {
     ));
     insns.push(TestUnit::new(
         Inst::Store {
-            to: AMode::SPOffset(100, I16),
+            to: AMode::SPOffset(100),
             op: StoreOP::Sh,
             flags: MemFlags::new(),
             src: a0(),
@@ -711,7 +711,7 @@ fn test_riscv64_binemit() {
     ));
     insns.push(TestUnit::new(
         Inst::Store {
-            to: AMode::SPOffset(100, I32),
+            to: AMode::SPOffset(100),
             op: StoreOP::Sw,
             flags: MemFlags::new(),
             src: a0(),
@@ -721,7 +721,7 @@ fn test_riscv64_binemit() {
     ));
     insns.push(TestUnit::new(
         Inst::Store {
-            to: AMode::SPOffset(100, I64),
+            to: AMode::SPOffset(100),
             op: StoreOP::Sd,
             flags: MemFlags::new(),
             src: a0(),
@@ -731,7 +731,7 @@ fn test_riscv64_binemit() {
     ));
     insns.push(TestUnit::new(
         Inst::Store {
-            to: AMode::SPOffset(100, I64),
+            to: AMode::SPOffset(100),
             op: StoreOP::Fsw,
             flags: MemFlags::new(),
             src: fa0(),
@@ -741,7 +741,7 @@ fn test_riscv64_binemit() {
     ));
     insns.push(TestUnit::new(
         Inst::Store {
-            to: AMode::SPOffset(100, I64),
+            to: AMode::SPOffset(100),
             op: StoreOP::Fsd,
             flags: MemFlags::new(),
             src: fa0(),