Repository: bytecodealliance/wasmtime
Pull request #9164 (2024-08-22 20:51:00)

Remove reference types (`r32` and `r64`) from Cranelift
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Patch:
diff --git a/cranelift/codegen/meta/src/cdsl/types.rs b/cranelift/codegen/meta/src/cdsl/types.rs
index 34bafe1e5..ce3c2e582 100644
--- a/cranelift/codegen/meta/src/cdsl/types.rs
+++ b/cranelift/codegen/meta/src/cdsl/types.rs
@@ -17,7 +17,6 @@ static RUST_NAME_PREFIX: &str = "ir::types::";
 #[derive(Clone, Debug, PartialEq, Eq, Hash)]
 pub(crate) enum ValueType {
     Lane(LaneType),
-    Reference(ReferenceType),
     Vector(VectorType),
     DynamicVector(DynamicVectorType),
 }
@@ -28,15 +27,10 @@ impl ValueType {
         LaneTypeIterator::new()
     }
 
-    pub fn all_reference_types() -> ReferenceTypeIterator {
-        ReferenceTypeIterator::new()
-    }
-
     /// Return a string containing the documentation comment for this type.
     pub fn doc(&self) -> String {
         match *self {
             ValueType::Lane(l) => l.doc(),
-            ValueType::Reference(r) => r.doc(),
             ValueType::Vector(ref v) => v.doc(),
             ValueType::DynamicVector(ref v) => v.doc(),
         }
@@ -46,7 +40,6 @@ impl ValueType {
     pub fn lane_bits(&self) -> u64 {
         match *self {
             ValueType::Lane(l) => l.lane_bits(),
-            ValueType::Reference(r) => r.lane_bits(),
             ValueType::Vector(ref v) => v.lane_bits(),
             ValueType::DynamicVector(ref v) => v.lane_bits(),
         }
@@ -69,7 +62,6 @@ impl ValueType {
     pub fn number(&self) -> u16 {
         match *self {
             ValueType::Lane(l) => l.number(),
-            ValueType::Reference(r) => r.number(),
             ValueType::Vector(ref v) => v.number(),
             ValueType::DynamicVector(ref v) => v.number(),
         }
@@ -90,7 +82,6 @@ impl fmt::Display for ValueType {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         match *self {
             ValueType::Lane(l) => l.fmt(f),
-            ValueType::Reference(r) => r.fmt(f),
             ValueType::Vector(ref v) => v.fmt(f),
             ValueType::DynamicVector(ref v) => v.fmt(f),
         }
@@ -104,13 +95,6 @@ impl From<LaneType> for ValueType {
     }
 }
 
-/// Create a ValueType from a given reference type.
-impl From<ReferenceType> for ValueType {
-    fn from(reference: ReferenceType) -> Self {
-        ValueType::Reference(reference)
-    }
-}
-
 /// Create a ValueType from a given vector type.
 impl From<VectorType> for ValueType {
     fn from(vector: VectorType) -> Self {
@@ -434,79 +418,3 @@ impl fmt::Debug for DynamicVectorType {
         )
     }
 }
-
-/// Reference type is scalar type, but not lane type.
-#[derive(Clone, Copy, PartialEq, Eq, Hash)]
-pub(crate) struct ReferenceType(pub shared_types::Reference);
-
-impl ReferenceType {
-    /// Return a string containing the documentation comment for this reference type.
-    pub fn doc(self) -> String {
-        format!("An opaque reference type with {} bits.", self.lane_bits())
-    }
-
-    /// Return the number of bits in a lane.
-    pub fn lane_bits(self) -> u64 {
-        match self.0 {
-            shared_types::Reference::R32 => 32,
-            shared_types::Reference::R64 => 64,
-        }
-    }
-
-    /// Find the unique number associated with this reference type.
-    pub fn number(self) -> u16 {
-        constants::REFERENCE_BASE
-            + match self {
-                ReferenceType(shared_types::Reference::R32) => 0,
-                ReferenceType(shared_types::Reference::R64) => 1,
-            }
-    }
-
-    pub fn ref_from_bits(num_bits: u16) -> ReferenceType {
-        ReferenceType(match num_bits {
-            32 => shared_types::Reference::R32,
-            64 => shared_types::Reference::R64,
-            _ => unreachable!("unexpected number of bits for a reference type"),
-        })
-    }
-}
-
-impl fmt::Display for ReferenceType {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "r{}", self.lane_bits())
-    }
-}
-
-impl fmt::Debug for ReferenceType {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "ReferenceType(bits={})", self.lane_bits())
-    }
-}
-
-/// Create a ReferenceType from a given reference variant.
-impl From<shared_types::Reference> for ReferenceType {
-    fn from(r: shared_types::Reference) -> Self {
-        ReferenceType(r)
-    }
-}
-
-/// An iterator for different reference types.
-pub(crate) struct ReferenceTypeIterator {
-    reference_iter: shared_types::ReferenceIterator,
-}
-
-impl ReferenceTypeIterator {
-    /// Create a new reference type iterator.
-    fn new() -> Self {
-        Self {
-            reference_iter: shared_types::ReferenceIterator::new(),
-        }
-    }
-}
-
-impl Iterator for ReferenceTypeIterator {
-    type Item = ReferenceType;
-    fn next(&mut self) -> Option<Self::Item> {
-        self.reference_iter.next().map(ReferenceType::from)
-    }
-}
diff --git a/cranelift/codegen/meta/src/cdsl/typevar.rs b/cranelift/codegen/meta/src/cdsl/typevar.rs
index d0a331369..61f31d9db 100644
--- a/cranelift/codegen/meta/src/cdsl/typevar.rs
+++ b/cranelift/codegen/meta/src/cdsl/typevar.rs
@@ -5,7 +5,7 @@ use std::hash;
 use std::ops;
 use std::rc::Rc;
 
-use crate::cdsl::types::{LaneType, ReferenceType, ValueType};
+use crate::cdsl::types::{LaneType, ValueType};
 
 const MAX_LANES: u16 = 256;
 const MAX_BITS: u16 = 128;
@@ -56,10 +56,6 @@ impl TypeVar {
         let mut builder = TypeSetBuilder::new();
 
         let (scalar_type, num_lanes) = match value_type {
-            ValueType::Reference(ReferenceType(reference_type)) => {
-                let bits = reference_type as RangeBound;
-                return TypeVar::new(name, doc, builder.refs(bits..bits).build());
-            }
             ValueType::Lane(lane_type) => (lane_type, 1),
             ValueType::Vector(vec_type) => {
                 (vec_type.lane_type(), vec_type.lane_count() as RangeBound)
@@ -208,9 +204,7 @@ impl TypeVar {
                     "The `narrower` constraint does not apply to vectors"
                 );
                 assert!(
-                    (!ts.ints.is_empty() || !ts.floats.is_empty())
-                        && ts.refs.is_empty()
-                        && ts.dynamic_lanes.is_empty(),
+                    (!ts.ints.is_empty() || !ts.floats.is_empty()) && ts.dynamic_lanes.is_empty(),
                     "The `narrower` constraint only applies to scalar ints or floats"
                 );
             }
@@ -221,9 +215,7 @@ impl TypeVar {
                     "The `wider` constraint does not apply to vectors"
                 );
                 assert!(
-                    (!ts.ints.is_empty() || !ts.floats.is_empty())
-                        && ts.refs.is_empty()
-                        && ts.dynamic_lanes.is_empty(),
+                    (!ts.ints.is_empty() || !ts.floats.is_empty()) && ts.dynamic_lanes.is_empty(),
                     "The `wider` constraint only applies to scalar ints or floats"
                 );
             }
@@ -394,30 +386,22 @@ pub(crate) struct TypeSet {
     pub dynamic_lanes: NumSet,
     pub ints: NumSet,
     pub floats: NumSet,
-    pub refs: NumSet,
 }
 
 impl TypeSet {
-    fn new(
-        lanes: NumSet,
-        dynamic_lanes: NumSet,
-        ints: NumSet,
-        floats: NumSet,
-        refs: NumSet,
-    ) -> Self {
+    fn new(lanes: NumSet, dynamic_lanes: NumSet, ints: NumSet, floats: NumSet) -> Self {
         Self {
             lanes,
             dynamic_lanes,
             ints,
             floats,
-            refs,
         }
     }
 
     /// Return the number of concrete types represented by this typeset.
     pub fn size(&self) -> usize {
-        self.lanes.len() * (self.ints.len() + self.floats.len() + self.refs.len())
-            + self.dynamic_lanes.len() * (self.ints.len() + self.floats.len() + self.refs.len())
+        self.lanes.len() * (self.ints.len() + self.floats.len())
+            + self.dynamic_lanes.len() * (self.ints.len() + self.floats.len())
     }
 
     /// Return the image of self across the derived function func.
@@ -456,7 +440,6 @@ impl TypeSet {
         }
 
         copy.floats = NumSet::new();
-        copy.refs = NumSet::new();
         copy
     }
 
@@ -521,9 +504,6 @@ impl TypeSet {
             for &bits in &self.floats {
                 ret.push(LaneType::float_from_bits(bits).by(num_lanes));
             }
-            for &bits in &self.refs {
-                ret.push(ReferenceType::ref_from_bits(bits).into());
-            }
         }
         for &num_lanes in &self.dynamic_lanes {
             for &bits in &self.ints {
@@ -573,12 +553,6 @@ impl fmt::Debug for TypeSet {
                 Vec::from_iter(self.floats.iter().map(|x| x.to_string())).join(", ")
             ));
         }
-        if !self.refs.is_empty() {
-            subsets.push(format!(
-                "refs={{{}}}",
-                Vec::from_iter(self.refs.iter().map(|x| x.to_string())).join(", ")
-            ));
-        }
 
         write!(fmt, "{})", subsets.join(", "))?;
         Ok(())
@@ -588,7 +562,6 @@ impl fmt::Debug for TypeSet {
 pub(crate) struct TypeSetBuilder {
     ints: Interval,
     floats: Interval,
-    refs: Interval,
     includes_scalars: bool,
     simd_lanes: Interval,
     dynamic_simd_lanes: Interval,
@@ -599,7 +572,6 @@ impl TypeSetBuilder {
         Self {
             ints: Interval::None,
             floats: Interval::None,
-            refs: Interval::None,
             includes_scalars: true,
             simd_lanes: Interval::None,
             dynamic_simd_lanes: Interval::None,
@@ -616,11 +588,6 @@ impl TypeSetBuilder {
         self.floats = interval.into();
         self
     }
-    pub fn refs(mut self, interval: impl Into<Interval>) -> Self {
-        assert!(self.refs == Interval::None);
-        self.refs = interval.into();
-        self
-    }
     pub fn includes_scalars(mut self, includes_scalars: bool) -> Self {
         self.includes_scalars = includes_scalars;
         self
@@ -644,7 +611,6 @@ impl TypeSetBuilder {
             range_to_set(self.dynamic_simd_lanes.to_range(2..MAX_LANES, None)),
             range_to_set(self.ints.to_range(8..MAX_BITS, None)),
             range_to_set(self.floats.to_range(16..MAX_FLOAT_BITS, None)),
-            range_to_set(self.refs.to_range(32..64, None)),
         )
     }
 }
diff --git a/cranelift/codegen/meta/src/gen_inst.rs b/cranelift/codegen/meta/src/gen_inst.rs
index 03138b861..7609d060d 100644
--- a/cranelift/codegen/meta/src/gen_inst.rs
+++ b/cranelift/codegen/meta/src/gen_inst.rs
@@ -745,9 +745,6 @@ fn typeset_to_string(ts: &TypeSet) -> String {
     if !ts.floats.is_empty() {
         result += &format!(", floats={}", iterable_to_string(&ts.floats));
     }
-    if !ts.refs.is_empty() {
-        result += &format!(", refs={}", iterable_to_string(&ts.refs));
-    }
     result += ")";
     result
 }
@@ -774,7 +771,6 @@ pub(crate) fn gen_typesets_table(type_sets: &UniqueTable<TypeSet>, fmt: &mut For
                 gen_bitset(&ts.dynamic_lanes, "dynamic_lanes", 16, fmt);
                 gen_bitset(&ts.ints, "ints", 8, fmt);
                 gen_bitset(&ts.floats, "floats", 8, fmt);
-                gen_bitset(&ts.refs, "refs", 8, fmt);
             });
             fmt.line("},");
         }
diff --git a/cranelift/codegen/meta/src/gen_types.rs b/cranelift/codegen/meta/src/gen_types.rs
index 3310e36fd..e0e66a3de 100644
--- a/cranelift/codegen/meta/src/gen_types.rs
+++ b/cranelift/codegen/meta/src/gen_types.rs
@@ -53,11 +53,6 @@ fn emit_types(fmt: &mut srcgen::Formatter) {
         emit_type(&ty, fmt);
     }
 
-    // Emit all reference types.
-    for ty in cdsl_types::ValueType::all_reference_types().map(cdsl_types::ValueType::from) {
-        emit_type(&ty, fmt);
-    }
-
     // Emit vector definitions for common SIMD sizes.
     // Emit dynamic vector definitions.
     for vec_size in &[16_u64, 32, 64, 128, 256, 512] {
diff --git a/cranelift/codegen/meta/src/shared/instructions.rs b/cranelift/codegen/meta/src/shared/instructions.rs
index c0f62954f..4348a7b71 100644
--- a/cranelift/codegen/meta/src/shared/instructions.rs
+++ b/cranelift/codegen/meta/src/shared/instructions.rs
@@ -98,7 +98,7 @@ fn define_control_flow(
     let iAddr = &TypeVar::new(
         "iAddr",
         "An integer address type",
-        TypeSetBuilder::new().ints(32..64).refs(32..64).build(),
+        TypeSetBuilder::new().ints(32..64).build(),
     );
 
     ig.push(
@@ -642,13 +642,7 @@ pub(crate) fn define(
     let iAddr = &TypeVar::new(
         "iAddr",
         "An integer address type",
-        TypeSetBuilder::new().ints(32..64).refs(32..64).build(),
-    );
-
-    let Ref = &TypeVar::new(
-        "Ref",
-        "A scalar reference type",
-        TypeSetBuilder::new().refs(Interval::All).build(),
+        TypeSetBuilder::new().ints(32..64).build(),
     );
 
     let TxN = &TypeVar::new(
@@ -667,7 +661,6 @@ pub(crate) fn define(
         TypeSetBuilder::new()
             .ints(Interval::All)
             .floats(Interval::All)
-            .refs(Interval::All)
             .simd_lanes(Interval::All)
             .includes_scalars(true)
             .build(),
@@ -680,7 +673,6 @@ pub(crate) fn define(
             .ints(Interval::All)
             .floats(Interval::All)
             .simd_lanes(Interval::All)
-            .refs(Interval::All)
             .dynamic_simd_lanes(Interval::All)
             .build(),
     );
@@ -1461,21 +1453,6 @@ pub(crate) fn define(
         .operands_out(vec![Operand::new("a", Tx16).with_doc("A vector value")]),
     );
 
-    ig.push(
-        Inst::new(
-            "null",
-            r#"
-        Null constant value for reference types.
-
-        Create a scalar reference SSA value with a constant null value.
-        "#,
-            &formats.nullary,
-        )
-        .operands_out(vec![
-            Operand::new("a", Ref).with_doc("A constant reference null value")
-        ]),
-    );
-
     ig.push(Inst::new(
         "nop",
         r#"
@@ -3050,36 +3027,6 @@ pub(crate) fn define(
         ]),
     );
 
-    ig.push(
-        Inst::new(
-            "is_null",
-            r#"
-        Reference verification.
-
-        The condition code determines if the reference type in question is
-        null or not.
-        "#,
-            &formats.unary,
-        )
-        .operands_in(vec![Operand::new("x", Ref)])
-        .operands_out(vec![Operand::new("a", i8)]),
-    );
-
-    ig.push(
-        Inst::new(
-            "is_invalid",
-            r#"
-        Reference verification.
-
-        The condition code determines if the reference type in question is
-        invalid or not.
-        "#,
-            &formats.unary,
-        )
-        .operands_in(vec![Operand::new("x", Ref)])
-        .operands_out(vec![Operand::new("a", i8)]),
-    );
-
     ig.push(
         Inst::new(
             "bitcast",
diff --git a/cranelift/codegen/meta/src/shared/types.rs b/cranelift/codegen/meta/src/shared/types.rs
index 3bd2e2d55..d09abe179 100644
--- a/cranelift/codegen/meta/src/shared/types.rs
+++ b/cranelift/codegen/meta/src/shared/types.rs
@@ -76,38 +76,6 @@ impl Iterator for FloatIterator {
     }
 }
 
-#[derive(Debug, Clone, Copy, Eq, PartialEq, Hash)]
-pub(crate) enum Reference {
-    /// 32-bit reference.
-    R32 = 32,
-    /// 64-bit reference.
-    R64 = 64,
-}
-
-/// This provides an iterator through all of the supported reference variants.
-pub(crate) struct ReferenceIterator {
-    index: u8,
-}
-
-impl ReferenceIterator {
-    pub fn new() -> Self {
-        Self { index: 0 }
-    }
-}
-
-impl Iterator for ReferenceIterator {
-    type Item = Reference;
-    fn next(&mut self) -> Option<Self::Item> {
-        let res = match self.index {
-            0 => Some(Reference::R32),
-            1 => Some(Reference::R64),
-            _ => return None,
-        };
-        self.index += 1;
-        res
-    }
-}
-
 #[cfg(test)]
 mod iter_tests {
     use super::*;
@@ -132,12 +100,4 @@ mod iter_tests {
         assert_eq!(float_iter.next(), Some(Float::F128));
         assert_eq!(float_iter.next(), None);
     }
-
-    #[test]
-    fn reference_iter_works() {
-        let mut reference_iter = ReferenceIterator::new();
-        assert_eq!(reference_iter.next(), Some(Reference::R32));
-        assert_eq!(reference_iter.next(), Some(Reference::R64));
-        assert_eq!(reference_iter.next(), None);
-    }
 }
diff --git a/cranelift/codegen/src/inst_predicates.rs b/cranelift/codegen/src/inst_predicates.rs
index f31da8f04..e0000b726 100644
--- a/cranelift/codegen/src/inst_predicates.rs
+++ b/cranelift/codegen/src/inst_predicates.rs
@@ -38,17 +38,6 @@ fn has_side_effect(func: &Function, inst: Inst) -> bool {
     trivially_has_side_effects(opcode) || is_load_with_defined_trapping(opcode, data)
 }
 
-/// Is the given instruction a bitcast to or from a reference type (e.g. `r64`)?
-pub fn is_bitcast_from_ref(func: &Function, inst: Inst) -> bool {
-    let op = func.dfg.insts[inst].opcode();
-    if op != ir::Opcode::Bitcast {
-        return false;
-    }
-
-    let arg = func.dfg.inst_args(inst)[0];
-    func.dfg.value_type(arg).is_ref()
-}
-
 /// Does the given instruction behave as a "pure" node with respect to
 /// aegraph semantics?
 ///
@@ -76,11 +65,7 @@ pub fn is_pure_for_egraph(func: &Function, inst: Inst) -> bool {
 
     let op = func.dfg.insts[inst].opcode();
 
-    has_one_result
-        && (is_readonly_load || (!op.can_load() && !trivially_has_side_effects(op)))
-        // Cannot optimize ref-y bitcasts, as that can interact badly with
-        // safepoints and stack maps.
-        && !is_bitcast_from_ref(func, inst)
+    has_one_result && (is_readonly_load || (!op.can_load() && !trivially_has_side_effects(op)))
 }
 
 /// Can the given instruction be merged into another copy of itself?
@@ -100,9 +85,6 @@ pub fn is_mergeable_for_egraph(func: &Function, inst: Inst) -> bool {
         && !op.can_store()
         // Can only have idempotent side-effects.
         && (!has_side_effect(func, inst) || op.side_effects_idempotent())
-        // Cannot optimize ref-y bitcasts, as that can interact badly with
-        // safepoints and stack maps.
-        && !is_bitcast_from_ref(func, inst)
 }
 
 /// Does the given instruction have any side-effect as per [has_side_effect], or else is a load,
@@ -115,11 +97,7 @@ pub fn has_lowering_side_effect(func: &Function, inst: Inst) -> bool {
 /// Is the given instruction a constant value (`iconst`, `fconst`) that can be
 /// represented in 64 bits?
 pub fn is_constant_64bit(func: &Function, inst: Inst) -> Option<u64> {
-    let data = &func.dfg.insts[inst];
-    if data.opcode() == Opcode::Null {
-        return Some(0);
-    }
-    match data {
+    match &func.dfg.insts[inst] {
         &InstructionData::UnaryImm { imm, .. } => Some(imm.bits() as u64),
         &InstructionData::UnaryIeee16 { imm, .. } => Some(imm.bits() as u64),
         &InstructionData::UnaryIeee32 { imm, .. } => Some(imm.bits() as u64),
@@ -130,8 +108,7 @@ pub fn is_constant_64bit(func: &Function, inst: Inst) -> Option<u64> {
 
 /// Get the address, offset, and access type from the given instruction, if any.
 pub fn inst_addr_offset_type(func: &Function, inst: Inst) -> Option<(Value, Offset32, Type)> {
-    let data = &func.dfg.insts[inst];
-    match data {
+    match &func.dfg.insts[inst] {
         InstructionData::Load { arg, offset, .. } => {
             let ty = func.dfg.value_type(func.dfg.inst_results(inst)[0]);
             Some((*arg, *offset, ty))
@@ -154,8 +131,7 @@ pub fn inst_addr_offset_type(func: &Function, inst: Inst) -> Option<(Value, Offs
 
 /// Get the store data, if any, from an instruction.
 pub fn inst_store_data(func: &Function, inst: Inst) -> Option<Value> {
-    let data = &func.dfg.insts[inst];
-    match data {
+    match &func.dfg.insts[inst] {
         InstructionData::Store { args, .. } | InstructionData::StoreNoOffset { args, .. } => {
             Some(args[0])
         }
diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs
index 069f2adc3..ab97327e4 100644
--- a/cranelift/codegen/src/ir/instructions.rs
+++ b/cranelift/codegen/src/ir/instructions.rs
@@ -650,8 +650,6 @@ pub struct ValueTypeSet {
     pub ints: BitSet8,
     /// Allowed float widths
     pub floats: BitSet8,
-    /// Allowed ref widths
-    pub refs: BitSet8,
     /// Allowed dynamic vectors minimum lane sizes
     pub dynamic_lanes: BitSet16,
 }
@@ -666,8 +664,6 @@ impl ValueTypeSet {
             self.ints.contains(l2b)
         } else if scalar.is_float() {
             self.floats.contains(l2b)
-        } else if scalar.is_ref() {
-            self.refs.contains(l2b)
         } else {
             false
         }
@@ -976,7 +972,6 @@ mod tests {
             lanes: BitSet16::from_range(0, 8),
             ints: BitSet8::from_range(4, 7),
             floats: BitSet8::from_range(0, 0),
-            refs: BitSet8::from_range(5, 7),
             dynamic_lanes: BitSet16::from_range(0, 4),
         };
         assert!(!vts.contains(I8));
@@ -987,15 +982,12 @@ mod tests {
         assert!(!vts.contains(F16));
         assert!(!vts.contains(F32));
         assert!(!vts.contains(F128));
-        assert!(vts.contains(R32));
-        assert!(vts.contains(R64));
         assert_eq!(vts.example().to_string(), "i32");
 
         let vts = ValueTypeSet {
             lanes: BitSet16::from_range(0, 8),
             ints: BitSet8::from_range(0, 0),
             floats: BitSet8::from_range(5, 7),
-            refs: BitSet8::from_range(0, 0),
             dynamic_lanes: BitSet16::from_range(0, 8),
         };
         assert_eq!(vts.example().to_string(), "f32");
@@ -1004,7 +996,6 @@ mod tests {
             lanes: BitSet16::from_range(1, 8),
             ints: BitSet8::from_range(0, 0),
             floats: BitSet8::from_range(5, 7),
-            refs: BitSet8::from_range(0, 0),
             dynamic_lanes: BitSet16::from_range(0, 8),
         };
         assert_eq!(vts.example().to_string(), "f32x2");
@@ -1013,7 +1004,6 @@ mod tests {
             lanes: BitSet16::from_range(2, 8),
             ints: BitSet8::from_range(3, 7),
             floats: BitSet8::from_range(0, 0),
-            refs: BitSet8::from_range(0, 0),
             dynamic_lanes: BitSet16::from_range(0, 8),
         };
         assert_eq!(vts.example().to_string(), "i32x4");
@@ -1023,12 +1013,9 @@ mod tests {
             lanes: BitSet16::from_range(0, 9),
             ints: BitSet8::from_range(3, 7),
             floats: BitSet8::from_range(0, 0),
-            refs: BitSet8::from_range(0, 0),
             dynamic_lanes: BitSet16::from_range(0, 8),
         };
         assert!(vts.contains(I32));
         assert!(vts.contains(I32X4));
-        assert!(!vts.contains(R32));
-        assert!(!vts.contains(R64));
     }
 }
diff --git a/cranelift/codegen/src/ir/types.rs b/cranelift/codegen/src/ir/types.rs
index a62fffa61..bc7704cf0 100644
--- a/cranelift/codegen/src/ir/types.rs
+++ b/cranelift/codegen/src/ir/types.rs
@@ -57,8 +57,8 @@ impl Type {
         match self.lane_type() {
             I8 => 3,
             I16 | F16 => 4,
-            I32 | F32 | R32 => 5,
-            I64 | F64 | R64 => 6,
+            I32 | F32 => 5,
+            I64 | F64 => 6,
             I128 | F128 => 7,
             _ => 0,
         }
@@ -69,8 +69,8 @@ impl Type {
         match self.lane_type() {
             I8 => 8,
             I16 | F16 => 16,
-            I32 | F32 | R32 => 32,
-            I64 | F64 | R64 => 64,
+            I32 | F32 => 32,
+            I64 | F64 => 64,
             I128 | F128 => 128,
             _ => 0,
         }
@@ -139,7 +139,6 @@ impl Type {
             I16 | F16 => I16,
             I32 | F32 => I32,
             I64 | F64 => I64,
-            R32 | R64 => panic!("Reference types are not truthy"),
             I128 | F128 => I128,
             _ => I8,
         })
@@ -162,8 +161,8 @@ impl Type {
         self.replace_lanes(match self.lane_type() {
             I8 => I8,
             I16 | F16 => I16,
-            I32 | F32 | R32 => I32,
-            I64 | F64 | R64 => I64,
+            I32 | F32 => I32,
+            I64 | F64 => I64,
             I128 | F128 => I128,
             _ => unimplemented!(),
         })
@@ -244,14 +243,6 @@ impl Type {
         }
     }
 
-    /// Is this a ref type?
-    pub fn is_ref(self) -> bool {
-        match self {
-            R32 | R64 => true,
-            _ => false,
-        }
-    }
-
     /// Get log_2 of the number of lanes in this SIMD vector type.
     ///
     /// All SIMD types have a lane count that is a power of two and no larger than 256, so this
@@ -437,8 +428,6 @@ impl Display for Type {
             write!(f, "{}x{}", self.lane_type(), self.lane_count())
         } else if self.is_dynamic_vector() {
             write!(f, "{:?}x{}xN", self.lane_type(), self.min_lane_count())
-        } else if self.is_ref() {
-            write!(f, "r{}", self.lane_bits())
         } else {
             match *self {
                 INVALID => panic!("INVALID encountered"),
@@ -458,8 +447,6 @@ impl Debug for Type {
             write!(f, "{:?}X{}", self.lane_type(), self.lane_count())
         } else if self.is_dynamic_vector() {
             write!(f, "{:?}X{}XN", self.lane_type(), self.min_lane_count())
-        } else if self.is_ref() {
-            write!(f, "types::R{}", self.lane_bits())
         } else {
             match *self {
                 INVALID => write!(f, "types::INVALID"),
@@ -495,8 +482,6 @@ mod tests {
         assert_eq!(F128, F128.lane_type());
         assert_eq!(I32, I32X4.lane_type());
         assert_eq!(F64, F64X2.lane_type());
-        assert_eq!(R32, R32.lane_type());
-        assert_eq!(R64, R64.lane_type());
 
         assert_eq!(INVALID.lane_bits(), 0);
         assert_eq!(I8.lane_bits(), 8);
@@ -508,8 +493,6 @@ mod tests {
         assert_eq!(F32.lane_bits(), 32);
         assert_eq!(F64.lane_bits(), 64);
         assert_eq!(F128.lane_bits(), 128);
-        assert_eq!(R32.lane_bits(), 32);
-        assert_eq!(R64.lane_bits(), 64);
     }
 
     #[test]
@@ -602,8 +585,6 @@ mod tests {
         assert_eq!(I128.to_string(), "i128");
         assert_eq!(F32.to_string(), "f32");
         assert_eq!(F64.to_string(), "f64");
-        assert_eq!(R32.to_string(), "r32");
-        assert_eq!(R64.to_string(), "r64");
     }
 
     #[test]
diff --git a/cranelift/codegen/src/ir/user_stack_maps.rs b/cranelift/codegen/src/ir/user_stack_maps.rs
index fe495a814..6ad9b697c 100644
--- a/cranelift/codegen/src/ir/user_stack_maps.rs
+++ b/cranelift/codegen/src/ir/user_stack_maps.rs
@@ -25,8 +25,7 @@
 //! the associated stack map entries to each safepoint themselves (see
 //! `cranelift_frontend::Function::declare_needs_stack_map` and
 //! `cranelift_codegen::ir::DataFlowGraph::append_user_stack_map_entry`). Cranelift
-//! will not insert spills and record these stack map entries automatically (in
-//! contrast to the old system and its `r64` values).
+//! will not insert spills and record these stack map entries automatically.
 //!
 //! Logically, a set of stack maps for a function record a table of the form:
 //!
diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs
index 176570cb0..59a493ea2 100644
--- a/cranelift/codegen/src/isa/aarch64/abi.rs
+++ b/cranelift/codegen/src/isa/aarch64/abi.rs
@@ -155,12 +155,6 @@ impl ABIMachineSpec for AArch64MachineDeps {
         };
 
         for param in params {
-            assert!(
-                legal_type_for_machine(param.value_type),
-                "Invalid type for AArch64: {:?}",
-                param.value_type
-            );
-
             if is_apple_cc && param.value_type == types::F128 && !flags.enable_llvm_abi_extensions()
             {
                 panic!(
@@ -1329,15 +1323,6 @@ impl AArch64CallSite {
     }
 }
 
-/// Is this type supposed to be seen on this machine? E.g. references of the
-/// wrong width are invalid.
-fn legal_type_for_machine(ty: Type) -> bool {
-    match ty {
-        R32 => false,
-        _ => true,
-    }
-}
-
 /// Is the given register saved in the prologue if clobbered, i.e., is it a
 /// callee-save?
 fn is_reg_saved_in_prologue(
diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle
index d7aaaed0d..e55586a95 100644
--- a/cranelift/codegen/src/isa/aarch64/inst.isle
+++ b/cranelift/codegen/src/isa/aarch64/inst.isle
@@ -3527,27 +3527,6 @@
             (_ Unit (emit (MInst.AtomicCASLoop ty flags addr expect replace dst scratch))))
         dst))
 
-;; Copy a register of the given type to a new register.
-;;
-;; Generally, regalloc should take care of this kind of thing for us. This is
-;; only useful for implementing things like `bitcast` from an `r64` to an `i64`
-;; to avoid conflicting constraints on a single aliased value by splitting the
-;; value into two parts.
-(decl copy_reg (Type Reg) Reg)
-(rule (copy_reg $I32 src)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit (MInst.Mov (OperandSize.Size32)
-                                     dst
-                                     src))))
-        dst))
-(rule (copy_reg $I64 src)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.Mov (OperandSize.Size64)
-                                     dst
-                                     src))))
-        dst))
-
-
 ;; Helper for emitting `MInst.MovPReg` instructions.
 (decl mov_from_preg (PReg) Reg)
 (rule (mov_from_preg src)
diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index a7f3ba714..eff651e57 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -1,7 +1,7 @@
 //! This module defines aarch64-specific machine instruction types.
 
 use crate::binemit::{Addend, CodeOffset, Reloc};
-use crate::ir::types::{F128, F16, F32, F64, I128, I16, I32, I64, I8, I8X16, R32, R64};
+use crate::ir::types::{F128, F16, F32, F64, I128, I16, I32, I64, I8, I8X16};
 use crate::ir::{types, ExternalName, MemFlags, Type};
 use crate::isa::{CallConv, FunctionAlignment};
 use crate::machinst::*;
@@ -271,12 +271,12 @@ impl Inst {
                 mem,
                 flags,
             },
-            I32 | R32 => Inst::ULoad32 {
+            I32 => Inst::ULoad32 {
                 rd: into_reg,
                 mem,
                 flags,
             },
-            I64 | R64 => Inst::ULoad64 {
+            I64 => Inst::ULoad64 {
                 rd: into_reg,
                 mem,
                 flags,
@@ -327,12 +327,12 @@ impl Inst {
                 mem,
                 flags,
             },
-            I32 | R32 => Inst::Store32 {
+            I32 => Inst::Store32 {
                 rd: from_reg,
                 mem,
                 flags,
             },
-            I64 | R64 => Inst::Store64 {
+            I64 => Inst::Store64 {
                 rd: from_reg,
                 mem,
                 flags,
@@ -1156,8 +1156,6 @@ impl MachInst for Inst {
             I16 => Ok((&[RegClass::Int], &[I16])),
             I32 => Ok((&[RegClass::Int], &[I32])),
             I64 => Ok((&[RegClass::Int], &[I64])),
-            R32 => panic!("32-bit reftype pointer should never be seen on AArch64"),
-            R64 => Ok((&[RegClass::Int], &[R64])),
             F16 => Ok((&[RegClass::Float], &[F16])),
             F32 => Ok((&[RegClass::Float], &[F32])),
             F64 => Ok((&[RegClass::Float], &[F64])),
diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle
index a36d0d6fc..415d40854 100644
--- a/cranelift/codegen/src/isa/aarch64/lower.isle
+++ b/cranelift/codegen/src/isa/aarch64/lower.isle
@@ -19,11 +19,6 @@
 (rule (lower (has_type ty (iconst (u64_from_imm64 n))))
       (imm ty (ImmExtend.Zero) n))
 
-;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (null)))
-      (imm ty (ImmExtend.Zero) 0))
-
 ;;;; Rules for `f16const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (f16const (u16_from_ieee16 n)))
@@ -2269,18 +2264,6 @@
 (rule (lower (fence))
       (side_effect (aarch64_fence)))
 
-;;;; Rules for `IsNull` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (is_null x @ (value_type ty)))
-      (with_flags (cmp_imm (operand_size ty) x (u8_into_imm12 0))
-                  (materialize_bool_result (Cond.Eq))))
-
-;;;; Rules for `IsInvalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (is_invalid x @ (value_type ty)))
-      (with_flags (cmn_imm (operand_size ty) x (u8_into_imm12 1))
-                  (materialize_bool_result (Cond.Eq))))
-
 ;;;; Rules for `Debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (debugtrap))
@@ -2343,9 +2326,6 @@
 (rule (lower
        (has_type $I64 (load flags address offset)))
       (aarch64_uload64 (amode $I64 address offset) flags))
-(rule (lower
-       (has_type $R64 (load flags address offset)))
-      (aarch64_uload64 (amode $I64 address offset) flags))
 (rule (lower
        (has_type $F16 (load flags address offset)))
       (aarch64_fpuload16 (amode $F16 address offset) flags))
@@ -2452,10 +2432,6 @@
        (store flags value @ (value_type $I64) address offset))
       (side_effect
        (aarch64_store64 (amode $I64 address offset) flags value)))
-(rule (lower
-       (store flags value @ (value_type $R64) address offset))
-      (side_effect
-       (aarch64_store64 (amode $I64 address offset) flags value)))
 
 (rule (lower
        (istore8 flags value address offset))
@@ -2543,22 +2519,6 @@
       (if (ty_int_ref_scalar_64 out_ty))
       (mov_from_vec x 0 (scalar_size out_ty)))
 
-;; Bitcasts between `r{32,64}` and `i{32,64}` need to be a copy to avoid
-;; conflicting regalloc constraints on reference type values that both need to
-;; be in some register but also some safepoint stack slot at the same time.
-(rule 2 (lower (has_type dst_ty (bitcast _ x @ (value_type src_ty))))
-      (if (ty_int_ref_scalar_64 src_ty))
-      (if (ty_int_ref_scalar_64 dst_ty))
-      (if-let $true (is_ref_type src_ty))
-      (if-let $false (is_ref_type dst_ty))
-      (copy_reg dst_ty x))
-(rule 2 (lower (has_type dst_ty (bitcast _ x @ (value_type src_ty))))
-      (if (ty_int_ref_scalar_64 src_ty))
-      (if (ty_int_ref_scalar_64 dst_ty))
-      (if-let $false (is_ref_type src_ty))
-      (if-let $true (is_ref_type dst_ty))
-      (copy_reg src_ty x))
-
 ; GPR <=> GPR
 (rule 1 (lower (has_type out_ty (bitcast _ x @ (value_type in_ty))))
       (if (ty_int_ref_scalar_64 out_ty))
diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs
index b1f099799..29a3f1c68 100644
--- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs
@@ -230,7 +230,7 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> {
 
     fn integral_ty(&mut self, ty: Type) -> Option<Type> {
         match ty {
-            I8 | I16 | I32 | I64 | R64 => Some(ty),
+            I8 | I16 | I32 | I64 => Some(ty),
             _ => None,
         }
     }
diff --git a/cranelift/codegen/src/isa/pulley_shared/inst.isle b/cranelift/codegen/src/isa/pulley_shared/inst.isle
index 986085118..6301353a7 100644
--- a/cranelift/codegen/src/isa/pulley_shared/inst.isle
+++ b/cranelift/codegen/src/isa/pulley_shared/inst.isle
@@ -335,10 +335,6 @@
 (rule 0 (imm $I32 x) (pulley_xconst32 (u64_as_i32 x)))
 (rule 0 (imm $I64 x) (pulley_xconst64 (u64_as_i64 x)))
 
-;; References are actually integers.
-(rule 0 (imm $R32 x) (imm $I32 x))
-(rule 0 (imm $R64 x) (imm $I64 x))
-
 ;; Base cases for floats.
 (rule 0 (imm $F32 c) (gen_bitcast (imm $I32 c) $I32 $F32))
 (rule 0 (imm $F64 c) (gen_bitcast (imm $I64 c) $I64 $F64))
@@ -351,22 +347,8 @@
 (rule (gen_bitcast r $F64 $I64) (pulley_bitcast_float_from_int_64 r))
 (rule (gen_bitcast r $I32 $F32) (pulley_bitcast_int_from_float_32 r))
 (rule (gen_bitcast r $I64 $F64) (pulley_bitcast_int_from_float_64 r))
-(rule (gen_bitcast r $I64 $R64) (copy_reg r $I64))
-(rule (gen_bitcast r $R64 $I64) (copy_reg r $I64))
 (rule -1 (gen_bitcast r ty ty) r)
 
-;; Copy a register of the given type to a new register.
-;;
-;; Generally, regalloc should take care of this kind of thing for us. This is
-;; only useful for implementing things like `bitcast` from an `r64` to an `i64`
-;; to avoid conflicting constraints on a single aliased value by splitting the
-;; value into two parts.
-(decl copy_reg (Reg Type) Reg)
-(rule (copy_reg src (ty_int_ref_scalar_64 ty))
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.Xmov dst src))))
-        dst))
-
 ;;;; Instruction Constructors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl pulley_trap (TrapCode) SideEffectNoResult)
diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs
index bf6bae4c3..8051ae9f3 100644
--- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs
+++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs
@@ -3,7 +3,7 @@
 use core::marker::PhantomData;
 
 use crate::binemit::{Addend, CodeOffset, Reloc};
-use crate::ir::types::{self, F32, F64, I128, I16, I32, I64, I8, I8X16, R32, R64};
+use crate::ir::types::{self, F32, F64, I128, I16, I32, I64, I8, I8X16};
 use crate::ir::{self, MemFlags, Type};
 use crate::isa::pulley_shared::abi::PulleyMachineDeps;
 use crate::isa::FunctionAlignment;
@@ -409,8 +409,6 @@ where
             I16 => Ok((&[RegClass::Int], &[I16])),
             I32 => Ok((&[RegClass::Int], &[I32])),
             I64 => Ok((&[RegClass::Int], &[I64])),
-            R32 => Ok((&[RegClass::Int], &[R32])),
-            R64 => Ok((&[RegClass::Int], &[R64])),
             F32 => Ok((&[RegClass::Float], &[F32])),
             F64 => Ok((&[RegClass::Float], &[F64])),
             I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index d345cd064..1e9e004b3 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -1867,10 +1867,6 @@
 (rule 6 (imm (ty_supported_float $F32) c) (gen_bitcast (imm $I32 c) $I32 $F32))
 (rule 6 (imm (ty_supported_float $F64) c) (gen_bitcast (imm $I64 c) $I64 $F64))
 
-;; Refs get loaded as integers.
-(rule 5 (imm $R32 c) (imm $I32 c))
-(rule 5 (imm $R64 c) (imm $I64 c))
-
 ;; Try to match just an imm12
 (rule 4 (imm (ty_int ty) c)
   (if-let (i64_generate_imm (imm20_is_zero) imm12) (i64_sextend_u64 ty c))
@@ -2938,8 +2934,6 @@
 (rule 1 (gen_bitcast r $I16 $F16) (rv_fmvhx r))
 (rule 1 (gen_bitcast r $I32 $F32) (rv_fmvwx r))
 (rule 1 (gen_bitcast r $I64 $F64) (rv_fmvdx r))
-(rule 1 (gen_bitcast r $I64 $R64) (copy_reg r $I64))
-(rule 1 (gen_bitcast r $R64 $I64) (copy_reg r $I64))
 (rule (gen_bitcast r _ _) r)
 
 (decl move_f_to_x (FReg Type) XReg)
@@ -3051,20 +3045,6 @@
         (_ Unit (emit (MInst.MovFromPReg rd rm))))
     rd))
 
-;; Copy a register of the given type to a new register.
-;;
-;; Generally, regalloc should take care of this kind of thing for us. This is
-;; only useful for implementing things like `bitcast` from an `r64` to an `i64`
-;; to avoid conflicting constraints on a single aliased value by splitting the
-;; value into two parts.
-(decl copy_reg (XReg Type) XReg)
-(rule (copy_reg src ty)
-      (let ((dst WritableXReg (temp_writable_xreg))
-            (_ Unit (emit (MInst.Mov dst
-                                     src
-                                     ty))))
-        dst))
-
 (decl fp_reg () PReg)
 (extern constructor fp_reg fp_reg)
 
diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs
index 60123aeb8..1d5449678 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/args.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs
@@ -1184,8 +1184,7 @@ impl LoadOP {
             I8 => Self::Lb,
             I16 => Self::Lh,
             I32 => Self::Lw,
-            R32 => Self::Lwu,
-            R64 | I64 => Self::Ld,
+            I64 => Self::Ld,
             _ => unreachable!(),
         }
     }
@@ -1242,8 +1241,8 @@ impl StoreOP {
             F64 => Self::Fsd,
             I8 => Self::Sb,
             I16 => Self::Sh,
-            I32 | R32 => Self::Sw,
-            I64 | R64 => Self::Sd,
+            I32 => Self::Sw,
+            I64 => Self::Sd,
             _ => unreachable!(),
         }
     }
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index 70ca1d019..292892b9f 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -3,7 +3,7 @@
 use super::lower::isle::generated_code::{VecAMode, VecElementWidth, VecOpMasking};
 use crate::binemit::{Addend, CodeOffset, Reloc};
 pub use crate::ir::condcodes::IntCC;
-use crate::ir::types::{self, F128, F16, F32, F64, I128, I16, I32, I64, I8, I8X16, R32, R64};
+use crate::ir::types::{self, F128, F16, F32, F64, I128, I16, I32, I64, I8, I8X16};
 
 pub use crate::ir::{ExternalName, MemFlags, Type};
 use crate::isa::{CallConv, FunctionAlignment};
@@ -805,8 +805,6 @@ impl MachInst for Inst {
             I16 => Ok((&[RegClass::Int], &[I16])),
             I32 => Ok((&[RegClass::Int], &[I32])),
             I64 => Ok((&[RegClass::Int], &[I64])),
-            R32 => panic!("32-bit reftype pointer should never be seen on riscv64"),
-            R64 => Ok((&[RegClass::Int], &[R64])),
             F16 => Ok((&[RegClass::Float], &[F16])),
             F32 => Ok((&[RegClass::Float], &[F32])),
             F64 => Ok((&[RegClass::Float], &[F64])),
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index 7e3328af7..41c07ae00 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -29,12 +29,6 @@
 (rule (lower (f64const (u64_from_ieee64 n)))
   (imm $F64 n))
 
-;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (null)))
-  (imm ty 0))
-
-
 ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Base case, simply adding things in registers.
@@ -1848,18 +1842,6 @@
   (lower (stack_addr ss offset))
   (gen_stack_addr ss offset))
 
-;;;;;  Rules for `is_null`;;;;;;;;;
-
-;; Null references are represented by the constant value `0`.
-(rule (lower (is_null v))
-  (rv_seqz v))
-
-;;;;;  Rules for `is_invalid`;;;;;;;;;
-
-;; Invalid references are represented by the constant value `-1`.
-(rule (lower (is_invalid v))
-  (rv_seqz (rv_addi v (imm12_const 1))))
-
 ;;;;;  Rules for `select`;;;;;;;;;
 
 ;; Manually matching (iconst 0) here is a bit of a hack. We can't do that as part
diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
index e4d516e22..3c0090d0b 100644
--- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
@@ -191,8 +191,6 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
         let supported = match ty {
             // Scalar integers are always supported
             ty if ty.is_int() => true,
-            // So are references
-            ty if ty.is_ref() => true,
             // Floating point types depend on certain extensions
             F16 => self.backend.isa_flags.has_zfh(),
             // F32 depends on the F extension
diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs
index e69ed03f6..20082a80b 100644
--- a/cranelift/codegen/src/isa/s390x/abi.rs
+++ b/cranelift/codegen/src/isa/s390x/abi.rs
@@ -158,7 +158,7 @@ pub type S390xCallee = Callee<S390xMachineDeps>;
 
 fn in_int_reg(ty: Type) -> bool {
     match ty {
-        types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
+        types::I8 | types::I16 | types::I32 | types::I64 => true,
         _ => false,
     }
 }
diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle
index 9745c2784..f4a88a254 100644
--- a/cranelift/codegen/src/isa/s390x/inst.isle
+++ b/cranelift/codegen/src/isa/s390x/inst.isle
@@ -2865,7 +2865,6 @@
 (rule (arg_store $I16 reg mem) (store16 reg mem))
 (rule (arg_store $I32 reg mem) (store32 reg mem))
 (rule (arg_store $I64 reg mem) (store64 reg mem))
-(rule (arg_store $R64 reg mem) (store64 reg mem))
 (rule (arg_store $F32 reg mem) (vec_store_lane $F32X4 reg mem 0))
 (rule (arg_store $F64 reg mem) (vec_store_lane $F64X2 reg mem 0))
 (rule -1 (arg_store (vr128_ty ty) reg mem) (vec_store reg mem))
@@ -2875,7 +2874,6 @@
 (rule (arg_load $I16 mem) (zext32_mem $I16 mem))
 (rule (arg_load $I32 mem) (load32 mem))
 (rule (arg_load $I64 mem) (load64 mem))
-(rule (arg_load $R64 mem) (load64 mem))
 (rule (arg_load $F32 mem) (vec_load_lane_undef $F32X4 mem 0))
 (rule (arg_load $F64 mem) (vec_load_lane_undef $F64X2 mem 0))
 (rule -1 (arg_load (vr128_ty ty) mem) (vec_load ty mem))
@@ -2948,8 +2946,6 @@
 ;; Copy reference values into registers of integer type.
 ;; Zero- or sign-extend as required by the ABI.
 (decl prepare_arg_val (ABIArgSlot Value) Reg)
-(rule 1 (prepare_arg_val (ABIArgSlot.Reg _ $R64 (ArgumentExtension.None)) val)
-        (copy_reg $I64 val))
 (rule (prepare_arg_val (ABIArgSlot.Reg _ _ (ArgumentExtension.None)) val)
       val)
 (rule (prepare_arg_val (ABIArgSlot.Reg _ _ (ArgumentExtension.Uext)) val)
diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs
index ed8a98e26..763c35a51 100644
--- a/cranelift/codegen/src/isa/s390x/inst/mod.rs
+++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs
@@ -361,7 +361,7 @@ impl Inst {
             types::I8 => Inst::Load64ZExt8 { rd: into_reg, mem },
             types::I16 => Inst::Load64ZExt16 { rd: into_reg, mem },
             types::I32 => Inst::Load64ZExt32 { rd: into_reg, mem },
-            types::I64 | types::R64 => Inst::Load64 { rd: into_reg, mem },
+            types::I64 => Inst::Load64 { rd: into_reg, mem },
             types::F32 => Inst::VecLoadLaneUndef {
                 size: 32,
                 rd: into_reg,
@@ -386,7 +386,7 @@ impl Inst {
             types::I8 => Inst::Store8 { rd: from_reg, mem },
             types::I16 => Inst::Store16 { rd: from_reg, mem },
             types::I32 => Inst::Store32 { rd: from_reg, mem },
-            types::I64 | types::R64 => Inst::Store64 { rd: from_reg, mem },
+            types::I64 => Inst::Store64 { rd: from_reg, mem },
             types::F32 => Inst::VecStoreLane {
                 size: 32,
                 rd: from_reg,
@@ -1156,8 +1156,6 @@ impl MachInst for Inst {
             types::I16 => Ok((&[RegClass::Int], &[types::I16])),
             types::I32 => Ok((&[RegClass::Int], &[types::I32])),
             types::I64 => Ok((&[RegClass::Int], &[types::I64])),
-            types::R32 => panic!("32-bit reftype pointer should never be seen on s390x"),
-            types::R64 => Ok((&[RegClass::Int], &[types::R64])),
             types::F32 => Ok((&[RegClass::Float], &[types::F32])),
             types::F64 => Ok((&[RegClass::Float], &[types::F64])),
             types::I128 => Ok((&[RegClass::Float], &[types::I128])),
diff --git a/cranelift/codegen/src/isa/s390x/lower.isle b/cranelift/codegen/src/isa/s390x/lower.isle
index bc69221ac..d0efcd25f 100644
--- a/cranelift/codegen/src/isa/s390x/lower.isle
+++ b/cranelift/codegen/src/isa/s390x/lower.isle
@@ -34,12 +34,6 @@
       (vec_imm ty (be_vec_const ty x)))
 
 
-;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (null)))
-      (imm ty 0))
-
-
 ;;;; Rules for `nop` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (nop))
@@ -1726,18 +1720,6 @@
 (rule (lower (has_type $I32 (bitcast _ x @ (value_type $F32))))
       (vec_extract_lane $F32X4 x 0 (zero_reg)))
 
-;; Bitcasts between `r{32,64}` and `i{32,64}` need to be a copy to avoid
-;; conflicting regalloc constraints on reference type values that both need to
-;; be in some register but also some safepoint stack slot at the same time.
-(rule 6 (lower (has_type $R32 (bitcast _ x @ (value_type $I32))))
-      (copy_reg $I32 x))
-(rule 6 (lower (has_type $R64 (bitcast _ x @ (value_type $I64))))
-      (copy_reg $I64 x))
-(rule 6 (lower (has_type $I32 (bitcast _ x @ (value_type $R32))))
-      (copy_reg $I32 x))
-(rule 6 (lower (has_type $I64 (bitcast _ x @ (value_type $R64))))
-      (copy_reg $I64 x))
-
 ;; Bitcast between types residing in GPRs is a no-op.
 (rule 1 (lower (has_type (gpr32_ty _)
                          (bitcast _ x @ (value_type (gpr32_ty _)))))
@@ -2327,14 +2309,6 @@
 (rule -1 (lower (has_type $I64 (load flags @ (littleendian) addr offset)))
       (loadrev64 (lower_address flags addr offset)))
 
-;; Load 64-bit big-endian references.
-(rule (lower (has_type $R64 (load flags @ (bigendian) addr offset)))
-      (load64 (lower_address flags addr offset)))
-
-;; Load 64-bit little-endian references.
-(rule -1 (lower (has_type $R64 (load flags @ (littleendian) addr offset)))
-      (loadrev64 (lower_address flags addr offset)))
-
 ;; Load 32-bit big-endian floating-point values (as vector lane).
 (rule (lower (has_type $F32 (load flags @ (bigendian) addr offset)))
       (vec_load_lane_undef $F32X4 (lower_address flags addr offset) 0))
@@ -2653,10 +2627,6 @@
 (rule (lower (store flags val @ (value_type $I64) addr offset))
       (side_effect (istore64_impl flags val addr offset)))
 
-;; Store 64-bit reference type, main lowering entry point.
-(rule (lower (store flags val @ (value_type $R64) addr offset))
-      (side_effect (istore64_impl flags val addr offset)))
-
 ;; Store 32-bit big-endian floating-point type (as vector lane).
 (rule -1 (lower (store flags @ (bigendian)
                     val @ (value_type $F32) addr offset))
@@ -3689,20 +3659,6 @@
         (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
 
 
-;;;; Rules for `is_null` and `is_invalid`  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Null references are represented by the constant value 0.
-(rule (lower (has_type $I8 (is_null x @ (value_type $R64))))
-      (lower_bool $I8 (bool (icmps_simm16 $I64 x 0)
-                            (intcc_as_cond (IntCC.Equal)))))
-
-
-;; Invalid references are represented by the constant value -1.
-(rule (lower (has_type $I8 (is_invalid x @ (value_type $R64))))
-      (lower_bool $I8 (bool (icmps_simm16 $I64 x -1)
-                            (intcc_as_cond (IntCC.Equal)))))
-
-
 ;;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Return a `ProducesBool` to capture the fact that the input value is nonzero.
diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs
index a3812a6d9..42c769536 100644
--- a/cranelift/codegen/src/isa/s390x/lower/isle.rs
+++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs
@@ -488,7 +488,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, S390xBackend> {
     #[inline]
     fn gpr64_ty(&mut self, ty: Type) -> Option<Type> {
         match ty {
-            I64 | R64 => Some(ty),
+            I64 => Some(ty),
             _ => None,
         }
     }
diff --git a/cranelift/codegen/src/isa/x64/inst.isle b/cranelift/codegen/src/isa/x64/inst.isle
index 30377633e..80e46ec44 100644
--- a/cranelift/codegen/src/isa/x64/inst.isle
+++ b/cranelift/codegen/src/isa/x64/inst.isle
@@ -5337,20 +5337,6 @@
 (decl put_in_xmm_mem_aligned (Value) XmmMemAligned)
 (rule (put_in_xmm_mem_aligned val) (put_in_xmm_mem val))
 
-;; Copy a GPR of the given type to a new GPR.
-;;
-;; Generally, regalloc should take care of this kind of thing for us. This is
-;; only useful for implementing things like `bitcast` from an `r64` to an `i64`
-;; to avoid conflicting constraints on a single aliased value by splitting the
-;; value into two parts.
-(decl copy_gpr (Type Gpr) Gpr)
-(rule (copy_gpr ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.MovRR (operand_size_of_type_32_64 ty)
-                                       src
-                                       dst))))
-        dst))
-
 (decl mov_to_preg (PReg Gpr) SideEffectNoResult)
 (rule (mov_to_preg dst src)
       (SideEffectNoResult.Inst (MInst.MovToPReg src dst)))
diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index b255e12ef..705d8151b 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -2664,8 +2664,6 @@ impl MachInst for Inst {
             types::I16 => Ok((&[RegClass::Int], &[types::I16])),
             types::I32 => Ok((&[RegClass::Int], &[types::I32])),
             types::I64 => Ok((&[RegClass::Int], &[types::I64])),
-            types::R32 => panic!("32-bit reftype pointer should never be seen on x86-64"),
-            types::R64 => Ok((&[RegClass::Int], &[types::R64])),
             types::F16 => Ok((&[RegClass::Float], &[types::F16])),
             types::F32 => Ok((&[RegClass::Float], &[types::F32])),
             types::F64 => Ok((&[RegClass::Float], &[types::F64])),
diff --git a/cranelift/codegen/src/isa/x64/lower.isle b/cranelift/codegen/src/isa/x64/lower.isle
index fea56b48d..538aa5ba0 100644
--- a/cranelift/codegen/src/isa/x64/lower.isle
+++ b/cranelift/codegen/src/isa/x64/lower.isle
@@ -45,11 +45,6 @@
 (rule 1 (lower (f128const (u128_from_constant 0)))
       (xmm_zero $F128))
 
-;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (null)))
-      (imm ty 0))
-
 ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; `i64` and smaller.
@@ -2502,23 +2497,6 @@
        (x64_bswap $I64 (value_regs_get_gpr src 1))
        (x64_bswap $I64 (value_regs_get_gpr src 0))))
 
-;; Rules for `is_null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Null references are represented by the constant value `0`.
-(rule (lower (is_null src @ (value_type $R64)))
-      (with_flags
-       (x64_cmp_imm (OperandSize.Size64) src 0)
-       (x64_setcc (CC.Z))))
-
-;; Rules for `is_invalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Invalid references are represented by the constant value `-1`.
-(rule (lower (is_invalid src @ (value_type $R64)))
-      (with_flags
-       (x64_cmp_imm (OperandSize.Size64) src 0xffffffff)  ;; simm32 0xffff_ffff is sign-extended to -1.
-       (x64_setcc (CC.Z))))
-
-
 ;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; I{8,16,32,64} -> I128.
@@ -4134,20 +4112,6 @@
                          (bitcast _ x @ (value_type (is_gpr_type _)))))
       x)
 
-;; Bitcasts between `r{32,64}` and `i{32,64}` need to be a copy to avoid
-;; conflicting regalloc constraints on reference type values that both need to
-;; be in some register but also some safepoint stack slot at the same time.
-(rule 2 (lower (has_type (is_gpr_type dst_ty)
-                         (bitcast _ x @ (value_type (is_gpr_type src_ty)))))
-      (if-let $true (is_ref_type src_ty))
-      (if-let $false (is_ref_type dst_ty))
-      (copy_gpr dst_ty x))
-(rule 2 (lower (has_type (is_gpr_type dst_ty)
-                         (bitcast _ x @ (value_type (is_gpr_type src_ty)))))
-      (if-let $false (is_ref_type src_ty))
-      (if-let $true (is_ref_type dst_ty))
-      (copy_gpr dst_ty x))
-
 ;; Bitcast between types residing in XMM registers is a no-op.
 (rule 3 (lower (has_type (is_xmm_type _)
                          (bitcast _ x @ (value_type (is_xmm_type _)))))
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index a063854b2..ae780089d 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -34,8 +34,7 @@ impl Lower<'_, Inst> {
 
 fn is_int_or_ref_ty(ty: Type) -> bool {
     match ty {
-        types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
-        types::R32 => panic!("shouldn't have 32-bits refs on x64"),
+        types::I8 | types::I16 | types::I32 | types::I64 => true,
         _ => false,
     }
 }
diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs
index d05950a3c..54a5ad518 100644
--- a/cranelift/codegen/src/isa/x64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/x64/lower/isle.rs
@@ -607,8 +607,7 @@ impl Context for IsleContext<'_, '_, MInst, X64Backend> {
     #[inline]
     fn ty_int_bool_or_ref(&mut self, ty: Type) -> Option<()> {
         match ty {
-            types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => Some(()),
-            types::R32 => panic!("shouldn't have 32-bits refs on x64"),
+            types::I8 | types::I16 | types::I32 | types::I64 => Some(()),
             _ => None,
         }
     }
diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs
index accb2761b..79fcd2488 100644
--- a/cranelift/codegen/src/isle_prelude.rs
+++ b/cranelift/codegen/src/isle_prelude.rs
@@ -421,7 +421,7 @@ macro_rules! isle_common_prelude_methods {
         #[inline]
         fn ty_int_ref_64(&mut self, ty: Type) -> Option<Type> {
             match ty {
-                I64 | R64 => Some(ty),
+                I64 => Some(ty),
                 _ => None,
             }
         }
@@ -429,7 +429,7 @@ macro_rules! isle_common_prelude_methods {
         #[inline]
         fn ty_int_ref_16_to_64(&mut self, ty: Type) -> Option<Type> {
             match ty {
-                I16 | I32 | I64 | R64 => Some(ty),
+                I16 | I32 | I64 => Some(ty),
                 _ => None,
             }
         }
@@ -549,7 +549,7 @@ macro_rules! isle_common_prelude_methods {
         #[inline]
         fn ty_addr64(&mut self, ty: Type) -> Option<Type> {
             match ty {
-                I64 | R64 => Some(ty),
+                I64 => Some(ty),
                 _ => None,
             }
         }
diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs
index bd2c211fb..7760aef20 100644
--- a/cranelift/codegen/src/machinst/abi.rs
+++ b/cranelift/codegen/src/machinst/abi.rs
@@ -2096,37 +2096,27 @@ impl<M: ABIMachineSpec> CallSite<M> {
                             reg, ty, extension, ..
                         } => {
                             let ext = M::get_ext_mode(ctx.sigs()[self.sig].call_conv, extension);
-                            let vreg = if ext != ir::ArgumentExtension::None
-                                && ty_bits(ty) < word_bits
-                            {
-                                assert_eq!(word_rc, reg.class());
-                                let signed = match ext {
-                                    ir::ArgumentExtension::Uext => false,
-                                    ir::ArgumentExtension::Sext => true,
-                                    _ => unreachable!(),
+                            let vreg =
+                                if ext != ir::ArgumentExtension::None && ty_bits(ty) < word_bits {
+                                    assert_eq!(word_rc, reg.class());
+                                    let signed = match ext {
+                                        ir::ArgumentExtension::Uext => false,
+                                        ir::ArgumentExtension::Sext => true,
+                                        _ => unreachable!(),
+                                    };
+                                    let extend_result =
+                                        ctx.alloc_tmp(M::word_type()).only_reg().unwrap();
+                                    ctx.emit(M::gen_extend(
+                                        extend_result,
+                                        *from_reg,
+                                        signed,
+                                        ty_bits(ty) as u8,
+                                        word_bits as u8,
+                                    ));
+                                    extend_result.to_reg()
+                                } else {
+                                    *from_reg
                                 };
-                                let extend_result =
-                                    ctx.alloc_tmp(M::word_type()).only_reg().unwrap();
-                                ctx.emit(M::gen_extend(
-                                    extend_result,
-                                    *from_reg,
-                                    signed,
-                                    ty_bits(ty) as u8,
-                                    word_bits as u8,
-                                ));
-                                extend_result.to_reg()
-                            } else if ty.is_ref() {
-                                // Reference-typed args need to be
-                                // passed as a copy; the original vreg
-                                // is constrained to the stack and
-                                // this copy is in a reg.
-                                let ref_copy = ctx.alloc_tmp(M::word_type()).only_reg().unwrap();
-                                ctx.emit(M::gen_move(ref_copy, *from_reg, M::word_type()));
-
-                                ref_copy.to_reg()
-                            } else {
-                                *from_reg
-                            };
 
                             let preg = reg.into();
                             self.uses.push(CallArgPair { vreg, preg });
diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs
index 0ea503bec..f2f9fe73b 100644
--- a/cranelift/codegen/src/machinst/vcode.rs
+++ b/cranelift/codegen/src/machinst/vcode.rs
@@ -185,11 +185,6 @@ pub struct VCode<I: VCodeInst> {
     /// immutable across function compilations within the same module.
     emit_info: I::Info,
 
-    /// Reference-typed `regalloc2::VReg`s. The regalloc requires
-    /// these in a dense slice (as opposed to querying the
-    /// reftype-status of each vreg) for efficient iteration.
-    reftyped_vregs: Vec<VReg>,
-
     /// Constants.
     pub(crate) constants: VCodeConstants,
 
@@ -543,26 +538,12 @@ impl<I: VCodeInst> VCodeBuilder<I> {
     pub fn build(mut self, mut vregs: VRegAllocator<I>) -> VCode<I> {
         self.vcode.vreg_types = take(&mut vregs.vreg_types);
         self.vcode.facts = take(&mut vregs.facts);
-        self.vcode.reftyped_vregs = take(&mut vregs.reftyped_vregs);
 
         if self.direction == VCodeBuildDirection::Backward {
             self.reverse_and_finalize(&vregs);
         }
         self.collect_operands(&vregs);
 
-        // Apply register aliases to the `reftyped_vregs` list since this list
-        // will be returned directly to `regalloc2` eventually and all
-        // operands/results of instructions will use the alias-resolved vregs
-        // from `regalloc2`'s perspective.
-        //
-        // Also note that `reftyped_vregs` can't have duplicates, so after the
-        // aliases are applied duplicates are removed.
-        for reg in self.vcode.reftyped_vregs.iter_mut() {
-            *reg = vregs.resolve_vreg_alias(*reg);
-        }
-        self.vcode.reftyped_vregs.sort();
-        self.vcode.reftyped_vregs.dedup();
-
         self.compute_preds_from_succs();
         self.vcode.debug_value_labels.sort_unstable();
 
@@ -577,8 +558,6 @@ impl<I: VCodeInst> VCodeBuilder<I> {
         vregs.debug_assert_no_vreg_aliases(self.vcode.block_params.iter().copied());
         // Branch block args are resolved in collect_operands.
         vregs.debug_assert_no_vreg_aliases(self.vcode.branch_block_args.iter().copied());
-        // Reftyped vregs are resolved above in this function.
-        vregs.debug_assert_no_vreg_aliases(self.vcode.reftyped_vregs.iter().copied());
         // Debug value labels are resolved in reverse_and_finalize.
         vregs.debug_assert_no_vreg_aliases(
             self.vcode.debug_value_labels.iter().map(|&(vreg, ..)| vreg),
@@ -612,11 +591,6 @@ impl<I: VCodeInst> VCodeBuilder<I> {
     }
 }
 
-/// Is this type a reference type?
-fn is_reftype(ty: Type) -> bool {
-    ty == types::R64 || ty == types::R32
-}
-
 const NO_INST_OFFSET: CodeOffset = u32::MAX;
 
 impl<I: VCodeInst> VCode<I> {
@@ -652,7 +626,6 @@ impl<I: VCodeInst> VCode<I> {
             block_order,
             abi,
             emit_info,
-            reftyped_vregs: vec![],
             constants,
             debug_value_labels: vec![],
             facts: vec![],
@@ -1371,8 +1344,8 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
         }
     }
 
-    fn requires_refs_on_stack(&self, insn: InsnIndex) -> bool {
-        self.insts[insn.index()].is_safepoint()
+    fn requires_refs_on_stack(&self, _insn: InsnIndex) -> bool {
+        false
     }
 
     fn inst_operands(&self, insn: InsnIndex) -> &[Operand] {
@@ -1388,10 +1361,6 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
         self.vreg_types.len()
     }
 
-    fn reftype_vregs(&self) -> &[VReg] {
-        &self.reftyped_vregs
-    }
-
     fn debug_value_labels(&self) -> &[(VReg, InsnIndex, InsnIndex, u32)] {
         &self.debug_value_labels
     }
@@ -1487,11 +1456,6 @@ pub struct VRegAllocator<I> {
     /// VReg IR-level types.
     vreg_types: Vec<Type>,
 
-    /// Reference-typed `regalloc2::VReg`s. The regalloc requires
-    /// these in a dense slice (as opposed to querying the
-    /// reftype-status of each vreg) for efficient iteration.
-    reftyped_vregs: Vec<VReg>,
-
     /// VReg aliases. When the final VCode is built we rewrite all
     /// uses of the keys in this table to their replacement values.
     ///
@@ -1521,7 +1485,6 @@ impl<I: VCodeInst> VRegAllocator<I> {
         vreg_types.resize(first_user_vreg_index(), types::INVALID);
         Self {
             vreg_types,
-            reftyped_vregs: vec![],
             vreg_aliases: FxHashMap::with_capacity_and_hasher(capacity, Default::default()),
             deferred_error: None,
             facts: Vec::with_capacity(capacity),
@@ -1552,9 +1515,6 @@ impl<I: VCodeInst> VRegAllocator<I> {
             let vreg = reg.to_virtual_reg().unwrap();
             debug_assert_eq!(self.vreg_types.len(), vreg.index());
             self.vreg_types.push(reg_ty);
-            if is_reftype(reg_ty) {
-                self.reftyped_vregs.push(vreg.into());
-            }
         }
 
         // Create empty facts for each allocated vreg.
diff --git a/cranelift/codegen/src/prelude.isle b/cranelift/codegen/src/prelude.isle
index 4ec7c483c..3f4c8d12b 100644
--- a/cranelift/codegen/src/prelude.isle
+++ b/cranelift/codegen/src/prelude.isle
@@ -359,9 +359,6 @@
 (extern const $I64 Type)
 (extern const $I128 Type)
 
-(extern const $R32 Type)
-(extern const $R64 Type)
-
 (extern const $F16 Type)
 (extern const $F32 Type)
 (extern const $F64 Type)
@@ -445,11 +442,6 @@
 (decl pure ty_equal (Type Type) bool)
 (extern constructor ty_equal ty_equal)
 
-(decl pure is_ref_type (Type) bool)
-(rule 1 (is_ref_type $R32) $true)
-(rule 1 (is_ref_type $R64) $true)
-(rule 0 (is_ref_type _) $false)
-
 ;;;; `cranelift_codegen::ir::MemFlags ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; `MemFlags::trusted`
@@ -562,7 +554,7 @@
 (decl int_fits_in_32 (Type) Type)
 (extern extractor int_fits_in_32 int_fits_in_32)
 
-;; An extractor that matches I64 or R64.
+;; An extractor that matches I64.
 (decl ty_int_ref_64 (Type) Type)
 (extern extractor ty_int_ref_64 ty_int_ref_64)
 
diff --git a/cranelift/frontend/src/ssa.rs b/cranelift/frontend/src/ssa.rs
index cf232d3b3..694e467b0 100644
--- a/cranelift/frontend/src/ssa.rs
+++ b/cranelift/frontend/src/ssa.rs
@@ -142,8 +142,6 @@ fn emit_zero(ty: Type, mut cur: FuncCursor) -> Value {
         cur.ins().f32const(Ieee32::with_bits(0))
     } else if ty == F64 {
         cur.ins().f64const(Ieee64::with_bits(0))
-    } else if ty.is_ref() {
-        cur.ins().null(ty)
     } else if ty.is_vector() {
         let scalar_ty = ty.lane_type();
         if scalar_ty.is_int() {
diff --git a/cranelift/fuzzgen/src/function_generator.rs b/cranelift/fuzzgen/src/function_generator.rs
index f0ff1abd4..b7b1049ae 100644
--- a/cranelift/fuzzgen/src/function_generator.rs
+++ b/cranelift/fuzzgen/src/function_generator.rs
@@ -911,7 +911,6 @@ static OPCODE_SIGNATURES: Lazy<Vec<OpcodeSignature>> = Lazy::new(|| {
                 (Opcode::GetFramePointer),
                 (Opcode::GetStackPointer),
                 (Opcode::GetReturnAddress),
-                (Opcode::Null),
                 (Opcode::X86Blendv),
                 (Opcode::IcmpImm),
                 (Opcode::X86Pmulhrsw),
@@ -935,8 +934,6 @@ static OPCODE_SIGNATURES: Lazy<Vec<OpcodeSignature>> = Lazy::new(|| {
                 (Opcode::IshlImm),
                 (Opcode::UshrImm),
                 (Opcode::SshrImm),
-                (Opcode::IsNull),
-                (Opcode::IsInvalid),
                 (Opcode::ScalarToVector),
                 (Opcode::X86Pmaddubsw),
                 (Opcode::X86Cvtt2dq),
diff --git a/cranelift/interpreter/src/step.rs b/cranelift/interpreter/src/step.rs
index 7497e866a..ed5e61772 100644
--- a/cranelift/interpreter/src/step.rs
+++ b/cranelift/interpreter/src/step.rs
@@ -560,7 +560,6 @@ where
         Opcode::F64const => assign(imm()),
         Opcode::F128const => assign(imm()),
         Opcode::Vconst => assign(imm()),
-        Opcode::Null => unimplemented!("Null"),
         Opcode::Nop => ControlFlow::Continue,
         Opcode::Select | Opcode::SelectSpectreGuard => choose(arg(0).into_bool()?, arg(1), arg(2)),
         Opcode::Bitselect => assign(bitselect(arg(0), arg(1), arg(2))?),
@@ -873,8 +872,6 @@ where
         Opcode::Floor => unary(DataValueExt::floor, arg(0))?,
         Opcode::Trunc => unary(DataValueExt::trunc, arg(0))?,
         Opcode::Nearest => unary(DataValueExt::nearest, arg(0))?,
-        Opcode::IsNull => unimplemented!("IsNull"),
-        Opcode::IsInvalid => unimplemented!("IsInvalid"),
         Opcode::Bitcast | Opcode::ScalarToVector => {
             let input_ty = inst_context.type_of(inst_context.args()[0]).unwrap();
             let lanes = &if input_ty.is_vector() {
diff --git a/cranelift/reader/src/lexer.rs b/cranelift/reader/src/lexer.rs
index afdf3043b..28d75feb5 100644
--- a/cranelift/reader/src/lexer.rs
+++ b/cranelift/reader/src/lexer.rs
@@ -373,8 +373,6 @@ impl<'a> Lexer<'a> {
             "f32" => types::F32,
             "f64" => types::F64,
             "f128" => types::F128,
-            "r32" => types::R32,
-            "r64" => types::R64,
             _ => return None,
         };
         if is_vector {
diff --git a/cranelift/src/bugpoint.rs b/cranelift/src/bugpoint.rs
index 8beafb4d1..bc186d475 100644
--- a/cranelift/src/bugpoint.rs
+++ b/cranelift/src/bugpoint.rs
@@ -770,9 +770,6 @@ fn replace_with_const(pos: &mut FuncCursor, param: Value) -> &'static str {
     } else if ty == F64 {
         pos.ins().with_result(param).f64const(0.0);
         "f64const"
-    } else if ty.is_ref() {
-        pos.ins().with_result(param).null(ty);
-        "null"
     } else if ty.is_vector() {
         let zero_data = vec![0; ty.bytes() as usize].into();
         let zero_handle = pos.func.dfg.constants.insert(zero_data);
diff --git a/cranelift/wasm/src/environ/dummy.rs b/cranelift/wasm/src/environ/dummy.rs
index 4b5bdb8e7..cb4b09bce 100644
--- a/cranelift/wasm/src/environ/dummy.rs
+++ b/cranelift/wasm/src/environ/dummy.rs
@@ -194,11 +194,7 @@ impl<'dummy_environment> DummyFuncEnvironment<'dummy_environment> {
     }
 
     fn reference_type(&self) -> ir::Type {
-        match self.pointer_type() {
-            ir::types::I32 => ir::types::R32,
-            ir::types::I64 => ir::types::R64,
-            _ => panic!("unsupported pointer type"),
-        }
+        self.pointer_type()
     }
 
     fn ensure_table_exists(&mut self, func: &mut ir::Function, index: TableIndex) {
@@ -279,7 +275,7 @@ impl<'dummy_environment> FuncEnvironment for DummyFuncEnvironment<'dummy_environ
                 WasmValType::F32 => ir::types::F32,
                 WasmValType::F64 => ir::types::F64,
                 WasmValType::V128 => ir::types::I8X16,
-                WasmValType::Ref(_) => ir::types::R64,
+                WasmValType::Ref(_) => self.pointer_type(),
             },
         })
     }
@@ -687,18 +683,13 @@ impl<'data> ModuleEnvironment<'data> for DummyEnvironment {
     fn declare_type_func(&mut self, wasm: WasmFuncType) -> WasmResult<()> {
         let mut sig = ir::Signature::new(CallConv::Fast);
         let mut cvt = |ty: &WasmValType| {
-            let reference_type = match self.pointer_type() {
-                ir::types::I32 => ir::types::R32,
-                ir::types::I64 => ir::types::R64,
-                _ => panic!("unsupported pointer type"),
-            };
             ir::AbiParam::new(match ty {
                 WasmValType::I32 => ir::types::I32,
                 WasmValType::I64 => ir::types::I64,
                 WasmValType::F32 => ir::types::F32,
                 WasmValType::F64 => ir::types::F64,
                 WasmValType::V128 => ir::types::I8X16,
-                WasmValType::Ref(_) => reference_type,
+                WasmValType::Ref(_) => self.pointer_type(),
             })
         };
         sig.params.extend(wasm.params().iter().map(&mut cvt));
diff --git a/crates/cranelift/src/compiler.rs b/crates/cranelift/src/compiler.rs
index a49d019b7..a25679b6e 100644
--- a/crates/cranelift/src/compiler.rs
+++ b/crates/cranelift/src/compiler.rs
@@ -702,11 +702,9 @@ impl Compiler {
             .with_endianness(ir::Endianness::Little);
 
         let value_size = mem::size_of::<u128>();
-        for (i, (val, ty)) in values.iter().copied().zip(types).enumerate() {
+        for (i, val) in values.iter().copied().enumerate() {
             crate::unbarriered_store_type_at_offset(
-                &*self.isa,
                 &mut builder.cursor(),
-                *ty,
                 flags,
                 values_vec_ptr,
                 i32::try_from(i * value_size).unwrap(),
diff --git a/crates/cranelift/src/gc/enabled.rs b/crates/cranelift/src/gc/enabled.rs
index 81d0abb67..79d36c30d 100644
--- a/crates/cranelift/src/gc/enabled.rs
+++ b/crates/cranelift/src/gc/enabled.rs
@@ -457,7 +457,7 @@ impl GcCompiler for DrcCompiler {
         // into `dst`, or we are in unreachable code and should just trap.
         if let WasmHeapType::None = ty.heap_type {
             if ty.nullable {
-                let null = builder.ins().null(ref_ty);
+                let null = builder.ins().iconst(ref_ty, 0);
                 builder.ins().store(flags, null, dst, 0);
             } else {
                 // NB: Don't use an unconditional trap instruction, since that
diff --git a/crates/cranelift/src/lib.rs b/crates/cranelift/src/lib.rs
index edc4ab687..1f1a97daa 100644
--- a/crates/cranelift/src/lib.rs
+++ b/crates/cranelift/src/lib.rs
@@ -60,28 +60,13 @@ fn blank_sig(isa: &dyn TargetIsa, call_conv: CallConv) -> ir::Signature {
 /// This is intended to be used with things like `ValRaw` and the array calling
 /// convention.
 fn unbarriered_store_type_at_offset(
-    isa: &dyn TargetIsa,
     pos: &mut FuncCursor,
-    ty: WasmValType,
     flags: ir::MemFlags,
     base: ir::Value,
     offset: i32,
     value: ir::Value,
 ) {
-    let ir_ty = value_type(isa, ty);
-    if ir_ty.is_ref() {
-        let value = pos
-            .ins()
-            .bitcast(ir_ty.as_int(), ir::MemFlags::new(), value);
-        let truncated = match isa.pointer_bytes() {
-            4 => value,
-            8 => pos.ins().ireduce(ir::types::I32, value),
-            _ => unreachable!(),
-        };
-        pos.ins().store(flags, truncated, base, offset);
-    } else {
-        pos.ins().store(flags, value, base, offset);
-    }
+    pos.ins().store(flags, value, base, offset);
 }
 
 /// Emit code to do the following unbarriered memory read of the given type and
@@ -102,17 +87,7 @@ fn unbarriered_load_type_at_offset(
     offset: i32,
 ) -> ir::Value {
     let ir_ty = value_type(isa, ty);
-    if ir_ty.is_ref() {
-        let gc_ref = pos.ins().load(ir::types::I32, flags, base, offset);
-        let extended = match isa.pointer_bytes() {
-            4 => gc_ref,
-            8 => pos.ins().uextend(ir::types::I64, gc_ref),
-            _ => unreachable!(),
-        };
-        pos.ins().bitcast(ir_ty, ir::MemFlags::new(), extended)
-    } else {
-        pos.ins().load(ir_ty, flags, base, offset)
-    }
+    pos.ins().load(ir_ty, flags, base, offset)
 }
 
 /// Returns the corresponding cranelift type for the provided wasm type.


Test patch:
diff --git a/cranelift/filetests/filetests/egraph/bitcast-ref.clif b/cranelift/filetests/filetests/egraph/bitcast-ref.clif
deleted file mode 100644
index e6bb67818..000000000
--- a/cranelift/filetests/filetests/egraph/bitcast-ref.clif
+++ /dev/null
@@ -1,71 +0,0 @@
-test optimize precise-output
-set opt_level=speed
-target x86_64
-
-function %bitcast_from_r64(i64 vmctx, r64) -> i32 fast {
-    sig0 = (i32) fast
-    fn0 = colocated %foo sig0
-
-block0(v0: i64, v1: r64):
-    v2 = bitcast.i64 v1
-    v3 = ireduce.i32 v2
-
-    call fn0(v3)
-
-    ;; We MUST NOT dedupe the bitcast *from* the reference type, as that would
-    ;; make `v1` no longer live across the `call`, which would mean that it
-    ;; would not show up in the `call`'s safepoint's stack map, which could
-    ;; result in the collector reclaiming an object too early, which is basically
-    ;; a use-after-free bug.
-    v4 = bitcast.i64 v1
-    v5 = ireduce.i32 v4
-
-    return v5
-}
-
-; function %bitcast_from_r64(i64 vmctx, r64) -> i32 fast {
-;     sig0 = (i32) fast
-;     fn0 = colocated %foo sig0
-;
-; block0(v0: i64, v1: r64):
-;     v2 = bitcast.i64 v1
-;     v3 = ireduce.i32 v2
-;     call fn0(v3)
-;     v4 = bitcast.i64 v1
-;     v5 = ireduce.i32 v4
-;     return v5
-; }
-
-function %bitcast_to_r64(i64 vmctx, i32) -> r64 fast {
-    sig0 = (r64) fast
-    fn0 = colocated %foo sig0
-
-block0(v0: i64, v1: i32):
-    v2 = uextend.i64 v1
-    v3 = bitcast.r64 v2
-
-    call fn0(v3)
-
-    ;; On the other hand, it is technically fine to dedupe bitcasts *to*
-    ;; reference types. Doing so extends the live range of the GC reference --
-    ;; potentially adding it to more stack maps than it otherwise would have
-    ;; been in, which means it might unnecessarily survive a GC it otherwise
-    ;; wouldn't have -- but that is okay. Shrinking live ranges of GC
-    ;; references, and removing them from stack maps they otherwise would have
-    ;; been in, is the problematic transformation.
-    v4 = uextend.i64 v1
-    v5 = bitcast.r64 v4
-
-    return v5
-}
-
-; function %bitcast_to_r64(i64 vmctx, i32) -> r64 fast {
-;     sig0 = (r64) fast
-;     fn0 = colocated %foo sig0
-;
-; block0(v0: i64, v1: i32):
-;     v2 = uextend.i64 v1
-;     v3 = bitcast.r64 v2
-;     call fn0(v3)
-;     return v3
-; }
diff --git a/cranelift/filetests/filetests/isa/aarch64/call.clif b/cranelift/filetests/filetests/isa/aarch64/call.clif
index 3868d8be0..102dc4f4e 100644
--- a/cranelift/filetests/filetests/isa/aarch64/call.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/call.clif
@@ -704,8 +704,6 @@ block0(v0: i128, v1: i64):
 ;   str x1, [sp, #8]
 ;   mov x5, x1
 ;   load_ext_name x8, TestCase(%f14)+0
-;   mov x0, x4
-;   mov x1, x5
 ;   mov x2, x4
 ;   mov x3, x5
 ;   blr x8
@@ -728,8 +726,6 @@ block0(v0: i128, v1: i64):
 ;   b #0x30
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f14 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   mov x0, x4
-;   mov x1, x5
 ;   mov x2, x4
 ;   mov x3, x5
 ;   blr x8
@@ -780,8 +776,6 @@ block0(v0: i128, v1: i64):
 ;   str x1, [sp, #8]
 ;   mov x5, x1
 ;   load_ext_name x8, TestCase(%f15)+0
-;   mov x0, x4
-;   mov x1, x5
 ;   mov x2, x4
 ;   mov x3, x5
 ;   blr x8
@@ -804,8 +798,6 @@ block0(v0: i128, v1: i64):
 ;   b #0x30
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f15 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   mov x0, x4
-;   mov x1, x5
 ;   mov x2, x4
 ;   mov x3, x5
 ;   blr x8
@@ -879,7 +871,6 @@ block0(v0: i64):
 ; block0:
 ;   mov x23, x8
 ;   load_ext_name x2, TestCase(%g)+0
-;   mov x8, x23
 ;   blr x2
 ;   mov x8, x23
 ;   ldr x23, [sp], #16
@@ -897,7 +888,6 @@ block0(v0: i64):
 ;   b #0x20
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   mov x8, x23
 ;   blr x2
 ;   mov x8, x23
 ;   ldr x23, [sp], #0x10
diff --git a/cranelift/filetests/filetests/isa/aarch64/reftypes.clif b/cranelift/filetests/filetests/isa/aarch64/reftypes.clif
deleted file mode 100644
index f35508a3d..000000000
--- a/cranelift/filetests/filetests/isa/aarch64/reftypes.clif
+++ /dev/null
@@ -1,160 +0,0 @@
-test compile precise-output
-set unwind_info=false
-target aarch64
-
-function %f0(r64) -> r64 {
-block0(v0: r64):
-  return v0
-}
-
-; VCode:
-; block0:
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   ret
-
-function %f1(r64) -> i8 {
-block0(v0: r64):
-  v1 = is_null v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   subs xzr, x0, #0
-;   cset x0, eq
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   cmp x0, #0
-;   cset x0, eq
-;   ret
-
-function %f2(r64) -> i8 {
-block0(v0: r64):
-  v1 = is_invalid v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   adds xzr, x0, #1
-;   cset x0, eq
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   cmn x0, #1
-;   cset x0, eq
-;   ret
-
-function %f3() -> r64 {
-block0:
-  v0 = null.r64
-  return v0
-}
-
-; VCode:
-; block0:
-;   movz x0, #0
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   mov x0, #0
-;   ret
-
-function %f4(r64, r64) -> r64, r64, r64 {
-    fn0 = %f(r64) -> i8
-    ss0 = explicit_slot 8
-
-block0(v0: r64, v1: r64):
-    v2 = call fn0(v0)
-    stack_store.r64 v0, ss0
-    brif v2, block2(v0, v1), block1(v1, v0)
-
-block1(v3: r64, v4: r64):
-    jump block3(v3, v4)
-
-block2(v5: r64, v6: r64):
-    jump block3(v5, v6)
-
-block3(v7: r64, v8: r64):
-    v9 = stack_load.r64 ss0
-    return v7, v8, v9
-}
-
-; VCode:
-;   stp fp, lr, [sp, #-16]!
-;   mov fp, sp
-;   str x24, [sp, #-16]!
-;   sub sp, sp, #32
-; block0:
-;   mov x5, x0
-;   str x1, [sp, #16]
-;   mov x0, x5
-;   mov x24, x5
-;   load_ext_name x12, TestCase(%f)+0
-;   str x24, [sp, #8]
-;   blr x12
-;   mov x11, sp
-;   mov x5, x24
-;   str x5, [x11]
-;   uxtb w12, w0
-;   cbnz x12, label2 ; b label1
-; block1:
-;   ldr x0, [sp, #16]
-;   mov x1, x24
-;   b label3
-; block2:
-;   mov x0, x24
-;   ldr x1, [sp, #16]
-;   b label3
-; block3:
-;   mov x15, sp
-;   ldr x2, [x15]
-;   add sp, sp, #32
-;   ldr x24, [sp], #16
-;   ldp fp, lr, [sp], #16
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   stp x29, x30, [sp, #-0x10]!
-;   mov x29, sp
-;   str x24, [sp, #-0x10]!
-;   sub sp, sp, #0x20
-; block1: ; offset 0x10
-;   mov x5, x0
-;   stur x1, [sp, #0x10]
-;   mov x0, x5
-;   mov x24, x5
-;   ldr x12, #0x28
-;   b #0x30
-;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f 0
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   stur x24, [sp, #8]
-;   blr x12
-;   mov x11, sp
-;   mov x5, x24
-;   str x5, [x11]
-;   uxtb w12, w0
-;   cbnz x12, #0x58
-; block2: ; offset 0x4c
-;   ldur x0, [sp, #0x10]
-;   mov x1, x24
-;   b #0x60
-; block3: ; offset 0x58
-;   mov x0, x24
-;   ldur x1, [sp, #0x10]
-; block4: ; offset 0x60
-;   mov x15, sp
-;   ldr x2, [x15]
-;   add sp, sp, #0x20
-;   ldr x24, [sp], #0x10
-;   ldp x29, x30, [sp], #0x10
-;   ret
-
diff --git a/cranelift/filetests/filetests/isa/aarch64/user_stack_maps.clif b/cranelift/filetests/filetests/isa/aarch64/user_stack_maps.clif
index 1d4efdf44..e51a2e507 100644
--- a/cranelift/filetests/filetests/isa/aarch64/user_stack_maps.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/user_stack_maps.clif
@@ -59,7 +59,6 @@ block0:
 ;   add x13, sp, #4
 ;   mov x0, x22
 ;   str w0, [x13]
-;   mov x22, x0
 ;   mov x0, x24
 ;   bl 0
 ;   ; UserStackMap { by_type: [(types::I32, CompoundBitSet {0, 4})], sp_to_sized_stack_slots: None }
@@ -105,16 +104,15 @@ block0:
 ;   add x13, sp, #4
 ;   mov x0, x22
 ;   str w0, [x13]
-;   mov x22, x0
 ;   mov x0, x24
-;   bl #0x6c ; reloc_external Call u0:0 0
+;   bl #0x68 ; reloc_external Call u0:0 0
 ;   mov x15, sp
 ;   mov x0, x22
 ;   str w0, [x15]
 ;   mov x0, x19
-;   bl #0x80 ; reloc_external Call u0:0 0
+;   bl #0x7c ; reloc_external Call u0:0 0
 ;   mov x0, x22
-;   bl #0x88 ; reloc_external Call u0:0 0
+;   bl #0x84 ; reloc_external Call u0:0 0
 ;   add sp, sp, #0x10
 ;   ldp x19, x22, [sp], #0x10
 ;   ldr x24, [sp], #0x10
diff --git a/cranelift/filetests/filetests/isa/issue-8180.clif b/cranelift/filetests/filetests/isa/issue-8180.clif
deleted file mode 100644
index 7ff22173d..000000000
--- a/cranelift/filetests/filetests/isa/issue-8180.clif
+++ /dev/null
@@ -1,30 +0,0 @@
-;; https://github.com/bytecodealliance/wasmtime/issues/8180
-;;
-;; Make sure that bitcasting between integer and reference types doesn't result
-;; in conflicting regalloc constraints where a register has to be both in a
-;; register for a call and a stack slot for a safepoint.
-;;
-;; We aren't testing for any particular resuyting code sequence, just that
-;; compilation succeeds.
-
-test compile
-target x86_64
-target aarch64
-target riscv64
-target s390x
-
-function %a(i64, r64) fast {
-    sig0 = (i64) system_v
-block1(v0: i64, v1: r64):
-    v2 = bitcast.i64 v1
-    call_indirect sig0, v0(v2)
-    return
-}
-
-function %b(i64, i64) fast {
-    sig0 = (r64) system_v
-block1(v0: i64, v1: i64):
-    v2 = bitcast.r64 v1
-    call_indirect sig0, v0(v2)
-    return
-}
diff --git a/cranelift/filetests/filetests/isa/riscv64/call.clif b/cranelift/filetests/filetests/isa/riscv64/call.clif
index 3e7762a92..534cc5398 100644
--- a/cranelift/filetests/filetests/isa/riscv64/call.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/call.clif
@@ -632,8 +632,6 @@ block0(v0: i128, v1: i64):
 ;   sd a1,0(sp)
 ;   mv a5,a1
 ;   load_sym s1,%f14+0
-;   mv a0,a7
-;   mv a1,a5
 ;   mv a2,a7
 ;   mv a3,a5
 ;   mv a4,a7
@@ -663,8 +661,6 @@ block0(v0: i128, v1: i64):
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f14 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   mv a0, a7
-;   mv a1, a5
 ;   mv a2, a7
 ;   mv a3, a5
 ;   mv a4, a7
@@ -729,8 +725,6 @@ block0(v0: i128, v1: i64):
 ;   sd a1,0(sp)
 ;   mv a5,a1
 ;   load_sym s1,%f15+0
-;   mv a0,a7
-;   mv a1,a5
 ;   mv a2,a7
 ;   mv a3,a5
 ;   mv a4,a7
@@ -760,8 +754,6 @@ block0(v0: i128, v1: i64):
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f15 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   mv a0, a7
-;   mv a1, a5
 ;   mv a2, a7
 ;   mv a3, a5
 ;   mv a4, a7
diff --git a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif b/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
deleted file mode 100644
index 86ca5d605..000000000
--- a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
+++ /dev/null
@@ -1,173 +0,0 @@
-test compile precise-output
-set unwind_info=false
-target riscv64
-
-function %f0(r64) -> r64 {
-block0(v0: r64):
-  return v0
-}
-
-; VCode:
-; block0:
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   ret
-
-function %f1(r64) -> i8 {
-block0(v0: r64):
-  v1 = is_null v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   seqz a0,a0
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   seqz a0, a0
-;   ret
-
-function %f2(r64) -> i8 {
-block0(v0: r64):
-  v1 = is_invalid v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   addi a2,a0,1
-;   seqz a0,a2
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   addi a2, a0, 1
-;   seqz a0, a2
-;   ret
-
-function %f3() -> r64 {
-block0:
-  v0 = null.r64
-  return v0
-}
-
-; VCode:
-; block0:
-;   li a0,0
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   mv a0, zero
-;   ret
-
-function %f4(r64, r64) -> r64, r64, r64 {
-    fn0 = %f(r64) -> i8
-    ss0 = explicit_slot 8
-
-block0(v0: r64, v1: r64):
-    v2 = call fn0(v0)
-    stack_store.r64 v0, ss0
-    brif v2, block2(v0, v1), block1(v1, v0)
-
-block1(v3: r64, v4: r64):
-    jump block3(v3, v4)
-
-block2(v5: r64, v6: r64):
-    jump block3(v5, v6)
-
-block3(v7: r64, v8: r64):
-    v9 = stack_load.r64 ss0
-    return v7, v8, v9
-}
-
-; VCode:
-;   addi sp,sp,-16
-;   sd ra,8(sp)
-;   sd fp,0(sp)
-;   mv fp,sp
-;   addi sp,sp,-48
-;   sd s5,40(sp)
-;   sd s9,32(sp)
-; block0:
-;   mv a3,a0
-;   mv s5,a2
-;   sd a1,16(slot)
-;   mv a0,a3
-;   mv s9,a3
-;   load_sym a5,%f+0
-;   sd s9,8(slot)
-;   callind a5
-;   mv a3,s9
-;   sd a3,0(slot)
-;   andi a5,a0,255
-;   bne a5,zero,taken(label2),not_taken(label1)
-; block1:
-;   ld a0,16(slot)
-;   mv a1,s9
-;   j label3
-; block2:
-;   mv a0,s9
-;   ld a1,16(slot)
-;   j label3
-; block3:
-;   ld a2,0(slot)
-;   mv a3,s5
-;   sd a2,0(a3)
-;   ld s5,40(sp)
-;   ld s9,32(sp)
-;   addi sp,sp,48
-;   ld ra,8(sp)
-;   ld fp,0(sp)
-;   addi sp,sp,16
-;   ret
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   addi sp, sp, -0x10
-;   sd ra, 8(sp)
-;   sd s0, 0(sp)
-;   mv s0, sp
-;   addi sp, sp, -0x30
-;   sd s5, 0x28(sp)
-;   sd s9, 0x20(sp)
-; block1: ; offset 0x1c
-;   mv a3, a0
-;   mv s5, a2
-;   sd a1, 0x10(sp)
-;   mv a0, a3
-;   mv s9, a3
-;   auipc a5, 0
-;   ld a5, 0xc(a5)
-;   j 0xc
-;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f 0
-;   .byte 0x00, 0x00, 0x00, 0x00
-;   sd s9, 8(sp)
-;   jalr a5
-;   mv a3, s9
-;   sd a3, 0(sp)
-;   andi a5, a0, 0xff
-;   bnez a5, 0x10
-; block2: ; offset 0x5c
-;   ld a0, 0x10(sp)
-;   mv a1, s9
-;   j 0xc
-; block3: ; offset 0x68
-;   mv a0, s9
-;   ld a1, 0x10(sp)
-; block4: ; offset 0x70
-;   ld a2, 0(sp)
-;   mv a3, s5
-;   sd a2, 0(a3)
-;   ld s5, 0x28(sp)
-;   ld s9, 0x20(sp)
-;   addi sp, sp, 0x30
-;   ld ra, 8(sp)
-;   ld s0, 0(sp)
-;   addi sp, sp, 0x10
-;   ret
-
diff --git a/cranelift/filetests/filetests/isa/riscv64/user_stack_maps.clif b/cranelift/filetests/filetests/isa/riscv64/user_stack_maps.clif
index 5b46be979..341f7bd4f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/user_stack_maps.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/user_stack_maps.clif
@@ -57,7 +57,6 @@ block0:
 ;   sw a0,0(slot)
 ;   mv a0,s2
 ;   sw a0,4(slot)
-;   mv s2,a0
 ;   mv a0,s3
 ;   call userextname0
 ;   ; UserStackMap { by_type: [(types::I32, CompoundBitSet {0, 4})], sp_to_sized_stack_slots: None }
@@ -104,7 +103,6 @@ block0:
 ;   sw a0, 0(sp)
 ;   mv a0, s2
 ;   sw a0, 4(sp)
-;   mv s2, a0
 ;   mv a0, s3
 ;   auipc ra, 0 ; reloc_external RiscvCallPlt u0:0 0
 ;   jalr ra
diff --git a/cranelift/filetests/filetests/isa/s390x/bitcast.clif b/cranelift/filetests/filetests/isa/s390x/bitcast.clif
index 879c74d54..0232401df 100644
--- a/cranelift/filetests/filetests/isa/s390x/bitcast.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bitcast.clif
@@ -76,50 +76,3 @@ block0(v0: i128):
 ;   vl %v1, 0(%r3)
 ;   vst %v1, 0(%r2)
 ;   br %r14
-
-function %bitcast_r64_i64(r64) -> i64 {
-block0(v0: r64):
-  v1 = bitcast.i64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   lgr %r2, %r2
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r2, %r2
-;   br %r14
-
-function %bitcast_i64_r64(i64) -> r64 {
-block0(v0: i64):
-  v1 = bitcast.r64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   lgr %r2, %r2
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r2, %r2
-;   br %r14
-
-function %bitcast_r64_r64(r64) -> r64 {
-block0(v0: r64):
-  v1 = bitcast.r64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   br %r14
-
diff --git a/cranelift/filetests/filetests/isa/s390x/call-tail.clif b/cranelift/filetests/filetests/isa/s390x/call-tail.clif
index 8fc6665ce..e2e930382 100644
--- a/cranelift/filetests/filetests/isa/s390x/call-tail.clif
+++ b/cranelift/filetests/filetests/isa/s390x/call-tail.clif
@@ -194,7 +194,6 @@ block0(v0: i64):
 ;   stg %r2, 160(%r15)
 ;   stg %r2, 168(%r15)
 ;   lgr %r7, %r2
-;   lgr %r2, %r7
 ;   lgr %r3, %r7
 ;   lgr %r4, %r7
 ;   lgr %r5, %r7
@@ -212,12 +211,11 @@ block0(v0: i64):
 ;   stg %r2, 0xa0(%r15)
 ;   stg %r2, 0xa8(%r15)
 ;   lgr %r7, %r2
-;   lgr %r2, %r7
 ;   lgr %r3, %r7
 ;   lgr %r4, %r7
 ;   lgr %r5, %r7
 ;   lgr %r6, %r7
-;   brasl %r14, 0x32 ; reloc_external PLTRel32Dbl %g 2
+;   brasl %r14, 0x2e ; reloc_external PLTRel32Dbl %g 2
 ;   lmg %r14, %r15, 0x110(%r15)
 ;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/reftypes.clif b/cranelift/filetests/filetests/isa/s390x/reftypes.clif
deleted file mode 100644
index 69d73b3e6..000000000
--- a/cranelift/filetests/filetests/isa/s390x/reftypes.clif
+++ /dev/null
@@ -1,161 +0,0 @@
-test compile precise-output
-target s390x
-
-function %f0(r64, r64) -> r64 {
-block0(v0: r64, v1: r64):
-  return v1
-}
-
-; VCode:
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r2, %r3
-;   br %r14
-
-function %f1(r64) -> i8 {
-block0(v0: r64):
-  v1 = is_null v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   cghi %r2, 0
-;   lhi %r2, 0
-;   lochie %r2, 1
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   cghi %r2, 0
-;   lhi %r2, 0
-;   lochie %r2, 1
-;   br %r14
-
-function %f2(r64) -> i8 {
-block0(v0: r64):
-  v1 = is_invalid v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   cghi %r2, -1
-;   lhi %r2, 0
-;   lochie %r2, 1
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   cghi %r2, -1
-;   lhi %r2, 0
-;   lochie %r2, 1
-;   br %r14
-
-function %f3() -> r64 {
-block0:
-  v0 = null.r64
-  return v0
-}
-
-; VCode:
-; block0:
-;   lghi %r2, 0
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   lghi %r2, 0
-;   br %r14
-
-function %f4(r64, r64) -> r64, r64, r64 {
-    fn0 = %f(r64) -> i8
-    ss0 = explicit_slot 8
-
-block0(v0: r64, v1: r64):
-    v2 = call fn0(v0)
-    stack_store.r64 v0, ss0
-    brif v2, block2(v0, v1), block1(v1, v0)
-
-block1(v3: r64, v4: r64):
-    jump block3(v3, v4)
-
-block2(v5: r64, v6: r64):
-    jump block3(v5, v6)
-
-block3(v7: r64, v8: r64):
-    v9 = stack_load.r64 ss0
-    return v7, v8, v9
-}
-
-; VCode:
-;   stmg %r11, %r15, 88(%r15)
-;   aghi %r15, -184
-; block0:
-;   stg %r3, 176(%r15)
-;   lgr %r3, %r2
-;   lgr %r2, %r3
-;   lgr %r11, %r3
-;   bras %r1, 12 ; data %f + 0 ; lg %r3, 0(%r1)
-;   stg %r11, 168(%r15)
-;   basr %r14, %r3
-;   la %r5, 160(%r15)
-;   lgr %r3, %r11
-;   stg %r3, 0(%r5)
-;   lbr %r2, %r2
-;   chi %r2, 0
-;   jglh label2 ; jg label1
-; block1:
-;   lg %r2, 176(%r15)
-;   lgr %r3, %r11
-;   jg label3
-; block2:
-;   lgr %r2, %r11
-;   lg %r3, 176(%r15)
-;   jg label3
-; block3:
-;   la %r4, 160(%r15)
-;   lg %r4, 0(%r4)
-;   lmg %r11, %r15, 272(%r15)
-;   br %r14
-;
-; Disassembled:
-; block0: ; offset 0x0
-;   stmg %r11, %r15, 0x58(%r15)
-;   aghi %r15, -0xb8
-; block1: ; offset 0xa
-;   stg %r3, 0xb0(%r15)
-;   lgr %r3, %r2
-;   lgr %r2, %r3
-;   lgr %r11, %r3
-;   bras %r1, 0x28
-;   .byte 0x00, 0x00 ; reloc_external Abs8 %f 0
-;   .byte 0x00, 0x00
-;   .byte 0x00, 0x00
-;   .byte 0x00, 0x00
-;   lg %r3, 0(%r1)
-;   stg %r11, 0xa8(%r15)
-;   basr %r14, %r3
-;   la %r5, 0xa0(%r15)
-;   lgr %r3, %r11
-;   stg %r3, 0(%r5)
-;   lbr %r2, %r2
-;   chi %r2, 0
-;   jglh 0x62
-; block2: ; offset 0x52
-;   lg %r2, 0xb0(%r15)
-;   lgr %r3, %r11
-;   jg 0x6c
-; block3: ; offset 0x62
-;   lgr %r2, %r11
-;   lg %r3, 0xb0(%r15)
-; block4: ; offset 0x6c
-;   la %r4, 0xa0(%r15)
-;   lg %r4, 0(%r4)
-;   lmg %r11, %r15, 0x110(%r15)
-;   br %r14
-
diff --git a/cranelift/filetests/filetests/isa/x64/fastcall.clif b/cranelift/filetests/filetests/isa/x64/fastcall.clif
index 41dd23724..44b42f962 100644
--- a/cranelift/filetests/filetests/isa/x64/fastcall.clif
+++ b/cranelift/filetests/filetests/isa/x64/fastcall.clif
@@ -247,7 +247,6 @@ block0(v0: i64):
 ;   movq    %rcx, 40(%rsp)
 ;   movq    %rcx, %rdx
 ;   load_ext_name %g+0, %r11
-;   movq    %rdx, %rcx
 ;   movdqa  %xmm3, %xmm2
 ;   call    *%r11
 ;   addq    %rsp, $48, %rsp
@@ -267,7 +266,6 @@ block0(v0: i64):
 ;   movq %rcx, 0x28(%rsp)
 ;   movq %rcx, %rdx
 ;   movabsq $0, %r11 ; reloc_external Abs8 %g 0
-;   movq %rdx, %rcx
 ;   movdqa %xmm3, %xmm2
 ;   callq *%r11
 ;   addq $0x30, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/fma-call.clif b/cranelift/filetests/filetests/isa/x64/fma-call.clif
index 79175599d..8b19a8e94 100644
--- a/cranelift/filetests/filetests/isa/x64/fma-call.clif
+++ b/cranelift/filetests/filetests/isa/x64/fma-call.clif
@@ -70,9 +70,6 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4):
 ;   movdqu  %xmm1, rsp(16 + virtual offset)
 ;   movdqu  %xmm2, rsp(32 + virtual offset)
 ;   load_ext_name %FmaF32+0, %r8
-;   movdqu  rsp(0 + virtual offset), %xmm0
-;   movdqu  rsp(16 + virtual offset), %xmm1
-;   movdqu  rsp(32 + virtual offset), %xmm2
 ;   call    *%r8
 ;   movdqu  rsp(0 + virtual offset), %xmm4
 ;   movdqu  %xmm0, rsp(80 + virtual offset)
@@ -124,9 +121,6 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4):
 ;   movdqu %xmm1, 0x10(%rsp)
 ;   movdqu %xmm2, 0x20(%rsp)
 ;   movabsq $0, %r8 ; reloc_external Abs8 %FmaF32 0
-;   movdqu (%rsp), %xmm0
-;   movdqu 0x10(%rsp), %xmm1
-;   movdqu 0x20(%rsp), %xmm2
 ;   callq *%r8
 ;   movdqu (%rsp), %xmm4
 ;   movdqu %xmm0, 0x50(%rsp)
@@ -183,9 +177,6 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2):
 ;   movdqu  %xmm1, rsp(16 + virtual offset)
 ;   movdqu  %xmm2, rsp(32 + virtual offset)
 ;   load_ext_name %FmaF64+0, %r8
-;   movdqu  rsp(0 + virtual offset), %xmm0
-;   movdqu  rsp(16 + virtual offset), %xmm1
-;   movdqu  rsp(32 + virtual offset), %xmm2
 ;   call    *%r8
 ;   movdqu  %xmm0, rsp(48 + virtual offset)
 ;   movdqu  rsp(0 + virtual offset), %xmm0
@@ -214,9 +205,6 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2):
 ;   movdqu %xmm1, 0x10(%rsp)
 ;   movdqu %xmm2, 0x20(%rsp)
 ;   movabsq $0, %r8 ; reloc_external Abs8 %FmaF64 0
-;   movdqu (%rsp), %xmm0
-;   movdqu 0x10(%rsp), %xmm1
-;   movdqu 0x20(%rsp), %xmm2
 ;   callq *%r8
 ;   movdqu %xmm0, 0x30(%rsp)
 ;   movdqu (%rsp), %xmm0
diff --git a/cranelift/filetests/filetests/isa/x64/struct-ret.clif b/cranelift/filetests/filetests/isa/x64/struct-ret.clif
index fd735ee28..1947901dd 100644
--- a/cranelift/filetests/filetests/isa/x64/struct-ret.clif
+++ b/cranelift/filetests/filetests/isa/x64/struct-ret.clif
@@ -78,7 +78,6 @@ block0(v0: i64):
 ; block0:
 ;   movq    %rdi, %r15
 ;   load_ext_name %f4+0, %rax
-;   movq    %r15, %rdi
 ;   call    *%rax
 ;   movq    %r15, %rax
 ;   movq    0(%rsp), %r15
@@ -96,7 +95,6 @@ block0(v0: i64):
 ; block1: ; offset 0xc
 ;   movq %rdi, %r15
 ;   movabsq $0, %rax ; reloc_external Abs8 %f4 0
-;   movq %r15, %rdi
 ;   callq *%rax
 ;   movq %r15, %rax
 ;   movq (%rsp), %r15
diff --git a/cranelift/filetests/filetests/isa/x64/winch.clif b/cranelift/filetests/filetests/isa/x64/winch.clif
index d730bf261..9a9fce756 100644
--- a/cranelift/filetests/filetests/isa/x64/winch.clif
+++ b/cranelift/filetests/filetests/isa/x64/winch.clif
@@ -238,7 +238,6 @@ block0:
 ; block0:
 ;   load_ext_name userextname0+0, %r10
 ;   movq    %r10, rsp(0 + virtual offset)
-;   movq    rsp(0 + virtual offset), %r10
 ;   call    *%r10
 ;   movq    rsp(0 + virtual offset), %r10
 ;   call    *%r10
@@ -265,7 +264,6 @@ block0:
 ; block1: ; offset 0x21
 ;   movabsq $0, %r10 ; reloc_external Abs8 u2:0 0
 ;   movq %r10, (%rsp)
-;   movq (%rsp), %r10
 ;   callq *%r10
 ;   movq (%rsp), %r10
 ;   callq *%r10
diff --git a/cranelift/filetests/filetests/pcc/succeed/fuzz-float-loads.clif b/cranelift/filetests/filetests/pcc/succeed/fuzz-float-loads.clif
index af5aa34c8..a69bf96bc 100644
--- a/cranelift/filetests/filetests/pcc/succeed/fuzz-float-loads.clif
+++ b/cranelift/filetests/filetests/pcc/succeed/fuzz-float-loads.clif
@@ -22,7 +22,7 @@ block0(v0: i64, v1: i64):
     v25 -> v2
     v45 -> v2
     v24 -> v25
-    v3 = null.r64
+    v3 = iconst.i64 0
     v4 = global_value.i64 gv3
     v5 = load.i64 notrap aligned v4+8
     v17 -> v5
@@ -83,4 +83,3 @@ block7(v40: i64):
     store notrap aligned v41, v17+8
     trap unreachable
 }
-
diff --git a/cranelift/filetests/filetests/runtests/bitcast-ref64.clif b/cranelift/filetests/filetests/runtests/bitcast-ref64.clif
deleted file mode 100644
index 698cea8e1..000000000
--- a/cranelift/filetests/filetests/runtests/bitcast-ref64.clif
+++ /dev/null
@@ -1,29 +0,0 @@
-test run
-target aarch64
-target x86_64
-target s390x
-target riscv64gc
-target riscv64 has_c has_zcb
-; the interpreter does not support bitcasting to/from references
-
-function %bitcast_ir64(i64) -> i8 {
-block0(v0: i64):
-  v1 = bitcast.r64 v0
-  v2 = is_null v1
-  return v2
-}
-; run: %bitcast_ir64(0) == 1
-; run: %bitcast_ir64(18446744073709551615) == 0
-; run: %bitcast_ir64(-1) == 0
-; run: %bitcast_ir64(127) == 0
-
-function %bitcast_ri64(i64) -> i64 {
-block0(v0: i64):
-  v1 = bitcast.r64 v0
-  v2 = bitcast.i64 v1
-  return v2
-}
-; run: %bitcast_ri64(0) == 0
-; run: %bitcast_ri64(18446744073709551615) == 18446744073709551615
-; run: %bitcast_ri64(-1) == -1
-; run: %bitcast_ri64(127) == 127
diff --git a/cranelift/filetests/filetests/runtests/ref64-invalid-null.clif b/cranelift/filetests/filetests/runtests/ref64-invalid-null.clif
deleted file mode 100644
index b0bca96b7..000000000
--- a/cranelift/filetests/filetests/runtests/ref64-invalid-null.clif
+++ /dev/null
@@ -1,44 +0,0 @@
-; Tests for platforms with 64-bit references.
-test run
-target aarch64
-target x86_64
-target s390x
-target riscv64
-target riscv64 has_c has_zcb
-
-function %is_null_true_r64() -> i8 {
-block0:
-  v0 = null.r64
-  v1 = is_null v0
-  return v1
-}
-; run: %is_null_true_r64() == 1
-
-function %is_null_r64(i64) -> i8 {
-block0(v0: i64):
-  v1 = bitcast.r64 v0
-  v2 = is_null v1
-  return v2
-}
-; run: %is_null_r64(256347) == 0
-; run: %is_null_r64(-1) == 0
-; run: %is_null_r64(0) == 1
-
-function %is_invalid_r64(i64) -> i8 {
-block0(v0: i64):
-  v1 = bitcast.r64 v0
-  v2 = is_invalid v1
-  return v2
-}
-; run: %is_invalid_r64(0xffffffffffffffff) == 1
-; run: %is_invalid_r64(-1) == 1
-; run: %is_invalid_r64(256347) == 0
-; run: %is_invalid_r64(0) == 0
-
-function %is_invalid_null_r64() -> i8 {
-block0:
-  v0 = null.r64
-  v1 = is_invalid v0
-  return v1
-}
-; run: %is_invalid_null_r64() == 0
diff --git a/cranelift/filetests/filetests/wasm/r32.clif b/cranelift/filetests/filetests/wasm/r32.clif
deleted file mode 100644
index f9525a818..000000000
--- a/cranelift/filetests/filetests/wasm/r32.clif
+++ /dev/null
@@ -1,51 +0,0 @@
-; Test basic code generation for 32-bit reftypes
-; This test is the 32-bit version of r64.clif. If you change this test you
-; should most likely update that test as well.
-test compile
-set enable_safepoints=true
-
-target aarch64
-target i686 haswell
-
-function %select_ref(i32, r32, r32) -> r32 {
-block0(v0: i32, v1: r32, v2: r32):
-    brif v0, block1(v1), block1(v2)
-
-block1(v3: r32):
-    return v3
-}
-
-function %test_refs(r32, r32, r32, i32 vmctx) {
-    fn0 = %select_ref(i32, r32, r32) -> r32
-    fn1 = %table_set(i32, r32, i32 vmctx)
-    fn2 = %table_get(i32, i32 vmctx) -> r32
-
-block0(v0: r32, v1: r32, v2: r32, v3: i32):
-    v4 = iconst.i32 0
-    v5 = iconst.i32 1
-    v8 = iconst.i32 2
-
-    ; Shuffle around the first two refs
-    v6 = call fn0(v4, v0, v1)
-    v7 = call fn0(v5, v0, v1)
-
-    ; Store in the table
-    call fn1(v4, v6, v3)
-    call fn1(v5, v7, v3)
-    call fn1(v8, v2, v3)
-
-    ; Load from the table
-    v9 = call fn2(v4, v3)
-    v10 = call fn2(v5, v3)
-    v11 = call fn2(v8, v3)
-
-    ; Compare the results
-    v12 = is_null v9
-    trapnz v12, user0
-    v13 = is_null v10
-    trapnz v13, user0
-    v14 = is_invalid v11
-    trapnz v14, user0
-
-    return
-}
diff --git a/cranelift/filetests/filetests/wasm/r64.clif b/cranelift/filetests/filetests/wasm/r64.clif
deleted file mode 100644
index f448f9db0..000000000
--- a/cranelift/filetests/filetests/wasm/r64.clif
+++ /dev/null
@@ -1,51 +0,0 @@
-; Test basic code generation for 64-bit reftypes
-; This test is the 64-bit version of r32.clif. If you change this test you
-; should most likely update that test as well.
-test compile
-set enable_safepoints=true
-
-target aarch64
-target x86_64 haswell
-
-function %select_ref(i32, r64, r64) -> r64 {
-block0(v0: i32, v1: r64, v2: r64):
-    brif v0, block1(v1), block1(v2)
-
-block1(v3: r64):
-    return v3
-}
-
-function %test_refs(r64, r64, r64, i64 vmctx) {
-    fn0 = %select_ref(i32, r64, r64) -> r64
-    fn1 = %table_set(i32, r64, i64 vmctx)
-    fn2 = %table_get(i32, i64 vmctx) -> r64
-
-block0(v0: r64, v1: r64, v2: r64, v3: i64):
-    v4 = iconst.i32 0
-    v5 = iconst.i32 1
-    v8 = iconst.i32 2
-
-    ; Shuffle around the first two refs
-    v6 = call fn0(v4, v0, v1)
-    v7 = call fn0(v5, v0, v1)
-
-    ; Store in the table
-    call fn1(v4, v6, v3)
-    call fn1(v5, v7, v3)
-    call fn1(v8, v2, v3)
-
-    ; Load from the table
-    v9 = call fn2(v4, v3)
-    v10 = call fn2(v5, v3)
-    v11 = call fn2(v8, v3)
-
-    ; Compare the results
-    v12 = is_null v9
-    trapnz v12, user0
-    v13 = is_null v10
-    trapnz v13, user0
-    v14 = is_invalid v11
-    trapnz v14, user0
-
-    return
-}
diff --git a/cranelift/tests/bugpoint_consts.clif b/cranelift/tests/bugpoint_consts.clif
index 449b53ebb..2234123e4 100644
--- a/cranelift/tests/bugpoint_consts.clif
+++ b/cranelift/tests/bugpoint_consts.clif
@@ -2,13 +2,13 @@ test compile
 target x86_64
 
 function u0:0() {
-    sig0 = (f32, f64, i8, i16, i32, i64, i128, i8, i8, i128, r32, r64, i8x16, i16x4, f32x16)
+    sig0 = (f32, f64, i8, i16, i32, i64, i128, i8, i8, i128, i8x16, i16x4, f32x16)
     fn0 = u0:1 sig0
 
 block0:
     trap user0
 
-block1(v0: f32, v1: f64, v2: i8, v3: i16, v4: i32, v5: i64, v6: i128, v7: i8, v8: i8, v9: i128, v10: r32, v11: r64, v12: i8x16, v13: i16x4, v14: f32x16):
-    call fn0(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14)
+block1(v0: f32, v1: f64, v2: i8, v3: i16, v4: i32, v5: i64, v6: i128, v7: i8, v8: i8, v9: i128, v12: i8x16, v13: i16x4, v14: f32x16):
+    call fn0(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v12, v13, v14)
     trap user0
 }
diff --git a/cranelift/tests/bugpoint_consts_expected.clif b/cranelift/tests/bugpoint_consts_expected.clif
index c344f484f..bf95789f1 100644
--- a/cranelift/tests/bugpoint_consts_expected.clif
+++ b/cranelift/tests/bugpoint_consts_expected.clif
@@ -1,5 +1,5 @@
 function u0:0() fast {
-    sig0 = (f32, f64, i8, i16, i32, i64, i128, i8, i8, i128, r32, r64, i8x16, i16x4, f32x16) fast
+    sig0 = (f32, f64, i8, i16, i32, i64, i128, i8, i8, i128, i8x16, i16x4, f32x16) fast
     fn0 = u0:1 sig0
     const0 = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
     const1 = 0x0000000000000000
@@ -18,11 +18,9 @@ block1:
     v8 = iconst.i8 0
     v15 = iconst.i64 0
     v9 = uextend.i128 v15  ; v15 = 0
-    v10 = null.r32 
-    v11 = null.r64 
     v12 = vconst.i8x16 const2
     v13 = vconst.i16x4 const1
     v14 = vconst.f32x16 const0
-    call fn0(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14)  ; v0 = 0.0, v1 = 0.0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v7 = 0, v8 = 0, v12 = const2, v13 = const1, v14 = const0
+    call fn0(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v12, v13, v14)  ; v0 = 0.0, v1 = 0.0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v7 = 0, v8 = 0, v12 = const2, v13 = const1, v14 = const0
     trap user0
 }