nebius/SWE-rebench-V2-PRs huggingface dataset:
Repository: amaranth-lang/amaranth
Pull request #1516 (2024-09-19 11:18:51)

lib.wiring: fix Signature.is_compliant docstring [0.5 backport]


Patch:
diff --git a/amaranth/hdl/_nir.py b/amaranth/hdl/_nir.py
index 2cd4d28..c15247a 100644
--- a/amaranth/hdl/_nir.py
+++ b/amaranth/hdl/_nir.py
@@ -921,8 +921,8 @@ class AssignmentList(Cell):
     def comb_edges_to(self, bit):
         yield (self.default[bit], self.src_loc)
         for assign in self.assignments:
-            yield (assign.cond, assign.src_loc)
             if bit >= assign.start and bit < assign.start + len(assign.value):
+                yield (assign.cond, assign.src_loc)
                 yield (assign.value[bit - assign.start], assign.src_loc)
 
 
diff --git a/amaranth/lib/wiring.py b/amaranth/lib/wiring.py
index 4a08469..1122a62 100644
--- a/amaranth/lib/wiring.py
+++ b/amaranth/lib/wiring.py
@@ -826,8 +826,8 @@ class Signature(metaclass=SignatureMeta):
             satisfying the requirements below;
           * for port members, is a :ref:`value-like <lang-valuelike>` object casting to
             a :class:`Signal` or a :class:`Const` whose width and signedness is the same as that
-            of the member, and (in case of a :class:`Signal`) which is not reset-less and whose
-            initial value is that of the member;
+            of the member, and (in case of a :class:`Signal`) whose initial value is that of the
+            member;
           * for signature members, matches the description in the signature as verified by
             :meth:`Signature.is_compliant`.
 


Test patch:
diff --git a/tests/test_hdl_ir.py b/tests/test_hdl_ir.py
index e73a972..4899d18 100644
--- a/tests/test_hdl_ir.py
+++ b/tests/test_hdl_ir.py
@@ -3678,6 +3678,30 @@ class CycleTestCase(FHDLTestCase):
                 r"$"):
             build_netlist(Fragment.get(m, None), [])
 
+    def test_assignment_cycle(self):
+        a = Signal(2)
+        m = Module()
+
+        with m.If(a[0]):
+            m.d.comb += a[0].eq(1)
+
+        with self.assertRaisesRegex(CombinationalCycle,
+                r"^Combinational cycle detected, path:\n"
+                r".*test_hdl_ir.py:\d+: cell Matches bit 0\n"
+                r".*test_hdl_ir.py:\d+: signal a bit 0\n"
+                r".*test_hdl_ir.py:\d+: cell AssignmentList bit 0\n"
+                r".*test_hdl_ir.py:\d+: cell PriorityMatch bit 0\n"
+                r"$"):
+            build_netlist(Fragment.get(m, None), [])
+
+        m = Module()
+
+        with m.If(a[0]):
+            m.d.comb += a[1].eq(1)
+
+        # no cycle here, a[1] gets assigned and a[0] gets checked
+        build_netlist(Fragment.get(m, None), [])
+
 
 class DomainLookupTestCase(FHDLTestCase):
     def test_domain_lookup(self):
Repository: amaranth-lang/amaranth
Pull request #1594 (2025-05-11 18:46:55)

hdl._ir: chain Fragment.origins with preexisting [0.5 backport]


Patch:
diff --git a/amaranth/hdl/_ir.py b/amaranth/hdl/_ir.py
index 90ddb8a..57f9d4a 100644
--- a/amaranth/hdl/_ir.py
+++ b/amaranth/hdl/_ir.py
@@ -54,7 +54,7 @@ class Fragment:
         while True:
             if isinstance(obj, Fragment):
                 if hasattr(obj, "origins"):
-                    obj.origins = tuple(origins)
+                    obj.origins = tuple(origins) + (obj.origins or ())
                 return obj
             elif isinstance(obj, Elaboratable):
                 code = obj.elaborate.__code__


Test patch:
diff --git a/tests/test_hdl_ir.py b/tests/test_hdl_ir.py
index 4899d18..a4829b2 100644
--- a/tests/test_hdl_ir.py
+++ b/tests/test_hdl_ir.py
@@ -1079,12 +1079,31 @@ class OriginsTestCase(FHDLTestCase):
         self.assertIs(frag.origins[1], elab2)
         self.assertIs(frag.origins[2], m)
 
+    def test_origins_transformed_elaboratable(self):
+        renamed = DomainRenamer("sync")(elab1 := ElaboratesTo(elab2 := ElaboratesTo(m := Module())))
+        frag = Fragment.get(renamed, platform=None)
+        self.assertEqual(len(frag.origins), 4)
+        self.assertIsInstance(frag.origins, tuple)
+        self.assertIs(frag.origins[0], renamed)
+        self.assertIs(frag.origins[1], elab1)
+        self.assertIs(frag.origins[2], elab2)
+        self.assertIs(frag.origins[3], m)
+
+        renamed_nested = ElaboratesTo(elab2 := ElaboratesTo(renamed := DomainRenamer("sync")(m := Module())))
+        frag = Fragment.get(renamed_nested, platform=None)
+        self.assertEqual(len(frag.origins), 4)
+        self.assertIsInstance(frag.origins, tuple)
+        self.assertIs(frag.origins[0], renamed_nested)
+        self.assertIs(frag.origins[1], elab2)
+        self.assertIs(frag.origins[2], renamed)
+        self.assertIs(frag.origins[3], m)
+
     def test_origins_disable(self):
         inst = Instance("test")
         del inst.origins
         elab = ElaboratesTo(inst)
         frag = Fragment.get(elab, platform=None)
-        self.assertFalse(hasattr(frag, "_origins"))
+        self.assertFalse(hasattr(frag, "origins"))
 
 
 class IOBufferTestCase(FHDLTestCase):