Repository: bytecodealliance/wasmtime
Pull request #6026 (2023-03-15 17:44:21)

x64: Take SIGFPE signals for divide traps
Prior to this commit Wasmtime would configure `avoid_div_traps=true` unconditionally for Cranelift. This, for the division-based instructions, would change emitted code to explicitly trap on trap conditions instead of letting the `div` x86 instruction trap.

There's no specific reason for Wasmtime, however, to specifically avoid traps in the `div` instruction. This means that the extra generated branches on x86 aren't necessary since the `div` and `idiv` instructions already trap for similar conditions as wasm requires.

This commit instead disables the `avoid_div_traps` setting for Wasmtime's usage of Cranelift. Subsequently the codegen rules were updated slightly:

* When `avoid_div_traps=true`, traps are no longer emitted for `div` instructions.
* The `udiv`/`urem` instructions now list their trap as divide-by-zero instead of integer overflow.
* The lowering for `sdiv` was updated to still explicitly check for zero but the integer overflow case is deferred to the instruction itself.
* The lowering of `srem` no longer checks for zero and the listed trap for the `div` instruction is a divide-by-zero.

This means that the codegen for `udiv` and `urem` no longer have any branches. The codegen for `sdiv` removes one branch but keeps the zero-check to differentiate the two kinds of traps. The codegen for `srem` removes one branch but keeps the -1 check since the semantics of `srem` mismatch with the semantics of `idiv` with a -1 divisor (specifically for INT_MIN).

This is unlikely to have really all that much of a speedup but was something I noticed during #6008 which seemed like it'd be good to clean up. Plus Wasmtime's signal handling was already set up to catch `SIGFPE`, it was just never firing.

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Patch:
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index e08191a89..064179ea0 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -82,7 +82,7 @@ jobs:
     if: needs.determine.outputs.audit
     runs-on: ubuntu-latest
     env:
-      CARGO_VET_VERSION: 0.4.0
+      CARGO_VET_VERSION: 0.5.0
     steps:
     - uses: actions/checkout@v3
       with:
diff --git a/cranelift/codegen/meta/src/shared/settings.rs b/cranelift/codegen/meta/src/shared/settings.rs
index 2db1f1303..e68412183 100644
--- a/cranelift/codegen/meta/src/shared/settings.rs
+++ b/cranelift/codegen/meta/src/shared/settings.rs
@@ -97,19 +97,6 @@ pub(crate) fn define() -> SettingGroup {
         false,
     );
 
-    settings.add_bool(
-        "avoid_div_traps",
-        "Generate explicit checks around native division instructions to avoid their trapping.",
-        r#"
-            Generate explicit checks around native division instructions to
-            avoid their trapping.
-
-            On ISAs like ARM where the native division instructions don't trap,
-            this setting has no effect - explicit checks are always inserted.
-        "#,
-        false,
-    );
-
     settings.add_bool(
         "enable_float",
         "Enable the use of floating-point instructions.",
diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle
index 4330b33e0..92a956037 100644
--- a/cranelift/codegen/src/isa/s390x/inst.isle
+++ b/cranelift/codegen/src/isa/s390x/inst.isle
@@ -1446,10 +1446,6 @@
 (decl vxrs_ext2_disabled () Type)
 (extern extractor vxrs_ext2_disabled vxrs_ext2_disabled)
 
-(decl allow_div_traps () Type)
-(extern extractor allow_div_traps allow_div_traps)
-
-
 ;; Helpers for SIMD lane number operations ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; There are two ways to map vector types onto the SIMD vector registers
diff --git a/cranelift/codegen/src/isa/s390x/lower.isle b/cranelift/codegen/src/isa/s390x/lower.isle
index 965074fa6..1db1e8de3 100644
--- a/cranelift/codegen/src/isa/s390x/lower.isle
+++ b/cranelift/codegen/src/isa/s390x/lower.isle
@@ -536,7 +536,6 @@
 (rule (lower (has_type (fits_in_64 ty) (udiv x y)))
       (let (;; Look at the divisor to determine whether we need to generate
             ;; an explicit division-by zero check.
-            (DZcheck bool (zero_divisor_check_needed y))
             ;; Load up the dividend, by loading the input (possibly zero-
             ;; extended) input into the low half of the register pair,
             ;; and setting the high half to zero.
@@ -545,10 +544,6 @@
             ;; Load up the divisor, zero-extended if necessary.
             (ext_y Reg (put_in_reg_zext32 y))
             (ext_ty Type (ty_ext32 ty))
-            ;; Now actually perform the division-by zero check if necessary.
-            ;; This cannot be done earlier than here, because the check
-            ;; requires an already extended divisor value.
-            (_ Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
             ;; Emit the actual divide instruction.
             (pair RegPair (udivmod ext_ty ext_x ext_y)))
         ;; The quotient can be found in the low half of the result.
@@ -557,38 +552,13 @@
 ;; Implement `urem`.  Same as `udiv`, but finds the remainder in
 ;; the high half of the result register pair instead.
 (rule (lower (has_type (fits_in_64 ty) (urem x y)))
-      (let ((DZcheck bool (zero_divisor_check_needed y))
-            (ext_x RegPair (regpair (imm (ty_ext32 ty) 0)
+      (let ((ext_x RegPair (regpair (imm (ty_ext32 ty) 0)
                                     (put_in_reg_zext32 x)))
             (ext_y Reg (put_in_reg_zext32 y))
             (ext_ty Type (ty_ext32 ty))
-            (_ Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
             (pair RegPair (udivmod ext_ty ext_x ext_y)))
         (copy_reg ty (regpair_hi pair))))
 
-;; Determine whether we need to perform a divide-by-zero-check.
-;;
-;; If the `avoid_div_traps` flag is false, we never need to perform
-;; that check; we can rely on the divide instruction itself to trap.
-;;
-;; If the `avoid_div_traps` flag is true, we perform the check explicitly.
-;; This still can be omittted if the divisor is a non-zero immediate.
-(decl zero_divisor_check_needed (Value) bool)
-(rule 2 (zero_divisor_check_needed (i64_from_value x))
-      (if (i64_nonzero x))
-      $false)
-(rule 1 (zero_divisor_check_needed (value_type (allow_div_traps))) $false)
-(rule 0 (zero_divisor_check_needed _) $true)
-
-;; Perform the divide-by-zero check if required.
-;; This is simply a compare-and-trap of the (extended) divisor against 0.
-(decl maybe_trap_if_zero_divisor (bool Type Reg) Reg)
-(rule (maybe_trap_if_zero_divisor $false _ _) (invalid_reg))
-(rule (maybe_trap_if_zero_divisor $true ext_ty reg)
-      (icmps_simm16_and_trap ext_ty reg 0
-                             (intcc_as_cond (IntCC.Equal))
-                             (trap_code_division_by_zero)))
-
 
 ;;;; Rules for `sdiv` and `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -610,15 +580,12 @@
 (rule (lower (has_type (fits_in_64 ty) (sdiv x y)))
       (let (;; Look at the divisor to determine whether we need to generate
             ;; explicit division-by-zero and/or integer-overflow checks.
-            (DZcheck bool (zero_divisor_check_needed y))
             (OFcheck bool (div_overflow_check_needed y))
             ;; Load up the dividend (sign-extended to 64-bit)
             (ext_x Reg (put_in_reg_sext64 x))
             ;; Load up the divisor (sign-extended if necessary).
             (ext_y Reg (put_in_reg_sext32 y))
             (ext_ty Type (ty_ext32 ty))
-            ;; Perform division-by-zero check (same as for `udiv`).
-            (_ Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
             ;; Perform integer-overflow check if necessary.
             (_ Reg (maybe_trap_if_sdiv_overflow OFcheck ext_ty ty ext_x ext_y))
             ;; Emit the actual divide instruction.
@@ -630,12 +597,10 @@
 ;; the high half of the result register pair instead.  Also, handle
 ;; the integer overflow case differently, see below.
 (rule (lower (has_type (fits_in_64 ty) (srem x y)))
-      (let ((DZcheck bool (zero_divisor_check_needed y))
-            (OFcheck bool (div_overflow_check_needed y))
+      (let ((OFcheck bool (div_overflow_check_needed y))
             (ext_x Reg (put_in_reg_sext64 x))
             (ext_y Reg (put_in_reg_sext32 y))
             (ext_ty Type (ty_ext32 ty))
-            (_ Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
             (checked_x Reg (maybe_avoid_srem_overflow OFcheck ext_ty ext_x ext_y))
             (pair RegPair (sdivmod ext_ty checked_x ext_y)))
         (copy_reg ty (regpair_hi pair))))
diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs
index 7baf0f5cf..f32d38b79 100644
--- a/cranelift/codegen/src/isa/s390x/lower/isle.rs
+++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs
@@ -291,15 +291,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, S390xBackend> {
         Box::new(symbol_reloc.clone())
     }
 
-    #[inline]
-    fn allow_div_traps(&mut self, _: Type) -> Option<()> {
-        if !self.backend.flags.avoid_div_traps() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
     #[inline]
     fn mie2_enabled(&mut self, _: Type) -> Option<()> {
         if self.backend.isa_flags.has_mie2() {
diff --git a/cranelift/codegen/src/isa/x64/inst.isle b/cranelift/codegen/src/isa/x64/inst.isle
index faf5bc045..69b926f82 100644
--- a/cranelift/codegen/src/isa/x64/inst.isle
+++ b/cranelift/codegen/src/isa/x64/inst.isle
@@ -63,6 +63,7 @@
        ;; instruction.
        (Div (size OperandSize) ;; 2, 4, or 8
             (sign DivSignedness)
+            (trap TrapCode)
             (divisor GprMem)
             (dividend_lo Gpr)
             (dividend_hi Gpr)
@@ -71,6 +72,7 @@
 
        ;; Same as `Div`, but for 8-bits where the regalloc behavior is different
        (Div8 (sign DivSignedness)
+             (trap TrapCode)
              (divisor GprMem)
              (dividend Gpr)
              (dst WritableGpr))
@@ -103,29 +105,6 @@
                         (divisor Gpr)
                         (dst WritableGpr))
 
-       ;; Validates that the `divisor` can be safely divided into the
-       ;; `dividend`.
-       ;;
-       ;; This is a separate pseudo-instruction because it has some jumps in
-       ;; ways that can't be modeled otherwise with instructions right now. This
-       ;; will trap if the `divisor` is zero or if it's -1 and `dividend` is
-       ;; INT_MIN for the associated type.
-       ;;
-       ;; Note that 64-bit types must use `ValidateSdivDivisor64`.
-       (ValidateSdivDivisor (size OperandSize)
-                            (dividend Gpr)
-                            (divisor Gpr))
-
-       ;; Same as `ValidateSdivDivisor` but for 64-bit types.
-       ;;
-       ;; This is a distinct instruction because the emission in `emit.rs`
-       ;; requires a temporary register to load an immediate into, hence the
-       ;; `tmp` field in this instruction not present in the non-64-bit one.
-       (ValidateSdivDivisor64 (dividend Gpr)
-                              (divisor Gpr)
-                              (tmp WritableGpr))
-
-
        ;; Do a sign-extend based on the sign of the value in rax into rdx: (cwd
        ;; cdq cqo) or al into ah: (cbw)
        (SignExtendData (size OperandSize) ;; 1, 2, 4, or 8
@@ -170,7 +149,8 @@
 
        ;; Loads the memory address of addr into dst.
        (LoadEffectiveAddress (addr SyntheticAmode)
-                             (dst WritableGpr))
+                             (dst WritableGpr)
+                             (size OperandSize))
 
        ;; Sign-extended loads and moves: movs (bl bq wl wq lq) addr reg.
        (MovsxRmR (ext_mode ExtMode)
@@ -917,6 +897,8 @@
             Punpcklqdq
             Pshuflw
             Pshufhw
+            Pblendw
+            Movddup
           ))
 
 (type CmpOpcode extern
@@ -990,25 +972,6 @@
              ;; the given MachLabel.
              (RipRelative (target MachLabel))))
 
-;; Some Amode constructor helpers.
-
-(decl amode_with_flags (Amode MemFlags) Amode)
-(extern constructor amode_with_flags amode_with_flags)
-
-(decl amode_imm_reg (u32 Gpr) Amode)
-(extern constructor amode_imm_reg amode_imm_reg)
-
-(decl amode_imm_reg_flags (u32 Gpr MemFlags) Amode)
-(rule (amode_imm_reg_flags offset base flags)
-      (amode_with_flags (amode_imm_reg offset base) flags))
-
-(decl amode_imm_reg_reg_shift (u32 Gpr Gpr u8) Amode)
-(extern constructor amode_imm_reg_reg_shift amode_imm_reg_reg_shift)
-
-(decl amode_imm_reg_reg_shift_flags (u32 Gpr Gpr u8 MemFlags) Amode)
-(rule (amode_imm_reg_reg_shift_flags offset base index shift flags)
-      (amode_with_flags (amode_imm_reg_reg_shift offset base index shift) flags))
-
 ;; A helper to both check that the `Imm64` and `Offset32` values sum to less
 ;; than 32-bits AND return this summed `u32` value. Also, the `Imm64` will be
 ;; zero-extended from `Type` up to 64 bits. This is useful for `to_amode`.
@@ -1017,168 +980,59 @@
 
 ;;;; Amode lowering ;;;;
 
-;; To generate an address for a memory access, we can pattern-match
-;; various CLIF sub-trees to x64's complex addressing modes (`Amode`).
-;;
-;; Information about available addressing modes is available in
-;; Intel's Software Developer's Manual, volume 2, section 2.1.5,
-;; "Addressing-Mode Encoding of ModR/M and SIB Bytes."
-;;
-;; The general strategy to build an `Amode` is to traverse over the
-;; input expression's addends, recursively deconstructing a tree of
-;; `iadd` operators that add up parts of the address, updating the
-;; `Amode` in an incremental fashion as we add in each piece.
-;;
-;; We start with an "immediate + register" form that encapsulates the
-;; load/store's built-in `Offset32` and `invalid_reg` as the
-;; register. This is given by `amode_initial`. Then we add `Value`s
-;; one at a time with `amode_add`. (Why start with `invalid_reg` at
-;; all? Because we don't want to special-case the first input and
-;; duplicate rules; this lets us use the "add a value" logic even for
-;; the first value.)
-;;
-;; It is always valid to use `amode_add` to add the one single
-;; `address` input to the load/store (i.e., the `Value` given to
-;; `to_amode`). In the fallback case, this is what we do. Then we get
-;; an `Amode.ImmReg` with the `Offset32` and `Value` below and nothing
-;; else; this always works and is not *that* bad.
-;;
-;; But we can often do better. The toplevel rule for `iadd` below will
-;; turn an `(amode_add amode (iadd a b))` into two invocations of
-;; `amode_add`, for each operand of the `iadd`. This is what allows us
-;; to handle sums of many parts.
-;;
-;; Then we "just" need to work out how we can incorporate a new
-;; component into an existing addressing mode:
-;;
-;; - Case 1: When we have an `ImmReg` and the register is
-;;   `invalid_reg` (the initial `Amode` above), we can put the new
-;;   addend into a register and insert it into the `ImmReg`.
-;;
-;; - Case 2: When we have an `ImmReg` with a valid register already,
-;;   and we have another register to add, we can transition to an
-;;   `ImmRegRegShift`.
-;;
-;; - Case 3: When we're adding an `ishl`, we can refine the above rule
-;;   and use the built-in multiplier of 1, 2, 4, 8 to implement a
-;;   left-shift by 0, 1, 2, 3.
-;;
-;; - Case 4: When we are adding another constant offset, we can fold
-;;   it into the existing offset, as long as the sum still fits into
-;;   the signed 32-bit field.
-;;
-;; - Case 5: And as a general fallback, we can generate a new `add`
-;;   instruction and add the new addend to an existing component of
-;;   the `Amode`.
+;; Converts a `Value` and a static offset into an `Amode` for x64, attempting
+;; to be as fancy as possible with offsets/registers/shifts/etc to make maximal
+;; use of the x64 addressing modes.
 (decl to_amode (MemFlags Value Offset32) Amode)
 
-;; Initial step in amode processing: create an ImmReg with
-;; (invalid_reg) and encapsulating the flags and offset from the
-;; load/store.
-(decl amode_initial (MemFlags Offset32) Amode)
-(rule (amode_initial flags (offset32 off))
-      (Amode.ImmReg off (invalid_reg) flags))
+;; Base case, "just put it in a register"
+(rule (to_amode flags base offset)
+      (Amode.ImmReg offset base flags))
 
-;; One step in amode processing: take an existing amode and add
-;; another value to it.
-(decl amode_add (Amode Value) Amode)
+;; Slightly-more-fancy case, if the address is the addition of two things then
+;; delegate to the `to_amode_add` helper.
+(rule 1 (to_amode flags (iadd x y) offset)
+      (to_amode_add flags x y offset))
 
-;; -- Top-level driver: pull apart the addends.
-;;
-;; Any amode can absorb an `iadd` by absorbing first the LHS of the
-;; add, then the RHS.
-;;
-;; Priority 2 to take this above fallbacks and ensure we traverse the
-;; `iadd` tree fully.
-(rule 2 (amode_add amode (iadd x y))
-      (let ((amode1 Amode (amode_add amode x))
-            (amode2 Amode (amode_add amode1 y)))
-        amode2))
-
-;; -- Case 1 (adding a register to the initial Amode with invalid_reg).
-;;
-;; An Amode.ImmReg with invalid_reg (initial state) can absorb a
-;; register as the base register.
-(rule (amode_add (Amode.ImmReg off (invalid_reg) flags) value)
-      (Amode.ImmReg off value flags))
+;; Same as `to_amode`, except that the base address is computed via the addition
+;; of the two `Value` arguments provided.
+(decl to_amode_add (MemFlags Value Value Offset32) Amode)
 
-;; -- Case 2 (adding a register to an Amode with a register already).
-;;
-;; An Amode.ImmReg can absorb another register as the index register.
-(rule (amode_add (Amode.ImmReg off (valid_reg base) flags) value)
-      ;; Shift of 0 --> base + 1*value.
-      (Amode.ImmRegRegShift off base value 0 flags))
+;; Base case, "just put things in registers". Note that the shift value of 0
+;; here  means `x + (y << 0)` which is the same as `x + y`.
+(rule (to_amode_add flags x y offset)
+      (Amode.ImmRegRegShift offset x y 0 flags))
 
-;; -- Case 3 (adding a shifted value to an Amode).
-;;
-;; An Amode.ImmReg can absorb a shift of another register as the index register.
-;;
-;; Priority 2 to take these rules above generic case.
-(rule 2 (amode_add (Amode.ImmReg off (valid_reg base) flags) (ishl index (iconst (uimm8 shift))))
+;; If the one of the arguments being added is itself a constant shift then
+;; that can be modeled directly so long as the shift is a modestly small amount.
+(rule 1 (to_amode_add flags x (ishl y (iconst (uimm8 shift))) offset)
       (if (u32_lteq (u8_as_u32 shift) 3))
-      (Amode.ImmRegRegShift off base index shift flags))
+      (Amode.ImmRegRegShift offset x y shift flags))
+(rule 2 (to_amode_add flags (ishl y (iconst (uimm8 shift))) x offset)
+      (if (u32_lteq (u8_as_u32 shift) 3))
+      (Amode.ImmRegRegShift offset x y shift flags))
 
-;; -- Case 4 (absorbing constant offsets).
-;;
-;; An Amode can absorb a constant (i64, or extended i32) as long as
-;; the sum still fits in the signed-32-bit offset.
+;; Constant extraction rules.
 ;;
-;; Priority 3 in order to take this option above the fallback
-;; (immediate in register). Two rules, for imm+reg and
-;; imm+reg+scale*reg cases.
-(rule 3 (amode_add (Amode.ImmReg off base flags)
-                   (iconst (simm32 c)))
-      (if-let sum (s32_add_fallible off c))
-      (Amode.ImmReg sum base flags))
-(rule 3 (amode_add (Amode.ImmRegRegShift off base index shift flags)
-                   (iconst (simm32 c)))
-      (if-let sum (s32_add_fallible off c))
-      (Amode.ImmRegRegShift sum base index shift flags))
-
-;; Likewise for a zero-extended i32 const, as long as the constant
-;; wasn't negative. (Why nonnegative? Because adding a
-;; non-sign-extended negative to a 64-bit address is not the same as
-;; adding in simm32-space.)
-(rule 3 (amode_add (Amode.ImmReg off base flags)
-                   (uextend (iconst (simm32 (u32_nonnegative c)))))
-      (if-let sum (s32_add_fallible off c))
-      (Amode.ImmReg sum base flags))
-(rule 3 (amode_add (Amode.ImmRegRegShift off base index shift flags)
-                   (uextend (iconst (simm32 (u32_nonnegative c)))))
-      (if-let sum (s32_add_fallible off c))
-      (Amode.ImmRegRegShift sum base index shift flags))
-
-;; Likewise for a sign-extended i32 const.
-(rule 3 (amode_add (Amode.ImmReg off base flags)
-                   (sextend (iconst (simm32 c))))
-      (if-let sum (s32_add_fallible off c))
-      (Amode.ImmReg sum base flags))
-(rule 3 (amode_add (Amode.ImmRegRegShift off base index shift flags)
-                   (sextend (iconst (simm32 c))))
-      (if-let sum (s32_add_fallible off c))
-      (Amode.ImmRegRegShift sum base index shift flags))
-
-;; -- Case 5 (fallback to add a new value to an imm+reg+scale*reg).
+;; These rules attempt to find a constant within one of `x` or `y`, or deeper
+;; within them if they have their own adds. These only succeed if the constant
+;; itself can be represented with 32-bits and can be infallibly added to the
+;; offset that we already have.
 ;;
-;; An Amode.ImmRegRegShift can absorb any other value by creating a
-;; new add instruction and replacing the base with
-;; (base+value).
-(rule (amode_add (Amode.ImmRegRegShift off base index shift flags) value)
-      (let ((sum Gpr (x64_add $I64 base value)))
-        (Amode.ImmRegRegShift off sum index shift flags)))
-
-;; Finally, define the toplevel `to_amode`.
-(rule (to_amode flags base @ (value_type (ty_addr64 _)) offset)
-      (amode_finalize (amode_add (amode_initial flags offset) base)))
-
-;; If an amode has no registers at all and only offsets (a constant
-;; value), we need to "finalize" it by sticking in a zero'd reg in
-;; place of the (invalid_reg) produced by (amode_initial).
-(decl amode_finalize (Amode) Amode)
-(rule 1 (amode_finalize (Amode.ImmReg off (invalid_reg) flags))
-      (Amode.ImmReg off (imm $I64 0) flags))
-(rule 0 (amode_finalize amode)
-      amode)
+;; Note the recursion here where this rule is defined in terms of itself to
+;; "peel" layers of constants.
+(rule 3 (to_amode_add flags (iadd x (iconst (simm32 c))) y offset)
+      (if-let sum (s32_add_fallible offset c))
+      (to_amode_add flags x y sum))
+(rule 4 (to_amode_add flags x (iadd y (iconst (simm32 c))) offset)
+      (if-let sum (s32_add_fallible offset c))
+      (to_amode_add flags x y sum))
+(rule 5 (to_amode_add flags x (iconst (simm32 c)) offset)
+      (if-let sum (s32_add_fallible offset c))
+      (to_amode flags x sum))
+(rule 6 (to_amode_add flags (iconst (simm32 c)) x offset)
+      (if-let sum (s32_add_fallible offset c))
+      (to_amode flags x sum))
 
 ;; Offsetting an Amode. Used when we need to do consecutive
 ;; loads/stores to adjacent addresses.
@@ -1417,6 +1271,12 @@
             Vpextrw
             Vpextrd
             Vpextrq
+            Vpblendw
+            Vmovddup
+            Vpbroadcastb
+            Vpbroadcastw
+            Vpbroadcastd
+            Vbroadcastss
           ))
 
 (type Avx512Opcode extern
@@ -1747,6 +1607,9 @@
 (decl pure has_avx () bool)
 (extern constructor has_avx has_avx)
 
+(decl pure has_avx2 () bool)
+(extern constructor has_avx2 has_avx2)
+
 ;;;; Helpers for Merging and Sinking Immediates/Loads  ;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Extract a constant `Imm8Reg.Imm8` from a value operand.
@@ -1781,9 +1644,21 @@
 
 ;; Extract a `SinkableLoad` that works with `RegMemImm.Mem` from a value
 ;; operand.
+;;
+;; Note that this will only work for 32-bit-types-or-larger since this is
+;; pervasively used with operations that load a minimum of 32-bits. For
+;; instructions which load exactly the type width necessary use
+;; `sinkable_load_exact`.
 (decl sinkable_load (SinkableLoad) Value)
 (extern extractor sinkable_load sinkable_load)
 
+;; Same as `sinkable_load` except that all type widths of loads are supported.
+;;
+;; Only use this when the instruction which performs the load is guaranteed to
+;; load the precisely correct size.
+(decl sinkable_load_exact (SinkableLoad) Value)
+(extern extractor sinkable_load_exact sinkable_load_exact)
+
 ;; Sink a `SinkableLoad` into a `SyntheticAmode`.
 ;;
 ;; This is a side-effectful operation that notifies the context that the
@@ -1803,6 +1678,9 @@
 (decl sink_load_to_reg_mem (SinkableLoad) RegMem)
 (rule (sink_load_to_reg_mem load) (RegMem.Mem load))
 
+(decl sink_load_to_gpr_mem (SinkableLoad) GprMem)
+(rule (sink_load_to_gpr_mem load) (RegMem.Mem load))
+
 (decl sink_load_to_reg_mem_imm (SinkableLoad) RegMemImm)
 (rule (sink_load_to_reg_mem_imm load) (RegMemImm.Mem load))
 
@@ -3094,6 +2972,14 @@
       (if-let $true (has_avx))
       (xmm_rmr_blend_vex (AvxOpcode.Vpblendvb) src1 src2 mask))
 
+;; Helper for creating `pblendw` instructions.
+(decl x64_pblendw (Xmm XmmMem u8) Xmm)
+(rule 0 (x64_pblendw src1 src2 imm)
+      (xmm_rm_r_imm (SseOpcode.Pblendw) src1 src2 imm (OperandSize.Size32)))
+(rule 1 (x64_pblendw src1 src2 imm)
+      (if-let $true (has_avx))
+      (xmm_rmr_imm_vex (AvxOpcode.Vpblendw) src1 src2 imm))
+
 ;; Helper for creating a `movsd` instruction which creates a new vector
 ;; register where the upper 64-bits are from the first operand and the low
 ;; 64-bits are from the second operand.
@@ -3787,10 +3673,10 @@
             (inst MInst (MInst.Neg size src dst)))
         (ProducesFlags.ProducesFlagsReturnsResultWithConsumer inst dst)))
 
-(decl x64_lea (SyntheticAmode) Gpr)
-(rule (x64_lea addr)
+(decl x64_lea (Type SyntheticAmode) Gpr)
+(rule (x64_lea ty addr)
       (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.LoadEffectiveAddress addr dst))))
+            (_ Unit (emit (MInst.LoadEffectiveAddress addr dst (operand_size_of_type_32_64 ty)))))
         dst))
 
 ;; Helper for creating `ud2` instructions.
@@ -4220,6 +4106,34 @@
 (rule (trap_if_fcmp (FcmpCondResult.OrCondition producer cc1 cc2) tc)
       (with_flags_side_effect producer (trap_if_or cc1 cc2 tc)))
 
+;; Helper for creating `movddup` instructions
+(decl x64_movddup (XmmMem) Xmm)
+(rule (x64_movddup src)
+      (xmm_unary_rm_r_unaligned (SseOpcode.Movddup) src))
+(rule 1 (x64_movddup src)
+        (if-let $true (has_avx))
+        (xmm_unary_rm_r_vex (AvxOpcode.Vmovddup) src))
+
+;; Helper for creating `vpbroadcastb` instructions
+(decl x64_vpbroadcastb (XmmMem) Xmm)
+(rule (x64_vpbroadcastb src)
+      (xmm_unary_rm_r_vex (AvxOpcode.Vpbroadcastb) src))
+
+;; Helper for creating `vpbroadcastw` instructions
+(decl x64_vpbroadcastw (XmmMem) Xmm)
+(rule (x64_vpbroadcastw src)
+      (xmm_unary_rm_r_vex (AvxOpcode.Vpbroadcastw) src))
+
+;; Helper for creating `vpbroadcastd` instructions
+(decl x64_vpbroadcastd (XmmMem) Xmm)
+(rule (x64_vpbroadcastd src)
+      (xmm_unary_rm_r_vex (AvxOpcode.Vpbroadcastd) src))
+
+;; Helper for creating `vbroadcastss` instructions
+(decl x64_vbroadcastss (XmmMem) Xmm)
+(rule (x64_vbroadcastss src)
+      (xmm_unary_rm_r_vex (AvxOpcode.Vbroadcastss) src))
+
 ;;;; Jumps ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Unconditional jump.
@@ -4571,32 +4485,32 @@
         dst))
 
 ;; Helper for creating `Div8` instructions
-(decl x64_div8 (Gpr GprMem DivSignedness) Gpr)
-(rule (x64_div8 dividend divisor sign)
+(decl x64_div8 (Gpr GprMem DivSignedness TrapCode) Gpr)
+(rule (x64_div8 dividend divisor sign trap)
       (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.Div8 sign divisor dividend dst))))
+            (_ Unit (emit (MInst.Div8 sign trap divisor dividend dst))))
         dst))
 
 ;; Helper for creating `Div` instructions
 ;;
 ;; Two registers are returned through `ValueRegs` where the first is the
 ;; quotient and the second is the remainder.
-(decl x64_div (Gpr Gpr GprMem OperandSize DivSignedness) ValueRegs)
-(rule (x64_div dividend_lo dividend_hi divisor size sign)
+(decl x64_div (Gpr Gpr GprMem OperandSize DivSignedness TrapCode) ValueRegs)
+(rule (x64_div dividend_lo dividend_hi divisor size sign trap)
       (let ((dst_quotient WritableGpr (temp_writable_gpr))
             (dst_remainder WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.Div size sign divisor dividend_lo dividend_hi dst_quotient dst_remainder))))
+            (_ Unit (emit (MInst.Div size sign trap divisor dividend_lo dividend_hi dst_quotient dst_remainder))))
         (value_regs dst_quotient dst_remainder)))
 
 ;; Helper for `Div`, returning the quotient and discarding the remainder.
-(decl x64_div_quotient (Gpr Gpr GprMem OperandSize DivSignedness) ValueRegs)
-(rule (x64_div_quotient dividend_lo dividend_hi divisor size sign)
-      (value_regs_get (x64_div dividend_lo dividend_hi divisor size sign) 0))
+(decl x64_div_quotient (Gpr Gpr GprMem OperandSize DivSignedness TrapCode) ValueRegs)
+(rule (x64_div_quotient dividend_lo dividend_hi divisor size sign trap)
+      (value_regs_get (x64_div dividend_lo dividend_hi divisor size sign trap) 0))
 
 ;; Helper for `Div`, returning the remainder and discarding the quotient.
-(decl x64_div_remainder (Gpr Gpr GprMem OperandSize DivSignedness) ValueRegs)
-(rule (x64_div_remainder dividend_lo dividend_hi divisor size sign)
-      (value_regs_get (x64_div dividend_lo dividend_hi divisor size sign) 1))
+(decl x64_div_remainder (Gpr Gpr GprMem OperandSize DivSignedness TrapCode) ValueRegs)
+(rule (x64_div_remainder dividend_lo dividend_hi divisor size sign trap)
+      (value_regs_get (x64_div dividend_lo dividend_hi divisor size sign trap) 1))
 
 ;; Helper for creating `SignExtendData` instructions
 (decl x64_sign_extend_data (Gpr OperandSize) Gpr)
@@ -4605,21 +4519,6 @@
             (_ Unit (emit (MInst.SignExtendData size src dst))))
         dst))
 
-;; Helper for creating `ValidateSdivDivisor` instructions.
-(decl validate_sdiv_divisor (OperandSize Gpr Gpr) Gpr)
-(rule (validate_sdiv_divisor size dividend divisor)
-      (let ((_ Unit (emit (MInst.ValidateSdivDivisor size dividend divisor))))
-        divisor))
-
-;; Helper for creating `ValidateSdivDivisor64` instructions.
-(decl validate_sdiv_divisor64 (Gpr Gpr) Gpr)
-(rule (validate_sdiv_divisor64 dividend divisor)
-      (let (
-          (tmp WritableGpr (temp_writable_gpr))
-          (_ Unit (emit (MInst.ValidateSdivDivisor64 dividend divisor tmp)))
-        )
-        divisor))
-
 ;;;; Pinned Register ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl read_pinned_gpr () Gpr)
@@ -4781,6 +4680,7 @@
 (convert AtomicRmwOp MachAtomicRmwOp atomic_rmw_op_to_mach_atomic_rmw_op)
 
 (convert SinkableLoad RegMem sink_load_to_reg_mem)
+(convert SinkableLoad GprMem sink_load_to_gpr_mem)
 (convert SinkableLoad RegMemImm sink_load_to_reg_mem_imm)
 (convert SinkableLoad GprMemImm sink_load_to_gpr_mem_imm)
 (convert SinkableLoad XmmMem sink_load_to_xmm_mem)
diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs
index 024313c45..d7a851e66 100644
--- a/cranelift/codegen/src/isa/x64/inst/args.rs
+++ b/cranelift/codegen/src/isa/x64/inst/args.rs
@@ -928,6 +928,7 @@ pub(crate) enum InstructionSet {
     BMI2,
     FMA,
     AVX,
+    AVX2,
     AVX512BITALG,
     AVX512DQ,
     AVX512F,
@@ -1125,6 +1126,8 @@ pub enum SseOpcode {
     Punpcklqdq,
     Pshuflw,
     Pshufhw,
+    Pblendw,
+    Movddup,
 }
 
 impl SseOpcode {
@@ -1279,7 +1282,8 @@ impl SseOpcode {
             | SseOpcode::Pmulhrsw
             | SseOpcode::Pshufb
             | SseOpcode::Phaddw
-            | SseOpcode::Phaddd => SSSE3,
+            | SseOpcode::Phaddd
+            | SseOpcode::Movddup => SSSE3,
 
             SseOpcode::Blendvpd
             | SseOpcode::Blendvps
@@ -1318,7 +1322,8 @@ impl SseOpcode {
             | SseOpcode::Roundps
             | SseOpcode::Roundpd
             | SseOpcode::Roundss
-            | SseOpcode::Roundsd => SSE41,
+            | SseOpcode::Roundsd
+            | SseOpcode::Pblendw => SSE41,
 
             SseOpcode::Pcmpgtq => SSE42,
         }
@@ -1521,6 +1526,8 @@ impl fmt::Debug for SseOpcode {
             SseOpcode::Punpckhqdq => "punpckhqdq",
             SseOpcode::Pshuflw => "pshuflw",
             SseOpcode::Pshufhw => "pshufhw",
+            SseOpcode::Pblendw => "pblendw",
+            SseOpcode::Movddup => "movddup",
         };
         write!(fmt, "{}", name)
     }
@@ -1705,9 +1712,16 @@ impl AvxOpcode {
             | AvxOpcode::Vpextrb
             | AvxOpcode::Vpextrw
             | AvxOpcode::Vpextrd
-            | AvxOpcode::Vpextrq => {
+            | AvxOpcode::Vpextrq
+            | AvxOpcode::Vpblendw
+            | AvxOpcode::Vmovddup
+            | AvxOpcode::Vbroadcastss => {
                 smallvec![InstructionSet::AVX]
             }
+
+            AvxOpcode::Vpbroadcastb | AvxOpcode::Vpbroadcastw | AvxOpcode::Vpbroadcastd => {
+                smallvec![InstructionSet::AVX2]
+            }
         }
     }
 }
diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs
index 4e409979d..3e19d3344 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit.rs
@@ -122,6 +122,7 @@ pub(crate) fn emit(
             InstructionSet::BMI2 => info.isa_flags.has_bmi2(),
             InstructionSet::FMA => info.isa_flags.has_fma(),
             InstructionSet::AVX => info.isa_flags.has_avx(),
+            InstructionSet::AVX2 => info.isa_flags.has_avx2(),
             InstructionSet::AVX512BITALG => info.isa_flags.has_avx512bitalg(),
             InstructionSet::AVX512DQ => info.isa_flags.has_avx512dq(),
             InstructionSet::AVX512F => info.isa_flags.has_avx512f(),
@@ -399,7 +400,18 @@ pub(crate) fn emit(
             emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
         }
 
-        Inst::Div { sign, divisor, .. } | Inst::Div8 { sign, divisor, .. } => {
+        Inst::Div {
+            sign,
+            trap,
+            divisor,
+            ..
+        }
+        | Inst::Div8 {
+            sign,
+            trap,
+            divisor,
+            ..
+        } => {
             let divisor = divisor.clone().to_reg_mem().with_allocs(allocs);
             let size = match inst {
                 Inst::Div {
@@ -437,7 +449,7 @@ pub(crate) fn emit(
                 OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
             };
 
-            sink.add_trap(TrapCode::IntegerDivisionByZero);
+            sink.add_trap(*trap);
 
             let subopcode = match sign {
                 DivSignedness::Signed => 7,
@@ -612,6 +624,7 @@ pub(crate) fn emit(
             let inst = match size {
                 OperandSize::Size8 => Inst::div8(
                     DivSignedness::Signed,
+                    TrapCode::IntegerDivisionByZero,
                     RegMem::reg(divisor),
                     Gpr::new(regs::rax()).unwrap(),
                     Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
@@ -619,6 +632,7 @@ pub(crate) fn emit(
                 _ => Inst::div(
                     size,
                     DivSignedness::Signed,
+                    TrapCode::IntegerDivisionByZero,
                     RegMem::reg(divisor),
                     Gpr::new(regs::rax()).unwrap(),
                     Gpr::new(regs::rdx()).unwrap(),
@@ -631,55 +645,6 @@ pub(crate) fn emit(
             sink.bind_label(done_label);
         }
 
-        Inst::ValidateSdivDivisor {
-            dividend, divisor, ..
-        }
-        | Inst::ValidateSdivDivisor64 {
-            dividend, divisor, ..
-        } => {
-            let orig_inst = &inst;
-            let divisor = allocs.next(divisor.to_reg());
-            let dividend = allocs.next(dividend.to_reg());
-            let size = match inst {
-                Inst::ValidateSdivDivisor { size, .. } => *size,
-                _ => OperandSize::Size64,
-            };
-
-            // First trap if the divisor is zero
-            let inst = Inst::cmp_rmi_r(size, RegMemImm::imm(0), divisor);
-            inst.emit(&[], sink, info, state);
-            let inst = Inst::trap_if(CC::Z, TrapCode::IntegerDivisionByZero);
-            inst.emit(&[], sink, info, state);
-
-            // Now check if the divisor is -1. If it is then additionally
-            // check if the dividend is INT_MIN. If it isn't then jump to the
-            // end. If both conditions here are true then trap.
-            let inst = Inst::cmp_rmi_r(size, RegMemImm::imm(0xffffffff), divisor);
-            inst.emit(&[], sink, info, state);
-            let done = sink.get_label();
-            one_way_jmp(sink, CC::NZ, done);
-            let int_min = match orig_inst {
-                Inst::ValidateSdivDivisor64 { tmp, .. } => {
-                    let tmp = allocs.next(tmp.to_reg().to_reg());
-                    let inst = Inst::imm(size, i64::MIN as u64, Writable::from_reg(tmp));
-                    inst.emit(&[], sink, info, state);
-                    RegMemImm::reg(tmp)
-                }
-                _ => RegMemImm::imm(match size {
-                    OperandSize::Size8 => 0x80,
-                    OperandSize::Size16 => 0x8000,
-                    OperandSize::Size32 => 0x80000000,
-                    OperandSize::Size64 => unreachable!(),
-                }),
-            };
-            let inst = Inst::cmp_rmi_r(size, int_min, dividend);
-            inst.emit(&[], sink, info, state);
-            let inst = Inst::trap_if(CC::Z, TrapCode::IntegerOverflow);
-            inst.emit(&[], sink, info, state);
-
-            sink.bind_label(done);
-        }
-
         Inst::Imm {
             dst_size,
             simm64,
@@ -869,20 +834,84 @@ pub(crate) fn emit(
             )
         }
 
-        Inst::LoadEffectiveAddress { addr, dst } => {
+        Inst::LoadEffectiveAddress { addr, dst, size } => {
             let dst = allocs.next(dst.to_reg().to_reg());
             let amode = addr.finalize(state, sink).with_allocs(allocs);
 
-            emit_std_reg_mem(
-                sink,
-                LegacyPrefixes::None,
-                0x8D,
-                1,
-                dst,
-                &amode,
-                RexFlags::set_w(),
-                0,
-            );
+            // If this `lea` can actually get encoded as an `add` then do that
+            // instead. Currently all candidate `iadd`s become an `lea`
+            // pseudo-instruction here but maximizing the sue of `lea` is not
+            // necessarily optimal. The `lea` instruction goes through dedicated
+            // address units on cores which are finite and disjoint from the
+            // general ALU, so if everything uses `lea` then those units can get
+            // saturated while leaving the ALU idle.
+            //
+            // To help make use of more parts of a cpu, this attempts to use
+            // `add` when it's semantically equivalent to `lea`, or otherwise
+            // when the `dst` register is the same as the `base` or `index`
+            // register.
+            //
+            // FIXME: ideally regalloc is informed of this constraint. Register
+            // allocation of `lea` should "attempt" to put the `base` in the
+            // same register as `dst` but not at the expense of generating a
+            // `mov` instruction. Currently that's not possible but perhaps one
+            // day it may be worth it.
+            match amode {
+                // If `base == dst` then this is `add $imm, %dst`, so encode
+                // that instead.
+                Amode::ImmReg {
+                    simm32,
+                    base,
+                    flags: _,
+                } if base == dst => {
+                    let inst = Inst::alu_rmi_r(
+                        *size,
+                        AluRmiROpcode::Add,
+                        RegMemImm::imm(simm32),
+                        Writable::from_reg(dst),
+                    );
+                    inst.emit(&[], sink, info, state);
+                }
+                // If the offset is 0 and the shift is 0 (meaning multiplication
+                // by 1) then:
+                //
+                // * If `base == dst`, then this is `add %index, %base`
+                // * If `index == dst`, then this is `add %base, %index`
+                //
+                // Encode the appropriate instruction here in that case.
+                Amode::ImmRegRegShift {
+                    simm32: 0,
+                    base,
+                    index,
+                    shift: 0,
+                    flags: _,
+                } if base == dst || index == dst => {
+                    let (dst, operand) = if base == dst {
+                        (base, index)
+                    } else {
+                        (index, base)
+                    };
+                    let inst = Inst::alu_rmi_r(
+                        *size,
+                        AluRmiROpcode::Add,
+                        RegMemImm::reg(operand.to_reg()),
+                        Writable::from_reg(dst.to_reg()),
+                    );
+                    inst.emit(&[], sink, info, state);
+                }
+
+                // If `lea`'s 3-operand mode is leveraged by regalloc, or if
+                // it's fancy like imm-plus-shift-plus-base, then `lea` is
+                // actually emitted.
+                _ => {
+                    let flags = match size {
+                        OperandSize::Size32 => RexFlags::clear_w(),
+                        OperandSize::Size64 => RexFlags::set_w(),
+                        _ => unreachable!(),
+                    };
+                    emit_std_reg_mem(sink, LegacyPrefixes::None, 0x8D, 1, dst, &amode, flags, 0);
+                }
+            };
         }
 
         Inst::MovsxRmR { ext_mode, src, dst } => {
@@ -1762,6 +1791,7 @@ pub(crate) fn emit(
                 SseOpcode::Sqrtpd => (LegacyPrefixes::_66, 0x0F51, 2),
                 SseOpcode::Sqrtss => (LegacyPrefixes::_F3, 0x0F51, 2),
                 SseOpcode::Sqrtsd => (LegacyPrefixes::_F2, 0x0F51, 2),
+                SseOpcode::Movddup => (LegacyPrefixes::_F2, 0x0F12, 2),
                 _ => unimplemented!("Opcode {:?} not implemented", op),
             };
 
@@ -2199,6 +2229,7 @@ pub(crate) fn emit(
                 AvxOpcode::Vpalignr => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0F),
                 AvxOpcode::Vinsertps => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x21),
                 AvxOpcode::Vshufps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC6),
+                AvxOpcode::Vpblendw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0E),
                 _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
             };
 
@@ -2385,6 +2416,13 @@ pub(crate) fn emit(
                     RegisterOrAmode::Amode(_) => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x10),
                     _ => unreachable!(),
                 },
+
+                AvxOpcode::Vpbroadcastb => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x78),
+                AvxOpcode::Vpbroadcastw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x79),
+                AvxOpcode::Vpbroadcastd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x58),
+                AvxOpcode::Vbroadcastss => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x18),
+                AvxOpcode::Vmovddup => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x12),
+
                 _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
             };
 
@@ -2655,6 +2693,7 @@ pub(crate) fn emit(
                 SseOpcode::Pinsrw => (LegacyPrefixes::_66, 0x0FC4, 2),
                 SseOpcode::Pinsrd => (LegacyPrefixes::_66, 0x0F3A22, 3),
                 SseOpcode::Shufps => (LegacyPrefixes::None, 0x0FC6, 2),
+                SseOpcode::Pblendw => (LegacyPrefixes::_66, 0x0F3A0E, 3),
                 _ => unimplemented!("Opcode {:?} not implemented", op),
             };
             let rex = RexFlags::from(*size);
diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index b7865b21b..84455dc20 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -73,8 +73,6 @@ impl Inst {
             | Inst::CallUnknown { .. }
             | Inst::CheckedSRemSeq { .. }
             | Inst::CheckedSRemSeq8 { .. }
-            | Inst::ValidateSdivDivisor { .. }
-            | Inst::ValidateSdivDivisor64 { .. }
             | Inst::Cmove { .. }
             | Inst::CmpRmiR { .. }
             | Inst::CvtFloatToSintSeq { .. }
@@ -225,6 +223,7 @@ impl Inst {
     pub(crate) fn div(
         size: OperandSize,
         sign: DivSignedness,
+        trap: TrapCode,
         divisor: RegMem,
         dividend_lo: Gpr,
         dividend_hi: Gpr,
@@ -235,6 +234,7 @@ impl Inst {
         Inst::Div {
             size,
             sign,
+            trap,
             divisor: GprMem::new(divisor).unwrap(),
             dividend_lo,
             dividend_hi,
@@ -245,6 +245,7 @@ impl Inst {
 
     pub(crate) fn div8(
         sign: DivSignedness,
+        trap: TrapCode,
         divisor: RegMem,
         dividend: Gpr,
         dst: WritableGpr,
@@ -252,6 +253,7 @@ impl Inst {
         divisor.assert_regclass_is(RegClass::Int);
         Inst::Div8 {
             sign,
+            trap,
             divisor: GprMem::new(divisor).unwrap(),
             dividend,
             dst,
@@ -429,6 +431,7 @@ impl Inst {
         Inst::LoadEffectiveAddress {
             addr: addr.into(),
             dst: WritableGpr::from_writable_reg(dst).unwrap(),
+            size: OperandSize::Size64,
         }
     }
 
@@ -547,10 +550,6 @@ impl Inst {
         Inst::JmpUnknown { target }
     }
 
-    pub(crate) fn trap_if(cc: CC, trap_code: TrapCode) -> Inst {
-        Inst::TrapIf { cc, trap_code }
-    }
-
     /// Choose which instruction to use for loading a register value from memory. For loads smaller
     /// than 64 bits, this method expects a way to extend the value (i.e. [ExtKind::SignExtend],
     /// [ExtKind::ZeroExtend]); loads with no extension necessary will ignore this.
@@ -770,6 +769,7 @@ impl PrettyPrint for Inst {
             Inst::Div {
                 size,
                 sign,
+                trap,
                 divisor,
                 dividend_lo,
                 dividend_hi,
@@ -784,7 +784,7 @@ impl PrettyPrint for Inst {
                 let dst_remainder =
                     pretty_print_reg(dst_remainder.to_reg().to_reg(), size.to_bytes(), allocs);
                 format!(
-                    "{} {}, {}, {}, {}, {}",
+                    "{} {}, {}, {}, {}, {} ; trap={trap}",
                     ljustify(match sign {
                         DivSignedness::Signed => "idiv".to_string(),
                         DivSignedness::Unsigned => "div".to_string(),
@@ -799,6 +799,7 @@ impl PrettyPrint for Inst {
 
             Inst::Div8 {
                 sign,
+                trap,
                 divisor,
                 dividend,
                 dst,
@@ -807,7 +808,7 @@ impl PrettyPrint for Inst {
                 let dividend = pretty_print_reg(dividend.to_reg(), 1, allocs);
                 let dst = pretty_print_reg(dst.to_reg().to_reg(), 1, allocs);
                 format!(
-                    "{} {dividend}, {divisor}, {dst}",
+                    "{} {dividend}, {divisor}, {dst} ; trap={trap}",
                     ljustify(match sign {
                         DivSignedness::Signed => "idiv".to_string(),
                         DivSignedness::Unsigned => "div".to_string(),
@@ -873,27 +874,6 @@ impl PrettyPrint for Inst {
                 format!("checked_srem_seq {dividend}, {divisor}, {dst}")
             }
 
-            Inst::ValidateSdivDivisor {
-                dividend,
-                divisor,
-                size,
-            } => {
-                let dividend = pretty_print_reg(dividend.to_reg(), size.to_bytes(), allocs);
-                let divisor = pretty_print_reg(divisor.to_reg(), size.to_bytes(), allocs);
-                format!("validate_sdiv_divisor {dividend}, {divisor}")
-            }
-
-            Inst::ValidateSdivDivisor64 {
-                dividend,
-                divisor,
-                tmp,
-            } => {
-                let dividend = pretty_print_reg(dividend.to_reg(), 8, allocs);
-                let divisor = pretty_print_reg(divisor.to_reg(), 8, allocs);
-                let tmp = pretty_print_reg(tmp.to_reg().to_reg(), 8, allocs);
-                format!("validate_sdiv_divisor {dividend}, {divisor} {tmp}")
-            }
-
             Inst::SignExtendData { size, src, dst } => {
                 let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
                 let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
@@ -1432,8 +1412,8 @@ impl PrettyPrint for Inst {
                 format!("{} {}, {}", ljustify("movq".to_string()), src, dst)
             }
 
-            Inst::LoadEffectiveAddress { addr, dst } => {
-                let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
+            Inst::LoadEffectiveAddress { addr, dst, size } => {
+                let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
                 let addr = addr.pretty_print(8, allocs);
                 format!("{} {}, {}", ljustify("lea".to_string()), addr, dst)
             }
@@ -1916,21 +1896,6 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
             collector.reg_fixed_def(dst_hi.to_writable_reg(), regs::rdx());
             src2.get_operands(collector);
         }
-        Inst::ValidateSdivDivisor {
-            dividend, divisor, ..
-        } => {
-            collector.reg_use(divisor.to_reg());
-            collector.reg_use(dividend.to_reg());
-        }
-        Inst::ValidateSdivDivisor64 {
-            dividend,
-            divisor,
-            tmp,
-        } => {
-            collector.reg_use(divisor.to_reg());
-            collector.reg_use(dividend.to_reg());
-            collector.reg_early_def(tmp.to_writable_reg());
-        }
         Inst::SignExtendData { size, src, dst } => {
             match size {
                 OperandSize::Size8 => {
@@ -2173,7 +2138,7 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
             collector.reg_def(dst.to_writable_reg());
             src.get_operands(collector);
         }
-        Inst::LoadEffectiveAddress { addr: src, dst } => {
+        Inst::LoadEffectiveAddress { addr: src, dst, .. } => {
             collector.reg_def(dst.to_writable_reg());
             src.get_operands(collector);
         }
diff --git a/cranelift/codegen/src/isa/x64/lower.isle b/cranelift/codegen/src/isa/x64/lower.isle
index b5fcffe48..99adfb7cf 100644
--- a/cranelift/codegen/src/isa/x64/lower.isle
+++ b/cranelift/codegen/src/isa/x64/lower.isle
@@ -41,17 +41,27 @@
 
 ;; `i64` and smaller.
 
-;; Add two registers.
-(rule -5 (lower (has_type (fits_in_64 ty)
+;; Base case for 8 and 16-bit types
+(rule -6 (lower (has_type (fits_in_16 ty)
                        (iadd x y)))
       (x64_add ty x y))
 
-;; The above case handles when the rhs is an immediate or a sinkable load, but
-;; additionally add lhs meets these criteria.
-
+;; Base case for 32 and 64-bit types which might end up using the `lea`
+;; instruction to fold multiple operations into one.
+;;
+;; Note that at this time this always generates a `lea` pseudo-instruction,
+;; but the actual instruction emitted might be an `add` if it's equivalent.
+;; For more details on this see the `emit.rs` logic to emit
+;; `LoadEffectiveAddress`.
+(rule -5 (lower (has_type (ty_32_or_64 ty) (iadd x y)))
+      (x64_lea ty (to_amode_add (mem_flags_trusted) x y (zero_offset))))
+
+;; Higher-priority cases than the previous two where a load can be sunk into
+;; the add instruction itself. Note that both operands are tested for
+;; sink-ability since addition is commutative
 (rule -4 (lower (has_type (fits_in_64 ty)
-                       (iadd (simm32_from_value x) y)))
-      (x64_add ty y x))
+                       (iadd x (sinkable_load y))))
+      (x64_add ty x y))
 (rule -3 (lower (has_type (fits_in_64 ty)
                        (iadd (sinkable_load x) y)))
       (x64_add ty y x))
@@ -442,13 +452,14 @@
 (extern constructor ishl_i8x16_mask_table ishl_i8x16_mask_table)
 (rule (ishl_i8x16_mask (RegMemImm.Reg amt))
       (let ((mask_table SyntheticAmode (ishl_i8x16_mask_table))
-            (base_mask_addr Gpr (x64_lea mask_table))
+            (base_mask_addr Gpr (x64_lea $I64 mask_table))
             (mask_offset Gpr (x64_shl $I64 amt
                                   (imm8_to_imm8_gpr 4))))
-        (amode_imm_reg_reg_shift 0
-                                 base_mask_addr
-                                 mask_offset
-                                 0)))
+        (Amode.ImmRegRegShift 0
+                              base_mask_addr
+                              mask_offset
+                              0
+                              (mem_flags_trusted))))
 
 (rule (ishl_i8x16_mask (RegMemImm.Mem amt))
       (ishl_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
@@ -546,14 +557,15 @@
 (extern constructor ushr_i8x16_mask_table ushr_i8x16_mask_table)
 (rule (ushr_i8x16_mask (RegMemImm.Reg amt))
       (let ((mask_table SyntheticAmode (ushr_i8x16_mask_table))
-            (base_mask_addr Gpr (x64_lea mask_table))
+            (base_mask_addr Gpr (x64_lea $I64 mask_table))
             (mask_offset Gpr (x64_shl $I64
                                   amt
                                   (imm8_to_imm8_gpr 4))))
-        (amode_imm_reg_reg_shift 0
-                                 base_mask_addr
-                                 mask_offset
-                                 0)))
+        (Amode.ImmRegRegShift 0
+                              base_mask_addr
+                              mask_offset
+                              0
+                              (mem_flags_trusted))))
 
 (rule (ushr_i8x16_mask (RegMemImm.Mem amt))
       (ushr_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
@@ -3491,13 +3503,20 @@
 
 ;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;; NB: a `RegMem` divisor, while allowed in the instruction encoding, isn't
+;; used right now to prevent a possibly-trapping load getting folded into the
+;; `div` instruction. Ideally non-trapping loads would get folded, however, or
+;; alternatively Wasmtime/Cranelift would grow support for multiple traps on
+;; a single opcode and the signal kind would differentiate at runtime.
+
 ;; The inputs to the `div` instruction are different for 8-bit division so
 ;; it needs a special case here since the instruction being crafted has a
 ;; different shape.
 (rule 2 (lower (udiv a @ (value_type $I8) b))
         (x64_div8 (extend_to_gpr a $I32 (ExtendKind.Zero))
-                  (nonzero_divisor $I8 b)
-                  (DivSignedness.Unsigned)))
+                  (put_in_gpr b)
+                  (DivSignedness.Unsigned)
+                  (TrapCode.IntegerDivisionByZero)))
 
 ;; 16-to-64-bit division is all done with a similar instruction and the only
 ;; tricky requirement here is that when div traps are disallowed the divisor
@@ -3505,76 +3524,47 @@
 (rule 1 (lower (udiv a @ (value_type (fits_in_64 ty)) b))
         (x64_div_quotient a
                           (imm $I64 0)
-                          (nonzero_divisor ty b)
+                          (put_in_gpr b)
                           (raw_operand_size_of_type ty)
-                          (DivSignedness.Unsigned)))
-
-;; Helper to place `Value` into a `Gpr` while possibly trapping if it's zero.
-;;
-;; If the `avoid_div_traps=true` codegen setting is specified then the value
-;; is checked for zero and a trap happens before the value is returned as a
-;; register here.
-(decl nonzero_divisor (Type Value) Gpr)
-
-;; As a special-case if the divisor is a constant number which is nonzero then
-;; no matter what there's no checks necessary.
-(rule 2 (nonzero_divisor ty (iconst (u64_from_imm64 (u64_nonzero n))))
-        (imm ty n))
-
-;; No checks necessary when `avoid_div_traps=false`
-(rule 1 (nonzero_divisor ty val)
-        (if-let $false (avoid_div_traps))
-        val)
-
-;; Base case traps if `val` is zero by using a `test` + `trap_if` combo
-(rule (nonzero_divisor ty val)
-      (let (
-          (val Reg val)
-          (_ InstOutput (side_effect (with_flags_side_effect
-            (x64_test (raw_operand_size_of_type ty) val val)
-            (trap_if (CC.Z) (TrapCode.IntegerDivisionByZero)))))
-        )
-        val))
+                          (DivSignedness.Unsigned)
+                          (TrapCode.IntegerDivisionByZero)))
 
 ;; Rules for `sdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule 2 (lower (sdiv a @ (value_type $I8) b))
-        (let (
-            (a Gpr (x64_sign_extend_data a (OperandSize.Size8)))
-          )
-          (x64_div8 a (safe_sdiv_divisor $I8 a b) (DivSignedness.Signed))))
+        (x64_div8 (x64_sign_extend_data a (OperandSize.Size8))
+                  (nonzero_sdiv_divisor $I8 b)
+                  (DivSignedness.Signed)
+                  (TrapCode.IntegerOverflow)))
 
 (rule 1 (lower (sdiv a @ (value_type (fits_in_64 ty)) b))
         (let (
             (a Gpr a)
             (size OperandSize (raw_operand_size_of_type ty))
-            (b Gpr (safe_sdiv_divisor ty a b))
           )
-          (x64_div_quotient a (x64_sign_extend_data a size) b size (DivSignedness.Signed))))
-
-;; Similar to `nonzero_divisor` except this checks to make sure that the divisor
-;; provided as a `Value` is safe to divide into the dividend `Gpr` provided.
-(decl safe_sdiv_divisor (Type Gpr Value) Reg)
+        (x64_div_quotient a
+                          (x64_sign_extend_data a size)
+                          (nonzero_sdiv_divisor ty b)
+                          size
+                          (DivSignedness.Signed)
+                          (TrapCode.IntegerOverflow))))
 
-;; If the divisor is a constant that isn't 0 or -1, then it's always safe so
-;; materialize it into a register.
-(rule 3 (safe_sdiv_divisor ty a (iconst imm))
+;; Checks to make sure that the input `Value` is a non-zero value for `sdiv`.
+;;
+;; This is required to differentiate the divide-by-zero trap from the
+;; integer-overflow trap, the two trapping conditions of signed division.
+(decl nonzero_sdiv_divisor (Type Value) Reg)
+(rule 1 (nonzero_sdiv_divisor ty (iconst imm))
         (if-let n (safe_divisor_from_imm64 ty imm))
         (imm ty n))
-
-;; With `avoid_div_traps=false` the divisor can be plumbed through.
-;;
-;; Note that CLIF semantics dictate that division-by-zero and INT_MIN/-1 both
-;; trap, but this matches the hardware semantics of `idiv` on x64 so they're
-;; fine to get plumbed through as-is.
-(rule 2 (safe_sdiv_divisor ty a b)
-        (if-let $false (avoid_div_traps))
-        b)
-
-;; The base cases here rely on some pseudo-instructions to do the checks to
-;; jump around with labels and such.
-(rule 1 (safe_sdiv_divisor $I64 a b) (validate_sdiv_divisor64 a b))
-(rule 0 (safe_sdiv_divisor ty a b) (validate_sdiv_divisor (raw_operand_size_of_type ty) a b))
+(rule 0 (nonzero_sdiv_divisor ty val)
+      (let (
+          (val Reg val)
+          (_ InstOutput (side_effect (with_flags_side_effect
+            (x64_test (raw_operand_size_of_type ty) val val)
+            (trap_if (CC.Z) (TrapCode.IntegerDivisionByZero)))))
+        )
+        val))
 
 ;; Rules for `urem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -3582,18 +3572,20 @@
 ;; by 8.
 (rule 2 (lower (urem a @ (value_type $I8) b))
         (let (
-            (a Gpr (extend_to_gpr a $I32 (ExtendKind.Zero)))
-            (b Gpr (nonzero_divisor $I8 b))
-            (result Gpr (x64_div8 a b (DivSignedness.Unsigned)))
+            (result Gpr (x64_div8 (extend_to_gpr a $I32 (ExtendKind.Zero))
+                                  (put_in_gpr b) ;; see `udiv` for why not `gpr_mem`
+                                  (DivSignedness.Unsigned)
+                                  (TrapCode.IntegerDivisionByZero)))
           )
           (x64_shr $I64 result (Imm8Reg.Imm8 8))))
 
 (rule 1 (lower (urem a @ (value_type (fits_in_64 ty)) b))
         (x64_div_remainder a
                            (imm $I64 0)
-                           (nonzero_divisor ty b)
+                           (put_in_gpr b) ;; see `udiv` for why not `gpr_mem`
                            (raw_operand_size_of_type ty)
-                           (DivSignedness.Unsigned)))
+                           (DivSignedness.Unsigned)
+                           (TrapCode.IntegerDivisionByZero)))
 
 ;; Rules for `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -3606,7 +3598,7 @@
         (if-let n (safe_divisor_from_imm64 $I8 imm))
         (let (
             (a Gpr (x64_sign_extend_data a (OperandSize.Size8)))
-            (result Gpr (x64_div8 a (imm $I8 n) (DivSignedness.Signed)))
+            (result Gpr (x64_div8 a (imm $I8 n) (DivSignedness.Signed) (TrapCode.IntegerDivisionByZero)))
           )
           (x64_shr $I64 result (Imm8Reg.Imm8 8))))
 
@@ -3621,19 +3613,18 @@
                              (x64_sign_extend_data a size)
                              (imm ty n)
                              size
-                             (DivSignedness.Signed))))
+                             (DivSignedness.Signed)
+                             (TrapCode.IntegerDivisionByZero))))
 
 (rule 1 (lower (srem a @ (value_type $I8) b))
         (let (
             (a Gpr (x64_sign_extend_data a (OperandSize.Size8)))
-            (b Gpr (nonzero_divisor $I8 b))
           )
           (x64_shr $I64 (x64_checked_srem_seq8 a b) (Imm8Reg.Imm8 8))))
 
 (rule (lower (srem a @ (value_type ty) b))
       (let (
           (a Gpr a)
-          (b Gpr (nonzero_divisor ty b))
           (size OperandSize (raw_operand_size_of_type ty))
           (hi Gpr (x64_sign_extend_data a size))
           (tmp ValueRegs (x64_checked_srem_seq size a hi b))
@@ -3692,6 +3683,15 @@
 
 ;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;; Special case for `pblendw` which takes an 8-bit immediate where each bit
+;; indicates which lane of the two operands is chosen for the output. A bit of
+;; 0 chooses the corresponding 16-it lane from `a` and a bit of 1 chooses the
+;; corresponding 16-bit lane from `b`.
+(rule 14 (lower (shuffle a b (pblendw_imm n)))
+         (x64_pblendw a b n))
+(decl pblendw_imm (u8) Immediate)
+(extern extractor pblendw_imm pblendw_imm)
+
 ;; When the shuffle looks like "concatenate `a` and `b` and shift right by n*8
 ;; bytes", that's a `palignr` instruction. Note that the order of operands are
 ;; swapped in the instruction here. The `palignr` instruction uses the second
@@ -3894,47 +3894,89 @@
 
 ;; Rules for `splat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(rule (lower (has_type (multi_lane 8 16) (splat src)))
-      (let ((vec Xmm (vec_insert_lane $I8X16 (xmm_uninit_value) src 0))
-            (zeros Xmm (xmm_zero $I8X16)))
-        ;; Shuffle the lowest byte lane to all other lanes.
-        (x64_pshufb vec zeros)))
-
-(rule (lower (has_type (multi_lane 16 8) (splat src)))
-      (let (;; Force the input into a register so that we don't create a
-            ;; VCodeConstant.
-            (src RegMem (RegMem.Reg src))
-            (vec Xmm (vec_insert_lane $I16X8 (xmm_uninit_value) src 0))
-            (vec Xmm (vec_insert_lane $I16X8 vec src 1)))
-        ;; Shuffle the lowest two lanes to all other lanes.
-        (x64_pshufd vec 0)))
-
-(rule 1 (lower (has_type (multi_lane 32 4) (splat src @ (value_type (ty_scalar_float _)))))
-      (lower_splat_32x4 $F32X4 src))
-
-(rule (lower (has_type (multi_lane 32 4) (splat src)))
-      (lower_splat_32x4 $I32X4 src))
-
-(decl lower_splat_32x4 (Type Value) Xmm)
-(rule (lower_splat_32x4 ty src)
-      (let ((src RegMem src)
-            (vec Xmm (vec_insert_lane ty (xmm_uninit_value) src 0)))
-        ;; Shuffle the lowest lane to all other lanes.
-        (x64_pshufd vec 0)))
-
-(rule 1 (lower (has_type (multi_lane 64 2) (splat src @ (value_type (ty_scalar_float _)))))
-      (lower_splat_64x2 $F64X2 src))
-
-(rule (lower (has_type (multi_lane 64 2) (splat src)))
-      (lower_splat_64x2 $I64X2 src))
-
-(decl lower_splat_64x2 (Type Value) Xmm)
-(rule (lower_splat_64x2 ty src)
-      (let (;; Force the input into a register so that we don't create a
-            ;; VCodeConstant.
-            (src RegMem (RegMem.Reg src))
-            (vec Xmm (vec_insert_lane ty (xmm_uninit_value) src 0)))
-        (vec_insert_lane ty vec src 1)))
+;; For all the splat rules below one of the goals is that splatting a value
+;; doesn't end up accidentally depending on the previous value in a register.
+;; This means that instructions are chosen to avoid false dependencies where
+;; new values are created fresh or otherwise overwrite previous register
+;; contents where possible.
+;;
+;; Additionally splats are specialized to special-case load-and-splat which
+;; has a number of micro-optimizations available.
+
+;; i8x16 splats: use `vpbroadcastb` on AVX2 and otherwise `pshufb` broadcasts
+;; with a mask of zero which is calculated with an xor-against-itself register.
+(rule 0 (lower (has_type $I8X16 (splat src)))
+        (x64_pshufb (bitcast_gpr_to_xmm $I32 src) (xmm_zero $I8X16)))
+(rule 1 (lower (has_type $I8X16 (splat src)))
+        (if-let $true (has_avx2))
+        (x64_vpbroadcastb (bitcast_gpr_to_xmm $I32 src)))
+(rule 2 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
+        (x64_pshufb (x64_pinsrb (xmm_uninit_value) addr 0) (xmm_zero $I8X16)))
+(rule 3 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
+        (if-let $true (has_avx2))
+        (x64_vpbroadcastb addr))
+
+;; i16x8 splats: use `vpbroadcastw` on AVX2 and otherwise a 16-bit value is
+;; loaded into an xmm register, `pshuflw` broadcasts the low 16-bit lane
+;; to the low four lanes, and `pshufd` broadcasts the low 32-bit lane (which
+;; at that point is two of the 16-bit values we want to broadcast) to all the
+;; lanes.
+(rule 0 (lower (has_type $I16X8 (splat src)))
+        (x64_pshufd (x64_pshuflw (bitcast_gpr_to_xmm $I32 src) 0) 0))
+(rule 1 (lower (has_type $I16X8 (splat src)))
+        (if-let $true (has_avx2))
+        (x64_vpbroadcastw (bitcast_gpr_to_xmm $I32 src)))
+(rule 2 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
+        (x64_pshufd (x64_pshuflw (x64_pinsrw (xmm_uninit_value) addr 0) 0) 0))
+(rule 3 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
+        (if-let $true (has_avx2))
+        (x64_vpbroadcastw addr))
+
+;; i32x4.splat - use `vpbroadcastd` on AVX2 and otherwise `pshufd` can be
+;; used to broadcast the low lane to all other lanes.
+;;
+;; Note that sinkable-load cases come later
+(rule 0 (lower (has_type $I32X4 (splat src)))
+        (x64_pshufd (bitcast_gpr_to_xmm $I32 src) 0))
+(rule 1 (lower (has_type $I32X4 (splat src)))
+        (if-let $true (has_avx2))
+        (x64_vpbroadcastd (bitcast_gpr_to_xmm $I32 src)))
+
+;; f32x4.splat - the source is already in an xmm register so `shufps` is all
+;; that's necessary to complete the splat. This is specialized to `vbroadcastss`
+;; on AVX2 to leverage that specific instruction for this operation.
+(rule 0 (lower (has_type $F32X4 (splat src)))
+        (let ((tmp Xmm src))
+          (x64_shufps src src 0)))
+(rule 1 (lower (has_type $F32X4 (splat src)))
+        (if-let $true (has_avx2))
+        (x64_vbroadcastss src))
+
+;; t32x4.splat of a load - use a `movss` to load into an xmm register and then
+;; `shufps` broadcasts to the other lanes. Note that this is used for both i32
+;; and f32 splats.
+;;
+;; With AVX the `vbroadcastss` instruction suits this purpose precisely. Note
+;; that the memory-operand encoding of `vbroadcastss` is usable with AVX, but
+;; the register-based encoding is only available with AVX2. With the
+;; `sinkable_load` extractor this should be guaranteed to use the memory-based
+;; encoding hence the `has_avx` test.
+(rule 4 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
+        (let ((tmp Xmm (x64_movss_load addr)))
+          (x64_shufps tmp tmp 0)))
+(rule 5 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
+        (if-let $true (has_avx))
+        (x64_vbroadcastss addr))
+
+;; t64x2.splat - use `movddup` which is exactly what we want and there's a
+;; minor specialization for sinkable loads to avoid going through a gpr for i64
+;; splats
+(rule 0 (lower (has_type $I64X2 (splat src)))
+        (x64_movddup (bitcast_gpr_to_xmm $I64 src)))
+(rule 0 (lower (has_type $F64X2 (splat src)))
+        (x64_movddup src))
+(rule 5 (lower (has_type (multi_lane 64 2) (splat (sinkable_load addr))))
+        (x64_movddup addr))
 
 ;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 868d0860e..bd3b6e8dc 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -70,26 +70,42 @@ fn put_input_in_reg(ctx: &mut Lower<Inst>, spec: InsnInput) -> Reg {
         .expect("Multi-register value not expected")
 }
 
+enum MergeableLoadSize {
+    /// The load size performed by a sinkable load merging operation is
+    /// precisely the size necessary for the type in question.
+    Exact,
+
+    /// Narrower-than-32-bit values are handled by ALU insts that are at least
+    /// 32 bits wide, which is normally OK as we ignore upper buts; but, if we
+    /// generate, e.g., a direct-from-memory 32-bit add for a byte value and
+    /// the byte is the last byte in a page, the extra data that we load is
+    /// incorrectly accessed. So we only allow loads to merge for
+    /// 32-bit-and-above widths.
+    Min32,
+}
+
 /// Determines whether a load operation (indicated by `src_insn`) can be merged
 /// into the current lowering point. If so, returns the address-base source (as
 /// an `InsnInput`) and an offset from that address from which to perform the
 /// load.
-fn is_mergeable_load(ctx: &mut Lower<Inst>, src_insn: IRInst) -> Option<(InsnInput, i32)> {
+fn is_mergeable_load(
+    ctx: &mut Lower<Inst>,
+    src_insn: IRInst,
+    size: MergeableLoadSize,
+) -> Option<(InsnInput, i32)> {
     let insn_data = ctx.data(src_insn);
     let inputs = ctx.num_inputs(src_insn);
     if inputs != 1 {
         return None;
     }
 
+    // If this type is too small to get a merged load, don't merge the load.
     let load_ty = ctx.output_ty(src_insn, 0);
     if ty_bits(load_ty) < 32 {
-        // Narrower values are handled by ALU insts that are at least 32 bits
-        // wide, which is normally OK as we ignore upper buts; but, if we
-        // generate, e.g., a direct-from-memory 32-bit add for a byte value and
-        // the byte is the last byte in a page, the extra data that we load is
-        // incorrectly accessed. So we only allow loads to merge for
-        // 32-bit-and-above widths.
-        return None;
+        match size {
+            MergeableLoadSize::Exact => {}
+            MergeableLoadSize::Min32 => return None,
+        }
     }
 
     // Just testing the opcode is enough, because the width will always match if
diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs
index 4d0a96015..904b67a88 100644
--- a/cranelift/codegen/src/isa/x64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/x64/lower/isle.rs
@@ -11,7 +11,7 @@ use crate::{isle_common_prelude_methods, isle_lower_prelude_methods};
 use generated_code::{Context, MInst, RegisterClass};
 
 // Types that the generated ISLE code uses via `use super::*`.
-use super::{is_int_or_ref_ty, is_mergeable_load, lower_to_amode};
+use super::{is_int_or_ref_ty, is_mergeable_load, lower_to_amode, MergeableLoadSize};
 use crate::ir::LibCall;
 use crate::isa::x64::lower::emit_vm_call;
 use crate::isa::x64::X64Backend;
@@ -174,6 +174,11 @@ impl Context for IsleContext<'_, '_, MInst, X64Backend> {
         self.backend.x64_flags.has_avx()
     }
 
+    #[inline]
+    fn has_avx2(&mut self) -> bool {
+        self.backend.x64_flags.has_avx2()
+    }
+
     #[inline]
     fn avx512vl_enabled(&mut self, _: Type) -> bool {
         self.backend.x64_flags.use_avx512vl_simd()
@@ -268,7 +273,25 @@ impl Context for IsleContext<'_, '_, MInst, X64Backend> {
     fn sinkable_load(&mut self, val: Value) -> Option<SinkableLoad> {
         let input = self.lower_ctx.get_value_as_source_or_const(val);
         if let InputSourceInst::UniqueUse(inst, 0) = input.inst {
-            if let Some((addr_input, offset)) = is_mergeable_load(self.lower_ctx, inst) {
+            if let Some((addr_input, offset)) =
+                is_mergeable_load(self.lower_ctx, inst, MergeableLoadSize::Min32)
+            {
+                return Some(SinkableLoad {
+                    inst,
+                    addr_input,
+                    offset,
+                });
+            }
+        }
+        None
+    }
+
+    fn sinkable_load_exact(&mut self, val: Value) -> Option<SinkableLoad> {
+        let input = self.lower_ctx.get_value_as_source_or_const(val);
+        if let InputSourceInst::UniqueUse(inst, 0) = input.inst {
+            if let Some((addr_input, offset)) =
+                is_mergeable_load(self.lower_ctx, inst, MergeableLoadSize::Exact)
+            {
                 return Some(SinkableLoad {
                     inst,
                     addr_input,
@@ -315,21 +338,6 @@ impl Context for IsleContext<'_, '_, MInst, X64Backend> {
         RegMem::mem(addr.clone())
     }
 
-    #[inline]
-    fn amode_imm_reg_reg_shift(&mut self, simm32: u32, base: Gpr, index: Gpr, shift: u8) -> Amode {
-        Amode::imm_reg_reg_shift(simm32, base, index, shift)
-    }
-
-    #[inline]
-    fn amode_imm_reg(&mut self, simm32: u32, base: Gpr) -> Amode {
-        Amode::imm_reg(simm32, base.to_reg())
-    }
-
-    #[inline]
-    fn amode_with_flags(&mut self, amode: &Amode, flags: MemFlags) -> Amode {
-        amode.with_flags(flags)
-    }
-
     #[inline]
     fn amode_to_synthetic_amode(&mut self, amode: &Amode) -> SyntheticAmode {
         amode.clone().into()
@@ -995,6 +1003,41 @@ impl Context for IsleContext<'_, '_, MInst, X64Backend> {
             None
         }
     }
+
+    fn pblendw_imm(&mut self, imm: Immediate) -> Option<u8> {
+        // First make sure that the shuffle immediate is selecting 16-bit lanes.
+        let (a, b, c, d, e, f, g, h) = self.shuffle16_from_imm(imm)?;
+
+        // Next build up an 8-bit mask from each of the bits of the selected
+        // lanes above. This instruction can only be used when each lane
+        // selector chooses from the corresponding lane in either of the two
+        // operands, meaning the Nth lane selection must satisfy `lane % 8 ==
+        // N`.
+        //
+        // This helper closure is used to calculate the value of the
+        // corresponding bit.
+        let bit = |x: u8, c: u8| {
+            if x % 8 == c {
+                if x < 8 {
+                    Some(0)
+                } else {
+                    Some(1 << c)
+                }
+            } else {
+                None
+            }
+        };
+        Some(
+            bit(a, 0)?
+                | bit(b, 1)?
+                | bit(c, 2)?
+                | bit(d, 3)?
+                | bit(e, 4)?
+                | bit(f, 5)?
+                | bit(g, 6)?
+                | bit(h, 7)?,
+        )
+    }
 }
 
 impl IsleContext<'_, '_, MInst, X64Backend> {
diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs
index 9d78044b3..cf0caac32 100644
--- a/cranelift/codegen/src/isle_prelude.rs
+++ b/cranelift/codegen/src/isle_prelude.rs
@@ -648,6 +648,11 @@ macro_rules! isle_common_prelude_methods {
             offset as u32
         }
 
+        #[inline]
+        fn u32_to_offset32(&mut self, offset: u32) -> Offset32 {
+            Offset32::new(offset as i32)
+        }
+
         fn range(&mut self, start: usize, end: usize) -> Range {
             (start, end)
         }
diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs
index 6fa43e055..c226f0cb5 100644
--- a/cranelift/codegen/src/legalizer/mod.rs
+++ b/cranelift/codegen/src/legalizer/mod.rs
@@ -82,8 +82,10 @@ pub fn simple_legalize(func: &mut ir::Function, cfg: &mut ControlFlowGraph, isa:
 
                     let addr = pos.ins().stack_addr(addr_ty, stack_slot, offset);
 
-                    // Stack slots are required to be accessible and aligned.
-                    let mflags = MemFlags::trusted();
+                    // Stack slots are required to be accessible.
+                    // We can't currently ensure that they are aligned.
+                    let mut mflags = MemFlags::new();
+                    mflags.set_notrap();
                     pos.func.dfg.replace(inst).load(ty, mflags, addr, 0);
                 }
                 InstructionData::StackStore {
@@ -99,10 +101,10 @@ pub fn simple_legalize(func: &mut ir::Function, cfg: &mut ControlFlowGraph, isa:
 
                     let addr = pos.ins().stack_addr(addr_ty, stack_slot, offset);
 
+                    // Stack slots are required to be accessible.
+                    // We can't currently ensure that they are aligned.
                     let mut mflags = MemFlags::new();
-                    // Stack slots are required to be accessible and aligned.
                     mflags.set_notrap();
-                    mflags.set_aligned();
                     pos.func.dfg.replace(inst).store(mflags, arg, addr, 0);
                 }
                 InstructionData::DynamicStackLoad {
diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs
index ca39d0feb..867102c32 100644
--- a/cranelift/codegen/src/machinst/isle.rs
+++ b/cranelift/codegen/src/machinst/isle.rs
@@ -285,10 +285,6 @@ macro_rules! isle_lower_prelude_methods {
             }
         }
 
-        fn avoid_div_traps(&mut self) -> bool {
-            self.backend.flags().avoid_div_traps()
-        }
-
         #[inline]
         fn tls_model(&mut self, _: Type) -> TlsModel {
             self.backend.flags().tls_model()
diff --git a/cranelift/codegen/src/prelude.isle b/cranelift/codegen/src/prelude.isle
index 4815cf635..ef2741570 100644
--- a/cranelift/codegen/src/prelude.isle
+++ b/cranelift/codegen/src/prelude.isle
@@ -439,6 +439,10 @@
 (decl pure offset32_to_u32 (Offset32) u32)
 (extern constructor offset32_to_u32 offset32_to_u32)
 
+;; Convert a number to an `Offset32`
+(decl pure u32_to_offset32 (u32) Offset32)
+(extern constructor u32_to_offset32 u32_to_offset32)
+
 ;; This is a direct import of `IntCC::unsigned`.
 ;; Get the corresponding IntCC with the signed component removed.
 ;; For conditions without a signed component, this is a no-op.
@@ -491,3 +495,4 @@
 ;;;; Automatic conversions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (convert Offset32 u32 offset32_to_u32)
+(convert u32 Offset32 u32_to_offset32)
diff --git a/cranelift/codegen/src/prelude_lower.isle b/cranelift/codegen/src/prelude_lower.isle
index 8db2f7355..eab34154e 100644
--- a/cranelift/codegen/src/prelude_lower.isle
+++ b/cranelift/codegen/src/prelude_lower.isle
@@ -530,9 +530,6 @@
 
 ;;;; Helpers for accessing compilation flags ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(decl pure avoid_div_traps () bool)
-(extern constructor avoid_div_traps avoid_div_traps)
-
 ;; This definition should be kept up to date with the values defined in
 ;; cranelift/codegen/meta/src/shared/settings.rs
 (type TlsModel extern (enum (None) (ElfGd) (Macho) (Coff)))
diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs
index 5485779de..44d2504df 100644
--- a/cranelift/codegen/src/settings.rs
+++ b/cranelift/codegen/src/settings.rs
@@ -532,7 +532,6 @@ use_egraphs = true
 enable_verifier = true
 is_pic = false
 use_colocated_libcalls = false
-avoid_div_traps = false
 enable_float = true
 enable_nan_canonicalization = false
 enable_pinned_reg = false
diff --git a/crates/cranelift-shared/src/isa_builder.rs b/crates/cranelift-shared/src/isa_builder.rs
index d15abe992..ad16bb8e8 100644
--- a/crates/cranelift-shared/src/isa_builder.rs
+++ b/crates/cranelift-shared/src/isa_builder.rs
@@ -23,12 +23,6 @@ impl<T> IsaBuilder<T> {
     pub fn new(lookup: fn(Triple) -> Result<Builder<T>>) -> Self {
         let mut flags = settings::builder();
 
-        // There are two possible traps for division, and this way
-        // we get the proper one if code traps.
-        flags
-            .enable("avoid_div_traps")
-            .expect("should be valid flag");
-
         // We don't use probestack as a stack limit mechanism
         flags
             .set("enable_probestack", "false")
diff --git a/crates/runtime/src/traphandlers/macos.rs b/crates/runtime/src/traphandlers/macos.rs
index b8047e03a..da2cdac91 100644
--- a/crates/runtime/src/traphandlers/macos.rs
+++ b/crates/runtime/src/traphandlers/macos.rs
@@ -244,7 +244,7 @@ unsafe fn handle_exception(request: &mut ExceptionRequest) -> bool {
     // First make sure that this exception is one that we actually expect to
     // get raised by wasm code. All other exceptions we safely ignore.
     match request.body.exception as u32 {
-        EXC_BAD_ACCESS | EXC_BAD_INSTRUCTION => {}
+        EXC_BAD_ACCESS | EXC_BAD_INSTRUCTION | EXC_ARITHMETIC => {}
         _ => return false,
     }
 
@@ -424,7 +424,7 @@ pub fn lazy_per_thread_init() {
         let this_thread = mach_thread_self();
         let kret = thread_set_exception_ports(
             this_thread,
-            EXC_MASK_BAD_ACCESS | EXC_MASK_BAD_INSTRUCTION,
+            EXC_MASK_BAD_ACCESS | EXC_MASK_BAD_INSTRUCTION | EXC_MASK_ARITHMETIC,
             WASMTIME_PORT,
             EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES,
             mach_addons::THREAD_STATE_NONE,
diff --git a/crates/wasmtime/src/engine.rs b/crates/wasmtime/src/engine.rs
index 9523278f5..de7ba922d 100644
--- a/crates/wasmtime/src/engine.rs
+++ b/crates/wasmtime/src/engine.rs
@@ -350,7 +350,7 @@ impl Engine {
     /// currently rely on the compiler informing us of all settings, including
     /// those disabled. Settings then fall in a few buckets:
     ///
-    /// * Some settings must be enabled, such as `avoid_div_traps`.
+    /// * Some settings must be enabled, such as `preserve_frame_pointers`.
     /// * Some settings must have a particular value, such as
     ///   `libcall_call_conv`.
     /// * Some settings do not matter as to their value, such as `opt_level`.
@@ -364,7 +364,6 @@ impl Engine {
             // These settings must all have be enabled, since their value
             // can affect the way the generated code performs or behaves at
             // runtime.
-            "avoid_div_traps" => *value == FlagValue::Bool(true),
             "libcall_call_conv" => *value == FlagValue::Enum("isa_default".into()),
             "preserve_frame_pointers" => *value == FlagValue::Bool(true),
             "enable_probestack" => *value == FlagValue::Bool(crate::config::probestack_supported(target.architecture)),
diff --git a/crates/wasmtime/src/engine/serialization.rs b/crates/wasmtime/src/engine/serialization.rs
index 36063b495..f8b2f83e8 100644
--- a/crates/wasmtime/src/engine/serialization.rs
+++ b/crates/wasmtime/src/engine/serialization.rs
@@ -489,9 +489,10 @@ mod test {
         let engine = Engine::default();
         let mut metadata = Metadata::new(&engine);
 
-        metadata
-            .shared_flags
-            .insert("avoid_div_traps".to_string(), FlagValue::Bool(false));
+        metadata.shared_flags.insert(
+            "preserve_frame_pointers".to_string(),
+            FlagValue::Bool(false),
+        );
 
         match metadata.check_compatible(&engine) {
             Ok(_) => unreachable!(),
@@ -500,7 +501,7 @@ mod test {
 compilation settings of module incompatible with native host
 
 Caused by:
-    setting \"avoid_div_traps\" is configured to Bool(false) which is not supported"
+    setting \"preserve_frame_pointers\" is configured to Bool(false) which is not supported"
             )),
         }
 
diff --git a/supply-chain/config.toml b/supply-chain/config.toml
index e8eb3e2b8..6d2b34dc6 100644
--- a/supply-chain/config.toml
+++ b/supply-chain/config.toml
@@ -1,6 +1,9 @@
 
 # cargo-vet config file
 
+[cargo-vet]
+version = "0.5"
+
 [imports.chromeos]
 url = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/main/cargo-vet/audits.toml?format=TEXT"
 
diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock
index c4bc9af4d..e2e66717c 100644
--- a/supply-chain/imports.lock
+++ b/supply-chain/imports.lock
@@ -15,68 +15,19 @@ user-id = 696
 user-login = "fitzgen"
 user-name = "Nick Fitzgerald"
 
-[audits.chromeos.criteria.crypto-safe]
-description = """
-All crypto algorithms in this crate have been reviewed by a relevant expert.
-
-**Note**: If a crate does not implement crypto, use `does-not-implement-crypto`,
-which implies `crypto-safe`, but does not require expert review in order to
-audit for."""
-
-[audits.chromeos.criteria.does-not-implement-crypto]
-description = """
-Inspection reveals that the crate in question does not attempt to implement any
-cryptographic algorithms on its own.
-
-Note that certification of this does not require an expert on all forms of
-cryptography: it's expected for crates we import to be \"good enough\" citizens,
-so they'll at least be forthcoming if they try to implement something
-cryptographic. When in doubt, please ask an expert."""
-implies = "crypto-safe"
-
-[audits.chromeos.criteria.rule-of-two-safe-to-deploy]
-description = """
-This is a stronger requirement than the built-in safe-to-deploy criteria,
-motivated by Chromium's rule-of-two related requirements:
-https://chromium.googlesource.com/chromium/src/+/master/docs/security/rule-of-2.md#unsafe-code-in-safe-languages
-
-This crate will not introduce a serious security vulnerability to production
-software exposed to untrusted input.
-
-Auditors are not required to perform a full logic review of the entire crate.
-Rather, they must review enough to fully reason about the behavior of all unsafe
-blocks and usage of powerful imports. For any reasonable usage of the crate in
-real-world software, an attacker must not be able to manipulate the runtime
-behavior of these sections in an exploitable or surprising way.
-
-Ideally, ambient capabilities (e.g. filesystem access) are hardened against
-manipulation and consistent with the advertised behavior of the crate. However,
-some discretion is permitted. In such cases, the nature of the discretion should
-be recorded in the `notes` field of the audit record.
-
-Any unsafe code in this crate must, in general, be kept well-contained, and
-documentation must exist to describe how Rust's invariants are being upheld
-despite the unsafe block(s). Nontrivial uses of unsafe must be reviewed by an
-expert in Rust's unsafety guarantees/non-guarantees.
-
-For crates which generate deployed code (e.g. build dependencies or procedural
-macros), reasonable usage of the crate should output code which meets the above
-criteria."""
-implies = "safe-to-deploy"
-
 [[audits.chromeos.audits.libfuzzer-sys]]
 who = "ChromeOS"
-criteria = ["safe-to-run", "does-not-implement-crypto"]
+criteria = "safe-to-run"
 version = "0.4.4"
 
 [[audits.chromeos.audits.miniz_oxide]]
 who = "George Burgess IV <gbiv@google.com>"
-criteria = ["safe-to-run", "does-not-implement-crypto"]
+criteria = "safe-to-run"
 version = "0.6.2"
 
 [[audits.chromeos.audits.static_assertions]]
 who = "ChromeOS"
-criteria = ["safe-to-run", "does-not-implement-crypto"]
+criteria = "safe-to-run"
 version = "1.1.0"
 
 [[audits.embark-studios.audits.anyhow]]
diff --git a/winch/codegen/src/isa/x64/asm.rs b/winch/codegen/src/isa/x64/asm.rs
index f60dde22d..c6a2548c8 100644
--- a/winch/codegen/src/isa/x64/asm.rs
+++ b/winch/codegen/src/isa/x64/asm.rs
@@ -282,34 +282,13 @@ impl Assembler {
     /// caller has correctly allocated the dividend as `(rdx:rax)` and
     /// accounted for the quotient to be stored in `rax`.
     pub fn div(&mut self, divisor: Reg, dst: (Reg, Reg), kind: DivKind, size: OperandSize) {
-        match kind {
-            // Signed division goes through a pseudo-instruction to validate
-            // the divisor followed by a sign extension to initialize `rdx`.
+        let trap = match kind {
+            // Signed division has two trapping conditions, integer overflow and
+            // divide-by-zero. Check for divide-by-zero explicitly and let the
+            // hardware detect overflow.
+            //
+            // The dividend is sign extended to initialize `rdx`.
             DivKind::Signed => {
-                if size == OperandSize::S64 {
-                    self.emit(Inst::ValidateSdivDivisor64 {
-                        dividend: dst.0.into(),
-                        divisor: divisor.into(),
-                        tmp: regs::scratch().into(),
-                    });
-                } else {
-                    self.emit(Inst::ValidateSdivDivisor {
-                        dividend: dst.0.into(),
-                        divisor: divisor.into(),
-                        size: size.into(),
-                    });
-                }
-                self.emit(Inst::SignExtendData {
-                    size: size.into(),
-                    src: dst.0.into(),
-                    dst: dst.1.into(),
-                });
-            }
-
-            // Unsigned division only needs to check for 0 and then the `rdx`
-            // divisor_hi is initialized with zero through an xor-against-itself
-            // op.
-            DivKind::Unsigned => {
                 self.emit(Inst::CmpRmiR {
                     size: size.into(),
                     src: GprMemImm::new(RegMemImm::imm(0)).unwrap(),
@@ -320,6 +299,20 @@ impl Assembler {
                     cc: CC::Z,
                     trap_code: TrapCode::IntegerDivisionByZero,
                 });
+                self.emit(Inst::SignExtendData {
+                    size: size.into(),
+                    src: dst.0.into(),
+                    dst: dst.1.into(),
+                });
+                TrapCode::IntegerOverflow
+            }
+
+            // Unsigned division only traps in one case, on divide-by-zero, so
+            // defer that to the trap opcode.
+            //
+            // The divisor_hi reg is initialized with zero through an
+            // xor-against-itself op.
+            DivKind::Unsigned => {
                 self.emit(Inst::AluRmiR {
                     size: size.into(),
                     op: AluRmiROpcode::Xor,
@@ -327,11 +320,13 @@ impl Assembler {
                     src2: dst.1.into(),
                     dst: dst.1.into(),
                 });
+                TrapCode::IntegerDivisionByZero
             }
-        }
+        };
         self.emit(Inst::Div {
             sign: kind.into(),
             size: size.into(),
+            trap,
             divisor: GprMem::new(RegMem::reg(divisor.into())).unwrap(),
             dividend_lo: dst.0.into(),
             dividend_hi: dst.1.into(),
@@ -348,17 +343,6 @@ impl Assembler {
     /// caller has correctly allocated the dividend as `(rdx:rax)` and
     /// accounted for the remainder to be stored in `rdx`.
     pub fn rem(&mut self, divisor: Reg, dst: (Reg, Reg), kind: RemKind, size: OperandSize) {
-        // First check for zero and explicitly trap.
-        self.emit(Inst::CmpRmiR {
-            size: size.into(),
-            src: GprMemImm::new(RegMemImm::imm(0)).unwrap(),
-            dst: divisor.into(),
-            opcode: CmpOpcode::Cmp,
-        });
-        self.emit(Inst::TrapIf {
-            cc: CC::Z,
-            trap_code: TrapCode::IntegerDivisionByZero,
-        });
         match kind {
             // Signed remainder goes through a pseudo-instruction which has
             // some internal branching. The `dividend_hi`, or `rdx`, is
@@ -391,6 +375,7 @@ impl Assembler {
                 });
                 self.emit(Inst::Div {
                     sign: DivSignedness::Unsigned,
+                    trap: TrapCode::IntegerDivisionByZero,
                     size: size.into(),
                     divisor: GprMem::new(RegMem::reg(divisor.into())).unwrap(),
                     dividend_lo: dst.0.into(),


Test patch:
diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
index 7e258bb8f..ee759d1a1 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
@@ -1750,6 +1750,7 @@ fn test_x64_emit() {
         Inst::div(
             OperandSize::Size32,
             DivSignedness::Signed,
+            TrapCode::IntegerDivisionByZero,
             RegMem::reg(regs::rsi()),
             Gpr::new(regs::rax()).unwrap(),
             Gpr::new(regs::rdx()).unwrap(),
@@ -1757,12 +1758,13 @@ fn test_x64_emit() {
             WritableGpr::from_reg(Gpr::new(regs::rdx()).unwrap()),
         ),
         "F7FE",
-        "idiv    %eax, %edx, %esi, %eax, %edx",
+        "idiv    %eax, %edx, %esi, %eax, %edx ; trap=int_divz",
     ));
     insns.push((
         Inst::div(
             OperandSize::Size64,
             DivSignedness::Signed,
+            TrapCode::IntegerDivisionByZero,
             RegMem::reg(regs::r15()),
             Gpr::new(regs::rax()).unwrap(),
             Gpr::new(regs::rdx()).unwrap(),
@@ -1770,12 +1772,13 @@ fn test_x64_emit() {
             WritableGpr::from_reg(Gpr::new(regs::rdx()).unwrap()),
         ),
         "49F7FF",
-        "idiv    %rax, %rdx, %r15, %rax, %rdx",
+        "idiv    %rax, %rdx, %r15, %rax, %rdx ; trap=int_divz",
     ));
     insns.push((
         Inst::div(
             OperandSize::Size32,
             DivSignedness::Unsigned,
+            TrapCode::IntegerDivisionByZero,
             RegMem::reg(regs::r14()),
             Gpr::new(regs::rax()).unwrap(),
             Gpr::new(regs::rdx()).unwrap(),
@@ -1783,12 +1786,13 @@ fn test_x64_emit() {
             WritableGpr::from_reg(Gpr::new(regs::rdx()).unwrap()),
         ),
         "41F7F6",
-        "div     %eax, %edx, %r14d, %eax, %edx",
+        "div     %eax, %edx, %r14d, %eax, %edx ; trap=int_divz",
     ));
     insns.push((
         Inst::div(
             OperandSize::Size64,
             DivSignedness::Unsigned,
+            TrapCode::IntegerDivisionByZero,
             RegMem::reg(regs::rdi()),
             Gpr::new(regs::rax()).unwrap(),
             Gpr::new(regs::rdx()).unwrap(),
@@ -1796,27 +1800,29 @@ fn test_x64_emit() {
             WritableGpr::from_reg(Gpr::new(regs::rdx()).unwrap()),
         ),
         "48F7F7",
-        "div     %rax, %rdx, %rdi, %rax, %rdx",
+        "div     %rax, %rdx, %rdi, %rax, %rdx ; trap=int_divz",
     ));
     insns.push((
         Inst::div8(
             DivSignedness::Unsigned,
+            TrapCode::IntegerDivisionByZero,
             RegMem::reg(regs::rax()),
             Gpr::new(regs::rax()).unwrap(),
             WritableGpr::from_reg(Gpr::new(regs::rax()).unwrap()),
         ),
         "F6F0",
-        "div     %al, %al, %al",
+        "div     %al, %al, %al ; trap=int_divz",
     ));
     insns.push((
         Inst::div8(
             DivSignedness::Unsigned,
+            TrapCode::IntegerDivisionByZero,
             RegMem::reg(regs::rsi()),
             Gpr::new(regs::rax()).unwrap(),
             WritableGpr::from_reg(Gpr::new(regs::rax()).unwrap()),
         ),
         "40F6F6",
-        "div     %al, %sil, %al",
+        "div     %al, %sil, %al ; trap=int_divz",
     ));
 
     // ========================================================
diff --git a/cranelift/filetests/filetests/egraph/misc.clif b/cranelift/filetests/filetests/egraph/misc.clif
index 811211601..5eb42631c 100644
--- a/cranelift/filetests/filetests/egraph/misc.clif
+++ b/cranelift/filetests/filetests/egraph/misc.clif
@@ -16,6 +16,6 @@ block0(v0: i64):
 ; nextln:    ss0 = explicit_slot 8
 ; check:  block0(v0: i64):
 ; nextln:     v2 = stack_addr.i64 ss0
-; nextln:     store notrap aligned v0, v2
+; nextln:     store notrap v0, v2
 ; nextln:     return v0
 ; nextln: }
diff --git a/cranelift/filetests/filetests/isa/s390x/div-traps.clif b/cranelift/filetests/filetests/isa/s390x/div-traps.clif
deleted file mode 100644
index 5b776de46..000000000
--- a/cranelift/filetests/filetests/isa/s390x/div-traps.clif
+++ /dev/null
@@ -1,727 +0,0 @@
-test compile precise-output
-set avoid_div_traps=1
-target s390x
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; SDIV
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-function %sdiv_i64(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = sdiv.i64 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   cgite %r3, 0
-;   llihf %r4, 2147483647
-;   iilf %r4, 4294967295
-;   xgr %r4, %r2
-;   lgr %r5, %r2
-;   ngr %r4, %r3
-;   lgr %r2, %r3
-;   cgite %r4, -1
-;   lgr %r4, %r2
-;   lgr %r3, %r5
-;   dsgr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   cgite %r3, 0 ; trap: int_divz
-;   llihf %r4, 0x7fffffff
-;   iilf %r4, 0xffffffff
-;   xgr %r4, %r2
-;   lgr %r5, %r2
-;   ngr %r4, %r3
-;   lgr %r2, %r3
-;   cgite %r4, -1 ; trap: int_ovf
-;   lgr %r4, %r2
-;   lgr %r3, %r5
-;   dsgr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %sdiv_i64_imm(i64) -> i64 {
-block0(v0: i64):
-  v1 = iconst.i64 2
-  v2 = sdiv.i64 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r3, %r2
-;   lghi %r4, 2
-;   dsgr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r3, %r2
-;   lghi %r4, 2
-;   dsgr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %sdiv_i32(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = sdiv.i32 v0, v1
-  return v2
-}
-
-; VCode:
-;   stmg %r7, %r15, 56(%r15)
-; block0:
-;   lgfr %r5, %r2
-;   lgr %r7, %r5
-;   cite %r3, 0
-;   iilf %r5, 2147483647
-;   lgr %r4, %r7
-;   xrk %r2, %r5, %r4
-;   nrk %r4, %r2, %r3
-;   lgr %r5, %r3
-;   cite %r4, -1
-;   lgr %r3, %r7
-;   dsgfr %r2, %r5
-;   lgr %r2, %r3
-;   lmg %r7, %r15, 56(%r15)
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   stmg %r7, %r15, 0x38(%r15)
-; block1: ; offset 0x6
-;   lgfr %r5, %r2
-;   lgr %r7, %r5
-;   cite %r3, 0 ; trap: int_divz
-;   iilf %r5, 0x7fffffff
-;   lgr %r4, %r7
-;   xrk %r2, %r5, %r4
-;   nrk %r4, %r2, %r3
-;   lgr %r5, %r3
-;   cite %r4, -1 ; trap: int_ovf
-;   lgr %r3, %r7
-;   dsgfr %r2, %r5 ; trap: int_divz
-;   lgr %r2, %r3
-;   lmg %r7, %r15, 0x38(%r15)
-;   br %r14
-
-function %sdiv_i32_imm(i32) -> i32 {
-block0(v0: i32):
-  v1 = iconst.i32 2
-  v2 = sdiv.i32 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgfr %r3, %r2
-;   lhi %r2, 2
-;   dsgfr %r2, %r2
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgfr %r3, %r2
-;   lhi %r2, 2
-;   dsgfr %r2, %r2 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %sdiv_i16(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = sdiv.i16 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lghr %r5, %r2
-;   lhr %r4, %r3
-;   cite %r4, 0
-;   lhi %r2, 32767
-;   lgr %r3, %r5
-;   xrk %r5, %r2, %r3
-;   nrk %r2, %r5, %r4
-;   cite %r2, -1
-;   dsgfr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lghr %r5, %r2
-;   lhr %r4, %r3
-;   cite %r4, 0 ; trap: int_divz
-;   lhi %r2, 0x7fff
-;   lgr %r3, %r5
-;   xrk %r5, %r2, %r3
-;   nrk %r2, %r5, %r4
-;   cite %r2, -1 ; trap: int_ovf
-;   dsgfr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %sdiv_i16_imm(i16) -> i16 {
-block0(v0: i16):
-  v1 = iconst.i16 2
-  v2 = sdiv.i16 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lghr %r3, %r2
-;   lhi %r2, 2
-;   dsgfr %r2, %r2
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lghr %r3, %r2
-;   lhi %r2, 2
-;   dsgfr %r2, %r2 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %sdiv_i8(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = sdiv.i8 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgbr %r5, %r2
-;   lbr %r4, %r3
-;   cite %r4, 0
-;   lhi %r2, 127
-;   lgr %r3, %r5
-;   xrk %r5, %r2, %r3
-;   nrk %r2, %r5, %r4
-;   cite %r2, -1
-;   dsgfr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgbr %r5, %r2
-;   lbr %r4, %r3
-;   cite %r4, 0 ; trap: int_divz
-;   lhi %r2, 0x7f
-;   lgr %r3, %r5
-;   xrk %r5, %r2, %r3
-;   nrk %r2, %r5, %r4
-;   cite %r2, -1 ; trap: int_ovf
-;   dsgfr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %sdiv_i8_imm(i8) -> i8 {
-block0(v0: i8):
-  v1 = iconst.i8 2
-  v2 = sdiv.i8 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgbr %r3, %r2
-;   lhi %r2, 2
-;   dsgfr %r2, %r2
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgbr %r3, %r2
-;   lhi %r2, 2
-;   dsgfr %r2, %r2 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %udiv_i64(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = udiv.i64 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r5, %r2
-;   lghi %r2, 0
-;   cgite %r3, 0
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlgr %r2, %r5
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r5, %r2
-;   lghi %r2, 0
-;   cgite %r3, 0 ; trap: int_divz
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlgr %r2, %r5 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %udiv_i64_imm(i64) -> i64 {
-block0(v0: i64):
-  v1 = iconst.i64 2
-  v2 = udiv.i64 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r3, %r2
-;   lghi %r2, 0
-;   lghi %r4, 2
-;   dlgr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r3, %r2
-;   lghi %r2, 0
-;   lghi %r4, 2
-;   dlgr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %udiv_i32(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = udiv.i32 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r5, %r2
-;   lhi %r2, 0
-;   cite %r3, 0
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlr %r2, %r5
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r5, %r2
-;   lhi %r2, 0
-;   cite %r3, 0 ; trap: int_divz
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlr %r2, %r5 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %udiv_i32_imm(i32) -> i32 {
-block0(v0: i32):
-  v1 = iconst.i32 2
-  v2 = udiv.i32 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r3, %r2
-;   lhi %r2, 0
-;   lhi %r4, 2
-;   dlr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r3, %r2
-;   lhi %r2, 0
-;   lhi %r4, 2
-;   dlr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %udiv_i16(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = udiv.i16 v0, v1
-  return v2
-}
-
-; VCode:
-;   stmg %r8, %r15, 64(%r15)
-; block0:
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llhr %r3, %r2
-;   lgr %r5, %r4
-;   llhr %r5, %r5
-;   cite %r5, 0
-;   lgr %r2, %r8
-;   dlr %r2, %r5
-;   lgr %r2, %r3
-;   lmg %r8, %r15, 64(%r15)
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   stmg %r8, %r15, 0x40(%r15)
-; block1: ; offset 0x6
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llhr %r3, %r2
-;   lgr %r5, %r4
-;   llhr %r5, %r5
-;   cite %r5, 0 ; trap: int_divz
-;   lgr %r2, %r8
-;   dlr %r2, %r5 ; trap: int_divz
-;   lgr %r2, %r3
-;   lmg %r8, %r15, 0x40(%r15)
-;   br %r14
-
-function %udiv_i16_imm(i16) -> i16 {
-block0(v0: i16):
-  v1 = iconst.i16 2
-  v2 = udiv.i16 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lhi %r4, 0
-;   lgr %r5, %r4
-;   llhr %r3, %r2
-;   lhi %r4, 2
-;   lgr %r2, %r5
-;   dlr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lhi %r4, 0
-;   lgr %r5, %r4
-;   llhr %r3, %r2
-;   lhi %r4, 2
-;   lgr %r2, %r5
-;   dlr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %udiv_i8(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = udiv.i8 v0, v1
-  return v2
-}
-
-; VCode:
-;   stmg %r8, %r15, 64(%r15)
-; block0:
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llcr %r3, %r2
-;   lgr %r5, %r4
-;   llcr %r5, %r5
-;   cite %r5, 0
-;   lgr %r2, %r8
-;   dlr %r2, %r5
-;   lgr %r2, %r3
-;   lmg %r8, %r15, 64(%r15)
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   stmg %r8, %r15, 0x40(%r15)
-; block1: ; offset 0x6
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llcr %r3, %r2
-;   lgr %r5, %r4
-;   llcr %r5, %r5
-;   cite %r5, 0 ; trap: int_divz
-;   lgr %r2, %r8
-;   dlr %r2, %r5 ; trap: int_divz
-;   lgr %r2, %r3
-;   lmg %r8, %r15, 0x40(%r15)
-;   br %r14
-
-function %udiv_i8_imm(i8) -> i8 {
-block0(v0: i8):
-  v1 = iconst.i8 2
-  v2 = udiv.i8 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lhi %r4, 0
-;   lgr %r5, %r4
-;   llcr %r3, %r2
-;   lhi %r4, 2
-;   lgr %r2, %r5
-;   dlr %r2, %r4
-;   lgr %r2, %r3
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lhi %r4, 0
-;   lgr %r5, %r4
-;   llcr %r3, %r2
-;   lhi %r4, 2
-;   lgr %r2, %r5
-;   dlr %r2, %r4 ; trap: int_divz
-;   lgr %r2, %r3
-;   br %r14
-
-function %srem_i64(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = srem.i64 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   cgite %r3, 0
-;   cghi %r3, -1
-;   lgr %r4, %r3
-;   lgr %r3, %r2
-;   locghie %r3, 0
-;   dsgr %r2, %r4
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   cgite %r3, 0 ; trap: int_divz
-;   cghi %r3, -1
-;   lgr %r4, %r3
-;   lgr %r3, %r2
-;   locghie %r3, 0
-;   dsgr %r2, %r4 ; trap: int_divz
-;   br %r14
-
-function %srem_i32(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = srem.i32 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r5, %r3
-;   lgfr %r3, %r2
-;   lgr %r2, %r5
-;   cite %r2, 0
-;   dsgfr %r2, %r2
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r5, %r3
-;   lgfr %r3, %r2
-;   lgr %r2, %r5
-;   cite %r2, 0 ; trap: int_divz
-;   dsgfr %r2, %r2 ; trap: int_divz
-;   br %r14
-
-function %srem_i16(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = srem.i16 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lghr %r5, %r2
-;   lgr %r2, %r5
-;   lhr %r4, %r3
-;   cite %r4, 0
-;   lgr %r3, %r2
-;   dsgfr %r2, %r4
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lghr %r5, %r2
-;   lgr %r2, %r5
-;   lhr %r4, %r3
-;   cite %r4, 0 ; trap: int_divz
-;   lgr %r3, %r2
-;   dsgfr %r2, %r4 ; trap: int_divz
-;   br %r14
-
-function %srem_i8(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = srem.i8 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgbr %r5, %r2
-;   lgr %r2, %r5
-;   lbr %r4, %r3
-;   cite %r4, 0
-;   lgr %r3, %r2
-;   dsgfr %r2, %r4
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgbr %r5, %r2
-;   lgr %r2, %r5
-;   lbr %r4, %r3
-;   cite %r4, 0 ; trap: int_divz
-;   lgr %r3, %r2
-;   dsgfr %r2, %r4 ; trap: int_divz
-;   br %r14
-
-function %urem_i64(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = urem.i64 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r5, %r2
-;   lghi %r2, 0
-;   cgite %r3, 0
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlgr %r2, %r5
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r5, %r2
-;   lghi %r2, 0
-;   cgite %r3, 0 ; trap: int_divz
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlgr %r2, %r5 ; trap: int_divz
-;   br %r14
-
-function %urem_i32(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = urem.i32 v0, v1
-  return v2
-}
-
-; VCode:
-; block0:
-;   lgr %r5, %r2
-;   lhi %r2, 0
-;   cite %r3, 0
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlr %r2, %r5
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   lgr %r5, %r2
-;   lhi %r2, 0
-;   cite %r3, 0 ; trap: int_divz
-;   lgr %r4, %r3
-;   lgr %r3, %r5
-;   lgr %r5, %r4
-;   dlr %r2, %r5 ; trap: int_divz
-;   br %r14
-
-function %urem_i16(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = urem.i16 v0, v1
-  return v2
-}
-
-; VCode:
-;   stmg %r8, %r15, 64(%r15)
-; block0:
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llhr %r3, %r2
-;   lgr %r5, %r4
-;   llhr %r5, %r5
-;   cite %r5, 0
-;   lgr %r2, %r8
-;   dlr %r2, %r5
-;   lmg %r8, %r15, 64(%r15)
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   stmg %r8, %r15, 0x40(%r15)
-; block1: ; offset 0x6
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llhr %r3, %r2
-;   lgr %r5, %r4
-;   llhr %r5, %r5
-;   cite %r5, 0 ; trap: int_divz
-;   lgr %r2, %r8
-;   dlr %r2, %r5 ; trap: int_divz
-;   lmg %r8, %r15, 0x40(%r15)
-;   br %r14
-
-function %urem_i8(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = urem.i8 v0, v1
-  return v2
-}
-
-; VCode:
-;   stmg %r8, %r15, 64(%r15)
-; block0:
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llcr %r3, %r2
-;   lgr %r5, %r4
-;   llcr %r5, %r5
-;   cite %r5, 0
-;   lgr %r2, %r8
-;   dlr %r2, %r5
-;   lmg %r8, %r15, 64(%r15)
-;   br %r14
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   stmg %r8, %r15, 0x40(%r15)
-; block1: ; offset 0x6
-;   lgr %r4, %r3
-;   lhi %r5, 0
-;   lgr %r8, %r5
-;   llcr %r3, %r2
-;   lgr %r5, %r4
-;   llcr %r5, %r5
-;   cite %r5, 0 ; trap: int_divz
-;   lgr %r2, %r8
-;   dlr %r2, %r5 ; trap: int_divz
-;   lmg %r8, %r15, 0x40(%r15)
-;   br %r14
-
diff --git a/cranelift/filetests/filetests/isa/x64/amode-opt.clif b/cranelift/filetests/filetests/isa/x64/amode-opt.clif
index eef1d2893..e3d689998 100644
--- a/cranelift/filetests/filetests/isa/x64/amode-opt.clif
+++ b/cranelift/filetests/filetests/isa/x64/amode-opt.clif
@@ -1,4 +1,6 @@
 test compile precise-output
+set use_egraphs=true
+set opt_level=speed
 target x86_64
 
 function %amode_add(i64, i64) -> i64 {
@@ -244,8 +246,7 @@ block0(v0: i64, v1: i32, v2: i32):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movq    %rsi, %r8
-;   addl    %r8d, %edx, %r8d
+;   lea     0(%rsi,%rdx,1), %r8d
 ;   shll    $2, %r8d, %r8d
 ;   movq    -1(%rdi,%r8,1), %rax
 ;   movq    %rbp, %rsp
@@ -257,8 +258,7 @@ block0(v0: i64, v1: i32, v2: i32):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movq %rsi, %r8
-;   addl %edx, %r8d
+;   leal (%rsi, %rdx), %r8d
 ;   shll $2, %r8d
 ;   movq -1(%rdi, %r8), %rax ; trap: heap_oob
 ;   movq %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/basic.clif b/cranelift/filetests/filetests/isa/x64/basic.clif
index d10885cd0..01fac2deb 100644
--- a/cranelift/filetests/filetests/isa/x64/basic.clif
+++ b/cranelift/filetests/filetests/isa/x64/basic.clif
@@ -11,8 +11,7 @@ block0(v0: i32, v1: i32):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movq    %rdi, %rax
-;   addl    %eax, %esi, %eax
+;   lea     0(%rdi,%rsi,1), %eax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -22,8 +21,7 @@ block0(v0: i32, v1: i32):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   addl %esi, %eax
+;   leal (%rdi, %rsi), %eax
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
diff --git a/cranelift/filetests/filetests/isa/x64/branches.clif b/cranelift/filetests/filetests/isa/x64/branches.clif
index 01d9c3abd..bdaf6b5b6 100644
--- a/cranelift/filetests/filetests/isa/x64/branches.clif
+++ b/cranelift/filetests/filetests/isa/x64/branches.clif
@@ -784,8 +784,7 @@ block5(v5: i32):
 ;   movl    $4, %esi
 ;   jmp     label7
 ; block7:
-;   movq    %rdi, %rax
-;   addl    %eax, %esi, %eax
+;   lea     0(%rdi,%rsi,1), %eax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -825,8 +824,7 @@ block5(v5: i32):
 ; block6: ; offset 0x59
 ;   movl $4, %esi
 ; block7: ; offset 0x5e
-;   movq %rdi, %rax
-;   addl %esi, %eax
+;   leal (%rdi, %rsi), %eax
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
diff --git a/cranelift/filetests/filetests/isa/x64/div-checks.clif b/cranelift/filetests/filetests/isa/x64/div-checks.clif
index 381a66b63..9dd90788c 100644
--- a/cranelift/filetests/filetests/isa/x64/div-checks.clif
+++ b/cranelift/filetests/filetests/isa/x64/div-checks.clif
@@ -1,10 +1,8 @@
 test compile precise-output
-set avoid_div_traps=false
 target x86_64
 
-;; We should get the checked-div/rem sequence (`srem` pseudoinst below) even
-;; when `avoid_div_traps` above is false (i.e. even when the host is normally
-;; willing to accept SIGFPEs as Wasm traps). The machine will SIGFPE in some
+;; We should get the checked-div/rem sequence (`srem` pseudoinst below).
+;; The machine will SIGFPE in some
 ;; cases when `srem` is valid (specifically -INT_MIN % -1).
 
 function %i8(i8, i8) -> i8 {
diff --git a/cranelift/filetests/filetests/isa/x64/immediates.clif b/cranelift/filetests/filetests/isa/x64/immediates.clif
index bdbd7ece6..62528f0b6 100644
--- a/cranelift/filetests/filetests/isa/x64/immediates.clif
+++ b/cranelift/filetests/filetests/isa/x64/immediates.clif
@@ -19,15 +19,15 @@ block0(v0: i64, v1: i64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movq    %rdi, %r9
-;   addq    %r9, const(0), %r9
-;   movq    %r9, 0(%rsi)
-;   movq    %rdi, %r10
-;   subq    %r10, const(0), %r10
-;   movq    %r10, 0(%rsi)
+;   movabsq $-18765284782900, %r9
+;   lea     0(%rdi,%r9,1), %r11
+;   movq    %r11, 0(%rsi)
 ;   movq    %rdi, %r11
-;   andq    %r11, const(0), %r11
+;   subq    %r11, const(0), %r11
 ;   movq    %r11, 0(%rsi)
+;   movq    %rdi, %rax
+;   andq    %rax, const(0), %rax
+;   movq    %rax, 0(%rsi)
 ;   orq     %rdi, const(0), %rdi
 ;   movq    %rdi, 0(%rsi)
 ;   movq    %rbp, %rsp
@@ -39,24 +39,21 @@ block0(v0: i64, v1: i64):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movq %rdi, %r9
-;   addq 0x32(%rip), %r9
-;   movq %r9, (%rsi) ; trap: heap_oob
-;   movq %rdi, %r10
-;   subq 0x25(%rip), %r10
-;   movq %r10, (%rsi) ; trap: heap_oob
+;   movabsq $18446725308424768716, %r9
+;   leaq (%rdi, %r9), %r11
+;   movq %r11, (%rsi) ; trap: heap_oob
 ;   movq %rdi, %r11
-;   andq 0x18(%rip), %r11
+;   subq 0x20(%rip), %r11
 ;   movq %r11, (%rsi) ; trap: heap_oob
-;   orq 0xe(%rip), %rdi
+;   movq %rdi, %rax
+;   andq 0x13(%rip), %rax
+;   movq %rax, (%rsi) ; trap: heap_oob
+;   orq 9(%rip), %rdi
 ;   movq %rdi, (%rsi) ; trap: heap_oob
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
-;   addb %al, (%rax)
-;   addb %al, (%rax)
-;   addb %al, (%rax)
-;   int3
+;   addb %cl, %ah
 ;   int3
 ;   fstp %st(5)
 ;   outb %al, %dx
diff --git a/cranelift/filetests/filetests/isa/x64/lea.clif b/cranelift/filetests/filetests/isa/x64/lea.clif
new file mode 100644
index 000000000..4dc8182bd
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/lea.clif
@@ -0,0 +1,271 @@
+test compile precise-output
+target x86_64
+
+function %add_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = iadd v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     0(%rdi,%rsi,1), %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leal (%rdi, %rsi), %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = iadd v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     0(%rdi,%rsi,1), %rax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leaq (%rdi, %rsi), %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i32_const(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 100
+  v2 = iadd v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     100(%rdi), %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leal 0x64(%rdi), %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i64_const(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i64 100
+  v2 = iadd v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     100(%rdi), %rax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leaq 0x64(%rdi), %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i32_i32_const(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = iconst.i32 100
+  v3 = iadd v0, v1
+  v4 = iadd v3, v2
+  return v4
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     100(%rdi,%rsi,1), %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leal 0x64(%rdi, %rsi), %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i64_i64_const(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = iconst.i64 100
+  v3 = iadd v0, v1
+  v4 = iadd v3, v2
+  return v4
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     100(%rdi,%rsi,1), %rax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leaq 0x64(%rdi, %rsi), %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i32_i32_mul_const(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = iconst.i32 100
+  v3 = iconst.i32 2
+  v4 = ishl v1, v3
+  v5 = iadd v0, v4
+  v6 = iadd v5, v2
+  return v6
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     100(%rdi,%rsi,4), %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leal 0x64(%rdi, %rsi, 4), %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i64_i64_mul_const(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = iconst.i64 100
+  v3 = iconst.i64 2
+  v4 = ishl v1, v3
+  v5 = iadd v0, v4
+  v6 = iadd v5, v2
+  return v6
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     100(%rdi,%rsi,4), %rax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leaq 0x64(%rdi, %rsi, 4), %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i32_i32_mul(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v3 = iconst.i32 2
+  v4 = ishl v1, v3
+  v5 = iadd v0, v4
+  return v5
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     0(%rdi,%rsi,4), %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leal (%rdi, %rsi, 4), %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %add_i64_i64_mul(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v3 = iconst.i64 2
+  v4 = ishl v1, v3
+  v5 = iadd v0, v4
+  return v5
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   lea     0(%rdi,%rsi,4), %rax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   leaq (%rdi, %rsi, 4), %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/load-op.clif b/cranelift/filetests/filetests/isa/x64/load-op.clif
index ab140cb5f..3c4e5fde9 100644
--- a/cranelift/filetests/filetests/isa/x64/load-op.clif
+++ b/cranelift/filetests/filetests/isa/x64/load-op.clif
@@ -155,8 +155,7 @@ block0(v0: i64, v1: i64):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    0(%rdi), %r8
-;   movq    %r8, %r9
-;   addq    %r9, %rdi, %r9
+;   lea     0(%r8,%rdi,1), %r9
 ;   movq    %r9, 0(%rsi)
 ;   movq    0(%r8,%rdi,1), %rax
 ;   movq    %rbp, %rsp
@@ -169,8 +168,7 @@ block0(v0: i64, v1: i64):
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
 ;   movq (%rdi), %r8 ; trap: heap_oob
-;   movq %r8, %r9
-;   addq %rdi, %r9
+;   leaq (%r8, %rdi), %r9
 ;   movq %r9, (%rsi) ; trap: heap_oob
 ;   movq (%r8, %rdi), %rax ; trap: heap_oob
 ;   movq %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/pinned-reg.clif b/cranelift/filetests/filetests/isa/x64/pinned-reg.clif
index 26bc0b280..36797fb11 100644
--- a/cranelift/filetests/filetests/isa/x64/pinned-reg.clif
+++ b/cranelift/filetests/filetests/isa/x64/pinned-reg.clif
@@ -14,9 +14,9 @@ block0:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movq    %r15, %rsi
-;   addq    %rsi, $1, %rsi
-;   movq    %rsi, %r15
+;   movq    %r15, %rdi
+;   lea     1(%rdi), %rdi
+;   movq    %rdi, %r15
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -26,9 +26,9 @@ block0:
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movq %r15, %rsi
-;   addq $1, %rsi
-;   movq %rsi, %r15
+;   movq %r15, %rdi
+;   addq $1, %rdi
+;   movq %rdi, %r15
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -45,12 +45,12 @@ block0:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
-;   movq    %rsi, 0(%rsp)
+;   movq    %rdi, 0(%rsp)
 ; block0:
-;   movq    %r15, %rsi
-;   addq    %rsi, $1, %rsi
-;   movq    %rsi, %r15
-;   movq    0(%rsp), %rsi
+;   movq    %r15, %rdi
+;   lea     1(%rdi), %rdi
+;   movq    %rdi, %r15
+;   movq    0(%rsp), %rdi
 ;   addq    %rsp, $16, %rsp
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -61,12 +61,12 @@ block0:
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ;   subq $0x10, %rsp
-;   movq %rsi, (%rsp)
+;   movq %rdi, (%rsp)
 ; block1: ; offset 0xc
-;   movq %r15, %rsi
-;   addq $1, %rsi
-;   movq %rsi, %r15
-;   movq (%rsp), %rsi
+;   movq %r15, %rdi
+;   addq $1, %rdi
+;   movq %rdi, %r15
+;   movq (%rsp), %rdi
 ;   addq $0x10, %rsp
 ;   movq %rbp, %rsp
 ;   popq %rbp
diff --git a/cranelift/filetests/filetests/isa/x64/sdiv-checked.clif b/cranelift/filetests/filetests/isa/x64/sdiv-checked.clif
deleted file mode 100644
index 7505a3078..000000000
--- a/cranelift/filetests/filetests/isa/x64/sdiv-checked.clif
+++ /dev/null
@@ -1,285 +0,0 @@
-test compile precise-output
-set avoid_div_traps=true
-target x86_64
-
-function %f1(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   cbw %al, %al
-;   validate_sdiv_divisor %sil, %al
-;   idiv    %al, %sil, %al
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   cbtw
-;   cmpb $0, %sil
-;   jne 0x15
-;   ud2 ; trap: int_divz
-;   cmpb $0xff, %sil
-;   jne 0x2a
-;   cmpb $0x80, %al
-;   jne 0x2a
-;   ud2 ; trap: int_ovf
-;   idivb %sil ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f2(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   validate_sdiv_divisor %si, %di
-;   movq    %rdi, %rax
-;   cwd %ax, %dx
-;   idiv    %ax, %dx, %si, %ax, %dx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   cmpw $0, %si
-;   jne 0x10
-;   ud2 ; trap: int_divz
-;   cmpw $-1, %si
-;   jne 0x27
-;   cmpw $0x8000, %di
-;   jne 0x27
-;   ud2 ; trap: int_ovf
-;   movq %rdi, %rax
-;   cwtd
-;   idivw %si ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f3(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   validate_sdiv_divisor %esi, %edi
-;   movq    %rdi, %rax
-;   cdq %eax, %edx
-;   idiv    %eax, %edx, %esi, %eax, %edx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   cmpl $0, %esi
-;   jne 0xf
-;   ud2 ; trap: int_divz
-;   cmpl $-1, %esi
-;   jne 0x26
-;   cmpl $0x80000000, %edi
-;   jne 0x26
-;   ud2 ; trap: int_ovf
-;   movq %rdi, %rax
-;   cltd
-;   idivl %esi ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f4(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   validate_sdiv_divisor %rsi, %rdi %rcx
-;   movq    %rdi, %rax
-;   cqo %rax, %rdx
-;   idiv    %rax, %rdx, %rsi, %rax, %rdx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   cmpq $0, %rsi
-;   jne 0x10
-;   ud2 ; trap: int_divz
-;   cmpq $-1, %rsi
-;   jne 0x2f
-;   movabsq $9223372036854775808, %rcx
-;   cmpq %rcx, %rdi
-;   jne 0x2f
-;   ud2 ; trap: int_ovf
-;   movq %rdi, %rax
-;   cqto
-;   idivq %rsi ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i8_imm(i8) -> i8 {
-block0(v0: i8):
-  v1 = iconst.i8 17
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   cbw %al, %al
-;   movl    $17, %edx
-;   idiv    %al, %dl, %al
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   cbtw
-;   movl $0x11, %edx
-;   idivb %dl ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i16_imm(i16) -> i16 {
-block0(v0: i16):
-  v1 = iconst.i16 17
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movl    $17, %ecx
-;   movq    %rdi, %rax
-;   cwd %ax, %dx
-;   idiv    %ax, %dx, %cx, %ax, %dx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movl $0x11, %ecx
-;   movq %rdi, %rax
-;   cwtd
-;   idivw %cx ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i32_imm(i32) -> i32 {
-block0(v0: i32):
-  v1 = iconst.i32 17
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movl    $17, %ecx
-;   movq    %rdi, %rax
-;   cdq %eax, %edx
-;   idiv    %eax, %edx, %ecx, %eax, %edx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movl $0x11, %ecx
-;   movq %rdi, %rax
-;   cltd
-;   idivl %ecx ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i64_imm(i64) -> i64 {
-block0(v0: i64):
-  v1 = iconst.i64 17
-  v2 = sdiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movl    $17, %ecx
-;   movq    %rdi, %rax
-;   cqo %rax, %rdx
-;   idiv    %rax, %rdx, %rcx, %rax, %rdx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movl $0x11, %ecx
-;   movq %rdi, %rax
-;   cqto
-;   idivq %rcx ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
diff --git a/cranelift/filetests/filetests/isa/x64/sdiv.clif b/cranelift/filetests/filetests/isa/x64/sdiv.clif
index 657a1e7fa..f20b17d0b 100644
--- a/cranelift/filetests/filetests/isa/x64/sdiv.clif
+++ b/cranelift/filetests/filetests/isa/x64/sdiv.clif
@@ -13,7 +13,9 @@ block0(v0: i8, v1: i8):
 ; block0:
 ;   movq    %rdi, %rax
 ;   cbw %al, %al
-;   idiv    %al, %sil, %al
+;   testb   %sil, %sil
+;   jnz ; ud2 int_divz ;
+;   idiv    %al, %sil, %al ; trap=int_ovf
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -25,7 +27,10 @@ block0(v0: i8, v1: i8):
 ; block1: ; offset 0x4
 ;   movq %rdi, %rax
 ;   cbtw
-;   idivb %sil ; trap: int_divz
+;   testb %sil, %sil
+;   jne 0x14
+;   ud2 ; trap: int_divz
+;   idivb %sil ; trap: int_ovf
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -42,7 +47,9 @@ block0(v0: i16, v1: i16):
 ; block0:
 ;   movq    %rdi, %rax
 ;   cwd %ax, %dx
-;   idiv    %ax, %dx, %si, %ax, %dx
+;   testw   %si, %si
+;   jnz ; ud2 int_divz ;
+;   idiv    %ax, %dx, %si, %ax, %dx ; trap=int_ovf
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -54,7 +61,10 @@ block0(v0: i16, v1: i16):
 ; block1: ; offset 0x4
 ;   movq %rdi, %rax
 ;   cwtd
-;   idivw %si ; trap: int_divz
+;   testw %si, %si
+;   jne 0x14
+;   ud2 ; trap: int_divz
+;   idivw %si ; trap: int_ovf
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -71,7 +81,9 @@ block0(v0: i32, v1: i32):
 ; block0:
 ;   movq    %rdi, %rax
 ;   cdq %eax, %edx
-;   idiv    %eax, %edx, %esi, %eax, %edx
+;   testl   %esi, %esi
+;   jnz ; ud2 int_divz ;
+;   idiv    %eax, %edx, %esi, %eax, %edx ; trap=int_ovf
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -83,7 +95,10 @@ block0(v0: i32, v1: i32):
 ; block1: ; offset 0x4
 ;   movq %rdi, %rax
 ;   cltd
-;   idivl %esi ; trap: int_divz
+;   testl %esi, %esi
+;   jne 0x12
+;   ud2 ; trap: int_divz
+;   idivl %esi ; trap: int_ovf
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -100,7 +115,9 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   movq    %rdi, %rax
 ;   cqo %rax, %rdx
-;   idiv    %rax, %rdx, %rsi, %rax, %rdx
+;   testq   %rsi, %rsi
+;   jnz ; ud2 int_divz ;
+;   idiv    %rax, %rdx, %rsi, %rax, %rdx ; trap=int_ovf
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -112,7 +129,10 @@ block0(v0: i64, v1: i64):
 ; block1: ; offset 0x4
 ;   movq %rdi, %rax
 ;   cqto
-;   idivq %rsi ; trap: int_divz
+;   testq %rsi, %rsi
+;   jne 0x14
+;   ud2 ; trap: int_divz
+;   idivq %rsi ; trap: int_ovf
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
diff --git a/cranelift/filetests/filetests/isa/x64/shuffle-avx.clif b/cranelift/filetests/filetests/isa/x64/shuffle-avx.clif
index 30cf9721e..06aa6da5a 100644
--- a/cranelift/filetests/filetests/isa/x64/shuffle-avx.clif
+++ b/cranelift/filetests/filetests/isa/x64/shuffle-avx.clif
@@ -114,3 +114,31 @@ block0(v0: i64x2, v1: i64x2):
 ;   popq %rbp
 ;   retq
 
+function %pblendw_0b10011001(i16x8, i16x8) -> i16x8 {
+block0(v0: i16x8, v1: i16x8):
+    v2 = bitcast.i8x16 little v0
+    v3 = bitcast.i8x16 little v1
+    v4 = shuffle v2, v3, [16 17 2 3 4 5 22 23 24 25 10 11 12 13 30 31]
+    v5 = bitcast.i16x8 little v4
+    return v5
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vpblendw $153, %xmm0, %xmm1, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vpblendw $0x99, %xmm1, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/shuffle.clif b/cranelift/filetests/filetests/isa/x64/shuffle.clif
index f8f9b613e..cf58cd916 100644
--- a/cranelift/filetests/filetests/isa/x64/shuffle.clif
+++ b/cranelift/filetests/filetests/isa/x64/shuffle.clif
@@ -654,9 +654,7 @@ block0(v0: i8x16, v1: i8x16):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movdqa  %xmm0, %xmm4
-;   movdqa  %xmm1, %xmm0
-;   palignr $0, %xmm0, %xmm4, %xmm0
+;   pblendw $0, %xmm0, %xmm1, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -666,9 +664,7 @@ block0(v0: i8x16, v1: i8x16):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movdqa %xmm0, %xmm4
-;   movdqa %xmm1, %xmm0
-;   palignr $0, %xmm4, %xmm0
+;   pblendw $0, %xmm1, %xmm0
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -770,9 +766,7 @@ block0(v0: i8x16, v1: i8x16):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movdqa  %xmm0, %xmm4
-;   movdqa  %xmm1, %xmm0
-;   palignr $16, %xmm0, %xmm4, %xmm0
+;   pblendw $255, %xmm0, %xmm1, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -782,9 +776,35 @@ block0(v0: i8x16, v1: i8x16):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movdqa %xmm0, %xmm4
-;   movdqa %xmm1, %xmm0
-;   palignr $0x10, %xmm4, %xmm0
+;   pblendw $0xff, %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %pblendw_0b10011001(i16x8, i16x8) -> i16x8 {
+block0(v0: i16x8, v1: i16x8):
+    v2 = bitcast.i8x16 little v0
+    v3 = bitcast.i8x16 little v1
+    v4 = shuffle v2, v3, [16 17 2 3 4 5 22 23 24 25 10 11 12 13 30 31]
+    v5 = bitcast.i16x8 little v4
+    return v5
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   pblendw $153, %xmm0, %xmm1, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   pblendw $0x99, %xmm1, %xmm0
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
diff --git a/cranelift/filetests/filetests/isa/x64/simd-arith-avx.clif b/cranelift/filetests/filetests/isa/x64/simd-arith-avx.clif
index c33650d1a..15f5c84d1 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-arith-avx.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-arith-avx.clif
@@ -1315,11 +1315,10 @@ block0(v0: i8):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   uninit  %xmm2
-;   vpinsrb $0, %xmm2, %rdi, %xmm4
-;   uninit  %xmm6
-;   vpxor   %xmm6, %xmm6, %xmm8
-;   vpshufb %xmm4, %xmm8, %xmm0
+;   movd    %edi, %xmm2
+;   uninit  %xmm4
+;   vpxor   %xmm4, %xmm4, %xmm6
+;   vpshufb %xmm2, %xmm6, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -1329,9 +1328,9 @@ block0(v0: i8):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   vpinsrb $0, %edi, %xmm2, %xmm4
-;   vpxor %xmm6, %xmm6, %xmm8
-;   vpshufb %xmm8, %xmm4, %xmm0
+;   movd %edi, %xmm2
+;   vpxor %xmm4, %xmm4, %xmm6
+;   vpshufb %xmm6, %xmm2, %xmm0
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
diff --git a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
index f2ce65fec..522470533 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
@@ -170,11 +170,10 @@ block0(v0: i8):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   uninit  %xmm0
-;   pinsrb  $0, %xmm0, %rdi, %xmm0
-;   uninit  %xmm7
-;   pxor    %xmm7, %xmm7, %xmm7
-;   pshufb  %xmm0, %xmm7, %xmm0
+;   movd    %edi, %xmm0
+;   uninit  %xmm5
+;   pxor    %xmm5, %xmm5, %xmm5
+;   pshufb  %xmm0, %xmm5, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -184,9 +183,9 @@ block0(v0: i8):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   pinsrb $0, %edi, %xmm0
-;   pxor %xmm7, %xmm7
-;   pshufb %xmm7, %xmm0
+;   movd %edi, %xmm0
+;   pxor %xmm5, %xmm5
+;   pshufb %xmm5, %xmm0
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -203,9 +202,8 @@ block0:
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movl    $-1, %esi
-;   uninit  %xmm4
-;   pinsrw  $0, %xmm4, %rsi, %xmm4
-;   pinsrw  $1, %xmm4, %rsi, %xmm4
+;   movd    %esi, %xmm2
+;   pshuflw $0, %xmm2, %xmm4
 ;   pshufd  $0, %xmm4, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -217,8 +215,8 @@ block0:
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
 ;   movl $0xffffffff, %esi
-;   pinsrw $0, %esi, %xmm4
-;   pinsrw $1, %esi, %xmm4
+;   movd %esi, %xmm2
+;   pshuflw $0, %xmm2, %xmm4
 ;   pshufd $0, %xmm4, %xmm0
 ;   movq %rbp, %rsp
 ;   popq %rbp
@@ -234,9 +232,8 @@ block0(v0: i32):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   uninit  %xmm3
-;   pinsrd  $0, %xmm3, %rdi, %xmm3
-;   pshufd  $0, %xmm3, %xmm0
+;   movd    %edi, %xmm2
+;   pshufd  $0, %xmm2, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -246,8 +243,8 @@ block0(v0: i32):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   pinsrd $0, %edi, %xmm3
-;   pshufd $0, %xmm3, %xmm0
+;   movd %edi, %xmm2
+;   pshufd $0, %xmm2, %xmm0
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -262,11 +259,7 @@ block0(v0: f64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movdqa  %xmm0, %xmm5
-;   uninit  %xmm0
-;   movdqa  %xmm5, %xmm6
-;   movsd   %xmm0, %xmm6, %xmm0
-;   movlhps %xmm0, %xmm6, %xmm0
+;   movddup %xmm0, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -276,10 +269,7 @@ block0(v0: f64):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movdqa %xmm0, %xmm5
-;   movdqa %xmm5, %xmm6
-;   movsd %xmm6, %xmm0
-;   movlhps %xmm6, %xmm0
+;   movddup %xmm0, %xmm0
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
diff --git a/cranelift/filetests/filetests/isa/x64/simd-splat-avx.clif b/cranelift/filetests/filetests/isa/x64/simd-splat-avx.clif
new file mode 100644
index 000000000..8848b6694
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/simd-splat-avx.clif
@@ -0,0 +1,334 @@
+test compile precise-output
+set enable_simd
+target x86_64 has_avx
+
+function %splat_i8(i8) -> i8x16 {
+block0(v0: i8):
+  v1 = splat.i8x16 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   uninit  %xmm4
+;   vpxor   %xmm4, %xmm4, %xmm6
+;   vpshufb %xmm2, %xmm6, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   vpxor %xmm4, %xmm4, %xmm6
+;   vpshufb %xmm6, %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i16(i16) -> i16x8 {
+block0(v0: i16):
+  v1 = splat.i16x8 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   vpshuflw $0, %xmm2, %xmm4
+;   vpshufd $0, %xmm4, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   vpshuflw $0, %xmm2, %xmm4
+;   vpshufd $0, %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i32(i32) -> i32x4 {
+block0(v0: i32):
+  v1 = splat.i32x4 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   vpshufd $0, %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   vpshufd $0, %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i64(i64) -> i64x2 {
+block0(v0: i64):
+  v1 = splat.i64x2 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movq    %rdi, %xmm2
+;   vmovddup %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movq %rdi, %xmm2
+;   vmovddup %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_f32(f32) -> f32x4 {
+block0(v0: f32):
+  v1 = splat.f32x4 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vshufps $0, %xmm0, %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vshufps $0, %xmm0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_f64(f64) -> f64x2 {
+block0(v0: f64):
+  v1 = splat.f64x2 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vmovddup %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vmovddup %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i8(i64) -> i8x16 {
+block0(v0: i64):
+  v1 = load.i8 v0
+  v2 = splat.i8x16 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   uninit  %xmm2
+;   vpinsrb $0, %xmm2, 0(%rdi), %xmm4
+;   uninit  %xmm6
+;   vpxor   %xmm6, %xmm6, %xmm8
+;   vpshufb %xmm4, %xmm8, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vpinsrb $0, (%rdi), %xmm2, %xmm4 ; trap: heap_oob
+;   vpxor %xmm6, %xmm6, %xmm8
+;   vpshufb %xmm8, %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i16(i64) -> i16x8 {
+block0(v0: i64):
+  v1 = load.i16 v0
+  v2 = splat.i16x8 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   uninit  %xmm2
+;   vpinsrw $0, %xmm2, 0(%rdi), %xmm4
+;   vpshuflw $0, %xmm4, %xmm6
+;   vpshufd $0, %xmm6, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vpinsrw $0, (%rdi), %xmm2, %xmm4 ; trap: heap_oob
+;   vpshuflw $0, %xmm4, %xmm6
+;   vpshufd $0, %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i32(i64) -> i32x4 {
+block0(v0: i64):
+  v1 = load.i32 v0
+  v2 = splat.i32x4 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vbroadcastss 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vbroadcastss (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i64(i64) -> i64x2 {
+block0(v0: i64):
+  v1 = load.i64 v0
+  v2 = splat.i64x2 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vmovddup 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vmovddup (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_f32(i64) -> f32x4 {
+block0(v0: i64):
+  v1 = load.f32 v0
+  v2 = splat.f32x4 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vbroadcastss 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vbroadcastss (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_f64(i64) -> f64x2 {
+block0(v0: i64):
+  v1 = load.f64 v0
+  v2 = splat.f64x2 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vmovddup 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vmovddup (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/simd-splat-avx2.clif b/cranelift/filetests/filetests/isa/x64/simd-splat-avx2.clif
new file mode 100644
index 000000000..84cdfd373
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/simd-splat-avx2.clif
@@ -0,0 +1,318 @@
+test compile precise-output
+set enable_simd
+target x86_64 has_avx has_avx2
+
+function %splat_i8(i8) -> i8x16 {
+block0(v0: i8):
+  v1 = splat.i8x16 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   vpbroadcastb %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   vpbroadcastb %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i16(i16) -> i16x8 {
+block0(v0: i16):
+  v1 = splat.i16x8 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   vpbroadcastw %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   vpbroadcastw %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i32(i32) -> i32x4 {
+block0(v0: i32):
+  v1 = splat.i32x4 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   vpbroadcastd %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   vpbroadcastd %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i64(i64) -> i64x2 {
+block0(v0: i64):
+  v1 = splat.i64x2 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movq    %rdi, %xmm2
+;   vmovddup %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movq %rdi, %xmm2
+;   vmovddup %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_f32(f32) -> f32x4 {
+block0(v0: f32):
+  v1 = splat.f32x4 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vbroadcastss %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vbroadcastss %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_f64(f64) -> f64x2 {
+block0(v0: f64):
+  v1 = splat.f64x2 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vmovddup %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vmovddup %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i8(i64) -> i8x16 {
+block0(v0: i64):
+  v1 = load.i8 v0
+  v2 = splat.i8x16 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vpbroadcastb 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vpbroadcastb (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i16(i64) -> i16x8 {
+block0(v0: i64):
+  v1 = load.i16 v0
+  v2 = splat.i16x8 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vpbroadcastw 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vpbroadcastw (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i32(i64) -> i32x4 {
+block0(v0: i64):
+  v1 = load.i32 v0
+  v2 = splat.i32x4 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vbroadcastss 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vbroadcastss (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i64(i64) -> i64x2 {
+block0(v0: i64):
+  v1 = load.i64 v0
+  v2 = splat.i64x2 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vmovddup 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vmovddup (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_f32(i64) -> f32x4 {
+block0(v0: i64):
+  v1 = load.f32 v0
+  v2 = splat.f32x4 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vbroadcastss 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vbroadcastss (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_f64(i64) -> f64x2 {
+block0(v0: i64):
+  v1 = load.f64 v0
+  v2 = splat.f64x2 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vmovddup 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vmovddup (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/simd-splat.clif b/cranelift/filetests/filetests/isa/x64/simd-splat.clif
new file mode 100644
index 000000000..8bb3b0890
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/simd-splat.clif
@@ -0,0 +1,338 @@
+test compile precise-output
+set enable_simd
+target x86_64
+
+function %splat_i8(i8) -> i8x16 {
+block0(v0: i8):
+  v1 = splat.i8x16 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm0
+;   uninit  %xmm5
+;   pxor    %xmm5, %xmm5, %xmm5
+;   pshufb  %xmm0, %xmm5, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm0
+;   pxor %xmm5, %xmm5
+;   pshufb %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i16(i16) -> i16x8 {
+block0(v0: i16):
+  v1 = splat.i16x8 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   pshuflw $0, %xmm2, %xmm4
+;   pshufd  $0, %xmm4, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   pshuflw $0, %xmm2, %xmm4
+;   pshufd $0, %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i32(i32) -> i32x4 {
+block0(v0: i32):
+  v1 = splat.i32x4 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movd    %edi, %xmm2
+;   pshufd  $0, %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movd %edi, %xmm2
+;   pshufd $0, %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_i64(i64) -> i64x2 {
+block0(v0: i64):
+  v1 = splat.i64x2 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movq    %rdi, %xmm2
+;   movddup %xmm2, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movq %rdi, %xmm2
+;   movddup %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_f32(f32) -> f32x4 {
+block0(v0: f32):
+  v1 = splat.f32x4 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   shufps  $0, %xmm0, %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   shufps $0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %splat_f64(f64) -> f64x2 {
+block0(v0: f64):
+  v1 = splat.f64x2 v0
+  return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movddup %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movddup %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i8(i64) -> i8x16 {
+block0(v0: i64):
+  v1 = load.i8 v0
+  v2 = splat.i8x16 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   uninit  %xmm0
+;   pinsrb  $0, %xmm0, 0(%rdi), %xmm0
+;   uninit  %xmm7
+;   pxor    %xmm7, %xmm7, %xmm7
+;   pshufb  %xmm0, %xmm7, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   pinsrb $0, (%rdi), %xmm0 ; trap: heap_oob
+;   pxor %xmm7, %xmm7
+;   pshufb %xmm7, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i16(i64) -> i16x8 {
+block0(v0: i64):
+  v1 = load.i16 v0
+  v2 = splat.i16x8 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   uninit  %xmm3
+;   pinsrw  $0, %xmm3, 0(%rdi), %xmm3
+;   pshuflw $0, %xmm3, %xmm6
+;   pshufd  $0, %xmm6, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   pinsrw $0, (%rdi), %xmm3 ; trap: heap_oob
+;   pshuflw $0, %xmm3, %xmm6
+;   pshufd $0, %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i32(i64) -> i32x4 {
+block0(v0: i64):
+  v1 = load.i32 v0
+  v2 = splat.i32x4 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm0
+;   shufps  $0, %xmm0, %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm0 ; trap: heap_oob
+;   shufps $0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_i64(i64) -> i64x2 {
+block0(v0: i64):
+  v1 = load.i64 v0
+  v2 = splat.i64x2 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movddup 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movddup (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_f32(i64) -> f32x4 {
+block0(v0: i64):
+  v1 = load.f32 v0
+  v2 = splat.f32x4 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm0
+;   shufps  $0, %xmm0, %xmm0, %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm0 ; trap: heap_oob
+;   shufps $0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %load_splat_f64(i64) -> f64x2 {
+block0(v0: i64):
+  v1 = load.f64 v0
+  v2 = splat.f64x2 v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movddup 0(%rdi), %xmm0
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movddup (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/srem-checked.clif b/cranelift/filetests/filetests/isa/x64/srem-checked.clif
deleted file mode 100644
index e4bb829b3..000000000
--- a/cranelift/filetests/filetests/isa/x64/srem-checked.clif
+++ /dev/null
@@ -1,300 +0,0 @@
-test compile precise-output
-set avoid_div_traps=true
-target x86_64
-
-function %f1(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   cbw %al, %al
-;   testb   %sil, %sil
-;   jnz ; ud2 int_divz ;
-;   checked_srem_seq %al, %sil, %al
-;   shrq    $8, %rax, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   cbtw
-;   testb %sil, %sil
-;   jne 0x14
-;   ud2 ; trap: int_divz
-;   cmpb $0xff, %sil
-;   jne 0x28
-;   movl $0, %eax
-;   jmp 0x2b
-;   idivb %sil ; trap: int_divz
-;   shrq $8, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f2(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   testw   %si, %si
-;   jnz ; ud2 int_divz ;
-;   movq    %rdi, %rax
-;   cwd %ax, %dx
-;   checked_srem_seq %ax, %dx, %si, %ax, %dx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   testw %si, %si
-;   jne 0xf
-;   ud2 ; trap: int_divz
-;   movq %rdi, %rax
-;   cwtd
-;   cmpw $-1, %si
-;   jne 0x28
-;   movl $0, %edx
-;   jmp 0x2b
-;   idivw %si ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f3(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   testl   %esi, %esi
-;   jnz ; ud2 int_divz ;
-;   movq    %rdi, %rax
-;   cdq %eax, %edx
-;   checked_srem_seq %eax, %edx, %esi, %eax, %edx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   testl %esi, %esi
-;   jne 0xe
-;   ud2 ; trap: int_divz
-;   movq %rdi, %rax
-;   cltd
-;   cmpl $-1, %esi
-;   jne 0x25
-;   movl $0, %edx
-;   jmp 0x27
-;   idivl %esi ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f4(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   testq   %rsi, %rsi
-;   jnz ; ud2 int_divz ;
-;   movq    %rdi, %rax
-;   cqo %rax, %rdx
-;   checked_srem_seq %rax, %rdx, %rsi, %rax, %rdx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   testq %rsi, %rsi
-;   jne 0xf
-;   ud2 ; trap: int_divz
-;   movq %rdi, %rax
-;   cqto
-;   cmpq $-1, %rsi
-;   jne 0x28
-;   movl $0, %edx
-;   jmp 0x2b
-;   idivq %rsi ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i8_imm(i8) -> i8 {
-block0(v0: i8):
-  v1 = iconst.i8 17
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   cbw %al, %al
-;   movl    $17, %edx
-;   idiv    %al, %dl, %al
-;   shrq    $8, %rax, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   cbtw
-;   movl $0x11, %edx
-;   idivb %dl ; trap: int_divz
-;   shrq $8, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i16_imm(i16) -> i16 {
-block0(v0: i16):
-  v1 = iconst.i16 17
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   cwd %ax, %dx
-;   movl    $17, %r8d
-;   idiv    %ax, %dx, %r8w, %ax, %dx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   cwtd
-;   movl $0x11, %r8d
-;   idivw %r8w ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i32_imm(i32) -> i32 {
-block0(v0: i32):
-  v1 = iconst.i32 17
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   cdq %eax, %edx
-;   movl    $17, %r8d
-;   idiv    %eax, %edx, %r8d, %eax, %edx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   cltd
-;   movl $0x11, %r8d
-;   idivl %r8d ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i64_imm(i64) -> i64 {
-block0(v0: i64):
-  v1 = iconst.i64 17
-  v2 = srem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   cqo %rax, %rdx
-;   movl    $17, %r8d
-;   idiv    %rax, %rdx, %r8, %rax, %rdx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   cqto
-;   movl $0x11, %r8d
-;   idivq %r8 ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
diff --git a/cranelift/filetests/filetests/isa/x64/srem.clif b/cranelift/filetests/filetests/isa/x64/srem.clif
index 973a9f0be..14ed4efee 100644
--- a/cranelift/filetests/filetests/isa/x64/srem.clif
+++ b/cranelift/filetests/filetests/isa/x64/srem.clif
@@ -155,7 +155,7 @@ block0(v0: i8):
 ;   movq    %rdi, %rax
 ;   cbw %al, %al
 ;   movl    $17, %edx
-;   idiv    %al, %dl, %al
+;   idiv    %al, %dl, %al ; trap=int_divz
 ;   shrq    $8, %rax, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -189,7 +189,7 @@ block0(v0: i16):
 ;   movq    %rdi, %rax
 ;   cwd %ax, %dx
 ;   movl    $17, %r8d
-;   idiv    %ax, %dx, %r8w, %ax, %dx
+;   idiv    %ax, %dx, %r8w, %ax, %dx ; trap=int_divz
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -223,7 +223,7 @@ block0(v0: i32):
 ;   movq    %rdi, %rax
 ;   cdq %eax, %edx
 ;   movl    $17, %r8d
-;   idiv    %eax, %edx, %r8d, %eax, %edx
+;   idiv    %eax, %edx, %r8d, %eax, %edx ; trap=int_divz
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -257,7 +257,7 @@ block0(v0: i64):
 ;   movq    %rdi, %rax
 ;   cqo %rax, %rdx
 ;   movl    $17, %r8d
-;   idiv    %rax, %rdx, %r8, %rax, %rdx
+;   idiv    %rax, %rdx, %r8, %rax, %rdx ; trap=int_divz
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
diff --git a/cranelift/filetests/filetests/isa/x64/table.clif b/cranelift/filetests/filetests/isa/x64/table.clif
index 101debb9b..0bfe7a35f 100644
--- a/cranelift/filetests/filetests/isa/x64/table.clif
+++ b/cranelift/filetests/filetests/isa/x64/table.clif
@@ -26,11 +26,10 @@ block0(v0: i32, v1: r64, v2: i64):
 ; block1:
 ;   movl    %edi, %ecx
 ;   movq    0(%rdx), %rax
-;   movq    %rax, %rdx
-;   addq    %rdx, %rcx, %rdx
+;   lea     0(%rax,%rcx,1), %rcx
 ;   cmpl    %r11d, %edi
-;   cmovnbq %rax, %rdx, %rdx
-;   movq    %rsi, 0(%rdx)
+;   cmovnbq %rax, %rcx, %rcx
+;   movq    %rsi, 0(%rcx)
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -44,18 +43,17 @@ block0(v0: i32, v1: r64, v2: i64):
 ; block1: ; offset 0x4
 ;   movl 8(%rdx), %r11d
 ;   cmpl %r11d, %edi
-;   jae 0x2b
+;   jae 0x28
 ; block2: ; offset 0x11
 ;   movl %edi, %ecx
 ;   movq (%rdx), %rax
-;   movq %rax, %rdx
-;   addq %rcx, %rdx
+;   addq %rax, %rcx
 ;   cmpl %r11d, %edi
-;   cmovaeq %rax, %rdx
-;   movq %rsi, (%rdx)
+;   cmovaeq %rax, %rcx
+;   movq %rsi, (%rcx)
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
-; block3: ; offset 0x2b
+; block3: ; offset 0x28
 ;   ud2 ; trap: table_oob
 
diff --git a/cranelift/filetests/filetests/isa/x64/udiv-checked.clif b/cranelift/filetests/filetests/isa/x64/udiv-checked.clif
deleted file mode 100644
index 4eec243fb..000000000
--- a/cranelift/filetests/filetests/isa/x64/udiv-checked.clif
+++ /dev/null
@@ -1,264 +0,0 @@
-test compile precise-output
-set avoid_div_traps=true
-target x86_64
-
-function %f1(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movzbl  %dil, %eax
-;   testb   %sil, %sil
-;   jnz ; ud2 int_divz ;
-;   div     %al, %sil, %al
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movzbl %dil, %eax
-;   testb %sil, %sil
-;   jne 0x13
-;   ud2 ; trap: int_divz
-;   divb %sil ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f2(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   testw   %si, %si
-;   jnz ; ud2 int_divz ;
-;   div     %ax, %dx, %si, %ax, %dx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   testw %si, %si
-;   jne 0x15
-;   ud2 ; trap: int_divz
-;   divw %si ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f3(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   testl   %esi, %esi
-;   jnz ; ud2 int_divz ;
-;   div     %eax, %edx, %esi, %eax, %edx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   testl %esi, %esi
-;   jne 0x14
-;   ud2 ; trap: int_divz
-;   divl %esi ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f4(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   testq   %rsi, %rsi
-;   jnz ; ud2 int_divz ;
-;   div     %rax, %rdx, %rsi, %rax, %rdx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   testq %rsi, %rsi
-;   jne 0x15
-;   ud2 ; trap: int_divz
-;   divq %rsi ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i8_imm(i8) -> i8 {
-block0(v0: i8):
-  v1 = iconst.i8 17
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movzbl  %dil, %eax
-;   movl    $17, %edx
-;   div     %al, %dl, %al
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movzbl %dil, %eax
-;   movl $0x11, %edx
-;   divb %dl ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i16_imm(i16) -> i16 {
-block0(v0: i16):
-  v1 = iconst.i16 17
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   movl    $17, %r8d
-;   div     %ax, %dx, %r8w, %ax, %dx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   movl $0x11, %r8d
-;   divw %r8w ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i32_imm(i32) -> i32 {
-block0(v0: i32):
-  v1 = iconst.i32 17
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   movl    $17, %r8d
-;   div     %eax, %edx, %r8d, %eax, %edx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   movl $0x11, %r8d
-;   divl %r8d ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i64_imm(i64) -> i64 {
-block0(v0: i64):
-  v1 = iconst.i64 17
-  v2 = udiv v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   movl    $17, %r8d
-;   div     %rax, %rdx, %r8, %rax, %rdx
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   movl $0x11, %r8d
-;   divq %r8 ; trap: int_divz
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
diff --git a/cranelift/filetests/filetests/isa/x64/udiv.clif b/cranelift/filetests/filetests/isa/x64/udiv.clif
index 391abff20..bf3ec0820 100644
--- a/cranelift/filetests/filetests/isa/x64/udiv.clif
+++ b/cranelift/filetests/filetests/isa/x64/udiv.clif
@@ -12,7 +12,7 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movzbl  %dil, %eax
-;   div     %al, %sil, %al
+;   div     %al, %sil, %al ; trap=int_divz
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -40,7 +40,7 @@ block0(v0: i16, v1: i16):
 ; block0:
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %ax, %dx, %si, %ax, %dx
+;   div     %ax, %dx, %si, %ax, %dx ; trap=int_divz
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -69,7 +69,7 @@ block0(v0: i32, v1: i32):
 ; block0:
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %eax, %edx, %esi, %eax, %edx
+;   div     %eax, %edx, %esi, %eax, %edx ; trap=int_divz
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -98,7 +98,7 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %rax, %rdx, %rsi, %rax, %rdx
+;   div     %rax, %rdx, %rsi, %rax, %rdx ; trap=int_divz
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/udivrem.clif b/cranelift/filetests/filetests/isa/x64/udivrem.clif
index d0368a430..4d0708e89 100644
--- a/cranelift/filetests/filetests/isa/x64/udivrem.clif
+++ b/cranelift/filetests/filetests/isa/x64/udivrem.clif
@@ -15,10 +15,10 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movzbl  %dil, %eax
-;   div     %al, %sil, %al
+;   div     %al, %sil, %al ; trap=int_divz
 ;   movq    %rax, %r11
 ;   movzbl  %dil, %eax
-;   div     %al, %sil, %al
+;   div     %al, %sil, %al ; trap=int_divz
 ;   movq    %rax, %rdx
 ;   shrq    $8, %rdx, %rdx
 ;   movq    %r11, %rax
@@ -56,11 +56,11 @@ block0(v0: i16, v1: i16):
 ; block0:
 ;   xorq    %rdx, %rdx, %rdx
 ;   movq    %rdi, %rax
-;   div     %ax, %dx, %si, %ax, %dx
+;   div     %ax, %dx, %si, %ax, %dx ; trap=int_divz
 ;   movq    %rax, %rcx
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %ax, %dx, %si, %ax, %dx
+;   div     %ax, %dx, %si, %ax, %dx ; trap=int_divz
 ;   movq    %rcx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -96,11 +96,11 @@ block0(v0: i32, v1: i32):
 ; block0:
 ;   xorq    %rdx, %rdx, %rdx
 ;   movq    %rdi, %rax
-;   div     %eax, %edx, %esi, %eax, %edx
+;   div     %eax, %edx, %esi, %eax, %edx ; trap=int_divz
 ;   movq    %rax, %rcx
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %eax, %edx, %esi, %eax, %edx
+;   div     %eax, %edx, %esi, %eax, %edx ; trap=int_divz
 ;   movq    %rcx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -136,11 +136,11 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   xorq    %rdx, %rdx, %rdx
 ;   movq    %rdi, %rax
-;   div     %rax, %rdx, %rsi, %rax, %rdx
+;   div     %rax, %rdx, %rsi, %rax, %rdx ; trap=int_divz
 ;   movq    %rax, %rcx
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %rax, %rdx, %rsi, %rax, %rdx
+;   div     %rax, %rdx, %rsi, %rax, %rdx ; trap=int_divz
 ;   movq    %rcx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
diff --git a/cranelift/filetests/filetests/isa/x64/uextend-elision.clif b/cranelift/filetests/filetests/isa/x64/uextend-elision.clif
index faf3a6763..d4e306f50 100644
--- a/cranelift/filetests/filetests/isa/x64/uextend-elision.clif
+++ b/cranelift/filetests/filetests/isa/x64/uextend-elision.clif
@@ -12,8 +12,7 @@ block0(v0: i32, v1: i32):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movq    %rdi, %rax
-;   addl    %eax, %esi, %eax
+;   lea     0(%rdi,%rsi,1), %eax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -23,8 +22,7 @@ block0(v0: i32, v1: i32):
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   addl %esi, %eax
+;   leal (%rdi, %rsi), %eax
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
diff --git a/cranelift/filetests/filetests/isa/x64/urem-checked.clif b/cranelift/filetests/filetests/isa/x64/urem-checked.clif
deleted file mode 100644
index df6e20e1c..000000000
--- a/cranelift/filetests/filetests/isa/x64/urem-checked.clif
+++ /dev/null
@@ -1,280 +0,0 @@
-test compile precise-output
-set avoid_div_traps=true
-target x86_64
-
-function %f1(i8, i8) -> i8 {
-block0(v0: i8, v1: i8):
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movzbl  %dil, %eax
-;   testb   %sil, %sil
-;   jnz ; ud2 int_divz ;
-;   div     %al, %sil, %al
-;   shrq    $8, %rax, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movzbl %dil, %eax
-;   testb %sil, %sil
-;   jne 0x13
-;   ud2 ; trap: int_divz
-;   divb %sil ; trap: int_divz
-;   shrq $8, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f2(i16, i16) -> i16 {
-block0(v0: i16, v1: i16):
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   testw   %si, %si
-;   jnz ; ud2 int_divz ;
-;   div     %ax, %dx, %si, %ax, %dx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   testw %si, %si
-;   jne 0x15
-;   ud2 ; trap: int_divz
-;   divw %si ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f3(i32, i32) -> i32 {
-block0(v0: i32, v1: i32):
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   testl   %esi, %esi
-;   jnz ; ud2 int_divz ;
-;   div     %eax, %edx, %esi, %eax, %edx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   testl %esi, %esi
-;   jne 0x14
-;   ud2 ; trap: int_divz
-;   divl %esi ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %f4(i64, i64) -> i64 {
-block0(v0: i64, v1: i64):
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   testq   %rsi, %rsi
-;   jnz ; ud2 int_divz ;
-;   div     %rax, %rdx, %rsi, %rax, %rdx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   testq %rsi, %rsi
-;   jne 0x15
-;   ud2 ; trap: int_divz
-;   divq %rsi ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i8_imm(i8) -> i8 {
-block0(v0: i8):
-  v1 = iconst.i8 17
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movzbl  %dil, %eax
-;   movl    $17, %edx
-;   div     %al, %dl, %al
-;   shrq    $8, %rax, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movzbl %dil, %eax
-;   movl $0x11, %edx
-;   divb %dl ; trap: int_divz
-;   shrq $8, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i16_imm(i16) -> i16 {
-block0(v0: i16):
-  v1 = iconst.i16 17
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   movl    $17, %r8d
-;   div     %ax, %dx, %r8w, %ax, %dx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   movl $0x11, %r8d
-;   divw %r8w ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i32_imm(i32) -> i32 {
-block0(v0: i32):
-  v1 = iconst.i32 17
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   movl    $17, %r8d
-;   div     %eax, %edx, %r8d, %eax, %edx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   movl $0x11, %r8d
-;   divl %r8d ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
-function %i64_imm(i64) -> i64 {
-block0(v0: i64):
-  v1 = iconst.i64 17
-  v2 = urem v0, v1
-  return v2
-}
-
-; VCode:
-;   pushq   %rbp
-;   movq    %rsp, %rbp
-; block0:
-;   movq    %rdi, %rax
-;   xorq    %rdx, %rdx, %rdx
-;   movl    $17, %r8d
-;   div     %rax, %rdx, %r8, %rax, %rdx
-;   movq    %rdx, %rax
-;   movq    %rbp, %rsp
-;   popq    %rbp
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   pushq %rbp
-;   movq %rsp, %rbp
-; block1: ; offset 0x4
-;   movq %rdi, %rax
-;   xorq %rdx, %rdx
-;   movl $0x11, %r8d
-;   divq %r8 ; trap: int_divz
-;   movq %rdx, %rax
-;   movq %rbp, %rsp
-;   popq %rbp
-;   retq
-
diff --git a/cranelift/filetests/filetests/isa/x64/urem.clif b/cranelift/filetests/filetests/isa/x64/urem.clif
index 63daeaade..7cf197041 100644
--- a/cranelift/filetests/filetests/isa/x64/urem.clif
+++ b/cranelift/filetests/filetests/isa/x64/urem.clif
@@ -12,7 +12,7 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movzbl  %dil, %eax
-;   div     %al, %sil, %al
+;   div     %al, %sil, %al ; trap=int_divz
 ;   shrq    $8, %rax, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -42,7 +42,7 @@ block0(v0: i16, v1: i16):
 ; block0:
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %ax, %dx, %si, %ax, %dx
+;   div     %ax, %dx, %si, %ax, %dx ; trap=int_divz
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -73,7 +73,7 @@ block0(v0: i32, v1: i32):
 ; block0:
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %eax, %edx, %esi, %eax, %edx
+;   div     %eax, %edx, %esi, %eax, %edx ; trap=int_divz
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -104,7 +104,7 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   movq    %rdi, %rax
 ;   xorq    %rdx, %rdx, %rdx
-;   div     %rax, %rdx, %rsi, %rax, %rdx
+;   div     %rax, %rdx, %rsi, %rax, %rdx ; trap=int_divz
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index b53718fbb..3010a8185 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -45,17 +45,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rdx), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rdi
-;;   addq    %rdi, const(0), %rdi
-;;   movl    %esi, 0(%rdi,%r11,1)
+;;   addq    %r8, 0(%rdx), %r8
+;;   movl    $-65536, %eax
+;;   movl    %esi, 0(%r8,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,17 +70,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rsi), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %rsi
-;;   addq    %rsi, const(0), %rsi
-;;   movl    0(%rsi,%r11,1), %eax
+;;   addq    %r8, 0(%rsi), %r8
+;;   movl    $-65536, %edi
+;;   movl    0(%r8,%rdi,1), %eax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index b8c74b7a2..5c3c1ac1e 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,17 +45,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rdx), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rdi
-;;   addq    %rdi, const(0), %rdi
-;;   movb    %sil, 0(%rdi,%r11,1)
+;;   addq    %r8, 0(%rdx), %r8
+;;   movl    $-65536, %eax
+;;   movb    %sil, 0(%r8,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,17 +70,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rsi), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %rsi
-;;   addq    %rsi, const(0), %rsi
-;;   movzbq  0(%rsi,%r11,1), %rax
+;;   addq    %r8, 0(%rsi), %r8
+;;   movl    $-65536, %edi
+;;   movzbq  0(%r8,%rdi,1), %rax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 8bc688f26..3c42b63e6 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -48,13 +48,12 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4100, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rcx, %rcx, %rcx
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rcx
+;;   xorq    %rdx, %rdx, %rdx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r11, %r11
-;;   movl    %esi, 0(%r11)
+;;   cmovnbeq %rdx, %rcx, %rcx
+;;   movl    %esi, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -70,15 +69,14 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4100, %rax
 ;;   addq    %rax, 8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rsi, %rsi, %rsi
+;;   movq    0(%rsi), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rsi
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movl    0(%r11), %eax
+;;   cmovnbeq %rcx, %rsi, %rsi
+;;   movl    0(%rsi), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index f4f79fff1..412b47919 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movl    %esi, 0(%r8)
+;;   movq    8(%rdx), %rcx
+;;   addq    %r11, 0(%rdx), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movl    %esi, 0(%rdx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movl    0(%r8), %eax
+;;   movq    8(%rsi), %rcx
+;;   addq    %r11, 0(%rsi), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movl    0(%rdx), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index f10feb9cb..69169611b 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -48,13 +48,12 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4097, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rcx, %rcx, %rcx
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rcx
+;;   xorq    %rdx, %rdx, %rdx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r11, %r11
-;;   movb    %sil, 0(%r11)
+;;   cmovnbeq %rdx, %rcx, %rcx
+;;   movb    %sil, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -70,15 +69,14 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4097, %rax
 ;;   addq    %rax, 8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rsi, %rsi, %rsi
+;;   movq    0(%rsi), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rsi
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movzbq  0(%r11), %rax
+;;   cmovnbeq %rcx, %rsi, %rsi
+;;   movzbq  0(%rsi), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index c68204b5d..a4adf2663 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movb    %sil, 0(%r8)
+;;   movq    8(%rdx), %rcx
+;;   addq    %r11, 0(%rdx), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movb    %sil, 0(%rdx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movzbq  0(%r8), %rax
+;;   movq    8(%rsi), %rcx
+;;   addq    %r11, 0(%rsi), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movzbq  0(%rdx), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 41697bf72..2b8019e85 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -45,17 +45,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rdx), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rdi
-;;   addq    %rdi, const(0), %rdi
-;;   movl    %esi, 0(%rdi,%r11,1)
+;;   addq    %r8, 0(%rdx), %r8
+;;   movl    $-65536, %eax
+;;   movl    %esi, 0(%r8,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,17 +70,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rsi), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %rsi
-;;   addq    %rsi, const(0), %rsi
-;;   movl    0(%rsi,%r11,1), %eax
+;;   addq    %r8, 0(%rsi), %r8
+;;   movl    $-65536, %edi
+;;   movl    0(%r8,%rdi,1), %eax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index cc2c6f792..29ff03b82 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,17 +45,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rdx), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rdi
-;;   addq    %rdi, const(0), %rdi
-;;   movb    %sil, 0(%rdi,%r11,1)
+;;   addq    %r8, 0(%rdx), %r8
+;;   movl    $-65536, %eax
+;;   movb    %sil, 0(%r8,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,17 +70,17 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r11d
-;;   movq    %r11, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r8d
+;;   movq    %r8, %r11
+;;   addq    %r11, const(0), %r11
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   cmpq    %rax, %rdi
+;;   movq    8(%rsi), %rdi
+;;   cmpq    %rdi, %r11
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %rsi
-;;   addq    %rsi, const(0), %rsi
-;;   movzbq  0(%rsi,%r11,1), %rax
+;;   addq    %r8, 0(%rsi), %r8
+;;   movl    $-65536, %edi
+;;   movzbq  0(%r8,%rdi,1), %rax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index e9cc1c103..9b8f9e4b3 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -48,13 +48,12 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4100, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rcx, %rcx, %rcx
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rcx
+;;   xorq    %rdx, %rdx, %rdx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r11, %r11
-;;   movl    %esi, 0(%r11)
+;;   cmovnbeq %rdx, %rcx, %rcx
+;;   movl    %esi, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -70,15 +69,14 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4100, %rax
 ;;   addq    %rax, 8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rsi, %rsi, %rsi
+;;   movq    0(%rsi), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rsi
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movl    0(%r11), %eax
+;;   cmovnbeq %rcx, %rsi, %rsi
+;;   movl    0(%rsi), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index f4ffb0d0f..37401d352 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movl    %esi, 0(%r8)
+;;   movq    8(%rdx), %rcx
+;;   addq    %r11, 0(%rdx), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movl    %esi, 0(%rdx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movl    0(%r8), %eax
+;;   movq    8(%rsi), %rcx
+;;   addq    %r11, 0(%rsi), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movl    0(%rdx), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index a5d43ce9c..99113750d 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -48,13 +48,12 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4097, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rcx, %rcx, %rcx
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rcx
+;;   xorq    %rdx, %rdx, %rdx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r11, %r11
-;;   movb    %sil, 0(%r11)
+;;   cmovnbeq %rdx, %rcx, %rcx
+;;   movb    %sil, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -70,15 +69,14 @@
 ;;   movl    %edi, %edi
 ;;   movabsq $-4097, %rax
 ;;   addq    %rax, 8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, $4096, %r11
-;;   xorq    %rsi, %rsi, %rsi
+;;   movq    0(%rsi), %rcx
+;;   lea     4096(%rcx,%rdi,1), %rsi
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movzbq  0(%r11), %rax
+;;   cmovnbeq %rcx, %rsi, %rsi
+;;   movzbq  0(%rsi), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index a67a3975a..05ca250ad 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rdx), %rax
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movb    %sil, 0(%r8)
+;;   movq    8(%rdx), %rcx
+;;   addq    %r11, 0(%rdx), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movb    %sil, 0(%rdx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movl    %edi, %r8d
-;;   movq    %r8, %rdi
-;;   addq    %rdi, const(1), %rdi
+;;   movl    %edi, %r11d
+;;   movq    %r11, %rax
+;;   addq    %rax, const(0), %rax
 ;;   jnb ; ud2 heap_oob ;
-;;   movq    8(%rsi), %rax
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, const(0), %r8
-;;   xorq    %rcx, %rcx, %rcx
-;;   cmpq    %rax, %rdi
-;;   cmovnbeq %rcx, %r8, %r8
-;;   movzbq  0(%r8), %rax
+;;   movq    8(%rsi), %rcx
+;;   addq    %r11, 0(%rsi), %r11
+;;   movl    $-65536, %edx
+;;   lea     0(%r11,%rdx,1), %rdx
+;;   xorq    %r8, %r8, %r8
+;;   cmpq    %rcx, %rax
+;;   cmovnbeq %r8, %rdx, %rdx
+;;   movzbq  0(%rdx), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 583769bad..277b469a8 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -46,15 +46,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rax
-;;   addq    %rax, const(0), %rax
-;;   movl    %esi, 0(%rax,%rdi,1)
+;;   addq    %rdi, 0(%rdx), %rdi
+;;   movl    $-65536, %eax
+;;   movl    %esi, 0(%rdi,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,15 +70,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   movl    0(%r11,%rdi,1), %eax
+;;   addq    %rdi, 0(%rsi), %rdi
+;;   movl    $-65536, %esi
+;;   movl    0(%rdi,%rsi,1), %eax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index fb540d9fb..a790538c9 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -46,15 +46,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rax
-;;   addq    %rax, const(0), %rax
-;;   movb    %sil, 0(%rax,%rdi,1)
+;;   addq    %rdi, 0(%rdx), %rdi
+;;   movl    $-65536, %eax
+;;   movb    %sil, 0(%rdi,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,15 +70,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   movzbq  0(%r11,%rdi,1), %rax
+;;   addq    %rdi, 0(%rsi), %rdi
+;;   movl    $-65536, %esi
+;;   movzbq  0(%rdi,%rsi,1), %rax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 6a2274169..ca9a9ac97 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -47,13 +47,12 @@
 ;; block0:
 ;;   movabsq $-4100, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rdx), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %r11
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movl    %esi, 0(%r10)
+;;   cmovnbeq %rcx, %r11, %r11
+;;   movl    %esi, 0(%r11)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -66,18 +65,16 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rsi, %rax
-;;   movabsq $-4100, %rsi
-;;   addq    %rsi, 8(%rax), %rsi
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rax), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
-;;   cmpq    %rsi, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movl    0(%r10), %eax
+;;   movabsq $-4100, %rcx
+;;   addq    %rcx, 8(%rsi), %rcx
+;;   movq    0(%rsi), %rsi
+;;   lea     4096(%rsi,%rdi,1), %r11
+;;   xorq    %rax, %rax, %rax
+;;   cmpq    %rcx, %rdi
+;;   cmovnbeq %rax, %r11, %r11
+;;   movl    0(%r11), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 0a1c3e7e4..369f5146a 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %r8
+;;   addq    %r8, const(0), %r8
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, const(0), %r11
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rdx), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
 ;;   xorq    %rdi, %rdi, %rdi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rdi, %r11, %r11
-;;   movl    %esi, 0(%r11)
+;;   cmpq    %rax, %r8
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movl    %esi, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %rdx
+;;   addq    %rdx, const(0), %rdx
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   xorq    %rsi, %rsi, %rsi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movl    0(%r11), %eax
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rsi), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
+;;   xorq    %rdi, %rdi, %rdi
+;;   cmpq    %rax, %rdx
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movl    0(%rcx), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 7e1de03d1..28522fed9 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -47,13 +47,12 @@
 ;; block0:
 ;;   movabsq $-4097, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rdx), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %r11
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movb    %sil, 0(%r10)
+;;   cmovnbeq %rcx, %r11, %r11
+;;   movb    %sil, 0(%r11)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -66,18 +65,16 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rsi, %rax
-;;   movabsq $-4097, %rsi
-;;   addq    %rsi, 8(%rax), %rsi
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rax), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
-;;   cmpq    %rsi, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movzbq  0(%r10), %rax
+;;   movabsq $-4097, %rcx
+;;   addq    %rcx, 8(%rsi), %rcx
+;;   movq    0(%rsi), %rsi
+;;   lea     4096(%rsi,%rdi,1), %r11
+;;   xorq    %rax, %rax, %rax
+;;   cmpq    %rcx, %rdi
+;;   cmovnbeq %rax, %r11, %r11
+;;   movzbq  0(%r11), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index b29744517..e3aa79c86 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %r8
+;;   addq    %r8, const(0), %r8
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, const(0), %r11
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rdx), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
 ;;   xorq    %rdi, %rdi, %rdi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rdi, %r11, %r11
-;;   movb    %sil, 0(%r11)
+;;   cmpq    %rax, %r8
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movb    %sil, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %rdx
+;;   addq    %rdx, const(0), %rdx
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   xorq    %rsi, %rsi, %rsi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movzbq  0(%r11), %rax
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rsi), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
+;;   xorq    %rdi, %rdi, %rdi
+;;   cmpq    %rax, %rdx
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movzbq  0(%rcx), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 3f4ec47b0..95d01f56a 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -46,15 +46,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rax
-;;   addq    %rax, const(0), %rax
-;;   movl    %esi, 0(%rax,%rdi,1)
+;;   addq    %rdi, 0(%rdx), %rdi
+;;   movl    $-65536, %eax
+;;   movl    %esi, 0(%rdi,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,15 +70,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   movl    0(%r11,%rdi,1), %eax
+;;   addq    %rdi, 0(%rsi), %rdi
+;;   movl    $-65536, %esi
+;;   movl    0(%rdi,%rsi,1), %eax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 9d2072729..ebc17c889 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -46,15 +46,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rdx), %rax
-;;   addq    %rax, const(0), %rax
-;;   movb    %sil, 0(%rax,%rdi,1)
+;;   addq    %rdi, 0(%rdx), %rdi
+;;   movl    $-65536, %eax
+;;   movb    %sil, 0(%rdi,%rax,1)
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
@@ -70,15 +70,15 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movq    %rdi, %r10
-;;   addq    %r10, const(1), %r10
+;;   addq    %r10, const(0), %r10
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %r11
 ;;   cmpq    %r11, %r10
 ;;   jnbe    label3; j label1
 ;; block1:
-;;   movq    0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   movzbq  0(%r11,%rdi,1), %rax
+;;   addq    %rdi, 0(%rsi), %rdi
+;;   movl    $-65536, %esi
+;;   movzbq  0(%rdi,%rsi,1), %rax
 ;;   jmp     label2
 ;; block2:
 ;;   movq    %rbp, %rsp
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 7e7b96928..99f3c89c1 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -47,13 +47,12 @@
 ;; block0:
 ;;   movabsq $-4100, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rdx), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %r11
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movl    %esi, 0(%r10)
+;;   cmovnbeq %rcx, %r11, %r11
+;;   movl    %esi, 0(%r11)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -66,18 +65,16 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rsi, %rax
-;;   movabsq $-4100, %rsi
-;;   addq    %rsi, 8(%rax), %rsi
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rax), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
-;;   cmpq    %rsi, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movl    0(%r10), %eax
+;;   movabsq $-4100, %rcx
+;;   addq    %rcx, 8(%rsi), %rcx
+;;   movq    0(%rsi), %rsi
+;;   lea     4096(%rsi,%rdi,1), %r11
+;;   xorq    %rax, %rax, %rax
+;;   cmpq    %rcx, %rdi
+;;   cmovnbeq %rax, %r11, %r11
+;;   movl    0(%r11), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 636878960..95a7e4aff 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %r8
+;;   addq    %r8, const(0), %r8
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, const(0), %r11
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rdx), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
 ;;   xorq    %rdi, %rdi, %rdi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rdi, %r11, %r11
-;;   movl    %esi, 0(%r11)
+;;   cmpq    %rax, %r8
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movl    %esi, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %rdx
+;;   addq    %rdx, const(0), %rdx
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   xorq    %rsi, %rsi, %rsi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movl    0(%r11), %eax
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rsi), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
+;;   xorq    %rdi, %rdi, %rdi
+;;   cmpq    %rax, %rdx
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movl    0(%rcx), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index ba1cf0055..a0cffc83b 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -47,13 +47,12 @@
 ;; block0:
 ;;   movabsq $-4097, %rax
 ;;   addq    %rax, 8(%rdx), %rax
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rdx), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
+;;   movq    0(%rdx), %rcx
+;;   lea     4096(%rcx,%rdi,1), %r11
+;;   xorq    %rcx, %rcx, %rcx
 ;;   cmpq    %rax, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movb    %sil, 0(%r10)
+;;   cmovnbeq %rcx, %r11, %r11
+;;   movb    %sil, 0(%r11)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -66,18 +65,16 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rsi, %rax
-;;   movabsq $-4097, %rsi
-;;   addq    %rsi, 8(%rax), %rsi
-;;   movq    %rdi, %r10
-;;   addq    %r10, 0(%rax), %r10
-;;   addq    %r10, $4096, %r10
-;;   xorq    %r11, %r11, %r11
-;;   cmpq    %rsi, %rdi
-;;   cmovnbeq %r11, %r10, %r10
-;;   movzbq  0(%r10), %rax
+;;   movabsq $-4097, %rcx
+;;   addq    %rcx, 8(%rsi), %rcx
+;;   movq    0(%rsi), %rsi
+;;   lea     4096(%rsi,%rdi,1), %r11
+;;   xorq    %rax, %rax, %rax
+;;   cmpq    %rcx, %rdi
+;;   cmovnbeq %rax, %r11, %r11
+;;   movzbq  0(%r11), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 003dd6aa8..20977fe01 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,17 +45,18 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %r8
+;;   addq    %r8, const(0), %r8
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rdx), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rdx), %r11
-;;   addq    %r11, const(0), %r11
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rdx), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
 ;;   xorq    %rdi, %rdi, %rdi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rdi, %r11, %r11
-;;   movb    %sil, 0(%r11)
+;;   cmpq    %rax, %r8
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movb    %sil, 0(%rcx)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -68,19 +69,20 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %rcx
-;;   addq    %rcx, const(1), %rcx
+;;   movq    %rdi, %rdx
+;;   addq    %rdx, const(0), %rdx
 ;;   jnb ; ud2 heap_oob ;
 ;;   movq    8(%rsi), %rax
-;;   movq    %rdi, %r11
-;;   addq    %r11, 0(%rsi), %r11
-;;   addq    %r11, const(0), %r11
-;;   xorq    %rsi, %rsi, %rsi
-;;   cmpq    %rax, %rcx
-;;   cmovnbeq %rsi, %r11, %r11
-;;   movzbq  0(%r11), %rax
+;;   movq    %rdi, %rcx
+;;   addq    %rcx, 0(%rsi), %rcx
+;;   movl    $-65536, %edi
+;;   lea     0(%rcx,%rdi,1), %rcx
+;;   xorq    %rdi, %rdi, %rdi
+;;   cmpq    %rax, %rdx
+;;   cmovnbeq %rdi, %rcx, %rcx
+;;   movzbq  0(%rcx), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 2f434668a..3a6c1b9dc 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -44,13 +44,12 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movl    %edi, %r11d
-;;   movq    %r11, %r9
-;;   addq    %r9, 0(%rdx), %r9
-;;   addq    %r9, $4096, %r9
-;;   xorq    %r10, %r10, %r10
+;;   movq    0(%rdx), %rdi
+;;   lea     4096(%rdi,%r11,1), %r10
+;;   xorq    %rdi, %rdi, %rdi
 ;;   cmpq    $268431356, %r11
-;;   cmovnbeq %r10, %r9, %r9
-;;   movl    %esi, 0(%r9)
+;;   cmovnbeq %rdi, %r10, %r10
+;;   movl    %esi, 0(%r10)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -64,15 +63,14 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movl    %edi, %r11d
-;;   movq    %r11, %r9
-;;   addq    %r9, 0(%rsi), %r9
-;;   addq    %r9, $4096, %r9
-;;   xorq    %r10, %r10, %r10
+;;   movq    0(%rsi), %rsi
+;;   lea     4096(%rsi,%r11,1), %r10
+;;   xorq    %rsi, %rsi, %rsi
 ;;   cmpq    $268431356, %r11
-;;   cmovnbeq %r10, %r9, %r9
-;;   movl    0(%r9), %eax
+;;   cmovnbeq %rsi, %r10, %r10
+;;   movl    0(%r10), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 7b8d88b48..70caad3ef 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -44,13 +44,12 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movl    %edi, %r11d
-;;   movq    %r11, %r9
-;;   addq    %r9, 0(%rdx), %r9
-;;   addq    %r9, $4096, %r9
-;;   xorq    %r10, %r10, %r10
+;;   movq    0(%rdx), %rdi
+;;   lea     4096(%rdi,%r11,1), %r10
+;;   xorq    %rdi, %rdi, %rdi
 ;;   cmpq    $268431359, %r11
-;;   cmovnbeq %r10, %r9, %r9
-;;   movb    %sil, 0(%r9)
+;;   cmovnbeq %rdi, %r10, %r10
+;;   movb    %sil, 0(%r10)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -64,15 +63,14 @@
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
 ;;   movl    %edi, %r11d
-;;   movq    %r11, %r9
-;;   addq    %r9, 0(%rsi), %r9
-;;   addq    %r9, $4096, %r9
-;;   xorq    %r10, %r10, %r10
+;;   movq    0(%rsi), %rsi
+;;   lea     4096(%rsi,%r11,1), %r10
+;;   xorq    %rsi, %rsi, %rsi
 ;;   cmpq    $268431359, %r11
-;;   cmovnbeq %r10, %r9, %r9
-;;   movzbq  0(%r9), %rax
+;;   cmovnbeq %rsi, %r10, %r10
+;;   movzbq  0(%r10), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
index 4bf94389c..bdab2846d 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -65,4 +65,4 @@
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 3abcc96da..8f925ce9c 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -65,4 +65,4 @@
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 22ca45d73..068f359bc 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -65,4 +65,4 @@
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 9174a582c..818bd94e0 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -65,4 +65,4 @@
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index cb65508f6..cc461ab9f 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -43,13 +43,12 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rdx), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431356, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movl    %esi, 0(%r8)
+;;   cmovnbeq %r10, %r9, %r9
+;;   movl    %esi, 0(%r9)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -62,15 +61,14 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rsi), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431356, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movl    0(%r8), %eax
+;;   cmovnbeq %r10, %r9, %r9
+;;   movl    0(%r9), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index d706afe92..ed9ca6fad 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -43,13 +43,12 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rdx), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431359, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movb    %sil, 0(%r8)
+;;   cmovnbeq %r10, %r9, %r9
+;;   movb    %sil, 0(%r9)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -62,15 +61,14 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rsi), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431359, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movzbq  0(%r8), %rax
+;;   cmovnbeq %r10, %r9, %r9
+;;   movzbq  0(%r9), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 9758a1e0c..5917c8e75 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -43,13 +43,12 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rdx), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431356, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movl    %esi, 0(%r8)
+;;   cmovnbeq %r10, %r9, %r9
+;;   movl    %esi, 0(%r9)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -62,15 +61,14 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rsi), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431356, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movl    0(%r8), %eax
+;;   cmovnbeq %r10, %r9, %r9
+;;   movl    0(%r9), %eax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 29284edfc..16dd75e52 100644
--- a/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/x64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -43,13 +43,12 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rdx), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rdx), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431359, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movb    %sil, 0(%r8)
+;;   cmovnbeq %r10, %r9, %r9
+;;   movb    %sil, 0(%r9)
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
@@ -62,15 +61,14 @@
 ;;   movq    %rsp, %rbp
 ;;   unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 }
 ;; block0:
-;;   movq    %rdi, %r8
-;;   addq    %r8, 0(%rsi), %r8
-;;   addq    %r8, $4096, %r8
-;;   xorq    %r9, %r9, %r9
+;;   movq    0(%rsi), %r10
+;;   lea     4096(%r10,%rdi,1), %r9
+;;   xorq    %r10, %r10, %r10
 ;;   cmpq    $268431359, %rdi
-;;   cmovnbeq %r9, %r8, %r8
-;;   movzbq  0(%r8), %rax
+;;   cmovnbeq %r10, %r9, %r9
+;;   movzbq  0(%r9), %rax
 ;;   jmp     label1
 ;; block1:
 ;;   movq    %rbp, %rsp
 ;;   popq    %rbp
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/runtests/div-checks.clif b/cranelift/filetests/filetests/runtests/div-checks.clif
index 3a854adba..2c385fa19 100644
--- a/cranelift/filetests/filetests/runtests/div-checks.clif
+++ b/cranelift/filetests/filetests/runtests/div-checks.clif
@@ -1,13 +1,8 @@
 test run
-set avoid_div_traps=false
 target aarch64
 target s390x
 target x86_64
-target riscv64 
-
-
-; Tests that the `avoid_div_traps` flag prevents a trap when {s,u}rem is called
-; with INT_MIN % -1.
+target riscv64
 
 function %i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
diff --git a/cranelift/filetests/filetests/runtests/simd-extractlane.clif b/cranelift/filetests/filetests/runtests/simd-extractlane.clif
index 2216d68c8..1b15d01eb 100644
--- a/cranelift/filetests/filetests/runtests/simd-extractlane.clif
+++ b/cranelift/filetests/filetests/runtests/simd-extractlane.clif
@@ -100,3 +100,19 @@ block0(v0: f64x2):
     return v4
 }
 ; run: %extractlane_f64x2_through_stack([0x1.0 0x2.0]) == 0x1.0
+
+
+function %unaligned_extractlane() -> f64 {
+    ss0 = explicit_slot 24
+
+block0:
+    v0 = iconst.i64 0
+    stack_store.i64 v0, ss0+0
+    stack_store.i64 v0, ss0+8
+    stack_store.i64 v0, ss0+16
+
+    v1 = stack_load.f64x2 ss0+1
+    v2 = extractlane v1, 1
+    return v2
+}
+; run: %unaligned_extractlane() == 0.0
diff --git a/cranelift/filetests/filetests/runtests/simd-shuffle.clif b/cranelift/filetests/filetests/runtests/simd-shuffle.clif
index 2ef1671e2..cdf2adfc5 100644
--- a/cranelift/filetests/filetests/runtests/simd-shuffle.clif
+++ b/cranelift/filetests/filetests/runtests/simd-shuffle.clif
@@ -553,3 +553,13 @@ block0(v0: i64x2, v1: i64x2):
     return v5
 }
 ; run: %aarch64_rev64_words([0x0102030405060708 0x0807060504030201], [0 0]) == [0x0506070801020304 0x0403020108070605]
+
+function %pblendw_0b10011001(i16x8, i16x8) -> i16x8 {
+block0(v0: i16x8, v1: i16x8):
+    v2 = bitcast.i8x16 little v0
+    v3 = bitcast.i8x16 little v1
+    v4 = shuffle v2, v3, [16 17 2 3 4 5 22 23 24 25 10 11 12 13 30 31]
+    v5 = bitcast.i16x8 little v4
+    return v5
+}
+; run: %pblendw_0b10011001([1 2 3 4 5 6 7 8], [9 10 11 12 13 14 15 16]) == [9 2 3 12 13 6 7 16]
diff --git a/cranelift/filetests/filetests/runtests/simd-splat.clif b/cranelift/filetests/filetests/runtests/simd-splat.clif
index 37db142ec..de2b49fd4 100644
--- a/cranelift/filetests/filetests/runtests/simd-splat.clif
+++ b/cranelift/filetests/filetests/runtests/simd-splat.clif
@@ -4,6 +4,8 @@ target aarch64
 target s390x
 set enable_simd
 target x86_64 has_sse3 has_ssse3 has_sse41
+target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
+target x86_64 has_sse3 has_ssse3 has_sse41 has_avx has_avx2
 
 function %splat_i8x16(i8) -> i8x16 {
 block0(v0: i8):
diff --git a/cranelift/filetests/filetests/runtests/srem.clif b/cranelift/filetests/filetests/runtests/srem.clif
index 96b0f95fe..6d0a6217f 100644
--- a/cranelift/filetests/filetests/runtests/srem.clif
+++ b/cranelift/filetests/filetests/runtests/srem.clif
@@ -1,7 +1,5 @@
 test interpret
 test run
-; Test these inputs without div traps, it shouldn't affect normal inputs
-set avoid_div_traps
 target aarch64
 target s390x
 target x86_64
diff --git a/cranelift/filetests/filetests/runtests/urem.clif b/cranelift/filetests/filetests/runtests/urem.clif
index f0b6bb067..8ab17fc4e 100644
--- a/cranelift/filetests/filetests/runtests/urem.clif
+++ b/cranelift/filetests/filetests/runtests/urem.clif
@@ -4,11 +4,6 @@ target aarch64
 target s390x
 target x86_64
 target riscv64
-; Test these inputs without div traps, it shouldn't affect normal inputs
-set avoid_div_traps
-target aarch64
-target s390x
-target x86_64
 
 function %urem_i64(i64, i64) -> i64 {
 block0(v0: i64,v1: i64):
diff --git a/tests/all/traps.rs b/tests/all/traps.rs
index ae62280c6..ccceb7116 100644
--- a/tests/all/traps.rs
+++ b/tests/all/traps.rs
@@ -1185,3 +1185,97 @@ fn host_return_error_no_backtrace() -> Result<()> {
     assert!(f.call(&mut store, ()).is_err());
     Ok(())
 }
+
+#[test]
+fn div_plus_load_reported_right() -> Result<()> {
+    let engine = Engine::default();
+    let mut store = Store::new(&engine, ());
+    let module = Module::new(
+        &engine,
+        r#"
+            (module
+                (memory (export "memory") 1)
+                (func (export "i32.div_s") (param i32 i32) (result i32)
+                    (i32.div_s (local.get 0) (i32.load (local.get 1))))
+                (func (export "i32.div_u") (param i32 i32) (result i32)
+                    (i32.div_u (local.get 0) (i32.load (local.get 1))))
+                (func (export "i32.rem_s") (param i32 i32) (result i32)
+                    (i32.rem_s (local.get 0) (i32.load (local.get 1))))
+                (func (export "i32.rem_u") (param i32 i32) (result i32)
+                    (i32.rem_u (local.get 0) (i32.load (local.get 1))))
+            )
+        "#,
+    )?;
+    let instance = Instance::new(&mut store, &module, &[])?;
+    let memory = instance.get_memory(&mut store, "memory").unwrap();
+    let i32_div_s = instance.get_typed_func::<(i32, i32), i32>(&mut store, "i32.div_s")?;
+    let i32_div_u = instance.get_typed_func::<(u32, u32), u32>(&mut store, "i32.div_u")?;
+    let i32_rem_s = instance.get_typed_func::<(i32, i32), i32>(&mut store, "i32.rem_s")?;
+    let i32_rem_u = instance.get_typed_func::<(u32, u32), u32>(&mut store, "i32.rem_u")?;
+
+    memory.write(&mut store, 0, &1i32.to_le_bytes()).unwrap();
+    memory.write(&mut store, 4, &0i32.to_le_bytes()).unwrap();
+    memory.write(&mut store, 8, &(-1i32).to_le_bytes()).unwrap();
+
+    assert_eq!(i32_div_s.call(&mut store, (100, 0))?, 100);
+    assert_eq!(i32_div_u.call(&mut store, (101, 0))?, 101);
+    assert_eq!(i32_rem_s.call(&mut store, (102, 0))?, 0);
+    assert_eq!(i32_rem_u.call(&mut store, (103, 0))?, 0);
+
+    assert_trap(
+        i32_div_s.call(&mut store, (100, 4)),
+        Trap::IntegerDivisionByZero,
+    );
+    assert_trap(
+        i32_div_u.call(&mut store, (100, 4)),
+        Trap::IntegerDivisionByZero,
+    );
+    assert_trap(
+        i32_rem_s.call(&mut store, (100, 4)),
+        Trap::IntegerDivisionByZero,
+    );
+    assert_trap(
+        i32_rem_u.call(&mut store, (100, 4)),
+        Trap::IntegerDivisionByZero,
+    );
+
+    assert_trap(
+        i32_div_s.call(&mut store, (i32::MIN, 8)),
+        Trap::IntegerOverflow,
+    );
+    assert_eq!(i32_rem_s.call(&mut store, (i32::MIN, 8))?, 0);
+
+    assert_trap(
+        i32_div_s.call(&mut store, (100, 100_000)),
+        Trap::MemoryOutOfBounds,
+    );
+    assert_trap(
+        i32_div_u.call(&mut store, (100, 100_000)),
+        Trap::MemoryOutOfBounds,
+    );
+    assert_trap(
+        i32_rem_s.call(&mut store, (100, 100_000)),
+        Trap::MemoryOutOfBounds,
+    );
+    assert_trap(
+        i32_rem_u.call(&mut store, (100, 100_000)),
+        Trap::MemoryOutOfBounds,
+    );
+
+    return Ok(());
+
+    #[track_caller]
+    fn assert_trap<T>(result: Result<T>, expected: Trap) {
+        match result {
+            Ok(_) => panic!("expected failure"),
+            Err(e) => {
+                if let Some(code) = e.downcast_ref::<Trap>() {
+                    if *code == expected {
+                        return;
+                    }
+                }
+                panic!("unexpected error {e:?}");
+            }
+        }
+    }
+}
diff --git a/winch/filetests/filetests/x64/i32_divs/const.wat b/winch/filetests/filetests/x64/i32_divs/const.wat
index c32078198..cd9be27f2 100644
--- a/winch/filetests/filetests/x64/i32_divs/const.wat
+++ b/winch/filetests/filetests/x64/i32_divs/const.wat
@@ -14,12 +14,7 @@
 ;;    e:	 83f900               	cmp	ecx, 0
 ;;   11:	 0f8502000000         	jne	0x19
 ;;   17:	 0f0b                 	ud2	
-;;   19:	 83f9ff               	cmp	ecx, -1
-;;   1c:	 0f850e000000         	jne	0x30
-;;   22:	 81f800000080         	cmp	eax, 0x80000000
-;;   28:	 0f8502000000         	jne	0x30
-;;   2e:	 0f0b                 	ud2	
-;;   30:	 99                   	cdq	
-;;   31:	 f7f9                 	idiv	ecx
-;;   33:	 5d                   	pop	rbp
-;;   34:	 c3                   	ret	
+;;   19:	 99                   	cdq	
+;;   1a:	 f7f9                 	idiv	ecx
+;;   1c:	 5d                   	pop	rbp
+;;   1d:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divs/one_zero.wat b/winch/filetests/filetests/x64/i32_divs/one_zero.wat
index 1ef0d7885..6b3094ea6 100644
--- a/winch/filetests/filetests/x64/i32_divs/one_zero.wat
+++ b/winch/filetests/filetests/x64/i32_divs/one_zero.wat
@@ -14,12 +14,7 @@
 ;;    e:	 83f900               	cmp	ecx, 0
 ;;   11:	 0f8502000000         	jne	0x19
 ;;   17:	 0f0b                 	ud2	
-;;   19:	 83f9ff               	cmp	ecx, -1
-;;   1c:	 0f850e000000         	jne	0x30
-;;   22:	 81f800000080         	cmp	eax, 0x80000000
-;;   28:	 0f8502000000         	jne	0x30
-;;   2e:	 0f0b                 	ud2	
-;;   30:	 99                   	cdq	
-;;   31:	 f7f9                 	idiv	ecx
-;;   33:	 5d                   	pop	rbp
-;;   34:	 c3                   	ret	
+;;   19:	 99                   	cdq	
+;;   1a:	 f7f9                 	idiv	ecx
+;;   1c:	 5d                   	pop	rbp
+;;   1d:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divs/overflow.wat b/winch/filetests/filetests/x64/i32_divs/overflow.wat
index 7f2499a1b..33c7d05bb 100644
--- a/winch/filetests/filetests/x64/i32_divs/overflow.wat
+++ b/winch/filetests/filetests/x64/i32_divs/overflow.wat
@@ -14,12 +14,7 @@
 ;;    e:	 83f900               	cmp	ecx, 0
 ;;   11:	 0f8502000000         	jne	0x19
 ;;   17:	 0f0b                 	ud2	
-;;   19:	 83f9ff               	cmp	ecx, -1
-;;   1c:	 0f850e000000         	jne	0x30
-;;   22:	 81f800000080         	cmp	eax, 0x80000000
-;;   28:	 0f8502000000         	jne	0x30
-;;   2e:	 0f0b                 	ud2	
-;;   30:	 99                   	cdq	
-;;   31:	 f7f9                 	idiv	ecx
-;;   33:	 5d                   	pop	rbp
-;;   34:	 c3                   	ret	
+;;   19:	 99                   	cdq	
+;;   1a:	 f7f9                 	idiv	ecx
+;;   1c:	 5d                   	pop	rbp
+;;   1d:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divs/params.wat b/winch/filetests/filetests/x64/i32_divs/params.wat
index ec999077b..cc3c25b8c 100644
--- a/winch/filetests/filetests/x64/i32_divs/params.wat
+++ b/winch/filetests/filetests/x64/i32_divs/params.wat
@@ -17,13 +17,8 @@
 ;;   16:	 83f900               	cmp	ecx, 0
 ;;   19:	 0f8502000000         	jne	0x21
 ;;   1f:	 0f0b                 	ud2	
-;;   21:	 83f9ff               	cmp	ecx, -1
-;;   24:	 0f850e000000         	jne	0x38
-;;   2a:	 81f800000080         	cmp	eax, 0x80000000
-;;   30:	 0f8502000000         	jne	0x38
-;;   36:	 0f0b                 	ud2	
-;;   38:	 99                   	cdq	
-;;   39:	 f7f9                 	idiv	ecx
-;;   3b:	 4883c408             	add	rsp, 8
-;;   3f:	 5d                   	pop	rbp
-;;   40:	 c3                   	ret	
+;;   21:	 99                   	cdq	
+;;   22:	 f7f9                 	idiv	ecx
+;;   24:	 4883c408             	add	rsp, 8
+;;   28:	 5d                   	pop	rbp
+;;   29:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divs/zero_zero.wat b/winch/filetests/filetests/x64/i32_divs/zero_zero.wat
index 807b7f7eb..7158174ad 100644
--- a/winch/filetests/filetests/x64/i32_divs/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i32_divs/zero_zero.wat
@@ -14,12 +14,7 @@
 ;;    e:	 83f900               	cmp	ecx, 0
 ;;   11:	 0f8502000000         	jne	0x19
 ;;   17:	 0f0b                 	ud2	
-;;   19:	 83f9ff               	cmp	ecx, -1
-;;   1c:	 0f850e000000         	jne	0x30
-;;   22:	 81f800000080         	cmp	eax, 0x80000000
-;;   28:	 0f8502000000         	jne	0x30
-;;   2e:	 0f0b                 	ud2	
-;;   30:	 99                   	cdq	
-;;   31:	 f7f9                 	idiv	ecx
-;;   33:	 5d                   	pop	rbp
-;;   34:	 c3                   	ret	
+;;   19:	 99                   	cdq	
+;;   1a:	 f7f9                 	idiv	ecx
+;;   1c:	 5d                   	pop	rbp
+;;   1d:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divu/const.wat b/winch/filetests/filetests/x64/i32_divu/const.wat
index 3ba1c3dbb..a2bbfd014 100644
--- a/winch/filetests/filetests/x64/i32_divu/const.wat
+++ b/winch/filetests/filetests/x64/i32_divu/const.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b90a000000           	mov	ecx, 0xa
 ;;    9:	 b814000000           	mov	eax, 0x14
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 5d                   	pop	rbp
-;;   1e:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 5d                   	pop	rbp
+;;   13:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divu/one_zero.wat b/winch/filetests/filetests/x64/i32_divu/one_zero.wat
index 938f78778..3f3de081e 100644
--- a/winch/filetests/filetests/x64/i32_divu/one_zero.wat
+++ b/winch/filetests/filetests/x64/i32_divu/one_zero.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b900000000           	mov	ecx, 0
 ;;    9:	 b801000000           	mov	eax, 1
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 5d                   	pop	rbp
-;;   1e:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 5d                   	pop	rbp
+;;   13:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divu/params.wat b/winch/filetests/filetests/x64/i32_divu/params.wat
index e732e05bc..a566659c1 100644
--- a/winch/filetests/filetests/x64/i32_divu/params.wat
+++ b/winch/filetests/filetests/x64/i32_divu/params.wat
@@ -14,11 +14,8 @@
 ;;    c:	 893424               	mov	dword ptr [rsp], esi
 ;;    f:	 8b0c24               	mov	ecx, dword ptr [rsp]
 ;;   12:	 8b442404             	mov	eax, dword ptr [rsp + 4]
-;;   16:	 83f900               	cmp	ecx, 0
-;;   19:	 0f8502000000         	jne	0x21
-;;   1f:	 0f0b                 	ud2	
-;;   21:	 31d2                 	xor	edx, edx
-;;   23:	 f7f1                 	div	ecx
-;;   25:	 4883c408             	add	rsp, 8
-;;   29:	 5d                   	pop	rbp
-;;   2a:	 c3                   	ret	
+;;   16:	 31d2                 	xor	edx, edx
+;;   18:	 f7f1                 	div	ecx
+;;   1a:	 4883c408             	add	rsp, 8
+;;   1e:	 5d                   	pop	rbp
+;;   1f:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divu/signed.wat b/winch/filetests/filetests/x64/i32_divu/signed.wat
index ce39cff78..a0b91f279 100644
--- a/winch/filetests/filetests/x64/i32_divu/signed.wat
+++ b/winch/filetests/filetests/x64/i32_divu/signed.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b9ffffffff           	mov	ecx, 0xffffffff
 ;;    9:	 b8ffffffff           	mov	eax, 0xffffffff
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 5d                   	pop	rbp
-;;   1e:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 5d                   	pop	rbp
+;;   13:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_divu/zero_zero.wat b/winch/filetests/filetests/x64/i32_divu/zero_zero.wat
index 418d08432..e78558a66 100644
--- a/winch/filetests/filetests/x64/i32_divu/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i32_divu/zero_zero.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b900000000           	mov	ecx, 0
 ;;    9:	 b800000000           	mov	eax, 0
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 5d                   	pop	rbp
-;;   1e:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 5d                   	pop	rbp
+;;   13:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_rems/const.wat b/winch/filetests/filetests/x64/i32_rems/const.wat
index 1edb0d896..221b810c5 100644
--- a/winch/filetests/filetests/x64/i32_rems/const.wat
+++ b/winch/filetests/filetests/x64/i32_rems/const.wat
@@ -11,15 +11,12 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b905000000           	mov	ecx, 5
 ;;    9:	 b807000000           	mov	eax, 7
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 99                   	cdq	
-;;   1a:	 83f9ff               	cmp	ecx, -1
-;;   1d:	 0f850a000000         	jne	0x2d
-;;   23:	 ba00000000           	mov	edx, 0
-;;   28:	 e902000000           	jmp	0x2f
-;;   2d:	 f7f9                 	idiv	ecx
-;;   2f:	 4889d0               	mov	rax, rdx
-;;   32:	 5d                   	pop	rbp
-;;   33:	 c3                   	ret	
+;;    e:	 99                   	cdq	
+;;    f:	 83f9ff               	cmp	ecx, -1
+;;   12:	 0f850a000000         	jne	0x22
+;;   18:	 ba00000000           	mov	edx, 0
+;;   1d:	 e902000000           	jmp	0x24
+;;   22:	 f7f9                 	idiv	ecx
+;;   24:	 4889d0               	mov	rax, rdx
+;;   27:	 5d                   	pop	rbp
+;;   28:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_rems/one_zero.wat b/winch/filetests/filetests/x64/i32_rems/one_zero.wat
index 3b618c3c1..d8569b3c0 100644
--- a/winch/filetests/filetests/x64/i32_rems/one_zero.wat
+++ b/winch/filetests/filetests/x64/i32_rems/one_zero.wat
@@ -11,15 +11,12 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b900000000           	mov	ecx, 0
 ;;    9:	 b801000000           	mov	eax, 1
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 99                   	cdq	
-;;   1a:	 83f9ff               	cmp	ecx, -1
-;;   1d:	 0f850a000000         	jne	0x2d
-;;   23:	 ba00000000           	mov	edx, 0
-;;   28:	 e902000000           	jmp	0x2f
-;;   2d:	 f7f9                 	idiv	ecx
-;;   2f:	 4889d0               	mov	rax, rdx
-;;   32:	 5d                   	pop	rbp
-;;   33:	 c3                   	ret	
+;;    e:	 99                   	cdq	
+;;    f:	 83f9ff               	cmp	ecx, -1
+;;   12:	 0f850a000000         	jne	0x22
+;;   18:	 ba00000000           	mov	edx, 0
+;;   1d:	 e902000000           	jmp	0x24
+;;   22:	 f7f9                 	idiv	ecx
+;;   24:	 4889d0               	mov	rax, rdx
+;;   27:	 5d                   	pop	rbp
+;;   28:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_rems/overflow.wat b/winch/filetests/filetests/x64/i32_rems/overflow.wat
index b42f2ce35..fcfed2582 100644
--- a/winch/filetests/filetests/x64/i32_rems/overflow.wat
+++ b/winch/filetests/filetests/x64/i32_rems/overflow.wat
@@ -11,15 +11,12 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b9ffffffff           	mov	ecx, 0xffffffff
 ;;    9:	 b800000080           	mov	eax, 0x80000000
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 99                   	cdq	
-;;   1a:	 83f9ff               	cmp	ecx, -1
-;;   1d:	 0f850a000000         	jne	0x2d
-;;   23:	 ba00000000           	mov	edx, 0
-;;   28:	 e902000000           	jmp	0x2f
-;;   2d:	 f7f9                 	idiv	ecx
-;;   2f:	 4889d0               	mov	rax, rdx
-;;   32:	 5d                   	pop	rbp
-;;   33:	 c3                   	ret	
+;;    e:	 99                   	cdq	
+;;    f:	 83f9ff               	cmp	ecx, -1
+;;   12:	 0f850a000000         	jne	0x22
+;;   18:	 ba00000000           	mov	edx, 0
+;;   1d:	 e902000000           	jmp	0x24
+;;   22:	 f7f9                 	idiv	ecx
+;;   24:	 4889d0               	mov	rax, rdx
+;;   27:	 5d                   	pop	rbp
+;;   28:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_rems/params.wat b/winch/filetests/filetests/x64/i32_rems/params.wat
index 752f5abee..cfa264e0f 100644
--- a/winch/filetests/filetests/x64/i32_rems/params.wat
+++ b/winch/filetests/filetests/x64/i32_rems/params.wat
@@ -14,16 +14,13 @@
 ;;    c:	 893424               	mov	dword ptr [rsp], esi
 ;;    f:	 8b0c24               	mov	ecx, dword ptr [rsp]
 ;;   12:	 8b442404             	mov	eax, dword ptr [rsp + 4]
-;;   16:	 83f900               	cmp	ecx, 0
-;;   19:	 0f8502000000         	jne	0x21
-;;   1f:	 0f0b                 	ud2	
-;;   21:	 99                   	cdq	
-;;   22:	 83f9ff               	cmp	ecx, -1
-;;   25:	 0f850a000000         	jne	0x35
-;;   2b:	 ba00000000           	mov	edx, 0
-;;   30:	 e902000000           	jmp	0x37
-;;   35:	 f7f9                 	idiv	ecx
-;;   37:	 4889d0               	mov	rax, rdx
-;;   3a:	 4883c408             	add	rsp, 8
-;;   3e:	 5d                   	pop	rbp
-;;   3f:	 c3                   	ret	
+;;   16:	 99                   	cdq	
+;;   17:	 83f9ff               	cmp	ecx, -1
+;;   1a:	 0f850a000000         	jne	0x2a
+;;   20:	 ba00000000           	mov	edx, 0
+;;   25:	 e902000000           	jmp	0x2c
+;;   2a:	 f7f9                 	idiv	ecx
+;;   2c:	 4889d0               	mov	rax, rdx
+;;   2f:	 4883c408             	add	rsp, 8
+;;   33:	 5d                   	pop	rbp
+;;   34:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_rems/zero_zero.wat b/winch/filetests/filetests/x64/i32_rems/zero_zero.wat
index 01358814f..5fff7d4a6 100644
--- a/winch/filetests/filetests/x64/i32_rems/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i32_rems/zero_zero.wat
@@ -11,15 +11,12 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b900000000           	mov	ecx, 0
 ;;    9:	 b800000000           	mov	eax, 0
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 99                   	cdq	
-;;   1a:	 83f9ff               	cmp	ecx, -1
-;;   1d:	 0f850a000000         	jne	0x2d
-;;   23:	 ba00000000           	mov	edx, 0
-;;   28:	 e902000000           	jmp	0x2f
-;;   2d:	 f7f9                 	idiv	ecx
-;;   2f:	 4889d0               	mov	rax, rdx
-;;   32:	 5d                   	pop	rbp
-;;   33:	 c3                   	ret	
+;;    e:	 99                   	cdq	
+;;    f:	 83f9ff               	cmp	ecx, -1
+;;   12:	 0f850a000000         	jne	0x22
+;;   18:	 ba00000000           	mov	edx, 0
+;;   1d:	 e902000000           	jmp	0x24
+;;   22:	 f7f9                 	idiv	ecx
+;;   24:	 4889d0               	mov	rax, rdx
+;;   27:	 5d                   	pop	rbp
+;;   28:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_remu/const.wat b/winch/filetests/filetests/x64/i32_remu/const.wat
index bbcb387cb..0a48c6c4c 100644
--- a/winch/filetests/filetests/x64/i32_remu/const.wat
+++ b/winch/filetests/filetests/x64/i32_remu/const.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b905000000           	mov	ecx, 5
 ;;    9:	 b807000000           	mov	eax, 7
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 4889d0               	mov	rax, rdx
-;;   20:	 5d                   	pop	rbp
-;;   21:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 4889d0               	mov	rax, rdx
+;;   15:	 5d                   	pop	rbp
+;;   16:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_remu/one_zero.wat b/winch/filetests/filetests/x64/i32_remu/one_zero.wat
index 404264c86..4b3975ab1 100644
--- a/winch/filetests/filetests/x64/i32_remu/one_zero.wat
+++ b/winch/filetests/filetests/x64/i32_remu/one_zero.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b900000000           	mov	ecx, 0
 ;;    9:	 b801000000           	mov	eax, 1
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 4889d0               	mov	rax, rdx
-;;   20:	 5d                   	pop	rbp
-;;   21:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 4889d0               	mov	rax, rdx
+;;   15:	 5d                   	pop	rbp
+;;   16:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_remu/params.wat b/winch/filetests/filetests/x64/i32_remu/params.wat
index 9d6a2e632..714217d78 100644
--- a/winch/filetests/filetests/x64/i32_remu/params.wat
+++ b/winch/filetests/filetests/x64/i32_remu/params.wat
@@ -14,12 +14,9 @@
 ;;    c:	 893424               	mov	dword ptr [rsp], esi
 ;;    f:	 8b0c24               	mov	ecx, dword ptr [rsp]
 ;;   12:	 8b442404             	mov	eax, dword ptr [rsp + 4]
-;;   16:	 83f900               	cmp	ecx, 0
-;;   19:	 0f8502000000         	jne	0x21
-;;   1f:	 0f0b                 	ud2	
-;;   21:	 31d2                 	xor	edx, edx
-;;   23:	 f7f1                 	div	ecx
-;;   25:	 4889d0               	mov	rax, rdx
-;;   28:	 4883c408             	add	rsp, 8
-;;   2c:	 5d                   	pop	rbp
-;;   2d:	 c3                   	ret	
+;;   16:	 31d2                 	xor	edx, edx
+;;   18:	 f7f1                 	div	ecx
+;;   1a:	 4889d0               	mov	rax, rdx
+;;   1d:	 4883c408             	add	rsp, 8
+;;   21:	 5d                   	pop	rbp
+;;   22:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_remu/signed.wat b/winch/filetests/filetests/x64/i32_remu/signed.wat
index f886e5ac7..85e83eb0a 100644
--- a/winch/filetests/filetests/x64/i32_remu/signed.wat
+++ b/winch/filetests/filetests/x64/i32_remu/signed.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b9ffffffff           	mov	ecx, 0xffffffff
 ;;    9:	 b8ffffffff           	mov	eax, 0xffffffff
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 4889d0               	mov	rax, rdx
-;;   20:	 5d                   	pop	rbp
-;;   21:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 4889d0               	mov	rax, rdx
+;;   15:	 5d                   	pop	rbp
+;;   16:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i32_remu/zero_zero.wat b/winch/filetests/filetests/x64/i32_remu/zero_zero.wat
index 4654eafd4..c60bac6e3 100644
--- a/winch/filetests/filetests/x64/i32_remu/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i32_remu/zero_zero.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 b900000000           	mov	ecx, 0
 ;;    9:	 b800000000           	mov	eax, 0
-;;    e:	 83f900               	cmp	ecx, 0
-;;   11:	 0f8502000000         	jne	0x19
-;;   17:	 0f0b                 	ud2	
-;;   19:	 31d2                 	xor	edx, edx
-;;   1b:	 f7f1                 	div	ecx
-;;   1d:	 4889d0               	mov	rax, rdx
-;;   20:	 5d                   	pop	rbp
-;;   21:	 c3                   	ret	
+;;    e:	 31d2                 	xor	edx, edx
+;;   10:	 f7f1                 	div	ecx
+;;   12:	 4889d0               	mov	rax, rdx
+;;   15:	 5d                   	pop	rbp
+;;   16:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divs/const.wat b/winch/filetests/filetests/x64/i64_divs/const.wat
index 840f1ad5f..4f2d67cb2 100644
--- a/winch/filetests/filetests/x64/i64_divs/const.wat
+++ b/winch/filetests/filetests/x64/i64_divs/const.wat
@@ -14,14 +14,7 @@
 ;;   12:	 4883f900             	cmp	rcx, 0
 ;;   16:	 0f8502000000         	jne	0x1e
 ;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4883f9ff             	cmp	rcx, -1
-;;   22:	 0f8515000000         	jne	0x3d
-;;   28:	 49bb0000000000000080 	
-;; 				movabs	r11, 0x8000000000000000
-;;   32:	 4c39d8               	cmp	rax, r11
-;;   35:	 0f8502000000         	jne	0x3d
-;;   3b:	 0f0b                 	ud2	
-;;   3d:	 4899                 	cqo	
-;;   3f:	 48f7f9               	idiv	rcx
-;;   42:	 5d                   	pop	rbp
-;;   43:	 c3                   	ret	
+;;   1e:	 4899                 	cqo	
+;;   20:	 48f7f9               	idiv	rcx
+;;   23:	 5d                   	pop	rbp
+;;   24:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divs/one_zero.wat b/winch/filetests/filetests/x64/i64_divs/one_zero.wat
index c274f531e..3c0156434 100644
--- a/winch/filetests/filetests/x64/i64_divs/one_zero.wat
+++ b/winch/filetests/filetests/x64/i64_divs/one_zero.wat
@@ -14,14 +14,7 @@
 ;;   12:	 4883f900             	cmp	rcx, 0
 ;;   16:	 0f8502000000         	jne	0x1e
 ;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4883f9ff             	cmp	rcx, -1
-;;   22:	 0f8515000000         	jne	0x3d
-;;   28:	 49bb0000000000000080 	
-;; 				movabs	r11, 0x8000000000000000
-;;   32:	 4c39d8               	cmp	rax, r11
-;;   35:	 0f8502000000         	jne	0x3d
-;;   3b:	 0f0b                 	ud2	
-;;   3d:	 4899                 	cqo	
-;;   3f:	 48f7f9               	idiv	rcx
-;;   42:	 5d                   	pop	rbp
-;;   43:	 c3                   	ret	
+;;   1e:	 4899                 	cqo	
+;;   20:	 48f7f9               	idiv	rcx
+;;   23:	 5d                   	pop	rbp
+;;   24:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divs/overflow.wat b/winch/filetests/filetests/x64/i64_divs/overflow.wat
index 18630116b..0161afa14 100644
--- a/winch/filetests/filetests/x64/i64_divs/overflow.wat
+++ b/winch/filetests/filetests/x64/i64_divs/overflow.wat
@@ -15,14 +15,7 @@
 ;;   15:	 4883f900             	cmp	rcx, 0
 ;;   19:	 0f8502000000         	jne	0x21
 ;;   1f:	 0f0b                 	ud2	
-;;   21:	 4883f9ff             	cmp	rcx, -1
-;;   25:	 0f8515000000         	jne	0x40
-;;   2b:	 49bb0000000000000080 	
-;; 				movabs	r11, 0x8000000000000000
-;;   35:	 4c39d8               	cmp	rax, r11
-;;   38:	 0f8502000000         	jne	0x40
-;;   3e:	 0f0b                 	ud2	
-;;   40:	 4899                 	cqo	
-;;   42:	 48f7f9               	idiv	rcx
-;;   45:	 5d                   	pop	rbp
-;;   46:	 c3                   	ret	
+;;   21:	 4899                 	cqo	
+;;   23:	 48f7f9               	idiv	rcx
+;;   26:	 5d                   	pop	rbp
+;;   27:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divs/params.wat b/winch/filetests/filetests/x64/i64_divs/params.wat
index d52e28cff..ee29c99b5 100644
--- a/winch/filetests/filetests/x64/i64_divs/params.wat
+++ b/winch/filetests/filetests/x64/i64_divs/params.wat
@@ -17,15 +17,8 @@
 ;;   1a:	 4883f900             	cmp	rcx, 0
 ;;   1e:	 0f8502000000         	jne	0x26
 ;;   24:	 0f0b                 	ud2	
-;;   26:	 4883f9ff             	cmp	rcx, -1
-;;   2a:	 0f8515000000         	jne	0x45
-;;   30:	 49bb0000000000000080 	
-;; 				movabs	r11, 0x8000000000000000
-;;   3a:	 4c39d8               	cmp	rax, r11
-;;   3d:	 0f8502000000         	jne	0x45
-;;   43:	 0f0b                 	ud2	
-;;   45:	 4899                 	cqo	
-;;   47:	 48f7f9               	idiv	rcx
-;;   4a:	 4883c410             	add	rsp, 0x10
-;;   4e:	 5d                   	pop	rbp
-;;   4f:	 c3                   	ret	
+;;   26:	 4899                 	cqo	
+;;   28:	 48f7f9               	idiv	rcx
+;;   2b:	 4883c410             	add	rsp, 0x10
+;;   2f:	 5d                   	pop	rbp
+;;   30:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divs/zero_zero.wat b/winch/filetests/filetests/x64/i64_divs/zero_zero.wat
index 4a08ab105..820699451 100644
--- a/winch/filetests/filetests/x64/i64_divs/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i64_divs/zero_zero.wat
@@ -14,14 +14,7 @@
 ;;   12:	 4883f900             	cmp	rcx, 0
 ;;   16:	 0f8502000000         	jne	0x1e
 ;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4883f9ff             	cmp	rcx, -1
-;;   22:	 0f8515000000         	jne	0x3d
-;;   28:	 49bb0000000000000080 	
-;; 				movabs	r11, 0x8000000000000000
-;;   32:	 4c39d8               	cmp	rax, r11
-;;   35:	 0f8502000000         	jne	0x3d
-;;   3b:	 0f0b                 	ud2	
-;;   3d:	 4899                 	cqo	
-;;   3f:	 48f7f9               	idiv	rcx
-;;   42:	 5d                   	pop	rbp
-;;   43:	 c3                   	ret	
+;;   1e:	 4899                 	cqo	
+;;   20:	 48f7f9               	idiv	rcx
+;;   23:	 5d                   	pop	rbp
+;;   24:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divu/const.wat b/winch/filetests/filetests/x64/i64_divu/const.wat
index c44bc6091..ba7bf6507 100644
--- a/winch/filetests/filetests/x64/i64_divu/const.wat
+++ b/winch/filetests/filetests/x64/i64_divu/const.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c10a000000       	mov	rcx, 0xa
 ;;    b:	 48c7c014000000       	mov	rax, 0x14
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 5d                   	pop	rbp
-;;   25:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 5d                   	pop	rbp
+;;   19:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divu/one_zero.wat b/winch/filetests/filetests/x64/i64_divu/one_zero.wat
index 7c5accf23..13ed67815 100644
--- a/winch/filetests/filetests/x64/i64_divu/one_zero.wat
+++ b/winch/filetests/filetests/x64/i64_divu/one_zero.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c100000000       	mov	rcx, 0
 ;;    b:	 48c7c001000000       	mov	rax, 1
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 5d                   	pop	rbp
-;;   25:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 5d                   	pop	rbp
+;;   19:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divu/params.wat b/winch/filetests/filetests/x64/i64_divu/params.wat
index 8dfbdbe85..2c4e612b0 100644
--- a/winch/filetests/filetests/x64/i64_divu/params.wat
+++ b/winch/filetests/filetests/x64/i64_divu/params.wat
@@ -14,11 +14,8 @@
 ;;    d:	 48893424             	mov	qword ptr [rsp], rsi
 ;;   11:	 488b0c24             	mov	rcx, qword ptr [rsp]
 ;;   15:	 488b442408           	mov	rax, qword ptr [rsp + 8]
-;;   1a:	 4883f900             	cmp	rcx, 0
-;;   1e:	 0f8502000000         	jne	0x26
-;;   24:	 0f0b                 	ud2	
-;;   26:	 4831d2               	xor	rdx, rdx
-;;   29:	 48f7f1               	div	rcx
-;;   2c:	 4883c410             	add	rsp, 0x10
-;;   30:	 5d                   	pop	rbp
-;;   31:	 c3                   	ret	
+;;   1a:	 4831d2               	xor	rdx, rdx
+;;   1d:	 48f7f1               	div	rcx
+;;   20:	 4883c410             	add	rsp, 0x10
+;;   24:	 5d                   	pop	rbp
+;;   25:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divu/signed.wat b/winch/filetests/filetests/x64/i64_divu/signed.wat
index af7cc2d20..28208571a 100644
--- a/winch/filetests/filetests/x64/i64_divu/signed.wat
+++ b/winch/filetests/filetests/x64/i64_divu/signed.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c1ffffffff       	mov	rcx, 0xffffffffffffffff
 ;;    b:	 48c7c0ffffffff       	mov	rax, 0xffffffffffffffff
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 5d                   	pop	rbp
-;;   25:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 5d                   	pop	rbp
+;;   19:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_divu/zero_zero.wat b/winch/filetests/filetests/x64/i64_divu/zero_zero.wat
index 458e4965a..e8c119a9a 100644
--- a/winch/filetests/filetests/x64/i64_divu/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i64_divu/zero_zero.wat
@@ -11,10 +11,7 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c100000000       	mov	rcx, 0
 ;;    b:	 48c7c000000000       	mov	rax, 0
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 5d                   	pop	rbp
-;;   25:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 5d                   	pop	rbp
+;;   19:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_rems/const.wat b/winch/filetests/filetests/x64/i64_rems/const.wat
index f8e1c3439..ad6182c23 100644
--- a/winch/filetests/filetests/x64/i64_rems/const.wat
+++ b/winch/filetests/filetests/x64/i64_rems/const.wat
@@ -11,15 +11,12 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c105000000       	mov	rcx, 5
 ;;    b:	 48c7c007000000       	mov	rax, 7
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4899                 	cqo	
-;;   20:	 4883f9ff             	cmp	rcx, -1
-;;   24:	 0f850a000000         	jne	0x34
-;;   2a:	 ba00000000           	mov	edx, 0
-;;   2f:	 e903000000           	jmp	0x37
-;;   34:	 48f7f9               	idiv	rcx
-;;   37:	 4889d0               	mov	rax, rdx
-;;   3a:	 5d                   	pop	rbp
-;;   3b:	 c3                   	ret	
+;;   12:	 4899                 	cqo	
+;;   14:	 4883f9ff             	cmp	rcx, -1
+;;   18:	 0f850a000000         	jne	0x28
+;;   1e:	 ba00000000           	mov	edx, 0
+;;   23:	 e903000000           	jmp	0x2b
+;;   28:	 48f7f9               	idiv	rcx
+;;   2b:	 4889d0               	mov	rax, rdx
+;;   2e:	 5d                   	pop	rbp
+;;   2f:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_rems/one_zero.wat b/winch/filetests/filetests/x64/i64_rems/one_zero.wat
index 3ef0f3289..0ac94edd6 100644
--- a/winch/filetests/filetests/x64/i64_rems/one_zero.wat
+++ b/winch/filetests/filetests/x64/i64_rems/one_zero.wat
@@ -11,15 +11,12 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c100000000       	mov	rcx, 0
 ;;    b:	 48c7c001000000       	mov	rax, 1
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4899                 	cqo	
-;;   20:	 4883f9ff             	cmp	rcx, -1
-;;   24:	 0f850a000000         	jne	0x34
-;;   2a:	 ba00000000           	mov	edx, 0
-;;   2f:	 e903000000           	jmp	0x37
-;;   34:	 48f7f9               	idiv	rcx
-;;   37:	 4889d0               	mov	rax, rdx
-;;   3a:	 5d                   	pop	rbp
-;;   3b:	 c3                   	ret	
+;;   12:	 4899                 	cqo	
+;;   14:	 4883f9ff             	cmp	rcx, -1
+;;   18:	 0f850a000000         	jne	0x28
+;;   1e:	 ba00000000           	mov	edx, 0
+;;   23:	 e903000000           	jmp	0x2b
+;;   28:	 48f7f9               	idiv	rcx
+;;   2b:	 4889d0               	mov	rax, rdx
+;;   2e:	 5d                   	pop	rbp
+;;   2f:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_rems/overflow.wat b/winch/filetests/filetests/x64/i64_rems/overflow.wat
index d3c69a9c6..6de1bfe75 100644
--- a/winch/filetests/filetests/x64/i64_rems/overflow.wat
+++ b/winch/filetests/filetests/x64/i64_rems/overflow.wat
@@ -12,15 +12,12 @@
 ;;    4:	 48c7c1ffffffff       	mov	rcx, 0xffffffffffffffff
 ;;    b:	 48b80000000000000080 	
 ;; 				movabs	rax, 0x8000000000000000
-;;   15:	 4883f900             	cmp	rcx, 0
-;;   19:	 0f8502000000         	jne	0x21
-;;   1f:	 0f0b                 	ud2	
-;;   21:	 4899                 	cqo	
-;;   23:	 4883f9ff             	cmp	rcx, -1
-;;   27:	 0f850a000000         	jne	0x37
-;;   2d:	 ba00000000           	mov	edx, 0
-;;   32:	 e903000000           	jmp	0x3a
-;;   37:	 48f7f9               	idiv	rcx
-;;   3a:	 4889d0               	mov	rax, rdx
-;;   3d:	 5d                   	pop	rbp
-;;   3e:	 c3                   	ret	
+;;   15:	 4899                 	cqo	
+;;   17:	 4883f9ff             	cmp	rcx, -1
+;;   1b:	 0f850a000000         	jne	0x2b
+;;   21:	 ba00000000           	mov	edx, 0
+;;   26:	 e903000000           	jmp	0x2e
+;;   2b:	 48f7f9               	idiv	rcx
+;;   2e:	 4889d0               	mov	rax, rdx
+;;   31:	 5d                   	pop	rbp
+;;   32:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_rems/params.wat b/winch/filetests/filetests/x64/i64_rems/params.wat
index 9851aa14c..222b54efa 100644
--- a/winch/filetests/filetests/x64/i64_rems/params.wat
+++ b/winch/filetests/filetests/x64/i64_rems/params.wat
@@ -14,16 +14,13 @@
 ;;    d:	 48893424             	mov	qword ptr [rsp], rsi
 ;;   11:	 488b0c24             	mov	rcx, qword ptr [rsp]
 ;;   15:	 488b442408           	mov	rax, qword ptr [rsp + 8]
-;;   1a:	 4883f900             	cmp	rcx, 0
-;;   1e:	 0f8502000000         	jne	0x26
-;;   24:	 0f0b                 	ud2	
-;;   26:	 4899                 	cqo	
-;;   28:	 4883f9ff             	cmp	rcx, -1
-;;   2c:	 0f850a000000         	jne	0x3c
-;;   32:	 ba00000000           	mov	edx, 0
-;;   37:	 e903000000           	jmp	0x3f
-;;   3c:	 48f7f9               	idiv	rcx
-;;   3f:	 4889d0               	mov	rax, rdx
-;;   42:	 4883c410             	add	rsp, 0x10
-;;   46:	 5d                   	pop	rbp
-;;   47:	 c3                   	ret	
+;;   1a:	 4899                 	cqo	
+;;   1c:	 4883f9ff             	cmp	rcx, -1
+;;   20:	 0f850a000000         	jne	0x30
+;;   26:	 ba00000000           	mov	edx, 0
+;;   2b:	 e903000000           	jmp	0x33
+;;   30:	 48f7f9               	idiv	rcx
+;;   33:	 4889d0               	mov	rax, rdx
+;;   36:	 4883c410             	add	rsp, 0x10
+;;   3a:	 5d                   	pop	rbp
+;;   3b:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_rems/zero_zero.wat b/winch/filetests/filetests/x64/i64_rems/zero_zero.wat
index 3a745e384..e3f24719a 100644
--- a/winch/filetests/filetests/x64/i64_rems/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i64_rems/zero_zero.wat
@@ -11,15 +11,12 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c100000000       	mov	rcx, 0
 ;;    b:	 48c7c000000000       	mov	rax, 0
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4899                 	cqo	
-;;   20:	 4883f9ff             	cmp	rcx, -1
-;;   24:	 0f850a000000         	jne	0x34
-;;   2a:	 ba00000000           	mov	edx, 0
-;;   2f:	 e903000000           	jmp	0x37
-;;   34:	 48f7f9               	idiv	rcx
-;;   37:	 4889d0               	mov	rax, rdx
-;;   3a:	 5d                   	pop	rbp
-;;   3b:	 c3                   	ret	
+;;   12:	 4899                 	cqo	
+;;   14:	 4883f9ff             	cmp	rcx, -1
+;;   18:	 0f850a000000         	jne	0x28
+;;   1e:	 ba00000000           	mov	edx, 0
+;;   23:	 e903000000           	jmp	0x2b
+;;   28:	 48f7f9               	idiv	rcx
+;;   2b:	 4889d0               	mov	rax, rdx
+;;   2e:	 5d                   	pop	rbp
+;;   2f:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_remu/const.wat b/winch/filetests/filetests/x64/i64_remu/const.wat
index 3b86a6769..101877d13 100644
--- a/winch/filetests/filetests/x64/i64_remu/const.wat
+++ b/winch/filetests/filetests/x64/i64_remu/const.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c105000000       	mov	rcx, 5
 ;;    b:	 48c7c007000000       	mov	rax, 7
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 4889d0               	mov	rax, rdx
-;;   27:	 5d                   	pop	rbp
-;;   28:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 4889d0               	mov	rax, rdx
+;;   1b:	 5d                   	pop	rbp
+;;   1c:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_remu/one_zero.wat b/winch/filetests/filetests/x64/i64_remu/one_zero.wat
index e31033b33..5af4f5989 100644
--- a/winch/filetests/filetests/x64/i64_remu/one_zero.wat
+++ b/winch/filetests/filetests/x64/i64_remu/one_zero.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c100000000       	mov	rcx, 0
 ;;    b:	 48c7c001000000       	mov	rax, 1
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 4889d0               	mov	rax, rdx
-;;   27:	 5d                   	pop	rbp
-;;   28:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 4889d0               	mov	rax, rdx
+;;   1b:	 5d                   	pop	rbp
+;;   1c:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_remu/params.wat b/winch/filetests/filetests/x64/i64_remu/params.wat
index 773debc84..4d6d4abce 100644
--- a/winch/filetests/filetests/x64/i64_remu/params.wat
+++ b/winch/filetests/filetests/x64/i64_remu/params.wat
@@ -14,12 +14,9 @@
 ;;    d:	 48893424             	mov	qword ptr [rsp], rsi
 ;;   11:	 488b0c24             	mov	rcx, qword ptr [rsp]
 ;;   15:	 488b442408           	mov	rax, qword ptr [rsp + 8]
-;;   1a:	 4883f900             	cmp	rcx, 0
-;;   1e:	 0f8502000000         	jne	0x26
-;;   24:	 0f0b                 	ud2	
-;;   26:	 4831d2               	xor	rdx, rdx
-;;   29:	 48f7f1               	div	rcx
-;;   2c:	 4889d0               	mov	rax, rdx
-;;   2f:	 4883c410             	add	rsp, 0x10
-;;   33:	 5d                   	pop	rbp
-;;   34:	 c3                   	ret	
+;;   1a:	 4831d2               	xor	rdx, rdx
+;;   1d:	 48f7f1               	div	rcx
+;;   20:	 4889d0               	mov	rax, rdx
+;;   23:	 4883c410             	add	rsp, 0x10
+;;   27:	 5d                   	pop	rbp
+;;   28:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_remu/signed.wat b/winch/filetests/filetests/x64/i64_remu/signed.wat
index 77b185982..2556ecfcc 100644
--- a/winch/filetests/filetests/x64/i64_remu/signed.wat
+++ b/winch/filetests/filetests/x64/i64_remu/signed.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c1ffffffff       	mov	rcx, 0xffffffffffffffff
 ;;    b:	 48c7c0ffffffff       	mov	rax, 0xffffffffffffffff
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 4889d0               	mov	rax, rdx
-;;   27:	 5d                   	pop	rbp
-;;   28:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 4889d0               	mov	rax, rdx
+;;   1b:	 5d                   	pop	rbp
+;;   1c:	 c3                   	ret	
diff --git a/winch/filetests/filetests/x64/i64_remu/zero_zero.wat b/winch/filetests/filetests/x64/i64_remu/zero_zero.wat
index df358d922..18983cd08 100644
--- a/winch/filetests/filetests/x64/i64_remu/zero_zero.wat
+++ b/winch/filetests/filetests/x64/i64_remu/zero_zero.wat
@@ -11,11 +11,8 @@
 ;;    1:	 4889e5               	mov	rbp, rsp
 ;;    4:	 48c7c100000000       	mov	rcx, 0
 ;;    b:	 48c7c000000000       	mov	rax, 0
-;;   12:	 4883f900             	cmp	rcx, 0
-;;   16:	 0f8502000000         	jne	0x1e
-;;   1c:	 0f0b                 	ud2	
-;;   1e:	 4831d2               	xor	rdx, rdx
-;;   21:	 48f7f1               	div	rcx
-;;   24:	 4889d0               	mov	rax, rdx
-;;   27:	 5d                   	pop	rbp
-;;   28:	 c3                   	ret	
+;;   12:	 4831d2               	xor	rdx, rdx
+;;   15:	 48f7f1               	div	rcx
+;;   18:	 4889d0               	mov	rax, rdx
+;;   1b:	 5d                   	pop	rbp
+;;   1c:	 c3                   	ret