Repository: probe-rs/probe-rs
Pull request #3047 (2025-01-23 20:45:48)

Improve exception unwinding
This changes the general flow of unwinding to better handle exceptions. The existing code first checked for an exception, before using the unwind information from the debug information. This is wrong if we're inside an exception handler which modifies the stack pointer. In such a case, we first have to unwind to the call site of the exception handler, and only then can we check for an exception.



## Additional changes

- When unwinding an exception, ensure that we get a program counter pointing to the calling instruction, not one to the next instruction to be executed after returning from the exception. This is achieved by subtracting one from the PC. 


probe-rs-perfbot[bot]: # Benchmarks

https://perfbot.drop.huesser.dev/run/12937757080

No benchmarks were found. Check your CI workflows.
    
probe-rs-perfbot[bot]: # Benchmarks

https://perfbot.drop.huesser.dev/run/12937757080

No benchmarks were found. Check your CI workflows.
    
probe-rs-perfbot[bot]: # Benchmarks

https://perfbot.drop.huesser.dev/run/12937757080

No benchmarks were found. Check your CI workflows.
    

Patch:
diff --git a/README.md b/README.md
index 5ea62f38..4abd06d6 100644
--- a/README.md
+++ b/README.md
@@ -156,6 +156,10 @@ Building requires Rust and Cargo which can be installed [using rustup](https://r
 Target files are generated using [target-gen](https://github.com/probe-rs/probe-rs/tree/master/target-gen) from CMSIS packs provided [here](https://developer.arm.com/tools-and-software/embedded/cmsis/cmsis-search).
 Generated files are then placed in `probe-rs/targets` for inclusion in the probe-rs project.
 
+### Updating STM32 targets
+
+STM32 memory region data has been proven unreliable on multiple occasions. We now rely on [stm32-data](https://github.com/embassy-rs/stm32-data/tree/main) for the correct values. Use target-gen to update the list of devices and their flash algorithms, then use the https://github.com/bugadani/stm-probers tool to regenerate memory maps for all STM32 devices.
+
 ### Writing new flash algorithms
 
 If there is no CMSIS-Pack with a flash algorithm available, it is necessary to write a target definition and a flash algorithm by oneself.
diff --git a/changelog/fixed-c-language-64bits-support.md b/changelog/fixed-c-language-64bits-support.md
new file mode 100644
index 00000000..6406d221
--- /dev/null
+++ b/changelog/fixed-c-language-64bits-support.md
@@ -0,0 +1,1 @@
+C-Language now properly supports 64bits variables (int, uint and double)
diff --git a/changelog/fixed-stm32-memory-maps.md b/changelog/fixed-stm32-memory-maps.md
new file mode 100644
index 00000000..aea7f560
--- /dev/null
+++ b/changelog/fixed-stm32-memory-maps.md
@@ -0,0 +1,1 @@
+Updates STM32H7 memory maps
\ No newline at end of file
diff --git a/probe-rs-debug/src/debug_info.rs b/probe-rs-debug/src/debug_info.rs
index 8f42cf00..5507b209 100644
--- a/probe-rs-debug/src/debug_info.rs
+++ b/probe-rs-debug/src/debug_info.rs
@@ -14,7 +14,7 @@ use gimli::{
     UnwindTableRow,
 };
 use object::read::{Object, ObjectSection};
-use probe_rs::{Error, MemoryInterface, RegisterRole, RegisterValue, UnwindRule};
+use probe_rs::{Error, MemoryInterface, RegisterDataType, RegisterRole, RegisterValue, UnwindRule};
 use probe_rs_target::InstructionSet;
 use std::{
     borrow, cmp::Ordering, num::NonZeroU64, ops::ControlFlow, path::Path, rc::Rc, str::from_utf8,
@@ -341,12 +341,13 @@ impl DebugInfo {
     }
 
     /// Returns a populated (resolved) [`StackFrame`] struct.
-    /// This function will also populate the `DebugInfo::VariableCache` with in scope `Variable`s for each `StackFrame`, while taking into account the appropriate strategy for lazy-loading of variables.
+    /// This function will also populate the `DebugInfo::VariableCache` with in scope `Variable`s for each `StackFrame`,
+    /// while taking into account the appropriate strategy for lazy-loading of variables.
     pub(crate) fn get_stackframe_info(
         &self,
         memory: &mut impl MemoryInterface,
         address: u64,
-        unwind_context: &mut UnwindContext<GimliReaderOffset>,
+        cfa: Option<u64>,
         unwind_registers: &registers::DebugRegisters,
     ) -> Result<Vec<StackFrame>, DebugError> {
         // When reporting the address, we format it as a hex string, with the width matching
@@ -359,23 +360,15 @@ impl DebugInfo {
             )
         };
 
-        let mut frames = Vec::new();
-
         let Ok((unit_info, functions)) = self.get_function_dies(address) else {
             // No function found at the given address.
-            return Ok(frames);
+            return Ok(vec![]);
         };
         if functions.is_empty() {
             // No function found at the given address.
-            return Ok(frames);
+            return Ok(vec![]);
         }
 
-        // Determining the frame base may need the CFA (Canonical Frame Address) to be calculated first.
-        let cfa = get_unwind_info(unwind_context, &self.frame_section, address)
-            .ok()
-            .and_then(|unwind_info| determine_cfa(unwind_registers, unwind_info).ok())
-            .flatten();
-
         // The first function is the non-inlined function, and the rest are inlined functions.
         // The frame base only exists for the non-inlined function, so we can reuse it for all the inlined functions.
         let frame_base = functions[0].frame_base(
@@ -388,17 +381,20 @@ impl DebugInfo {
             },
         )?;
 
+        let mut frames = Vec::new();
+
         // Handle all functions which contain further inlined functions. For
         // these functions, the location is the call site of the inlined function.
-        for (index, function_die) in functions[0..functions.len() - 1].iter().enumerate() {
+        for function_pair in functions.windows(2) {
+            let function_die = &function_pair[0];
+            let next_function = &function_pair[1];
+
             let function_name = function_die
                 .function_name(self)
                 .unwrap_or_else(unknown_function);
 
             tracing::debug!("UNWIND: Function name: {}", function_name);
 
-            let next_function = &functions[index + 1];
-
             assert!(next_function.is_inline());
 
             // Calculate the call site for this function, so that we can use it later to create an additional 'callee' `StackFrame` from that PC.
@@ -411,48 +407,45 @@ impl DebugInfo {
                 );
                 continue;
             };
-            if next_function_low_pc > address_size && next_function_low_pc < u32::MAX as u64 {
-                // The first instruction of the inlined function is used as the call site
-                let inlined_call_site = RegisterValue::from(next_function_low_pc);
 
-                tracing::debug!(
-                    "UNWIND: Callsite for inlined function {:?}",
-                    next_function.function_name(self)
-                );
-
-                let inlined_caller_source_location = next_function.inline_call_location(self);
+            if !(next_function_low_pc > address_size && next_function_low_pc < u32::MAX as u64) {
+                tracing::warn!("UNWIND: Unknown call site for inlined function {function_name}.");
+                continue;
+            }
 
-                tracing::debug!("UNWIND: Call site: {inlined_caller_source_location:?}");
+            // The first instruction of the inlined function is used as the call site
+            let inlined_call_site = RegisterValue::from(next_function_low_pc);
 
-                // Now that we have the function_name and function_source_location, we can create the appropriate variable caches for this stack frame.
-                // Resolve the statics that belong to the compilation unit that this function is in.
-                // Next, resolve and cache the function variables.
-                let local_variables = self
-                    .create_function_scope_cache(function_die, unit_info)
-                    .map_or_else(
-                        |error| {
-                            tracing::error!(
-                                "Could not resolve function variables. {error}. Continuing..."
-                            );
-                            None
-                        },
-                        Some,
-                    );
+            tracing::debug!(
+                "UNWIND: Callsite for inlined function {:?}",
+                next_function.function_name(self)
+            );
 
-                frames.push(StackFrame {
-                    id: get_object_reference(),
-                    function_name,
-                    source_location: inlined_caller_source_location,
-                    registers: unwind_registers.clone(),
-                    pc: inlined_call_site,
-                    frame_base,
-                    is_inlined: function_die.is_inline(),
-                    local_variables,
-                    canonical_frame_address: cfa,
-                });
-            } else {
-                tracing::warn!("UNWIND: Unknown call site for inlined function {function_name}.",);
-            }
+            let inlined_caller_source_location = next_function.inline_call_location(self);
+
+            tracing::debug!("UNWIND: Call site: {inlined_caller_source_location:?}");
+
+            // Now that we have the function_name and function_source_location, we can create the appropriate variable caches for this stack frame.
+            // Resolve the statics that belong to the compilation unit that this function is in.
+            // Next, resolve and cache the function variables.
+            let local_variables = self
+                .create_function_scope_cache(function_die, unit_info)
+                .inspect_err(|error| {
+                    tracing::error!("Could not resolve function variables. {error}. Continuing...");
+                })
+                .ok();
+
+            frames.push(StackFrame {
+                id: get_object_reference(),
+                function_name,
+                source_location: inlined_caller_source_location,
+                registers: unwind_registers.clone(),
+                pc: inlined_call_site,
+                frame_base,
+                is_inlined: function_die.is_inline(),
+                local_variables,
+                canonical_frame_address: cfa,
+            });
         }
 
         // Handle last function, which contains no further inlined functions
@@ -559,125 +552,67 @@ impl DebugInfo {
                 }
             })
         {
-            // PART 0: The first step is to determine the exception context for the current PC.
-            // - If we are at an exception hanlder frame:
-            //   - Create a "handler" stackframe that can be inserted into the stack_frames list,
-            //     instead of "unknown function @ address";
-            //   - Overwrite the unwind registers with the exception context.
-            // - If for some reason we cannot determine the exception context, we silently continue with the rest of the unwind.
-            // At worst, the unwind will be able to unwind the stack to the frame of the most recent exception handler.
             let frame_pc = frame_pc_register_value.try_into().map_err(|error| {
                 let message = format!("Cannot convert register value for program counter to a 64-bit integer value: {error:?}");
                 probe_rs::Error::Register(message)
             })?;
-            let exception_frame = match exception_handler.exception_details(
-                memory,
-                &unwind_registers,
-                self,
-            ) {
-                Ok(Some(exception_info)) => {
-                    tracing::trace!(
-                        "UNWIND: Stack unwind reached an exception handler {}",
-                        exception_info.description
-                    );
-                    Some(exception_info.handler_frame)
-                }
-                Ok(None) => {
-                    tracing::trace!(
-                        "UNWIND: No exception context found. Stack unwind will continue."
-                    );
-                    None
-                }
-                Err(e) => {
-                    let message = format!("UNWIND: Error while checking for exception context. The stack trace will not include the calling frames. : {e}");
-                    tracing::warn!("{message}");
-                    stack_frames.push(StackFrame {
-                        id: get_object_reference(),
-                        function_name: message,
-                        source_location: None,
-                        registers: unwind_registers.clone(),
-                        pc: frame_pc_register_value,
-                        frame_base: None,
-                        is_inlined: false,
-                        local_variables: None,
-                        canonical_frame_address: None,
-                    });
-                    break 'unwind;
-                }
-            };
 
-            // PART 1: Construct the `StackFrame` for the current pc.
+            // PART 1: Construct the `StackFrame`s for the current program counter.
+            //
+            //         Multiple stack frames can be constructed if we are inside inlined functions.
             tracing::trace!("UNWIND: Will generate `StackFrame` for function at address (PC) {frame_pc_register_value:#}");
+            let unwind_info = get_unwind_info(&mut unwind_context, &self.frame_section, frame_pc);
 
-            // PART 1-a: Prepare the `StackFrame`'s that holds the current frame information.
-            let mut cached_stack_frames = match self.get_stackframe_info(
-                memory,
-                frame_pc,
-                &mut unwind_context,
-                &unwind_registers,
-            ) {
-                Ok(cached_stack_frames) => cached_stack_frames,
-                Err(e) => {
-                    tracing::error!("UNWIND: Unable to complete `StackFrame` information: {}", e);
-                    // There is no point in continuing with the unwind, so let's get out of here.
-                    break;
-                }
-            };
-
-            // Part 1-b: If there were inlined functions, we push them to the stack first.
-            while cached_stack_frames.len() > 1 {
-                // If we encountered INLINED functions (all `StackFrames`s in this Vec, except for the last one, which is the containing NON-INLINED function), these are simply added to the list of stack_frames we return.
-                #[allow(clippy::unwrap_used)]
-                let inlined_frame = cached_stack_frames.pop().unwrap(); // unwrap is safe while .len() > 1
-                tracing::trace!(
-                    "UNWIND: Found inlined function - name={}, pc={}",
-                    inlined_frame.function_name,
-                    inlined_frame.pc
-                );
-                stack_frames.push(inlined_frame);
-            }
+            // Determining the frame base may need the CFA (Canonical Frame Address) to be calculated first.
+            let cfa = unwind_info
+                .as_ref()
+                .ok()
+                .and_then(|unwind_info| determine_cfa(&unwind_registers, unwind_info).ok())
+                .flatten();
+
+            // PART 1-a: Prepare the `StackFrame`s that holds the current frame information.
+            let cached_stack_frames =
+                match self.get_stackframe_info(memory, frame_pc, cfa, &unwind_registers) {
+                    Ok(cached_stack_frames) => cached_stack_frames,
+                    Err(e) => {
+                        tracing::error!("UNWIND: Unable to complete `StackFrame` information: {e}");
+                        // There is no point in continuing with the unwind, so let's get out of here.
+                        break;
+                    }
+                };
 
-            // PART 1-c: Process the remaining frame, if any, in the list of cached_stack_frames.
-            let unwind_canonical_frame_address = match cached_stack_frames.pop() {
-                Some(frame) => {
-                    // We have valid code for the current frame.
-                    let unwind_canonical_frame_address = frame.canonical_frame_address;
+            // Add the found stackframes to the list, in reverse order. `get_stackframe_info` returns the frames in
+            // the order of the most recently called function last, but the stack frames should be
+            // in the order of the most recently called function first.
+            if !cached_stack_frames.is_empty() {
+                for frame in cached_stack_frames.into_iter().rev() {
+                    if frame.is_inlined {
+                        tracing::trace!(
+                            "UNWIND: Found inlined function - name={}, pc={}",
+                            frame.function_name,
+                            frame.pc
+                        );
+                    }
                     stack_frames.push(frame);
-                    unwind_canonical_frame_address
-                }
-                None if exception_frame.is_some() => {
-                    // Nothing to do, we will add the exception frame to the stack_frames list,
-                    // and use it's unwind registers to we prepare for unwinding the preceding frame.
-                    None
-                }
-                None => {
-                    // We have no valid code for the current frame, so we
-                    // construct a frame, using what information we have.
-                    stack_frames.push(StackFrame {
-                        id: get_object_reference(),
-                        function_name: format!(
-                            "<unknown function @ {:#0width$x}>",
-                            frame_pc,
-                            width = (unwind_registers.get_address_size_bytes() * 2 + 2)
-                        ),
-                        source_location: self.get_source_location(frame_pc),
-                        registers: unwind_registers.clone(),
-                        pc: frame_pc_register_value,
-                        frame_base: None,
-                        is_inlined: false,
-                        local_variables: None,
-                        canonical_frame_address: None,
-                    });
-                    None
                 }
-            };
-
-            // Part 1-d: If we have an exception frame, we will insert it, before we continue unwinding.
-            if let Some(exception_frame) = exception_frame {
-                unwind_registers = exception_frame.registers.clone();
-                stack_frames.push(exception_frame);
-                // We have everything we need to unwind the next frame in the stack.
-                continue 'unwind;
+            } else {
+                // We have no valid code for the current frame, so we
+                // construct a frame, using what information we have.
+                stack_frames.push(StackFrame {
+                    id: get_object_reference(),
+                    function_name: format!(
+                        "<unknown function @ {:#0width$x}>",
+                        frame_pc,
+                        width = (unwind_registers.get_address_size_bytes() * 2 + 2)
+                    ),
+                    source_location: self.get_source_location(frame_pc),
+                    registers: unwind_registers.clone(),
+                    pc: frame_pc_register_value,
+                    frame_base: None,
+                    is_inlined: false,
+                    local_variables: None,
+                    canonical_frame_address: None,
+                });
             };
 
             // PART 2: Setup the registers for the next iteration (a.k.a. unwind previous frame, a.k.a. "callee", in the call stack).
@@ -685,96 +620,160 @@ impl DebugInfo {
 
             // PART 2-a: get the `gimli::FrameDescriptorEntry` for the program counter
             // and then the unwind info associated with this row.
-            let unwind_info =
-                match get_unwind_info(&mut unwind_context, &self.frame_section, frame_pc) {
-                    Ok(unwind_info) => {
-                        tracing::trace!("UNWIND: Found unwind info for address {frame_pc:#010x}");
-                        unwind_info
-                    }
-                    Err(err) => {
-                        tracing::trace!(
-                            "UNWIND: Unable to find unwind info for address {frame_pc:#010x}: {err}"
-                        );
-                        if let ControlFlow::Break(error) = exception_handler
-                            .unwind_without_debuginfo(
-                                &mut unwind_registers,
-                                frame_pc,
-                                &stack_frames,
-                                instruction_set,
-                                memory,
-                            )
-                        {
-                            if let Some(error) = error {
-                                // This is not fatal, but we cannot continue unwinding beyond the current frame.
-                                tracing::error!("{:?}", &error);
-                                if let Some(first_frame) = stack_frames.first_mut() {
-                                    first_frame.function_name =
-                                        format!("{} : ERROR : {error}", first_frame.function_name);
-                                };
-                            }
-                            break 'unwind;
+            let unwind_info = match unwind_info {
+                Ok(unwind_info) => {
+                    tracing::trace!("UNWIND: Found unwind info for address {frame_pc:#010x}");
+                    unwind_info
+                }
+                Err(err) => {
+                    tracing::trace!(
+                        "UNWIND: Unable to find unwind info for address {frame_pc:#010x}: {err}"
+                    );
+                    if let ControlFlow::Break(error) = exception_handler.unwind_without_debuginfo(
+                        &mut unwind_registers,
+                        frame_pc,
+                        &stack_frames,
+                        instruction_set,
+                        memory,
+                    ) {
+                        if let Some(error) = error {
+                            // This is not fatal, but we cannot continue unwinding beyond the current frame.
+                            tracing::error!("{:?}", &error);
+                            if let Some(first_frame) = stack_frames.first_mut() {
+                                first_frame.function_name =
+                                    format!("{} : ERROR : {error}", first_frame.function_name);
+                            };
                         }
-                        continue 'unwind;
+                        break 'unwind;
                     }
-                };
+                    continue 'unwind;
+                }
+            };
 
-            // Because we will be updating the `unwind_registers` with previous frame unwind info, we need to keep a copy of the current frame's registers that can be used to resolve [DWARF](https://dwarfstd.org) expressions.
+            // Because we will be updating the `unwind_registers` with previous frame unwind info,
+            // we need to keep a copy of the current frame's registers that can be used to resolve [DWARF](https://dwarfstd.org) expressions.
             let callee_frame_registers = unwind_registers.clone();
 
             // PART 2-b: Unwind registers for the "previous/calling" frame.
-            // We sometimes need to keep a copy of the LR value to calculate the PC. For both ARM, and RISC-V, The LR will be unwound before the PC, so we can reference it safely.
-            let mut unwound_return_address: Option<RegisterValue> = None;
-
-            // When we unwind the registers for the current frame, we should always do the FP and SP first,
-            // since many of the unwind rule calculations for the other registers depend on either one of these two.
-            let critical_unwind_registers =
-                &mut [RegisterRole::FramePointer, RegisterRole::StackPointer].to_vec();
-            for register_role in critical_unwind_registers.iter() {
-                if let ControlFlow::Break(error) = unwind_register(
-                    unwind_registers.get_register_mut_by_role(register_role)?,
-                    &callee_frame_registers,
-                    Some(unwind_info),
-                    unwind_canonical_frame_address,
-                    &mut None,
-                    memory,
-                    instruction_set,
-                ) {
-                    tracing::error!("{:?}", &error);
-                    if let Some(first_frame) = stack_frames.last_mut() {
-                        first_frame.function_name =
-                            format!("{} : ERROR: {error}", first_frame.function_name);
-                    };
-                    break 'unwind;
-                };
-            }
             for debug_register in unwind_registers.0.iter_mut() {
+                // The program counter is handled later
                 if debug_register
                     .core_register
-                    .register_has_role(RegisterRole::FramePointer)
-                    || debug_register
-                        .core_register
-                        .register_has_role(RegisterRole::StackPointer)
+                    .register_has_role(RegisterRole::ProgramCounter)
                 {
                     continue;
                 }
-                if let ControlFlow::Break(error) = unwind_register(
+
+                match unwind_register(
                     debug_register,
                     &callee_frame_registers,
-                    Some(unwind_info),
-                    unwind_canonical_frame_address,
-                    &mut unwound_return_address,
+                    unwind_info,
+                    cfa,
                     memory,
-                    instruction_set,
                 ) {
-                    tracing::error!("{:?}", &error);
-                    if let Some(first_frame) = stack_frames.last_mut() {
-                        first_frame.function_name =
-                            format!("{} : ERROR: {error}", first_frame.function_name);
-                    };
-                    break 'unwind;
+                    Err(error) => {
+                        tracing::error!("{:?}", &error);
+                        if let Some(first_frame) = stack_frames.last_mut() {
+                            first_frame.function_name =
+                                format!("{} : ERROR: {error}", first_frame.function_name);
+                        };
+                        break 'unwind;
+                    }
+                    Ok(val) => {
+                        debug_register.value = val;
+                    }
+                };
+            }
+
+            // PART 3: Check if we entered the current frame from an exception handler.
+            // - If we are at an exception handler frame:
+            //   - Create a "handler" stackframe that can be inserted into the stack_frames list,
+            //     instead of "unknown function @ address";
+            //   - Overwrite the unwind registers with the exception context.
+            // - If for some reason we cannot determine the exception context, we silently continue with the rest of the unwind.
+            // At worst, the unwind will be able to unwind the stack to the frame of the most recent exception handler.
+            if unwind_registers
+                .get_return_address()
+                .is_some_and(|ra| ra.value.is_some())
+            {
+                match exception_handler.exception_details(memory, &unwind_registers, self) {
+                    Ok(Some(exception_info)) => {
+                        tracing::trace!(
+                            "UNWIND: Stack unwind reached an exception handler {}",
+                            exception_info.description
+                        );
+                        unwind_registers = exception_info.handler_frame.registers.clone();
+                        stack_frames.push(exception_info.handler_frame);
+                        // We have everything we need to unwind the next frame in the stack.
+                        continue 'unwind;
+                    }
+                    Ok(None) => {
+                        tracing::trace!(
+                            "UNWIND: No exception context found. Stack unwind will continue."
+                        );
+                    }
+                    Err(e) => {
+                        let message = format!("UNWIND: Error while checking for exception context. The stack trace will not include the calling frames. : {e:?}");
+                        tracing::warn!("{message}");
+                        stack_frames.push(StackFrame {
+                            id: get_object_reference(),
+                            function_name: message,
+                            source_location: None,
+                            registers: unwind_registers.clone(),
+                            pc: frame_pc_register_value,
+                            frame_base: None,
+                            is_inlined: false,
+                            local_variables: None,
+                            canonical_frame_address: None,
+                        });
+                        break 'unwind;
+                    }
                 };
             }
 
+            let unwound_return_address = unwind_registers
+                .get_register_by_role(&RegisterRole::ReturnAddress)
+                .ok()
+                .and_then(|reg| reg.value);
+
+            let program_counter = unwind_registers.get_program_counter_mut().unwrap();
+
+            let Ok(current_pc) =
+                callee_frame_registers.get_register_value_by_role(&RegisterRole::ProgramCounter)
+            else {
+                let error =    probe_rs::Error::Other(
+                        "UNWIND: Tried to unwind return address value where current program counter is unknown.".to_string()
+                    );
+                tracing::error!("{:?}", &error);
+                if let Some(first_frame) = stack_frames.last_mut() {
+                    first_frame.function_name =
+                        format!("{} : ERROR: {error}", first_frame.function_name);
+                };
+                break 'unwind;
+            };
+            // NOTE: PC = Value of the unwound LR, i.e. the first instruction after the one that called this function.
+            // If both the LR and PC registers have undefined rules, this will prevent the unwind from continuing.
+            let mut register_rule_string = "PC=(unwound LR) (dwarf Undefined)".to_string();
+            program_counter.value = unwound_return_address.and_then(|return_address| {
+                unwind_program_counter_register(
+                    return_address,
+                    current_pc,
+                    instruction_set,
+                    &mut register_rule_string,
+                )
+            });
+
+            tracing::trace!(
+                "UNWIND - {:>10}: Caller: {}\tCallee: {}\tRule: {}",
+                program_counter.get_register_name(),
+                program_counter.value.unwrap_or_default(),
+                callee_frame_registers
+                    .get_register(program_counter.core_register.id)
+                    .and_then(|reg| reg.value)
+                    .unwrap_or_default(),
+                register_rule_string,
+            );
+
             if callee_frame_registers == unwind_registers {
                 tracing::debug!("No change, preventing infinite loop");
                 break;
@@ -1047,9 +1046,7 @@ pub fn determine_cfa<R: gimli::ReaderOffset>(
 pub fn unwind_pc_without_debuginfo(
     unwind_registers: &mut DebugRegisters,
     frame_pc: u64,
-    stack_frames: &[StackFrame],
     instruction_set: Option<probe_rs::InstructionSet>,
-    memory: &mut dyn MemoryInterface,
 ) -> ControlFlow<Option<DebugError>> {
     // For non exception frames, we cannot do stack unwinding if we do not have debug info.
     // However, there is one case where we can continue. When the frame registers have a valid
@@ -1058,25 +1055,33 @@ pub fn unwind_pc_without_debuginfo(
     // we will be able to continue unwinding.
     // If the calling frame has no debug info, then the unwinding will end with that frame.
     let callee_frame_registers = unwind_registers.clone();
-    let mut unwound_return_address: Option<RegisterValue> = unwind_registers
+    let unwound_return_address: Option<RegisterValue> = unwind_registers
         .get_return_address()
         .and_then(|lr| lr.value);
 
     // This will update the program counter in the `unwind_registers` with the PC value calculated from the LR value.
     if let Some(calling_pc) = unwind_registers.get_program_counter_mut() {
-        if let ControlFlow::Break(error) = unwind_register(
-            calling_pc,
-            &callee_frame_registers,
-            None,
-            stack_frames
-                .last()
-                .and_then(|first_frame| first_frame.canonical_frame_address),
-            &mut unwound_return_address,
-            memory,
-            instruction_set,
-        ) {
-            return ControlFlow::Break(Some(error.into()));
+        let mut register_rule_string = "PC=(unwound LR) (dwarf Undefined)".to_string();
+
+        let Ok(current_pc) =
+            callee_frame_registers.get_register_value_by_role(&RegisterRole::ProgramCounter)
+        else {
+            return ControlFlow::Break(
+                Some(probe_rs::Error::Other(
+                    "UNWIND: Tried to unwind return address value where current program counter is unknown.".to_string()
+                ).into())
+            );
         };
+        // NOTE: PC = Value of the unwound LR, i.e. the first instruction after the one that called this function.
+        // If both the LR and PC registers have undefined rules, this will prevent the unwind from continuing.
+        unwound_return_address.and_then(|return_address| {
+            unwind_program_counter_register(
+                return_address,
+                current_pc,
+                instruction_set,
+                &mut register_rule_string,
+            )
+        });
 
         if calling_pc
             .value
@@ -1095,82 +1100,93 @@ pub fn unwind_pc_without_debuginfo(
 
 /// A per_register unwind, applying register rules and updating the [`registers::DebugRegister`] value as appropriate, before returning control to the calling function.
 pub fn unwind_register(
-    debug_register: &mut super::DebugRegister,
+    debug_register: &super::DebugRegister,
     // The callee_frame_registers are used to lookup values and never updated.
     callee_frame_registers: &DebugRegisters,
-    unwind_info: Option<&gimli::UnwindTableRow<GimliReaderOffset>>,
+    unwind_info: &gimli::UnwindTableRow<GimliReaderOffset>,
     unwind_cfa: Option<u64>,
-    unwound_return_address: &mut Option<RegisterValue>,
     memory: &mut dyn MemoryInterface,
-    instruction_set: Option<InstructionSet>,
-) -> ControlFlow<probe_rs::Error, ()> {
+) -> Result<Option<RegisterValue>, probe_rs::Error> {
     use gimli::read::RegisterRule;
 
     // If we do not have unwind info, or there is no register rule, then use UnwindRule::Undefined.
     let register_rule = debug_register
         .dwarf_id
-        .and_then(|register_position| {
-            unwind_info.map(|unwind_info| unwind_info.register(gimli::Register(register_position)))
-        })
+        .map(|register_position| unwind_info.register(gimli::Register(register_position)))
         .unwrap_or(RegisterRule::Undefined);
 
+    unwind_register_using_rule(
+        debug_register.core_register,
+        callee_frame_registers,
+        unwind_cfa,
+        memory,
+        register_rule,
+    )
+}
+
+fn unwind_register_using_rule(
+    debug_register: &probe_rs::CoreRegister,
+    callee_frame_registers: &DebugRegisters,
+    unwind_cfa: Option<u64>,
+    memory: &mut dyn MemoryInterface,
+    register_rule: gimli::RegisterRule<usize>,
+) -> Result<Option<RegisterValue>, probe_rs::Error> {
+    use gimli::read::RegisterRule;
+
     let mut register_rule_string = format!("{register_rule:?}");
 
     let new_value = match register_rule {
         RegisterRule::Undefined => {
-            // In many cases, the DWARF has `Undefined` rules for variables like frame pointer, program counter, etc., so we hard-code some rules here to make sure unwinding can continue. If there is a valid rule, it will bypass these hardcoded ones.
+            // In many cases, the DWARF has `Undefined` rules for variables like frame pointer, program counter, etc.,
+            // so we hard-code some rules here to make sure unwinding can continue. If there is a valid rule, it will bypass these hardcoded ones.
             match &debug_register {
-                fp if fp
-                    .core_register
-                    .register_has_role(RegisterRole::FramePointer) =>
-                {
+                fp if fp.register_has_role(RegisterRole::FramePointer) => {
                     register_rule_string = "FP=CFA (dwarf Undefined)".to_string();
                     unwind_cfa.map(|unwind_cfa| {
-                        if fp.is_u32() {
+                        if fp.data_type == RegisterDataType::UnsignedInteger(32) {
                             RegisterValue::U32(unwind_cfa as u32 & !0b11)
                         } else {
                             RegisterValue::U64(unwind_cfa & !0b11)
                         }
                     })
                 }
-                sp if sp
-                    .core_register
-                    .register_has_role(RegisterRole::StackPointer) =>
-                {
+                sp if sp.register_has_role(RegisterRole::StackPointer) => {
                     // NOTE: [ARMv7-M Architecture Reference Manual](https://developer.arm.com/documentation/ddi0403/ee), Section B.1.4.1: Treat bits [1:0] as `Should be Zero or Preserved`
                     // - Applying this logic to RISC-V has no adverse effects, since all incoming addresses are already 32-bit aligned.
                     register_rule_string = "SP=CFA (dwarf Undefined)".to_string();
                     unwind_cfa.map(|unwind_cfa| {
-                        if sp.is_u32() {
+                        if sp.data_type == RegisterDataType::UnsignedInteger(32) {
                             RegisterValue::U32(unwind_cfa as u32 & !0b11)
                         } else {
                             RegisterValue::U64(unwind_cfa & !0b11)
                         }
                     })
                 }
-                lr if lr
-                    .core_register
-                    .register_has_role(RegisterRole::ReturnAddress) =>
-                {
+                lr if lr.register_has_role(RegisterRole::ReturnAddress) => {
                     let Ok(current_pc) = callee_frame_registers
                         .get_register_value_by_role(&RegisterRole::ProgramCounter)
                     else {
-                        return ControlFlow::Break(
+                        return Err(
                             probe_rs::Error::Other(
                                 "UNWIND: Tried to unwind return address value where current program counter is unknown.".to_string()
                             )
                         );
                     };
-                    let Ok(current_lr) = callee_frame_registers
-                        .get_register_value_by_role(&RegisterRole::ReturnAddress)
+                    let Some(current_lr) = callee_frame_registers
+                        .get_register_by_role(&RegisterRole::ReturnAddress)
+                        .ok()
+                        .and_then(|lr| lr.value)
                     else {
-                        return ControlFlow::Break(
+                        return Err(
                             probe_rs::Error::Other(
                                 "UNWIND: Tried to unwind return address value where current return address is unknown.".to_string()
                             )
                         );
                     };
-                    *unwound_return_address = if current_pc == current_lr & !0b1 {
+
+                    let current_lr_value: u64 = current_lr.try_into()?;
+
+                    if current_pc == current_lr_value & !0b1 {
                         // If the previous PC is the same as the half-word aligned current LR,
                         // we have no way of inferring the previous frames LR until we have the PC.
                         register_rule_string = "LR=Undefined (dwarf Undefined)".to_string();
@@ -1178,44 +1194,20 @@ pub fn unwind_register(
                     } else {
                         // We can attempt to continue unwinding with the current LR value, e.g. inlined code.
                         register_rule_string = "LR=Current LR (dwarf Undefined)".to_string();
-                        lr.value
-                    };
-
-                    *unwound_return_address
+                        Some(current_lr)
+                    }
                 }
-                pc if pc
-                    .core_register
-                    .register_has_role(RegisterRole::ProgramCounter) =>
-                {
-                    let Ok(current_pc) = callee_frame_registers
-                        .get_register_value_by_role(&RegisterRole::ProgramCounter)
-                    else {
-                        return ControlFlow::Break(
-                            probe_rs::Error::Other(
-                                "UNWIND: Tried to unwind return address value where current program counter is unknown.".to_string()
-                            )
-                        );
-                    };
-                    // NOTE: PC = Value of the unwound LR, i.e. the first instruction after the one that called this function.
-                    // If both the LR and PC registers have undefined rules, this will prevent the unwind from continuing.
-                    register_rule_string = "PC=(unwound LR) (dwarf Undefined)".to_string();
-                    unwound_return_address.and_then(|return_address| {
-                        unwind_program_counter_register(
-                            return_address,
-                            current_pc,
-                            instruction_set,
-                            &mut register_rule_string,
-                        )
-                    })
+                pc if pc.register_has_role(RegisterRole::ProgramCounter) => {
+                    unreachable!("The program counter is handled separately")
                 }
                 other_register => {
                     // If the the register rule was not specified, then we either carry the previous value forward,
                     // or we clear the register value, depending on the architecture and register type.
-                    match other_register.core_register.unwind_rule {
+                    match other_register.unwind_rule {
                         UnwindRule::Preserve => {
                             register_rule_string = "Preserve".to_string();
                             callee_frame_registers
-                                .get_register(other_register.core_register.id)
+                                .get_register(other_register.id)
                                 .and_then(|reg| reg.value)
                         }
                         UnwindRule::Clear => {
@@ -1224,7 +1216,7 @@ pub fn unwind_register(
                         }
                         UnwindRule::SpecialRule => {
                             // When no DWARF rules are available, and it is not a special register like PC, SP, FP, etc.,
-                            // we will preserve the value. It is possible it might have its value set later if
+                            // we will clear the value. It is possible it might have its value set later if
                             // exception frame information is available.
                             register_rule_string = "Clear (no unwind rules specified)".to_string();
                             None
@@ -1235,13 +1227,13 @@ pub fn unwind_register(
         }
 
         RegisterRule::SameValue => callee_frame_registers
-            .get_register(debug_register.core_register.id)
+            .get_register(debug_register.id)
             .and_then(|reg| reg.value),
 
         RegisterRule::Offset(address_offset) => {
             // "The previous value of this register is saved at the address CFA+N where CFA is the current CFA value and N is a signed offset"
             let Some(unwind_cfa) = unwind_cfa else {
-                return ControlFlow::Break(probe_rs::Error::Other(
+                return Err(probe_rs::Error::Other(
                     "UNWIND: Tried to unwind `RegisterRule` at CFA = None.".to_string(),
                 ));
             };
@@ -1250,6 +1242,8 @@ pub fn unwind_register(
                 add_to_address(unwind_cfa, address_offset, address_size);
 
             register_rule_string = format!("CFA {register_rule:?}");
+
+            // TODO: This should be the size of the register, not the address size.
             let result = match address_size {
                 4 => {
                     let mut buff = [0u8; 4];
@@ -1264,7 +1258,7 @@ pub fn unwind_register(
                         .map(|_| RegisterValue::U64(u64::from_le_bytes(buff)))
                 }
                 _ => {
-                    return ControlFlow::Break(Error::Other(format!(
+                    return Err(Error::Other(format!(
                         "UNWIND: Address size {} not supported.",
                         address_size
                     )));
@@ -1272,16 +1266,7 @@ pub fn unwind_register(
             };
 
             match result {
-                Ok(register_value) => {
-                    if debug_register
-                        .core_register
-                        .register_has_role(RegisterRole::ReturnAddress)
-                    {
-                        // We need to store this value to be used by the calculation of the PC.
-                        *unwound_return_address = Some(register_value);
-                    }
-                    Some(register_value)
-                }
+                Ok(register_value) => Some(register_value),
                 Err(error) => {
                     tracing::error!(
                         "UNWIND: Rule: Offset {} from address {:#010x}",
@@ -1289,34 +1274,33 @@ pub fn unwind_register(
                         unwind_cfa
                     );
 
-                    return ControlFlow::Break(
+                    return Err(
                         Error::Other(format!(
                             "UNWIND: Failed to read value for register {} from address {} ({} bytes): {}",
-                            debug_register.get_register_name(),
+                            debug_register,
                             RegisterValue::from(previous_frame_register_address),
                             4,
                             error
-                        )),
-                    );
+                        ),
+                    ));
                 }
             }
         }
         //TODO: Implement the remainder of these `RegisterRule`s
         _ => unimplemented!(),
     };
-    debug_register.value = new_value;
 
     tracing::trace!(
         "UNWIND - {:>10}: Caller: {}\tCallee: {}\tRule: {}",
-        debug_register.get_register_name(),
-        debug_register.value.unwrap_or_default(),
+        debug_register,
+        new_value.unwrap_or_default(),
         callee_frame_registers
-            .get_register(debug_register.core_register.id)
+            .get_register(debug_register.id)
             .and_then(|reg| reg.value)
             .unwrap_or_default(),
         register_rule_string,
     );
-    ControlFlow::Continue(())
+    Ok(new_value)
 }
 
 /// Helper function to determine the program counter value for the previous frame.
@@ -1416,13 +1400,17 @@ mod test {
         DebugInfo, DebugRegister, DebugRegisters,
     };
 
+    use gimli::RegisterRule;
     use probe_rs::{
-        architecture::arm::core::registers::cortex_m::CORTEX_M_CORE_REGISTERS, test::MockMemory,
+        architecture::arm::core::registers::cortex_m::{self, CORTEX_M_CORE_REGISTERS},
+        test::MockMemory,
         CoreDump, RegisterValue,
     };
     use std::path::{Path, PathBuf};
     use test_case::test_case;
 
+    use super::unwind_register_using_rule;
+
     /// Get the full path to a file in the `tests` directory.
     fn get_path_for_test_files(relative_file: &str) -> PathBuf {
         let mut path = PathBuf::from(env!("CARGO_MANIFEST_DIR"));
@@ -1548,7 +1536,7 @@ mod test {
 
         let next_frame = &frames[1];
         assert_eq!(next_frame.function_name, "SVC");
-        assert_eq!(next_frame.pc, RegisterValue::U32(0x00000180));
+        assert_eq!(next_frame.pc, RegisterValue::U32(0x0000017f));
 
         // Expected stack frame(s):
         // Frame 0: __cortex_m_rt_SVCall_trampoline @ 0x00000182
@@ -1695,15 +1683,16 @@ mod test {
         );
 
         assert_eq!(frames[1].pc, RegisterValue::U32(0x0000018A)); // <-- This is the instruction *after* the jump into the topmost frame.
-                                                                  // The PC value in the exception data
-                                                                  // depends on the exception type, and for some exceptions, it will
-                                                                  // be the address of the instruction that caused the exception, while for other exceptions
-                                                                  // it will be the address of the next instruction after the instruction that caused the exception.
-                                                                  // See: https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/ARMv7-M-exception-model/Exception-entry-behavior?lang=en
+
+        // The PC value in the exception data
+        // depends on the exception type, and for some exceptions, it will
+        // be the address of the instruction that caused the exception, while for other exceptions
+        // it will be the address of the next instruction after the instruction that caused the exception.
+        // See: https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/ARMv7-M-exception-model/Exception-entry-behavior?lang=en
         assert_eq!(
             frames[1]
                 .registers
-                .get_frame_pointer()
+                .get_register(probe_rs::RegisterId(7))
                 .and_then(|r| r.value),
             Some(RegisterValue::U32(0x2001ffc8))
         );
@@ -1862,9 +1851,9 @@ mod test {
             0x00000000, // R10
             0x00000000, // R11
             0x5000050c, // R12
-            0x20003ff0, // R13
-            0x00200000, // R14
-            0x000002e4, // R15
+            0x20003ff0, // R13 (SP)
+            0x00200000, // R14 (RA)
+            0x000002e4, // R15 (PC)
             0x20003ff0, // MSP
             0x00000000, // PSP
             0x61000000, // XPSR
@@ -2039,4 +2028,107 @@ mod test {
         // and also because they provide better diffs.
         insta::assert_yaml_snapshot!(snapshot_name, static_variables);
     }
+
+    #[test]
+    fn unwind_same_value() {
+        let rule = gimli::RegisterRule::SameValue;
+
+        let mut callee_frame_registers = DebugRegisters::default();
+        let debug_register = CORTEX_M_CORE_REGISTERS.core_registers().next().unwrap();
+
+        let expected_value = Some(RegisterValue::U32(0x1234));
+
+        callee_frame_registers.0.push(DebugRegister {
+            core_register: debug_register,
+            dwarf_id: Some(0),
+            value: expected_value,
+        });
+
+        let mut memory = MockMemory::new();
+
+        let value = unwind_register_using_rule(
+            debug_register,
+            &callee_frame_registers,
+            None,
+            &mut memory,
+            rule,
+        )
+        .unwrap();
+
+        assert_eq!(value, expected_value);
+    }
+
+    #[test]
+    fn unwind_offset() {
+        let cfa = 0x1000;
+        let offset = 4;
+        let rule = gimli::RegisterRule::Offset(offset as i64);
+        let expected_value = 0xcafe;
+
+        let expected_register_value = Some(RegisterValue::U32(expected_value));
+
+        let mut memory = MockMemory::new();
+        memory.add_word_range(cfa + offset, &[expected_value]);
+
+        let mut callee_frame_registers = DebugRegisters::default();
+        let debug_register = CORTEX_M_CORE_REGISTERS.core_registers().next().unwrap();
+
+        callee_frame_registers.0.push(DebugRegister {
+            core_register: debug_register,
+            dwarf_id: Some(0),
+            value: None,
+        });
+
+        // This is necessary for the unwind code to determine the address size of the system
+        callee_frame_registers.0.push(DebugRegister {
+            core_register: &cortex_m::PC,
+            dwarf_id: Some(15),
+            value: Some(RegisterValue::U32(0x0)),
+        });
+
+        let value = unwind_register_using_rule(
+            debug_register,
+            &callee_frame_registers,
+            Some(cfa),
+            &mut memory,
+            rule,
+        )
+        .unwrap();
+
+        assert_eq!(value, expected_register_value);
+    }
+
+    #[test]
+    fn unwind_undefined_for_frame_pointer() {
+        let mut callee_frame_registers = DebugRegisters::default();
+        callee_frame_registers.0.push(DebugRegister {
+            core_register: &cortex_m::FP,
+            dwarf_id: Some(7),
+            value: Some(RegisterValue::U32(0x100)),
+        });
+
+        // This is necessary for the unwind code to determine the address size of the system
+        callee_frame_registers.0.push(DebugRegister {
+            core_register: &cortex_m::PC,
+            dwarf_id: Some(15),
+            value: Some(RegisterValue::U32(0x0)),
+        });
+
+        let cfa = 0x200;
+
+        let mut memory = MockMemory::new();
+
+        let value = unwind_register_using_rule(
+            &cortex_m::FP,
+            &callee_frame_registers,
+            Some(cfa),
+            &mut memory,
+            RegisterRule::Undefined,
+        )
+        .unwrap();
+
+        // If there is no rule defined for the frame pointer,
+        // we assume that it is the same as the canonical frame address.
+        assert_eq!(value, Some(RegisterValue::U32(0x200)));
+    }
 }
diff --git a/probe-rs-debug/src/exception_handling.rs b/probe-rs-debug/src/exception_handling.rs
index 0e8ca511..8d32f9c3 100644
--- a/probe-rs-debug/src/exception_handling.rs
+++ b/probe-rs-debug/src/exception_handling.rs
@@ -134,16 +134,10 @@ pub trait ExceptionInterface {
         &self,
         unwind_registers: &mut DebugRegisters,
         frame_pc: u64,
-        stack_frames: &[StackFrame],
+        _stack_frames: &[StackFrame],
         instruction_set: Option<probe_rs::InstructionSet>,
-        memory: &mut dyn MemoryInterface,
+        _memory: &mut dyn MemoryInterface,
     ) -> ControlFlow<Option<DebugError>> {
-        unwind_pc_without_debuginfo(
-            unwind_registers,
-            frame_pc,
-            stack_frames,
-            instruction_set,
-            memory,
-        )
+        unwind_pc_without_debuginfo(unwind_registers, frame_pc, instruction_set)
     }
 }
diff --git a/probe-rs-debug/src/exception_handling/armv6m.rs b/probe-rs-debug/src/exception_handling/armv6m.rs
index b0fc80b1..46e396e1 100644
--- a/probe-rs-debug/src/exception_handling/armv6m.rs
+++ b/probe-rs-debug/src/exception_handling/armv6m.rs
@@ -1,5 +1,5 @@
 use crate::{DebugError, DebugInfo, DebugRegisters};
-use probe_rs::{Error, MemoryInterface};
+use probe_rs::MemoryInterface;
 
 use super::{armv6m_armv7m_shared, ExceptionInfo, ExceptionInterface};
 
@@ -63,18 +63,15 @@ impl ExceptionReason {
 
     /// Determines how the exception return address should be offset when unwinding the stack.
     /// See Armv6-M Architecture Reference Manual, section B1.5.6.
-    pub(crate) fn is_precise_fault(
-        &self,
-        _memory: &mut dyn MemoryInterface,
-    ) -> Result<bool, Error> {
-        Ok(match self {
+    pub(crate) fn is_precise_fault(&self) -> bool {
+        match self {
             ExceptionReason::HardFault => {
                 // This should be true for synchronous exceptions, and false otherwise.
                 // TODO: Figure out how to differentiate that on ARMv6-M.
                 true
             }
             _ => false,
-        })
+        }
     }
 }
 
@@ -86,14 +83,9 @@ impl ExceptionInterface for ArmV6MExceptionHandler {
         &self,
         memory_interface: &mut dyn MemoryInterface,
         stackframe_registers: &DebugRegisters,
-        debug_info: &DebugInfo,
+        _debug_info: &DebugInfo,
     ) -> Result<Option<ExceptionInfo>, DebugError> {
-        armv6m_armv7m_shared::exception_details(
-            self,
-            memory_interface,
-            stackframe_registers,
-            debug_info,
-        )
+        armv6m_armv7m_shared::exception_details(self, memory_interface, stackframe_registers)
     }
 
     fn calling_frame_registers(
@@ -102,24 +94,37 @@ impl ExceptionInterface for ArmV6MExceptionHandler {
         stackframe_registers: &crate::DebugRegisters,
         raw_exception: u32,
     ) -> Result<crate::DebugRegisters, DebugError> {
+        let exception_reason = ExceptionReason::from(raw_exception);
+
+        // This shouldn't be called for Reset, because for Reset, no registers
+        // are stored on the stack.
+        if exception_reason == ExceptionReason::Reset {
+            return Err(DebugError::Other(
+                "Unwinding over Reset is not possible.".to_string(),
+            ));
+        }
+
         let mut updated_registers = stackframe_registers.clone();
 
-        // Identify the correct location for the exception context. This is different between Armv6-M and Armv7-M.
-        let exception_reason = ExceptionReason::from(raw_exception);
-        if exception_reason.is_precise_fault(memory_interface)? {
-            let exception_context_address = updated_registers
-                .get_register_mut_by_role(&probe_rs::RegisterRole::StackPointer)?;
-            if let Some(sp_value) = exception_context_address.value.as_mut() {
-                sp_value.increment_address(0x8)?;
+        updated_registers =
+            armv6m_armv7m_shared::calling_frame_registers(memory_interface, &updated_registers)?;
+
+        if !exception_reason.is_precise_fault() {
+            // PC is always stored on the stack when unwinding an exception,
+            // so we know that it exists, and that it has a value
+            let pc = updated_registers.get_program_counter_mut().unwrap();
+
+            // If it is not a precise fault, the PC value in the stack frame will point to the next instruction.
+            // Subtracing 1 here so that the PC value points to the instruction that caused the fault.
+            if pc.value.as_mut().unwrap().decrement_address(1).is_err() {
+                // Ignore errors here, better to continue in the unlikely case that we encounter PC = 0x0.
+                // It might be that in that case, the actual exception *was* a precise fault.
+                tracing::debug!(
+                    "UNWIND: Failed to reproduce caller program counter, using PC unchanged."
+                );
             }
         }
 
-        updated_registers = armv6m_armv7m_shared::calling_frame_registers(
-            memory_interface,
-            &updated_registers,
-            raw_exception,
-        )?;
-
         Ok(updated_registers)
     }
 
diff --git a/probe-rs-debug/src/exception_handling/armv6m_armv7m_shared.rs b/probe-rs-debug/src/exception_handling/armv6m_armv7m_shared.rs
index 8ba46a89..664c0a21 100644
--- a/probe-rs-debug/src/exception_handling/armv6m_armv7m_shared.rs
+++ b/probe-rs-debug/src/exception_handling/armv6m_armv7m_shared.rs
@@ -1,12 +1,6 @@
-use std::ops::ControlFlow;
-
-use crate::{
-    determine_cfa, get_object_reference, get_unwind_info, stack_frame::StackFrameInfo,
-    unwind_register, DebugError, DebugInfo, DebugRegisters, StackFrame,
-};
+use crate::{get_object_reference, DebugError, DebugRegisters, StackFrame};
 use bitfield::bitfield;
 use probe_rs::{Error, MemoryInterface, RegisterRole, RegisterValue};
-use probe_rs_target::InstructionSet;
 
 use super::{ExceptionInfo, ExceptionInterface};
 
@@ -73,114 +67,89 @@ pub(crate) fn exception_details(
     exception_interface: &impl ExceptionInterface,
     memory_interface: &mut dyn MemoryInterface,
     stackframe_registers: &DebugRegisters,
-    debug_info: &DebugInfo,
 ) -> Result<Option<ExceptionInfo>, DebugError> {
     let frame_return_address = get_stack_frame_return_address(stackframe_registers)?;
+    let frame_return_address = ExcReturn(frame_return_address);
 
-    if ExcReturn(frame_return_address).is_exception_flag() != 0xF {
+    if frame_return_address.is_exception_flag() != 0xF {
         // This is a normal function return / not an exception.
         return Ok(None);
     }
 
     let raw_exception = exception_interface.raw_exception(stackframe_registers)?;
-    let registers = exception_interface.calling_frame_registers(
+
+    if raw_exception == 1 {
+        let mut stackframe_registers = stackframe_registers.clone();
+
+        // We don't know what happened before Reset
+        for stackframe_register in &mut stackframe_registers.0 {
+            stackframe_register.value = None;
+        }
+
+        // This is a reset exception.
+        return Ok(Some(ExceptionInfo {
+            raw_exception,
+            description: "Reset".to_string(),
+            handler_frame: StackFrame {
+                id: get_object_reference(),
+                function_name: "Reset".to_string(),
+                source_location: None,
+                registers: stackframe_registers.clone(),
+                // The PC value is not 0, this should be the address of the reset vector
+                pc: RegisterValue::U32(0),
+                frame_base: None,
+                is_inlined: false,
+                local_variables: None,
+                canonical_frame_address: None,
+            },
+        }));
+    }
+
+    let mut registers = exception_interface.calling_frame_registers(
         memory_interface,
         stackframe_registers,
         raw_exception,
     )?;
     let description = exception_interface.exception_description(raw_exception, memory_interface)?;
 
-    let exception_frame_pc = registers.get_register_value_by_role(&RegisterRole::ProgramCounter)?;
+    let exception_frame_pc = registers.get_register_mut_by_role(&RegisterRole::ProgramCounter)?;
+
+    // TODO: If this was not a precise exception, the program counter will be the address of the next instruction.
+    //       We have to adjust the program counter to point to the instruction that caused the exception.
+
+    // unwrap: We know that we have a PC value, unwinding an exception will retrieve it from the stack
+    let pc_value = exception_frame_pc.value.unwrap();
 
     let mut handler_frame = StackFrame {
         id: get_object_reference(),
         function_name: description.clone(),
         source_location: None,
         registers,
-        pc: RegisterValue::U32(exception_frame_pc as u32),
+        pc: pc_value,
         frame_base: None,
         is_inlined: false,
         local_variables: None,
         canonical_frame_address: None,
     };
 
-    // A fault that is escalated to the priority of a HardFault retains the program counter value of the original fault,
-    // so we have to unwind the frame pointer that matches.
-    if raw_exception == 3 {
-        // A fault that is escalated to the priority of a HardFault retains program counter value of the original fault,
-        // So we have to unwind the frame pointer that matches.
-        // Determining the frame base may need the CFA (Canonical Frame Address) to be calculated first.
-        let mut unwind_context = Box::new(gimli::UnwindContext::new());
-        // let exception_interface = exception_handler_for_core(memory_interface.core.core_type());
-        // let instruction_set = memory_interface.core.instruction_set().ok();
-        let unwind_info = get_unwind_info(
-            &mut unwind_context,
-            &debug_info.frame_section,
-            exception_frame_pc,
-        )?;
-        handler_frame.canonical_frame_address =
-            determine_cfa(&handler_frame.registers, unwind_info)?;
-        let Ok((_, functions)) = debug_info.get_function_dies(exception_frame_pc) else {
-            handler_frame.function_name = format!("{} : ERROR: While resolving function information for the program counter ({exception_frame_pc:#010x}) that caused the exception.", handler_frame.function_name);
-            // Return the available exception info, along with the error information captured in the function_name.
-            return Ok(Some(ExceptionInfo {
-                raw_exception,
-                description,
-                handler_frame,
-            }));
-        };
-        if functions.is_empty() {
-            handler_frame.function_name = format!("{} : ERROR: No function information for the program counter ({exception_frame_pc:#010x}) that caused the exception.", handler_frame.function_name);
-            // Return the available exception info, along with the error information captured in the function_name.
-            return Ok(Some(ExceptionInfo {
-                raw_exception,
-                description,
-                handler_frame,
-            }));
-        }
-        handler_frame.frame_base = functions[0].frame_base(
-            debug_info,
-            memory_interface,
-            StackFrameInfo {
-                registers: &handler_frame.registers,
-                frame_base: None,
-                canonical_frame_address: handler_frame.canonical_frame_address,
-            },
-        )?;
-        let callee_frame_registers = handler_frame.registers.clone();
-        if let ControlFlow::Break(error) = unwind_register(
-            handler_frame
-                .registers
-                .get_register_mut_by_role(&RegisterRole::FramePointer)?,
-            &callee_frame_registers,
-            Some(unwind_info),
-            handler_frame.canonical_frame_address,
-            &mut None,
-            memory_interface,
-            Some(InstructionSet::Thumb2),
-        ) {
-            tracing::error!("{:?}", &error);
-            handler_frame.function_name =
-                format!("{} : ERROR: {error}", handler_frame.function_name);
-        };
-        // Now we can update the stack pointer also, but
-        // first we have to determine the size of the exception data on the stack.
-        // See <https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/ARMv7-M-exception-model/Exception-entry-behavior?lang=en>
-        let frame_size = if ExcReturn(frame_return_address).use_standard_stackframe() {
-            // This is a standard exception frame.
-            0x20usize
-        } else {
-            // This is an extended frame that includes FPU registers.
-            0x68
-        };
-        // // Now we can update the registers with the new stack pointer.
-        let sp = handler_frame
-            .registers
-            .get_register_mut_by_role(&RegisterRole::StackPointer)?;
-        if let Some(sp_value) = sp.value.as_mut() {
-            sp_value.increment_address(frame_size)?;
-        }
+    // Now we can update the stack pointer also, but
+    // first we have to determine the size of the exception data on the stack.
+    // See <https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/ARMv7-M-exception-model/Exception-entry-behavior?lang=en>
+    let frame_size = if frame_return_address.use_standard_stackframe() {
+        // This is a standard exception frame.
+        0x20usize
+    } else {
+        // This is an extended frame that includes FPU registers.
+        0x68
+    };
+    // // Now we can update the registers with the new stack pointer.
+    let sp = handler_frame
+        .registers
+        .get_register_mut_by_role(&RegisterRole::StackPointer)?;
+    if let Some(sp_value) = sp.value.as_mut() {
+        sp_value.increment_address(frame_size)?;
     }
+    //}
 
     Ok(Some(ExceptionInfo {
         raw_exception,
@@ -239,7 +208,6 @@ pub(crate) fn raw_exception(stackframe_registers: &crate::DebugRegisters) -> Res
 pub(crate) fn calling_frame_registers(
     memory: &mut dyn MemoryInterface,
     stackframe_registers: &crate::DebugRegisters,
-    _raw_exception: u32,
 ) -> Result<crate::DebugRegisters, probe_rs::Error> {
     let exception_context_address: u32 =
         stackframe_registers.get_register_value_by_role(&RegisterRole::StackPointer)? as u32;
diff --git a/probe-rs-debug/src/exception_handling/armv7m.rs b/probe-rs-debug/src/exception_handling/armv7m.rs
index ec4c97ef..dfd97c6b 100644
--- a/probe-rs-debug/src/exception_handling/armv7m.rs
+++ b/probe-rs-debug/src/exception_handling/armv7m.rs
@@ -284,14 +284,17 @@ impl ExceptionReason {
         }
     }
 
-    /// Determines how the exception return address should be offset when unwinding the stack.
-    /// See Armv7-M Architecture Reference Manual, Section B1.5.6.
+    /// If a precise fault occurs, the PC value in the stack frame will point to the instruction that caused the fault.
+    /// This means that the PC value in the stack frame is the address of the faulting instruction.
+    ///
+    /// For other faults, or interrupts, the PC value in the stack frame will point to the next instruction to be executed.
+    ///
+    /// See Armv7-M Architecture Reference Manual, section B1.5.6.
     pub(crate) fn is_precise_fault(&self, memory: &mut dyn MemoryInterface) -> Result<bool, Error> {
         let is_precise = match self {
-            ExceptionReason::HardFault
-            | ExceptionReason::BusFault
-            | ExceptionReason::MemoryManagementFault
-            | ExceptionReason::UsageFault => {
+            // Usage fault and memory management fault are always precise.
+            ExceptionReason::UsageFault | ExceptionReason::MemoryManagementFault => true,
+            ExceptionReason::HardFault | ExceptionReason::BusFault => {
                 // Same logic for direct and escalated faults.
                 let cfsr = Cfsr(memory.read_word_32(Cfsr::get_mmio_address())?);
                 cfsr.bf_precise_data_access_error()
@@ -300,7 +303,7 @@ impl ExceptionReason {
                     || cfsr.usage_fault() > 0
             }
             ExceptionReason::DebugMonitor => {
-                // This should be true for syncrhonous exceptions, and false otherwise.
+                // This should be true for synchronous exceptions, and false otherwise.
                 // TODO: Identify if this debug event was triggered by a vector catch and decode the corresponding FSR. Not a priority for unwinding purposes.
                 true
             }
@@ -318,14 +321,9 @@ impl ExceptionInterface for ArmV7MExceptionHandler {
         &self,
         memory_interface: &mut dyn MemoryInterface,
         stackframe_registers: &DebugRegisters,
-        debug_info: &DebugInfo,
+        _debug_info: &DebugInfo,
     ) -> Result<Option<ExceptionInfo>, DebugError> {
-        armv6m_armv7m_shared::exception_details(
-            self,
-            memory_interface,
-            stackframe_registers,
-            debug_info,
-        )
+        armv6m_armv7m_shared::exception_details(self, memory_interface, stackframe_registers)
     }
 
     fn calling_frame_registers(
@@ -334,23 +332,31 @@ impl ExceptionInterface for ArmV7MExceptionHandler {
         stackframe_registers: &crate::DebugRegisters,
         raw_exception: u32,
     ) -> Result<crate::DebugRegisters, DebugError> {
+        let exception_reason = ExceptionReason::from(raw_exception);
+
+        // This shouldn't be called for Reset, because for Reset, no registers
+        // are stored on the stack.
+        if exception_reason == ExceptionReason::Reset {
+            return Err(DebugError::Other(
+                "Unwinding over Reset is not possible.".to_string(),
+            ));
+        }
+
         let mut updated_registers = stackframe_registers.clone();
 
-        // Identify the correct location for the exception context. This is different between Armv6-M and Armv7-M.
-        let exception_reason = ExceptionReason::from(raw_exception);
-        if exception_reason.is_precise_fault(memory_interface)? {
-            let exception_context_address = updated_registers
-                .get_register_mut_by_role(&probe_rs::RegisterRole::StackPointer)?;
-            if let Some(sp_value) = exception_context_address.value.as_mut() {
-                sp_value.increment_address(0x8)?;
-            }
+        updated_registers =
+            armv6m_armv7m_shared::calling_frame_registers(memory_interface, &updated_registers)?;
+
+        if !exception_reason.is_precise_fault(memory_interface)? {
+            // PC is always stored on the stack when unwinding an exception,
+            // so we know that it exists, and that it has a value
+            let pc = updated_registers.get_program_counter_mut().unwrap();
+
+            // If it is not a precise fault, the PC value in the stack frame will point to the next instruction.
+            // Subtracing 1 here so that the PC value points to the instruction that caused the fault.
+            pc.value.as_mut().unwrap().decrement_address(1)?;
         }
 
-        updated_registers = armv6m_armv7m_shared::calling_frame_registers(
-            memory_interface,
-            &updated_registers,
-            raw_exception,
-        )?;
         Ok(updated_registers)
     }
 
diff --git a/probe-rs-debug/src/exception_handling/xtensa.rs b/probe-rs-debug/src/exception_handling/xtensa.rs
index a60c4cbf..1f64faeb 100644
--- a/probe-rs-debug/src/exception_handling/xtensa.rs
+++ b/probe-rs-debug/src/exception_handling/xtensa.rs
@@ -50,18 +50,12 @@ impl ExceptionInterface for XtensaExceptionHandler {
         &self,
         unwind_registers: &mut DebugRegisters,
         frame_pc: u64,
-        stack_frames: &[StackFrame],
+        _stack_frames: &[StackFrame],
         instruction_set: Option<probe_rs::InstructionSet>,
         memory: &mut dyn MemoryInterface,
     ) -> ControlFlow<Option<DebugError>> {
         // Use the default method to unwind PC.
-        unwind_pc_without_debuginfo(
-            unwind_registers,
-            frame_pc,
-            stack_frames,
-            instruction_set,
-            memory,
-        )?;
+        unwind_pc_without_debuginfo(unwind_registers, frame_pc, instruction_set)?;
 
         // We can try and use FP to unwind SP and RA that allows us to continue unwinding.
 
diff --git a/probe-rs-debug/src/language/c.rs b/probe-rs-debug/src/language/c.rs
index 1d8cc8b5..2ea12231 100644
--- a/probe-rs-debug/src/language/c.rs
+++ b/probe-rs-debug/src/language/c.rs
@@ -27,11 +27,22 @@ impl ProgrammingLanguage for C {
                 "_Bool" => UnsignedInt::get_value(variable, None, memory, variable_cache).into(),
                 "char" => CChar::get_value(variable, memory, variable_cache).into(),
 
-                "unsigned char" | "unsigned int" | "short unsigned int" | "long unsigned int" => {
+                "unsigned char"
+                | "unsigned int"
+                | "short unsigned int"
+                | "long unsigned int"
+                | "long long unsigned int" => {
                     UnsignedInt::get_value(variable, None, memory, variable_cache).into()
                 }
-                "signed char" | "int" | "short int" | "long int" | "signed int"
-                | "short signed int" | "long signed int" => {
+                "signed char"
+                | "int"
+                | "short int"
+                | "long int"
+                | "long long int"
+                | "signed int"
+                | "short signed int"
+                | "long signed int"
+                | "long long signed int" => {
                     SignedInt::get_value(variable, None, memory, variable_cache).into()
                 }
 
@@ -43,7 +54,14 @@ impl ProgrammingLanguage for C {
                         VariableValue::Error(format!("Invalid byte size for float: {size}"))
                     }
                 },
-                // TODO: doubles
+                "double" => match variable.byte_size {
+                    Some(8) | None => f64::get_value(variable, memory, variable_cache)
+                        .map(format_float)
+                        .into(),
+                    Some(size) => {
+                        VariableValue::Error(format!("Invalid byte size for double: {size}"))
+                    }
+                },
                 _undetermined_value => VariableValue::Empty,
             },
 
diff --git a/probe-rs-debug/src/registers.rs b/probe-rs-debug/src/registers.rs
index db060579..5faaf7df 100644
--- a/probe-rs-debug/src/registers.rs
+++ b/probe-rs-debug/src/registers.rs
@@ -52,11 +52,6 @@ impl DebugRegister {
         Ok(None)
     }
 
-    /// Test if this is a 32-bit unsigned integer register
-    pub(crate) fn is_u32(&self) -> bool {
-        self.core_register.data_type == RegisterDataType::UnsignedInteger(32)
-    }
-
     /// A helper function to determine if the contained register value is equal to the maximum value that can be stored in that datatype.
     /// Will return false if the value is `None`
     pub(crate) fn is_max_value(&self) -> bool {
@@ -126,14 +121,15 @@ impl DebugRegisters {
 
     /// Gets the address size for this target, in bytes
     pub fn get_address_size_bytes(&self) -> usize {
-        self.get_program_counter().map_or_else(
-            || 0,
-            |debug_register| debug_register.core_register.size_in_bits().div_ceil(8),
-        )
+        self.get_program_counter()
+            .map(|debug_register| debug_register.core_register.size_in_bits().div_ceil(8))
+            .unwrap_or(0)
     }
 
     /// Get the canonical frame address, as specified in the [DWARF](https://dwarfstd.org) specification, section 6.4.
     /// [DWARF](https://dwarfstd.org)
+    ///
+    /// This is not always available
     pub fn get_frame_pointer(&self) -> Option<&DebugRegister> {
         self.0.iter().find(|debug_register| {
             debug_register
diff --git a/probe-rs/src/architecture/arm/core/registers/cortex_m.rs b/probe-rs/src/architecture/arm/core/registers/cortex_m.rs
index 70954ae4..c545b400 100644
--- a/probe-rs/src/architecture/arm/core/registers/cortex_m.rs
+++ b/probe-rs/src/architecture/arm/core/registers/cortex_m.rs
@@ -7,21 +7,24 @@ use crate::{
     CoreRegister, CoreRegisters, RegisterId,
 };
 
-pub(crate) const PC: CoreRegister = CoreRegister {
+/// Program counter (PC) register.
+pub const PC: CoreRegister = CoreRegister {
     roles: &[RegisterRole::Core("R15"), RegisterRole::ProgramCounter],
     id: RegisterId(15),
     data_type: RegisterDataType::UnsignedInteger(32),
     unwind_rule: UnwindRule::SpecialRule,
 };
 
-pub(crate) const FP: CoreRegister = CoreRegister {
+/// Frame pointer (FP) register.
+pub const FP: CoreRegister = CoreRegister {
     roles: &[RegisterRole::Core("R7"), RegisterRole::FramePointer],
     id: RegisterId(7),
     data_type: RegisterDataType::UnsignedInteger(32),
-    unwind_rule: UnwindRule::SpecialRule,
+    unwind_rule: UnwindRule::Preserve,
 };
 
-pub(crate) const SP: CoreRegister = CoreRegister {
+/// Stack pointer (SP) register.
+pub const SP: CoreRegister = CoreRegister {
     roles: &[RegisterRole::Core("R13"), RegisterRole::StackPointer],
     id: RegisterId(13),
     data_type: RegisterDataType::UnsignedInteger(32),
@@ -44,7 +47,7 @@ pub const XPSR: CoreRegister = CoreRegister {
     unwind_rule: UnwindRule::Preserve,
 };
 
-/// All off the Cortex-M core registers.
+/// All of the Cortex-M core registers.
 pub static CORTEX_M_CORE_REGISTERS: LazyLock<CoreRegisters> = LazyLock::new(|| {
     CoreRegisters::new(
         ARM32_COMMON_REGS_SET
diff --git a/probe-rs/targets/STM32H5_Series.yaml b/probe-rs/targets/STM32H5_Series.yaml
index fc4adedd..e44765d0 100644
--- a/probe-rs/targets/STM32H5_Series.yaml
+++ b/probe-rs/targets/STM32H5_Series.yaml
@@ -14,7 +14,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -60,7 +59,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -106,7 +104,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -152,7 +149,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -199,7 +195,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -254,7 +249,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -306,7 +300,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: Flash
@@ -343,7 +336,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -397,7 +389,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -452,7 +443,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -507,7 +497,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -562,7 +551,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -617,7 +605,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -672,7 +659,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -724,7 +710,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: Flash
@@ -761,7 +746,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -816,7 +800,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -871,7 +854,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -925,7 +907,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -979,7 +960,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1034,7 +1014,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1089,7 +1068,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1144,7 +1122,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1199,7 +1176,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1253,7 +1229,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1307,7 +1282,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1361,7 +1335,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1415,7 +1388,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1469,7 +1441,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1524,7 +1495,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1579,7 +1549,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1636,7 +1605,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1690,7 +1658,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1745,7 +1712,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1800,7 +1766,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1854,7 +1819,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1909,7 +1873,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -1963,7 +1926,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -2018,7 +1980,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -2073,7 +2034,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -2130,7 +2090,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -2184,7 +2143,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -2239,7 +2197,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -2294,7 +2251,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -2349,7 +2305,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
diff --git a/probe-rs/targets/STM32H7RS_Series.yaml b/probe-rs/targets/STM32H7RS_Series.yaml
index 1c017fba..23635a73 100644
--- a/probe-rs/targets/STM32H7RS_Series.yaml
+++ b/probe-rs/targets/STM32H7RS_Series.yaml
@@ -13,7 +13,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -95,7 +94,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -177,7 +175,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -258,7 +255,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -341,7 +337,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -423,7 +418,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -504,7 +498,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -586,7 +579,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -668,7 +660,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -749,7 +740,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -830,7 +820,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -912,7 +901,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -994,7 +982,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -1075,7 +1062,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -1158,7 +1144,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -1240,7 +1225,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -1321,7 +1305,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -1403,7 +1386,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -1485,7 +1467,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
@@ -1566,7 +1547,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Ram
     name: ITCM
diff --git a/probe-rs/targets/STM32H7_Series.yaml b/probe-rs/targets/STM32H7_Series.yaml
index e722215e..fc9fc79a 100644
--- a/probe-rs/targets/STM32H7_Series.yaml
+++ b/probe-rs/targets/STM32H7_Series.yaml
@@ -40,21 +40,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -111,21 +118,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -182,21 +196,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -253,21 +274,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -323,21 +351,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -393,21 +428,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -464,21 +506,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -535,21 +584,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -605,21 +661,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -675,21 +738,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -746,21 +816,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -818,21 +895,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -888,21 +972,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -958,21 +1049,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1028,21 +1126,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1099,21 +1204,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1170,21 +1282,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1241,21 +1360,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1312,21 +1438,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1383,21 +1516,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1453,21 +1593,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1524,21 +1671,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1594,21 +1748,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1666,21 +1827,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1736,21 +1904,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24050000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM2
     range:
       start: 0x30000000
+      end: 0x30004000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30004000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38004000
@@ -1816,28 +1991,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -1903,28 +2078,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -1990,28 +2165,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2077,28 +2252,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2165,28 +2340,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2253,28 +2428,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2341,28 +2516,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2429,28 +2604,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2516,28 +2691,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2603,28 +2778,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2690,28 +2865,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2777,28 +2952,28 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24060000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
       end: 0x30008000
     cores:
     - main
   - !Ram
-    name: RAM2_D2
+    name: SRAM2
     range:
       start: 0x30020000
       end: 0x30024000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2864,21 +3039,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -2944,21 +3133,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3024,21 +3227,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3104,23 +3321,37 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
-      end: 0x30048000
+      end: 0x30020000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM2
     range:
-      start: 0x38000000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - main
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
       end: 0x38010000
     cores:
     - main
@@ -3185,21 +3416,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3266,21 +3511,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3347,21 +3606,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3428,21 +3701,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3508,21 +3795,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3588,21 +3889,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3668,21 +3983,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3748,21 +4077,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -3796,7 +4139,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -3810,7 +4152,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -3821,7 +4163,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -3829,34 +4171,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -3888,7 +4246,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -3921,34 +4278,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -3981,7 +4354,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -3995,7 +4367,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -4006,7 +4378,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -4014,34 +4386,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4074,7 +4462,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4107,34 +4494,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4166,7 +4569,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4180,7 +4582,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -4191,7 +4593,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -4199,34 +4601,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4258,7 +4676,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4291,34 +4708,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4350,7 +4783,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4364,7 +4796,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -4375,7 +4807,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -4383,34 +4815,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4442,7 +4890,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4475,34 +4922,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4534,7 +4997,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4548,7 +5010,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -4559,7 +5021,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -4567,34 +5029,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4626,7 +5104,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4659,34 +5136,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4718,7 +5211,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4732,7 +5224,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -4743,7 +5235,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -4751,34 +5243,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4810,7 +5318,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4843,34 +5350,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4902,7 +5425,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -4916,7 +5438,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -4927,7 +5449,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -4935,34 +5457,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -4994,7 +5532,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -5027,34 +5564,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -5086,7 +5639,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -5100,7 +5652,7 @@ variants:
     name: BANK_1
     range:
       start: 0x8000000
-      end: 0x8100000
+      end: 0x8080000
     cores:
     - cm7
     - cm4
@@ -5111,7 +5663,7 @@ variants:
     name: BANK_2
     range:
       start: 0x8100000
-      end: 0x8200000
+      end: 0x8180000
     cores:
     - cm7
     - cm4
@@ -5119,34 +5671,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -5178,7 +5746,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -5211,34 +5778,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -5270,7 +5853,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -5303,34 +5885,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -5385,21 +5983,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
+    range:
+      start: 0x24000000
+      end: 0x24080000
+    cores:
+    - main
+  - !Ram
+    name: SRAM1
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM3
     range:
-      start: 0x30000000
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5455,21 +6067,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5525,21 +6151,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5595,21 +6235,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5675,21 +6329,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5755,21 +6423,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5836,21 +6518,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5917,21 +6613,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -5997,21 +6707,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -6077,21 +6801,35 @@ variants:
     cores:
     - main
   - !Ram
-    name: RAM_D1
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24080000
     cores:
     - main
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
       start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
+  - !Ram
+    name: SRAM2
+    range:
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - main
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
       end: 0x30048000
     cores:
     - main
   - !Ram
-    name: RAM_D3
+    name: SRAM4
     range:
       start: 0x38000000
       end: 0x38010000
@@ -6125,7 +6863,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6158,34 +6895,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
+    range:
+      start: 0x20000000
+      end: 0x20020000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: AXISRAM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: SRAM1
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM2
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30020000
+      end: 0x30040000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM3
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6218,7 +6971,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6251,34 +7003,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
+    range:
+      start: 0x24000000
+      end: 0x24080000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM1
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM2
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30020000
+      end: 0x30040000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM3
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6310,7 +7078,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6343,34 +7110,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6402,7 +7185,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6435,34 +7217,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6494,7 +7292,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6523,38 +7320,54 @@ variants:
     cores:
     - cm7
     - cm4
-    access:
-      write: false
-      boot: true
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: DTCM
+    range:
+      start: 0x20000000
+      end: 0x20020000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: AXISRAM
+    range:
+      start: 0x24000000
+      end: 0x24080000
+    cores:
+    - cm7
+    - cm4
   - !Ram
-    name: RAM_D2
+    name: SRAM1
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: SRAM2
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x30020000
+      end: 0x30040000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM3
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30040000
+      end: 0x30048000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM4
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6586,7 +7399,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6619,34 +7431,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6678,7 +7506,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6711,34 +7538,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6770,7 +7613,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6803,34 +7645,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x24000000
+      end: 0x24080000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM1
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM2
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30020000
+      end: 0x30040000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM3
+    range:
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -6862,7 +7720,6 @@ variants:
     type: armv7em
     core_access_options: !Arm
       ap: 3
-
   memory_map:
   - !Ram
     name: ITCM
@@ -6895,34 +7752,50 @@ variants:
       write: false
       boot: true
   - !Ram
-    name: RAM_D2
+    name: DTCM
     range:
-      start: 0x10000000
-      end: 0x10048000
+      start: 0x20000000
+      end: 0x20020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D3
+    name: AXISRAM
+    range:
+      start: 0x24000000
+      end: 0x24080000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM1
     range:
-      start: 0x18000000
-      end: 0x18010000
+      start: 0x30000000
+      end: 0x30020000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: DTCM
+    name: SRAM2
     range:
-      start: 0x20000000
-      end: 0x20020000
+      start: 0x30020000
+      end: 0x30040000
     cores:
     - cm7
     - cm4
   - !Ram
-    name: RAM_D1
+    name: SRAM3
     range:
-      start: 0x24000000
-      end: 0x24080000
+      start: 0x30040000
+      end: 0x30048000
+    cores:
+    - cm7
+    - cm4
+  - !Ram
+    name: SRAM4
+    range:
+      start: 0x38000000
+      end: 0x38010000
     cores:
     - cm7
     - cm4
@@ -7131,12 +8004,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -7342,12 +8222,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -7693,12 +8580,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -7760,12 +8654,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -7897,12 +8798,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -7963,12 +8871,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8032,12 +8947,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8243,12 +9165,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8452,12 +9381,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8590,12 +9526,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8717,12 +9660,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8835,12 +9785,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8891,12 +9848,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -8916,7 +9880,6 @@ variants:
 - name: STM32H7B0VB
   package_variants:
   - STM32H7B0VBTx
-  - STM32H7B0VBTx
   cores:
   - name: main
     type: armv7em
@@ -8948,12 +9911,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -9004,12 +9974,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -9101,6 +10078,8 @@ variants:
   package_variants:
   - STM32H7B3IIKx
   - STM32H7B3IITx
+  - STM32H7B3IIKxQQ
+  - STM32H7B3IITxQQ
   cores:
   - name: main
     type: armv7em
@@ -9142,12 +10121,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -9380,6 +10366,7 @@ variants:
 - name: STM32H7B3NI
   package_variants:
   - STM32H7B3NIHx
+  - STM32H7B3NIHxQQ
   cores:
   - name: main
     type: armv7em
@@ -9421,12 +10408,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -9558,12 +10552,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -9584,6 +10585,8 @@ variants:
   package_variants:
   - STM32H7B3VIHx
   - STM32H7B3VITx
+  - STM32H7B3VIHxQQ
+  - STM32H7B3VITxQQ
   cores:
   - name: main
     type: armv7em
@@ -9625,12 +10628,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -9792,6 +10802,7 @@ variants:
 - name: STM32H7B3ZI
   package_variants:
   - STM32H7B3ZITx
+  - STM32H7B3ZITxQQ
   cores:
   - name: main
     type: armv7em
@@ -9833,12 +10844,19 @@ variants:
     cores:
     - main
   - !Ram
-    name: SRAM
+    name: AXISRAM
     range:
       start: 0x24000000
       end: 0x24100000
     cores:
     - main
+  - !Ram
+    name: AHBSRAM
+    range:
+      start: 0x30000000
+      end: 0x30020000
+    cores:
+    - main
   flash_algorithms:
   - stm32h7a-b3_flash_2m
   - stm32h7b3i_eval_fmc-nor
@@ -10182,7 +11200,6 @@ flash_algorithms:
   description: STM32H7x_2048
   default: true
   instructions: v/NPj3BHELUDRk/0gHDtTCBg7UgAaEDwBwDrTCBg60hgYQC/6EgAaQDwBAAAKPnR50jlTGBg50hgYORI5kwgYAC/5UgAHwBoAPAEAAAo+NHfSOFMEDwgYN5I20zE+AQBACAQvQFG2EjAaEDwAQDWStBg2UgIOABoQPABAML4DAEAIHBH0UjQSUhhAL/OSABpAPAEAAAo+dHMSM9JCGAAv81IAB8AaADwBAAAKPjRAL/FSABpAPAEAAAo+dHCSMBoIPAwAMBJyGAIRsBoQPAIAMhgCEbAaEDwgADIYAC/ukgAaQDwBAAAKPnRt0jAaCDwCAC1SchgAL+3SAAfAGgA8AQAACj40bRICDgAaCDwMACtScH4DAEIRtD4DAFA8AgAwfgMAQhG0PgMAUDwgADB+AwBAL+oSAAfAGgA8AQAACj40aVICDgAaCDwCACeScH4DAEAIHBHELUBRsHzQ0Kx8QBvN9Ox8QFvNNKXSEBpl0sYQ5VLWGEAv5NIAGkA8AQAACj50ZBIwGhH9jBzmEOOS9hgGEbAaAQjQ+oCIxhDikvYYBhGwGhA8IAA2GAAv4ZIAGkA8AQAACj50YNIwGgg8AQAgUvYYBhGAGkA8AEA6LMBIBC9gEgAaHxLGEN6S8P4FAEAv3xIAB8AaADwBAAAKPjReUgIOABoR/Ywc5hDckvD+AwBdEgIOABoovEIAwQkROoDIxhDbEvD+AwBGEbQ+AwBQPCAAMP4DAEAv2pIAB8AaADwBAAAKPjRZ0gIOABoIPAEAGBLw/gMAQDgB+BiSAAfAGgA8AEACLEBILnnACC35/C1A0YMRhZGGUY1RgAis/EAbw3Ts/EBbwrSAL9SSABpAPAEAAAo+dFQSE5PeGEK4AC/UEgAHwBoAPAEAAAo+NFKSExPOGCH4LPxAG8M07PxAW8J0kRIwGhH9jB3uENBT/hgAiD4YAzgQ0gIOABoR/Ywd7hDPE/H+AwBAiA+Twg/OGAgLAzTACIG4C9oaGgPYEhgCDUIMVIcBCr22yA8E+AAIgTgFfgBCwH4AQtSHKJC+NMAIgPg/yAB+AELUhzE8SAAkEL32AAk//dp/rPxAG8K07PxAW8H0gC/IkgAaQDwBAAAKPnRB+AAvyJIAB8AaADwBAAAKPjRG0gAaQAgsLGz8QBvCdOz8QFvBtIWSMBoIPACABRP+GAH4BZICDgAaCDwAgAQT8f4DAEBIPC9s/EAbwnTs/EBbwbSCkjAaCDwAgAIT/hgB+ALSAg4AGgg8AIABE/H+AwBACx/9HWvACDk55RFAlgAIABSAADvDyMBZ0Wrie/NFCEAUgAAAAA=
-  # load_address manually edited to not use DTCM
   load_address: 0x24000020
   pc_init: 0x7
   pc_uninit: 0x65
diff --git a/probe-rs/targets/STM32U0_Series.yaml b/probe-rs/targets/STM32U0_Series.yaml
index 1a2c2537..636865b8 100644
--- a/probe-rs/targets/STM32U0_Series.yaml
+++ b/probe-rs/targets/STM32U0_Series.yaml
@@ -358,8 +358,6 @@ variants:
   package_variants:
   - STM32U073C8Tx
   - STM32U073C8Ux
-  - STM32U073C8Ux
-  - STM32U073C8Tx
   cores:
   - name: main
     type: armv6m
@@ -389,7 +387,6 @@ variants:
   package_variants:
   - STM32U073CBTx
   - STM32U073CBUx
-  - STM32U073CBTx
   cores:
   - name: main
     type: armv6m
@@ -543,7 +540,6 @@ variants:
 - name: STM32U073K8
   package_variants:
   - STM32U073K8Ux
-  - STM32U073K8Ux
   cores:
   - name: main
     type: armv6m
@@ -572,7 +568,6 @@ variants:
 - name: STM32U073KB
   package_variants:
   - STM32U073KBUx
-  - STM32U073KBUx
   cores:
   - name: main
     type: armv6m
@@ -630,8 +625,6 @@ variants:
   package_variants:
   - STM32U073M8Tx
   - STM32U073M8Ix
-  - STM32U073M8Ix
-  - STM32U073M8Tx
   cores:
   - name: main
     type: armv6m
@@ -661,8 +654,6 @@ variants:
   package_variants:
   - STM32U073MBTx
   - STM32U073MBIx
-  - STM32U073MBIx
-  - STM32U073MBTx
   cores:
   - name: main
     type: armv6m
@@ -721,8 +712,6 @@ variants:
   package_variants:
   - STM32U073R8Tx
   - STM32U073R8Ix
-  - STM32U073R8Ix
-  - STM32U073R8Tx
   cores:
   - name: main
     type: armv6m
@@ -752,8 +741,6 @@ variants:
   package_variants:
   - STM32U073RBTx
   - STM32U073RBIx
-  - STM32U073RBIx
-  - STM32U073RBTx
   cores:
   - name: main
     type: armv6m
diff --git a/probe-rs/targets/STM32WBA_Series.yaml b/probe-rs/targets/STM32WBA_Series.yaml
index 04132a70..7422b757 100644
--- a/probe-rs/targets/STM32WBA_Series.yaml
+++ b/probe-rs/targets/STM32WBA_Series.yaml
@@ -15,7 +15,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -36,7 +35,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA50KG
   package_variants:
   - STM32WBA50KGUx
@@ -45,7 +43,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -66,7 +63,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA52CE
   package_variants:
   - STM32WBA52CEUx
@@ -75,7 +71,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -96,7 +91,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA52CG
   package_variants:
   - STM32WBA52CGUx
@@ -105,7 +99,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -126,7 +119,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA52KE
   package_variants:
   - STM32WBA52KEUx
@@ -135,7 +127,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -156,7 +147,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA52KG
   package_variants:
   - STM32WBA52KGUx
@@ -165,7 +155,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -186,7 +175,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA54CE
   package_variants:
   - STM32WBA54CEUx
@@ -195,7 +183,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -216,7 +203,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA54CG
   package_variants:
   - STM32WBA54CGUx
@@ -225,7 +211,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -246,7 +231,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA54KE
   package_variants:
   - STM32WBA54KEUx
@@ -255,7 +239,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -276,7 +259,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA54KG
   package_variants:
   - STM32WBA54KGUx
@@ -285,7 +267,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -306,7 +287,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA55CE
   package_variants:
   - STM32WBA55CEUx
@@ -315,7 +295,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -336,7 +315,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA55CG
   package_variants:
   - STM32WBA55CGUx
@@ -345,7 +323,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -366,7 +343,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA55HE
   package_variants:
   - STM32WBA55HEFx
@@ -375,7 +351,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -396,7 +371,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA55HG
   package_variants:
   - STM32WBA55HGFx
@@ -405,7 +379,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -426,7 +399,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA55UE
   package_variants:
   - STM32WBA55UEIx
@@ -435,7 +407,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -456,7 +427,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 - name: STM32WBA55UG
   package_variants:
   - STM32WBA55UGIx
@@ -465,7 +435,6 @@ variants:
     type: armv8m
     core_access_options: !Arm
       ap: 1
-
   memory_map:
   - !Nvm
     name: BANK_1
@@ -486,7 +455,6 @@ variants:
     - main
   flash_algorithms:
   - stm32wbax_1m_0800
-  #- stm32wbax_1m_0c00
 flash_algorithms:
 - name: stm32wbax_1m_0800
   description: STM32WBAxx 1M NSecure Flash
@@ -510,25 +478,3 @@ flash_algorithms:
     sectors:
     - size: 0x2000
       address: 0x0
-- name: stm32wbax_1m_0c00
-  description: STM32WBAxx 1M Secure Flash
-  default: true
-  instructions: v/NPj3BH/kkJbMgPcEdwtQRGDUYWRnK2//f1/yCx+EgAbMCyVSgR0fVIgGoA8ABAILH0SPJJiGDzSIhgAL/wSABqAPSAMAAo+dEY4E/w/zDrSYAxCGDqScH4hADoSYgxCGAJHQhg50jlSchg5kjIYAC/40hAagD0gDAAKPnRACBwvRC1BEb/977/ILHcSABswLJVKAbR2kiAakDwAEDYSYhiBeDWSMBqQPAAQNRJyGL/96b/ACAQvRC1//ek/yCxz0gAbMCyVSgj0QC/zEhAagD0gDAAKPnRICDJSQhiCEaAakDwBACIYghGgGpA9IAwiGL/94X/AL/BSABqAPSAMAAo+dG+SIBqIPAEALxJiGIf4AC/ukhAagD0gDAAKPnRICC3SUhiBCDIYghGwGpA9IAwyGL/92T/AL+xSEBqAPSAMAAo+dGuSIBqIPAEAKxJiGIAIBC9cLUERrTxQG8B06TxgGT/90//ILGlSABswLJVKC3RICCiSQhiCEaAakDwAgCIYsTzRzUIRoBqIPR+cIhiCEaAakDqxQCIYghGgGpA9IAwiGIAv5VIAGoA9IAwACj50ZJIAGoA8AIACLEBIHC9j0iAaiDwAgCNSYhiLOAgIItJSGIIRsBqQPACAMhixPNHNQhGwGog9H5wyGIIRsBqQOrFAMhiCEbAakD0gDDIYgC/fkhAagD0gDAAKPnRe0hAagDwAgAIsQEg0Od4SMBqIPACAHZJyGIAIMjnLen8RwVGD0aQRgXwBwZP8AAKB/EPACDwDwf/993+ILFsSABswLJVKH3RQvL7AGhJCGIBIIhiheAIL0zTQPL/EGRJCGIALjLQpesGCgAkBuCa+AAADfgEAArxAQpkHLRC9tMAJAfgmPgAAKEZDfgBAAjxAQhkHMbxCACgQvPYpesGCgC/U0gAagD0gDAAKPnRAJjK+AAAAZjK+AQAAL8Av8bxCAA/GsbxCAAFRAAmAL9ISABqAPSAMAAo+dHY+AAAKGDY+AQAaGAI8QgICD8INQC/AL8h4AAkBuCY+AAADfgEAAjxAQhkHLxC9tMAJATg/yDhGQ34AQBkHMfxCACgQvbYAL8zSABqAPSAMAAo+dEAmChgAZhoYAAnAL8tSABqAPSAMADgFOAAKPfRKUgAakLy+wEIQCixCEYlSQhiASC96PyHAC9/9HevACAhSYhiluBC8vsAHklIYgEgyGKJ4AgvU9NA8v8QGklIYr6zpesGCgAkBuCa+AAADfgEAArxAQpkHLRC9tMAJAfgmPgAAKEZDfgBAAjxAQhkHMbxCACgQvPYpesGCgC/CUhAagD0gDAAKPnRAJjK+AAAAZjK+AQAAL8Av8bxCAA/GsbxCAAG4AAgAkAjAWdFq4nvzQHgBUQAJgC/J0hAagD0gDAAKPnR2PgAAChg2PgEAGhgCPEICAg/CDUAvwC/IeAAJAbgmPgAAA34BAAI8QEIZBy8QvbTACQE4P8g4RkN+AEAZBzH8QgAoEL22AC/EkhAagD0gDAAKPnRAJgoYAGYaGAAJwC/DEhAagD0gDAAKPnRCUhAakLy+wEIQCCxCEYGSUhiASBl5wAvf/RzrwAgAknIYgAgXecAAAAgAkAAAAAA
-  load_address: 0x30000020
-  pc_init: 0xf
-  pc_uninit: 0x83
-  pc_program_page: 0x22f
-  pc_erase_sector: 0x157
-  pc_erase_all: 0xb9
-  data_section_offset: 0x4b8
-  flash_properties:
-    address_range:
-      start: 0xc000000
-      end: 0xc100000
-    page_size: 0x400
-    erased_byte_value: 0xff
-    program_page_timeout: 400
-    erase_sector_timeout: 400
-    sectors:
-    - size: 0x2000
-      address: 0x0
diff --git a/probe-rs/targets/STM32WL_Series.yaml b/probe-rs/targets/STM32WL_Series.yaml
index fe2b29f1..ceac0891 100644
--- a/probe-rs/targets/STM32WL_Series.yaml
+++ b/probe-rs/targets/STM32WL_Series.yaml
@@ -255,8 +255,6 @@ variants:
       end: 0x20005000
     cores:
     - main
-  flash_algorithms:
-  #- stm32wlexx_128
 - name: STM32WLE4CB
   package_variants:
   - STM32WLE4CBUx
@@ -360,8 +358,6 @@ variants:
       end: 0x20005000
     cores:
     - main
-  flash_algorithms:
-  #- stm32wlexx_128
 - name: STM32WLE4JB
   package_variants:
   - STM32WLE4JBIx
@@ -465,8 +461,6 @@ variants:
       end: 0x20005000
     cores:
     - main
-  flash_algorithms:
-  #- stm32wlexx_128
 - name: STM32WLE5CB
   package_variants:
   - STM32WLE5CBUx
@@ -571,8 +565,6 @@ variants:
       end: 0x20005000
     cores:
     - main
-  flash_algorithms:
-  #- stm32wlexx_128
 - name: STM32WLE5JB
   package_variants:
   - STM32WLE5JBIx


Test patch:
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_full_unwind.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_full_unwind.snap
index d752519a..7a59f952 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_full_unwind.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_full_unwind.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: test_deep_stack
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_svcall.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_svcall.snap
index f2c837f8..10512ca3 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_svcall.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_svcall.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: software_breakpoint
@@ -766,7 +765,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536886928
+        U32: 536886960
     - core_register:
         id: 14
         roles:
@@ -786,7 +785,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 268436742
+        U32: 268436741
     - core_register:
         id: 17
         roles:
@@ -825,7 +824,7 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 268436742
+    U32: 268436741
   frame_base: ~
   is_inlined: false
   local_variables: ~
@@ -833,10 +832,10 @@ expression: stack_frames
 - function_name: trigger_supervisor_call
   source_location:
     path: /Users/jacknoppe/dev/debug/probe-rs-debugger-test/src/bin/RP2040.rs
-    line: 80
+    line: 78
     column:
-      Column: 2
-    address: 268436742
+      Column: 9
+    address: 268436740
   registers:
     - core_register:
         id: 0
@@ -970,7 +969,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536886928
+        U32: 536886960
     - core_register:
         id: 14
         roles:
@@ -990,7 +989,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 268436742
+        U32: 268436741
     - core_register:
         id: 17
         roles:
@@ -1029,7 +1028,7 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 268436742
+    U32: 268436741
   frame_base: 536886960
   is_inlined: false
   local_variables:
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_systick.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_systick.snap
index be473e77..6e2fd474 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_systick.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__RP2040_systick.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: software_breakpoint
@@ -766,7 +765,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536886888
+        U32: 536886920
     - core_register:
         id: 14
         roles:
@@ -786,7 +785,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 268437366
+        U32: 268437365
     - core_register:
         id: 17
         roles:
@@ -825,7 +824,7 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 268437366
+    U32: 268437365
   frame_base: ~
   is_inlined: false
   local_variables: ~
@@ -833,10 +832,10 @@ expression: stack_frames
 - function_name: __delay
   source_location:
     path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
-    line: 62
+    line: 61
     column:
-      Column: 5
-    address: 268437366
+      Column: 20
+    address: 268437344
   registers:
     - core_register:
         id: 0
@@ -970,7 +969,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536886888
+        U32: 536886920
     - core_register:
         id: 14
         roles:
@@ -990,7 +989,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 268437366
+        U32: 268437365
     - core_register:
         id: 17
         roles:
@@ -1029,35 +1028,25 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 268437366
+    U32: 268437365
   frame_base: 536886936
   is_inlined: true
   local_variables:
     Child Variables:
       name: LocalScopeRoot
       type_name: Unknown
-      value: "<unknown> {\n\tcyc: u32 = 858993459,\n\treal_cyc: u32 = 48000000}"
+      value: "<unknown> {\n\tcyc: u32 = 1000000}"
       children:
         - name:
             Named: cyc
           type_name:
             Base: u32
-          value: "858993459"
+          value: "1000000"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
             line: 56
             column: ~
             address: ~
-        - name:
-            Named: real_cyc
-          type_name:
-            Base: u32
-          value: "48000000"
-          source_location:
-            path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
-            line: 61
-            column: ~
-            address: ~
   canonical_frame_address: 536886944
 - function_name: delay
   source_location:
@@ -1199,7 +1188,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536886888
+        U32: 536886920
     - core_register:
         id: 14
         roles:
@@ -1219,7 +1208,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 268437366
+        U32: 268437365
     - core_register:
         id: 17
         roles:
@@ -1265,13 +1254,13 @@ expression: stack_frames
     Child Variables:
       name: LocalScopeRoot
       type_name: Unknown
-      value: "<unknown> {\n\tcycles: u32 = 3758153744}"
+      value: "<unknown> {\n\tcycles: u32 = 1000000}"
       children:
         - name:
             Named: cycles
           type_name:
             Base: u32
-          value: "3758153744"
+          value: "1000000"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/asm.rs
             line: 28
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__atsamd51p19a.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__atsamd51p19a.snap
index f449cc41..ba220d34 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__atsamd51p19a.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__atsamd51p19a.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: print_const_pointers
@@ -950,3 +949,186 @@ expression: stack_frames
                       - Base: long unsigned int
               value: "484133903"
   canonical_frame_address: 536875128
+- function_name: Reset
+  source_location: ~
+  registers:
+    - core_register:
+        id: 0
+        roles:
+          - Core: R0
+          - Argument: a1
+          - Return: r1
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 0
+      value: ~
+    - core_register:
+        id: 1
+        roles:
+          - Core: R1
+          - Argument: a2
+          - Return: r2
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 1
+      value: ~
+    - core_register:
+        id: 2
+        roles:
+          - Core: R2
+          - Argument: a3
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 2
+      value: ~
+    - core_register:
+        id: 3
+        roles:
+          - Core: R3
+          - Argument: a4
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 3
+      value: ~
+    - core_register:
+        id: 4
+        roles:
+          - Core: R4
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 4
+      value: ~
+    - core_register:
+        id: 5
+        roles:
+          - Core: R5
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 5
+      value: ~
+    - core_register:
+        id: 6
+        roles:
+          - Core: R6
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 6
+      value: ~
+    - core_register:
+        id: 7
+        roles:
+          - Core: R7
+          - FramePointer
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 7
+      value: ~
+    - core_register:
+        id: 8
+        roles:
+          - Core: R8
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 8
+      value: ~
+    - core_register:
+        id: 9
+        roles:
+          - Core: R9
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 9
+      value: ~
+    - core_register:
+        id: 10
+        roles:
+          - Core: R10
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 10
+      value: ~
+    - core_register:
+        id: 11
+        roles:
+          - Core: R11
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 11
+      value: ~
+    - core_register:
+        id: 12
+        roles:
+          - Core: R12
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 12
+      value: ~
+    - core_register:
+        id: 13
+        roles:
+          - Core: R13
+          - StackPointer
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 13
+      value: ~
+    - core_register:
+        id: 14
+        roles:
+          - Core: R14
+          - ReturnAddress
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 14
+      value: ~
+    - core_register:
+        id: 15
+        roles:
+          - Core: R15
+          - ProgramCounter
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 15
+      value: ~
+    - core_register:
+        id: 17
+        roles:
+          - Core: MSP
+          - MainStackPointer
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 16
+      value: ~
+    - core_register:
+        id: 18
+        roles:
+          - Core: PSP
+          - ProcessStackPointer
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 17
+      value: ~
+    - core_register:
+        id: 16
+        roles:
+          - Core: XPSR
+          - ProcessorStatus
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 18
+      value: ~
+    - core_register:
+        id: 20
+        roles:
+          - Core: EXTRA
+          - Other: EXTRA
+        data_type:
+          UnsignedInteger: 32
+      dwarf_id: 19
+      value: ~
+  pc:
+    U32: 0
+  frame_base: ~
+  is_inlined: false
+  local_variables: ~
+  canonical_frame_address: ~
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_full_unwind.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_full_unwind.snap
index 7c8819b9..a2248277 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_full_unwind.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_full_unwind.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: test_deep_stack
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_busfault.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_busfault.snap
index 9b5f40cb..1de9d12e 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_busfault.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_busfault.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: software_breakpoint
@@ -525,8 +524,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 9
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 10
         roles:
@@ -592,8 +590,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 16
-      value:
-        U32: 536887064
+      value: ~
     - core_register:
         id: 18
         roles:
@@ -602,8 +599,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 17
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 16
         roles:
@@ -622,14 +618,13 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 19
-      value:
-        U32: 0
+      value: ~
   pc:
     U32: 1690
-  frame_base: 536887064
+  frame_base: ~
   is_inlined: false
   local_variables: ~
-  canonical_frame_address: 536887072
+  canonical_frame_address: ~
 - function_name: read_volatile<u32>
   source_location:
     path: /rustc/7f2fc33da6633f5a764ddc263c769b6b2873d167/library/core/src/ptr/mod.rs
@@ -733,8 +728,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 9
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 10
         roles:
@@ -800,8 +794,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 16
-      value:
-        U32: 536887064
+      value: ~
     - core_register:
         id: 18
         roles:
@@ -810,8 +803,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 17
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 16
         roles:
@@ -830,8 +822,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 19
-      value:
-        U32: 0
+      value: ~
   pc:
     U32: 1690
   frame_base: 536887120
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_usagefault.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_usagefault.snap
index db374162..e34e1354 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_usagefault.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_from_usagefault.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: software_breakpoint
@@ -508,7 +507,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 7
       value:
-        U32: 536887096
+        U32: 536887128
     - core_register:
         id: 8
         roles:
@@ -525,8 +524,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 9
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 10
         roles:
@@ -592,8 +590,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 16
-      value:
-        U32: 536887088
+      value: ~
     - core_register:
         id: 18
         roles:
@@ -602,8 +599,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 17
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 16
         roles:
@@ -622,14 +618,13 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 19
-      value:
-        U32: 0
+      value: ~
   pc:
     U32: 1586
-  frame_base: 536887088
+  frame_base: ~
   is_inlined: false
   local_variables: ~
-  canonical_frame_address: 536887096
+  canonical_frame_address: ~
 - function_name: __udf
   source_location:
     path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
@@ -716,7 +711,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 7
       value:
-        U32: 536887096
+        U32: 536887128
     - core_register:
         id: 8
         roles:
@@ -733,8 +728,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 9
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 10
         roles:
@@ -800,8 +794,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 16
-      value:
-        U32: 536887088
+      value: ~
     - core_register:
         id: 18
         roles:
@@ -810,8 +803,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 17
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 16
         roles:
@@ -830,11 +822,10 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 19
-      value:
-        U32: 0
+      value: ~
   pc:
     U32: 1586
-  frame_base: 536887096
+  frame_base: 536887128
   is_inlined: true
   local_variables:
     Child Variables:
@@ -928,7 +919,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 7
       value:
-        U32: 536887096
+        U32: 536887128
     - core_register:
         id: 8
         roles:
@@ -945,8 +936,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 9
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 10
         roles:
@@ -1012,8 +1002,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 16
-      value:
-        U32: 536887088
+      value: ~
     - core_register:
         id: 18
         roles:
@@ -1022,8 +1011,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 17
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 16
         roles:
@@ -1042,11 +1030,10 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 19
-      value:
-        U32: 0
+      value: ~
   pc:
     U64: 1586
-  frame_base: 536887096
+  frame_base: 536887128
   is_inlined: false
   local_variables:
     Child Variables:
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_in_systick.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_in_systick.snap
index c641dd6b..fff04017 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_in_systick.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_hardfault_in_systick.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: software_breakpoint
@@ -525,8 +524,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 9
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 10
         roles:
@@ -592,8 +590,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 16
-      value:
-        U32: 536886968
+      value: ~
     - core_register:
         id: 18
         roles:
@@ -602,8 +599,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 17
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 16
         roles:
@@ -622,14 +618,13 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 19
-      value:
-        U32: 0
+      value: ~
   pc:
     U32: 2166
-  frame_base: 536886968
+  frame_base: ~
   is_inlined: false
   local_variables: ~
-  canonical_frame_address: 536886976
+  canonical_frame_address: ~
 - function_name: read_volatile<u32>
   source_location:
     path: /rustc/7f2fc33da6633f5a764ddc263c769b6b2873d167/library/core/src/ptr/mod.rs
@@ -733,8 +728,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 9
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 10
         roles:
@@ -800,8 +794,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 16
-      value:
-        U32: 536886968
+      value: ~
     - core_register:
         id: 18
         roles:
@@ -810,8 +803,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 17
-      value:
-        U32: 0
+      value: ~
     - core_register:
         id: 16
         roles:
@@ -830,8 +822,7 @@ expression: stack_frames
         data_type:
           UnsignedInteger: 32
       dwarf_id: 19
-      value:
-        U32: 0
+      value: ~
   pc:
     U32: 2166
   frame_base: 536887024
@@ -1811,7 +1802,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887056
+        U32: 536887088
     - core_register:
         id: 14
         roles:
@@ -1831,7 +1822,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 1240
+        U32: 1239
     - core_register:
         id: 17
         roles:
@@ -1870,7 +1861,7 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 1240
+    U32: 1239
   frame_base: ~
   is_inlined: false
   local_variables: ~
@@ -2015,7 +2006,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887056
+        U32: 536887088
     - core_register:
         id: 14
         roles:
@@ -2035,7 +2026,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 1240
+        U32: 1239
     - core_register:
         id: 17
         roles:
@@ -2074,20 +2065,20 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 1240
+    U32: 1239
   frame_base: 536887104
   is_inlined: true
   local_variables:
     Child Variables:
       name: LocalScopeRoot
       type_name: Unknown
-      value: "<unknown> {\n\tcyc: u32 = 1,\n\treal_cyc: u32 = 85}"
+      value: "<unknown> {\n\tcyc: u32 = 1000000,\n\treal_cyc: u32 = 500001}"
       children:
         - name:
             Named: cyc
           type_name:
             Base: u32
-          value: "1"
+          value: "1000000"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
             line: 56
@@ -2097,7 +2088,7 @@ expression: stack_frames
             Named: real_cyc
           type_name:
             Base: u32
-          value: "85"
+          value: "500001"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
             line: 61
@@ -2244,7 +2235,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887056
+        U32: 536887088
     - core_register:
         id: 14
         roles:
@@ -2264,7 +2255,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 1240
+        U32: 1239
     - core_register:
         id: 17
         roles:
@@ -2310,13 +2301,13 @@ expression: stack_frames
     Child Variables:
       name: LocalScopeRoot
       type_name: Unknown
-      value: "<unknown> {\n\tcycles: u32 = 500001}"
+      value: "<unknown> {\n\tcycles: u32 = 1000000}"
       children:
         - name:
             Named: cycles
           type_name:
             Base: u32
-          value: "500001"
+          value: "1000000"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/asm.rs
             line: 28
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_svcall.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_svcall.snap
index 4d4cb994..20a15eec 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_svcall.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_svcall.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: software_breakpoint
@@ -766,7 +765,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887096
+        U32: 536887128
     - core_register:
         id: 14
         roles:
@@ -786,7 +785,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 938
+        U32: 937
     - core_register:
         id: 17
         roles:
@@ -825,7 +824,7 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 938
+    U32: 937
   frame_base: ~
   is_inlined: false
   local_variables: ~
@@ -833,10 +832,10 @@ expression: stack_frames
 - function_name: trigger_supervisor_call
   source_location:
     path: /Users/jacknoppe/dev/debug/probe-rs-debugger-test/src/bin/nRF52833_xxAA.rs
-    line: 63
+    line: 61
     column:
-      Column: 2
-    address: 938
+      Column: 9
+    address: 936
   registers:
     - core_register:
         id: 0
@@ -970,7 +969,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887096
+        U32: 536887128
     - core_register:
         id: 14
         roles:
@@ -990,7 +989,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 938
+        U32: 937
     - core_register:
         id: 17
         roles:
@@ -1029,7 +1028,7 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 938
+    U32: 937
   frame_base: 536887128
   is_inlined: false
   local_variables:
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_systick.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_systick.snap
index 83db2292..74bc7261 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_systick.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__nRF52833_xxAA_systick.snap
@@ -1,6 +1,5 @@
 ---
 source: probe-rs-debug/src/debug_info.rs
-assertion_line: 1999
 expression: stack_frames
 ---
 - function_name: software_breakpoint
@@ -766,7 +765,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887056
+        U32: 536887088
     - core_register:
         id: 14
         roles:
@@ -786,7 +785,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 1398
+        U32: 1397
     - core_register:
         id: 17
         roles:
@@ -825,7 +824,7 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 1398
+    U32: 1397
   frame_base: ~
   is_inlined: false
   local_variables: ~
@@ -970,7 +969,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887056
+        U32: 536887088
     - core_register:
         id: 14
         roles:
@@ -990,7 +989,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 1398
+        U32: 1397
     - core_register:
         id: 17
         roles:
@@ -1029,20 +1028,20 @@ expression: stack_frames
       dwarf_id: 19
       value: ~
   pc:
-    U32: 1398
+    U32: 1397
   frame_base: 536887104
   is_inlined: true
   local_variables:
     Child Variables:
       name: LocalScopeRoot
       type_name: Unknown
-      value: "<unknown> {\n\tcyc: u32 = 1,\n\treal_cyc: u32 = 85}"
+      value: "<unknown> {\n\tcyc: u32 = 1000000,\n\treal_cyc: u32 = 500001}"
       children:
         - name:
             Named: cyc
           type_name:
             Base: u32
-          value: "1"
+          value: "1000000"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
             line: 56
@@ -1052,7 +1051,7 @@ expression: stack_frames
             Named: real_cyc
           type_name:
             Base: u32
-          value: "85"
+          value: "500001"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/../asm/inline.rs
             line: 61
@@ -1199,7 +1198,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 13
       value:
-        U32: 536887056
+        U32: 536887088
     - core_register:
         id: 14
         roles:
@@ -1219,7 +1218,7 @@ expression: stack_frames
           UnsignedInteger: 32
       dwarf_id: 15
       value:
-        U32: 1398
+        U32: 1397
     - core_register:
         id: 17
         roles:
@@ -1265,13 +1264,13 @@ expression: stack_frames
     Child Variables:
       name: LocalScopeRoot
       type_name: Unknown
-      value: "<unknown> {\n\tcycles: u32 = 500001}"
+      value: "<unknown> {\n\tcycles: u32 = 1000000}"
       children:
         - name:
             Named: cycles
           type_name:
             Base: u32
-          value: "500001"
+          value: "1000000"
           source_location:
             path: /Users/jacknoppe/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cortex-m-0.7.7/src/asm.rs
             line: 28
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__print_stacktrace.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__print_stacktrace.snap
index 71c1e2de..9209c79e 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__print_stacktrace.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__print_stacktrace.snap
@@ -1,8 +1,6 @@
 ---
-source: probe-rs/src/debug/debug_info.rs
-assertion_line: 1926
+source: probe-rs-debug/src/debug_info.rs
 expression: printed_backtrace
-snapshot_kind: text
 ---
 Frame:
  function:        read<nrf51_pac::timer0::events_compare::EVENTS_COMPARE_SPEC>
@@ -68,7 +66,7 @@ Frame:
   column: Some(Column(1))
  frame_base:      Some(20003ff8)
 Frame:
- function:        <unknown function @ 0x000000ce> : ERROR: UNWIND: Tried to unwind `RegisterRule` at CFA = None.
+ function:        <unknown function @ 0x000000ce> : ERROR: UNWIND: Failed to read value for register R7/FP from address 0x0000000000000000 (4 bytes): The coredump does not include the memory for address 0x0 of size 0x4
  source_location:
 None
  frame_base:      None
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_handler.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_handler.snap
index 76d3d166..c84549ed 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_handler.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_handler.snap
@@ -1,8 +1,6 @@
 ---
-source: probe-rs/src/debug/debug_info.rs
-assertion_line: 1700
+source: probe-rs-debug/src/debug_info.rs
 expression: printed_backtrace
-snapshot_kind: text
 ---
 Frame:
  function:        __cortex_m_rt_SVCall
@@ -27,7 +25,7 @@ Frame:
  function:        __cortex_m_rt_main
  source_location:
   path: /home/dominik/code/probe-rs/probe-rs-repro/nrf/exceptions/src/main.rs
-  line: Some(19)
+  line: Some(17)
   column: Some(Column(5))
  frame_base:      Some(2001fff0)
 Frame:
diff --git a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_trampoline.snap b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_trampoline.snap
index c9881c4e..a7db139a 100644
--- a/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_trampoline.snap
+++ b/probe-rs-debug/src/snapshots/probe_rs_debug__debug_info__test__unwinding_in_exception_trampoline.snap
@@ -1,8 +1,6 @@
 ---
-source: probe-rs/src/debug/debug_info.rs
-assertion_line: 1804
+source: probe-rs-debug/src/debug_info.rs
 expression: printed_backtrace
-snapshot_kind: text
 ---
 Frame:
  function:        __cortex_m_rt_SVCall_trampoline
@@ -20,7 +18,7 @@ Frame:
  function:        __cortex_m_rt_main
  source_location:
   path: /home/dominik/code/probe-rs/probe-rs-repro/nrf/exceptions/src/main.rs
-  line: Some(19)
+  line: Some(17)
   column: Some(Column(5))
  frame_base:      Some(2001fff0)
 Frame: