Repository: amaranth-lang/amaranth
Pull request #1561 (2025-02-02 20:42:48)

amaranth._nir: implement new `Match` cell.
Both `Matches` and `PriorityMatch` cells are obsoleted by the new cell.

This isn't really a functional change, as the validity rules on the `PriorityMatch` inputs imposed by RTLIL backend forced the netlist to conform to the same rules as the new composite cell.


Patch:
diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py
index f2e3195..b25e140 100644
--- a/amaranth/back/rtlil.py
+++ b/amaranth/back/rtlil.py
@@ -585,7 +585,7 @@ class ModuleEmitter:
                     wire = self.emit_driven_wire(_nir.Value(nets))
                     self.instance_wires[cell_idx, name] = wire
                 continue # Instances use one wire per output, not per cell.
-            elif isinstance(cell, (_nir.PriorityMatch, _nir.Matches)):
+            elif isinstance(cell, _nir.Match):
                 continue # Inlined into assignment lists.
             elif isinstance(cell, (_nir.SyncPrint, _nir.AsyncPrint, _nir.SyncProperty,
                                    _nir.AsyncProperty, _nir.Memory, _nir.SyncWritePort)):
@@ -737,41 +737,25 @@ class ModuleEmitter:
                     search_cond = assign.cond
                     while True:
                         if search_cond == cond:
-                            # We have found the PriorityMatch cell that we should enter.
+                            # We have found the Match cell that we should enter.
                             break
                         if search_cond == _nir.Net.from_const(1):
                             # If this isn't nested condition, go back to parent invocation.
                             return
-                        # Grab the PriorityMatch cell that is on the next level of nesting.
-                        priority_cell_idx = search_cond.cell
-                        priority_cell = self.netlist.cells[priority_cell_idx]
-                        assert isinstance(priority_cell, _nir.PriorityMatch)
-                        search_cond = priority_cell.en
-                    # We assume that:
-                    # 1. PriorityMatch inputs can only be Match cell outputs, or constant 1.
-                    # 2. All Match cells driving a given PriorityMatch cell test the same value.
-                    # Grab the tested value from a random Match cell.
-                    test = _nir.Value()
-                    for net in priority_cell.inputs:
-                        if net != _nir.Net.from_const(1):
-                            matches_cell = self.netlist.cells[net.cell]
-                            assert isinstance(matches_cell, _nir.Matches)
-                            test = matches_cell.value
-                            break
+                        # Grab the Match cell that is on the next level of nesting.
+                        match_cell_idx = search_cond.cell
+                        match_cell = self.netlist.cells[match_cell_idx]
+                        assert isinstance(match_cell, _nir.Match)
+                        search_cond = match_cell.en
                     # Now emit cases for all PriorityMatch inputs, in sequence. Consume as many
                     # assignments as possible along the way.
-                    switch = case.switch(self.sigspec(test))
-                    for bit, net in enumerate(priority_cell.inputs):
-                        subcond = _nir.Net.from_cell(priority_cell_idx, bit)
-                        if net == _nir.Net.from_const(1):
+                    switch = case.switch(self.sigspec(match_cell.value))
+                    for bit, pattern_list in enumerate(match_cell.patterns):
+                        subcond = _nir.Net.from_cell(match_cell_idx, bit)
+                        if pattern_list == ("-" * len(match_cell.value),):
                             emit_assignments(switch.default(), subcond)
                         else:
-                            # Validate the above assumptions.
-                            matches_cell = self.netlist.cells[net.cell]
-                            assert isinstance(matches_cell, _nir.Matches)
-                            assert test == matches_cell.value
-                            patterns = matches_cell.patterns
-                            emit_assignments(switch.case(patterns), subcond)
+                            emit_assignments(switch.case(pattern_list), subcond)
 
         lhs = _nir.Value(_nir.Net.from_cell(cell_idx, bit) for bit in range(len(cell.default)))
         proc = self.builder.process(src_loc=cell.src_loc)
@@ -1235,10 +1219,8 @@ class ModuleEmitter:
             cell = self.netlist.cells[cell_idx]
             if isinstance(cell, _nir.Top):
                 pass
-            elif isinstance(cell, _nir.Matches):
-                pass # Matches is only referenced from PriorityMatch cells and inlined there
-            elif isinstance(cell, _nir.PriorityMatch):
-                pass # PriorityMatch is only referenced from AssignmentList cells and inlined there
+            elif isinstance(cell, _nir.Match):
+                pass # Match is only referenced from AssignmentList cells and inlined there
             elif isinstance(cell, _nir.AssignmentList):
                 self.emit_assignment_list(cell_idx, cell)
             elif isinstance(cell, _nir.Operator):
diff --git a/amaranth/hdl/_ir.py b/amaranth/hdl/_ir.py
index 5932774..0bdbb97 100644
--- a/amaranth/hdl/_ir.py
+++ b/amaranth/hdl/_ir.py
@@ -707,8 +707,7 @@ class NetlistEmitter:
         self.drivers = _ast.SignalDict()
         self.io_ports: dict[_ast.IOPort, int] = {}
         self.rhs_cache: dict[int, tuple[_nir.Value, bool, _ast.Value]] = {}
-        self.matches_cache = {}
-        self.priority_match_cache = {}
+        self.match_cache = {}
         self.fragment_module_idx: dict[Fragment, int] = {}
 
         # Collected for driver conflict diagnostics only.
@@ -787,24 +786,14 @@ class NetlistEmitter:
         op = _nir.Operator(module_idx, operator=operator, inputs=inputs, src_loc=src_loc)
         return self.netlist.add_value_cell(op.width, op)
 
-    def emit_matches(self, module_idx: int, value: _nir.Value, patterns, *, src_loc):
-        key = module_idx, value, patterns, src_loc
+    def emit_match(self, module_idx: int, en: _nir.Net, value: _nir.Value, patterns, *, src_loc):
+        key = module_idx, en, value, patterns, src_loc
         try:
-            return self.matches_cache[key]
+            return self.match_cache[key]
         except KeyError:
-            cell = _nir.Matches(module_idx, value=value, patterns=patterns, src_loc=src_loc)
-            net, = self.netlist.add_value_cell(1, cell)
-            self.matches_cache[key] = net
-            return net
-
-    def emit_priority_match(self, module_idx: int, en: _nir.Net, inputs: _nir.Value, *, src_loc):
-        key = module_idx, en, inputs, src_loc
-        try:
-            return self.priority_match_cache[key]
-        except KeyError:
-            cell = _nir.PriorityMatch(module_idx, en=en, inputs=inputs, src_loc=src_loc)
-            res = self.netlist.add_value_cell(len(inputs), cell)
-            self.priority_match_cache[key] = res
+            cell = _nir.Match(module_idx, en=en, value=value, patterns=patterns, src_loc=src_loc)
+            res = self.netlist.add_value_cell(len(patterns), cell)
+            self.match_cache[key] = res
             return res
 
     def unify_shapes_bitwise(self,
@@ -956,17 +945,16 @@ class NetlistEmitter:
                 result = self.emit_operator(module_idx, 'm', test, operand_a, operand_b,
                                             src_loc=value.src_loc)
             else:
-                conds = []
                 elems = []
-                for patterns, elem, in value.cases:
-                    if patterns is not None:
-                        net = self.emit_matches(module_idx, test, patterns, src_loc=value.src_loc)
-                        conds.append(net)
+                patterns = []
+                for pattern_list, elem, in value.cases:
+                    if pattern_list is not None:
+                        patterns.append(pattern_list)
                     else:
-                        conds.append(_nir.Net.from_const(1))
+                        patterns.append(("-" * len(test),))
                     elems.append(self.emit_rhs(module_idx, elem))
-                conds = self.emit_priority_match(module_idx, _nir.Net.from_const(1),
-                                                 _nir.Value(conds), src_loc=value.src_loc)
+                conds = self.emit_match(module_idx, _nir.Net.from_const(1), test, tuple(patterns),
+                                        src_loc=value.src_loc)
                 shape = _ast.Shape._unify(
                     _ast.Shape(len(value), signed)
                     for value, signed in elems
@@ -1056,14 +1044,10 @@ class NetlistEmitter:
             offset, _signed = self.emit_rhs(module_idx, lhs.offset)
             width = len(lhs.value)
             num_cases = min((width + lhs.stride - 1) // lhs.stride, 1 << len(offset))
-            conds = []
+            patterns = []
             for case_index in range(num_cases):
-                subcond = self.emit_matches(module_idx, offset,
-                                            (to_binary(case_index, len(offset)),),
-                                            src_loc=lhs.src_loc)
-                conds.append(subcond)
-            conds = self.emit_priority_match(module_idx, cond, _nir.Value(conds),
-                                             src_loc=lhs.src_loc)
+                patterns.append((to_binary(case_index, len(offset)),))
+            conds = self.emit_match(module_idx, cond, offset, tuple(patterns), src_loc=lhs.src_loc)
             for idx, subcond in enumerate(conds):
                 start = lhs_start + idx * lhs.stride
                 if start >= width:
@@ -1075,17 +1059,15 @@ class NetlistEmitter:
                 self.emit_assign(module_idx, cd, lhs.value, start, subrhs, subcond, src_loc=src_loc)
         elif isinstance(lhs, _ast.SwitchValue):
             test, _signed = self.emit_rhs(module_idx, lhs.test)
-            conds = []
+            patterns = []
             elems = []
-            for patterns, elem in lhs.cases:
-                if patterns is not None:
-                    net = self.emit_matches(module_idx, test, patterns, src_loc=lhs.src_loc)
-                    conds.append(net)
+            for pattern_list, elem in lhs.cases:
+                if pattern_list is not None:
+                    patterns.append(pattern_list)
                 else:
-                    conds.append(_nir.Net.from_const(1))
+                    patterns.append(("-" * len(test),))
                 elems.append(elem)
-            conds = self.emit_priority_match(module_idx, cond, _nir.Value(conds),
-                                             src_loc=lhs.src_loc)
+            conds = self.emit_match(module_idx, cond, test, tuple(patterns), src_loc=lhs.src_loc)
             for subcond, val in zip(conds, elems):
                 self.emit_assign(module_idx, cd, val, lhs_start, rhs[:len(val)], subcond, src_loc=src_loc)
         elif isinstance(lhs, _ast.Operator):
@@ -1166,17 +1148,15 @@ class NetlistEmitter:
             self.netlist.add_cell(cell)
         elif isinstance(stmt, _ast.Switch):
             test, _signed = self.emit_rhs(module_idx, stmt.test)
-            conds = []
+            patterns = []
             case_stmts = []
-            for patterns, stmts, case_src_loc in stmt.cases:
-                if patterns is not None:
-                    net = self.emit_matches(module_idx, test, patterns, src_loc=case_src_loc)
-                    conds.append(net)
+            for pattern_list, stmts, case_src_loc in stmt.cases:
+                if pattern_list is not None:
+                    patterns.append(pattern_list)
                 else:
-                    conds.append(_nir.Net.from_const(1))
+                    patterns.append(("-" * len(test),))
                 case_stmts.append(stmts)
-            conds = self.emit_priority_match(module_idx, cond, _nir.Value(conds),
-                                             src_loc=stmt.src_loc)
+            conds = self.emit_match(module_idx, cond, test, tuple(patterns), src_loc=stmt.src_loc)
             for subcond, substmts in zip(conds, case_stmts):
                 for substmt in substmts:
                     self.emit_stmt(module_idx, fragment, domain, substmt, subcond)
@@ -1430,13 +1410,10 @@ class NetlistEmitter:
                         driver.domain.rst is not None and
                         not driver.domain.async_reset and
                         not driver.signal.reset_less):
-                    cond = self.emit_matches(driver.module_idx,
+                    cond, = self.emit_match(driver.module_idx, _nir.Net.from_const(1),
                                             self.emit_signal(driver.domain.rst),
-                                            ("1",),
+                                            (("1",),),
                                             src_loc=driver.domain.rst.src_loc)
-                    cond, = self.emit_priority_match(driver.module_idx, _nir.Net.from_const(1),
-                                                    _nir.Value(cond),
-                                                    src_loc=driver.domain.rst.src_loc)
                     init = _nir.Value.from_const(driver.signal.init, len(driver.signal))
                     driver.assignments.append(_nir.Assignment(cond=cond, start=0,
                                                             value=init, src_loc=driver.signal.src_loc))
diff --git a/amaranth/hdl/_nir.py b/amaranth/hdl/_nir.py
index 3c0af06..23b5313 100644
--- a/amaranth/hdl/_nir.py
+++ b/amaranth/hdl/_nir.py
@@ -15,7 +15,7 @@ __all__ = [
     # Computation cells
     "Operator", "Part",
     # Decision tree cells
-    "Matches", "PriorityMatch", "Assignment", "AssignmentList",
+    "Match", "Assignment", "AssignmentList",
     # Storage cells
     "FlipFlop", "Memory", "SyncWritePort", "AsyncReadPort", "SyncReadPort",
     # Print cells
@@ -768,79 +768,48 @@ class Part(Cell):
             yield (net, self.src_loc)
 
 
-class Matches(Cell):
-    """A combinational cell performing a comparison like ``Value.matches``
-    (or, equivalently, a case condition).
-
-    Attributes
-    ----------
-
-    value: Value
-    patterns: tuple of str, each str contains '0', '1', '-'
-    """
-    def __init__(self, module_idx, *, value, patterns, src_loc):
-        super().__init__(module_idx, src_loc=src_loc)
-
-        for pattern in patterns:
-            assert len(pattern) == len(value)
-        self.value = Value(value)
-        self.patterns = tuple(patterns)
-
-    def input_nets(self):
-        return set(self.value)
-
-    def output_nets(self, self_idx: int):
-        return {Net.from_cell(self_idx, 0)}
-
-    def resolve_nets(self, netlist: Netlist):
-        self.value = netlist.resolve_value(self.value)
-
-    def __repr__(self):
-        patterns = " ".join(self.patterns)
-        return f"(matches {self.value} {patterns})"
-
-    def comb_edges_to(self, bit):
-        for net in self.value:
-            yield (net, self.src_loc)
-
-
-class PriorityMatch(Cell):
+class Match(Cell):
     """Used to represent a single switch on the control plane of processes.
 
-    The output is the same length as ``inputs``. If ``en`` is ``0``, the output
-    is all-0. Otherwise, output keeps the lowest-numbered ``1`` bit in the input
-    (if any) and masks all other bits to ``0``.
-
-    Note: the RTLIL backend requires all bits of ``inputs`` to be driven
-    by a ``Match`` cell within the same module.
+    The output is the same length as ``patterns``. If ``en`` is ``0``, the output
+    is all-0. Otherwise, the ``value`` is matched against all pattern sets
+    in ``patterns``. The output has a ``1`` bit for the first pattern set that
+    matches ``value``, and ``0`` for all other bits. If no pattern set matches
+    the value, the output is all-``0``.
 
     Attributes
     ----------
     en: Net
-    inputs: Value
+    value: Value
+    patterns: tuple of tuple of str, each str contains '0', '1', '-'
     """
-    def __init__(self, module_idx, *, en, inputs, src_loc):
+    def __init__(self, module_idx, *, en, value, patterns, src_loc):
         super().__init__(module_idx, src_loc=src_loc)
 
+        for pattern_list in patterns:
+            for pattern in pattern_list:
+                assert len(pattern) == len(value)
         self.en = Net.ensure(en)
-        self.inputs = Value(inputs)
+        self.value = Value(value)
+        self.patterns = patterns
 
     def input_nets(self):
-        return set(self.inputs) | {self.en}
+        return set(self.value) | {self.en}
 
     def output_nets(self, self_idx: int):
-        return {Net.from_cell(self_idx, bit) for bit in range(len(self.inputs))}
+        return {Net.from_cell(self_idx, bit) for bit in range(len(self.patterns))}
 
     def resolve_nets(self, netlist: Netlist):
         self.en = netlist.resolve_net(self.en)
-        self.inputs = netlist.resolve_value(self.inputs)
+        self.value = netlist.resolve_value(self.value)
 
     def __repr__(self):
-        return f"(priority_match {self.en} {self.inputs})"
+        patterns = " ".join("{" + " ".join(pattern_list) + "}" if len(pattern_list) != 1 else pattern_list[0] for pattern_list in self.patterns)
+        return f"(match {self.en} {self.value} {patterns})"
 
     def comb_edges_to(self, bit):
         yield (self.en, self.src_loc)
-        for net in self.inputs[:bit + 1]:
+        for net in self.value:
             yield (net, self.src_loc)
 
 
@@ -883,7 +852,7 @@ class AssignmentList(Cell):
     then executing each assignment in sequence.
 
     Note: the RTLIL backend requires all ``cond`` inputs of assignments to be driven
-    by a ``PriorityMatch`` cell within the same module.
+    by a ``Match`` cell within the same module.
 
     Attributes
     ----------


Test patch:
diff --git a/tests/test_back_rtlil.py b/tests/test_back_rtlil.py
index eefc399..fa223c3 100644
--- a/tests/test_back_rtlil.py
+++ b/tests/test_back_rtlil.py
@@ -1413,7 +1413,7 @@ class SwitchTestCase(RTLILTestCase):
             wire width 4 output 1 \out
             process $1
                 assign \out [3:0] 4'0000
-                switch { }
+                switch \sel [3:0]
                     case
                         assign \out [3:0] 4'0001
                 end
@@ -1838,7 +1838,7 @@ class PrintTestCase(RTLILTestCase):
             cell $check $3
                 parameter \FORMAT ""
                 parameter \ARGS_WIDTH 0
-                parameter signed \PRIORITY 32'11111111111111111111111111111100
+                parameter signed \PRIORITY 32'11111111111111111111111111111101
                 parameter \TRG_ENABLE 0
                 parameter \TRG_WIDTH 0
                 parameter \TRG_POLARITY 0
diff --git a/tests/test_hdl_ir.py b/tests/test_hdl_ir.py
index f515d76..bbfc86c 100644
--- a/tests/test_hdl_ir.py
+++ b/tests/test_hdl_ir.py
@@ -260,13 +260,12 @@ class FragmentPortsTestCase(FHDLTestCase):
         ])
         self.assertRepr(nl, """
         (
-            (module 0 None ('top') (input 'clk' 0.2) (input 'rst' 0.3) (output 'ctr' 5.0:4))
-            (cell 0 0 (top (input 'clk' 2:3) (input 'rst' 3:4) (output 'ctr' 5.0:4)))
-            (cell 1 0 (+ (cat 5.0:4 1'd0) 5'd1))
-            (cell 2 0 (matches 0.3 1))
-            (cell 3 0 (priority_match 1 2.0))
-            (cell 4 0 (assignment_list 1.0:4 (3.0 0:4 4'd0)))
-            (cell 5 0 (flipflop 4.0:4 0 pos 0.2 0))
+            (module 0 None ('top') (input 'clk' 0.2) (input 'rst' 0.3) (output 'ctr' 4.0:4))
+            (cell 0 0 (top (input 'clk' 2:3) (input 'rst' 3:4) (output 'ctr' 4.0:4)))
+            (cell 1 0 (+ (cat 4.0:4 1'd0) 5'd1))
+            (cell 2 0 (match 1 0.3 1))
+            (cell 3 0 (assignment_list 1.0:4 (2.0 0:4 4'd0)))
+            (cell 4 0 (flipflop 3.0:4 0 pos 0.2 0))
         )
         """)
 
@@ -277,13 +276,12 @@ class FragmentPortsTestCase(FHDLTestCase):
         nl = build_netlist(f, ports=[ctr])
         self.assertRepr(nl, """
         (
-            (module 0 None ('top') (input 'clk' 0.2) (input 'rst' 0.3) (output 'ctr' 5.0:4))
-            (cell 0 0 (top (input 'clk' 2:3) (input 'rst' 3:4) (output 'ctr' 5.0:4)))
-            (cell 1 0 (+ (cat 5.0:4 1'd0) 5'd1))
-            (cell 2 0 (matches 0.3 1))
-            (cell 3 0 (priority_match 1 2.0))
-            (cell 4 0 (assignment_list 1.0:4 (3.0 0:4 4'd0)))
-            (cell 5 0 (flipflop 4.0:4 0 pos 0.2 0))
+            (module 0 None ('top') (input 'clk' 0.2) (input 'rst' 0.3) (output 'ctr' 4.0:4))
+            (cell 0 0 (top (input 'clk' 2:3) (input 'rst' 3:4) (output 'ctr' 4.0:4)))
+            (cell 1 0 (+ (cat 4.0:4 1'd0) 5'd1))
+            (cell 2 0 (match 1 0.3 1))
+            (cell 3 0 (assignment_list 1.0:4 (2.0 0:4 4'd0)))
+            (cell 4 0 (flipflop 3.0:4 0 pos 0.2 0))
         )
         """)
 
@@ -1242,31 +1240,23 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:10)
-                (output 's1' 10.0:8)
+                (output 's1' 2.0:8)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:10)
-                (output 's1' 10.0:8)
-            ))
-            (cell 1 0 (matches 0.6:10 0000))
-            (cell 2 0 (matches 0.6:10 0001))
-            (cell 3 0 (matches 0.6:10 0010))
-            (cell 4 0 (matches 0.6:10 0011))
-            (cell 5 0 (matches 0.6:10 0100))
-            (cell 6 0 (matches 0.6:10 0101))
-            (cell 7 0 (matches 0.6:10 0110))
-            (cell 8 0 (matches 0.6:10 0111))
-            (cell 9 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0)))
-            (cell 10 0 (assignment_list 8'd0
-                (9.0 0:4 0.2:6)
-                (9.1 1:5 0.2:6)
-                (9.2 2:6 0.2:6)
-                (9.3 3:7 0.2:6)
-                (9.4 4:8 0.2:6)
-                (9.5 5:8 0.2:5)
-                (9.6 6:8 0.2:4)
-                (9.7 7:8 0.2)
+                (output 's1' 2.0:8)
+            ))
+            (cell 1 0 (match 1 0.6:10 0000 0001 0010 0011 0100 0101 0110 0111))
+            (cell 2 0 (assignment_list 8'd0
+                (1.0 0:4 0.2:6)
+                (1.1 1:5 0.2:6)
+                (1.2 2:6 0.2:6)
+                (1.3 3:7 0.2:6)
+                (1.4 4:8 0.2:6)
+                (1.5 5:8 0.2:5)
+                (1.6 6:8 0.2:4)
+                (1.7 7:8 0.2)
             ))
         )
         """)
@@ -1286,23 +1276,19 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:8)
-                (output 's1' 6.0:8)
+                (output 's1' 2.0:8)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:8)
-                (output 's1' 6.0:8)
+                (output 's1' 2.0:8)
             ))
-            (cell 1 0 (matches 0.6:8 00))
-            (cell 2 0 (matches 0.6:8 01))
-            (cell 3 0 (matches 0.6:8 10))
-            (cell 4 0 (matches 0.6:8 11))
-            (cell 5 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0)))
-            (cell 6 0 (assignment_list 8'd0
-                (5.0 0:4 0.2:6)
-                (5.1 1:5 0.2:6)
-                (5.2 2:6 0.2:6)
-                (5.3 3:7 0.2:6)
+            (cell 1 0 (match 1 0.6:8 00 01 10 11))
+            (cell 2 0 (assignment_list 8'd0
+                (1.0 0:4 0.2:6)
+                (1.1 1:5 0.2:6)
+                (1.2 2:6 0.2:6)
+                (1.3 3:7 0.2:6)
             ))
         )
         """)
@@ -1322,23 +1308,19 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:10)
-                (output 's1' 6.0:16)
+                (output 's1' 2.0:16)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:10)
-                (output 's1' 6.0:16)
+                (output 's1' 2.0:16)
             ))
-            (cell 1 0 (matches 0.6:10 0000))
-            (cell 2 0 (matches 0.6:10 0001))
-            (cell 3 0 (matches 0.6:10 0010))
-            (cell 4 0 (matches 0.6:10 0011))
-            (cell 5 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0)))
-            (cell 6 0 (assignment_list 16'd0
-                (5.0 0:4 0.2:6)
-                (5.1 4:8 0.2:6)
-                (5.2 8:12 0.2:6)
-                (5.3 12:16 0.2:6)
+            (cell 1 0 (match 1 0.6:10 0000 0001 0010 0011))
+            (cell 2 0 (assignment_list 16'd0
+                (1.0 0:4 0.2:6)
+                (1.1 4:8 0.2:6)
+                (1.2 8:12 0.2:6)
+                (1.3 12:16 0.2:6)
             ))
         )
         """)
@@ -1358,25 +1340,20 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:10)
-                (output 's1' 7.0:17)
+                (output 's1' 2.0:17)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:10)
-                (output 's1' 7.0:17)
+                (output 's1' 2.0:17)
             ))
-            (cell 1 0 (matches 0.6:10 0000))
-            (cell 2 0 (matches 0.6:10 0001))
-            (cell 3 0 (matches 0.6:10 0010))
-            (cell 4 0 (matches 0.6:10 0011))
-            (cell 5 0 (matches 0.6:10 0100))
-            (cell 6 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0)))
-            (cell 7 0 (assignment_list 17'd0
-                (6.0 0:4 0.2:6)
-                (6.1 4:8 0.2:6)
-                (6.2 8:12 0.2:6)
-                (6.3 12:16 0.2:6)
-                (6.4 16:17 0.2)
+            (cell 1 0 (match 1 0.6:10 0000 0001 0010 0011 0100))
+            (cell 2 0 (assignment_list 17'd0
+                (1.0 0:4 0.2:6)
+                (1.1 4:8 0.2:6)
+                (1.2 8:12 0.2:6)
+                (1.3 12:16 0.2:6)
+                (1.4 16:17 0.2)
             ))
         )
         """)
@@ -1478,24 +1455,21 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's4' 0.2:10)
                 (input 's5' 0.10:18)
-                (output 's1' 5.0:8)
-                (output 's2' 6.0:8)
-                (output 's3' 7.0:8)
+                (output 's1' 2.0:8)
+                (output 's2' 3.0:8)
+                (output 's3' 4.0:8)
             )
             (cell 0 0 (top
                 (input 's4' 2:10)
                 (input 's5' 10:18)
-                (output 's1' 5.0:8)
-                (output 's2' 6.0:8)
-                (output 's3' 7.0:8)
+                (output 's1' 2.0:8)
+                (output 's2' 3.0:8)
+                (output 's3' 4.0:8)
             ))
-            (cell 1 0 (matches 0.2:10 00000000))
-            (cell 2 0 (matches 0.2:10 00000001))
-            (cell 3 0 (matches 0.2:10 00000010))
-            (cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
-            (cell 5 0 (assignment_list 8'd0 (4.0 0:8 0.10:18)))
-            (cell 6 0 (assignment_list 8'd0 (4.1 0:8 0.10:18)))
-            (cell 7 0 (assignment_list 8'd0 (4.2 0:8 0.10:18)))
+            (cell 1 0 (match 1 0.2:10 00000000 00000001 00000010))
+            (cell 2 0 (assignment_list 8'd0 (1.0 0:8 0.10:18)))
+            (cell 3 0 (assignment_list 8'd0 (1.1 0:8 0.10:18)))
+            (cell 4 0 (assignment_list 8'd0 (1.2 0:8 0.10:18)))
         )
         """)
 
@@ -1529,33 +1503,26 @@ class AssignTestCase(FHDLTestCase):
                 (input 's5' 0.2:10)
                 (input 's6' 0.10:18)
                 (input 's7' 0.18:26)
-                (output 's1' 10.0:8)
-                (output 's2' 11.0:8)
-                (output 's3' 12.0:8)
-                (output 's4' 13.0:8)
+                (output 's1' 3.0:8)
+                (output 's2' 4.0:8)
+                (output 's3' 5.0:8)
+                (output 's4' 6.0:8)
             )
             (cell 0 0 (top
                 (input 's5' 2:10)
                 (input 's6' 10:18)
                 (input 's7' 18:26)
-                (output 's1' 10.0:8)
-                (output 's2' 11.0:8)
-                (output 's3' 12.0:8)
-                (output 's4' 13.0:8)
-            ))
-            (cell 1 0 (matches 0.2:6 0001))
-            (cell 2 0 (matches 0.2:6 0010 0011))
-            (cell 3 0 (matches 0.2:6 ))
-            (cell 4 0 (matches 0.2:6 11--))
-            (cell 5 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0)))
-            (cell 6 0 (matches 0.6:10 0100))
-            (cell 7 0 (matches 0.6:10 0101))
-            (cell 8 0 (matches 0.6:10 0110))
-            (cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0 1'd1)))
-            (cell 10 0 (assignment_list 8'd0 (5.0 0:8 0.10:18) (9.0 0:8 0.18:26)))
-            (cell 11 0 (assignment_list 8'd0 (5.1 0:8 0.10:18) (9.1 0:8 0.18:26)))
-            (cell 12 0 (assignment_list 8'd0 (5.2 0:8 0.10:18) (9.2 0:8 0.18:26)))
-            (cell 13 0 (assignment_list 8'd0 (5.3 0:8 0.10:18) (9.3 0:8 0.18:26)))
+                (output 's1' 3.0:8)
+                (output 's2' 4.0:8)
+                (output 's3' 5.0:8)
+                (output 's4' 6.0:8)
+            ))
+            (cell 1 0 (match 1 0.2:6 0001 {0010 0011} {} 11--))
+            (cell 2 0 (match 1 0.6:10 0100 0101 0110 ----))
+            (cell 3 0 (assignment_list 8'd0 (1.0 0:8 0.10:18) (2.0 0:8 0.18:26)))
+            (cell 4 0 (assignment_list 8'd0 (1.1 0:8 0.10:18) (2.1 0:8 0.18:26)))
+            (cell 5 0 (assignment_list 8'd0 (1.2 0:8 0.10:18) (2.2 0:8 0.18:26)))
+            (cell 6 0 (assignment_list 8'd0 (1.3 0:8 0.10:18) (2.3 0:8 0.18:26)))
         )
         """)
 
@@ -1575,22 +1542,20 @@ class AssignTestCase(FHDLTestCase):
                 (input 's1' 0.2:10)
                 (input 's4' 0.10:18)
                 (input 'en' 0.18)
-                (output 's2' 6.0:8)
-                (output 's3' 5.0:8)
+                (output 's2' 4.0:8)
+                (output 's3' 3.0:8)
             )
             (cell 0 0 (top
                 (input 's1' 2:10)
                 (input 's4' 10:18)
                 (input 'en' 18:19)
-                (output 's2' 6.0:8)
-                (output 's3' 5.0:8)
+                (output 's2' 4.0:8)
+                (output 's3' 3.0:8)
             ))
-            (cell 1 0 (matches 0.18 1))
-            (cell 2 0 (priority_match 1 1.0))
-            (cell 3 0 (matches 0.2:10 00000000))
-            (cell 4 0 (priority_match 2.0 (cat 3.0 1'd1)))
-            (cell 5 0 (assignment_list 8'd0 (4.0 0:8 0.10:18)))
-            (cell 6 0 (assignment_list 8'd0 (4.1 0:8 0.10:18)))
+            (cell 1 0 (match 1 0.18 1))
+            (cell 2 0 (match 1.0 0.2:10 00000000 --------))
+            (cell 3 0 (assignment_list 8'd0 (2.0 0:8 0.10:18)))
+            (cell 4 0 (assignment_list 8'd0 (2.1 0:8 0.10:18)))
         )
         """)
 
@@ -1668,29 +1633,21 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:10)
-                (output 's1' 10.0:8)
+                (output 's1' 2.0:8)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:10)
-                (output 's1' 10.0:8)
+                (output 's1' 2.0:8)
             ))
-            (cell 1 0 (matches 0.6:10 0000))
-            (cell 2 0 (matches 0.6:10 0001))
-            (cell 3 0 (matches 0.6:10 0010))
-            (cell 4 0 (matches 0.6:10 0011))
-            (cell 5 0 (matches 0.6:10 0100))
-            (cell 6 0 (matches 0.6:10 0101))
-            (cell 7 0 (matches 0.6:10 0110))
-            (cell 8 0 (matches 0.6:10 0111))
-            (cell 9 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0)))
-            (cell 10 0 (assignment_list 8'd0
-                (9.0 2:4 0.2:4)
-                (9.1 3:5 0.2:4)
-                (9.2 4:6 0.2:4)
-                (9.3 5:7 0.2:4)
-                (9.4 6:8 0.2:4)
-                (9.5 7:8 0.2)
+            (cell 1 0 (match 1 0.6:10 0000 0001 0010 0011 0100 0101 0110 0111))
+            (cell 2 0 (assignment_list 8'd0
+                (1.0 2:4 0.2:4)
+                (1.1 3:5 0.2:4)
+                (1.2 4:6 0.2:4)
+                (1.3 5:7 0.2:4)
+                (1.4 6:8 0.2:4)
+                (1.5 7:8 0.2)
             ))
         )
         """)
@@ -1710,19 +1667,17 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:10)
-                (output 's1' 4.0:8)
+                (output 's1' 2.0:8)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:10)
-                (output 's1' 4.0:8)
+                (output 's1' 2.0:8)
             ))
-            (cell 1 0 (matches 0.6:10 0000))
-            (cell 2 0 (matches 0.6:10 0001))
-            (cell 3 0 (priority_match 1 (cat 1.0 2.0)))
-            (cell 4 0 (assignment_list 8'd0
-                (3.0 1:3 0.2:4)
-                (3.1 5:7 0.2:4)
+            (cell 1 0 (match 1 0.6:10 0000 0001))
+            (cell 2 0 (assignment_list 8'd0
+                (1.0 1:3 0.2:4)
+                (1.1 5:7 0.2:4)
             ))
         )
         """)
@@ -1743,24 +1698,21 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's4' 0.2:10)
                 (input 's5' 0.10:18)
-                (output 's1' 5.0:8)
-                (output 's2' 6.0:8)
-                (output 's3' 7.0:8)
+                (output 's1' 2.0:8)
+                (output 's2' 3.0:8)
+                (output 's3' 4.0:8)
             )
             (cell 0 0 (top
                 (input 's4' 2:10)
                 (input 's5' 10:18)
-                (output 's1' 5.0:8)
-                (output 's2' 6.0:8)
-                (output 's3' 7.0:8)
+                (output 's1' 2.0:8)
+                (output 's2' 3.0:8)
+                (output 's3' 4.0:8)
             ))
-            (cell 1 0 (matches 0.2:10 00000000))
-            (cell 2 0 (matches 0.2:10 00000001))
-            (cell 3 0 (matches 0.2:10 00000010))
-            (cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
-            (cell 5 0 (assignment_list 8'd0 (4.0 2:7 0.10:15)))
-            (cell 6 0 (assignment_list 8'd0 (4.1 2:7 0.10:15)))
-            (cell 7 0 (assignment_list 8'd0 (4.2 2:7 0.10:15)))
+            (cell 1 0 (match 1 0.2:10 00000000 00000001 00000010))
+            (cell 2 0 (assignment_list 8'd0 (1.0 2:7 0.10:15)))
+            (cell 3 0 (assignment_list 8'd0 (1.1 2:7 0.10:15)))
+            (cell 4 0 (assignment_list 8'd0 (1.2 2:7 0.10:15)))
         )
         """)
 
@@ -1779,27 +1731,21 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:10)
-                (output 's1' 8.0:8)
+                (output 's1' 2.0:8)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:10)
-                (output 's1' 8.0:8)
-            ))
-            (cell 1 0 (matches 0.6:10 0000))
-            (cell 2 0 (matches 0.6:10 0001))
-            (cell 3 0 (matches 0.6:10 0010))
-            (cell 4 0 (matches 0.6:10 0011))
-            (cell 5 0 (matches 0.6:10 0100))
-            (cell 6 0 (matches 0.6:10 0101))
-            (cell 7 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0)))
-            (cell 8 0 (assignment_list 8'd0
-                (7.0 1:5 0.2:6)
-                (7.1 2:6 0.2:6)
-                (7.2 3:7 0.2:6)
-                (7.3 4:7 0.2:5)
-                (7.4 5:7 0.2:4)
-                (7.5 6:7 0.2)
+                (output 's1' 2.0:8)
+            ))
+            (cell 1 0 (match 1 0.6:10 0000 0001 0010 0011 0100 0101))
+            (cell 2 0 (assignment_list 8'd0
+                (1.0 1:5 0.2:6)
+                (1.1 2:6 0.2:6)
+                (1.2 3:7 0.2:6)
+                (1.3 4:7 0.2:5)
+                (1.4 5:7 0.2:4)
+                (1.5 6:7 0.2)
             ))
         )
         """)
@@ -1819,26 +1765,20 @@ class AssignTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 's2' 0.2:6)
                 (input 's3' 0.6:10)
-                (output 's1' 8.0:12)
+                (output 's1' 2.0:12)
             )
             (cell 0 0 (top
                 (input 's2' 2:6)
                 (input 's3' 6:10)
-                (output 's1' 8.0:12)
+                (output 's1' 2.0:12)
             ))
-            (cell 1 0 (matches 0.6:10 0000))
-            (cell 2 0 (matches 0.6:10 0001))
-            (cell 3 0 (matches 0.6:10 0010))
-            (cell 4 0 (matches 0.6:10 0011))
-            (cell 5 0 (matches 0.6:10 0100))
-            (cell 6 0 (matches 0.6:10 0101))
-            (cell 7 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0)))
-            (cell 8 0 (assignment_list 12'd0
-                (7.0 4:6 0.2:4)
-                (7.1 5:7 0.2:4)
-                (7.2 6:8 0.2:4)
-                (7.3 7:9 0.2:4)
-                (7.4 8:9 0.2)
+            (cell 1 0 (match 1 0.6:10 0000 0001 0010 0011 0100 0101))
+            (cell 2 0 (assignment_list 12'd0
+                (1.0 4:6 0.2:4)
+                (1.1 5:7 0.2:4)
+                (1.2 6:8 0.2:4)
+                (1.3 7:9 0.2:4)
+                (1.4 8:9 0.2)
             ))
         )
         """)
@@ -2888,10 +2828,10 @@ class RhsTestCase(FHDLTestCase):
                 (input 'i8sb' 0.34:42)
                 (input 'i8sc' 0.42:50)
                 (input 'i4' 0.50:54)
-                (output 'o1' (cat 5.0:8 2'd0))
-                (output 'o2' (cat 10.0:9 10.8))
-                (output 'o3' (cat 15.0:8 15.7 15.7))
-                (output 'o4' (cat 20.0:8 20.7 20.7))
+                (output 'o1' (cat 2.0:8 2'd0))
+                (output 'o2' (cat 4.0:9 4.8))
+                (output 'o3' (cat 6.0:8 6.7 6.7))
+                (output 'o4' (cat 8.0:8 8.7 8.7))
             )
             (cell 0 0 (top
                 (input 'i8ua' 2:10)
@@ -2901,46 +2841,34 @@ class RhsTestCase(FHDLTestCase):
                 (input 'i8sb' 34:42)
                 (input 'i8sc' 42:50)
                 (input 'i4' 50:54)
-                (output 'o1' (cat 5.0:8 2'd0))
-                (output 'o2' (cat 10.0:9 10.8))
-                (output 'o3' (cat 15.0:8 15.7 15.7))
-                (output 'o4' (cat 20.0:8 20.7 20.7))
-            ))
-            (cell 1 0 (matches 0.50:54 0000))
-            (cell 2 0 (matches 0.50:54 0001))
-            (cell 3 0 (matches 0.50:54 0010))
-            (cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
-            (cell 5 0 (assignment_list 8'd0
-                (4.0 0:8 0.2:10)
-                (4.1 0:8 0.10:18)
-                (4.2 0:8 0.18:26)
-            ))
-            (cell 6 0 (matches 0.50:54 0000))
-            (cell 7 0 (matches 0.50:54 0001))
-            (cell 8 0 (matches 0.50:54 0010))
-            (cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0)))
-            (cell 10 0 (assignment_list 9'd0
-                (9.0 0:9 (cat 0.2:10 1'd0))
-                (9.1 0:9 (cat 0.10:18 1'd0))
-                (9.2 0:9 (cat 0.42:50 0.49))
-            ))
-            (cell 11 0 (matches 0.50:54 0000))
-            (cell 12 0 (matches 0.50:54 0001))
-            (cell 13 0 (matches 0.50:54 0010))
-            (cell 14 0 (priority_match 1 (cat 11.0 12.0 13.0)))
-            (cell 15 0 (assignment_list 8'd0
-                (14.0 0:8 0.26:34)
-                (14.1 0:8 0.34:42)
-                (14.2 0:8 0.42:50)
-            ))
-            (cell 16 0 (matches 0.50:54 0000))
-            (cell 17 0 (matches 0.50:54 0001))
-            (cell 18 0 (matches 0.50:54 0010))
-            (cell 19 0 (priority_match 1 (cat 16.0 17.0 18.0)))
-            (cell 20 0 (assignment_list 8'd0
-                (19.0 0:8 0.26:34)
-                (19.1 0:8 0.34:42)
-                (19.2 0:8 (cat 0.50:54 4'd0))
+                (output 'o1' (cat 2.0:8 2'd0))
+                (output 'o2' (cat 4.0:9 4.8))
+                (output 'o3' (cat 6.0:8 6.7 6.7))
+                (output 'o4' (cat 8.0:8 8.7 8.7))
+            ))
+            (cell 1 0 (match 1 0.50:54 0000 0001 0010))
+            (cell 2 0 (assignment_list 8'd0
+                (1.0 0:8 0.2:10)
+                (1.1 0:8 0.10:18)
+                (1.2 0:8 0.18:26)
+            ))
+            (cell 3 0 (match 1 0.50:54 0000 0001 0010))
+            (cell 4 0 (assignment_list 9'd0
+                (3.0 0:9 (cat 0.2:10 1'd0))
+                (3.1 0:9 (cat 0.10:18 1'd0))
+                (3.2 0:9 (cat 0.42:50 0.49))
+            ))
+            (cell 5 0 (match 1 0.50:54 0000 0001 0010))
+            (cell 6 0 (assignment_list 8'd0
+                (5.0 0:8 0.26:34)
+                (5.1 0:8 0.34:42)
+                (5.2 0:8 0.42:50)
+            ))
+            (cell 7 0 (match 1 0.50:54 0000 0001 0010))
+            (cell 8 0 (assignment_list 8'd0
+                (7.0 0:8 0.26:34)
+                (7.1 0:8 0.34:42)
+                (7.2 0:8 (cat 0.50:54 4'd0))
             ))
         )
         """)
@@ -2974,8 +2902,8 @@ class RhsTestCase(FHDLTestCase):
                 (input 'i8uc' 0.18:26)
                 (input 'i8ud' 0.26:34)
                 (input 'i4' 0.34:38)
-                (output 'o1' (cat 5.0:8 2'd0))
-                (output 'o2' (cat 10.0:8 2'd0))
+                (output 'o1' (cat 2.0:8 2'd0))
+                (output 'o2' (cat 4.0:8 2'd0))
             )
             (cell 0 0 (top
                 (input 'i8ua' 2:10)
@@ -2983,27 +2911,21 @@ class RhsTestCase(FHDLTestCase):
                 (input 'i8uc' 18:26)
                 (input 'i8ud' 26:34)
                 (input 'i4' 34:38)
-                (output 'o1' (cat 5.0:8 2'd0))
-                (output 'o2' (cat 10.0:8 2'd0))
+                (output 'o1' (cat 2.0:8 2'd0))
+                (output 'o2' (cat 4.0:8 2'd0))
             ))
-            (cell 1 0 (matches 0.34:38 0001))
-            (cell 2 0 (matches 0.34:38 0010 0011))
-            (cell 3 0 (matches 0.34:38 11--))
-            (cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
-            (cell 5 0 (assignment_list 8'd0
-                (4.0 0:8 0.2:10)
-                (4.1 0:8 0.10:18)
-                (4.2 0:8 0.18:26)
+            (cell 1 0 (match 1 0.34:38 0001 {0010 0011} 11--))
+            (cell 2 0 (assignment_list 8'd0
+                (1.0 0:8 0.2:10)
+                (1.1 0:8 0.10:18)
+                (1.2 0:8 0.18:26)
             ))
-            (cell 6 0 (matches 0.34:38 0100 0101))
-            (cell 7 0 (matches 0.34:38 ))
-            (cell 8 0 (matches 0.34:38 0110 0111))
-            (cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0 1'd1)))
-            (cell 10 0 (assignment_list 8'd0
-                (9.0 0:8 0.2:10)
-                (9.1 0:8 0.10:18)
-                (9.2 0:8 0.18:26)
-                (9.3 0:8 0.26:34)
+            (cell 3 0 (match 1 0.34:38 {0100 0101} {} {0110 0111} ----))
+            (cell 4 0 (assignment_list 8'd0
+                (3.0 0:8 0.2:10)
+                (3.1 0:8 0.10:18)
+                (3.2 0:8 0.18:26)
+                (3.3 0:8 0.26:34)
             ))
         )
         """)
@@ -3086,36 +3008,29 @@ class SwitchTestCase(FHDLTestCase):
             (module 0 None ('top')
                 (input 'i' 0.2:6)
                 (input 'i2' 0.6:10)
-                (output 'o1' 12.0:8)
-                (output 'o2' 13.0:8)
+                (output 'o1' 5.0:8)
+                (output 'o2' 6.0:8)
             )
             (cell 0 0 (top
                 (input 'i' 2:6)
                 (input 'i2' 6:10)
-                (output 'o1' 12.0:8)
-                (output 'o2' 13.0:8)
-            ))
-            (cell 1 0 (matches 0.2:4 -1))
-            (cell 2 0 (matches 0.2:4 1-))
-            (cell 3 0 (priority_match 1 (cat 1.0 2.0)))
-            (cell 4 0 (matches 0.4 1))
-            (cell 5 0 (priority_match 1 4.0))
-            (cell 6 0 (matches 0.6:10 0001))
-            (cell 7 0 (matches 0.6:10 0010 0100))
-            (cell 8 0 (matches 0.6:10 11--))
-            (cell 9 0 (priority_match 5.0 (cat 6.0 7.0 8.0)))
-            (cell 10 0 (matches 0.5 1))
-            (cell 11 0 (priority_match 9.2 10.0))
-            (cell 12 0 (assignment_list 8'd0
-                (3.0 0:8 8'd1)
-                (3.1 2:4 2'd2)
-                (11.0 0:8 8'd7)
-            ))
-            (cell 13 0 (assignment_list 8'd123
-                (3.1 0:8 8'd3)
-                (9.0 0:8 8'd4)
-                (9.1 0:8 8'd5)
-                (9.2 0:8 8'd6)
+                (output 'o1' 5.0:8)
+                (output 'o2' 6.0:8)
+            ))
+            (cell 1 0 (match 1 0.2:4 -1 1-))
+            (cell 2 0 (match 1 0.4 1))
+            (cell 3 0 (match 2.0 0.6:10 0001 {0010 0100} 11--))
+            (cell 4 0 (match 3.2 0.5 1))
+            (cell 5 0 (assignment_list 8'd0
+                (1.0 0:8 8'd1)
+                (1.1 2:4 2'd2)
+                (4.0 0:8 8'd7)
+            ))
+            (cell 6 0 (assignment_list 8'd123
+                (1.1 0:8 8'd3)
+                (3.0 0:8 8'd4)
+                (3.1 0:8 8'd5)
+                (3.2 0:8 8'd6)
             ))
         )
         """)
@@ -3154,11 +3069,11 @@ class SwitchTestCase(FHDLTestCase):
                 (input 'b_clk' 0.13)
                 (input 'b_rst' 0.14)
                 (input 'c_clk' 0.15)
-                (output 'o1' 4.0:8)
-                (output 'o2' 8.0:8)
-                (output 'o3' 10.0:8)
-                (output 'o4' 12.0:8)
-                (output 'o5' 14.0:8)
+                (output 'o1' 3.0:8)
+                (output 'o2' 6.0:8)
+                (output 'o3' 8.0:8)
+                (output 'o4' 10.0:8)
+                (output 'o5' 12.0:8)
             )
             (cell 0 0 (top
                 (input 'i1' 2:10)
@@ -3168,26 +3083,24 @@ class SwitchTestCase(FHDLTestCase):
                 (input 'b_clk' 13:14)
                 (input 'b_rst' 14:15)
                 (input 'c_clk' 15:16)
-                (output 'o1' 4.0:8)
-                (output 'o2' 8.0:8)
-                (output 'o3' 10.0:8)
-                (output 'o4' 12.0:8)
-                (output 'o5' 14.0:8)
-            ))
-            (cell 1 0 (matches 0.10 1))
-            (cell 2 0 (priority_match 1 1.0))
-            (cell 3 0 (assignment_list 4.0:8 (2.0 0:8 0.2:10)))
-            (cell 4 0 (flipflop 3.0:8 0 pos 0.11 0))
-            (cell 5 0 (matches 0.12 1))
-            (cell 6 0 (priority_match 1 5.0))
-            (cell 7 0 (assignment_list 8.0:8 (2.0 0:8 0.2:10) (6.0 0:8 8'd123)))
-            (cell 8 0 (flipflop 7.0:8 123 pos 0.11 0))
-            (cell 9 0 (assignment_list 10.0:8 (2.0 0:8 0.2:10)))
-            (cell 10 0 (flipflop 9.0:8 45 pos 0.13 0))
-            (cell 11 0 (assignment_list 12.0:8 (2.0 0:8 0.2:10)))
-            (cell 12 0 (flipflop 11.0:8 67 pos 0.13 0.14))
-            (cell 13 0 (assignment_list 14.0:8 (2.0 0:8 0.2:10)))
-            (cell 14 0 (flipflop 13.0:8 89 neg 0.15 0))
+                (output 'o1' 3.0:8)
+                (output 'o2' 6.0:8)
+                (output 'o3' 8.0:8)
+                (output 'o4' 10.0:8)
+                (output 'o5' 12.0:8)
+            ))
+            (cell 1 0 (match 1 0.10 1))
+            (cell 2 0 (assignment_list 3.0:8 (1.0 0:8 0.2:10)))
+            (cell 3 0 (flipflop 2.0:8 0 pos 0.11 0))
+            (cell 4 0 (match 1 0.12 1))
+            (cell 5 0 (assignment_list 6.0:8 (1.0 0:8 0.2:10) (4.0 0:8 8'd123)))
+            (cell 6 0 (flipflop 5.0:8 123 pos 0.11 0))
+            (cell 7 0 (assignment_list 8.0:8 (1.0 0:8 0.2:10)))
+            (cell 8 0 (flipflop 7.0:8 45 pos 0.13 0))
+            (cell 9 0 (assignment_list 10.0:8 (1.0 0:8 0.2:10)))
+            (cell 10 0 (flipflop 9.0:8 67 pos 0.13 0.14))
+            (cell 11 0 (assignment_list 12.0:8 (1.0 0:8 0.2:10)))
+            (cell 12 0 (flipflop 11.0:8 89 neg 0.15 0))
         )
         """)
 
@@ -3233,18 +3146,17 @@ class SwitchTestCase(FHDLTestCase):
                 (input 'b_rst' 20:21)
                 (input 'c_clk' 21:22)
             ))
-            (cell 1 0 (matches 0.16 1))
-            (cell 2 0 (priority_match 1 1.0))
-            (cell 3 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 4 0 (print 3.0 ((u 0.2:8 ''))))
-            (cell 5 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 6 0 (print 5.0 ((s 0.8:16 '') '\\n')))
-            (cell 7 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 8 0 (print 7.0 pos 0.17 ((u 0.2:8 '') ' ' (s 0.8:16 '') '\\n')))
-            (cell 9 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 10 0 (print 9.0 pos 0.19 ('values: ' (u 0.2:8 '02x') ', ' (s 0.8:16 '+d') '\\n')))
-            (cell 11 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 12 0 (print 11.0 neg 0.21 ('meow\\n')))
+            (cell 1 0 (match 1 0.16 1))
+            (cell 2 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 3 0 (print 2.0 ((u 0.2:8 ''))))
+            (cell 4 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 5 0 (print 4.0 ((s 0.8:16 '') '\\n')))
+            (cell 6 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 7 0 (print 6.0 pos 0.17 ((u 0.2:8 '') ' ' (s 0.8:16 '') '\\n')))
+            (cell 8 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 9 0 (print 8.0 pos 0.19 ('values: ' (u 0.2:8 '02x') ', ' (s 0.8:16 '+d') '\\n')))
+            (cell 10 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 11 0 (print 10.0 neg 0.21 ('meow\\n')))
         )
         """)
 
@@ -3285,21 +3197,20 @@ class SwitchTestCase(FHDLTestCase):
                 (input 'b_rst' 11:12)
                 (input 'c_clk' 12:13)
             ))
-            (cell 1 0 (matches 0.7 1))
-            (cell 2 0 (priority_match 1 1.0))
-            (cell 3 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 4 0 (assert 0.2 3.0 None))
-            (cell 5 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 6 0 (assume 0.3 5.0 ('aaa')))
-            (cell 7 0 (b 0.2:8))
-            (cell 8 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 9 0 (cover 7.0 8.0 ('d')))
-            (cell 10 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 11 0 (assert 0.4 10.0 pos 0.8 None))
-            (cell 12 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 13 0 (assume 0.5 12.0 pos 0.10 ('value: ' (u 0.2:8 ''))))
-            (cell 14 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
-            (cell 15 0 (cover 0.6 14.0 neg 0.12 ('c')))
+            (cell 1 0 (match 1 0.7 1))
+            (cell 2 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 3 0 (assert 0.2 2.0 None))
+            (cell 4 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 5 0 (assume 0.3 4.0 ('aaa')))
+            (cell 6 0 (b 0.2:8))
+            (cell 7 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 8 0 (cover 6.0 7.0 ('d')))
+            (cell 9 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 10 0 (assert 0.4 9.0 pos 0.8 None))
+            (cell 11 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 12 0 (assume 0.5 11.0 pos 0.10 ('value: ' (u 0.2:8 ''))))
+            (cell 13 0 (assignment_list 1'd0 (1.0 0:1 1'd1)))
+            (cell 14 0 (cover 0.6 13.0 neg 0.12 ('c')))
         )
         """)
 
@@ -3337,7 +3248,7 @@ class SplitDriverTestCase(FHDLTestCase):
                 (input 'a_rst' 0.12)
                 (input 'b_clk' 0.13)
                 (input 'b_rst' 0.14)
-                (output 'o' (cat 6.0:2 12.0:2 8.0:2 2'd0 13.0:2))
+                (output 'o' (cat 4.0:2 9.0:2 6.0:2 2'd0 10.0:2))
             )
             (cell 0 0 (top
                 (input 'i1' 2:4)
@@ -3349,21 +3260,18 @@ class SplitDriverTestCase(FHDLTestCase):
                 (input 'a_rst' 12:13)
                 (input 'b_clk' 13:14)
                 (input 'b_rst' 14:15)
-                (output 'o' (cat 6.0:2 12.0:2 8.0:2 2'd0 13.0:2))
+                (output 'o' (cat 4.0:2 9.0:2 6.0:2 2'd0 10.0:2))
             ))
-            (cell 1 0 (matches 0.10 1))
-            (cell 2 0 (priority_match 1 1.0))
-            (cell 3 0 (matches 0.12 1))
-            (cell 4 0 (priority_match 1 3.0))
-            (cell 5 0 (assignment_list 0.2:4 (4.0 0:2 2'd3)))
-            (cell 6 0 (flipflop 5.0:2 3 pos 0.11 0))
-            (cell 7 0 (assignment_list 8.0:2 (2.0 0:2 0.6:8) (4.0 0:2 2'd2)))
-            (cell 8 0 (flipflop 7.0:2 2 pos 0.11 0))
-            (cell 9 0 (matches 0.14 1))
-            (cell 10 0 (priority_match 1 9.0))
-            (cell 11 0 (assignment_list 0.4:6 (10.0 0:2 2'd0)))
-            (cell 12 0 (flipflop 11.0:2 0 pos 0.13 0))
-            (cell 13 0 (assignment_list 2'd1 (2.0 0:2 0.8:10)))
+            (cell 1 0 (match 1 0.10 1))
+            (cell 2 0 (match 1 0.12 1))
+            (cell 3 0 (assignment_list 0.2:4 (2.0 0:2 2'd3)))
+            (cell 4 0 (flipflop 3.0:2 3 pos 0.11 0))
+            (cell 5 0 (assignment_list 6.0:2 (1.0 0:2 0.6:8) (2.0 0:2 2'd2)))
+            (cell 6 0 (flipflop 5.0:2 2 pos 0.11 0))
+            (cell 7 0 (match 1 0.14 1))
+            (cell 8 0 (assignment_list 0.4:6 (7.0 0:2 2'd0)))
+            (cell 9 0 (flipflop 8.0:2 0 pos 0.13 0))
+            (cell 10 0 (assignment_list 2'd1 (1.0 0:2 0.8:10)))
         )
         """)
 
@@ -3392,29 +3300,28 @@ class SplitDriverTestCase(FHDLTestCase):
                 (input 'i2' 0.6:10)
                 (input 'i3' 0.10:12)
                 (input 'cond' 0.12)
-                (output 'o' (cat 0.2:6 3.0:4))
+                (output 'o' (cat 0.2:6 2.0:4))
             )
             (module 1 0 ('top' 'm1')
                 (input 'i1' 0.2:6)
-                (input 'port$3$0' 3.0:4)
+                (input 'port$2$0' 2.0:4)
             )
             (module 2 0 ('top' 'm2')
                 (input 'port$0$2' 0.2:6)
                 (input 'i2' 0.6:10)
                 (input 'i3' 0.10:12)
                 (input 'cond' 0.12)
-                (output 'port$3$0' 3.0:4)
+                (output 'port$2$0' 2.0:4)
             )
             (cell 0 0 (top
                 (input 'i1' 2:6)
                 (input 'i2' 6:10)
                 (input 'i3' 10:12)
                 (input 'cond' 12:13)
-                (output 'o' (cat 0.2:6 3.0:4))
+                (output 'o' (cat 0.2:6 2.0:4))
             ))
-            (cell 1 2 (matches 0.12 1))
-            (cell 2 2 (priority_match 1 1.0))
-            (cell 3 2 (assignment_list 0.6:10 (2.0 1:3 0.10:12)))
+            (cell 1 2 (match 1 0.12 1))
+            (cell 2 2 (assignment_list 0.6:10 (1.0 1:3 0.10:12)))
         )
         """)
 
@@ -3580,10 +3487,9 @@ class CycleTestCase(FHDLTestCase):
 
         with self.assertRaisesRegex(CombinationalCycle,
                 r"^Combinational cycle detected, path:\n"
-                r".*test_hdl_ir.py:\d+: cell Matches bit 0\n"
+                r".*test_hdl_ir.py:\d+: cell Match bit 0\n"
                 r".*test_hdl_ir.py:\d+: signal a bit 0\n"
                 r".*test_hdl_ir.py:\d+: cell AssignmentList bit 0\n"
-                r".*test_hdl_ir.py:\d+: cell PriorityMatch bit 0\n"
                 r"$"):
             build_netlist(Fragment.get(m, None), [])