Repository: bytecodealliance/wasmtime
Pull request #7251 (2023-10-16 13:58:33)

riscv64: Refactor and improve some rotate-related codegen
This commit expands the support a bit for zbb-extension rotates in the riscv64 backend. The lowering rules are all moved to `lower.isle` and some special cases are added for constant rotates as well.


Patch:
diff --git a/Cargo.lock b/Cargo.lock
index 3b6e0bb5a..f3956ba07 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2831,6 +2831,18 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0955b8137a1df6f1a2e9a37d8a6656291ff0297c1a97c24e0d8425fe2312f79a"
 dependencies = [
  "once_cell",
+ "valuable",
+]
+
+[[package]]
+name = "tracing-log"
+version = "0.1.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "78ddad33d2d10b1ed7eb9d1f518a5674713876e97e5bb9b7345a7984fbb4f922"
+dependencies = [
+ "lazy_static",
+ "log",
+ "tracing-core",
 ]
 
 [[package]]
@@ -2847,6 +2859,7 @@ dependencies = [
  "thread_local",
  "tracing",
  "tracing-core",
+ "tracing-log",
 ]
 
 [[package]]
@@ -2953,6 +2966,12 @@ dependencies = [
  "which",
 ]
 
+[[package]]
+name = "valuable"
+version = "0.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "830b7e5d4d90034032940e4ace0d9a9a057e7a45cd94e6c007832e39edb82f6d"
+
 [[package]]
 name = "verify-component-adapter"
 version = "15.0.0"
@@ -3393,7 +3412,6 @@ dependencies = [
  "tempfile",
  "test-programs-artifacts",
  "tokio",
- "tracing-subscriber",
  "walkdir",
  "wasm-encoder",
  "wasmparser",
@@ -3423,8 +3441,8 @@ dependencies = [
  "clap",
  "file-per-thread-logger",
  "humantime 2.1.0",
- "pretty_env_logger 0.5.0",
  "rayon",
+ "tracing-subscriber",
  "wasmtime",
 ]
 
diff --git a/Cargo.toml b/Cargo.toml
index ec36b875e..7c5aa7d9b 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -39,7 +39,6 @@ wasmtime-runtime = { workspace = true }
 clap = { workspace = true, features = ["color", "suggestions", "derive"] }
 anyhow = { workspace = true }
 target-lexicon = { workspace = true }
-tracing-subscriber = { workspace = true }
 once_cell = { workspace = true }
 listenfd = "1.0.0"
 wat = { workspace = true }
@@ -264,7 +263,7 @@ indexmap = "2.0.0"
 pretty_env_logger = "0.5.0"
 syn = "2.0.25"
 test-log = { version = "0.2", default-features = false, features = ["trace"] }
-tracing-subscriber = { version = "0.3.1", default-features = false, features = ['fmt', 'env-filter', 'ansi'] }
+tracing-subscriber = { version = "0.3.1", default-features = false, features = ['fmt', 'env-filter', 'ansi', 'tracing-log'] }
 url = "2.3.1"
 
 [features]
diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index 000121887..57cb48229 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -1548,7 +1548,11 @@
 ;; rd ← rs1 ∧ ~(rs2)
 (decl rv_andn (XReg XReg) XReg)
 (rule (rv_andn rs1 rs2)
+  (if-let $true (has_zbb))
   (alu_rrr (AluOPRRR.Andn) rs1 rs2))
+(rule (rv_andn rs1 rs2)
+  (if-let $false (has_zbb))
+  (rv_and rs1 (rv_not rs2)))
 
 ;; Helper for emitting the `orn` ("Or Negated") instruction.
 ;; rd ← rs1 ∨ ~(rs2)
@@ -1641,6 +1645,16 @@
 (rule (rv_rorw rs1 rs2)
   (alu_rrr (AluOPRRR.Rorw) rs1 rs2))
 
+;; Helper for emitting the `rori` ("Rotate Right") instruction.
+(decl rv_rori (XReg Imm12) XReg)
+(rule (rv_rori rs1 rs2)
+  (alu_rr_imm12 (AluOPRRI.Rori) rs1 rs2))
+
+;; Helper for emitting the `roriw` ("Rotate Right Word") instruction.
+(decl rv_roriw (XReg Imm12) XReg)
+(rule (rv_roriw rs1 rs2)
+  (alu_rr_imm12 (AluOPRRI.Roriw) rs1 rs2))
+
 ;; Helper for emitting the `rev8` ("Byte Reverse") instruction.
 (decl rv_rev8 (XReg) XReg)
 (rule (rv_rev8 rs1)
@@ -1984,16 +1998,6 @@
   (rv_not (value_regs_get x 0)))
 
 
-(decl gen_and (Type ValueRegs ValueRegs) ValueRegs)
-(rule 1 (gen_and $I128 x y)
-  (value_regs
-    (rv_and (value_regs_get x 0) (value_regs_get y 0))
-    (rv_and (value_regs_get x 1) (value_regs_get y 1))))
-
-(rule 0 (gen_and (fits_in_64 _) x y)
-  (rv_and (value_regs_get x 0) (value_regs_get y 0)))
-
-
 (decl gen_andi (XReg u64) XReg)
 (rule 1 (gen_andi x (imm12_from_u64 y))
   (rv_andi x y))
@@ -2192,101 +2196,12 @@
     ((tmp XReg (rv_mul rs1 rs2)))
     (rv_srli tmp (imm12_const (ty_bits ty)))))
 
-
-(decl lower_rotl (Type XReg XReg) XReg)
-
-(rule 1
-  (lower_rotl $I64 rs amount)
-  (if-let $true (has_zbb))
-  (rv_rol rs amount))
-
-(rule
-  (lower_rotl $I64 rs amount)
-  (if-let $false (has_zbb))
-  (lower_rotl_shift $I64 rs amount))
-
-(rule 1
-  (lower_rotl $I32 rs amount)
-  (if-let $true (has_zbb))
-  (rv_rolw rs amount))
-
-(rule
-  (lower_rotl $I32 rs amount)
-  (if-let $false (has_zbb))
-  (lower_rotl_shift $I32 rs amount))
-
-(rule -1
-  (lower_rotl ty rs amount)
-  (lower_rotl_shift ty rs amount))
-
-;;; using shift to implement rotl.
-(decl lower_rotl_shift (Type XReg XReg) XReg)
-
-;;; for I8 and I16 ...
-(rule
-  (lower_rotl_shift ty rs amount)
-  (let
-    ((x ValueRegs (gen_shamt ty amount))
-      (shamt Reg (value_regs_get x 0))
-      (len_sub_shamt Reg (value_regs_get x 1))
-      ;;
-      (part1 Reg (rv_sll rs shamt))
-      ;;
-      (part2 Reg (rv_srl rs len_sub_shamt))
-      (part3 Reg (gen_select_xreg (cmp_eqz shamt) (zero_reg) part2)))
-    (rv_or part1 part3)))
-
-
 ;;;; construct shift amount.rotl on i128 will use shift to implement. So can call this function.
 ;;;; this will return shift amount and (ty_bits - "shift amount")
 ;;;; if ty_bits is greater than 64 like i128, then shmat will fallback to 64.because We are 64 bit platform.
 (decl gen_shamt (Type XReg) ValueRegs)
 (extern constructor gen_shamt gen_shamt)
 
-(decl lower_rotr (Type XReg XReg) XReg)
-
-(rule 1
-  (lower_rotr $I64 rs amount)
-  (if-let $true (has_zbb))
-  (rv_ror rs amount))
-(rule
-  (lower_rotr $I64 rs amount)
-  (if-let $false (has_zbb))
-  (lower_rotr_shift $I64 rs amount))
-
-(rule 1
-  (lower_rotr $I32 rs amount)
-  (if-let $true (has_zbb))
-  (rv_rorw rs amount))
-
-(rule
-  (lower_rotr $I32 rs amount)
-  (if-let $false (has_zbb))
-  (lower_rotr_shift $I32 rs amount))
-
-(rule -1
-  (lower_rotr ty rs amount)
-  (lower_rotr_shift ty rs amount))
-
-(decl lower_rotr_shift (Type XReg XReg) XReg)
-
-;;;
-(rule
-  (lower_rotr_shift ty rs amount)
-  (let
-    ((x ValueRegs (gen_shamt ty amount))
-      (shamt XReg (value_regs_get x 0))
-      (len_sub_shamt XReg (value_regs_get x 1))
-      ;;
-      (part1 XReg (rv_srl rs shamt))
-      ;;
-      (part2 XReg (rv_sll rs len_sub_shamt))
-      ;;
-      (part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) part2)))
-    (rv_or part1 part3)))
-
-
-
 ;; bseti: Set a single bit in a register, indexed by a constant.
 (decl gen_bseti (Reg u64) Reg)
 (rule (gen_bseti val bit)
@@ -2314,67 +2229,6 @@
       (_ Unit (emit (MInst.Popcnt sum step tmp rs $I64))))
     (writable_reg_to_reg sum)))
 
-
-(decl lower_i128_rotl (ValueRegs ValueRegs) ValueRegs)
-(rule
-  (lower_i128_rotl x y)
-  (let
-    ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
-      (shamt XReg (value_regs_get tmp 0))
-      (len_sub_shamt XReg (value_regs_get tmp 1))
-      ;;
-      (low_part1 XReg (rv_sll (value_regs_get x 0) shamt))
-      (low_part2 XReg (rv_srl (value_regs_get x 1) len_sub_shamt))
-      ;;; if shamt == 0 low_part2 will overflow we should zero instead.
-      (low_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) low_part2))
-      (low XReg (rv_or low_part1 low_part3))
-      ;;
-      (high_part1 XReg (rv_sll (value_regs_get x 1) shamt))
-      (high_part2 XReg (rv_srl (value_regs_get x 0) len_sub_shamt))
-      (high_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) high_part2))
-      (high XReg (rv_or high_part1 high_part3))
-      ;;
-      (const64 XReg (imm $I64 64))
-      (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
-    ;; right now we only rotate less than 64 bits.
-    ;; if shamt is greater than or equal 64 , we should switch low and high.
-    (gen_select_regs
-      (cmp_geu shamt_128 const64)
-      (value_regs high low)
-      (value_regs low high)
-    )))
-
-
-(decl lower_i128_rotr (ValueRegs ValueRegs) ValueRegs)
-(rule
-  (lower_i128_rotr x y)
-  (let
-    ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
-      (shamt XReg (value_regs_get tmp 0))
-      (len_sub_shamt XReg (value_regs_get tmp 1))
-      ;;
-      (low_part1 XReg (rv_srl (value_regs_get x 0) shamt))
-      (low_part2 XReg (rv_sll (value_regs_get x 1) len_sub_shamt))
-      ;;; if shamt == 0 low_part2 will overflow we should zero instead.
-      (low_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) low_part2))
-      (low XReg (rv_or low_part1 low_part3))
-      ;;
-      (high_part1 XReg (rv_srl (value_regs_get x 1) shamt))
-      (high_part2 XReg (rv_sll (value_regs_get x 0) len_sub_shamt))
-      (high_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) high_part2))
-      (high XReg (rv_or high_part1 high_part3))
-
-      ;;
-      (const64 XReg (imm $I64 64))
-      (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
-    ;; right now we only rotate less than 64 bits.
-    ;; if shamt is greater than or equal 64 , we should switch low and high.
-    (gen_select_regs
-      (cmp_geu shamt_128 const64)
-      (value_regs high low)
-      (value_regs low high)
-    )))
-
 ;; Generates a AMode that points to a register plus an offset.
 (decl gen_reg_offset_amode (Reg i64 Type) AMode)
 (extern constructor gen_reg_offset_amode gen_reg_offset_amode)
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index bb120d894..2fbeeed37 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -654,8 +654,13 @@
   (rv_rem x y))
 
 ;;;; Rules for `and` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule 0 (lower (has_type (ty_int ty) (band x y)))
-  (gen_and ty x y))
+(rule -1 (lower (has_type (fits_in_64 ty) (band x y)))
+  (rv_and x y))
+
+(rule 0 (lower (has_type $I128 (band x y)))
+  (value_regs
+    (rv_and (value_regs_get x 0) (value_regs_get y 0))
+    (rv_and (value_regs_get x 1) (value_regs_get y 1))))
 
 ;; Special cases for when one operand is an immediate that fits in 12 bits.
 (rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (band x (imm12_from_value y))))
@@ -1214,19 +1219,114 @@
 
 
 ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule (lower (has_type (fits_in_64 ty) (rotl x y)))
-  (lower_rotl ty (zext x) (value_regs_get y 0)))
+
+(rule 0 (lower (has_type (fits_in_64 ty) (rotl rs amount)))
+  (let
+    ((rs XReg (zext rs))
+      (amount XReg (value_regs_get amount 0))
+      (x ValueRegs (gen_shamt ty amount))
+      (shamt XReg (value_regs_get x 0))
+      (len_sub_shamt Reg (value_regs_get x 1))
+      (part1 Reg (rv_sll rs shamt))
+      (part2 Reg (rv_srl rs len_sub_shamt))
+      (part3 Reg (gen_select_xreg (cmp_eqz shamt) (zero_reg) part2)))
+    (rv_or part1 part3)))
+
+(rule 1 (lower (has_type $I32 (rotl rs amount)))
+  (if-let $true (has_zbb))
+  (rv_rolw rs (value_regs_get amount 0)))
+
+(rule 2 (lower (has_type $I32 (rotl rs (u64_from_iconst n))))
+  (if-let $true (has_zbb))
+  (if-let (imm12_from_u64 imm) (u64_sub 32 (u64_and n 31)))
+  (rv_roriw rs imm))
+
+(rule 1 (lower (has_type $I64 (rotl rs amount)))
+  (if-let $true (has_zbb))
+  (rv_rol rs (value_regs_get amount 0)))
+
+(rule 2 (lower (has_type $I64 (rotl rs (u64_from_iconst n))))
+  (if-let $true (has_zbb))
+  (if-let (imm12_from_u64 imm) (u64_sub 64 (u64_and n 63)))
+  (rv_rori rs imm))
 
 (rule 1 (lower (has_type $I128 (rotl x y)))
-  (lower_i128_rotl x y))
+  (let
+    ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
+      (shamt XReg (value_regs_get tmp 0))
+      (len_sub_shamt XReg (value_regs_get tmp 1))
+      (low_part1 XReg (rv_sll (value_regs_get x 0) shamt))
+      (low_part2 XReg (rv_srl (value_regs_get x 1) len_sub_shamt))
+      ;;; if shamt == 0 low_part2 will overflow we should zero instead.
+      (low_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) low_part2))
+      (low XReg (rv_or low_part1 low_part3))
+      (high_part1 XReg (rv_sll (value_regs_get x 1) shamt))
+      (high_part2 XReg (rv_srl (value_regs_get x 0) len_sub_shamt))
+      (high_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) high_part2))
+      (high XReg (rv_or high_part1 high_part3))
+      (const64 XReg (imm $I64 64))
+      (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
+    ;; right now we only rotate less than 64 bits.
+    ;; if shamt is greater than or equal 64 , we should switch low and high.
+    (gen_select_regs
+      (cmp_geu shamt_128 const64)
+      (value_regs high low)
+      (value_regs low high)
+    )))
 
 ;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule (lower (has_type (fits_in_64 ty) (rotr x y)))
-  (lower_rotr ty (zext x) (value_regs_get y 0)))
 
-(rule 1 (lower (has_type $I128 (rotr x y)))
-  (lower_i128_rotr x y))
+(rule (lower (has_type (fits_in_64 ty) (rotr rs amount)))
+  (let
+    ((rs XReg (zext rs))
+      (amount XReg (value_regs_get amount 0))
+      (x ValueRegs (gen_shamt ty amount))
+      (shamt XReg (value_regs_get x 0))
+      (len_sub_shamt XReg (value_regs_get x 1))
+      (part1 XReg (rv_srl rs shamt))
+      (part2 XReg (rv_sll rs len_sub_shamt))
+      (part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) part2)))
+    (rv_or part1 part3)))
+
+(rule 1 (lower (has_type $I32 (rotr rs amount)))
+  (if-let $true (has_zbb))
+  (rv_rorw rs (value_regs_get amount 0)))
+
+(rule 2 (lower (has_type $I32 (rotr rs (imm12_from_value n))))
+  (if-let $true (has_zbb))
+  (rv_roriw rs n))
+
+(rule 1 (lower (has_type $I64 (rotr rs amount)))
+  (if-let $true (has_zbb))
+  (rv_ror rs (value_regs_get amount 0)))
 
+(rule 2 (lower (has_type $I64 (rotr rs (imm12_from_value n))))
+  (if-let $true (has_zbb))
+  (rv_rori rs n))
+
+(rule 1 (lower (has_type $I128 (rotr x y)))
+  (let
+    ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
+      (shamt XReg (value_regs_get tmp 0))
+      (len_sub_shamt XReg (value_regs_get tmp 1))
+      (low_part1 XReg (rv_srl (value_regs_get x 0) shamt))
+      (low_part2 XReg (rv_sll (value_regs_get x 1) len_sub_shamt))
+      ;;; if shamt == 0 low_part2 will overflow we should zero instead.
+      (low_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) low_part2))
+      (low XReg (rv_or low_part1 low_part3))
+      (high_part1 XReg (rv_srl (value_regs_get x 1) shamt))
+      (high_part2 XReg (rv_sll (value_regs_get x 0) len_sub_shamt))
+      (high_part3 XReg (gen_select_xreg (cmp_eqz shamt) (zero_reg) high_part2))
+      (high XReg (rv_or high_part1 high_part3))
+      (const64 XReg (imm $I64 64))
+      (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
+    ;; right now we only rotate less than 64 bits.
+    ;; if shamt is greater than or equal 64 , we should switch low and high.
+    (gen_select_regs
+      (cmp_geu shamt_128 const64)
+      (value_regs high low)
+      (value_regs low high)
+    )))
 
 ;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 (rule 0 (lower (has_type (ty_scalar_float ty) (fabs x)))
@@ -2108,17 +2208,24 @@
 ;;
 ;; We don't have cmov's in RISC-V either, but we can emulate those using bitwise
 ;; operations, which is what we do below.
-(rule (lower (has_type ty (select_spectre_guard cmp @ (value_type cmp_ty) x @ (value_type arg_ty) y)))
-  (let (;; Build a mask that is 0 or -1 depending on the input comparision value.
-        ;; `lower_bmask` handles normalizing the input.
-        (mask ValueRegs (lower_bmask cmp arg_ty))
-        ;; Using the mask above we can select either `x` or `y` by
-        ;; performing a bitwise `and` on both sides and then merging them
-        ;; together. We know that only the bits of one of the sides will be selected.
-        ;; TODO: We can use `andn` here if we have `Zbb`
-        (lhs ValueRegs (gen_and arg_ty x mask))
-        (rhs ValueRegs (gen_and arg_ty y (gen_bnot arg_ty mask))))
-    (gen_or arg_ty lhs rhs)))
+
+;; Base case: use `gen_bmask` to generate a 0 mask or -1 mask from the value of
+;; `cmp`. This is then used with some bit twiddling to produce the final result.
+(rule 0 (lower (has_type (fits_in_64 _) (select_spectre_guard cmp x y)))
+  (let ((mask XReg (gen_bmask cmp)))
+    (rv_or (rv_and mask x) (rv_andn y mask))))
+(rule 1 (lower (has_type $I128 (select_spectre_guard cmp x y)))
+  (let ((mask XReg (gen_bmask cmp)))
+    (value_regs
+      (rv_or (rv_and mask (value_regs_get x 0)) (rv_andn (value_regs_get y 0) mask))
+      (rv_or (rv_and mask (value_regs_get x 1)) (rv_andn (value_regs_get y 1) mask)))))
+
+;; Special case when an argument is the constant zero as some ands and ors
+;; can be folded away.
+(rule 2 (lower (has_type (fits_in_64 _) (select_spectre_guard cmp (i64_from_iconst 0) y)))
+  (rv_andn y (gen_bmask cmp)))
+(rule 3 (lower (has_type (fits_in_64 _) (select_spectre_guard cmp x (i64_from_iconst 0))))
+  (rv_and x (gen_bmask cmp)))
 
 ;;;;;  Rules for `bmask`;;;;;;;;;
 (rule
diff --git a/cranelift/codegen/src/opts/bitops.isle b/cranelift/codegen/src/opts/bitops.isle
index 7e454902a..df0029c04 100644
--- a/cranelift/codegen/src/opts/bitops.isle
+++ b/cranelift/codegen/src/opts/bitops.isle
@@ -145,3 +145,54 @@
 
 ;; (bitrev (bitrev x)) == x
 (rule (simplify (bitrev ty (bitrev ty x))) (subsume x))
+
+;; WebAssembly doesn't have a native byte-swapping instruction at this time so
+;; languages which have a byte-swapping operation will compile it down to bit
+;; shifting and twiddling. This attempts to pattern match what LLVM currently
+;; generates today for the Rust code `a.swap_bytes()`. This might be a bit
+;; brittle over time and/or with other possible LLVM backend optimizations, but
+;; it's at least one way to generate a byte swap.
+;;
+;; Technically this could be permuted quite a few ways and currently there's no
+;; easy way to match all of them, so only one is matched here.
+(rule (simplify (bor ty @ $I32
+    (bor ty
+      (ishl ty x (iconst ty (u64_from_imm64 24)))
+      (ishl ty
+        (band ty x (iconst ty (u64_from_imm64 0xff00)))
+        (iconst ty (u64_from_imm64 8))))
+    (bor ty
+      (band ty
+        (ushr ty x (iconst ty (u64_from_imm64 8)))
+        (iconst ty (u64_from_imm64 0xff00)))
+      (ushr ty x (iconst ty (u64_from_imm64 24))))))
+  (bswap ty x))
+
+(rule (simplify (bor ty @ $I64
+    (bor ty
+      (bor ty
+        (ishl ty x (iconst ty (u64_from_imm64 56)))
+        (ishl ty
+          (band ty x (iconst ty (u64_from_imm64 0xff00)))
+          (iconst ty (u64_from_imm64 40))))
+      (bor ty
+        (ishl ty
+          (band ty x (iconst ty (u64_from_imm64 0xff_0000)))
+          (iconst ty (u64_from_imm64 24)))
+        (ishl ty
+          (band ty x (iconst ty (u64_from_imm64 0xff00_0000)))
+          (iconst ty (u64_from_imm64 8)))))
+    (bor ty
+      (bor ty
+        (band ty
+          (ushr ty x (iconst ty (u64_from_imm64 8)))
+          (iconst ty (u64_from_imm64 0xff00_0000)))
+        (band ty
+          (ushr ty x (iconst ty (u64_from_imm64 24)))
+          (iconst ty (u64_from_imm64 0xff_0000))))
+      (bor ty
+        (band ty
+          (ushr ty x (iconst ty (u64_from_imm64 40)))
+          (iconst ty (u64_from_imm64 0xff00)))
+        (ushr ty x (iconst ty (u64_from_imm64 56)))))))
+  (bswap ty x))
diff --git a/crates/c-api/include/wasmtime/store.h b/crates/c-api/include/wasmtime/store.h
index c86ac5723..ac67d1a1d 100644
--- a/crates/c-api/include/wasmtime/store.h
+++ b/crates/c-api/include/wasmtime/store.h
@@ -156,14 +156,35 @@ WASM_API_EXTERN void wasmtime_context_gc(wasmtime_context_t* context);
  * This function must be called for the store to have
  * some fuel to allow WebAssembly to execute.
  *
- * Note that at this time when fuel is entirely consumed it will cause
- * wasm to trap. More usages of fuel are planned for the future.
+ * Note by default when fuel is entirely consumed it will cause
+ * wasm to trap. If async_support is enabled, you can use 
+ * #wasmtime_context_out_of_fuel_async_yield and the async APIs to yield
+ * execution instead.
  *
  * If fuel is not enabled within this store then an error is returned. If fuel
  * is successfully added then NULL is returned.
  */
 WASM_API_EXTERN wasmtime_error_t *wasmtime_context_add_fuel(wasmtime_context_t *store, uint64_t fuel);
 
+/**
+ * \brief Set fuel to this context's store for wasm to consume while executing.
+ *
+ * For this method to work fuel consumption must be enabled via
+ * #wasmtime_config_consume_fuel_set. By default a store starts with 0 fuel
+ * for wasm to execute with (meaning it will immediately trap).
+ * This function must be called for the store to have
+ * some fuel to allow WebAssembly to execute.
+ *
+ * Note by default when fuel is entirely consumed it will cause
+ * wasm to trap. If async_support is enabled, you can use 
+ * #wasmtime_context_out_of_fuel_async_yield and the async APIs to yield
+ * execution instead.
+ *
+ * If fuel is not enabled within this store then an error is returned. If fuel
+ * is successfully added then NULL is returned.
+ */
+WASM_API_EXTERN wasmtime_error_t *wasmtime_context_reset_fuel(wasmtime_context_t *store, uint64_t fuel);
+
 /**
  * \brief Returns the amount of fuel consumed by this context's store execution
  * so far.
diff --git a/crates/c-api/src/store.rs b/crates/c-api/src/store.rs
index d56977619..d6c95e00c 100644
--- a/crates/c-api/src/store.rs
+++ b/crates/c-api/src/store.rs
@@ -216,6 +216,14 @@ pub extern "C" fn wasmtime_context_add_fuel(
     crate::handle_result(store.add_fuel(fuel), |()| {})
 }
 
+#[no_mangle]
+pub extern "C" fn wasmtime_context_reset_fuel(
+    mut store: CStoreContextMut<'_>,
+    fuel: u64,
+) -> Option<Box<wasmtime_error_t>> {
+    crate::handle_result(store.reset_fuel(fuel), |()| {})
+}
+
 #[no_mangle]
 pub extern "C" fn wasmtime_context_fuel_consumed(store: CStoreContext<'_>, fuel: &mut u64) -> bool {
     match store.fuel_consumed() {
diff --git a/crates/cli-flags/Cargo.toml b/crates/cli-flags/Cargo.toml
index e15b4d14f..725c76267 100644
--- a/crates/cli-flags/Cargo.toml
+++ b/crates/cli-flags/Cargo.toml
@@ -12,7 +12,7 @@ edition.workspace = true
 anyhow = { workspace = true }
 clap = { workspace = true }
 file-per-thread-logger = { workspace = true }
-pretty_env_logger = { workspace = true }
+tracing-subscriber = { workspace = true }
 rayon = "1.5.0"
 wasmtime = { workspace = true }
 humantime = "2.0.0"
diff --git a/crates/cli-flags/src/lib.rs b/crates/cli-flags/src/lib.rs
index db5ba3abc..13efde1dc 100644
--- a/crates/cli-flags/src/lib.rs
+++ b/crates/cli-flags/src/lib.rs
@@ -5,7 +5,9 @@
 
 use anyhow::Result;
 use clap::Parser;
+use std::io::IsTerminal;
 use std::time::Duration;
+use tracing_subscriber::{EnvFilter, FmtSubscriber};
 use wasmtime::Config;
 
 pub mod opt;
@@ -328,7 +330,13 @@ impl CommonOptions {
             let prefix = "wasmtime.dbg.";
             init_file_per_thread_logger(prefix);
         } else {
-            pretty_env_logger::init();
+            let mut b = FmtSubscriber::builder()
+                .with_writer(std::io::stderr)
+                .with_env_filter(EnvFilter::from_env("WASMTIME_LOG"));
+            if std::io::stderr().is_terminal() {
+                b = b.with_ansi(true);
+            }
+            b.init();
         }
     }
 
diff --git a/crates/jit/src/profiling.rs b/crates/jit/src/profiling.rs
index 5e24344ac..06edec82f 100644
--- a/crates/jit/src/profiling.rs
+++ b/crates/jit/src/profiling.rs
@@ -76,7 +76,7 @@ pub trait ProfilingAgent: Send + Sync + 'static {
             }
             let address = sym.address();
             let size = sym.size();
-            if address == 0 || size == 0 {
+            if size == 0 {
                 continue;
             }
             if let Ok(name) = sym.name() {
diff --git a/crates/wasmtime/src/func.rs b/crates/wasmtime/src/func.rs
index 8e3a39d00..a551b64da 100644
--- a/crates/wasmtime/src/func.rs
+++ b/crates/wasmtime/src/func.rs
@@ -1902,6 +1902,13 @@ impl<T> Caller<'_, T> {
         self.store.fuel_consumed()
     }
 
+    /// Returns the remaining fuel in the store.
+    ///
+    /// For more information see [`Store::fuel_remaining`](crate::Store::fuel_remaining)
+    pub fn fuel_remaining(&self) -> Option<u64> {
+        self.store.fuel_remaining()
+    }
+
     /// Inject more fuel into this store to be consumed when executing wasm code.
     ///
     /// For more information see [`Store::add_fuel`](crate::Store::add_fuel)
diff --git a/crates/wasmtime/src/store.rs b/crates/wasmtime/src/store.rs
index 48436c04f..e4745d3ad 100644
--- a/crates/wasmtime/src/store.rs
+++ b/crates/wasmtime/src/store.rs
@@ -792,7 +792,11 @@ impl<T> Store<T> {
     /// If fuel consumption is not enabled via
     /// [`Config::consume_fuel`](crate::Config::consume_fuel) then this
     /// function will return `None`. Also note that fuel, if enabled, must be
-    /// originally configured via [`Store::add_fuel`].
+    /// originally configured via [`Store::add_fuel`] or [`Store::reset_fuel`].
+    ///
+    /// Note that this function returns the amount of fuel consumed since the
+    /// last time [`reset_fuel`][Store::reset_fuel] was called, or since the creation
+    /// of the store if it's never been called.
     pub fn fuel_consumed(&self) -> Option<u64> {
         self.inner.fuel_consumed()
     }
@@ -830,6 +834,20 @@ impl<T> Store<T> {
     pub fn add_fuel(&mut self, fuel: u64) -> Result<()> {
         self.inner.add_fuel(fuel)
     }
+    ///
+    /// Set the remaining fuel to this [`Store`] for wasm to consume while executing.
+    ///
+    /// See [`Store::add_fuel`] for more information about fuel.
+    ///
+    /// This method will also reset the amount of fuel that has been consumed.
+    ///
+    /// # Errors
+    ///
+    /// This function will return an error if fuel consumption is not enabled via
+    /// [`Config::consume_fuel`](crate::Config::consume_fuel).
+    pub fn reset_fuel(&mut self, fuel: u64) -> Result<()> {
+        self.inner.reset_fuel(fuel)
+    }
 
     /// Synthetically consumes fuel from this [`Store`].
     ///
@@ -1118,6 +1136,13 @@ impl<'a, T> StoreContextMut<'a, T> {
         self.0.consume_fuel(fuel)
     }
 
+    /// Set the fuel for this store to be consumed when executing wasm code.
+    ///
+    /// For more information see [`Store::reset_fuel`]
+    pub fn reset_fuel(&mut self, fuel: u64) -> Result<()> {
+        self.0.reset_fuel(fuel)
+    }
+
     /// Configures this `Store` to trap whenever fuel runs out.
     ///
     /// For more information see [`Store::out_of_fuel_trap`]
@@ -1551,6 +1576,10 @@ impl StoreOpaque {
     }
 
     fn consume_fuel(&mut self, fuel: u64) -> Result<u64> {
+        anyhow::ensure!(
+            self.engine().config().tunables.consume_fuel,
+            "fuel is not configured in this store"
+        );
         let consumed_ptr = unsafe { &mut *self.runtime_limits.fuel_consumed.get() };
         match i64::try_from(fuel)
             .ok()
@@ -1564,6 +1593,17 @@ impl StoreOpaque {
         }
     }
 
+    fn reset_fuel(&mut self, fuel: u64) -> Result<()> {
+        anyhow::ensure!(
+            self.engine().config().tunables.consume_fuel,
+            "fuel is not configured in this store"
+        );
+        let fuel = i64::try_from(fuel).unwrap_or(i64::max_value());
+        self.fuel_adj = fuel;
+        unsafe { *self.runtime_limits.fuel_consumed.get() = -fuel };
+        Ok(())
+    }
+
     #[inline]
     pub fn signal_handler(&self) -> Option<*const SignalHandler<'static>> {
         let handler = self.signal_handler.as_ref()?;
diff --git a/src/bin/wasmtime.rs b/src/bin/wasmtime.rs
index 6e289a74b..46868b3ac 100644
--- a/src/bin/wasmtime.rs
+++ b/src/bin/wasmtime.rs
@@ -82,16 +82,6 @@ impl Wasmtime {
 }
 
 fn main() -> Result<()> {
-    use std::io::IsTerminal;
-    use tracing_subscriber::{EnvFilter, FmtSubscriber};
-
-    let mut b = FmtSubscriber::builder()
-        .with_writer(std::io::stderr)
-        .with_env_filter(EnvFilter::from_env("WASMTIME_LOG"));
-    if std::io::stderr().is_terminal() {
-        b = b.with_ansi(true);
-    }
-    b.init();
     Wasmtime::parse().execute()
 }
 
diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml
index f03ba4690..70303719b 100644
--- a/supply-chain/audits.toml
+++ b/supply-chain/audits.toml
@@ -2120,6 +2120,15 @@ This is a relatively minor set of releases with minor refactorings and bug
 fixes. Nothing fundamental was added in these changes.
 """
 
+[[audits.tracing-log]]
+who = "Alex Crichton <alex@alexcrichton.com>"
+criteria = "safe-to-deploy"
+version = "0.1.3"
+notes = """
+This is a standard adapter between the `log` ecosystem and the `tracing`
+ecosystem. There's one `unsafe` block in this crate and it's well-scoped.
+"""
+
 [[audits.tracing-subscriber]]
 who = "Pat Hickey <phickey@fastly.com>"
 criteria = "safe-to-deploy"
diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock
index e80834140..27558affd 100644
--- a/supply-chain/imports.lock
+++ b/supply-chain/imports.lock
@@ -1207,6 +1207,12 @@ criteria = "safe-to-deploy"
 version = "0.2.1"
 notes = "Single unsafe usage that looks sound, no ambient capabilities"
 
+[[audits.embark-studios.audits.valuable]]
+who = "Johan Andersson <opensource@embark-studios.com>"
+criteria = "safe-to-deploy"
+version = "0.1.0"
+notes = "No unsafe usage or ambient capabilities, sane build script"
+
 [[audits.embark-studios.audits.webpki-roots]]
 who = "Johan Andersson <opensource@embark-studios.com>"
 criteria = "safe-to-deploy"


Test patch:
diff --git a/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
index 60c5438e7..79c7787f3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
@@ -17,7 +17,7 @@ block0(v0: i8, v1: i8, v2: i8):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -30,7 +30,7 @@ block0(v0: i8, v1: i8, v2: i8):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -51,7 +51,7 @@ block0(v0: i8, v1: i16, v2: i16):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -64,7 +64,7 @@ block0(v0: i8, v1: i16, v2: i16):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -85,7 +85,7 @@ block0(v0: i8, v1: i32, v2: i32):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -98,7 +98,7 @@ block0(v0: i8, v1: i32, v2: i32):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -119,7 +119,7 @@ block0(v0: i8, v1: i64, v2: i64):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -132,7 +132,7 @@ block0(v0: i8, v1: i64, v2: i64):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -147,60 +147,37 @@ block0(v0: i8, v1: i128, v2: i128):
 }
 
 ; VCode:
-;   add sp,-16
-;   sd ra,8(sp)
-;   sd fp,0(sp)
-;   mv fp,sp
-;   sd s10,-8(sp)
-;   add sp,-16
 ; block0:
 ;   slli a5,a0,56
 ;   srai a5,a5,56
 ;   xori a5,a5,42
 ;   seqz a5,a5
 ;   sub a5,zero,a5
-;   and a0,a1,a5
-;   and a2,a2,a5
-;   not s10,a5
+;   and a0,a5,a1
 ;   not a1,a5
-;   and a3,a3,s10
-;   and a4,a4,a1
-;   or a0,a0,a3
-;   or a1,a2,a4
-;   add sp,+16
-;   ld s10,-8(sp)
-;   ld ra,8(sp)
-;   ld fp,0(sp)
-;   add sp,+16
+;   and a1,a3,a1
+;   or a0,a0,a1
+;   and a2,a5,a2
+;   not a5,a5
+;   and a1,a4,a5
+;   or a1,a2,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi sp, sp, -0x10
-;   sd ra, 8(sp)
-;   sd s0, 0(sp)
-;   mv s0, sp
-;   sd s10, -8(sp)
-;   addi sp, sp, -0x10
-; block1: ; offset 0x18
 ;   slli a5, a0, 0x38
 ;   srai a5, a5, 0x38
 ;   xori a5, a5, 0x2a
 ;   seqz a5, a5
 ;   neg a5, a5
-;   and a0, a1, a5
-;   and a2, a2, a5
-;   not s10, a5
+;   and a0, a5, a1
 ;   not a1, a5
-;   and a3, a3, s10
-;   and a4, a4, a1
-;   or a0, a0, a3
-;   or a1, a2, a4
-;   addi sp, sp, 0x10
-;   ld s10, -8(sp)
-;   ld ra, 8(sp)
-;   ld s0, 0(sp)
-;   addi sp, sp, 0x10
+;   and a1, a3, a1
+;   or a0, a0, a1
+;   and a2, a5, a2
+;   not a5, a5
+;   and a1, a4, a5
+;   or a1, a2, a1
 ;   ret
 
 function %f(i16, i8, i8) -> i8 {
@@ -218,7 +195,7 @@ block0(v0: i16, v1: i8, v2: i8):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -231,7 +208,7 @@ block0(v0: i16, v1: i8, v2: i8):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -252,7 +229,7 @@ block0(v0: i16, v1: i16, v2: i16):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -265,7 +242,7 @@ block0(v0: i16, v1: i16, v2: i16):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -286,7 +263,7 @@ block0(v0: i16, v1: i32, v2: i32):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -299,7 +276,7 @@ block0(v0: i16, v1: i32, v2: i32):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -320,7 +297,7 @@ block0(v0: i16, v1: i64, v2: i64):
 ;   xori a3,a5,42
 ;   seqz a3,a3
 ;   sub a3,zero,a3
-;   and a4,a1,a3
+;   and a4,a3,a1
 ;   not a0,a3
 ;   and a2,a2,a0
 ;   or a0,a4,a2
@@ -333,7 +310,7 @@ block0(v0: i16, v1: i64, v2: i64):
 ;   xori a3, a5, 0x2a
 ;   seqz a3, a3
 ;   neg a3, a3
-;   and a4, a1, a3
+;   and a4, a3, a1
 ;   not a0, a3
 ;   and a2, a2, a0
 ;   or a0, a4, a2
@@ -348,60 +325,37 @@ block0(v0: i16, v1: i128, v2: i128):
 }
 
 ; VCode:
-;   add sp,-16
-;   sd ra,8(sp)
-;   sd fp,0(sp)
-;   mv fp,sp
-;   sd s10,-8(sp)
-;   add sp,-16
 ; block0:
 ;   slli a5,a0,48
 ;   srai a5,a5,48
 ;   xori a5,a5,42
 ;   seqz a5,a5
 ;   sub a5,zero,a5
-;   and a0,a1,a5
-;   and a2,a2,a5
-;   not s10,a5
+;   and a0,a5,a1
 ;   not a1,a5
-;   and a3,a3,s10
-;   and a4,a4,a1
-;   or a0,a0,a3
-;   or a1,a2,a4
-;   add sp,+16
-;   ld s10,-8(sp)
-;   ld ra,8(sp)
-;   ld fp,0(sp)
-;   add sp,+16
+;   and a1,a3,a1
+;   or a0,a0,a1
+;   and a2,a5,a2
+;   not a5,a5
+;   and a1,a4,a5
+;   or a1,a2,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi sp, sp, -0x10
-;   sd ra, 8(sp)
-;   sd s0, 0(sp)
-;   mv s0, sp
-;   sd s10, -8(sp)
-;   addi sp, sp, -0x10
-; block1: ; offset 0x18
 ;   slli a5, a0, 0x30
 ;   srai a5, a5, 0x30
 ;   xori a5, a5, 0x2a
 ;   seqz a5, a5
 ;   neg a5, a5
-;   and a0, a1, a5
-;   and a2, a2, a5
-;   not s10, a5
+;   and a0, a5, a1
 ;   not a1, a5
-;   and a3, a3, s10
-;   and a4, a4, a1
-;   or a0, a0, a3
-;   or a1, a2, a4
-;   addi sp, sp, 0x10
-;   ld s10, -8(sp)
-;   ld ra, 8(sp)
-;   ld s0, 0(sp)
-;   addi sp, sp, 0x10
+;   and a1, a3, a1
+;   or a0, a0, a1
+;   and a2, a5, a2
+;   not a5, a5
+;   and a1, a4, a5
+;   or a1, a2, a1
 ;   ret
 
 function %f(i32, i8, i8) -> i8 {
@@ -418,7 +372,7 @@ block0(v0: i32, v1: i8, v2: i8):
 ;   xori a5,a3,42
 ;   seqz a3,a5
 ;   sub a4,zero,a3
-;   and a3,a1,a4
+;   and a3,a4,a1
 ;   not a5,a4
 ;   and a1,a2,a5
 ;   or a0,a3,a1
@@ -430,7 +384,7 @@ block0(v0: i32, v1: i8, v2: i8):
 ;   xori a5, a3, 0x2a
 ;   seqz a3, a5
 ;   neg a4, a3
-;   and a3, a1, a4
+;   and a3, a4, a1
 ;   not a5, a4
 ;   and a1, a2, a5
 ;   or a0, a3, a1
@@ -450,7 +404,7 @@ block0(v0: i32, v1: i16, v2: i16):
 ;   xori a5,a3,42
 ;   seqz a3,a5
 ;   sub a4,zero,a3
-;   and a3,a1,a4
+;   and a3,a4,a1
 ;   not a5,a4
 ;   and a1,a2,a5
 ;   or a0,a3,a1
@@ -462,7 +416,7 @@ block0(v0: i32, v1: i16, v2: i16):
 ;   xori a5, a3, 0x2a
 ;   seqz a3, a5
 ;   neg a4, a3
-;   and a3, a1, a4
+;   and a3, a4, a1
 ;   not a5, a4
 ;   and a1, a2, a5
 ;   or a0, a3, a1
@@ -482,7 +436,7 @@ block0(v0: i32, v1: i32, v2: i32):
 ;   xori a5,a3,42
 ;   seqz a3,a5
 ;   sub a4,zero,a3
-;   and a3,a1,a4
+;   and a3,a4,a1
 ;   not a5,a4
 ;   and a1,a2,a5
 ;   or a0,a3,a1
@@ -494,7 +448,7 @@ block0(v0: i32, v1: i32, v2: i32):
 ;   xori a5, a3, 0x2a
 ;   seqz a3, a5
 ;   neg a4, a3
-;   and a3, a1, a4
+;   and a3, a4, a1
 ;   not a5, a4
 ;   and a1, a2, a5
 ;   or a0, a3, a1
@@ -514,7 +468,7 @@ block0(v0: i32, v1: i64, v2: i64):
 ;   xori a5,a3,42
 ;   seqz a3,a5
 ;   sub a4,zero,a3
-;   and a3,a1,a4
+;   and a3,a4,a1
 ;   not a5,a4
 ;   and a1,a2,a5
 ;   or a0,a3,a1
@@ -526,7 +480,7 @@ block0(v0: i32, v1: i64, v2: i64):
 ;   xori a5, a3, 0x2a
 ;   seqz a3, a5
 ;   neg a4, a3
-;   and a3, a1, a4
+;   and a3, a4, a1
 ;   not a5, a4
 ;   and a1, a2, a5
 ;   or a0, a3, a1
@@ -545,15 +499,15 @@ block0(v0: i32, v1: i128, v2: i128):
 ;   sext.w a5,a0
 ;   xori a5,a5,42
 ;   seqz a5,a5
-;   sub a0,zero,a5
-;   and a5,a1,a0
-;   and a1,a2,a0
-;   not a2,a0
-;   not a0,a0
-;   and a2,a3,a2
-;   and a3,a4,a0
-;   or a0,a5,a2
-;   or a1,a1,a3
+;   sub a5,zero,a5
+;   and a0,a5,a1
+;   not a1,a5
+;   and a3,a3,a1
+;   or a0,a0,a3
+;   and a1,a5,a2
+;   not a3,a5
+;   and a5,a4,a3
+;   or a1,a1,a5
 ;   ret
 ;
 ; Disassembled:
@@ -561,15 +515,15 @@ block0(v0: i32, v1: i128, v2: i128):
 ;   sext.w a5, a0
 ;   xori a5, a5, 0x2a
 ;   seqz a5, a5
-;   neg a0, a5
-;   and a5, a1, a0
-;   and a1, a2, a0
-;   not a2, a0
-;   not a0, a0
-;   and a2, a3, a2
-;   and a3, a4, a0
-;   or a0, a5, a2
-;   or a1, a1, a3
+;   neg a5, a5
+;   and a0, a5, a1
+;   not a1, a5
+;   and a3, a3, a1
+;   or a0, a0, a3
+;   and a1, a5, a2
+;   not a3, a5
+;   and a5, a4, a3
+;   or a1, a1, a5
 ;   ret
 
 function %f(i64, i8, i8) -> i8 {
@@ -585,7 +539,7 @@ block0(v0: i64, v1: i8, v2: i8):
 ;   xori a3,a0,42
 ;   seqz a5,a3
 ;   sub a0,zero,a5
-;   and a3,a1,a0
+;   and a3,a0,a1
 ;   not a4,a0
 ;   and a0,a2,a4
 ;   or a0,a3,a0
@@ -596,7 +550,7 @@ block0(v0: i64, v1: i8, v2: i8):
 ;   xori a3, a0, 0x2a
 ;   seqz a5, a3
 ;   neg a0, a5
-;   and a3, a1, a0
+;   and a3, a0, a1
 ;   not a4, a0
 ;   and a0, a2, a4
 ;   or a0, a3, a0
@@ -615,7 +569,7 @@ block0(v0: i64, v1: i16, v2: i16):
 ;   xori a3,a0,42
 ;   seqz a5,a3
 ;   sub a0,zero,a5
-;   and a3,a1,a0
+;   and a3,a0,a1
 ;   not a4,a0
 ;   and a0,a2,a4
 ;   or a0,a3,a0
@@ -626,7 +580,7 @@ block0(v0: i64, v1: i16, v2: i16):
 ;   xori a3, a0, 0x2a
 ;   seqz a5, a3
 ;   neg a0, a5
-;   and a3, a1, a0
+;   and a3, a0, a1
 ;   not a4, a0
 ;   and a0, a2, a4
 ;   or a0, a3, a0
@@ -645,7 +599,7 @@ block0(v0: i64, v1: i32, v2: i32):
 ;   xori a3,a0,42
 ;   seqz a5,a3
 ;   sub a0,zero,a5
-;   and a3,a1,a0
+;   and a3,a0,a1
 ;   not a4,a0
 ;   and a0,a2,a4
 ;   or a0,a3,a0
@@ -656,7 +610,7 @@ block0(v0: i64, v1: i32, v2: i32):
 ;   xori a3, a0, 0x2a
 ;   seqz a5, a3
 ;   neg a0, a5
-;   and a3, a1, a0
+;   and a3, a0, a1
 ;   not a4, a0
 ;   and a0, a2, a4
 ;   or a0, a3, a0
@@ -675,7 +629,7 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   xori a3,a0,42
 ;   seqz a5,a3
 ;   sub a0,zero,a5
-;   and a3,a1,a0
+;   and a3,a0,a1
 ;   not a4,a0
 ;   and a0,a2,a4
 ;   or a0,a3,a0
@@ -686,7 +640,7 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   xori a3, a0, 0x2a
 ;   seqz a5, a3
 ;   neg a0, a5
-;   and a3, a1, a0
+;   and a3, a0, a1
 ;   not a4, a0
 ;   and a0, a2, a4
 ;   or a0, a3, a0
@@ -708,19 +662,19 @@ block0(v0: i64, v1: i128, v2: i128):
 ;   sd s11,-8(sp)
 ;   add sp,-16
 ; block0:
-;   mv s11,a1
-;   xori a5,a0,42
-;   seqz a5,a5
-;   sub a1,zero,a5
-;   mv a5,s11
-;   and a5,a5,a1
-;   and a2,a2,a1
-;   not a0,a1
-;   not a1,a1
-;   and a0,a3,a0
-;   and a3,a4,a1
+;   mv s11,a3
+;   xori a3,a0,42
+;   seqz a5,a3
+;   sub a3,zero,a5
+;   and a5,a3,a1
+;   not a0,a3
+;   mv a1,s11
+;   and a0,a1,a0
 ;   or a0,a5,a0
-;   or a1,a2,a3
+;   and a1,a3,a2
+;   not a2,a3
+;   and a4,a4,a2
+;   or a1,a1,a4
 ;   add sp,+16
 ;   ld s11,-8(sp)
 ;   ld ra,8(sp)
@@ -737,19 +691,19 @@ block0(v0: i64, v1: i128, v2: i128):
 ;   sd s11, -8(sp)
 ;   addi sp, sp, -0x10
 ; block1: ; offset 0x18
-;   mv s11, a1
-;   xori a5, a0, 0x2a
-;   seqz a5, a5
-;   neg a1, a5
-;   mv a5, s11
-;   and a5, a5, a1
-;   and a2, a2, a1
-;   not a0, a1
-;   not a1, a1
-;   and a0, a3, a0
-;   and a3, a4, a1
+;   mv s11, a3
+;   xori a3, a0, 0x2a
+;   seqz a5, a3
+;   neg a3, a5
+;   and a5, a3, a1
+;   not a0, a3
+;   mv a1, s11
+;   and a0, a1, a0
 ;   or a0, a5, a0
-;   or a1, a2, a3
+;   and a1, a3, a2
+;   not a2, a3
+;   and a4, a4, a2
+;   or a1, a1, a4
 ;   addi sp, sp, 0x10
 ;   ld s11, -8(sp)
 ;   ld ra, 8(sp)
@@ -775,7 +729,7 @@ block0(v0: i128, v1: i8, v2: i8):
 ;   or a4,a0,a4
 ;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a1,a2,a5
+;   and a1,a5,a2
 ;   not a4,a5
 ;   and a5,a3,a4
 ;   or a0,a1,a5
@@ -790,7 +744,7 @@ block0(v0: i128, v1: i8, v2: i8):
 ;   or a4, a0, a4
 ;   seqz a0, a4
 ;   neg a5, a0
-;   and a1, a2, a5
+;   and a1, a5, a2
 ;   not a4, a5
 ;   and a5, a3, a4
 ;   or a0, a1, a5
@@ -814,7 +768,7 @@ block0(v0: i128, v1: i16, v2: i16):
 ;   or a4,a0,a4
 ;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a1,a2,a5
+;   and a1,a5,a2
 ;   not a4,a5
 ;   and a5,a3,a4
 ;   or a0,a1,a5
@@ -829,7 +783,7 @@ block0(v0: i128, v1: i16, v2: i16):
 ;   or a4, a0, a4
 ;   seqz a0, a4
 ;   neg a5, a0
-;   and a1, a2, a5
+;   and a1, a5, a2
 ;   not a4, a5
 ;   and a5, a3, a4
 ;   or a0, a1, a5
@@ -853,7 +807,7 @@ block0(v0: i128, v1: i32, v2: i32):
 ;   or a4,a0,a4
 ;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a1,a2,a5
+;   and a1,a5,a2
 ;   not a4,a5
 ;   and a5,a3,a4
 ;   or a0,a1,a5
@@ -868,7 +822,7 @@ block0(v0: i128, v1: i32, v2: i32):
 ;   or a4, a0, a4
 ;   seqz a0, a4
 ;   neg a5, a0
-;   and a1, a2, a5
+;   and a1, a5, a2
 ;   not a4, a5
 ;   and a5, a3, a4
 ;   or a0, a1, a5
@@ -892,7 +846,7 @@ block0(v0: i128, v1: i64, v2: i64):
 ;   or a4,a0,a4
 ;   seqz a0,a4
 ;   sub a5,zero,a0
-;   and a1,a2,a5
+;   and a1,a5,a2
 ;   not a4,a5
 ;   and a5,a3,a4
 ;   or a0,a1,a5
@@ -907,7 +861,7 @@ block0(v0: i128, v1: i64, v2: i64):
 ;   or a4, a0, a4
 ;   seqz a0, a4
 ;   neg a5, a0
-;   and a1, a2, a5
+;   and a1, a5, a2
 ;   not a4, a5
 ;   and a5, a3, a4
 ;   or a0, a1, a5
@@ -923,12 +877,6 @@ block0(v0: i128, v1: i128, v2: i128):
 }
 
 ; VCode:
-;   add sp,-16
-;   sd ra,8(sp)
-;   sd fp,0(sp)
-;   mv fp,sp
-;   sd s7,-8(sp)
-;   add sp,-16
 ; block0:
 ;   li a6,42
 ;   li a7,0
@@ -936,50 +884,33 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   xor a1,a1,a7
 ;   or a0,a0,a1
 ;   seqz a0,a0
-;   sub s7,zero,a0
-;   and a1,a2,s7
-;   and a2,a3,s7
-;   not a0,s7
-;   not a3,s7
-;   and a0,a4,a0
-;   and a3,a5,a3
-;   or a0,a1,a0
+;   sub a1,zero,a0
+;   and a0,a1,a2
+;   not a2,a1
+;   and a2,a4,a2
+;   or a0,a0,a2
+;   and a2,a1,a3
+;   not a1,a1
+;   and a3,a5,a1
 ;   or a1,a2,a3
-;   add sp,+16
-;   ld s7,-8(sp)
-;   ld ra,8(sp)
-;   ld fp,0(sp)
-;   add sp,+16
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi sp, sp, -0x10
-;   sd ra, 8(sp)
-;   sd s0, 0(sp)
-;   mv s0, sp
-;   sd s7, -8(sp)
-;   addi sp, sp, -0x10
-; block1: ; offset 0x18
 ;   addi a6, zero, 0x2a
 ;   mv a7, zero
 ;   xor a0, a0, a6
 ;   xor a1, a1, a7
 ;   or a0, a0, a1
 ;   seqz a0, a0
-;   neg s7, a0
-;   and a1, a2, s7
-;   and a2, a3, s7
-;   not a0, s7
-;   not a3, s7
-;   and a0, a4, a0
-;   and a3, a5, a3
-;   or a0, a1, a0
+;   neg a1, a0
+;   and a0, a1, a2
+;   not a2, a1
+;   and a2, a4, a2
+;   or a0, a0, a2
+;   and a2, a1, a3
+;   not a1, a1
+;   and a3, a5, a1
 ;   or a1, a2, a3
-;   addi sp, sp, 0x10
-;   ld s7, -8(sp)
-;   ld ra, 8(sp)
-;   ld s0, 0(sp)
-;   addi sp, sp, 0x10
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index ba167eddf..0bb3e3c82 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,40 +41,34 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
+;;   slli a0,a0,32
+;;   srli a3,a0,32
 ;;   ld a4,8(a2)
 ;;   addi a4,a4,-4
-;;   sltu a0,a4,a5
-;;   ld a4,0(a2)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   sw a1,0(a2)
+;;   sltu a4,a4,a3
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   sub a5,zero,a4
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sw a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   ld a4,8(a1)
-;;   addi a4,a4,-4
-;;   sltu a0,a4,a5
-;;   ld a4,0(a1)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   lw a0,0(a2)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   ld a3,8(a1)
+;;   addi a3,a3,-4
+;;   sltu a3,a3,a2
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   sub a5,zero,a3
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lw a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 994cff4df..96357b19c 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,48 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a3,a3,32
-;;   ld a4,8(a2)
-;;   lui a5,-1
-;;   addi a5,a5,-4
-;;   add a4,a4,a5
-;;   sltu a4,a4,a3
+;;   slli a4,a0,32
+;;   srli a0,a4,32
+;;   ld a5,8(a2)
+;;   lui a4,-1
+;;   addi a3,a4,-4
+;;   add a5,a5,a3
+;;   sltu a5,a5,a0
 ;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a3,1
-;;   add a2,a2,a3
-;;   li a3,0
-;;   sub a4,zero,a4
-;;   and a0,a3,a4
-;;   not a3,a4
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sw a1,0(a0)
+;;   add a0,a2,a0
+;;   lui a2,1
+;;   add a0,a0,a2
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a2,a0,a5
+;;   sw a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a2,a0,32
-;;   srli a3,a2,32
-;;   ld a2,8(a1)
+;;   slli a4,a0,32
+;;   srli a0,a4,32
+;;   ld a5,8(a1)
 ;;   lui a4,-1
-;;   addi a4,a4,-4
-;;   add a2,a2,a4
-;;   sltu a2,a2,a3
-;;   ld a4,0(a1)
-;;   add a3,a4,a3
-;;   lui a4,1
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a2
-;;   and a0,a4,a5
-;;   not a2,a5
-;;   and a4,a3,a2
-;;   or a0,a0,a4
-;;   lw a0,0(a0)
+;;   addi a2,a4,-4
+;;   add a5,a5,a2
+;;   sltu a5,a5,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   lui a1,1
+;;   add a0,a0,a1
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a1,a0,a5
+;;   lw a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index ea77f187d..9baf545ce 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,54 +41,48 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   lui a3,262140
-;;   addi a4,a3,1
-;;   slli a0,a4,2
-;;   add a4,a5,a0
-;;   trap_if heap_oob##(a4 ult a5)
-;;   ld a0,8(a2)
-;;   sltu a0,a0,a4
+;;   slli a0,a0,32
+;;   srli a3,a0,32
+;;   lui a5,262140
+;;   addi a4,a5,1
+;;   slli a4,a4,2
+;;   add a4,a3,a4
+;;   trap_if heap_oob##(a4 ult a3)
+;;   ld a5,8(a2)
+;;   sltu a4,a5,a4
 ;;   ld a2,0(a2)
-;;   add a5,a2,a5
-;;   lui a4,65535
-;;   slli a2,a4,4
-;;   add a5,a5,a2
-;;   li a2,0
-;;   sub a4,zero,a0
-;;   and a3,a2,a4
-;;   not a0,a4
-;;   and a2,a5,a0
-;;   or a3,a3,a2
-;;   sw a1,0(a3)
+;;   add a2,a2,a3
+;;   lui a3,65535
+;;   slli a3,a3,4
+;;   add a2,a2,a3
+;;   sub a0,zero,a4
+;;   not a3,a0
+;;   and a4,a2,a3
+;;   sw a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   lui a2,262140
-;;   addi a4,a2,1
-;;   slli a0,a4,2
-;;   add a4,a5,a0
-;;   trap_if heap_oob##(a4 ult a5)
-;;   ld a0,8(a1)
-;;   sltu a0,a0,a4
-;;   ld a1,0(a1)
-;;   add a5,a1,a5
-;;   lui a4,65535
-;;   slli a1,a4,4
-;;   add a5,a5,a1
-;;   li a1,0
-;;   sub a2,zero,a0
-;;   and a3,a1,a2
-;;   not a0,a2
-;;   and a1,a5,a0
-;;   or a3,a3,a1
-;;   lw a0,0(a3)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   lui a5,262140
+;;   addi a3,a5,1
+;;   slli a3,a3,2
+;;   add a3,a2,a3
+;;   trap_if heap_oob##(a3 ult a2)
+;;   ld a4,8(a1)
+;;   sltu a3,a4,a3
+;;   ld a4,0(a1)
+;;   add a2,a4,a2
+;;   lui a1,65535
+;;   slli a4,a1,4
+;;   add a2,a2,a4
+;;   sub a0,zero,a3
+;;   not a3,a0
+;;   and a4,a2,a3
+;;   lw a0,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 195c5ac3d..78b730de2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,40 +41,34 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
+;;   slli a0,a0,32
+;;   srli a3,a0,32
 ;;   ld a4,8(a2)
-;;   sltu a3,a5,a4
-;;   xori a0,a3,1
-;;   ld a4,0(a2)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   sb a1,0(a2)
+;;   sltu a0,a3,a4
+;;   xori a4,a0,1
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   sub a5,zero,a4
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sb a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   ld a4,8(a1)
-;;   sltu a3,a5,a4
-;;   xori a0,a3,1
-;;   ld a4,0(a1)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   lbu a0,0(a2)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   ld a3,8(a1)
+;;   sltu a0,a2,a3
+;;   xori a3,a0,1
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   sub a5,zero,a3
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lbu a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 43c5420c6..889daa3f2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,48 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a3,a3,32
-;;   ld a4,8(a2)
-;;   lui a5,-1
-;;   addi a5,a5,-1
-;;   add a4,a4,a5
-;;   sltu a4,a4,a3
+;;   slli a4,a0,32
+;;   srli a0,a4,32
+;;   ld a5,8(a2)
+;;   lui a4,-1
+;;   addi a3,a4,-1
+;;   add a5,a5,a3
+;;   sltu a5,a5,a0
 ;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a3,1
-;;   add a2,a2,a3
-;;   li a3,0
-;;   sub a4,zero,a4
-;;   and a0,a3,a4
-;;   not a3,a4
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sb a1,0(a0)
+;;   add a0,a2,a0
+;;   lui a2,1
+;;   add a0,a0,a2
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a2,a0,a5
+;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a2,a0,32
-;;   srli a3,a2,32
-;;   ld a2,8(a1)
+;;   slli a4,a0,32
+;;   srli a0,a4,32
+;;   ld a5,8(a1)
 ;;   lui a4,-1
-;;   addi a4,a4,-1
-;;   add a2,a2,a4
-;;   sltu a2,a2,a3
-;;   ld a4,0(a1)
-;;   add a3,a4,a3
-;;   lui a4,1
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a2
-;;   and a0,a4,a5
-;;   not a2,a5
-;;   and a4,a3,a2
-;;   or a0,a0,a4
-;;   lbu a0,0(a0)
+;;   addi a2,a4,-1
+;;   add a5,a5,a2
+;;   sltu a5,a5,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   lui a1,1
+;;   add a0,a0,a1
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a1,a0,a5
+;;   lbu a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index beff93305..ed660712b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,24 +41,21 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a3,a3,32
-;;   ld a4,[const(0)]
-;;   add a4,a3,a4
-;;   trap_if heap_oob##(a4 ult a3)
-;;   ld a5,8(a2)
-;;   sltu a4,a5,a4
-;;   ld a5,0(a2)
-;;   add a3,a5,a3
-;;   lui a2,65535
-;;   slli a5,a2,4
-;;   add a3,a3,a5
-;;   li a5,0
-;;   sub a0,zero,a4
-;;   and a2,a5,a0
-;;   not a4,a0
-;;   and a5,a3,a4
-;;   or a2,a2,a5
+;;   slli a4,a0,32
+;;   srli a0,a4,32
+;;   ld a5,[const(0)]
+;;   add a5,a0,a5
+;;   trap_if heap_oob##(a5 ult a0)
+;;   ld a3,8(a2)
+;;   sltu a3,a3,a5
+;;   ld a2,0(a2)
+;;   add a0,a2,a0
+;;   lui a5,65535
+;;   slli a2,a5,4
+;;   add a0,a0,a2
+;;   sub a4,zero,a3
+;;   not a2,a4
+;;   and a2,a0,a2
 ;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
@@ -66,25 +63,22 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a2,a0,32
-;;   srli a3,a2,32
-;;   ld a2,[const(0)]
-;;   add a2,a3,a2
-;;   trap_if heap_oob##(a2 ult a3)
-;;   ld a4,8(a1)
-;;   sltu a4,a4,a2
-;;   ld a5,0(a1)
-;;   add a3,a5,a3
-;;   lui a2,65535
-;;   slli a5,a2,4
-;;   add a3,a3,a5
-;;   li a5,0
-;;   sub a0,zero,a4
-;;   and a1,a5,a0
-;;   not a4,a0
-;;   and a5,a3,a4
-;;   or a1,a1,a5
-;;   lbu a0,0(a1)
+;;   slli a4,a0,32
+;;   srli a0,a4,32
+;;   ld a5,[const(0)]
+;;   add a5,a0,a5
+;;   trap_if heap_oob##(a5 ult a0)
+;;   ld a2,8(a1)
+;;   sltu a2,a2,a5
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   lui a5,65535
+;;   slli a1,a5,4
+;;   add a0,a0,a1
+;;   sub a4,zero,a2
+;;   not a1,a4
+;;   and a2,a0,a1
+;;   lbu a0,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 3b1224187..2f23d3365 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,18 +41,15 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a4,a3,32
-;;   ld a3,8(a2)
-;;   sltu a5,a3,a4
-;;   ld a3,0(a2)
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a5
-;;   and a2,a4,a5
-;;   not a4,a5
-;;   and a5,a3,a4
-;;   or a2,a2,a5
+;;   slli a5,a0,32
+;;   srli a3,a5,32
+;;   ld a0,8(a2)
+;;   sltu a0,a0,a3
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   sub a4,zero,a0
+;;   not a0,a4
+;;   and a2,a2,a0
 ;;   sw a1,0(a2)
 ;;   j label1
 ;; block1:
@@ -60,19 +57,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a2,a0,32
-;;   srli a4,a2,32
-;;   ld a3,8(a1)
-;;   sltu a5,a3,a4
-;;   ld a3,0(a1)
-;;   add a3,a3,a4
-;;   li a4,0
-;;   sub a5,zero,a5
-;;   and a1,a4,a5
-;;   not a4,a5
-;;   and a5,a3,a4
-;;   or a1,a1,a5
-;;   lw a0,0(a1)
+;;   slli a5,a0,32
+;;   srli a2,a5,32
+;;   ld a0,8(a1)
+;;   sltu a0,a0,a2
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   sub a4,zero,a0
+;;   not a0,a4
+;;   and a2,a1,a0
+;;   lw a0,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 2e3e7ff87..7bac94ea9 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,42 +41,36 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a4,a0,32
-;;   srli a0,a4,32
-;;   ld a5,8(a2)
-;;   sltu a5,a5,a0
+;;   slli a3,a0,32
+;;   srli a4,a3,32
+;;   ld a3,8(a2)
+;;   sltu a3,a3,a4
 ;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   lui a2,1
-;;   add a0,a0,a2
-;;   li a2,0
-;;   sub a4,zero,a5
-;;   and a3,a2,a4
-;;   not a5,a4
-;;   and a2,a0,a5
-;;   or a3,a3,a2
-;;   sw a1,0(a3)
+;;   add a2,a2,a4
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   sub a0,zero,a3
+;;   not a3,a0
+;;   and a4,a2,a3
+;;   sw a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a4,a0,32
-;;   srli a0,a4,32
-;;   ld a5,8(a1)
-;;   sltu a5,a5,a0
-;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   lui a1,1
-;;   add a0,a0,a1
-;;   li a1,0
-;;   sub a2,zero,a5
-;;   and a3,a1,a2
-;;   not a5,a2
-;;   and a1,a0,a5
-;;   or a3,a3,a1
-;;   lw a0,0(a3)
+;;   slli a2,a0,32
+;;   srli a3,a2,32
+;;   ld a2,8(a1)
+;;   sltu a2,a2,a3
+;;   ld a4,0(a1)
+;;   add a3,a4,a3
+;;   lui a4,1
+;;   add a3,a3,a4
+;;   sub a0,zero,a2
+;;   not a2,a0
+;;   and a4,a3,a2
+;;   lw a0,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index a84eec913..cc49002d8 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,44 +41,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a3,a5,32
-;;   ld a0,8(a2)
-;;   sltu a0,a0,a3
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a5,65535
-;;   slli a3,a5,4
-;;   add a2,a2,a3
-;;   li a3,0
-;;   sub a5,zero,a0
-;;   and a4,a3,a5
-;;   not a0,a5
-;;   and a2,a2,a0
-;;   or a4,a4,a2
-;;   sw a1,0(a4)
+;;   slli a3,a0,32
+;;   srli a4,a3,32
+;;   ld a3,8(a2)
+;;   sltu a3,a3,a4
+;;   ld a5,0(a2)
+;;   add a4,a5,a4
+;;   lui a2,65535
+;;   slli a5,a2,4
+;;   add a4,a4,a5
+;;   sub a2,zero,a3
+;;   not a3,a2
+;;   and a5,a4,a3
+;;   sw a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a2,a5,32
-;;   ld a0,8(a1)
-;;   sltu a0,a0,a2
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   lui a5,65535
-;;   slli a2,a5,4
-;;   add a1,a1,a2
-;;   li a2,0
-;;   sub a3,zero,a0
-;;   and a4,a2,a3
-;;   not a0,a3
-;;   and a2,a1,a0
-;;   or a4,a4,a2
-;;   lw a0,0(a4)
+;;   slli a2,a0,32
+;;   srli a4,a2,32
+;;   ld a3,8(a1)
+;;   sltu a3,a3,a4
+;;   ld a5,0(a1)
+;;   add a4,a5,a4
+;;   lui a2,65535
+;;   slli a5,a2,4
+;;   add a4,a4,a5
+;;   sub a1,zero,a3
+;;   not a3,a1
+;;   and a5,a4,a3
+;;   lw a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 34d3c2fd2..18970c5a1 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,40 +41,34 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
+;;   slli a0,a0,32
+;;   srli a3,a0,32
 ;;   ld a4,8(a2)
-;;   sltu a3,a5,a4
-;;   xori a0,a3,1
-;;   ld a4,0(a2)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   sb a1,0(a2)
+;;   sltu a0,a3,a4
+;;   xori a4,a0,1
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   sub a5,zero,a4
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sb a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   ld a4,8(a1)
-;;   sltu a3,a5,a4
-;;   xori a0,a3,1
-;;   ld a4,0(a1)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   lbu a0,0(a2)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   ld a3,8(a1)
+;;   sltu a0,a2,a3
+;;   xori a3,a0,1
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   sub a5,zero,a3
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lbu a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index da2afc375..c93afa87b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,42 +41,36 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a4,a0,32
-;;   srli a0,a4,32
-;;   ld a5,8(a2)
-;;   sltu a5,a5,a0
+;;   slli a3,a0,32
+;;   srli a4,a3,32
+;;   ld a3,8(a2)
+;;   sltu a3,a3,a4
 ;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   lui a2,1
-;;   add a0,a0,a2
-;;   li a2,0
-;;   sub a4,zero,a5
-;;   and a3,a2,a4
-;;   not a5,a4
-;;   and a2,a0,a5
-;;   or a3,a3,a2
-;;   sb a1,0(a3)
+;;   add a2,a2,a4
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   sub a0,zero,a3
+;;   not a3,a0
+;;   and a4,a2,a3
+;;   sb a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a4,a0,32
-;;   srli a0,a4,32
-;;   ld a5,8(a1)
-;;   sltu a5,a5,a0
-;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   lui a1,1
-;;   add a0,a0,a1
-;;   li a1,0
-;;   sub a2,zero,a5
-;;   and a3,a1,a2
-;;   not a5,a2
-;;   and a1,a0,a5
-;;   or a3,a3,a1
-;;   lbu a0,0(a3)
+;;   slli a2,a0,32
+;;   srli a3,a2,32
+;;   ld a2,8(a1)
+;;   sltu a2,a2,a3
+;;   ld a4,0(a1)
+;;   add a3,a4,a3
+;;   lui a4,1
+;;   add a3,a3,a4
+;;   sub a0,zero,a2
+;;   not a2,a0
+;;   and a4,a3,a2
+;;   lbu a0,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 590e58f0a..ce5e2af1f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,44 +41,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a3,a5,32
-;;   ld a0,8(a2)
-;;   sltu a0,a0,a3
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a5,65535
-;;   slli a3,a5,4
-;;   add a2,a2,a3
-;;   li a3,0
-;;   sub a5,zero,a0
-;;   and a4,a3,a5
-;;   not a0,a5
-;;   and a2,a2,a0
-;;   or a4,a4,a2
-;;   sb a1,0(a4)
+;;   slli a3,a0,32
+;;   srli a4,a3,32
+;;   ld a3,8(a2)
+;;   sltu a3,a3,a4
+;;   ld a5,0(a2)
+;;   add a4,a5,a4
+;;   lui a2,65535
+;;   slli a5,a2,4
+;;   add a4,a4,a5
+;;   sub a2,zero,a3
+;;   not a3,a2
+;;   and a5,a4,a3
+;;   sb a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a2,a5,32
-;;   ld a0,8(a1)
-;;   sltu a0,a0,a2
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   lui a5,65535
-;;   slli a2,a5,4
-;;   add a1,a1,a2
-;;   li a2,0
-;;   sub a3,zero,a0
-;;   and a4,a2,a3
-;;   not a0,a3
-;;   and a2,a1,a0
-;;   or a4,a4,a2
-;;   lbu a0,0(a4)
+;;   slli a2,a0,32
+;;   srli a4,a2,32
+;;   ld a3,8(a1)
+;;   sltu a3,a3,a4
+;;   ld a5,0(a1)
+;;   add a4,a5,a4
+;;   lui a2,65535
+;;   slli a5,a2,4
+;;   add a4,a4,a5
+;;   sub a1,zero,a3
+;;   not a3,a1
+;;   and a5,a4,a3
+;;   lbu a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 6adb604a3..76bca6405 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,36 +41,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a3,8(a2)
-;;   addi a3,a3,-4
-;;   sltu a3,a3,a0
+;;   ld a5,8(a2)
+;;   addi a5,a5,-4
+;;   sltu a5,a5,a0
 ;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sw a1,0(a0)
+;;   add a0,a2,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a2,a0,a5
+;;   sw a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a2,8(a1)
-;;   addi a2,a2,-4
-;;   sltu a3,a2,a0
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   lw a0,0(a0)
+;;   ld a5,8(a1)
+;;   addi a5,a5,-4
+;;   sltu a5,a5,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a1,a0,a5
+;;   lw a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 3bdbeae34..c2c8fad1b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -42,43 +42,37 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   lui a5,-1
-;;   addi a4,a5,-4
+;;   lui a4,-1
+;;   addi a4,a4,-4
 ;;   add a3,a3,a4
 ;;   sltu a3,a3,a0
-;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   lui a2,1
-;;   add a0,a0,a2
-;;   li a2,0
-;;   sub a3,zero,a3
-;;   and a4,a2,a3
-;;   not a2,a3
-;;   and a2,a0,a2
-;;   or a4,a4,a2
-;;   sw a1,0(a4)
+;;   ld a4,0(a2)
+;;   add a4,a4,a0
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a2,zero,a3
+;;   not a3,a2
+;;   and a5,a4,a3
+;;   sw a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a2,8(a1)
-;;   lui a5,-1
-;;   addi a3,a5,-4
-;;   add a2,a2,a3
-;;   sltu a2,a2,a0
-;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   lui a1,1
-;;   add a0,a0,a1
-;;   li a1,0
-;;   sub a2,zero,a2
-;;   and a4,a1,a2
-;;   not a1,a2
-;;   and a2,a0,a1
-;;   or a4,a4,a2
-;;   lw a0,0(a4)
+;;   ld a3,8(a1)
+;;   lui a2,-1
+;;   addi a4,a2,-4
+;;   add a3,a3,a4
+;;   sltu a3,a3,a0
+;;   ld a4,0(a1)
+;;   add a4,a4,a0
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a1,zero,a3
+;;   not a3,a1
+;;   and a5,a4,a3
+;;   lw a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 7c4543ebf..cd9ffc9cc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -42,23 +42,20 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,262140
-;;   addi a3,a3,1
-;;   slli a4,a3,2
-;;   add a3,a0,a4
-;;   trap_if heap_oob##(a3 ult a0)
-;;   ld a4,8(a2)
-;;   sltu a3,a4,a3
-;;   ld a4,0(a2)
-;;   add a4,a4,a0
-;;   lui a2,65535
-;;   slli a5,a2,4
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a3
-;;   and a2,a5,a0
-;;   not a3,a0
-;;   and a5,a4,a3
-;;   or a2,a2,a5
+;;   addi a5,a3,1
+;;   slli a3,a5,2
+;;   add a5,a0,a3
+;;   trap_if heap_oob##(a5 ult a0)
+;;   ld a3,8(a2)
+;;   sltu a3,a3,a5
+;;   ld a2,0(a2)
+;;   add a0,a2,a0
+;;   lui a5,65535
+;;   slli a2,a5,4
+;;   add a0,a0,a2
+;;   sub a4,zero,a3
+;;   not a2,a4
+;;   and a2,a0,a2
 ;;   sw a1,0(a2)
 ;;   j label1
 ;; block1:
@@ -66,25 +63,22 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a2,262140
-;;   addi a2,a2,1
-;;   slli a4,a2,2
-;;   add a2,a0,a4
-;;   trap_if heap_oob##(a2 ult a0)
-;;   ld a3,8(a1)
-;;   sltu a3,a3,a2
-;;   ld a4,0(a1)
-;;   add a4,a4,a0
-;;   lui a2,65535
-;;   slli a5,a2,4
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a3
-;;   and a1,a5,a0
-;;   not a3,a0
-;;   and a5,a4,a3
-;;   or a1,a1,a5
-;;   lw a0,0(a1)
+;;   lui a3,262140
+;;   addi a5,a3,1
+;;   slli a2,a5,2
+;;   add a5,a0,a2
+;;   trap_if heap_oob##(a5 ult a0)
+;;   ld a2,8(a1)
+;;   sltu a2,a2,a5
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   lui a5,65535
+;;   slli a1,a5,4
+;;   add a0,a0,a1
+;;   sub a4,zero,a2
+;;   not a1,a4
+;;   and a2,a0,a1
+;;   lw a0,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 0efa4f99d..ab64fade6 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,36 +41,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a3,8(a2)
-;;   sltu a3,a0,a3
-;;   xori a3,a3,1
-;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sb a1,0(a0)
+;;   ld a5,8(a2)
+;;   sltu a4,a0,a5
+;;   xori a3,a4,1
+;;   ld a5,0(a2)
+;;   add a5,a5,a0
+;;   sub a3,zero,a3
+;;   not a0,a3
+;;   and a2,a5,a0
+;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a2,8(a1)
-;;   sltu a2,a0,a2
-;;   xori a3,a2,1
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   lbu a0,0(a0)
+;;   ld a5,8(a1)
+;;   sltu a4,a0,a5
+;;   xori a2,a4,1
+;;   ld a5,0(a1)
+;;   add a5,a5,a0
+;;   sub a3,zero,a2
+;;   not a0,a3
+;;   and a1,a5,a0
+;;   lbu a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 7173df6a2..66c48cb1b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -42,43 +42,37 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   lui a5,-1
-;;   addi a4,a5,-1
+;;   lui a4,-1
+;;   addi a4,a4,-1
 ;;   add a3,a3,a4
 ;;   sltu a3,a3,a0
-;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   lui a2,1
-;;   add a0,a0,a2
-;;   li a2,0
-;;   sub a3,zero,a3
-;;   and a4,a2,a3
-;;   not a2,a3
-;;   and a2,a0,a2
-;;   or a4,a4,a2
-;;   sb a1,0(a4)
+;;   ld a4,0(a2)
+;;   add a4,a4,a0
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a2,zero,a3
+;;   not a3,a2
+;;   and a5,a4,a3
+;;   sb a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a2,8(a1)
-;;   lui a5,-1
-;;   addi a3,a5,-1
-;;   add a2,a2,a3
-;;   sltu a2,a2,a0
-;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   lui a1,1
-;;   add a0,a0,a1
-;;   li a1,0
-;;   sub a2,zero,a2
-;;   and a4,a1,a2
-;;   not a1,a2
-;;   and a2,a0,a1
-;;   or a4,a4,a2
-;;   lbu a0,0(a4)
+;;   ld a3,8(a1)
+;;   lui a2,-1
+;;   addi a4,a2,-1
+;;   add a3,a3,a4
+;;   sltu a3,a3,a0
+;;   ld a4,0(a1)
+;;   add a4,a4,a0
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a1,zero,a3
+;;   not a3,a1
+;;   and a5,a4,a3
+;;   lbu a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 03b506de0..f8524212d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,42 +45,36 @@
 ;;   add a3,a0,a3
 ;;   trap_if heap_oob##(a3 ult a0)
 ;;   ld a4,8(a2)
-;;   sltu a3,a4,a3
-;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   lui a0,65535
-;;   slli a4,a0,4
-;;   add a2,a2,a4
-;;   li a4,0
-;;   sub a3,zero,a3
-;;   and a5,a4,a3
-;;   not a3,a3
-;;   and a3,a2,a3
-;;   or a5,a5,a3
-;;   sb a1,0(a5)
+;;   sltu a4,a4,a3
+;;   ld a5,0(a2)
+;;   add a5,a5,a0
+;;   lui a3,65535
+;;   slli a0,a3,4
+;;   add a5,a5,a0
+;;   sub a2,zero,a4
+;;   not a4,a2
+;;   and a0,a5,a4
+;;   sb a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a2,[const(0)]
-;;   add a2,a0,a2
-;;   trap_if heap_oob##(a2 ult a0)
-;;   ld a3,8(a1)
-;;   sltu a2,a3,a2
-;;   ld a1,0(a1)
-;;   add a1,a1,a0
-;;   lui a0,65535
-;;   slli a3,a0,4
-;;   add a1,a1,a3
-;;   li a3,0
-;;   sub a4,zero,a2
-;;   and a5,a3,a4
-;;   not a2,a4
-;;   and a3,a1,a2
-;;   or a5,a5,a3
-;;   lbu a0,0(a5)
+;;   ld a3,[const(0)]
+;;   add a3,a0,a3
+;;   trap_if heap_oob##(a3 ult a0)
+;;   ld a4,8(a1)
+;;   sltu a4,a4,a3
+;;   ld a5,0(a1)
+;;   add a5,a5,a0
+;;   lui a3,65535
+;;   slli a0,a3,4
+;;   add a5,a5,a0
+;;   sub a2,zero,a4
+;;   not a4,a2
+;;   and a0,a5,a4
+;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index e979425c8..8fa602c76 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,34 +41,28 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a3,8(a2)
-;;   sltu a3,a3,a0
-;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a3,zero,a3
-;;   and a5,a4,a3
-;;   not a3,a3
-;;   and a3,a2,a3
-;;   or a5,a5,a3
-;;   sw a1,0(a5)
+;;   ld a4,8(a2)
+;;   sltu a4,a4,a0
+;;   ld a5,0(a2)
+;;   add a5,a5,a0
+;;   sub a2,zero,a4
+;;   not a4,a2
+;;   and a0,a5,a4
+;;   sw a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a2,8(a1)
-;;   sltu a2,a2,a0
-;;   ld a1,0(a1)
-;;   add a1,a1,a0
-;;   li a3,0
-;;   sub a4,zero,a2
-;;   and a5,a3,a4
-;;   not a2,a4
-;;   and a3,a1,a2
-;;   or a5,a5,a3
-;;   lw a0,0(a5)
+;;   ld a4,8(a1)
+;;   sltu a4,a4,a0
+;;   ld a5,0(a1)
+;;   add a5,a5,a0
+;;   sub a2,zero,a4
+;;   not a4,a2
+;;   and a0,a5,a4
+;;   lw a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index c4222e3b4..0f24853ad 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -43,16 +43,13 @@
 ;; block0:
 ;;   ld a3,8(a2)
 ;;   sltu a3,a3,a0
-;;   ld a4,0(a2)
-;;   add a4,a4,a0
-;;   lui a5,1
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a3
-;;   and a2,a5,a0
-;;   not a3,a0
-;;   and a5,a4,a3
-;;   or a2,a2,a5
+;;   ld a2,0(a2)
+;;   add a0,a2,a0
+;;   lui a2,1
+;;   add a0,a0,a2
+;;   sub a4,zero,a3
+;;   not a2,a4
+;;   and a2,a0,a2
 ;;   sw a1,0(a2)
 ;;   j label1
 ;; block1:
@@ -60,19 +57,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a3,8(a1)
-;;   sltu a3,a3,a0
-;;   ld a4,0(a1)
-;;   add a4,a4,a0
-;;   lui a5,1
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a3
-;;   and a1,a5,a0
-;;   not a3,a0
-;;   and a5,a4,a3
-;;   or a1,a1,a5
-;;   lw a0,0(a1)
+;;   ld a2,8(a1)
+;;   sltu a2,a2,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   lui a1,1
+;;   add a0,a0,a1
+;;   sub a4,zero,a2
+;;   not a1,a4
+;;   and a2,a0,a1
+;;   lw a0,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 859bf515f..78a82b827 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,40 +41,34 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a4,8(a2)
-;;   sltu a4,a4,a0
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   lui a3,65535
-;;   slli a0,a3,4
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a3,zero,a4
-;;   and a2,a0,a3
-;;   not a4,a3
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   sw a1,0(a2)
+;;   ld a3,8(a2)
+;;   sltu a4,a3,a0
+;;   ld a2,0(a2)
+;;   add a3,a2,a0
+;;   lui a0,65535
+;;   slli a2,a0,4
+;;   add a3,a3,a2
+;;   sub a5,zero,a4
+;;   not a2,a5
+;;   and a3,a3,a2
+;;   sw a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a4,8(a1)
-;;   sltu a4,a4,a0
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lui a3,65535
-;;   slli a0,a3,4
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a1,zero,a4
-;;   and a2,a0,a1
-;;   not a4,a1
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   lw a0,0(a2)
+;;   ld a2,8(a1)
+;;   sltu a3,a2,a0
+;;   ld a1,0(a1)
+;;   add a2,a1,a0
+;;   lui a0,65535
+;;   slli a4,a0,4
+;;   add a2,a2,a4
+;;   sub a5,zero,a3
+;;   not a1,a5
+;;   and a3,a2,a1
+;;   lw a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index f07ab4fd0..8427fd5d3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,36 +41,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a3,8(a2)
-;;   sltu a3,a0,a3
-;;   xori a3,a3,1
-;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sb a1,0(a0)
+;;   ld a5,8(a2)
+;;   sltu a4,a0,a5
+;;   xori a3,a4,1
+;;   ld a5,0(a2)
+;;   add a5,a5,a0
+;;   sub a3,zero,a3
+;;   not a0,a3
+;;   and a2,a5,a0
+;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a2,8(a1)
-;;   sltu a2,a0,a2
-;;   xori a3,a2,1
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   lbu a0,0(a0)
+;;   ld a5,8(a1)
+;;   sltu a4,a0,a5
+;;   xori a2,a4,1
+;;   ld a5,0(a1)
+;;   add a5,a5,a0
+;;   sub a3,zero,a2
+;;   not a0,a3
+;;   and a1,a5,a0
+;;   lbu a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index a6025c9f4..c62abdfe2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -43,16 +43,13 @@
 ;; block0:
 ;;   ld a3,8(a2)
 ;;   sltu a3,a3,a0
-;;   ld a4,0(a2)
-;;   add a4,a4,a0
-;;   lui a5,1
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a3
-;;   and a2,a5,a0
-;;   not a3,a0
-;;   and a5,a4,a3
-;;   or a2,a2,a5
+;;   ld a2,0(a2)
+;;   add a0,a2,a0
+;;   lui a2,1
+;;   add a0,a0,a2
+;;   sub a4,zero,a3
+;;   not a2,a4
+;;   and a2,a0,a2
 ;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
@@ -60,19 +57,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a3,8(a1)
-;;   sltu a3,a3,a0
-;;   ld a4,0(a1)
-;;   add a4,a4,a0
-;;   lui a5,1
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a3
-;;   and a1,a5,a0
-;;   not a3,a0
-;;   and a5,a4,a3
-;;   or a1,a1,a5
-;;   lbu a0,0(a1)
+;;   ld a2,8(a1)
+;;   sltu a2,a2,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   lui a1,1
+;;   add a0,a0,a1
+;;   sub a4,zero,a2
+;;   not a1,a4
+;;   and a2,a0,a1
+;;   lbu a0,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index f145cd59b..d0ea46100 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,40 +41,34 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a4,8(a2)
-;;   sltu a4,a4,a0
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   lui a3,65535
-;;   slli a0,a3,4
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a3,zero,a4
-;;   and a2,a0,a3
-;;   not a4,a3
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   sb a1,0(a2)
+;;   ld a3,8(a2)
+;;   sltu a4,a3,a0
+;;   ld a2,0(a2)
+;;   add a3,a2,a0
+;;   lui a0,65535
+;;   slli a2,a0,4
+;;   add a3,a3,a2
+;;   sub a5,zero,a4
+;;   not a2,a5
+;;   and a3,a3,a2
+;;   sb a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a4,8(a1)
-;;   sltu a4,a4,a0
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lui a3,65535
-;;   slli a0,a3,4
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a1,zero,a4
-;;   and a2,a0,a1
-;;   not a4,a1
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   lbu a0,0(a2)
+;;   ld a2,8(a1)
+;;   sltu a3,a2,a0
+;;   ld a1,0(a1)
+;;   add a2,a1,a0
+;;   lui a0,65535
+;;   slli a4,a0,4
+;;   add a2,a2,a4
+;;   sub a5,zero,a3
+;;   not a1,a5
+;;   and a3,a2,a1
+;;   lbu a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 6c9f95e11..e2e3d0711 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,40 +39,34 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   lui a3,65536
-;;   addi a0,a3,-4
-;;   sltu a0,a0,a5
-;;   ld a4,0(a2)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   sw a1,0(a2)
+;;   slli a0,a0,32
+;;   srli a3,a0,32
+;;   lui a0,65536
+;;   addi a4,a0,-4
+;;   sltu a4,a4,a3
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   sub a5,zero,a4
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sw a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   lui a3,65536
-;;   addi a0,a3,-4
-;;   sltu a0,a0,a5
-;;   ld a4,0(a1)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   lw a0,0(a2)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   lui a0,65536
+;;   addi a3,a0,-4
+;;   sltu a3,a3,a2
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   sub a5,zero,a3
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lw a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index eb11c6b63..701c8583f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -39,44 +39,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a3,a5,32
-;;   lui a5,65535
-;;   addi a4,a5,-4
-;;   sltu a0,a4,a3
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a3,1
-;;   add a2,a2,a3
-;;   li a3,0
-;;   sub a5,zero,a0
-;;   and a4,a3,a5
-;;   not a0,a5
-;;   and a2,a2,a0
-;;   or a4,a4,a2
-;;   sw a1,0(a4)
+;;   slli a3,a0,32
+;;   srli a4,a3,32
+;;   lui a3,65535
+;;   addi a5,a3,-4
+;;   sltu a3,a5,a4
+;;   ld a5,0(a2)
+;;   add a4,a5,a4
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a2,zero,a3
+;;   not a3,a2
+;;   and a5,a4,a3
+;;   sw a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a2,a5,32
-;;   lui a5,65535
-;;   addi a3,a5,-4
-;;   sltu a0,a3,a2
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   lui a2,1
-;;   add a1,a1,a2
-;;   li a2,0
-;;   sub a3,zero,a0
-;;   and a4,a2,a3
-;;   not a0,a3
-;;   and a2,a1,a0
-;;   or a4,a4,a2
-;;   lw a0,0(a4)
+;;   slli a2,a0,32
+;;   srli a4,a2,32
+;;   lui a2,65535
+;;   addi a5,a2,-4
+;;   sltu a3,a5,a4
+;;   ld a5,0(a1)
+;;   add a4,a5,a4
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a1,zero,a3
+;;   not a3,a1
+;;   and a5,a4,a3
+;;   lw a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 27e8e0ab9..b433aef1c 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -39,40 +39,34 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   lui a3,65536
-;;   addi a0,a3,-1
-;;   sltu a0,a0,a5
-;;   ld a4,0(a2)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   sb a1,0(a2)
+;;   slli a0,a0,32
+;;   srli a3,a0,32
+;;   lui a0,65536
+;;   addi a4,a0,-1
+;;   sltu a4,a4,a3
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   sub a5,zero,a4
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sb a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a5,a3,32
-;;   lui a3,65536
-;;   addi a0,a3,-1
-;;   sltu a0,a0,a5
-;;   ld a4,0(a1)
-;;   add a4,a4,a5
-;;   li a5,0
-;;   sub a0,zero,a0
-;;   and a2,a5,a0
-;;   not a5,a0
-;;   and a0,a4,a5
-;;   or a2,a2,a0
-;;   lbu a0,0(a2)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   lui a0,65536
+;;   addi a3,a0,-1
+;;   sltu a3,a3,a2
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   sub a5,zero,a3
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lbu a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index dda7c67f2..3fec46bd4 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -39,44 +39,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a3,a5,32
-;;   lui a5,65535
-;;   addi a4,a5,-1
-;;   sltu a0,a4,a3
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a3,1
-;;   add a2,a2,a3
-;;   li a3,0
-;;   sub a5,zero,a0
-;;   and a4,a3,a5
-;;   not a0,a5
-;;   and a2,a2,a0
-;;   or a4,a4,a2
-;;   sb a1,0(a4)
+;;   slli a3,a0,32
+;;   srli a4,a3,32
+;;   lui a3,65535
+;;   addi a5,a3,-1
+;;   sltu a3,a5,a4
+;;   ld a5,0(a2)
+;;   add a4,a5,a4
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a2,zero,a3
+;;   not a3,a2
+;;   and a5,a4,a3
+;;   sb a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a2,a5,32
-;;   lui a5,65535
-;;   addi a3,a5,-1
-;;   sltu a0,a3,a2
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   lui a2,1
-;;   add a1,a1,a2
-;;   li a2,0
-;;   sub a3,zero,a0
-;;   and a4,a2,a3
-;;   not a0,a3
-;;   and a2,a1,a0
-;;   or a4,a4,a2
-;;   lbu a0,0(a4)
+;;   slli a2,a0,32
+;;   srli a4,a2,32
+;;   lui a2,65535
+;;   addi a5,a2,-1
+;;   sltu a3,a5,a4
+;;   ld a5,0(a1)
+;;   add a4,a5,a4
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   sub a1,zero,a3
+;;   not a3,a1
+;;   and a5,a4,a3
+;;   lbu a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 750ec5218..f37b13a2a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,36 +39,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a3,65536
-;;   addi a3,a3,-4
-;;   sltu a3,a3,a0
+;;   lui a4,65536
+;;   addi a3,a4,-4
+;;   sltu a5,a3,a0
 ;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sw a1,0(a0)
+;;   add a0,a2,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a2,a0,a5
+;;   sw a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a2,65536
-;;   addi a3,a2,-4
-;;   sltu a3,a3,a0
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   lw a0,0(a0)
+;;   lui a4,65536
+;;   addi a2,a4,-4
+;;   sltu a5,a2,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a1,a0,a5
+;;   lw a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index fd8115156..5dc39b67c 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -40,39 +40,33 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,-4
-;;   sltu a4,a5,a0
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a3,zero,a4
-;;   and a2,a0,a3
-;;   not a4,a3
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   sw a1,0(a2)
+;;   addi a3,a3,-4
+;;   sltu a3,a3,a0
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   sub a5,zero,a3
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sw a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a3,65535
-;;   addi a5,a3,-4
-;;   sltu a4,a5,a0
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a1,zero,a4
-;;   and a2,a0,a1
-;;   not a4,a1
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   lw a0,0(a2)
+;;   lui a2,65535
+;;   addi a2,a2,-4
+;;   sltu a2,a2,a0
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   lui a3,1
+;;   add a1,a1,a3
+;;   sub a5,zero,a2
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lw a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index f1c507233..448eeda62 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -39,36 +39,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a3,65536
-;;   addi a3,a3,-1
-;;   sltu a3,a3,a0
+;;   lui a4,65536
+;;   addi a3,a4,-1
+;;   sltu a5,a3,a0
 ;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sb a1,0(a0)
+;;   add a0,a2,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a2,a0,a5
+;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a2,65536
-;;   addi a3,a2,-1
-;;   sltu a3,a3,a0
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   lbu a0,0(a0)
+;;   lui a4,65536
+;;   addi a2,a4,-1
+;;   sltu a5,a2,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a1,a0,a5
+;;   lbu a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 724f21d94..7d9c18675 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -40,39 +40,33 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,-1
-;;   sltu a4,a5,a0
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a3,zero,a4
-;;   and a2,a0,a3
-;;   not a4,a3
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   sb a1,0(a2)
+;;   addi a3,a3,-1
+;;   sltu a3,a3,a0
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   sub a5,zero,a3
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sb a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a3,65535
-;;   addi a5,a3,-1
-;;   sltu a4,a5,a0
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a1,zero,a4
-;;   and a2,a0,a1
-;;   not a4,a1
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   lbu a0,0(a2)
+;;   lui a2,65535
+;;   addi a2,a2,-1
+;;   sltu a2,a2,a0
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   lui a3,1
+;;   add a1,a1,a3
+;;   sub a5,zero,a2
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lbu a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 50f72079b..2afdc5493 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,36 +39,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a3,65536
-;;   addi a3,a3,-4
-;;   sltu a3,a3,a0
+;;   lui a4,65536
+;;   addi a3,a4,-4
+;;   sltu a5,a3,a0
 ;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sw a1,0(a0)
+;;   add a0,a2,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a2,a0,a5
+;;   sw a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a2,65536
-;;   addi a3,a2,-4
-;;   sltu a3,a3,a0
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   lw a0,0(a0)
+;;   lui a4,65536
+;;   addi a2,a4,-4
+;;   sltu a5,a2,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a1,a0,a5
+;;   lw a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 0a91b43fc..968522c1f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -40,39 +40,33 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,-4
-;;   sltu a4,a5,a0
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a3,zero,a4
-;;   and a2,a0,a3
-;;   not a4,a3
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   sw a1,0(a2)
+;;   addi a3,a3,-4
+;;   sltu a3,a3,a0
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   sub a5,zero,a3
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sw a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a3,65535
-;;   addi a5,a3,-4
-;;   sltu a4,a5,a0
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a1,zero,a4
-;;   and a2,a0,a1
-;;   not a4,a1
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   lw a0,0(a2)
+;;   lui a2,65535
+;;   addi a2,a2,-4
+;;   sltu a2,a2,a0
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   lui a3,1
+;;   add a1,a1,a3
+;;   sub a5,zero,a2
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lw a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 522b63438..1d75bcf2d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -39,36 +39,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a3,65536
-;;   addi a3,a3,-1
-;;   sltu a3,a3,a0
+;;   lui a4,65536
+;;   addi a3,a4,-1
+;;   sltu a5,a3,a0
 ;;   ld a2,0(a2)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   sb a1,0(a0)
+;;   add a0,a2,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a2,a0,a5
+;;   sb a1,0(a2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a2,65536
-;;   addi a3,a2,-1
-;;   sltu a3,a3,a0
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
-;;   li a4,0
-;;   sub a5,zero,a3
-;;   and a0,a4,a5
-;;   not a3,a5
-;;   and a4,a2,a3
-;;   or a0,a0,a4
-;;   lbu a0,0(a0)
+;;   lui a4,65536
+;;   addi a2,a4,-1
+;;   sltu a5,a2,a0
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   sub a3,zero,a5
+;;   not a5,a3
+;;   and a1,a0,a5
+;;   lbu a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 51445a070..92c31e019 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -40,39 +40,33 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,-1
-;;   sltu a4,a5,a0
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a3,zero,a4
-;;   and a2,a0,a3
-;;   not a4,a3
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   sb a1,0(a2)
+;;   addi a3,a3,-1
+;;   sltu a3,a3,a0
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   sub a5,zero,a3
+;;   not a3,a5
+;;   and a3,a2,a3
+;;   sb a1,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a3,65535
-;;   addi a5,a3,-1
-;;   sltu a4,a5,a0
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lui a0,1
-;;   add a5,a5,a0
-;;   li a0,0
-;;   sub a1,zero,a4
-;;   and a2,a0,a1
-;;   not a4,a1
-;;   and a0,a5,a4
-;;   or a2,a2,a0
-;;   lbu a0,0(a2)
+;;   lui a2,65535
+;;   addi a2,a2,-1
+;;   sltu a2,a2,a0
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   lui a3,1
+;;   add a1,a1,a3
+;;   sub a5,zero,a2
+;;   not a2,a5
+;;   and a3,a1,a2
+;;   lbu a0,0(a3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/zbb.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/zbb.wat
new file mode 100644
index 000000000..ed51298d7
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/zbb.wat
@@ -0,0 +1,79 @@
+;;! target = "riscv64"
+;;! compile = true
+;;! settings = ["has_zbb", "opt_level=speed"]
+
+(module
+  (func (export "rolw") (param i32 i32) (result i32)
+    (i32.rotl (local.get 0) (local.get 1)))
+  (func (export "rol") (param i64 i64) (result i64)
+    (i64.rotl (local.get 0) (local.get 1)))
+  (func (export "rolwi") (param i32 ) (result i32)
+    (i32.rotl (local.get 0) (i32.const 100)))
+  (func (export "roli") (param i64) (result i64)
+    (i64.rotl (local.get 0) (i64.const 40)))
+
+  (func (export "rorw") (param i32 i32) (result i32)
+    (i32.rotr (local.get 0) (local.get 1)))
+  (func (export "ror") (param i64 i64) (result i64)
+    (i64.rotr (local.get 0) (local.get 1)))
+  (func (export "rorwi") (param i32 ) (result i32)
+    (i32.rotr (local.get 0) (i32.const 100)))
+  (func (export "rori") (param i64) (result i64)
+    (i64.rotr (local.get 0) (i64.const 40)))
+)
+
+;; function u0:0:
+;; block0:
+;;   j label1
+;; block1:
+;;   rolw a0,a0,a1
+;;   ret
+;;
+;; function u0:1:
+;; block0:
+;;   j label1
+;; block1:
+;;   rol a0,a0,a1
+;;   ret
+;;
+;; function u0:2:
+;; block0:
+;;   j label1
+;; block1:
+;;   roriw a0,a0,28
+;;   ret
+;;
+;; function u0:3:
+;; block0:
+;;   j label1
+;; block1:
+;;   rori a0,a0,24
+;;   ret
+;;
+;; function u0:4:
+;; block0:
+;;   j label1
+;; block1:
+;;   rorw a0,a0,a1
+;;   ret
+;;
+;; function u0:5:
+;; block0:
+;;   j label1
+;; block1:
+;;   ror a0,a0,a1
+;;   ret
+;;
+;; function u0:6:
+;; block0:
+;;   j label1
+;; block1:
+;;   roriw a0,a0,100
+;;   ret
+;;
+;; function u0:7:
+;; block0:
+;;   j label1
+;; block1:
+;;   rori a0,a0,40
+;;   ret
diff --git a/cranelift/filetests/filetests/wasm/byteswap.wat b/cranelift/filetests/filetests/wasm/byteswap.wat
new file mode 100644
index 000000000..de5b51985
--- /dev/null
+++ b/cranelift/filetests/filetests/wasm/byteswap.wat
@@ -0,0 +1,93 @@
+;;! target = "x86_64"
+;;! optimize = true
+;;! settings = ["opt_level=speed"]
+
+(module
+  (func (export "bswap32") (param i32) (result i32)
+    local.get 0
+    i32.const 24
+    i32.shl
+    local.get 0
+    i32.const 65280
+    i32.and
+    i32.const 8
+    i32.shl
+    i32.or
+    local.get 0
+    i32.const 8
+    i32.shr_u
+    i32.const 65280
+    i32.and
+    local.get 0
+    i32.const 24
+    i32.shr_u
+    i32.or
+    i32.or
+  )
+
+  (func (export "bswap64") (param i64) (result i64)
+    local.get 0
+    i64.const 56
+    i64.shl
+    local.get 0
+    i64.const 65280
+    i64.and
+    i64.const 40
+    i64.shl
+    i64.or
+    local.get 0
+    i64.const 16711680
+    i64.and
+    i64.const 24
+    i64.shl
+    local.get 0
+    i64.const 4278190080
+    i64.and
+    i64.const 8
+    i64.shl
+    i64.or
+    i64.or
+    local.get 0
+    i64.const 8
+    i64.shr_u
+    i64.const 4278190080
+    i64.and
+    local.get 0
+    i64.const 24
+    i64.shr_u
+    i64.const 16711680
+    i64.and
+    i64.or
+    local.get 0
+    i64.const 40
+    i64.shr_u
+    i64.const 65280
+    i64.and
+    local.get 0
+    i64.const 56
+    i64.shr_u
+    i64.or
+    i64.or
+    i64.or
+  )
+)
+
+;; function u0:0(i32, i64 vmctx) -> i32 fast {
+;;                                 block0(v0: i32, v1: i64):
+;; @0057                               jump block1
+;;
+;;                                 block1:
+;;                                     v18 = bswap.i32 v0
+;;                                     v19 -> v18
+;; @0057                               return v18
+;; }
+;;
+;; function u0:1(i64, i64 vmctx) -> i64 fast {
+;;                                 block0(v0: i64, v1: i64):
+;; @00ad                               jump block1
+;;
+;;                                 block1:
+;;                                     v38 = bswap.i64 v0
+;;                                     v39 -> v38
+;; @00ad                               return v38
+;; }
diff --git a/tests/all/cli_tests.rs b/tests/all/cli_tests.rs
index a114e2a3e..997738cdd 100644
--- a/tests/all/cli_tests.rs
+++ b/tests/all/cli_tests.rs
@@ -32,7 +32,7 @@ pub fn get_wasmtime_command() -> Result<Command> {
     // If we're running tests with a "runner" then we might be doing something
     // like cross-emulation, so spin up the emulator rather than the tests
     // itself, which may not be natively executable.
-    let mut cmd = if let Some((_, runner)) = runner {
+    let cmd = if let Some((_, runner)) = runner {
         let mut parts = runner.split_whitespace();
         let mut cmd = Command::new(parts.next().unwrap());
         for arg in parts {
@@ -44,10 +44,6 @@ pub fn get_wasmtime_command() -> Result<Command> {
         Command::new(&me)
     };
 
-    if let Ok(val) = std::env::var("WASMTIME_LOG") {
-        cmd.env("WASMTIME_LOG", val);
-    }
-
     Ok(cmd)
 }
 
diff --git a/tests/all/fuel.rs b/tests/all/fuel.rs
index c3f300d09..df046763c 100644
--- a/tests/all/fuel.rs
+++ b/tests/all/fuel.rs
@@ -143,6 +143,14 @@ fn manual_fuel() {
     assert_eq!(store.consume_fuel(1).unwrap(), 0);
     assert_eq!(store.consume_fuel(0).unwrap(), 0);
     assert_eq!(store.fuel_remaining(), Some(0));
+    store.add_fuel(5_000).unwrap();
+    assert_eq!(store.fuel_consumed(), Some(10_000));
+    assert_eq!(store.consume_fuel(2_500).unwrap(), 2_500);
+    assert_eq!(store.fuel_consumed(), Some(12_500));
+    store.reset_fuel(5_000).unwrap();
+    assert_eq!(store.fuel_consumed(), Some(0));
+    assert_eq!(store.consume_fuel(2_500).unwrap(), 2_500);
+    assert_eq!(store.fuel_consumed(), Some(2_500));
 }
 
 #[test]
@@ -168,7 +176,9 @@ fn host_function_consumes_all() {
     store.add_fuel(FUEL).unwrap();
     let func = Func::wrap(&mut store, |mut caller: Caller<'_, ()>| {
         let consumed = caller.fuel_consumed().unwrap();
-        assert_eq!(caller.consume_fuel((FUEL - consumed) - 1).unwrap(), 1);
+        let remaining = caller.fuel_remaining().unwrap();
+        assert_eq!(remaining, FUEL - consumed);
+        assert_eq!(caller.consume_fuel(remaining - 1).unwrap(), 1);
     });
 
     let instance = Instance::new(&mut store, &module, &[func.into()]).unwrap();