Repository: probe-rs/probe-rs
Pull request #2636 (2024-07-05 09:29:05)

Remove hardcoded BinaryFormat from target descriptors
If we ever end up having vendor-specific image formats, we can't hard-code them into the target YAMLs. Instead, we store their names and validate it as part of the builtin target validation.

This PR also removes a deprecated alias that was used by the VSCode plugin.

---

The end goal is to split up format and platform support. The plan is to keep a hard-coded set of formats, and an extensible set of platforms - "raw" and IDF being the first two of these platforms. Targets may declare a default platform, but the default image format should be dictated by the platform - and right now both should default to `Elf`.

The platform support code would receive something analogous to the current `Format`, file reader/path, `FlashLoader` and `Session`. "raw" would just load the image to `FlashLoader`, while IDF would process it as it wants.

The difficult bits are integrating a dynamic set of platforms with the binary, which requires clap and serde implementations with good UX in mind.

This PR is just the first step, that removes one point where the IDF platform was hard-coded into prob-rs.


Patch:
diff --git a/probe-rs-target/src/chip.rs b/probe-rs-target/src/chip.rs
index 12b54cf2..c0e9588a 100644
--- a/probe-rs-target/src/chip.rs
+++ b/probe-rs-target/src/chip.rs
@@ -16,17 +16,6 @@ pub struct ScanChainElement {
     pub ir_len: Option<u8>,
 }
 
-/// A finite list of all possible binary formats a target might support.
-#[derive(Debug, Default, Serialize, Deserialize, PartialEq, Eq, Clone)]
-#[serde(rename_all = "lowercase")]
-pub enum BinaryFormat {
-    /// Program sections are bit-for-bit copied to flash.
-    #[default]
-    Raw,
-    /// Program sections are copied to flash, with the relevant headers and metadata for the [ESP-IDF bootloader](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html#app-image-structures).
-    Idf,
-}
-
 /// Configuration for JTAG probes.
 #[derive(Debug, Clone, Serialize, Deserialize, PartialEq)]
 pub struct Jtag {
@@ -89,7 +78,9 @@ pub struct Chip {
     #[serde(default)]
     pub jtag: Option<Jtag>,
     /// The default binary format for this chip
-    pub default_binary_format: Option<BinaryFormat>,
+    // TODO: rename to default_platform
+    #[serde(default)]
+    pub default_binary_format: Option<String>,
 }
 
 impl Chip {
@@ -111,7 +102,7 @@ impl Chip {
             flash_algorithms: vec![],
             rtt_scan_ranges: None,
             jtag: None,
-            default_binary_format: Some(BinaryFormat::Raw),
+            default_binary_format: None,
         }
     }
 }
diff --git a/probe-rs-target/src/lib.rs b/probe-rs-target/src/lib.rs
index cca40435..da84405f 100644
--- a/probe-rs-target/src/lib.rs
+++ b/probe-rs-target/src/lib.rs
@@ -19,8 +19,8 @@ mod memory;
 pub(crate) mod serialize;
 
 pub use chip::{
-    ArmCoreAccessOptions, BinaryFormat, Chip, Core, CoreAccessOptions, Jtag,
-    RiscvCoreAccessOptions, ScanChainElement, XtensaCoreAccessOptions,
+    ArmCoreAccessOptions, Chip, Core, CoreAccessOptions, Jtag, RiscvCoreAccessOptions,
+    ScanChainElement, XtensaCoreAccessOptions,
 };
 pub use chip_family::{
     Architecture, ChipFamily, CoreType, InstructionSet, TargetDescriptionSource,
diff --git a/probe-rs-tools/src/bin/probe-rs/main.rs b/probe-rs-tools/src/bin/probe-rs/main.rs
index 9a4d8d11..597dbebb 100644
--- a/probe-rs-tools/src/bin/probe-rs/main.rs
+++ b/probe-rs-tools/src/bin/probe-rs/main.rs
@@ -12,12 +12,11 @@ use anyhow::{Context, Result};
 use clap::Parser;
 use colored::Colorize;
 use itertools::Itertools;
-use probe_rs::flashing::{BinOptions, Format, IdfOptions};
+use probe_rs::flashing::{BinOptions, Format, FormatKind, IdfOptions};
 use probe_rs::{probe::list::Lister, Target};
 use report::Report;
+use serde::Deserialize;
 use serde::Serialize;
-use serde::{de::Error, Deserialize, Deserializer};
-use serde_json::Value;
 use time::{OffsetDateTime, UtcOffset};
 
 use crate::util::logging::setup_logging;
@@ -105,15 +104,26 @@ pub(crate) struct CoreOptions {
     core: usize,
 }
 
-/// A helper function to deserialize a default [`Format`] from a string.
-fn format_from_str<'de, D: Deserializer<'de>>(deserializer: D) -> Result<Option<Format>, D::Error> {
-    match Value::deserialize(deserializer)? {
-        Value::String(s) => match Format::from_str(s.as_str()) {
-            Ok(format) => Ok(Some(format)),
-            Err(e) => Err(D::Error::custom(e)),
-        },
-        _ => Ok(None),
-    }
+#[derive(clap::Parser, Clone, Serialize, Deserialize, Debug, Default)]
+#[serde(default)]
+pub struct BinaryCliOptions {
+    /// The address in memory where the binary will be put at. This is only considered when `bin` is selected as the format.
+    #[clap(long, value_parser = parse_u64, help_heading = "DOWNLOAD CONFIGURATION")]
+    base_address: Option<u64>,
+    /// The number of bytes to skip at the start of the binary file. This is only considered when `bin` is selected as the format.
+    #[clap(long, value_parser = parse_u32, default_value = "0", help_heading = "DOWNLOAD CONFIGURATION")]
+    skip: u32,
+}
+
+#[derive(clap::Parser, Clone, Serialize, Deserialize, Debug, Default)]
+#[serde(default)]
+pub struct IdfCliOptions {
+    /// The idf bootloader path
+    #[clap(long, help_heading = "DOWNLOAD CONFIGURATION")]
+    idf_bootloader: Option<PathBuf>,
+    /// The idf partition table path
+    #[clap(long, help_heading = "DOWNLOAD CONFIGURATION")]
+    idf_partition_table: Option<PathBuf>,
 }
 
 #[derive(clap::Parser, Clone, Serialize, Deserialize, Debug, Default)]
@@ -128,21 +138,13 @@ pub struct FormatOptions {
         long,
         help_heading = "DOWNLOAD CONFIGURATION"
     )]
-    // TODO: remove this alias in the next release after 0.24 and release of https://github.com/probe-rs/vscode/pull/86
-    #[serde(deserialize_with = "format_from_str", alias = "format")]
-    binary_format: Option<Format>,
-    /// The address in memory where the binary will be put at. This is only considered when `bin` is selected as the format.
-    #[clap(long, value_parser = parse_u64, help_heading = "DOWNLOAD CONFIGURATION")]
-    pub base_address: Option<u64>,
-    /// The number of bytes to skip at the start of the binary file. This is only considered when `bin` is selected as the format.
-    #[clap(long, value_parser = parse_u32, default_value = "0", help_heading = "DOWNLOAD CONFIGURATION")]
-    pub skip: u32,
-    /// The idf bootloader path
-    #[clap(long, help_heading = "DOWNLOAD CONFIGURATION")]
-    pub idf_bootloader: Option<PathBuf>,
-    /// The idf partition table path
-    #[clap(long, help_heading = "DOWNLOAD CONFIGURATION")]
-    pub idf_partition_table: Option<PathBuf>,
+    binary_format: Option<FormatKind>,
+
+    #[clap(flatten)]
+    bin_options: BinaryCliOptions,
+
+    #[clap(flatten)]
+    idf_options: IdfCliOptions,
 }
 
 impl FormatOptions {
@@ -150,25 +152,23 @@ impl FormatOptions {
     /// If a target has a preferred format, we use that.
     /// Finally, if neither of the above cases are true, we default to [`Format::default()`].
     pub fn into_format(self, target: &Target) -> Format {
-        let format = self
-            .binary_format
-            .unwrap_or_else(|| match target.default_format {
-                probe_rs_target::BinaryFormat::Idf => Format::Idf(Default::default()),
-                probe_rs_target::BinaryFormat::Raw => Default::default(),
-            });
+        let format = self.binary_format.unwrap_or_else(|| {
+            FormatKind::from_optional(target.default_format.as_deref())
+                .expect("Failed to parse a default binary format. This shouldn't happen.")
+        });
 
         match format {
-            Format::Bin(_) => Format::Bin(BinOptions {
-                base_address: self.base_address,
-                skip: self.skip,
+            FormatKind::Bin => Format::Bin(BinOptions {
+                base_address: self.bin_options.base_address,
+                skip: self.bin_options.skip,
             }),
-            Format::Hex => Format::Hex,
-            Format::Elf => Format::Elf,
-            Format::Idf(_) => Format::Idf(IdfOptions {
-                bootloader: self.idf_bootloader,
-                partition_table: self.idf_partition_table,
+            FormatKind::Hex => Format::Hex,
+            FormatKind::Elf => Format::Elf,
+            FormatKind::Uf2 => Format::Uf2,
+            FormatKind::Idf => Format::Idf(IdfOptions {
+                bootloader: self.idf_options.idf_bootloader,
+                partition_table: self.idf_options.idf_partition_table,
             }),
-            Format::Uf2 => Format::Uf2,
         }
     }
 }
@@ -265,7 +265,7 @@ fn main() -> Result<()> {
     if let Some(format_arg_pos) = args.iter().position(|arg| arg == "--format") {
         if let Some(format_arg) = args.get(format_arg_pos + 1) {
             if let Some(format_arg) = format_arg.to_str() {
-                if Format::from_str(format_arg).is_ok() {
+                if FormatKind::from_str(format_arg).is_ok() {
                     anyhow::bail!("--format has been renamed to --binary-format. Please use --binary-format {0} instead of --format {0}", format_arg);
                 }
             }
diff --git a/probe-rs/src/architecture/arm/communication_interface.rs b/probe-rs/src/architecture/arm/communication_interface.rs
index c6a84d2d..19f63a36 100644
--- a/probe-rs/src/architecture/arm/communication_interface.rs
+++ b/probe-rs/src/architecture/arm/communication_interface.rs
@@ -7,10 +7,7 @@ use super::{
         Abort, Ctrl, DebugPortError, DebugPortId, DebugPortVersion, DpAccess, Select, BASEPTR0,
         BASEPTR1, DPIDR, DPIDR1,
     },
-    memory::{
-        adi_v5_memory_interface::{ADIMemoryInterface, ArmMemoryInterface},
-        Component,
-    },
+    memory::{adi_v5_memory_interface::ADIMemoryInterface, ArmMemoryInterface, Component},
     sequences::{ArmDebugSequence, DefaultArmSequence},
     ArmError, DapAccess, DpAddress, FullyQualifiedApAddress, PortType, RawDapAccess, SwoAccess,
     SwoConfig,
diff --git a/probe-rs/src/architecture/arm/core/armv6m.rs b/probe-rs/src/architecture/arm/core/armv6m.rs
index 105741c5..9773e366 100644
--- a/probe-rs/src/architecture/arm/core/armv6m.rs
+++ b/probe-rs/src/architecture/arm/core/armv6m.rs
@@ -2,9 +2,7 @@
 
 use super::{registers::cortex_m::*, CortexMState, Dfsr};
 use crate::{
-    architecture::arm::{
-        memory::adi_v5_memory_interface::ArmMemoryInterface, sequences::ArmDebugSequence, ArmError,
-    },
+    architecture::arm::{memory::ArmMemoryInterface, sequences::ArmDebugSequence, ArmError},
     core::{CoreRegisters, RegisterId, RegisterValue, VectorCatchCondition},
     error::Error,
     memory::valid_32bit_address,
diff --git a/probe-rs/src/architecture/arm/core/armv7a.rs b/probe-rs/src/architecture/arm/core/armv7a.rs
index 526e3ed1..28df15bc 100644
--- a/probe-rs/src/architecture/arm/core/armv7a.rs
+++ b/probe-rs/src/architecture/arm/core/armv7a.rs
@@ -16,8 +16,8 @@ use super::{
 };
 use crate::{
     architecture::arm::{
-        core::armv7a_debug_regs::*, memory::adi_v5_memory_interface::ArmMemoryInterface,
-        sequences::ArmDebugSequence, ArmError,
+        core::armv7a_debug_regs::*, memory::ArmMemoryInterface, sequences::ArmDebugSequence,
+        ArmError,
     },
     core::{CoreRegisters, MemoryMappedRegister, RegisterId, RegisterValue},
     error::Error,
diff --git a/probe-rs/src/architecture/arm/core/armv7m.rs b/probe-rs/src/architecture/arm/core/armv7m.rs
index f26f4aad..5df050c1 100644
--- a/probe-rs/src/architecture/arm/core/armv7m.rs
+++ b/probe-rs/src/architecture/arm/core/armv7m.rs
@@ -9,8 +9,8 @@ use super::{
 };
 use crate::{
     architecture::arm::{
-        core::registers::cortex_m::XPSR, memory::adi_v5_memory_interface::ArmMemoryInterface,
-        sequences::ArmDebugSequence, ArmError,
+        core::registers::cortex_m::XPSR, memory::ArmMemoryInterface, sequences::ArmDebugSequence,
+        ArmError,
     },
     core::{
         Architecture, CoreInformation, CoreInterface, CoreRegisters, CoreStatus, HaltReason,
diff --git a/probe-rs/src/architecture/arm/core/armv8a.rs b/probe-rs/src/architecture/arm/core/armv8a.rs
index ef4b2da7..20aa53ee 100644
--- a/probe-rs/src/architecture/arm/core/armv8a.rs
+++ b/probe-rs/src/architecture/arm/core/armv8a.rs
@@ -10,8 +10,8 @@ use super::{
 };
 use crate::{
     architecture::arm::{
-        core::armv8a_debug_regs::*, memory::adi_v5_memory_interface::ArmMemoryInterface,
-        sequences::ArmDebugSequence, ArmError,
+        core::armv8a_debug_regs::*, memory::ArmMemoryInterface, sequences::ArmDebugSequence,
+        ArmError,
     },
     core::{
         memory_mapped_registers::MemoryMappedRegister, CoreRegisters, RegisterId, RegisterValue,
diff --git a/probe-rs/src/architecture/arm/core/armv8m.rs b/probe-rs/src/architecture/arm/core/armv8m.rs
index 59a1652d..6a016d74 100644
--- a/probe-rs/src/architecture/arm/core/armv8m.rs
+++ b/probe-rs/src/architecture/arm/core/armv8m.rs
@@ -9,8 +9,8 @@ use super::{
 };
 use crate::{
     architecture::arm::{
-        core::registers::cortex_m::XPSR, memory::adi_v5_memory_interface::ArmMemoryInterface,
-        sequences::ArmDebugSequence, ArmError,
+        core::registers::cortex_m::XPSR, memory::ArmMemoryInterface, sequences::ArmDebugSequence,
+        ArmError,
     },
     core::{CoreRegisters, RegisterId, RegisterValue, VectorCatchCondition},
     error::Error,
diff --git a/probe-rs/src/architecture/arm/core/cortex_m.rs b/probe-rs/src/architecture/arm/core/cortex_m.rs
index ae576224..f81d73f3 100644
--- a/probe-rs/src/architecture/arm/core/cortex_m.rs
+++ b/probe-rs/src/architecture/arm/core/cortex_m.rs
@@ -1,7 +1,7 @@
 //! Common functions and data types for Cortex-M core variants
 
 use crate::{
-    architecture::arm::{memory::adi_v5_memory_interface::ArmMemoryInterface, ArmError},
+    architecture::arm::{memory::ArmMemoryInterface, ArmError},
     core::RegisterId,
     memory_mapped_bitfield_register,
     semihosting::decode_semihosting_syscall,
diff --git a/probe-rs/src/architecture/arm/core/mod.rs b/probe-rs/src/architecture/arm/core/mod.rs
index e27027de..0f727a26 100644
--- a/probe-rs/src/architecture/arm/core/mod.rs
+++ b/probe-rs/src/architecture/arm/core/mod.rs
@@ -8,7 +8,7 @@ use crate::{
     SemihostingCommand,
 };
 
-use super::memory::adi_v5_memory_interface::ArmMemoryInterface;
+use super::memory::ArmMemoryInterface;
 
 pub mod armv6m;
 pub mod armv7a;
diff --git a/probe-rs/src/architecture/arm/memory/adi_v5_memory_interface.rs b/probe-rs/src/architecture/arm/memory/adi_v5_memory_interface.rs
index 81d3124f..7051e210 100644
--- a/probe-rs/src/architecture/arm/memory/adi_v5_memory_interface.rs
+++ b/probe-rs/src/architecture/arm/memory/adi_v5_memory_interface.rs
@@ -4,31 +4,12 @@ use super::super::ap::{
 };
 use crate::architecture::arm::communication_interface::{FlushableArmAccess, SwdSequence};
 use crate::architecture::arm::{
-    communication_interface::Initialized, dp::DpAccess, MemoryApInformation,
+    communication_interface::Initialized, dp::DpAccess, memory::ArmMemoryInterface,
+    MemoryApInformation,
 };
 use crate::architecture::arm::{ArmCommunicationInterface, ArmError};
+use crate::probe::DebugProbeError;
 use crate::MemoryInterface;
-use crate::{probe::DebugProbeError, CoreStatus};
-
-pub trait ArmMemoryInterface: SwdSequence + MemoryInterface<ArmError> {
-    /// Returns the underlying [`MemoryAp`].
-    fn ap(&mut self) -> MemoryAp;
-
-    fn get_arm_communication_interface(
-        &mut self,
-    ) -> Result<&mut ArmCommunicationInterface<Initialized>, DebugProbeError>;
-
-    /// Inform the probe of the [`CoreStatus`] of the chip/core attached to
-    /// the probe.
-    //
-    // NOTE: this function should be infallible as it is usually only
-    // a visual indication.
-    fn update_core_status(&mut self, state: CoreStatus) {
-        self.get_arm_communication_interface()
-            .map(|iface| iface.core_status_notification(state))
-            .ok();
-    }
-}
 
 /// Calculate the maximum number of bytes we can write starting at address
 /// before we run into the 10-bit TAR autoincrement limit.
diff --git a/probe-rs/src/architecture/arm/memory/mod.rs b/probe-rs/src/architecture/arm/memory/mod.rs
index 82198708..fd155691 100644
--- a/probe-rs/src/architecture/arm/memory/mod.rs
+++ b/probe-rs/src/architecture/arm/memory/mod.rs
@@ -3,5 +3,33 @@
 pub(crate) mod adi_v5_memory_interface;
 pub mod romtable;
 
-use super::ap::AccessPortError;
+use crate::{memory::MemoryInterface, probe::DebugProbeError, CoreStatus};
+
+use super::{
+    ap::memory_ap::MemoryAp,
+    communication_interface::{Initialized, SwdSequence},
+    ArmCommunicationInterface, ArmError,
+};
 pub use romtable::{Component, ComponentId, CoresightComponent, PeripheralType};
+
+/// An ArmMemoryInterface (ArmProbeInterface + MemoryAp)
+pub trait ArmMemoryInterface: SwdSequence + MemoryInterface<ArmError> {
+    /// The underlying MemoryAp.
+    fn ap(&mut self) -> MemoryAp;
+
+    /// The underlying `ArmCommunicationInterface` if this is an `ArmCommunicationInterface`.
+    fn get_arm_communication_interface(
+        &mut self,
+    ) -> Result<&mut ArmCommunicationInterface<Initialized>, DebugProbeError>;
+
+    /// Inform the probe of the [`CoreStatus`] of the chip/core attached to
+    /// the probe.
+    //
+    // NOTE: this function should be infallible as it is usually only
+    // a visual indication.
+    fn update_core_status(&mut self, state: CoreStatus) {
+        self.get_arm_communication_interface()
+            .map(|iface| iface.core_status_notification(state))
+            .ok();
+    }
+}
diff --git a/probe-rs/src/architecture/arm/memory/romtable.rs b/probe-rs/src/architecture/arm/memory/romtable.rs
index 17984499..eb53171d 100644
--- a/probe-rs/src/architecture/arm/memory/romtable.rs
+++ b/probe-rs/src/architecture/arm/memory/romtable.rs
@@ -1,9 +1,11 @@
 //! CoreSight ROM table parsing and handling.
 
-use super::adi_v5_memory_interface::ArmMemoryInterface;
-use super::AccessPortError;
-use crate::architecture::arm::ArmError;
-use crate::architecture::arm::{ap::MemoryAp, communication_interface::ArmProbeInterface};
+use crate::architecture::arm::{
+    ap::{AccessPortError, MemoryAp},
+    communication_interface::ArmProbeInterface,
+    memory::ArmMemoryInterface,
+    ArmError,
+};
 
 /// An error to report any errors that are romtable discovery specific.
 #[derive(thiserror::Error, Debug, docsplay::Display)]
diff --git a/probe-rs/src/architecture/arm/sequences.rs b/probe-rs/src/architecture/arm/sequences.rs
index dac03345..2f1fbfba 100644
--- a/probe-rs/src/architecture/arm/sequences.rs
+++ b/probe-rs/src/architecture/arm/sequences.rs
@@ -27,8 +27,8 @@ use super::{
     core::cortex_m::Dhcsr,
     dp::{Abort, Ctrl, DebugPortError, DpAccess, Select, DPIDR},
     memory::{
-        adi_v5_memory_interface::ArmMemoryInterface,
         romtable::{CoresightComponent, PeripheralType},
+        ArmMemoryInterface,
     },
     ArmCommunicationInterface, ArmError, DpAddress, Pins, PortType, Register,
 };
diff --git a/probe-rs/src/config/registry.rs b/probe-rs/src/config/registry.rs
index 9bc4dea4..5ce57498 100644
--- a/probe-rs/src/config/registry.rs
+++ b/probe-rs/src/config/registry.rs
@@ -4,7 +4,7 @@ use super::{Chip, ChipFamily, ChipInfo, Core, Target, TargetDescriptionSource};
 use crate::config::CoreType;
 use once_cell::sync::Lazy;
 use parking_lot::{RwLock, RwLockReadGuard};
-use probe_rs_target::{BinaryFormat, CoreAccessOptions, RiscvCoreAccessOptions};
+use probe_rs_target::{CoreAccessOptions, RiscvCoreAccessOptions};
 use std::collections::HashMap;
 use std::io::Read;
 use std::ops::Deref;
@@ -110,7 +110,7 @@ fn add_generic_targets(vec: &mut Vec<ChipFamily>) {
                 flash_algorithms: vec![],
                 rtt_scan_ranges: None,
                 jtag: None,
-                default_binary_format: Some(BinaryFormat::Raw),
+                default_binary_format: None,
             }],
             flash_algorithms: vec![],
             source: TargetDescriptionSource::Generic,
@@ -324,12 +324,9 @@ impl Registry {
     {
         let family: ChipFamily = serde_yaml::from_reader(yaml_reader)?;
 
-        if let Err(error) = family.validate() {
-            return Err(RegistryError::InvalidChipFamilyDefinition(
-                Box::new(family),
-                error,
-            ));
-        };
+        validate_family(&family).map_err(|error| {
+            RegistryError::InvalidChipFamilyDefinition(Box::new(family.clone()), error)
+        })?;
 
         let family_name = family.name.clone();
 
@@ -437,6 +434,18 @@ fn match_name_prefix(pattern: &str, name: &str) -> bool {
     true
 }
 
+fn validate_family(family: &ChipFamily) -> Result<(), String> {
+    family.validate()?;
+
+    // We can't have this in the `validate` method as we need information that is not available in
+    // probe-rs-target.
+    for target in family.variants() {
+        crate::flashing::FormatKind::from_optional(target.default_binary_format.as_deref())?;
+    }
+
+    Ok(())
+}
+
 #[cfg(test)]
 mod tests {
     use crate::flashing::FlashAlgorithm;
@@ -513,7 +522,7 @@ mod tests {
             .iter()
             .flat_map(|family| {
                 // Validate all chip descriptors.
-                family.validate().unwrap();
+                validate_family(family).unwrap();
 
                 // Make additional checks by creating a target for each chip.
                 family
diff --git a/probe-rs/src/config/target.rs b/probe-rs/src/config/target.rs
index fd282ddb..3c250b9d 100644
--- a/probe-rs/src/config/target.rs
+++ b/probe-rs/src/config/target.rs
@@ -12,7 +12,7 @@ use crate::{
     },
     rtt::ScanRegion,
 };
-use probe_rs_target::{Architecture, BinaryFormat, Chip, ChipFamily, Jtag};
+use probe_rs_target::{Architecture, Chip, ChipFamily, Jtag};
 use std::sync::Arc;
 
 /// This describes a complete target with a fixed chip model and variant.
@@ -42,7 +42,7 @@ pub struct Target {
     /// the number devices in the scan chain and their ir lengths.
     pub jtag: Option<Jtag>,
     /// The default executable format for the target.
-    pub default_format: BinaryFormat,
+    pub default_format: Option<String>,
 }
 
 impl std::fmt::Debug for Target {
@@ -109,7 +109,7 @@ impl Target {
             debug_sequence,
             rtt_scan_regions,
             jtag: chip.jtag.clone(),
-            default_format: chip.default_binary_format.clone().unwrap_or_default(),
+            default_format: chip.default_binary_format.clone(),
         }
     }
 
diff --git a/probe-rs/src/flashing/download.rs b/probe-rs/src/flashing/download.rs
index bdfbc10d..d7634cfa 100644
--- a/probe-rs/src/flashing/download.rs
+++ b/probe-rs/src/flashing/download.rs
@@ -15,7 +15,7 @@ use super::*;
 use crate::session::Session;
 
 /// Extended options for flashing a binary file.
-#[derive(Debug, Serialize, Deserialize, PartialEq, Eq, Clone)]
+#[derive(Debug, Serialize, Deserialize, PartialEq, Eq, Clone, Default)]
 pub struct BinOptions {
     /// The address in memory where the binary will be put at.
     pub base_address: Option<u64>,
@@ -34,11 +34,11 @@ pub struct IdfOptions {
 
 /// A finite list of all the available binary formats probe-rs understands.
 #[derive(Debug, Default, Serialize, Deserialize, PartialEq, Eq, Clone)]
-pub enum Format {
+pub enum FormatKind {
     /// Marks a file in binary format. This means that the file contains the contents of the flash 1:1.
     /// [BinOptions] can be used to define the location in flash where the file contents should be put at.
     /// Additionally using the same config struct, you can skip the first N bytes of the binary file to have them not put into the flash.
-    Bin(BinOptions),
+    Bin,
     /// Marks a file in [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format.
     Hex,
     /// Marks a file in the [ELF](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format) format.
@@ -46,29 +46,69 @@ pub enum Format {
     Elf,
     /// Marks a file in the [ESP-IDF bootloader](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html#app-image-structures) format.
     /// Use [IdfOptions] to configure flashing.
-    Idf(IdfOptions),
+    Idf,
     /// Marks a file in the [UF2](https://github.com/microsoft/uf2) format.
     Uf2,
 }
 
-impl FromStr for Format {
+impl FormatKind {
+    /// Creates a new Format from an optional string.
+    ///
+    /// If the string is `None`, the default format is returned.
+    pub fn from_optional(s: Option<&str>) -> Result<Self, String> {
+        match s {
+            Some(format) => Self::from_str(format),
+            None => Ok(Self::default()),
+        }
+    }
+}
+
+impl FromStr for FormatKind {
     type Err = String;
 
     fn from_str(s: &str) -> Result<Self, Self::Err> {
         match &s.to_lowercase()[..] {
-            "bin" | "binary" => Ok(Format::Bin(BinOptions {
-                base_address: None,
-                skip: 0,
-            })),
-            "idf" | "esp-idf" => Ok(Format::Idf(Default::default())),
-            "hex" | "ihex" | "intelhex" => Ok(Format::Hex),
-            "elf" => Ok(Format::Elf),
-            "uf2" => Ok(Format::Uf2),
+            "bin" | "binary" => Ok(Self::Bin),
+            "hex" | "ihex" | "intelhex" => Ok(Self::Hex),
+            "elf" => Ok(Self::Elf),
+            "uf2" => Ok(Self::Uf2),
+            "idf" | "esp-idf" | "espidf" => Ok(Self::Idf),
             _ => Err(format!("Format '{s}' is unknown.")),
         }
     }
 }
 
+/// A finite list of all the available binary formats probe-rs understands.
+#[derive(Debug, Default, Serialize, Deserialize, PartialEq, Eq, Clone)]
+pub enum Format {
+    /// Marks a file in binary format. This means that the file contains the contents of the flash 1:1.
+    /// [BinOptions] can be used to define the location in flash where the file contents should be put at.
+    /// Additionally using the same config struct, you can skip the first N bytes of the binary file to have them not put into the flash.
+    Bin(BinOptions),
+    /// Marks a file in [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format.
+    Hex,
+    /// Marks a file in the [ELF](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format) format.
+    #[default]
+    Elf,
+    /// Marks a file in the [ESP-IDF bootloader](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html#app-image-structures) format.
+    /// Use [IdfOptions] to configure flashing.
+    Idf(IdfOptions),
+    /// Marks a file in the [UF2](https://github.com/microsoft/uf2) format.
+    Uf2,
+}
+
+impl From<FormatKind> for Format {
+    fn from(kind: FormatKind) -> Self {
+        match kind {
+            FormatKind::Bin => Format::Bin(BinOptions::default()),
+            FormatKind::Hex => Format::Hex,
+            FormatKind::Elf => Format::Elf,
+            FormatKind::Uf2 => Format::Uf2,
+            FormatKind::Idf => Format::Idf(IdfOptions::default()),
+        }
+    }
+}
+
 /// A finite list of all the errors that can occur when flashing a given file.
 ///
 /// This includes corrupt file issues,
@@ -196,10 +236,10 @@ pub fn build_loader(
 /// This will ensure that memory boundaries are honored and does unlocking, erasing and programming of the flash for you.
 ///
 /// If you are looking for more options, have a look at [download_file_with_options].
-pub fn download_file<P: AsRef<Path>>(
+pub fn download_file(
     session: &mut Session,
-    path: P,
-    format: Format,
+    path: impl AsRef<Path>,
+    format: impl Into<Format>,
 ) -> Result<(), FileDownloadError> {
     download_file_with_options(session, path, format, DownloadOptions::default())
 }
@@ -209,13 +249,13 @@ pub fn download_file<P: AsRef<Path>>(
 /// This will ensure that memory boundaries are honored and does unlocking, erasing and programming of the flash for you.
 ///
 /// If you are looking for a simple version without many options, have a look at [download_file].
-pub fn download_file_with_options<P: AsRef<Path>>(
+pub fn download_file_with_options(
     session: &mut Session,
-    path: P,
-    format: Format,
+    path: impl AsRef<Path>,
+    format: impl Into<Format>,
     options: DownloadOptions,
 ) -> Result<(), FileDownloadError> {
-    let loader = build_loader(session, path, format, None)?;
+    let loader = build_loader(session, path, format.into(), None)?;
 
     loader
         .commit(session, options)
@@ -349,59 +389,39 @@ pub(super) fn extract_from_elf(
 mod tests {
     use std::str::FromStr;
 
-    use super::{BinOptions, Format};
+    use super::FormatKind;
 
     #[test]
     fn parse_format() {
-        assert_eq!(Format::from_str("hex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("Hex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("Ihex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("IHex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("iHex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("IntelHex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("intelhex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("intelHex"), Ok(Format::Hex));
-        assert_eq!(Format::from_str("Intelhex"), Ok(Format::Hex));
-        assert_eq!(
-            Format::from_str("bin"),
-            Ok(Format::Bin(BinOptions {
-                base_address: None,
-                skip: 0
-            }))
-        );
-        assert_eq!(
-            Format::from_str("Bin"),
-            Ok(Format::Bin(BinOptions {
-                base_address: None,
-                skip: 0
-            }))
-        );
-        assert_eq!(
-            Format::from_str("binary"),
-            Ok(Format::Bin(BinOptions {
-                base_address: None,
-                skip: 0
-            }))
-        );
-        assert_eq!(
-            Format::from_str("Binary"),
-            Ok(Format::Bin(BinOptions {
-                base_address: None,
-                skip: 0
-            }))
-        );
-        assert_eq!(Format::from_str("Elf"), Ok(Format::Elf));
-        assert_eq!(Format::from_str("elf"), Ok(Format::Elf));
+        assert_eq!(FormatKind::from_str("hex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("Hex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("Ihex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("IHex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("iHex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("IntelHex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("intelhex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("intelHex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("Intelhex"), Ok(FormatKind::Hex));
+        assert_eq!(FormatKind::from_str("bin"), Ok(FormatKind::Bin));
+        assert_eq!(FormatKind::from_str("Bin"), Ok(FormatKind::Bin));
+        assert_eq!(FormatKind::from_str("binary"), Ok(FormatKind::Bin));
+        assert_eq!(FormatKind::from_str("Binary"), Ok(FormatKind::Bin));
+        assert_eq!(FormatKind::from_str("Elf"), Ok(FormatKind::Elf));
+        assert_eq!(FormatKind::from_str("elf"), Ok(FormatKind::Elf));
+        assert_eq!(FormatKind::from_str("idf"), Ok(FormatKind::Idf));
+        assert_eq!(FormatKind::from_str("espidf"), Ok(FormatKind::Idf));
+        assert_eq!(FormatKind::from_str("esp-idf"), Ok(FormatKind::Idf));
+        assert_eq!(FormatKind::from_str("ESP-IDF"), Ok(FormatKind::Idf));
         assert_eq!(
-            Format::from_str("elfbin"),
+            FormatKind::from_str("elfbin"),
             Err("Format 'elfbin' is unknown.".to_string())
         );
         assert_eq!(
-            Format::from_str(""),
+            FormatKind::from_str(""),
             Err("Format '' is unknown.".to_string())
         );
         assert_eq!(
-            Format::from_str("asdasdf"),
+            FormatKind::from_str("asdasdf"),
             Err("Format 'asdasdf' is unknown.".to_string())
         );
     }
diff --git a/probe-rs/src/probe/fake_probe.rs b/probe-rs/src/probe/fake_probe.rs
index b1857948..a603083f 100644
--- a/probe-rs/src/probe/fake_probe.rs
+++ b/probe-rs/src/probe/fake_probe.rs
@@ -10,7 +10,7 @@ use crate::{
         communication_interface::{
             ArmDebugState, Initialized, SwdSequence, Uninitialized, UninitializedArmProbe,
         },
-        memory::adi_v5_memory_interface::{ADIMemoryInterface, ArmMemoryInterface},
+        memory::{adi_v5_memory_interface::ADIMemoryInterface, ArmMemoryInterface},
         sequences::ArmDebugSequence,
         ArmError, ArmProbeInterface, DapAccess, DpAddress, FullyQualifiedApAddress,
         MemoryApInformation, PortType, RawDapAccess, SwoAccess,
diff --git a/probe-rs/src/probe/stlink/mod.rs b/probe-rs/src/probe/stlink/mod.rs
index fb06e594..fefb182b 100644
--- a/probe-rs/src/probe/stlink/mod.rs
+++ b/probe-rs/src/probe/stlink/mod.rs
@@ -7,7 +7,7 @@ mod usb_interface;
 use self::usb_interface::{StLinkUsb, StLinkUsbDevice};
 use super::{DebugProbe, DebugProbeError, ProbeCreationError, WireProtocol};
 use crate::architecture::arm::ap::GenericAp;
-use crate::architecture::arm::memory::adi_v5_memory_interface::ArmMemoryInterface;
+use crate::architecture::arm::memory::ArmMemoryInterface;
 use crate::architecture::arm::{valid_32bit_arm_address, ArmError};
 use crate::MemoryInterface;
 use crate::{
diff --git a/probe-rs/src/vendor/infineon/mod.rs b/probe-rs/src/vendor/infineon/mod.rs
index 531abda4..48902fed 100644
--- a/probe-rs/src/vendor/infineon/mod.rs
+++ b/probe-rs/src/vendor/infineon/mod.rs
@@ -5,8 +5,8 @@ use probe_rs_target::{chip_detection::ChipDetectionMethod, Chip};
 
 use crate::{
     architecture::arm::{
-        ap::MemoryAp, memory::adi_v5_memory_interface::ArmMemoryInterface, ArmChipInfo, ArmError,
-        ArmProbeInterface, FullyQualifiedApAddress,
+        ap::MemoryAp, memory::ArmMemoryInterface, ArmChipInfo, ArmError, ArmProbeInterface,
+        FullyQualifiedApAddress,
     },
     config::{registry, DebugSequence},
     error::Error,
diff --git a/probe-rs/src/vendor/infineon/sequences/xmc4000.rs b/probe-rs/src/vendor/infineon/sequences/xmc4000.rs
index 53f22aff..36ab694e 100644
--- a/probe-rs/src/vendor/infineon/sequences/xmc4000.rs
+++ b/probe-rs/src/vendor/infineon/sequences/xmc4000.rs
@@ -1,7 +1,7 @@
 //! Sequences for XMC4000
 
 use crate::architecture::arm::armv7m::{Aircr, Dhcsr, FpCtrl, FpRev1CompX, FpRev2CompX};
-use crate::architecture::arm::memory::adi_v5_memory_interface::ArmMemoryInterface;
+use crate::architecture::arm::memory::ArmMemoryInterface;
 use crate::architecture::arm::sequences::{ArmDebugSequence, ArmDebugSequenceError};
 use crate::architecture::arm::ArmError;
 use std::sync::Arc;
diff --git a/probe-rs/src/vendor/microchip/sequences/atsam.rs b/probe-rs/src/vendor/microchip/sequences/atsam.rs
index 96a6295f..8ab02992 100644
--- a/probe-rs/src/vendor/microchip/sequences/atsam.rs
+++ b/probe-rs/src/vendor/microchip/sequences/atsam.rs
@@ -7,7 +7,7 @@ use crate::{
             ap::MemoryAp,
             armv7m::Dhcsr,
             communication_interface::{DapProbe, SwdSequence},
-            memory::adi_v5_memory_interface::ArmMemoryInterface,
+            memory::ArmMemoryInterface,
             sequences::{ArmDebugSequence, ArmDebugSequenceError, DebugEraseSequence},
             ArmError, ArmProbeInterface, FullyQualifiedApAddress, Pins,
         },
diff --git a/probe-rs/src/vendor/nordicsemi/mod.rs b/probe-rs/src/vendor/nordicsemi/mod.rs
index 96ced47e..bec05e75 100644
--- a/probe-rs/src/vendor/nordicsemi/mod.rs
+++ b/probe-rs/src/vendor/nordicsemi/mod.rs
@@ -9,8 +9,8 @@ use probe_rs_target::{
 
 use crate::{
     architecture::arm::{
-        ap::MemoryAp, memory::adi_v5_memory_interface::ArmMemoryInterface, ArmChipInfo,
-        ArmProbeInterface, FullyQualifiedApAddress,
+        ap::MemoryAp, memory::ArmMemoryInterface, ArmChipInfo, ArmProbeInterface,
+        FullyQualifiedApAddress,
     },
     config::{registry, DebugSequence},
     vendor::{
diff --git a/probe-rs/src/vendor/nordicsemi/sequences/nrf.rs b/probe-rs/src/vendor/nordicsemi/sequences/nrf.rs
index bd3583a0..3f098a25 100644
--- a/probe-rs/src/vendor/nordicsemi/sequences/nrf.rs
+++ b/probe-rs/src/vendor/nordicsemi/sequences/nrf.rs
@@ -4,7 +4,7 @@ use crate::{
     architecture::arm::{
         ap::MemoryAp,
         communication_interface::Initialized,
-        memory::adi_v5_memory_interface::ArmMemoryInterface,
+        memory::ArmMemoryInterface,
         sequences::{ArmDebugSequence, ArmDebugSequenceError},
         ArmCommunicationInterface, ArmError, ArmProbeInterface, DapAccess, FullyQualifiedApAddress,
     },
diff --git a/probe-rs/src/vendor/nordicsemi/sequences/nrf52.rs b/probe-rs/src/vendor/nordicsemi/sequences/nrf52.rs
index 56610683..ede6291d 100644
--- a/probe-rs/src/vendor/nordicsemi/sequences/nrf52.rs
+++ b/probe-rs/src/vendor/nordicsemi/sequences/nrf52.rs
@@ -49,7 +49,7 @@ impl Nrf52 {
 }
 
 mod clock {
-    use crate::architecture::arm::{memory::adi_v5_memory_interface::ArmMemoryInterface, ArmError};
+    use crate::architecture::arm::{memory::ArmMemoryInterface, ArmError};
     use bitfield::bitfield;
 
     /// The base address of the DBGMCU component
diff --git a/probe-rs/src/vendor/nordicsemi/sequences/nrf53.rs b/probe-rs/src/vendor/nordicsemi/sequences/nrf53.rs
index b851c1fc..24c07a2c 100644
--- a/probe-rs/src/vendor/nordicsemi/sequences/nrf53.rs
+++ b/probe-rs/src/vendor/nordicsemi/sequences/nrf53.rs
@@ -4,7 +4,7 @@ use std::sync::Arc;
 
 use super::nrf::Nrf;
 use crate::architecture::arm::ap::{AccessPort, CSW};
-use crate::architecture::arm::memory::adi_v5_memory_interface::ArmMemoryInterface;
+use crate::architecture::arm::memory::ArmMemoryInterface;
 use crate::architecture::arm::sequences::ArmDebugSequence;
 use crate::architecture::arm::ArmError;
 use crate::architecture::arm::{
diff --git a/probe-rs/src/vendor/nordicsemi/sequences/nrf91.rs b/probe-rs/src/vendor/nordicsemi/sequences/nrf91.rs
index 40cca9f6..2f7057ee 100644
--- a/probe-rs/src/vendor/nordicsemi/sequences/nrf91.rs
+++ b/probe-rs/src/vendor/nordicsemi/sequences/nrf91.rs
@@ -4,7 +4,7 @@ use std::sync::Arc;
 
 use super::nrf::Nrf;
 use crate::architecture::arm::ap::AccessPort;
-use crate::architecture::arm::memory::adi_v5_memory_interface::ArmMemoryInterface;
+use crate::architecture::arm::memory::ArmMemoryInterface;
 use crate::architecture::arm::sequences::ArmDebugSequence;
 use crate::architecture::arm::ArmError;
 use crate::architecture::arm::{
diff --git a/probe-rs/src/vendor/nxp/sequences/nxp_armv7m.rs b/probe-rs/src/vendor/nxp/sequences/nxp_armv7m.rs
index 7e713b6e..4ad63d4d 100644
--- a/probe-rs/src/vendor/nxp/sequences/nxp_armv7m.rs
+++ b/probe-rs/src/vendor/nxp/sequences/nxp_armv7m.rs
@@ -17,7 +17,7 @@ use crate::{
             armv7m::{Aircr, Dhcsr},
             registers::cortex_m::PC,
         },
-        memory::adi_v5_memory_interface::ArmMemoryInterface,
+        memory::ArmMemoryInterface,
         sequences::{ArmDebugSequence, ArmDebugSequenceError},
         ArmError,
     },
diff --git a/probe-rs/src/vendor/nxp/sequences/nxp_armv8m.rs b/probe-rs/src/vendor/nxp/sequences/nxp_armv8m.rs
index a7bbc39e..47eeefcb 100644
--- a/probe-rs/src/vendor/nxp/sequences/nxp_armv8m.rs
+++ b/probe-rs/src/vendor/nxp/sequences/nxp_armv8m.rs
@@ -12,7 +12,7 @@ use crate::{
         communication_interface::{FlushableArmAccess, Initialized},
         core::armv8m::{Aircr, Demcr, Dhcsr},
         dp::{Abort, Ctrl, DpAccess, Select, DPIDR},
-        memory::adi_v5_memory_interface::ArmMemoryInterface,
+        memory::ArmMemoryInterface,
         sequences::ArmDebugSequence,
         ArmCommunicationInterface, ArmError, DapAccess, DpAddress, FullyQualifiedApAddress, Pins,
     },
diff --git a/probe-rs/src/vendor/silabs/sequences/efm32xg2.rs b/probe-rs/src/vendor/silabs/sequences/efm32xg2.rs
index 5ffe7516..d36e0442 100644
--- a/probe-rs/src/vendor/silabs/sequences/efm32xg2.rs
+++ b/probe-rs/src/vendor/silabs/sequences/efm32xg2.rs
@@ -5,7 +5,7 @@ use std::sync::Arc;
 use crate::{
     architecture::arm::{
         core::armv7m::{Demcr, Dhcsr},
-        memory::adi_v5_memory_interface::ArmMemoryInterface,
+        memory::ArmMemoryInterface,
         sequences::ArmDebugSequence,
         ArmError,
     },
diff --git a/probe-rs/src/vendor/st/sequences/stm32_armv6.rs b/probe-rs/src/vendor/st/sequences/stm32_armv6.rs
index 81381261..a730da77 100644
--- a/probe-rs/src/vendor/st/sequences/stm32_armv6.rs
+++ b/probe-rs/src/vendor/st/sequences/stm32_armv6.rs
@@ -7,8 +7,8 @@ use std::sync::Arc;
 use probe_rs_target::CoreType;
 
 use crate::architecture::arm::{
-    ap::MemoryAp, memory::adi_v5_memory_interface::ArmMemoryInterface, sequences::ArmDebugSequence,
-    ArmError, ArmProbeInterface,
+    ap::MemoryAp, memory::ArmMemoryInterface, sequences::ArmDebugSequence, ArmError,
+    ArmProbeInterface,
 };
 
 /// Supported families for custom sequences on ARMv6 STM32 devices.
@@ -38,7 +38,7 @@ impl Stm32Armv6 {
 }
 
 mod rcc {
-    use crate::architecture::arm::{memory::adi_v5_memory_interface::ArmMemoryInterface, ArmError};
+    use crate::architecture::arm::{memory::ArmMemoryInterface, ArmError};
     use bitfield::bitfield;
 
     /// The base address of the RCC peripheral
@@ -78,7 +78,7 @@ mod rcc {
 }
 
 mod dbgmcu {
-    use crate::architecture::arm::{memory::adi_v5_memory_interface::ArmMemoryInterface, ArmError};
+    use crate::architecture::arm::{memory::ArmMemoryInterface, ArmError};
     use bitfield::bitfield;
 
     /// The base address of the DBGMCU component
diff --git a/probe-rs/src/vendor/st/sequences/stm32_armv7.rs b/probe-rs/src/vendor/st/sequences/stm32_armv7.rs
index 4ee2fe1c..5c85bee3 100644
--- a/probe-rs/src/vendor/st/sequences/stm32_armv7.rs
+++ b/probe-rs/src/vendor/st/sequences/stm32_armv7.rs
@@ -15,7 +15,7 @@ use probe_rs_target::CoreType;
 use crate::architecture::arm::{
     ap::MemoryAp,
     component::TraceSink,
-    memory::{adi_v5_memory_interface::ArmMemoryInterface, CoresightComponent},
+    memory::{ArmMemoryInterface, CoresightComponent},
     sequences::ArmDebugSequence,
     ArmError, ArmProbeInterface,
 };
@@ -32,7 +32,7 @@ impl Stm32Armv7 {
 }
 
 mod dbgmcu {
-    use crate::architecture::arm::{memory::adi_v5_memory_interface::ArmMemoryInterface, ArmError};
+    use crate::architecture::arm::{memory::ArmMemoryInterface, ArmError};
     use bitfield::bitfield;
 
     /// The base address of the DBGMCU component
diff --git a/probe-rs/src/vendor/st/sequences/stm32_armv8.rs b/probe-rs/src/vendor/st/sequences/stm32_armv8.rs
index 247b8e1a..2f674791 100644
--- a/probe-rs/src/vendor/st/sequences/stm32_armv8.rs
+++ b/probe-rs/src/vendor/st/sequences/stm32_armv8.rs
@@ -11,7 +11,7 @@ use probe_rs_target::CoreType;
 use crate::architecture::arm::{
     ap::MemoryAp,
     component::TraceSink,
-    memory::{adi_v5_memory_interface::ArmMemoryInterface, CoresightComponent},
+    memory::{ArmMemoryInterface, CoresightComponent},
     sequences::ArmDebugSequence,
     ArmError, ArmProbeInterface,
 };
@@ -28,7 +28,7 @@ impl Stm32Armv8 {
 }
 
 mod dbgmcu {
-    use crate::architecture::arm::{memory::adi_v5_memory_interface::ArmMemoryInterface, ArmError};
+    use crate::architecture::arm::{memory::ArmMemoryInterface, ArmError};
     use bitfield::bitfield;
 
     /// The base address of the DBGMCU component
diff --git a/probe-rs/src/vendor/st/sequences/stm32h7.rs b/probe-rs/src/vendor/st/sequences/stm32h7.rs
index fe742cae..ea17b958 100644
--- a/probe-rs/src/vendor/st/sequences/stm32h7.rs
+++ b/probe-rs/src/vendor/st/sequences/stm32h7.rs
@@ -7,10 +7,7 @@ use probe_rs_target::CoreType;
 use crate::architecture::arm::{
     ap::MemoryAp,
     component::{TraceFunnel, TraceSink},
-    memory::{
-        adi_v5_memory_interface::ArmMemoryInterface, romtable::RomTableError, CoresightComponent,
-        PeripheralType,
-    },
+    memory::{romtable::RomTableError, ArmMemoryInterface, CoresightComponent, PeripheralType},
     sequences::ArmDebugSequence,
     ArmError, ArmProbeInterface, FullyQualifiedApAddress,
 };
@@ -79,7 +76,7 @@ impl Stm32h7 {
 }
 
 mod dbgmcu {
-    use crate::architecture::arm::{memory::adi_v5_memory_interface::ArmMemoryInterface, ArmError};
+    use crate::architecture::arm::{memory::ArmMemoryInterface, ArmError};
     use bitfield::bitfield;
 
     /// The base address of the DBGMCU component
diff --git a/probe-rs/src/vendor/ti/sequences/cc13xx_cc26xx.rs b/probe-rs/src/vendor/ti/sequences/cc13xx_cc26xx.rs
index ba422e98..3f2661e7 100644
--- a/probe-rs/src/vendor/ti/sequences/cc13xx_cc26xx.rs
+++ b/probe-rs/src/vendor/ti/sequences/cc13xx_cc26xx.rs
@@ -4,7 +4,7 @@ use std::time::Duration;
 
 use crate::architecture::arm::armv7m::{Demcr, Dhcsr};
 use crate::architecture::arm::communication_interface::DapProbe;
-use crate::architecture::arm::memory::adi_v5_memory_interface::ArmMemoryInterface;
+use crate::architecture::arm::memory::ArmMemoryInterface;
 use crate::architecture::arm::sequences::{ArmDebugSequence, ArmDebugSequenceError};
 use crate::architecture::arm::{ArmError, DpAddress};
 use crate::probe::{DebugProbeError, WireProtocol};
diff --git a/probe-rs/src/vendor/vorago/sequences/va416xx.rs b/probe-rs/src/vendor/vorago/sequences/va416xx.rs
index 4c5351a4..77b4507b 100644
--- a/probe-rs/src/vendor/vorago/sequences/va416xx.rs
+++ b/probe-rs/src/vendor/vorago/sequences/va416xx.rs
@@ -7,7 +7,7 @@ use crate::{
     architecture::arm::{
         ap::MemoryAp,
         armv7m::Demcr,
-        memory::adi_v5_memory_interface::ArmMemoryInterface,
+        memory::ArmMemoryInterface,
         sequences::{cortex_m_core_start, ArmDebugSequence},
         ArmError, ArmProbeInterface,
     },
diff --git a/probe-rs/targets/STM32WBA_Series.yaml b/probe-rs/targets/STM32WBA_Series.yaml
index c8dae74b..a63fd644 100644
--- a/probe-rs/targets/STM32WBA_Series.yaml
+++ b/probe-rs/targets/STM32WBA_Series.yaml
@@ -3,8 +3,64 @@ manufacturer:
   id: 0x20
   cc: 0x0
 generated_from_pack: true
-pack_file_release: 1.2.1
+pack_file_release: 1.3.0
 variants:
+- name: STM32WBA50KEUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8080000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA50KGUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8100000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20020000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
 - name: STM32WBA52CEUx
   cores:
   - name: main
@@ -14,16 +70,45 @@ variants:
       psel: 0x0
   memory_map:
   - !Nvm
-    name: Flash
+    name: BANK_1
     range:
       start: 0x8000000
       end: 0x8080000
     cores:
     - main
     access:
+      write: false
       boot: true
   - !Ram
-    name: SRAM1_2
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA52CGUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8100000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
     range:
       start: 0x20000000
       end: 0x20020000
@@ -32,7 +117,7 @@ variants:
   flash_algorithms:
   - stm32wbax_1m_0800
   - stm32wbax_1m_0c00
-- name: STM32WBA52CEUxT
+- name: STM32WBA52KEUx
   cores:
   - name: main
     type: armv8m
@@ -41,16 +126,45 @@ variants:
       psel: 0x0
   memory_map:
   - !Nvm
-    name: Flash
+    name: BANK_1
     range:
       start: 0x8000000
       end: 0x8080000
     cores:
     - main
     access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA52KGUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8100000
+    cores:
+    - main
+    access:
+      write: false
       boot: true
   - !Ram
-    name: SRAM1_2
+    name: SRAM
     range:
       start: 0x20000000
       end: 0x20020000
@@ -59,7 +173,63 @@ variants:
   flash_algorithms:
   - stm32wbax_1m_0800
   - stm32wbax_1m_0c00
-- name: STM32WBA52CGUx
+- name: STM32WBA54CEUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8080000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA54CGUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8100000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20020000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA54KEUx
   cores:
   - name: main
     type: armv8m
@@ -68,16 +238,45 @@ variants:
       psel: 0x0
   memory_map:
   - !Nvm
-    name: Flash
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8080000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA54KGUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
     range:
       start: 0x8000000
       end: 0x8100000
     cores:
     - main
     access:
+      write: false
       boot: true
   - !Ram
-    name: SRAM1_2
+    name: SRAM
     range:
       start: 0x20000000
       end: 0x20020000
@@ -86,7 +285,35 @@ variants:
   flash_algorithms:
   - stm32wbax_1m_0800
   - stm32wbax_1m_0c00
-- name: STM32WBA52CGUxT
+- name: STM32WBA55CEUx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8080000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA55CGUx
   cores:
   - name: main
     type: armv8m
@@ -95,16 +322,17 @@ variants:
       psel: 0x0
   memory_map:
   - !Nvm
-    name: Flash
+    name: BANK_1
     range:
       start: 0x8000000
       end: 0x8100000
     cores:
     - main
     access:
+      write: false
       boot: true
   - !Ram
-    name: SRAM1_2
+    name: SRAM
     range:
       start: 0x20000000
       end: 0x20020000
@@ -113,7 +341,91 @@ variants:
   flash_algorithms:
   - stm32wbax_1m_0800
   - stm32wbax_1m_0c00
-- name: STM32WBA52CGUxU
+- name: STM32WBA55HEFx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8080000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA55HGFx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8100000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20020000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA55UEIx
+  cores:
+  - name: main
+    type: armv8m
+    core_access_options: !Arm
+      ap: 1
+      psel: 0x0
+  memory_map:
+  - !Nvm
+    name: BANK_1
+    range:
+      start: 0x8000000
+      end: 0x8080000
+    cores:
+    - main
+    access:
+      write: false
+      boot: true
+  - !Ram
+    name: SRAM
+    range:
+      start: 0x20000000
+      end: 0x20018000
+    cores:
+    - main
+  flash_algorithms:
+  - stm32wbax_1m_0800
+  - stm32wbax_1m_0c00
+- name: STM32WBA55UGIx
   cores:
   - name: main
     type: armv8m
@@ -122,16 +434,17 @@ variants:
       psel: 0x0
   memory_map:
   - !Nvm
-    name: Flash
+    name: BANK_1
     range:
       start: 0x8000000
       end: 0x8100000
     cores:
     - main
     access:
+      write: false
       boot: true
   - !Ram
-    name: SRAM1_2
+    name: SRAM
     range:
       start: 0x20000000
       end: 0x20020000


Test patch:
diff --git a/smoke-tester/src/tests.rs b/smoke-tester/src/tests.rs
index 10c1cc06..9d1184ac 100644
--- a/smoke-tester/src/tests.rs
+++ b/smoke-tester/src/tests.rs
@@ -4,7 +4,7 @@ use colored::Colorize;
 use linkme::distributed_slice;
 use probe_rs::{
     config::MemoryRegion,
-    flashing::{download_file_with_options, DownloadOptions, FlashProgress, Format},
+    flashing::{download_file_with_options, DownloadOptions, FlashProgress, FormatKind},
     Architecture, Core, MemoryInterface, Session,
 };
 
@@ -224,10 +224,7 @@ pub fn test_flashing(tracker: &TestTracker, session: &mut Session) -> Result<(),
 
     let start_time = Instant::now();
 
-    let format = match session.target().default_format {
-        probe_rs_target::BinaryFormat::Idf => Format::Idf(Default::default()),
-        probe_rs_target::BinaryFormat::Raw => Default::default(),
-    };
+    let format = FormatKind::from_optional(session.target().default_format.as_deref()).unwrap();
 
     let result = download_file_with_options(session, test_binary, format, options);
 
diff --git a/target-gen/src/commands/snapshots/target_gen__commands__elf__test__serialization_cleanup.snap b/target-gen/src/commands/snapshots/target_gen__commands__elf__test__serialization_cleanup.snap
index 0cfe0734..7fe4b7a1 100644
--- a/target-gen/src/commands/snapshots/target_gen__commands__elf__test__serialization_cleanup.snap
+++ b/target-gen/src/commands/snapshots/target_gen__commands__elf__test__serialization_cleanup.snap
@@ -35,4 +35,3 @@ variants:
     - main
     access:
       execute: false
-  default_binary_format: raw