Repository: bytecodealliance/wasmtime
Pull request #8407 (2024-04-18 23:58:19)

x64: Use r10 for the indirect tail call destination
Use `r10` for the destination of indirect return calls, and indirect calls using the winch calling convention, as it is a caller-saved register. Additionally, always use `r11` for the temporary that's used for moving the return address in `emit_return_call_common_sequence`, as it's also a caller-saved register.

For tail calls, this ensures that we won't accidentally pick a callee-saved register for the destination or temporary, clobbering it when we restore callee-saves in the call to `emit_return_call_common_sequence`.

For winch calls, using `r10` instead of `r15` means that it's still possible to use the pinned register in combination with winch.

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Patch:
diff --git a/Cargo.lock b/Cargo.lock
index ea48ab4d5..37c6ede4d 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -849,7 +849,7 @@ dependencies = [
  "serde_derive",
  "smallvec",
  "target-lexicon",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmtime-types",
  "wat",
 ]
@@ -2756,7 +2756,7 @@ dependencies = [
  "cargo_metadata",
  "heck",
  "wasmtime",
- "wit-component 0.204.0",
+ "wit-component 0.205.0",
 ]
 
 [[package]]
@@ -3092,7 +3092,7 @@ name = "verify-component-adapter"
 version = "21.0.0"
 dependencies = [
  "anyhow",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wat",
 ]
 
@@ -3184,7 +3184,7 @@ dependencies = [
  "byte-array-literals",
  "object 0.33.0",
  "wasi",
- "wasm-encoder 0.204.0",
+ "wasm-encoder 0.205.0",
  "wit-bindgen",
 ]
 
@@ -3253,9 +3253,9 @@ dependencies = [
 
 [[package]]
 name = "wasm-encoder"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "500cbde9b4d8dfc0335ec729d226dbf083e51e47501ac71e6addaed10ccb0a51"
+checksum = "90e95b3563d164f33c1cfb0a7efbd5940c37710019be10cd09f800fdec8b0e5c"
 dependencies = [
  "leb128",
 ]
@@ -3278,9 +3278,9 @@ dependencies = [
 
 [[package]]
 name = "wasm-metadata"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f33b61754be27af5abf0fda890badb7c3265f7b634077157b4214704303ebbcc"
+checksum = "e9855ad6dd4d099fa8505f01fb0b84c7e3efd5f555207329e3ad938d5f394fe7"
 dependencies = [
  "anyhow",
  "indexmap 2.0.0",
@@ -3288,36 +3288,36 @@ dependencies = [
  "serde_derive",
  "serde_json",
  "spdx",
- "wasm-encoder 0.204.0",
- "wasmparser 0.204.0",
+ "wasm-encoder 0.205.0",
+ "wasmparser 0.205.0",
 ]
 
 [[package]]
 name = "wasm-mutate"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "34d24ec979ae72a27f3770a7db426e7f2d459e67ecf26983ca727675e4956037"
+checksum = "d92842509e0cc163a0f8f4a54e38ec180e18594b9ed3999d0a05108e70d25cb3"
 dependencies = [
  "egg",
  "log",
  "rand",
  "thiserror",
- "wasm-encoder 0.204.0",
- "wasmparser 0.204.0",
+ "wasm-encoder 0.205.0",
+ "wasmparser 0.205.0",
 ]
 
 [[package]]
 name = "wasm-smith"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e1fe1d435b8a14ebf05c2669cf76d1ca1cef6b632320c8e0b0e703ff0259a328"
+checksum = "1218f393276f7a13f6c54467434633144b46c33ecbc3cbafdc938033f0315d1a"
 dependencies = [
  "anyhow",
  "arbitrary",
  "flagset",
  "indexmap 2.0.0",
  "leb128",
- "wasm-encoder 0.204.0",
+ "wasm-encoder 0.205.0",
 ]
 
 [[package]]
@@ -3373,9 +3373,9 @@ dependencies = [
 
 [[package]]
 name = "wasmparser"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1239d539d9b92489cf729d40df694a62b09f5159f2ab058f4de15d4f820d6585"
+checksum = "1d457bb52804242e09d55a306e53ddbc65d1d29ed83db6a4eea3ed412ee0cfdf"
 dependencies = [
  "bitflags 2.4.1",
  "indexmap 2.0.0",
@@ -3393,12 +3393,12 @@ dependencies = [
 
 [[package]]
 name = "wasmprinter"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ce3e6a3111855bf59cb6a16a95e217c59eff1d30d9f09483039b81b0739c3128"
+checksum = "edcd1e00bc348d4b1c0abe913d86f4a89377cbd5c1c704d4eca5cf3492a27da8"
 dependencies = [
  "anyhow",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
 ]
 
 [[package]]
@@ -3430,8 +3430,8 @@ dependencies = [
  "target-lexicon",
  "tempfile",
  "wasi-common",
- "wasm-encoder 0.204.0",
- "wasmparser 0.204.0",
+ "wasm-encoder 0.205.0",
+ "wasmparser 0.205.0",
  "wasmtime-cache",
  "wasmtime-component-macro",
  "wasmtime-component-util",
@@ -3571,7 +3571,7 @@ dependencies = [
  "tracing",
  "walkdir",
  "wasi-common",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmtime",
  "wasmtime-cache",
  "wasmtime-cli-flags",
@@ -3585,10 +3585,10 @@ dependencies = [
  "wasmtime-wasi-nn",
  "wasmtime-wasi-threads",
  "wasmtime-wast",
- "wast 204.0.0",
+ "wast 205.0.0",
  "wat",
  "windows-sys 0.52.0",
- "wit-component 0.204.0",
+ "wit-component 0.205.0",
 ]
 
 [[package]]
@@ -3617,7 +3617,7 @@ dependencies = [
  "wasmtime",
  "wasmtime-component-util",
  "wasmtime-wit-bindgen",
- "wit-parser 0.204.0",
+ "wit-parser 0.205.0",
 ]
 
 [[package]]
@@ -3641,7 +3641,7 @@ dependencies = [
  "object 0.33.0",
  "target-lexicon",
  "thiserror",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmtime-environ",
  "wasmtime-versioned-export-macros",
 ]
@@ -3665,8 +3665,8 @@ dependencies = [
  "serde_derive",
  "target-lexicon",
  "thiserror",
- "wasm-encoder 0.204.0",
- "wasmparser 0.204.0",
+ "wasm-encoder 0.205.0",
+ "wasmparser 0.205.0",
  "wasmprinter",
  "wasmtime-component-util",
  "wasmtime-types",
@@ -3681,7 +3681,7 @@ dependencies = [
  "component-fuzz-util",
  "env_logger",
  "libfuzzer-sys",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmprinter",
  "wasmtime-environ",
  "wat",
@@ -3738,7 +3738,7 @@ dependencies = [
  "rand",
  "smallvec",
  "target-lexicon",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmtime",
  "wasmtime-fuzzing",
 ]
@@ -3758,12 +3758,12 @@ dependencies = [
  "target-lexicon",
  "tempfile",
  "v8",
- "wasm-encoder 0.204.0",
+ "wasm-encoder 0.205.0",
  "wasm-mutate",
  "wasm-smith",
  "wasm-spec-interpreter",
  "wasmi",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmprinter",
  "wasmtime",
  "wasmtime-wast",
@@ -3810,7 +3810,7 @@ dependencies = [
  "rand",
  "rustix",
  "sptr",
- "wasm-encoder 0.204.0",
+ "wasm-encoder 0.205.0",
  "wasmtime-asm-macros",
  "wasmtime-environ",
  "wasmtime-fiber",
@@ -3833,7 +3833,7 @@ dependencies = [
  "serde",
  "serde_derive",
  "thiserror",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
 ]
 
 [[package]]
@@ -3940,7 +3940,7 @@ dependencies = [
  "anyhow",
  "log",
  "wasmtime",
- "wast 204.0.0",
+ "wast 205.0.0",
 ]
 
 [[package]]
@@ -3952,7 +3952,7 @@ dependencies = [
  "gimli",
  "object 0.33.0",
  "target-lexicon",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmtime-cranelift",
  "wasmtime-environ",
  "winch-codegen",
@@ -3965,7 +3965,7 @@ dependencies = [
  "anyhow",
  "heck",
  "indexmap 2.0.0",
- "wit-parser 0.204.0",
+ "wit-parser 0.205.0",
 ]
 
 [[package]]
@@ -3983,24 +3983,24 @@ dependencies = [
 
 [[package]]
 name = "wast"
-version = "204.0.0"
+version = "205.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a0e3de19692b3d4c2fa13775271a751935decf530ae59c408c9f0b510b4ead62"
+checksum = "441a6a195b3b5245e26d450bbcc91366c6b652382a22f63cbe3c73240e13b2bb"
 dependencies = [
  "bumpalo",
  "leb128",
  "memchr",
  "unicode-width",
- "wasm-encoder 0.204.0",
+ "wasm-encoder 0.205.0",
 ]
 
 [[package]]
 name = "wat"
-version = "1.204.0"
+version = "1.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4280322d523214024d03bc05e25bdda6088d5229d9515aecd78c5914b1f3e734"
+checksum = "19832624d606e7c6bf3cd4caa73578ecec5eac30c768269256d19c79900beb18"
 dependencies = [
- "wast 204.0.0",
+ "wast 205.0.0",
 ]
 
 [[package]]
@@ -4130,7 +4130,7 @@ dependencies = [
  "regalloc2",
  "smallvec",
  "target-lexicon",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
  "wasmtime-cranelift",
  "wasmtime-environ",
 ]
@@ -4381,9 +4381,9 @@ dependencies = [
 
 [[package]]
 name = "wit-component"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "657fab6fd5f9ad3e1b7fd65a76f06ff25cac7f4fd8f885715bed4147095a6c38"
+checksum = "74841e17b2c2bfbd8ca8c45190ef85dff1c5e8659f0e2d164802ffc87dfb18c3"
 dependencies = [
  "anyhow",
  "bitflags 2.4.1",
@@ -4392,10 +4392,10 @@ dependencies = [
  "serde",
  "serde_derive",
  "serde_json",
- "wasm-encoder 0.204.0",
- "wasm-metadata 0.204.0",
- "wasmparser 0.204.0",
- "wit-parser 0.204.0",
+ "wasm-encoder 0.205.0",
+ "wasm-metadata 0.205.0",
+ "wasmparser 0.205.0",
+ "wit-parser 0.205.0",
 ]
 
 [[package]]
@@ -4418,9 +4418,9 @@ dependencies = [
 
 [[package]]
 name = "wit-parser"
-version = "0.204.0"
+version = "0.205.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bdc20f9284017574e942347e953e82fb3a0dccdfafa3beea7840b0bcbfa4fe00"
+checksum = "a3db34c7688c161ed7bd1b2f8055dca9fb2c15201db58754e9c48a0805f32e5f"
 dependencies = [
  "anyhow",
  "id-arena",
@@ -4431,7 +4431,7 @@ dependencies = [
  "serde_derive",
  "serde_json",
  "unicode-xid",
- "wasmparser 0.204.0",
+ "wasmparser 0.205.0",
 ]
 
 [[package]]
diff --git a/Cargo.toml b/Cargo.toml
index ab812cbc6..f137a2e26 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -234,15 +234,15 @@ rustix = "0.38.31"
 wit-bindgen = { version = "0.22.0", default-features = false }
 
 # wasm-tools family:
-wasmparser = "0.204.0"
-wat = "1.204.0"
-wast = "204.0.0"
-wasmprinter = "0.204.0"
-wasm-encoder = "0.204.0"
-wasm-smith = "0.204.0"
-wasm-mutate = "0.204.0"
-wit-parser = "0.204.0"
-wit-component = "0.204.0"
+wasmparser = "0.205.0"
+wat = "1.205.0"
+wast = "205.0.0"
+wasmprinter = "0.205.0"
+wasm-encoder = "0.205.0"
+wasm-smith = "0.205.0"
+wasm-mutate = "0.205.0"
+wit-parser = "0.205.0"
+wit-component = "0.205.0"
 
 # Non-Bytecode Alliance maintained dependencies:
 # --------------------------
diff --git a/RELEASES.md b/RELEASES.md
index 84af9edc6..5b232971f 100644
--- a/RELEASES.md
+++ b/RELEASES.md
@@ -139,6 +139,22 @@ Unreleased.
 
 --------------------------------------------------------------------------------
 
+## 19.0.2
+
+Released 2024-04-11.
+
+* Fix a panic when compiling invalid components.
+  [#8323](https://github.com/bytecodealliance/wasmtime/issues/8323)
+
+* Fix `bindgen!` with `trappable_error_type` using unversioned/versioned
+  packages.
+  [#8305](https://github.com/bytecodealliance/wasmtime/pull/8305)
+
+* cranelift: Include clobbers and outgoing args in stack limit.
+  [#8301](https://github.com/bytecodealliance/wasmtime/pull/8301)
+
+--------------------------------------------------------------------------------
+
 ## 19.0.1
 
 Released 2024-04-02.
@@ -248,6 +264,24 @@ Released 2024-03-20
 
 --------------------------------------------------------------------------------
 
+## 18.0.4
+
+Released 2024-04-11
+
+### Fixed
+
+* Fix `bindgen!` with `trappable_error_type` using unversioned/versioned
+  packages.
+  [#8305](https://github.com/bytecodealliance/wasmtime/pull/8305)
+
+* cranelift: Include clobbers and outgoing args in stack limit.
+  [#8301](https://github.com/bytecodealliance/wasmtime/pull/8301)
+
+* Fix a panic when compiling invalid components.
+  [#8323](https://github.com/bytecodealliance/wasmtime/issues/8323)
+
+--------------------------------------------------------------------------------
+
 ## 18.0.3
 
 Released 2024-03-12
@@ -333,6 +367,20 @@ Released 2024-02-20
 
 --------------------------------------------------------------------------------
 
+## 17.0.3
+
+Released 2024-04-11
+
+### Fixed
+
+* cranelift: Include clobbers and outgoing args in stack limit.
+  [#8301](https://github.com/bytecodealliance/wasmtime/pull/8301)
+
+* Fix a panic when compiling invalid components.
+  [#8323](https://github.com/bytecodealliance/wasmtime/issues/8323)
+
+--------------------------------------------------------------------------------
+
 ## 17.0.2
 
 Released 2024-02-28
diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index 9cc2a5740..223c7f63c 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -891,14 +891,7 @@ fn aarch64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             collector.reg_clobbers(info.clobbers);
         }
         &Inst::CallInd { ref info, .. } => {
-            match info.callee_callconv {
-                CallConv::Tail => {
-                    // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
-                    // This shouldn't be a fixed register constraint.
-                    collector.reg_fixed_use(info.rn, xreg(1))
-                }
-                _ => collector.reg_use(info.rn),
-            }
+            collector.reg_use(info.rn);
             for u in &info.uses {
                 collector.reg_fixed_use(u.vreg, u.preg);
             }
@@ -916,7 +909,11 @@ fn aarch64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             }
         }
         &Inst::ReturnCallInd { ref info, callee } => {
-            collector.reg_use(callee);
+            // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
+            // This shouldn't be a fixed register constraint, but it's not clear how to pick a
+            // register that won't be clobbered by the callee-save restore code emitted with a
+            // return_call_indirect.
+            collector.reg_fixed_use(callee, xreg(1));
             for u in &info.uses {
                 collector.reg_fixed_use(u.vreg, u.preg);
             }
diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs
index 0fa399059..b72768b2b 100644
--- a/cranelift/codegen/src/isa/riscv64/abi.rs
+++ b/cranelift/codegen/src/isa/riscv64/abi.rs
@@ -103,10 +103,9 @@ impl ABIMachineSpec for Riscv64MachineDeps {
 
         // All registers that can be used as parameters or rets.
         // both start and end are included.
-        let (x_start, x_end, f_start, f_end) = match (call_conv, args_or_rets) {
-            (isa::CallConv::Tail, _) => (9, 29, 0, 31),
-            (_, ArgsOrRets::Args) => (10, 17, 10, 17),
-            (_, ArgsOrRets::Rets) => (10, 11, 10, 11),
+        let (x_start, x_end, f_start, f_end) = match args_or_rets {
+            ArgsOrRets::Args => (10, 17, 10, 17),
+            ArgsOrRets::Rets => (10, 11, 10, 11),
         };
         let mut next_x_reg = x_start;
         let mut next_f_reg = f_start;
@@ -710,16 +709,12 @@ impl ABIMachineSpec for Riscv64MachineDeps {
         MACHINE_ENV.get_or_init(create_reg_enviroment)
     }
 
-    fn get_regs_clobbered_by_call(call_conv_of_callee: isa::CallConv) -> PRegSet {
-        if call_conv_of_callee == isa::CallConv::Tail {
-            TAIL_CLOBBERS
-        } else {
-            DEFAULT_CLOBBERS
-        }
+    fn get_regs_clobbered_by_call(_call_conv_of_callee: isa::CallConv) -> PRegSet {
+        DEFAULT_CLOBBERS
     }
 
     fn compute_frame_layout(
-        call_conv: isa::CallConv,
+        _call_conv: isa::CallConv,
         flags: &settings::Flags,
         _sig: &Signature,
         regs: &[Writable<RealReg>],
@@ -732,7 +727,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
         let mut regs: Vec<Writable<RealReg>> = regs
             .iter()
             .cloned()
-            .filter(|r| is_reg_saved_in_prologue(call_conv, r.to_reg()))
+            .filter(|r| DEFAULT_CALLEE_SAVES.contains(r.to_reg().into()))
             .collect();
 
         regs.sort_unstable();
@@ -768,7 +763,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
 
     fn gen_inline_probestack(
         insts: &mut SmallInstVec<Self::I>,
-        call_conv: isa::CallConv,
+        _call_conv: isa::CallConv,
         frame_size: u32,
         guard_size: u32,
     ) {
@@ -778,10 +773,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
         let probe_count = align_to(frame_size, guard_size) / guard_size;
 
         // Must be a caller-saved register that is not an argument.
-        let tmp = match call_conv {
-            isa::CallConv::Tail => Writable::from_reg(x_reg(1)),
-            _ => Writable::from_reg(x_reg(28)), // t3
-        };
+        let tmp = Writable::from_reg(x_reg(28)); // t3
 
         if probe_count <= PROBE_MAX_UNROLL {
             Self::gen_probestack_unroll(insts, tmp, guard_size, probe_count)
@@ -840,33 +832,34 @@ impl Riscv64ABICallSite {
     }
 }
 
-const CALLEE_SAVE_X_REG: [bool; 32] = [
-    false, false, true, false, false, false, false, false, // 0-7
-    true, true, false, false, false, false, false, false, // 8-15
-    false, false, true, true, true, true, true, true, // 16-23
-    true, true, true, true, false, false, false, false, // 24-31
-];
-const CALLEE_SAVE_F_REG: [bool; 32] = [
-    false, false, false, false, false, false, false, false, // 0-7
-    true, false, false, false, false, false, false, false, // 8-15
-    false, false, true, true, true, true, true, true, // 16-23
-    true, true, true, true, false, false, false, false, // 24-31
-];
-
-/// This should be the registers that must be saved by callee.
-#[inline]
-fn is_reg_saved_in_prologue(conv: CallConv, reg: RealReg) -> bool {
-    if conv == CallConv::Tail {
-        return false;
-    }
-
-    match reg.class() {
-        RegClass::Int => CALLEE_SAVE_X_REG[reg.hw_enc() as usize],
-        RegClass::Float => CALLEE_SAVE_F_REG[reg.hw_enc() as usize],
-        // All vector registers are caller saved.
-        RegClass::Vector => false,
-    }
-}
+// NOTE: no V regs are callee save.
+const DEFAULT_CALLEE_SAVES: PRegSet = PRegSet::empty()
+    // X Regs
+    .with(px_reg(2))
+    .with(px_reg(8))
+    .with(px_reg(9))
+    .with(px_reg(18))
+    .with(px_reg(19))
+    .with(px_reg(20))
+    .with(px_reg(21))
+    .with(px_reg(22))
+    .with(px_reg(23))
+    .with(px_reg(24))
+    .with(px_reg(25))
+    .with(px_reg(26))
+    .with(px_reg(27))
+    // F Regs
+    .with(pf_reg(8))
+    .with(pf_reg(18))
+    .with(pf_reg(19))
+    .with(pf_reg(20))
+    .with(pf_reg(21))
+    .with(pf_reg(22))
+    .with(pf_reg(23))
+    .with(pf_reg(24))
+    .with(pf_reg(25))
+    .with(pf_reg(26))
+    .with(pf_reg(27));
 
 fn compute_clobber_size(clobbers: &[Writable<RealReg>]) -> u32 {
     let mut clobbered_size = 0;
@@ -884,188 +877,78 @@ fn compute_clobber_size(clobbers: &[Writable<RealReg>]) -> u32 {
     align_to(clobbered_size, 16)
 }
 
-const fn default_clobbers() -> PRegSet {
-    PRegSet::empty()
-        .with(px_reg(1))
-        .with(px_reg(5))
-        .with(px_reg(6))
-        .with(px_reg(7))
-        .with(px_reg(10))
-        .with(px_reg(11))
-        .with(px_reg(12))
-        .with(px_reg(13))
-        .with(px_reg(14))
-        .with(px_reg(15))
-        .with(px_reg(16))
-        .with(px_reg(17))
-        .with(px_reg(28))
-        .with(px_reg(29))
-        .with(px_reg(30))
-        .with(px_reg(31))
-        // F Regs
-        .with(pf_reg(0))
-        .with(pf_reg(1))
-        .with(pf_reg(2))
-        .with(pf_reg(3))
-        .with(pf_reg(4))
-        .with(pf_reg(5))
-        .with(pf_reg(6))
-        .with(pf_reg(7))
-        .with(pf_reg(9))
-        .with(pf_reg(10))
-        .with(pf_reg(11))
-        .with(pf_reg(12))
-        .with(pf_reg(13))
-        .with(pf_reg(14))
-        .with(pf_reg(15))
-        .with(pf_reg(16))
-        .with(pf_reg(17))
-        .with(pf_reg(28))
-        .with(pf_reg(29))
-        .with(pf_reg(30))
-        .with(pf_reg(31))
-        // V Regs - All vector regs get clobbered
-        .with(pv_reg(0))
-        .with(pv_reg(1))
-        .with(pv_reg(2))
-        .with(pv_reg(3))
-        .with(pv_reg(4))
-        .with(pv_reg(5))
-        .with(pv_reg(6))
-        .with(pv_reg(7))
-        .with(pv_reg(8))
-        .with(pv_reg(9))
-        .with(pv_reg(10))
-        .with(pv_reg(11))
-        .with(pv_reg(12))
-        .with(pv_reg(13))
-        .with(pv_reg(14))
-        .with(pv_reg(15))
-        .with(pv_reg(16))
-        .with(pv_reg(17))
-        .with(pv_reg(18))
-        .with(pv_reg(19))
-        .with(pv_reg(20))
-        .with(pv_reg(21))
-        .with(pv_reg(22))
-        .with(pv_reg(23))
-        .with(pv_reg(24))
-        .with(pv_reg(25))
-        .with(pv_reg(26))
-        .with(pv_reg(27))
-        .with(pv_reg(28))
-        .with(pv_reg(29))
-        .with(pv_reg(30))
-        .with(pv_reg(31))
-}
-
-const DEFAULT_CLOBBERS: PRegSet = default_clobbers();
-
-// All allocatable registers are clobbered by calls using the `tail` calling
-// convention.
-const fn tail_clobbers() -> PRegSet {
-    PRegSet::empty()
-        // `x0` is the zero register, and not allocatable.
-        .with(px_reg(1))
-        // `x2` is the stack pointer, `x3` is the global pointer, and `x4` is
-        // the thread pointer. None are allocatable.
-        .with(px_reg(5))
-        .with(px_reg(6))
-        .with(px_reg(7))
-        // `x8` is the frame pointer, and not allocatable.
-        .with(px_reg(9))
-        .with(px_reg(10))
-        .with(px_reg(10))
-        .with(px_reg(11))
-        .with(px_reg(12))
-        .with(px_reg(13))
-        .with(px_reg(14))
-        .with(px_reg(15))
-        .with(px_reg(16))
-        .with(px_reg(17))
-        .with(px_reg(18))
-        .with(px_reg(19))
-        .with(px_reg(20))
-        .with(px_reg(21))
-        .with(px_reg(22))
-        .with(px_reg(23))
-        .with(px_reg(24))
-        .with(px_reg(25))
-        .with(px_reg(26))
-        .with(px_reg(27))
-        .with(px_reg(28))
-        .with(px_reg(29))
-        // `x30` and `x31` are reserved as scratch registers, and are not
-        // allocatable.
-        //
-        // F Regs
-        .with(pf_reg(0))
-        .with(pf_reg(1))
-        .with(pf_reg(2))
-        .with(pf_reg(3))
-        .with(pf_reg(4))
-        .with(pf_reg(5))
-        .with(pf_reg(6))
-        .with(pf_reg(7))
-        .with(pf_reg(9))
-        .with(pf_reg(10))
-        .with(pf_reg(11))
-        .with(pf_reg(12))
-        .with(pf_reg(13))
-        .with(pf_reg(14))
-        .with(pf_reg(15))
-        .with(pf_reg(16))
-        .with(pf_reg(17))
-        .with(pf_reg(18))
-        .with(pf_reg(19))
-        .with(pf_reg(20))
-        .with(pf_reg(21))
-        .with(pf_reg(22))
-        .with(pf_reg(23))
-        .with(pf_reg(24))
-        .with(pf_reg(25))
-        .with(pf_reg(26))
-        .with(pf_reg(27))
-        .with(pf_reg(28))
-        .with(pf_reg(29))
-        .with(pf_reg(30))
-        .with(pf_reg(31))
-        // V Regs
-        .with(pv_reg(0))
-        .with(pv_reg(1))
-        .with(pv_reg(2))
-        .with(pv_reg(3))
-        .with(pv_reg(4))
-        .with(pv_reg(5))
-        .with(pv_reg(6))
-        .with(pv_reg(7))
-        .with(pv_reg(8))
-        .with(pv_reg(9))
-        .with(pv_reg(10))
-        .with(pv_reg(11))
-        .with(pv_reg(12))
-        .with(pv_reg(13))
-        .with(pv_reg(14))
-        .with(pv_reg(15))
-        .with(pv_reg(16))
-        .with(pv_reg(17))
-        .with(pv_reg(18))
-        .with(pv_reg(19))
-        .with(pv_reg(20))
-        .with(pv_reg(21))
-        .with(pv_reg(22))
-        .with(pv_reg(23))
-        .with(pv_reg(24))
-        .with(pv_reg(25))
-        .with(pv_reg(26))
-        .with(pv_reg(27))
-        .with(pv_reg(28))
-        .with(pv_reg(29))
-        .with(pv_reg(30))
-        .with(pv_reg(31))
-}
-
-const TAIL_CLOBBERS: PRegSet = tail_clobbers();
+const DEFAULT_CLOBBERS: PRegSet = PRegSet::empty()
+    .with(px_reg(1))
+    .with(px_reg(5))
+    .with(px_reg(6))
+    .with(px_reg(7))
+    .with(px_reg(10))
+    .with(px_reg(11))
+    .with(px_reg(12))
+    .with(px_reg(13))
+    .with(px_reg(14))
+    .with(px_reg(15))
+    .with(px_reg(16))
+    .with(px_reg(17))
+    .with(px_reg(28))
+    .with(px_reg(29))
+    .with(px_reg(30))
+    .with(px_reg(31))
+    // F Regs
+    .with(pf_reg(0))
+    .with(pf_reg(1))
+    .with(pf_reg(2))
+    .with(pf_reg(3))
+    .with(pf_reg(4))
+    .with(pf_reg(5))
+    .with(pf_reg(6))
+    .with(pf_reg(7))
+    .with(pf_reg(9))
+    .with(pf_reg(10))
+    .with(pf_reg(11))
+    .with(pf_reg(12))
+    .with(pf_reg(13))
+    .with(pf_reg(14))
+    .with(pf_reg(15))
+    .with(pf_reg(16))
+    .with(pf_reg(17))
+    .with(pf_reg(28))
+    .with(pf_reg(29))
+    .with(pf_reg(30))
+    .with(pf_reg(31))
+    // V Regs - All vector regs get clobbered
+    .with(pv_reg(0))
+    .with(pv_reg(1))
+    .with(pv_reg(2))
+    .with(pv_reg(3))
+    .with(pv_reg(4))
+    .with(pv_reg(5))
+    .with(pv_reg(6))
+    .with(pv_reg(7))
+    .with(pv_reg(8))
+    .with(pv_reg(9))
+    .with(pv_reg(10))
+    .with(pv_reg(11))
+    .with(pv_reg(12))
+    .with(pv_reg(13))
+    .with(pv_reg(14))
+    .with(pv_reg(15))
+    .with(pv_reg(16))
+    .with(pv_reg(17))
+    .with(pv_reg(18))
+    .with(pv_reg(19))
+    .with(pv_reg(20))
+    .with(pv_reg(21))
+    .with(pv_reg(22))
+    .with(pv_reg(23))
+    .with(pv_reg(24))
+    .with(pv_reg(25))
+    .with(pv_reg(26))
+    .with(pv_reg(27))
+    .with(pv_reg(28))
+    .with(pv_reg(29))
+    .with(pv_reg(30))
+    .with(pv_reg(31));
 
 fn create_reg_enviroment() -> MachineEnv {
     // Some C Extension instructions can only use a subset of the registers.
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index 81bc3bc8c..9e26e5862 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -414,14 +414,7 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             collector.reg_clobbers(info.clobbers);
         }
         &Inst::CallInd { ref info } => {
-            if info.callee_callconv == CallConv::Tail {
-                // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
-                // This shouldn't be a fixed register constraint.
-                collector.reg_fixed_use(info.rn, x_reg(5));
-            } else {
-                collector.reg_use(info.rn);
-            }
-
+            collector.reg_use(info.rn);
             for u in &info.uses {
                 collector.reg_fixed_use(u.vreg, u.preg);
             }
@@ -439,7 +432,10 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             }
         }
         &Inst::ReturnCallInd { ref info, callee } => {
-            collector.reg_use(callee);
+            // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
+            // This shouldn't be a fixed register constraint.
+            collector.reg_fixed_use(callee, x_reg(5));
+
             for u in &info.uses {
                 collector.reg_fixed_use(u.vreg, u.preg);
             }
diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs
index ea2672328..0abb95131 100644
--- a/cranelift/codegen/src/isa/x64/abi.rs
+++ b/cranelift/codegen/src/isa/x64/abi.rs
@@ -1046,7 +1046,7 @@ impl X64CallSite {
                     distance: RelocDistance::Far,
                 });
                 ctx.emit(Inst::ReturnCallUnknown {
-                    callee: tmp2.to_writable_reg().into(),
+                    callee: tmp2.to_reg().to_reg(),
                     info,
                 });
             }
diff --git a/cranelift/codegen/src/isa/x64/inst.isle b/cranelift/codegen/src/isa/x64/inst.isle
index 919678795..2020be69e 100644
--- a/cranelift/codegen/src/isa/x64/inst.isle
+++ b/cranelift/codegen/src/isa/x64/inst.isle
@@ -367,6 +367,10 @@
                     (dst WritableGpr)
                     (dst_size OperandSize))
 
+       ;; Float comparisons/tests: cmp (b w l q) (reg addr imm) reg.
+       (XmmCmpRmRVex (op AvxOpcode)
+                     (src1 Xmm)
+                     (src2 XmmMem))
 
        ;; XMM (scalar or vector) binary op that relies on the EVEX
        ;; prefix. Takes two inputs.
@@ -502,10 +506,13 @@
                      (rhs Xmm)
                      (dst WritableXmm))
 
-       ;; Float comparisons/tests: cmp (b w l q) (reg addr imm) reg.
+       ;; Float comparisons/tests
+       ;;
+       ;; Compares `src1` against `src2` with `op`. Note that if you're testing
+       ;; `a < b` then `src1 == a` and `src2 == b`.
        (XmmCmpRmR (op SseOpcode)
-                  (src XmmMemAligned)
-                  (dst Xmm))
+                  (src1 Xmm)
+                  (src2 XmmMemAligned))
 
        ;; A binary XMM instruction with an 8-bit immediate: e.g. cmp (ps pd) imm
        ;; (reg addr) reg
@@ -538,7 +545,7 @@
                         (info BoxReturnCallInfo))
 
        ;; Tail call to an indirect destination.
-       (ReturnCallUnknown (callee RegMem)
+       (ReturnCallUnknown (callee Reg)
                           (info BoxReturnCallInfo))
 
        ;; A pseudo-instruction that captures register arguments in vregs.
@@ -1410,6 +1417,9 @@
             Vsqrtsd
             Vroundss
             Vroundsd
+            Vucomiss
+            Vucomisd
+            Vptest
           ))
 
 (type Avx512Opcode
@@ -2809,19 +2819,29 @@
       (cmp_rmi_r size (CmpOpcode.Cmp) (RegMemImm.Imm src1) src2))
 
 ;; Helper for creating `MInst.XmmCmpRmR` instructions.
-(decl xmm_cmp_rm_r (SseOpcode XmmMemAligned Xmm) ProducesFlags)
+(decl xmm_cmp_rm_r (SseOpcode Xmm XmmMem) ProducesFlags)
 (rule (xmm_cmp_rm_r opcode src1 src2)
       (ProducesFlags.ProducesFlagsSideEffect
        (MInst.XmmCmpRmR opcode src1 src2)))
 
+;; Helper for creating `MInst.XmmCmpRmRVex` instructions.
+(decl xmm_cmp_rm_r_vex (AvxOpcode Xmm XmmMem) ProducesFlags)
+(rule (xmm_cmp_rm_r_vex opcode src1 src2)
+      (ProducesFlags.ProducesFlagsSideEffect
+       (MInst.XmmCmpRmRVex opcode src1 src2)))
+
 ;; Helper for creating floating-point comparison instructions (`UCOMIS[S|D]`).
-(decl x64_ucomis (Value Value) ProducesFlags)
-(rule (x64_ucomis src1 @ (value_type $F32) src2)
-      ;; N.B.: cmp can be generated more than once, so cannot do a
-      ;; load-op merge. So `put_in_xmm` for src1, not `put_in_xmm_mem`.
-      (xmm_cmp_rm_r (SseOpcode.Ucomiss) (put_in_xmm src1) (put_in_xmm src2)))
-(rule (x64_ucomis src1 @ (value_type $F64) src2)
-      (xmm_cmp_rm_r (SseOpcode.Ucomisd) (put_in_xmm src1) (put_in_xmm src2)))
+(decl x64_ucomis (Type Xmm XmmMem) ProducesFlags)
+(rule (x64_ucomis $F32 src1 src2)
+      (xmm_cmp_rm_r (SseOpcode.Ucomiss) src1 src2))
+(rule (x64_ucomis $F64 src1 src2)
+      (xmm_cmp_rm_r (SseOpcode.Ucomisd) src1 src2))
+(rule 1 (x64_ucomis $F32 src1 src2)
+        (if-let $true (use_avx))
+        (xmm_cmp_rm_r_vex (AvxOpcode.Vucomiss) src1 src2))
+(rule 1 (x64_ucomis $F64 src1 src2)
+        (if-let $true (use_avx))
+        (xmm_cmp_rm_r_vex (AvxOpcode.Vucomisd) src1 src2))
 
 ;; Helper for creating `test` instructions.
 (decl x64_test (OperandSize GprMemImm Gpr) ProducesFlags)
@@ -2829,9 +2849,12 @@
       (cmp_rmi_r size (CmpOpcode.Test) src1 src2))
 
 ;; Helper for creating `ptest` instructions.
-(decl x64_ptest (XmmMem Xmm) ProducesFlags)
+(decl x64_ptest (Xmm XmmMem) ProducesFlags)
 (rule (x64_ptest src1 src2)
       (xmm_cmp_rm_r (SseOpcode.Ptest) src1 src2))
+(rule 1 (x64_ptest src1 src2)
+        (if-let $true (use_avx))
+        (xmm_cmp_rm_r_vex (AvxOpcode.Vptest) src1 src2))
 
 ;; Helper for creating `cmove` instructions. Note that these instructions do not
 ;; always result in a single emitted x86 instruction; e.g., XmmCmove uses jumps
@@ -4878,46 +4901,46 @@
 ;;  - equal assigns        Z = 1, P = 0, C = 0
 (decl emit_fcmp (FloatCC Value Value) FcmpCondResult)
 
-(rule (emit_fcmp (FloatCC.Equal) a @ (value_type (ty_scalar_float _)) b)
-      (FcmpCondResult.AndCondition (x64_ucomis b a) (CC.NP) (CC.Z)))
+(rule (emit_fcmp (FloatCC.Equal) a @ (value_type (ty_scalar_float ty)) b)
+      (FcmpCondResult.AndCondition (x64_ucomis ty a b) (CC.NP) (CC.Z)))
 
-(rule (emit_fcmp (FloatCC.NotEqual) a @ (value_type (ty_scalar_float _)) b)
-      (FcmpCondResult.OrCondition (x64_ucomis b a) (CC.P) (CC.NZ)))
+(rule (emit_fcmp (FloatCC.NotEqual) a @ (value_type (ty_scalar_float ty)) b)
+      (FcmpCondResult.OrCondition (x64_ucomis ty a b) (CC.P) (CC.NZ)))
 
 ;; Some scalar lowerings correspond to one condition code.
 
 (rule (emit_fcmp (FloatCC.Ordered) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.NP)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.NP)))
 (rule (emit_fcmp (FloatCC.Unordered) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.P)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.P)))
 (rule (emit_fcmp (FloatCC.OrderedNotEqual) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.NZ)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.NZ)))
 (rule (emit_fcmp (FloatCC.UnorderedOrEqual) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.Z)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.Z)))
 (rule (emit_fcmp (FloatCC.GreaterThan) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.NBE)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.NBE)))
 (rule (emit_fcmp (FloatCC.GreaterThanOrEqual) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.NB)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.NB)))
 (rule (emit_fcmp (FloatCC.UnorderedOrLessThan) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.B)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.B)))
 (rule (emit_fcmp (FloatCC.UnorderedOrLessThanOrEqual) a @ (value_type (ty_scalar_float ty)) b)
-      (FcmpCondResult.Condition (x64_ucomis b a) (CC.BE)))
+      (FcmpCondResult.Condition (x64_ucomis ty a b) (CC.BE)))
 
 ;; Other scalar lowerings are made possible by flipping the operands and
 ;; reversing the condition code.
 
 (rule (emit_fcmp (FloatCC.LessThan) a @ (value_type (ty_scalar_float ty)) b)
       ;; Same flags as `GreaterThan`.
-      (FcmpCondResult.Condition (x64_ucomis a b) (CC.NBE)))
+      (FcmpCondResult.Condition (x64_ucomis ty b a) (CC.NBE)))
 (rule (emit_fcmp (FloatCC.LessThanOrEqual) a @ (value_type (ty_scalar_float ty)) b)
       ;; Same flags as `GreaterThanOrEqual`.
-      (FcmpCondResult.Condition (x64_ucomis a b) (CC.NB)))
+      (FcmpCondResult.Condition (x64_ucomis ty b a) (CC.NB)))
 (rule (emit_fcmp (FloatCC.UnorderedOrGreaterThan) a @ (value_type (ty_scalar_float ty)) b)
       ;; Same flags as `UnorderedOrLessThan`.
-      (FcmpCondResult.Condition (x64_ucomis a b) (CC.B)))
+      (FcmpCondResult.Condition (x64_ucomis ty b a) (CC.B)))
 (rule (emit_fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) a @ (value_type (ty_scalar_float ty)) b)
       ;; Same flags as `UnorderedOrLessThanOrEqual`.
-      (FcmpCondResult.Condition (x64_ucomis a b) (CC.BE)))
+      (FcmpCondResult.Condition (x64_ucomis ty b a) (CC.BE)))
 
 ;;;; Type Guards ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs
index 992e322b4..caf21dbbb 100644
--- a/cranelift/codegen/src/isa/x64/inst/args.rs
+++ b/cranelift/codegen/src/isa/x64/inst/args.rs
@@ -1814,7 +1814,10 @@ impl AvxOpcode {
             | AvxOpcode::Vsqrtsd
             | AvxOpcode::Vroundss
             | AvxOpcode::Vroundsd
-            | AvxOpcode::Vunpcklpd => {
+            | AvxOpcode::Vunpcklpd
+            | AvxOpcode::Vptest
+            | AvxOpcode::Vucomiss
+            | AvxOpcode::Vucomisd => {
                 smallvec![InstructionSet::AVX]
             }
 
diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs
index 149fa03b8..cd43516a4 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit.rs
@@ -1647,11 +1647,14 @@ pub(crate) fn emit(
             callee,
             info: call_info,
         } => {
-            let callee = callee.with_allocs(allocs);
+            let callee = allocs.next(*callee);
 
             emit_return_call_common_sequence(allocs, sink, info, state, &call_info);
 
-            Inst::JmpUnknown { target: callee }.emit(&[], sink, info, state);
+            Inst::JmpUnknown {
+                target: RegMem::reg(callee),
+            }
+            .emit(&[], sink, info, state);
             sink.add_call_site(ir::Opcode::ReturnCallIndirect);
         }
 
@@ -2855,6 +2858,32 @@ pub(crate) fn emit(
                 .encode(sink);
         }
 
+        Inst::XmmCmpRmRVex { op, src1, src2 } => {
+            let src1 = allocs.next(src1.to_reg());
+            let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
+                RegMem::Reg { reg } => {
+                    RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
+                }
+                RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
+            };
+
+            let (prefix, map, opcode) = match op {
+                AvxOpcode::Vucomiss => (LegacyPrefixes::None, OpcodeMap::_0F, 0x2E),
+                AvxOpcode::Vucomisd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x2E),
+                AvxOpcode::Vptest => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x17),
+                _ => unimplemented!("Opcode {:?} not implemented", op),
+            };
+
+            VexInstruction::new()
+                .length(VexVectorLength::V128)
+                .prefix(prefix)
+                .map(map)
+                .opcode(opcode)
+                .rm(src2)
+                .reg(src1.to_real_reg().unwrap().hw_enc())
+                .encode(sink);
+        }
+
         Inst::XmmRmREvex {
             op,
             src1,
@@ -2964,7 +2993,7 @@ pub(crate) fn emit(
                 _ => unreachable!(),
             };
 
-            let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(lhs), dst);
+            let inst = Inst::xmm_cmp_rm_r(cmp_op, dst, RegMem::reg(lhs));
             inst.emit(&[], sink, info, state);
 
             one_way_jmp(sink, CC::NZ, do_min_max);
@@ -3171,9 +3200,9 @@ pub(crate) fn emit(
             }
         }
 
-        Inst::XmmCmpRmR { op, src, dst } => {
-            let dst = allocs.next(dst.to_reg());
-            let src = src.clone().to_reg_mem().with_allocs(allocs);
+        Inst::XmmCmpRmR { op, src1, src2 } => {
+            let src1 = allocs.next(src1.to_reg());
+            let src2 = src2.clone().to_reg_mem().with_allocs(allocs);
 
             let rex = RexFlags::clear_w();
             let (prefix, opcode, len) = match op {
@@ -3183,13 +3212,13 @@ pub(crate) fn emit(
                 _ => unimplemented!("Emit xmm cmp rm r"),
             };
 
-            match src {
+            match src2 {
                 RegMem::Reg { reg } => {
-                    emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
+                    emit_std_reg_reg(sink, prefix, opcode, len, src1, reg, rex);
                 }
                 RegMem::Mem { addr } => {
                     let addr = &addr.finalize(state, sink);
-                    emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 0);
+                    emit_std_reg_mem(sink, prefix, opcode, len, src1, addr, rex, 0);
                 }
             }
         }
@@ -3461,7 +3490,7 @@ pub(crate) fn emit(
 
             // Check for NaN.
 
-            let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), src);
+            let inst = Inst::xmm_cmp_rm_r(cmp_op, src, RegMem::reg(src));
             inst.emit(&[], sink, info, state);
 
             if *is_saturating {
@@ -3492,7 +3521,7 @@ pub(crate) fn emit(
                 );
                 inst.emit(&[], sink, info, state);
 
-                let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
+                let inst = Inst::xmm_cmp_rm_r(cmp_op, tmp_xmm, RegMem::reg(src));
                 inst.emit(&[], sink, info, state);
 
                 // Jump if >= to done.
@@ -3553,7 +3582,7 @@ pub(crate) fn emit(
                 );
                 inst.emit(&[], sink, info, state);
 
-                let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
+                let inst = Inst::xmm_cmp_rm_r(cmp_op, src, RegMem::reg(tmp_xmm));
                 inst.emit(&[], sink, info, state);
 
                 // no trap if src >= or > threshold
@@ -3570,7 +3599,7 @@ pub(crate) fn emit(
                 );
                 inst.emit(&[], sink, info, state);
 
-                let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
+                let inst = Inst::xmm_cmp_rm_r(cmp_op, tmp_xmm, RegMem::reg(src));
                 inst.emit(&[], sink, info, state);
 
                 // no trap if 0 >= src
@@ -3668,7 +3697,7 @@ pub(crate) fn emit(
             );
             inst.emit(&[], sink, info, state);
 
-            let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
+            let inst = Inst::xmm_cmp_rm_r(cmp_op, src, RegMem::reg(tmp_xmm));
             inst.emit(&[], sink, info, state);
 
             let handle_large = sink.get_label();
diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index 82a6b1d22..37ac3398b 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -191,7 +191,8 @@ impl Inst {
             | Inst::XmmToGprImmVex { op, .. }
             | Inst::XmmToGprVex { op, .. }
             | Inst::GprToXmmVex { op, .. }
-            | Inst::CvtIntToFloatVex { op, .. } => op.available_from(),
+            | Inst::CvtIntToFloatVex { op, .. }
+            | Inst::XmmCmpRmRVex { op, .. } => op.available_from(),
         }
     }
 }
@@ -396,12 +397,12 @@ impl Inst {
         }
     }
 
-    pub(crate) fn xmm_cmp_rm_r(op: SseOpcode, src: RegMem, dst: Reg) -> Inst {
-        src.assert_regclass_is(RegClass::Float);
-        debug_assert!(dst.class() == RegClass::Float);
-        let src = XmmMemAligned::new(src).unwrap();
-        let dst = Xmm::new(dst).unwrap();
-        Inst::XmmCmpRmR { op, src, dst }
+    pub(crate) fn xmm_cmp_rm_r(op: SseOpcode, src1: Reg, src2: RegMem) -> Inst {
+        src2.assert_regclass_is(RegClass::Float);
+        debug_assert!(src1.class() == RegClass::Float);
+        let src2 = XmmMemAligned::new(src2).unwrap();
+        let src1 = Xmm::new(src1).unwrap();
+        Inst::XmmCmpRmR { op, src1, src2 }
     }
 
     #[allow(dead_code)]
@@ -1316,11 +1317,11 @@ impl PrettyPrint for Inst {
                 format!("{op} {src}, {dst}")
             }
 
-            Inst::XmmCmpRmR { op, src, dst } => {
-                let dst = pretty_print_reg(dst.to_reg(), 8, allocs);
-                let src = src.pretty_print(8, allocs);
+            Inst::XmmCmpRmR { op, src1, src2 } => {
+                let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
+                let src2 = src2.pretty_print(8, allocs);
                 let op = ljustify(op.to_string());
-                format!("{op} {src}, {dst}")
+                format!("{op} {src2}, {src1}")
             }
 
             Inst::CvtIntToFloat {
@@ -1351,6 +1352,12 @@ impl PrettyPrint for Inst {
                 format!("{op} {src1}, {src2}, {dst}")
             }
 
+            Inst::XmmCmpRmRVex { op, src1, src2 } => {
+                let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
+                let src2 = src2.pretty_print(8, allocs);
+                format!("{} {src2}, {src1}", ljustify(op.to_string()))
+            }
+
             Inst::CvtUint64ToFloatSeq {
                 src,
                 dst,
@@ -1690,7 +1697,7 @@ impl PrettyPrint for Inst {
                     new_stack_arg_size,
                     tmp,
                 } = &**info;
-                let callee = callee.pretty_print(8, allocs);
+                let callee = pretty_print_reg(*callee, 8, allocs);
                 let tmp = pretty_print_reg(tmp.to_reg().to_reg(), 8, allocs);
                 let mut s =
                     format!("return_call_unknown {callee} ({new_stack_arg_size}) tmp={tmp}");
@@ -2155,9 +2162,13 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
             collector.reg_use(src.to_reg());
             dst.get_operands(collector);
         }
-        Inst::XmmCmpRmR { src, dst, .. } => {
-            collector.reg_use(dst.to_reg());
-            src.get_operands(collector);
+        Inst::XmmCmpRmR { src1, src2, .. } => {
+            collector.reg_use(src1.to_reg());
+            src2.get_operands(collector);
+        }
+        Inst::XmmCmpRmRVex { src1, src2, .. } => {
+            collector.reg_use(src1.to_reg());
+            src2.get_operands(collector);
         }
         Inst::Imm { dst, .. } => {
             collector.reg_def(dst.to_writable_reg());
@@ -2336,8 +2347,9 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
             match dest {
                 RegMem::Reg { reg } if info.callee_conv == CallConv::Winch => {
                     // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
-                    // This shouldn't be a fixed register constraint.
-                    collector.reg_fixed_use(*reg, regs::r15())
+                    // This shouldn't be a fixed register constraint. r10 is caller-saved, so this
+                    // should be safe to use.
+                    collector.reg_fixed_use(*reg, regs::r10())
                 }
                 _ => dest.get_operands(collector),
             }
@@ -2352,7 +2364,7 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
 
         Inst::ReturnCallKnown { callee, info } => {
             let ReturnCallInfo { uses, tmp, .. } = &**info;
-            collector.reg_early_def(tmp.to_writable_reg());
+            collector.reg_fixed_def(tmp.to_writable_reg(), regs::r11());
             // Same as in the `Inst::CallKnown` branch.
             debug_assert_ne!(*callee, ExternalName::LibCall(LibCall::Probestack));
             for u in uses {
@@ -2362,8 +2374,15 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
 
         Inst::ReturnCallUnknown { callee, info } => {
             let ReturnCallInfo { uses, tmp, .. } = &**info;
-            callee.get_operands(collector);
-            collector.reg_early_def(tmp.to_writable_reg());
+
+            // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
+            // This shouldn't be a fixed register constraint, but it's not clear how to
+            // pick a register that won't be clobbered by the callee-save restore code
+            // emitted with a return_call_indirect. r10 is caller-saved, so this should be
+            // safe to use.
+            collector.reg_fixed_use(*callee, regs::r10());
+
+            collector.reg_fixed_def(tmp.to_writable_reg(), regs::r11());
             for u in uses {
                 collector.reg_fixed_use(u.vreg, u.preg);
             }
diff --git a/cranelift/codegen/src/isa/x64/pcc.rs b/cranelift/codegen/src/isa/x64/pcc.rs
index bdae2d57a..c0c007f01 100644
--- a/cranelift/codegen/src/isa/x64/pcc.rs
+++ b/cranelift/codegen/src/isa/x64/pcc.rs
@@ -768,13 +768,17 @@ pub(crate) fn check(
 
         Inst::XmmMinMaxSeq { dst, .. } => ensure_no_fact(vcode, dst.to_writable_reg().to_reg()),
 
-        Inst::XmmCmpRmR { ref src, .. } => match <&RegMem>::from(src) {
-            RegMem::Mem { ref addr } => {
-                check_load(ctx, None, addr, vcode, I8X16, 128)?;
-                Ok(())
+        Inst::XmmCmpRmR {
+            ref src1, ref src2, ..
+        } => {
+            match <&RegMem>::from(src2) {
+                RegMem::Mem { ref addr } => {
+                    check_load(ctx, None, addr, vcode, I8X16, 128)?;
+                }
+                RegMem::Reg { .. } => {}
             }
-            RegMem::Reg { .. } => Ok(()),
-        },
+            ensure_no_fact(vcode, src1.to_reg())
+        }
 
         Inst::XmmRmRImm {
             dst,
@@ -809,6 +813,18 @@ pub(crate) fn check(
             ensure_no_fact(vcode, dst.to_reg())
         }
 
+        Inst::XmmCmpRmRVex {
+            ref src1, ref src2, ..
+        } => {
+            match <&RegMem>::from(src2) {
+                RegMem::Mem { ref addr } => {
+                    check_load(ctx, None, addr, vcode, F32, 32)?;
+                }
+                RegMem::Reg { .. } => {}
+            }
+            ensure_no_fact(vcode, src1.to_reg())
+        }
+
         Inst::CallKnown { .. }
         | Inst::ReturnCallKnown { .. }
         | Inst::JmpKnown { .. }
@@ -822,10 +838,9 @@ pub(crate) fn check(
         | Inst::Ud2 { .. } => Ok(()),
         Inst::Rets { .. } => Ok(()),
 
+        Inst::ReturnCallUnknown { .. } => Ok(()),
+
         Inst::CallUnknown { ref dest, .. }
-        | Inst::ReturnCallUnknown {
-            callee: ref dest, ..
-        }
         | Inst::JmpUnknown {
             target: ref dest, ..
         } => match <&RegMem>::from(dest) {
diff --git a/cranelift/wasm/src/code_translator.rs b/cranelift/wasm/src/code_translator.rs
index 2e32e0e70..502279f24 100644
--- a/cranelift/wasm/src/code_translator.rs
+++ b/cranelift/wasm/src/code_translator.rs
@@ -2543,6 +2543,10 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
         | Operator::StructGet { .. } => {
             unimplemented!("GC operators not yet implemented")
         }
+
+        Operator::GlobalAtomicGet { .. } | Operator::GlobalAtomicSet { .. } => {
+            unimplemented!("shared-everything-threads not yet implemented")
+        }
     };
     Ok(())
 }
diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock
index 263bfd6e6..61311c79f 100644
--- a/supply-chain/imports.lock
+++ b/supply-chain/imports.lock
@@ -1190,6 +1190,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wasm-encoder]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wasm-metadata]]
 version = "0.201.0"
 when = "2024-02-27"
@@ -1214,6 +1220,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wasm-metadata]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wasm-mutate]]
 version = "0.201.0"
 when = "2024-02-27"
@@ -1238,6 +1250,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wasm-mutate]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wasm-smith]]
 version = "0.201.0"
 when = "2024-02-27"
@@ -1262,6 +1280,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wasm-smith]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wasmparser]]
 version = "0.201.0"
 when = "2024-02-27"
@@ -1286,6 +1310,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wasmparser]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wasmprinter]]
 version = "0.201.0"
 when = "2024-02-27"
@@ -1310,6 +1340,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wasmprinter]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wasmtime]]
 version = "18.0.2"
 when = "2024-02-28"
@@ -1622,6 +1658,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wast]]
+version = "205.0.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wat]]
 version = "1.201.0"
 when = "2024-02-27"
@@ -1646,6 +1688,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wat]]
+version = "1.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wiggle]]
 version = "18.0.2"
 when = "2024-02-28"
@@ -1940,6 +1988,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wit-component]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.wit-parser]]
 version = "0.201.0"
 when = "2024-02-27"
@@ -1964,6 +2018,12 @@ when = "2024-04-16"
 user-id = 73222
 user-login = "wasmtime-publish"
 
+[[publisher.wit-parser]]
+version = "0.205.0"
+when = "2024-04-18"
+user-id = 73222
+user-login = "wasmtime-publish"
+
 [[publisher.witx]]
 version = "0.9.1"
 when = "2021-06-22"
diff --git a/winch/codegen/src/codegen/context.rs b/winch/codegen/src/codegen/context.rs
index 553295ec8..e613b1496 100644
--- a/winch/codegen/src/codegen/context.rs
+++ b/winch/codegen/src/codegen/context.rs
@@ -253,8 +253,8 @@ impl<'a> CodeGenContext<'a> {
         F: FnMut(&mut M, Reg, Reg, Reg, OperandSize),
         M: MacroAssembler,
     {
-        let src1 = self.pop_to_reg(masm, None);
         let src2 = self.pop_to_reg(masm, None);
+        let src1 = self.pop_to_reg(masm, None);
         let dst = self.any_gpr(masm);
         emit(masm, dst, src1.reg, src2.reg, size);
         self.free_reg(src1);
diff --git a/winch/codegen/src/isa/x64/asm.rs b/winch/codegen/src/isa/x64/asm.rs
index b0fbfd17a..8d380ea85 100644
--- a/winch/codegen/src/isa/x64/asm.rs
+++ b/winch/codegen/src/isa/x64/asm.rs
@@ -995,9 +995,9 @@ impl Assembler {
         });
     }
 
-    /// Compares values in src and dst and sets ZF, PF, and CF flags in EFLAGS
+    /// Compares values in src1 and src2 and sets ZF, PF, and CF flags in EFLAGS
     /// register.
-    pub fn ucomis(&mut self, src: Reg, dst: Reg, size: OperandSize) {
+    pub fn ucomis(&mut self, src1: Reg, src2: Reg, size: OperandSize) {
         let op = match size {
             OperandSize::S32 => SseOpcode::Ucomiss,
             OperandSize::S64 => SseOpcode::Ucomisd,
@@ -1006,8 +1006,8 @@ impl Assembler {
 
         self.emit(Inst::XmmCmpRmR {
             op,
-            src: Xmm::from(src).into(),
-            dst: dst.into(),
+            src1: src1.into(),
+            src2: Xmm::from(src2).into(),
         });
     }
 


Test patch:
diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
index 858fa07cd..7f4682966 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
@@ -3896,25 +3896,25 @@ fn test_x64_emit() {
     // XMM_CMP_RM_R
 
     insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, RegMem::reg(xmm1), xmm2),
+        Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, xmm2, RegMem::reg(xmm1)),
         "0F2ED1",
         "ucomiss %xmm1, %xmm2",
     ));
 
     insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, RegMem::reg(xmm0), xmm9),
+        Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, xmm9, RegMem::reg(xmm0)),
         "440F2EC8",
         "ucomiss %xmm0, %xmm9",
     ));
 
     insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, RegMem::reg(xmm13), xmm4),
+        Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, xmm4, RegMem::reg(xmm13)),
         "66410F2EE5",
         "ucomisd %xmm13, %xmm4",
     ));
 
     insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, RegMem::reg(xmm11), xmm12),
+        Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, xmm12, RegMem::reg(xmm11)),
         "66450F2EE3",
         "ucomisd %xmm11, %xmm12",
     ));
diff --git a/cranelift/filetests/filetests/isa/aarch64/call-pauth-bkey.clif b/cranelift/filetests/filetests/isa/aarch64/call-pauth-bkey.clif
index 4393309de..d919b28da 100644
--- a/cranelift/filetests/filetests/isa/aarch64/call-pauth-bkey.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/call-pauth-bkey.clif
@@ -99,8 +99,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x3, TestCase(%g)+0
-;   return_call_ind x3 new_stack_arg_size:0 x2=x2
+;   load_ext_name x1, TestCase(%g)+0
+;   return_call_ind x1 new_stack_arg_size:0 x2=x2
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -108,11 +108,11 @@ block0(v0: i64):
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0xc
-;   ldr x3, #0x14
+;   ldr x1, #0x14
 ;   b #0x1c
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
 ;   autibz
-;   br x3
+;   br x1
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif b/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif
index 705b6fc66..5e11b77d4 100644
--- a/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif
@@ -100,8 +100,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x3, TestCase(%g)+0
-;   return_call_ind x3 new_stack_arg_size:0 x2=x2
+;   load_ext_name x1, TestCase(%g)+0
+;   return_call_ind x1 new_stack_arg_size:0 x2=x2
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -109,11 +109,11 @@ block0(v0: i64):
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0xc
-;   ldr x3, #0x14
+;   ldr x1, #0x14
 ;   b #0x1c
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
 ;   autiaz
-;   br x3
+;   br x1
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/fuzzbug-60035.clif b/cranelift/filetests/filetests/isa/aarch64/fuzzbug-60035.clif
index fa453d757..40fd6ccfa 100644
--- a/cranelift/filetests/filetests/isa/aarch64/fuzzbug-60035.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/fuzzbug-60035.clif
@@ -15,15 +15,12 @@ block0:
 ; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
-;   str x20, [sp, #-16]!
+;   str x19, [sp, #-16]!
 ; block0:
-;   load_ext_name x1, User(userextname0)+0
-;   mov x20, x1
-;   mov x1, x20
-;   blr x1
-;   mov x1, x20
-;   blr x1
-;   ldr x20, [sp], #16
+;   load_ext_name x19, User(userextname0)+0
+;   blr x19
+;   blr x19
+;   ldr x19, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
 ;
@@ -31,18 +28,15 @@ block0:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
-;   str x20, [sp, #-0x10]!
+;   str x19, [sp, #-0x10]!
 ; block1: ; offset 0xc
-;   ldr x1, #0x14
+;   ldr x19, #0x14
 ;   b #0x1c
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 u1:7 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   mov x20, x1
-;   mov x1, x20
-;   blr x1
-;   mov x1, x20
-;   blr x1
-;   ldr x20, [sp], #0x10
+;   blr x19
+;   blr x19
+;   ldr x19, [sp], #0x10
 ;   ldp x29, x30, [sp], #0x10
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/return-call-indirect.clif b/cranelift/filetests/filetests/isa/aarch64/return-call-indirect.clif
index 96b682174..319ea508b 100644
--- a/cranelift/filetests/filetests/isa/aarch64/return-call-indirect.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/return-call-indirect.clif
@@ -33,20 +33,20 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x3, TestCase(%callee_i64)+0
-;   return_call_ind x3 new_stack_arg_size:0 x2=x2
+;   load_ext_name x1, TestCase(%callee_i64)+0
+;   return_call_ind x1 new_stack_arg_size:0 x2=x2
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   ldr x3, #0x10
+;   ldr x1, #0x10
 ;   b #0x18
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
-;   br x3
+;   br x1
 
 ;;;; Test colocated tail calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -63,20 +63,20 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x3, TestCase(%callee_i64)+0
-;   return_call_ind x3 new_stack_arg_size:0 x2=x2
+;   load_ext_name x1, TestCase(%callee_i64)+0
+;   return_call_ind x1 new_stack_arg_size:0 x2=x2
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   ldr x3, #0x10
+;   ldr x1, #0x10
 ;   b #0x18
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
-;   br x3
+;   br x1
 
 ;;;; Test passing `f64`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -112,20 +112,20 @@ block0(v0: f64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x2, TestCase(%callee_f64)+0
-;   return_call_ind x2 new_stack_arg_size:0 v0=v0
+;   load_ext_name x1, TestCase(%callee_f64)+0
+;   return_call_ind x1 new_stack_arg_size:0 v0=v0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   ldr x2, #0x10
+;   ldr x1, #0x10
 ;   b #0x18
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_f64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
-;   br x2
+;   br x1
 
 ;;;; Test passing `i8`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -163,20 +163,20 @@ block0(v0: i8):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x3, TestCase(%callee_i8)+0
-;   return_call_ind x3 new_stack_arg_size:0 x2=x2
+;   load_ext_name x1, TestCase(%callee_i8)+0
+;   return_call_ind x1 new_stack_arg_size:0 x2=x2
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   ldr x3, #0x10
+;   ldr x1, #0x10
 ;   b #0x18
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i8 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
-;   br x3
+;   br x1
 
 ;;;; Test passing many arguments on stack ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -276,9 +276,9 @@ block0:
 ;   str x23, [sp, #248]
 ;   str x24, [sp, #256]
 ;   str x25, [sp, #264]
-;   mov x10, x2
+;   mov x1, x2
 ;   ldr x2, [sp]
-;   return_call_ind x10 new_stack_arg_size:160 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
+;   return_call_ind x1 new_stack_arg_size:160 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -346,7 +346,7 @@ block0:
 ;   stur x23, [sp, #0xf8]
 ;   str x24, [sp, #0x100]
 ;   str x25, [sp, #0x108]
-;   mov x10, x2
+;   mov x1, x2
 ;   ldur x2, [sp]
 ;   add sp, sp, #0x10
 ;   ldp x19, x20, [sp], #0x10
@@ -355,5 +355,5 @@ block0:
 ;   ldp x25, x26, [sp], #0x10
 ;   ldp x27, x28, [sp], #0x10
 ;   ldp x29, x30, [sp], #0x10
-;   br x10
+;   br x1
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/return-call.clif b/cranelift/filetests/filetests/isa/aarch64/return-call.clif
index 3f8f7d20f..617bd422a 100644
--- a/cranelift/filetests/filetests/isa/aarch64/return-call.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/return-call.clif
@@ -31,20 +31,20 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x3, TestCase(%callee_i64)+0
-;   return_call_ind x3 new_stack_arg_size:0 x2=x2
+;   load_ext_name x1, TestCase(%callee_i64)+0
+;   return_call_ind x1 new_stack_arg_size:0 x2=x2
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   ldr x3, #0x10
+;   ldr x1, #0x10
 ;   b #0x18
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
-;   br x3
+;   br x1
 
 ;;;; Test colocated tail calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -101,20 +101,20 @@ block0(v0: f64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x2, TestCase(%callee_f64)+0
-;   return_call_ind x2 new_stack_arg_size:0 v0=v0
+;   load_ext_name x1, TestCase(%callee_f64)+0
+;   return_call_ind x1 new_stack_arg_size:0 v0=v0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   ldr x2, #0x10
+;   ldr x1, #0x10
 ;   b #0x18
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_f64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
-;   br x2
+;   br x1
 
 ;;;; Test passing `i8`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -150,20 +150,20 @@ block0(v0: i8):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   load_ext_name x3, TestCase(%callee_i8)+0
-;   return_call_ind x3 new_stack_arg_size:0 x2=x2
+;   load_ext_name x1, TestCase(%callee_i8)+0
+;   return_call_ind x1 new_stack_arg_size:0 x2=x2
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   ldr x3, #0x10
+;   ldr x1, #0x10
 ;   b #0x18
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i8 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ldp x29, x30, [sp], #0x10
-;   br x3
+;   br x1
 
 ;;;; Test passing many arguments on stack ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -321,8 +321,8 @@ block0:
 ;   str x23, [sp, #232]
 ;   str x24, [sp, #240]
 ;   str x25, [sp, #248]
-;   load_ext_name x14, TestCase(%tail_callee_stack_args)+0
-;   return_call_ind x14 new_stack_arg_size:160 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
+;   load_ext_name x1, TestCase(%tail_callee_stack_args)+0
+;   return_call_ind x1 new_stack_arg_size:160 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -384,7 +384,7 @@ block0:
 ;   stur x23, [sp, #0xe8]
 ;   stur x24, [sp, #0xf0]
 ;   stur x25, [sp, #0xf8]
-;   ldr x14, #0xec
+;   ldr x1, #0xec
 ;   b #0xf4
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_args 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
@@ -394,7 +394,7 @@ block0:
 ;   ldp x25, x26, [sp], #0x10
 ;   ldp x27, x28, [sp], #0x10
 ;   ldp x29, x30, [sp], #0x10
-;   br x14
+;   br x1
 
 ;;;; Test diff blocks with diff return calls with diff # of stack args ;;;;;;;;;
 
@@ -630,9 +630,9 @@ block2:
 ;   str x15, [sp, #256]
 ;   str x14, [sp, #264]
 ;   str x2, [sp, #272]
-;   load_ext_name x8, TestCase(%different_callee2)+0
+;   load_ext_name x1, TestCase(%different_callee2)+0
 ;   ldr x2, [sp]
-;   return_call_ind x8 new_stack_arg_size:176 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
+;   return_call_ind x1 new_stack_arg_size:176 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
 ; block2:
 ;   ldr x2, [sp]
 ;   str x21, [sp, #128]
@@ -655,8 +655,8 @@ block2:
 ;   str x0, [sp, #264]
 ;   str x15, [sp, #272]
 ;   str x14, [sp, #280]
-;   load_ext_name x9, TestCase(%different_callee1)+0
-;   return_call_ind x9 new_stack_arg_size:160 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
+;   load_ext_name x1, TestCase(%different_callee1)+0
+;   return_call_ind x1 new_stack_arg_size:160 x2=x2 x3=x3 x4=x4 x5=x5 x6=x6 x7=x7
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -724,7 +724,7 @@ block2:
 ;   str x15, [sp, #0x100]
 ;   str x14, [sp, #0x108]
 ;   str x2, [sp, #0x110]
-;   ldr x8, #0x100
+;   ldr x1, #0x100
 ;   b #0x108
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %different_callee2 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
@@ -736,7 +736,7 @@ block2:
 ;   ldp x25, x26, [sp], #0x10
 ;   ldp x27, x28, [sp], #0x10
 ;   ldp x29, x30, [sp], #0x10
-;   br x8
+;   br x1
 ; block3: ; offset 0x12c
 ;   ldur x2, [sp]
 ;   stur x21, [sp, #0x80]
@@ -759,7 +759,7 @@ block2:
 ;   str x0, [sp, #0x108]
 ;   str x15, [sp, #0x110]
 ;   str x14, [sp, #0x118]
-;   ldr x9, #0x188
+;   ldr x1, #0x188
 ;   b #0x190
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %different_callee1 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
@@ -771,5 +771,5 @@ block2:
 ;   ldp x27, x28, [sp], #0x10
 ;   ldp x29, x30, [sp], #0x10
 ;   add sp, sp, #0x10
-;   br x9
+;   br x1
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/tail-call-conv.clif b/cranelift/filetests/filetests/isa/aarch64/tail-call-conv.clif
index f90085e27..3311ef548 100644
--- a/cranelift/filetests/filetests/isa/aarch64/tail-call-conv.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/tail-call-conv.clif
@@ -156,8 +156,8 @@ block0:
 ;   str x24, [sp, #136]
 ;   str x25, [sp, #144]
 ;   str x26, [sp, #152]
-;   load_ext_name x1, TestCase(%tail_callee_stack_args)+0
-;   blr x1
+;   load_ext_name x15, TestCase(%tail_callee_stack_args)+0
+;   blr x15
 ;   sub sp, sp, #160
 ;   virtual_sp_offset_adjust 160
 ;   add sp, sp, #160
@@ -226,11 +226,11 @@ block0:
 ;   stur x24, [sp, #0x88]
 ;   stur x25, [sp, #0x90]
 ;   stur x26, [sp, #0x98]
-;   ldr x1, #0xe0
+;   ldr x15, #0xe0
 ;   b #0xe8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_args 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   blr x1
+;   blr x15
 ;   sub sp, sp, #0xa0
 ;   add sp, sp, #0xa0
 ;   ldp x19, x20, [sp], #0x10
@@ -424,8 +424,8 @@ block0:
 ;   virtual_sp_offset_adjust 160
 ; block0:
 ;   mov x0, sp
-;   load_ext_name x1, TestCase(%tail_callee_stack_rets)+0
-;   blr x1
+;   load_ext_name x12, TestCase(%tail_callee_stack_rets)+0
+;   blr x12
 ;   ldr x9, [sp]
 ;   ldr x11, [sp, #8]
 ;   ldr x13, [sp, #16]
@@ -457,11 +457,11 @@ block0:
 ;   sub sp, sp, #0xa0
 ; block1: ; offset 0xc
 ;   mov x0, sp
-;   ldr x1, #0x18
+;   ldr x12, #0x18
 ;   b #0x20
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_rets 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   blr x1
+;   blr x12
 ;   ldur x9, [sp]
 ;   ldur x11, [sp, #8]
 ;   ldur x13, [sp, #0x10]
@@ -711,8 +711,8 @@ block0:
 ;   str x20, [sp, #144]
 ;   str x22, [sp, #152]
 ;   add x0, sp, #160
-;   load_ext_name x1, TestCase(%tail_callee_stack_args_and_rets)+0
-;   blr x1
+;   load_ext_name x10, TestCase(%tail_callee_stack_args_and_rets)+0
+;   blr x10
 ;   sub sp, sp, #160
 ;   virtual_sp_offset_adjust 160
 ;   ldr x9, [sp, #160]
@@ -802,11 +802,11 @@ block0:
 ;   stur x20, [sp, #0x90]
 ;   stur x22, [sp, #0x98]
 ;   add x0, sp, #0xa0
-;   ldr x1, #0xe4
+;   ldr x10, #0xe4
 ;   b #0xec
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_args_and_rets 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   blr x1
+;   blr x10
 ;   sub sp, sp, #0xa0
 ;   ldur x9, [sp, #0xa0]
 ;   ldur x11, [sp, #0xa8]
diff --git a/cranelift/filetests/filetests/isa/riscv64/fuzzbug-60035.clif b/cranelift/filetests/filetests/isa/riscv64/fuzzbug-60035.clif
index 4a02ccf7f..8c5d54cea 100644
--- a/cranelift/filetests/filetests/isa/riscv64/fuzzbug-60035.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/fuzzbug-60035.clif
@@ -17,57 +17,14 @@ block0:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-192
-;   sd s1,184(sp)
-;   sd s2,176(sp)
-;   sd s3,168(sp)
-;   sd s4,160(sp)
-;   sd s5,152(sp)
-;   sd s6,144(sp)
-;   sd s7,136(sp)
-;   sd s8,128(sp)
-;   sd s9,120(sp)
-;   sd s10,112(sp)
-;   sd s11,104(sp)
-;   fsd fs2,96(sp)
-;   fsd fs3,88(sp)
-;   fsd fs4,80(sp)
-;   fsd fs5,72(sp)
-;   fsd fs6,64(sp)
-;   fsd fs7,56(sp)
-;   fsd fs8,48(sp)
-;   fsd fs9,40(sp)
-;   fsd fs10,32(sp)
-;   fsd fs11,24(sp)
+;   addi sp,sp,-16
+;   sd s1,8(sp)
 ; block0:
-;   load_sym t0,userextname0+0
-;   sd t0,0(nominal_sp)
-;   ld t0,0(nominal_sp)
-;   callind t0
-;   ld t0,0(nominal_sp)
-;   callind t0
-;   ld s1,184(sp)
-;   ld s2,176(sp)
-;   ld s3,168(sp)
-;   ld s4,160(sp)
-;   ld s5,152(sp)
-;   ld s6,144(sp)
-;   ld s7,136(sp)
-;   ld s8,128(sp)
-;   ld s9,120(sp)
-;   ld s10,112(sp)
-;   ld s11,104(sp)
-;   fld fs2,96(sp)
-;   fld fs3,88(sp)
-;   fld fs4,80(sp)
-;   fld fs5,72(sp)
-;   fld fs6,64(sp)
-;   fld fs7,56(sp)
-;   fld fs8,48(sp)
-;   fld fs9,40(sp)
-;   fld fs10,32(sp)
-;   fld fs11,24(sp)
-;   addi sp,sp,192
+;   load_sym s1,userextname0+0
+;   callind s1
+;   callind s1
+;   ld s1,8(sp)
+;   addi sp,sp,16
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
@@ -79,61 +36,18 @@ block0:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0xc0
-;   sd s1, 0xb8(sp)
-;   sd s2, 0xb0(sp)
-;   sd s3, 0xa8(sp)
-;   sd s4, 0xa0(sp)
-;   sd s5, 0x98(sp)
-;   sd s6, 0x90(sp)
-;   sd s7, 0x88(sp)
-;   sd s8, 0x80(sp)
-;   sd s9, 0x78(sp)
-;   sd s10, 0x70(sp)
-;   sd s11, 0x68(sp)
-;   fsd fs2, 0x60(sp)
-;   fsd fs3, 0x58(sp)
-;   fsd fs4, 0x50(sp)
-;   fsd fs5, 0x48(sp)
-;   fsd fs6, 0x40(sp)
-;   fsd fs7, 0x38(sp)
-;   fsd fs8, 0x30(sp)
-;   fsd fs9, 0x28(sp)
-;   fsd fs10, 0x20(sp)
-;   fsd fs11, 0x18(sp)
-; block1: ; offset 0x68
-;   auipc t0, 0
-;   ld t0, 0xc(t0)
+;   addi sp, sp, -0x10
+;   sd s1, 8(sp)
+; block1: ; offset 0x18
+;   auipc s1, 0
+;   ld s1, 0xc(s1)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 u1:7 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   sd t0, 0(sp)
-;   ld t0, 0(sp)
-;   jalr t0
-;   ld t0, 0(sp)
-;   jalr t0
-;   ld s1, 0xb8(sp)
-;   ld s2, 0xb0(sp)
-;   ld s3, 0xa8(sp)
-;   ld s4, 0xa0(sp)
-;   ld s5, 0x98(sp)
-;   ld s6, 0x90(sp)
-;   ld s7, 0x88(sp)
-;   ld s8, 0x80(sp)
-;   ld s9, 0x78(sp)
-;   ld s10, 0x70(sp)
-;   ld s11, 0x68(sp)
-;   fld fs2, 0x60(sp)
-;   fld fs3, 0x58(sp)
-;   fld fs4, 0x50(sp)
-;   fld fs5, 0x48(sp)
-;   fld fs6, 0x40(sp)
-;   fld fs7, 0x38(sp)
-;   fld fs8, 0x30(sp)
-;   fld fs9, 0x28(sp)
-;   fld fs10, 0x20(sp)
-;   fld fs11, 0x18(sp)
-;   addi sp, sp, 0xc0
+;   jalr s1
+;   jalr s1
+;   ld s1, 8(sp)
+;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/return-call-indirect.clif b/cranelift/filetests/filetests/isa/riscv64/return-call-indirect.clif
index a2a237175..f3979fb48 100644
--- a/cranelift/filetests/filetests/isa/riscv64/return-call-indirect.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/return-call-indirect.clif
@@ -12,12 +12,12 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   addi s1,s1,10
+;   addi a0,a0,10
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi s1, s1, 0xa
+;   addi a0, a0, 0xa
 ;   ret
 
 function %call_i64(i64) -> i64 tail {
@@ -35,8 +35,8 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_i64+0
-;   return_call_ind a2 new_stack_arg_size:0 s1=s1
+;   load_sym t0,%callee_i64+0
+;   return_call_ind t0 new_stack_arg_size:0 a0=a0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -45,15 +45,15 @@ block0(v0: i64):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   auipc a2, 0
-;   ld a2, 0xc(a2)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   jr a2
+;   jr t0
 
 ;;;; Test colocated tail calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -72,8 +72,8 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_i64+0
-;   return_call_ind a2 new_stack_arg_size:0 s1=s1
+;   load_sym t0,%callee_i64+0
+;   return_call_ind t0 new_stack_arg_size:0 a0=a0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -82,15 +82,15 @@ block0(v0: i64):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   auipc a2, 0
-;   ld a2, 0xc(a2)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   jr a2
+;   jr t0
 
 ;;;; Test passing `f64`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -106,7 +106,7 @@ block0(v0: f64):
 ;   lui a3,1027
 ;   slli a5,a3,40
 ;   fmv.d.x fa1,a5
-;   fadd.d ft0,ft0,fa1,rne
+;   fadd.d fa0,fa0,fa1,rne
 ;   ret
 ;
 ; Disassembled:
@@ -114,7 +114,7 @@ block0(v0: f64):
 ;   lui a3, 0x403
 ;   slli a5, a3, 0x28
 ;   fmv.d.x fa1, a5
-;   fadd.d ft0, ft0, fa1, rne
+;   fadd.d fa0, fa0, fa1, rne
 ;   ret
 
 function %call_f64(f64) -> f64 tail {
@@ -132,8 +132,8 @@ block0(v0: f64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_f64+0
-;   return_call_ind a2 new_stack_arg_size:0 ft0=ft0
+;   load_sym t0,%callee_f64+0
+;   return_call_ind t0 new_stack_arg_size:0 fa0=fa0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -142,15 +142,15 @@ block0(v0: f64):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   auipc a2, 0
-;   ld a2, 0xc(a2)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_f64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   jr a2
+;   jr t0
 
 ;;;; Test passing `i8`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -163,14 +163,14 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   andi a2,s1,255
-;   seqz s1,a2
+;   andi a2,a0,255
+;   seqz a0,a2
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   andi a2, s1, 0xff
-;   seqz s1, a2
+;   andi a2, a0, 0xff
+;   seqz a0, a2
 ;   ret
 
 function %call_i8(i8) -> i8 tail {
@@ -188,8 +188,8 @@ block0(v0: i8):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_i8+0
-;   return_call_ind a2 new_stack_arg_size:0 s1=s1
+;   load_sym t0,%callee_i8+0
+;   return_call_ind t0 new_stack_arg_size:0 a0=a0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -198,15 +198,15 @@ block0(v0: i8):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   auipc a2, 0
-;   ld a2, 0xc(a2)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i8 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   jr a2
+;   jr t0
 
 ;;;; Test passing many arguments on stack ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -249,53 +249,77 @@ block0:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-48
+;   addi sp,sp,-144
 ;   sd ra,8(sp)
-;   ld fp,48(sp)
+;   ld fp,144(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-32
+;   addi sp,sp,-128
+;   sd s1,120(sp)
+;   sd s2,112(sp)
+;   sd s3,104(sp)
+;   sd s4,96(sp)
+;   sd s5,88(sp)
+;   sd s6,80(sp)
+;   sd s7,72(sp)
+;   sd s8,64(sp)
+;   sd s9,56(sp)
+;   sd s10,48(sp)
+;   sd s11,40(sp)
 ; block0:
-;   li s1,10
-;   sd s1,16(nominal_sp)
-;   li a0,15
-;   sd a0,8(nominal_sp)
-;   li a1,20
-;   li a2,25
+;   li a0,10
+;   sd a0,16(nominal_sp)
+;   li a1,15
+;   sd a1,8(nominal_sp)
+;   li a2,20
 ;   sd a2,0(nominal_sp)
-;   li a3,30
-;   li a4,35
-;   li a5,40
-;   li a6,45
-;   li a7,50
-;   li s2,55
-;   li s3,60
-;   li s4,65
-;   li s5,70
-;   li s6,75
-;   li s7,80
-;   li s8,85
-;   li s9,90
-;   li s10,95
-;   li s11,100
-;   li t3,105
-;   li t4,110
-;   li t0,115
-;   li t1,120
-;   li t2,125
-;   li s1,130
-;   li a0,135
+;   li a3,25
+;   li a4,30
+;   li a5,35
+;   li a6,40
+;   li a7,45
+;   li s2,50
+;   li s3,55
+;   li s4,60
+;   li s5,65
+;   li s6,70
+;   li s7,75
+;   li s8,80
+;   li s9,85
+;   li s10,90
+;   li s11,95
+;   li t0,100
+;   li t1,105
+;   li t2,110
+;   li t3,115
+;   li t4,120
+;   li s1,125
+;   li a0,130
+;   li a1,135
 ;   load_sym a2,%tail_callee_stack_args+0
-;   sd t0,-48(incoming_arg)
-;   sd t1,-40(incoming_arg)
-;   sd t2,-32(incoming_arg)
+;   sd s2,-144(incoming_arg)
+;   sd s3,-136(incoming_arg)
+;   sd s4,-128(incoming_arg)
+;   sd s5,-120(incoming_arg)
+;   sd s6,-112(incoming_arg)
+;   sd s7,-104(incoming_arg)
+;   sd s8,-96(incoming_arg)
+;   sd s9,-88(incoming_arg)
+;   sd s10,-80(incoming_arg)
+;   sd s11,-72(incoming_arg)
+;   sd t0,-64(incoming_arg)
+;   sd t1,-56(incoming_arg)
+;   sd t2,-48(incoming_arg)
+;   sd t3,-40(incoming_arg)
+;   sd t4,-32(incoming_arg)
 ;   sd s1,-24(incoming_arg)
 ;   sd a0,-16(incoming_arg)
-;   ld a0,8(nominal_sp)
-;   ld s1,16(nominal_sp)
+;   sd a1,-8(incoming_arg)
+;   ld a1,8(nominal_sp)
+;   ld a0,16(nominal_sp)
 ;   mv t0,a2
 ;   ld a2,0(nominal_sp)
-;   return_call_ind t0 new_stack_arg_size:48 s1=s1 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7 s2=s2 s3=s3 s4=s4 s5=s5 s6=s6 s7=s7 s8=s8 s9=s9 s10=s10 s11=s11 t3=t3 t4=t4
+;   return_call_ind t0 new_stack_arg_size:144 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -303,58 +327,93 @@ block0:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x30
+;   addi sp, sp, -0x90
 ;   sd ra, 8(sp)
-;   ld s0, 0x30(sp)
+;   ld s0, 0x90(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x20
-; block1: ; offset 0x28
-;   addi s1, zero, 0xa
-;   sd s1, 0x10(sp)
-;   addi a0, zero, 0xf
-;   sd a0, 8(sp)
-;   addi a1, zero, 0x14
-;   addi a2, zero, 0x19
+;   addi sp, sp, -0x80
+;   sd s1, 0x78(sp)
+;   sd s2, 0x70(sp)
+;   sd s3, 0x68(sp)
+;   sd s4, 0x60(sp)
+;   sd s5, 0x58(sp)
+;   sd s6, 0x50(sp)
+;   sd s7, 0x48(sp)
+;   sd s8, 0x40(sp)
+;   sd s9, 0x38(sp)
+;   sd s10, 0x30(sp)
+;   sd s11, 0x28(sp)
+; block1: ; offset 0x54
+;   addi a0, zero, 0xa
+;   sd a0, 0x10(sp)
+;   addi a1, zero, 0xf
+;   sd a1, 8(sp)
+;   addi a2, zero, 0x14
 ;   sd a2, 0(sp)
-;   addi a3, zero, 0x1e
-;   addi a4, zero, 0x23
-;   addi a5, zero, 0x28
-;   addi a6, zero, 0x2d
-;   addi a7, zero, 0x32
-;   addi s2, zero, 0x37
-;   addi s3, zero, 0x3c
-;   addi s4, zero, 0x41
-;   addi s5, zero, 0x46
-;   addi s6, zero, 0x4b
-;   addi s7, zero, 0x50
-;   addi s8, zero, 0x55
-;   addi s9, zero, 0x5a
-;   addi s10, zero, 0x5f
-;   addi s11, zero, 0x64
-;   addi t3, zero, 0x69
-;   addi t4, zero, 0x6e
-;   addi t0, zero, 0x73
-;   addi t1, zero, 0x78
-;   addi t2, zero, 0x7d
-;   addi s1, zero, 0x82
-;   addi a0, zero, 0x87
+;   addi a3, zero, 0x19
+;   addi a4, zero, 0x1e
+;   addi a5, zero, 0x23
+;   addi a6, zero, 0x28
+;   addi a7, zero, 0x2d
+;   addi s2, zero, 0x32
+;   addi s3, zero, 0x37
+;   addi s4, zero, 0x3c
+;   addi s5, zero, 0x41
+;   addi s6, zero, 0x46
+;   addi s7, zero, 0x4b
+;   addi s8, zero, 0x50
+;   addi s9, zero, 0x55
+;   addi s10, zero, 0x5a
+;   addi s11, zero, 0x5f
+;   addi t0, zero, 0x64
+;   addi t1, zero, 0x69
+;   addi t2, zero, 0x6e
+;   addi t3, zero, 0x73
+;   addi t4, zero, 0x78
+;   addi s1, zero, 0x7d
+;   addi a0, zero, 0x82
+;   addi a1, zero, 0x87
 ;   auipc a2, 0
 ;   ld a2, 0xc(a2)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_args 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   sd t0, 0x30(sp)
-;   sd t1, 0x38(sp)
-;   sd t2, 0x40(sp)
-;   sd s1, 0x48(sp)
-;   sd a0, 0x50(sp)
-;   ld a0, 8(sp)
-;   ld s1, 0x10(sp)
+;   sd s2, 0x90(sp)
+;   sd s3, 0x98(sp)
+;   sd s4, 0xa0(sp)
+;   sd s5, 0xa8(sp)
+;   sd s6, 0xb0(sp)
+;   sd s7, 0xb8(sp)
+;   sd s8, 0xc0(sp)
+;   sd s9, 0xc8(sp)
+;   sd s10, 0xd0(sp)
+;   sd s11, 0xd8(sp)
+;   sd t0, 0xe0(sp)
+;   sd t1, 0xe8(sp)
+;   sd t2, 0xf0(sp)
+;   sd t3, 0xf8(sp)
+;   sd t4, 0x100(sp)
+;   sd s1, 0x108(sp)
+;   sd a0, 0x110(sp)
+;   sd a1, 0x118(sp)
+;   ld a1, 8(sp)
+;   ld a0, 0x10(sp)
 ;   mv t0, a2
 ;   ld a2, 0(sp)
-;   ld ra, 0x28(sp)
-;   ld s0, 0x20(sp)
-;   addi sp, sp, 0x30
+;   ld s1, 0x78(sp)
+;   ld s2, 0x70(sp)
+;   ld s3, 0x68(sp)
+;   ld s4, 0x60(sp)
+;   ld s5, 0x58(sp)
+;   ld s6, 0x50(sp)
+;   ld s7, 0x48(sp)
+;   ld s8, 0x40(sp)
+;   ld s9, 0x38(sp)
+;   ld s10, 0x30(sp)
+;   ld s11, 0x28(sp)
+;   ld ra, 0x88(sp)
+;   ld s0, 0x80(sp)
+;   addi sp, sp, 0x90
 ;   jr t0
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/return-call.clif b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
index 6f31ad93d..1b51b438e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/return-call.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
@@ -12,12 +12,12 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   addi s1,s1,10
+;   addi a0,a0,10
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi s1, s1, 0xa
+;   addi a0, a0, 0xa
 ;   ret
 
 function %call_i64(i64) -> i64 tail {
@@ -33,8 +33,8 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_i64+0
-;   return_call_ind a2 new_stack_arg_size:0 s1=s1
+;   load_sym t0,%callee_i64+0
+;   return_call_ind t0 new_stack_arg_size:0 a0=a0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -43,15 +43,15 @@ block0(v0: i64):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   auipc a2, 0
-;   ld a2, 0xc(a2)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   jr a2
+;   jr t0
 
 ;;;; Test colocated tail calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -68,7 +68,7 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   return_call TestCase(%callee_i64) new_stack_arg_size:0 s1=s1
+;   return_call TestCase(%callee_i64) new_stack_arg_size:0 a0=a0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -97,7 +97,7 @@ block0(v0: f64):
 ;   lui a3,1027
 ;   slli a5,a3,40
 ;   fmv.d.x fa1,a5
-;   fadd.d ft0,ft0,fa1,rne
+;   fadd.d fa0,fa0,fa1,rne
 ;   ret
 ;
 ; Disassembled:
@@ -105,7 +105,7 @@ block0(v0: f64):
 ;   lui a3, 0x403
 ;   slli a5, a3, 0x28
 ;   fmv.d.x fa1, a5
-;   fadd.d ft0, ft0, fa1, rne
+;   fadd.d fa0, fa0, fa1, rne
 ;   ret
 
 function %call_f64(f64) -> f64 tail {
@@ -121,8 +121,8 @@ block0(v0: f64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_f64+0
-;   return_call_ind a2 new_stack_arg_size:0 ft0=ft0
+;   load_sym t0,%callee_f64+0
+;   return_call_ind t0 new_stack_arg_size:0 fa0=fa0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -131,15 +131,15 @@ block0(v0: f64):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   auipc a2, 0
-;   ld a2, 0xc(a2)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_f64 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   jr a2
+;   jr t0
 
 ;;;; Test passing `i8`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -152,14 +152,14 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   andi a2,s1,255
-;   seqz s1,a2
+;   andi a2,a0,255
+;   seqz a0,a2
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   andi a2, s1, 0xff
-;   seqz s1, a2
+;   andi a2, a0, 0xff
+;   seqz a0, a2
 ;   ret
 
 function %call_i8(i8) -> i8 tail {
@@ -175,8 +175,8 @@ block0(v0: i8):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_i8+0
-;   return_call_ind a2 new_stack_arg_size:0 s1=s1
+;   load_sym t0,%callee_i8+0
+;   return_call_ind t0 new_stack_arg_size:0 a0=a0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -185,15 +185,15 @@ block0(v0: i8):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   auipc a2, 0
-;   ld a2, 0xc(a2)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %callee_i8 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   jr a2
+;   jr t0
 
 ;;;; Test passing many arguments on stack ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -208,15 +208,28 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   ld a4,-48(incoming_arg)
-;   ld a0,-40(incoming_arg)
-;   ld a2,-32(incoming_arg)
-;   ld a4,-24(incoming_arg)
-;   ld s1,-16(incoming_arg)
+;   ld a3,-144(incoming_arg)
+;   ld a5,-136(incoming_arg)
+;   ld a1,-128(incoming_arg)
+;   ld a3,-120(incoming_arg)
+;   ld a5,-112(incoming_arg)
+;   ld a1,-104(incoming_arg)
+;   ld a3,-96(incoming_arg)
+;   ld a5,-88(incoming_arg)
+;   ld a1,-80(incoming_arg)
+;   ld a3,-72(incoming_arg)
+;   ld a5,-64(incoming_arg)
+;   ld a1,-56(incoming_arg)
+;   ld a3,-48(incoming_arg)
+;   ld a5,-40(incoming_arg)
+;   ld a1,-32(incoming_arg)
+;   ld a3,-24(incoming_arg)
+;   ld a5,-16(incoming_arg)
+;   ld a0,-8(incoming_arg)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
-;   addi sp,sp,48
+;   addi sp,sp,144
 ;   ret
 ;
 ; Disassembled:
@@ -226,15 +239,28 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   ld a4, 0x10(sp)
-;   ld a0, 0x18(sp)
-;   ld a2, 0x20(sp)
-;   ld a4, 0x28(sp)
-;   ld s1, 0x30(sp)
+;   ld a3, 0x10(sp)
+;   ld a5, 0x18(sp)
+;   ld a1, 0x20(sp)
+;   ld a3, 0x28(sp)
+;   ld a5, 0x30(sp)
+;   ld a1, 0x38(sp)
+;   ld a3, 0x40(sp)
+;   ld a5, 0x48(sp)
+;   ld a1, 0x50(sp)
+;   ld a3, 0x58(sp)
+;   ld a5, 0x60(sp)
+;   ld a1, 0x68(sp)
+;   ld a3, 0x70(sp)
+;   ld a5, 0x78(sp)
+;   ld a1, 0x80(sp)
+;   ld a3, 0x88(sp)
+;   ld a5, 0x90(sp)
+;   ld a0, 0x98(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   addi sp, sp, 0x30
+;   addi sp, sp, 0x90
 ;   ret
 
 function %tail_caller_stack_args() -> i64 tail {
@@ -275,50 +301,74 @@ block0:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-48
+;   addi sp,sp,-144
 ;   sd ra,8(sp)
-;   ld fp,48(sp)
+;   ld fp,144(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-16
+;   addi sp,sp,-112
+;   sd s1,104(sp)
+;   sd s2,96(sp)
+;   sd s3,88(sp)
+;   sd s4,80(sp)
+;   sd s5,72(sp)
+;   sd s6,64(sp)
+;   sd s7,56(sp)
+;   sd s8,48(sp)
+;   sd s9,40(sp)
+;   sd s10,32(sp)
+;   sd s11,24(sp)
 ; block0:
-;   li s1,10
-;   sd s1,8(nominal_sp)
-;   li a0,15
-;   sd a0,0(nominal_sp)
-;   li a1,20
-;   li a2,25
-;   li a3,30
-;   li a4,35
-;   li a5,40
-;   li a6,45
-;   li a7,50
-;   li s2,55
-;   li s3,60
-;   li s4,65
-;   li s5,70
-;   li s6,75
-;   li s7,80
-;   li s8,85
-;   li s9,90
-;   li s10,95
-;   li s11,100
-;   li t3,105
-;   li t4,110
-;   li t0,115
-;   li t1,120
-;   li t2,125
-;   li s1,130
-;   li a0,135
-;   sd t0,-48(incoming_arg)
-;   sd t1,-40(incoming_arg)
-;   sd t2,-32(incoming_arg)
+;   li a0,10
+;   sd a0,8(nominal_sp)
+;   li a1,15
+;   sd a1,0(nominal_sp)
+;   li a2,20
+;   li a3,25
+;   li a4,30
+;   li a5,35
+;   li a6,40
+;   li a7,45
+;   li s2,50
+;   li s3,55
+;   li s4,60
+;   li s5,65
+;   li s6,70
+;   li s7,75
+;   li s8,80
+;   li s9,85
+;   li s10,90
+;   li s11,95
+;   li t0,100
+;   li t1,105
+;   li t2,110
+;   li t3,115
+;   li t4,120
+;   li s1,125
+;   li a0,130
+;   li a1,135
+;   sd s2,-144(incoming_arg)
+;   sd s3,-136(incoming_arg)
+;   sd s4,-128(incoming_arg)
+;   sd s5,-120(incoming_arg)
+;   sd s6,-112(incoming_arg)
+;   sd s7,-104(incoming_arg)
+;   sd s8,-96(incoming_arg)
+;   sd s9,-88(incoming_arg)
+;   sd s10,-80(incoming_arg)
+;   sd s11,-72(incoming_arg)
+;   sd t0,-64(incoming_arg)
+;   sd t1,-56(incoming_arg)
+;   sd t2,-48(incoming_arg)
+;   sd t3,-40(incoming_arg)
+;   sd t4,-32(incoming_arg)
 ;   sd s1,-24(incoming_arg)
 ;   sd a0,-16(incoming_arg)
+;   sd a1,-8(incoming_arg)
 ;   load_sym t0,%tail_callee_stack_args+0
-;   ld s1,8(nominal_sp)
-;   ld a0,0(nominal_sp)
-;   return_call_ind t0 new_stack_arg_size:48 s1=s1 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7 s2=s2 s3=s3 s4=s4 s5=s5 s6=s6 s7=s7 s8=s8 s9=s9 s10=s10 s11=s11 t3=t3 t4=t4
+;   ld a0,8(nominal_sp)
+;   ld a1,0(nominal_sp)
+;   return_call_ind t0 new_stack_arg_size:144 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -326,56 +376,91 @@ block0:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x30
+;   addi sp, sp, -0x90
 ;   sd ra, 8(sp)
-;   ld s0, 0x30(sp)
+;   ld s0, 0x90(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x10
-; block1: ; offset 0x28
-;   addi s1, zero, 0xa
-;   sd s1, 8(sp)
-;   addi a0, zero, 0xf
-;   sd a0, 0(sp)
-;   addi a1, zero, 0x14
-;   addi a2, zero, 0x19
-;   addi a3, zero, 0x1e
-;   addi a4, zero, 0x23
-;   addi a5, zero, 0x28
-;   addi a6, zero, 0x2d
-;   addi a7, zero, 0x32
-;   addi s2, zero, 0x37
-;   addi s3, zero, 0x3c
-;   addi s4, zero, 0x41
-;   addi s5, zero, 0x46
-;   addi s6, zero, 0x4b
-;   addi s7, zero, 0x50
-;   addi s8, zero, 0x55
-;   addi s9, zero, 0x5a
-;   addi s10, zero, 0x5f
-;   addi s11, zero, 0x64
-;   addi t3, zero, 0x69
-;   addi t4, zero, 0x6e
-;   addi t0, zero, 0x73
-;   addi t1, zero, 0x78
-;   addi t2, zero, 0x7d
-;   addi s1, zero, 0x82
-;   addi a0, zero, 0x87
-;   sd t0, 0x20(sp)
-;   sd t1, 0x28(sp)
-;   sd t2, 0x30(sp)
-;   sd s1, 0x38(sp)
-;   sd a0, 0x40(sp)
+;   addi sp, sp, -0x70
+;   sd s1, 0x68(sp)
+;   sd s2, 0x60(sp)
+;   sd s3, 0x58(sp)
+;   sd s4, 0x50(sp)
+;   sd s5, 0x48(sp)
+;   sd s6, 0x40(sp)
+;   sd s7, 0x38(sp)
+;   sd s8, 0x30(sp)
+;   sd s9, 0x28(sp)
+;   sd s10, 0x20(sp)
+;   sd s11, 0x18(sp)
+; block1: ; offset 0x54
+;   addi a0, zero, 0xa
+;   sd a0, 8(sp)
+;   addi a1, zero, 0xf
+;   sd a1, 0(sp)
+;   addi a2, zero, 0x14
+;   addi a3, zero, 0x19
+;   addi a4, zero, 0x1e
+;   addi a5, zero, 0x23
+;   addi a6, zero, 0x28
+;   addi a7, zero, 0x2d
+;   addi s2, zero, 0x32
+;   addi s3, zero, 0x37
+;   addi s4, zero, 0x3c
+;   addi s5, zero, 0x41
+;   addi s6, zero, 0x46
+;   addi s7, zero, 0x4b
+;   addi s8, zero, 0x50
+;   addi s9, zero, 0x55
+;   addi s10, zero, 0x5a
+;   addi s11, zero, 0x5f
+;   addi t0, zero, 0x64
+;   addi t1, zero, 0x69
+;   addi t2, zero, 0x6e
+;   addi t3, zero, 0x73
+;   addi t4, zero, 0x78
+;   addi s1, zero, 0x7d
+;   addi a0, zero, 0x82
+;   addi a1, zero, 0x87
+;   sd s2, 0x80(sp)
+;   sd s3, 0x88(sp)
+;   sd s4, 0x90(sp)
+;   sd s5, 0x98(sp)
+;   sd s6, 0xa0(sp)
+;   sd s7, 0xa8(sp)
+;   sd s8, 0xb0(sp)
+;   sd s9, 0xb8(sp)
+;   sd s10, 0xc0(sp)
+;   sd s11, 0xc8(sp)
+;   sd t0, 0xd0(sp)
+;   sd t1, 0xd8(sp)
+;   sd t2, 0xe0(sp)
+;   sd t3, 0xe8(sp)
+;   sd t4, 0xf0(sp)
+;   sd s1, 0xf8(sp)
+;   sd a0, 0x100(sp)
+;   sd a1, 0x108(sp)
 ;   auipc t0, 0
 ;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_args 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   ld s1, 8(sp)
-;   ld a0, 0(sp)
-;   ld ra, 0x18(sp)
-;   ld s0, 0x10(sp)
-;   addi sp, sp, 0x20
+;   ld a0, 8(sp)
+;   ld a1, 0(sp)
+;   ld s1, 0x68(sp)
+;   ld s2, 0x60(sp)
+;   ld s3, 0x58(sp)
+;   ld s4, 0x50(sp)
+;   ld s5, 0x48(sp)
+;   ld s6, 0x40(sp)
+;   ld s7, 0x38(sp)
+;   ld s8, 0x30(sp)
+;   ld s9, 0x28(sp)
+;   ld s10, 0x20(sp)
+;   ld s11, 0x18(sp)
+;   ld ra, 0x78(sp)
+;   ld s0, 0x70(sp)
+;   addi sp, sp, 0x80
 ;   jr t0
 
 ;;;; Test diff blocks with diff return calls with diff # of stack args ;;;;;;;;;
@@ -391,15 +476,28 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   ld a4,-48(incoming_arg)
-;   ld a0,-40(incoming_arg)
-;   ld a2,-32(incoming_arg)
-;   ld a4,-24(incoming_arg)
-;   ld s1,-16(incoming_arg)
+;   ld a3,-144(incoming_arg)
+;   ld a5,-136(incoming_arg)
+;   ld a1,-128(incoming_arg)
+;   ld a3,-120(incoming_arg)
+;   ld a5,-112(incoming_arg)
+;   ld a1,-104(incoming_arg)
+;   ld a3,-96(incoming_arg)
+;   ld a5,-88(incoming_arg)
+;   ld a1,-80(incoming_arg)
+;   ld a3,-72(incoming_arg)
+;   ld a5,-64(incoming_arg)
+;   ld a1,-56(incoming_arg)
+;   ld a3,-48(incoming_arg)
+;   ld a5,-40(incoming_arg)
+;   ld a1,-32(incoming_arg)
+;   ld a3,-24(incoming_arg)
+;   ld a5,-16(incoming_arg)
+;   ld a0,-8(incoming_arg)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
-;   addi sp,sp,48
+;   addi sp,sp,144
 ;   ret
 ;
 ; Disassembled:
@@ -409,15 +507,28 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   ld a4, 0x10(sp)
-;   ld a0, 0x18(sp)
-;   ld a2, 0x20(sp)
-;   ld a4, 0x28(sp)
-;   ld s1, 0x30(sp)
+;   ld a3, 0x10(sp)
+;   ld a5, 0x18(sp)
+;   ld a1, 0x20(sp)
+;   ld a3, 0x28(sp)
+;   ld a5, 0x30(sp)
+;   ld a1, 0x38(sp)
+;   ld a3, 0x40(sp)
+;   ld a5, 0x48(sp)
+;   ld a1, 0x50(sp)
+;   ld a3, 0x58(sp)
+;   ld a5, 0x60(sp)
+;   ld a1, 0x68(sp)
+;   ld a3, 0x70(sp)
+;   ld a5, 0x78(sp)
+;   ld a1, 0x80(sp)
+;   ld a3, 0x88(sp)
+;   ld a5, 0x90(sp)
+;   ld a0, 0x98(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   addi sp, sp, 0x30
+;   addi sp, sp, 0x90
 ;   ret
 
 function %different_callee2(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64) -> i64 tail {
@@ -431,16 +542,29 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   ld a4,-48(incoming_arg)
-;   ld a0,-40(incoming_arg)
-;   ld a2,-32(incoming_arg)
-;   ld a4,-24(incoming_arg)
+;   ld a3,-160(incoming_arg)
+;   ld a5,-152(incoming_arg)
+;   ld a1,-144(incoming_arg)
+;   ld a3,-136(incoming_arg)
+;   ld a5,-128(incoming_arg)
+;   ld a1,-120(incoming_arg)
+;   ld a3,-112(incoming_arg)
+;   ld a5,-104(incoming_arg)
+;   ld a1,-96(incoming_arg)
+;   ld a3,-88(incoming_arg)
+;   ld a5,-80(incoming_arg)
+;   ld a1,-72(incoming_arg)
+;   ld a3,-64(incoming_arg)
+;   ld a5,-56(incoming_arg)
+;   ld a1,-48(incoming_arg)
+;   ld a3,-40(incoming_arg)
+;   ld a5,-32(incoming_arg)
+;   ld a1,-24(incoming_arg)
 ;   ld a0,-16(incoming_arg)
-;   ld s1,-8(incoming_arg)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
-;   addi sp,sp,48
+;   addi sp,sp,160
 ;   ret
 ;
 ; Disassembled:
@@ -450,16 +574,29 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   ld a4, 0x10(sp)
-;   ld a0, 0x18(sp)
-;   ld a2, 0x20(sp)
-;   ld a4, 0x28(sp)
-;   ld a0, 0x30(sp)
-;   ld s1, 0x38(sp)
+;   ld a3, 0x10(sp)
+;   ld a5, 0x18(sp)
+;   ld a1, 0x20(sp)
+;   ld a3, 0x28(sp)
+;   ld a5, 0x30(sp)
+;   ld a1, 0x38(sp)
+;   ld a3, 0x40(sp)
+;   ld a5, 0x48(sp)
+;   ld a1, 0x50(sp)
+;   ld a3, 0x58(sp)
+;   ld a5, 0x60(sp)
+;   ld a1, 0x68(sp)
+;   ld a3, 0x70(sp)
+;   ld a5, 0x78(sp)
+;   ld a1, 0x80(sp)
+;   ld a3, 0x88(sp)
+;   ld a5, 0x90(sp)
+;   ld a1, 0x98(sp)
+;   ld a0, 0xa0(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   addi sp, sp, 0x30
+;   addi sp, sp, 0xa0
 ;   ret
 
 function %caller_of_different_callees(i64) -> i64 tail {
@@ -508,67 +645,104 @@ block2:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-48
+;   addi sp,sp,-160
 ;   sd ra,8(sp)
-;   ld fp,48(sp)
+;   ld fp,160(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-32
+;   addi sp,sp,-128
+;   sd s1,120(sp)
+;   sd s2,112(sp)
+;   sd s3,104(sp)
+;   sd s4,96(sp)
+;   sd s5,88(sp)
+;   sd s6,80(sp)
+;   sd s7,72(sp)
+;   sd s8,64(sp)
+;   sd s9,56(sp)
+;   sd s10,48(sp)
+;   sd s11,40(sp)
 ; block0:
-;   li a0,10
-;   sd a0,16(nominal_sp)
-;   li a0,15
-;   sd a0,8(nominal_sp)
-;   li a1,20
-;   sd a1,0(nominal_sp)
-;   li a2,25
-;   li a3,30
-;   li a4,35
-;   li a5,40
-;   li a6,45
-;   li a7,50
-;   li s2,55
-;   li s3,60
+;   li a1,10
+;   sd a1,16(nominal_sp)
+;   li a1,15
+;   sd a1,8(nominal_sp)
+;   li a2,20
+;   sd a2,0(nominal_sp)
+;   li a3,25
+;   li a4,30
+;   li a5,35
+;   li a6,40
+;   li a7,45
+;   li a2,50
+;   li a1,55
+;   li s5,60
 ;   li s4,65
-;   li s5,70
-;   li s6,75
-;   li s7,80
-;   li s8,85
-;   li s9,90
-;   li s10,95
-;   li s11,100
-;   li t3,105
-;   li t4,110
-;   li a1,115
-;   li a0,120
-;   li t2,125
-;   li t1,130
-;   li t0,135
-;   bne s1,zero,taken(label2),not_taken(label1)
+;   li s3,70
+;   li s2,75
+;   li s1,80
+;   li t4,85
+;   li t3,90
+;   li t2,95
+;   li t1,100
+;   li t0,105
+;   li s11,110
+;   li s10,115
+;   li s9,120
+;   li s8,125
+;   li s7,130
+;   li s6,135
+;   bne a0,zero,taken(label2),not_taken(label1)
 ; block1:
-;   li s1,140
-;   sd a1,-48(incoming_arg)
-;   sd a0,-40(incoming_arg)
-;   sd t2,-32(incoming_arg)
-;   sd t1,-24(incoming_arg)
-;   sd t0,-16(incoming_arg)
-;   sd s1,-8(incoming_arg)
-;   load_sym t1,%different_callee2+0
-;   ld s1,16(nominal_sp)
-;   ld a0,8(nominal_sp)
-;   ld a1,0(nominal_sp)
-;   return_call_ind t1 new_stack_arg_size:48 s1=s1 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7 s2=s2 s3=s3 s4=s4 s5=s5 s6=s6 s7=s7 s8=s8 s9=s9 s10=s10 s11=s11 t3=t3 t4=t4
+;   li a0,140
+;   sd a2,-160(incoming_arg)
+;   sd a1,-152(incoming_arg)
+;   sd s5,-144(incoming_arg)
+;   sd s4,-136(incoming_arg)
+;   sd s3,-128(incoming_arg)
+;   sd s2,-120(incoming_arg)
+;   sd s1,-112(incoming_arg)
+;   sd t4,-104(incoming_arg)
+;   sd t3,-96(incoming_arg)
+;   sd t2,-88(incoming_arg)
+;   sd t1,-80(incoming_arg)
+;   sd t0,-72(incoming_arg)
+;   sd s11,-64(incoming_arg)
+;   sd s10,-56(incoming_arg)
+;   sd s9,-48(incoming_arg)
+;   sd s8,-40(incoming_arg)
+;   sd s7,-32(incoming_arg)
+;   sd s6,-24(incoming_arg)
+;   sd a0,-16(incoming_arg)
+;   load_sym t0,%different_callee2+0
+;   ld a0,16(nominal_sp)
+;   ld a1,8(nominal_sp)
+;   ld a2,0(nominal_sp)
+;   return_call_ind t0 new_stack_arg_size:160 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
 ; block2:
-;   ld s1,16(nominal_sp)
-;   sd a1,-48(incoming_arg)
-;   sd a0,-40(incoming_arg)
-;   sd t2,-32(incoming_arg)
-;   sd t1,-24(incoming_arg)
-;   sd t0,-16(incoming_arg)
+;   ld a0,16(nominal_sp)
+;   sd a2,-144(incoming_arg)
+;   sd a1,-136(incoming_arg)
+;   sd s5,-128(incoming_arg)
+;   sd s4,-120(incoming_arg)
+;   sd s3,-112(incoming_arg)
+;   sd s2,-104(incoming_arg)
+;   sd s1,-96(incoming_arg)
+;   sd t4,-88(incoming_arg)
+;   sd t3,-80(incoming_arg)
+;   sd t2,-72(incoming_arg)
+;   sd t1,-64(incoming_arg)
+;   sd t0,-56(incoming_arg)
+;   sd s11,-48(incoming_arg)
+;   sd s10,-40(incoming_arg)
+;   sd s9,-32(incoming_arg)
+;   sd s8,-24(incoming_arg)
+;   sd s7,-16(incoming_arg)
+;   sd s6,-8(incoming_arg)
 ;   load_sym t0,%different_callee1+0
-;   ld a0,8(nominal_sp)
-;   ld a1,0(nominal_sp)
-;   return_call_ind t0 new_stack_arg_size:48 s1=s1 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7 s2=s2 s3=s3 s4=s4 s5=s5 s6=s6 s7=s7 s8=s8 s9=s9 s10=s10 s11=s11 t3=t3 t4=t4
+;   ld a1,8(nominal_sp)
+;   ld a2,0(nominal_sp)
+;   return_call_ind t0 new_stack_arg_size:144 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -576,79 +750,138 @@ block2:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x30
+;   addi sp, sp, -0xa0
 ;   sd ra, 8(sp)
-;   ld s0, 0x30(sp)
+;   ld s0, 0xa0(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x20
-; block1: ; offset 0x28
-;   addi a0, zero, 0xa
-;   sd a0, 0x10(sp)
-;   addi a0, zero, 0xf
-;   sd a0, 8(sp)
-;   addi a1, zero, 0x14
-;   sd a1, 0(sp)
-;   addi a2, zero, 0x19
-;   addi a3, zero, 0x1e
-;   addi a4, zero, 0x23
-;   addi a5, zero, 0x28
-;   addi a6, zero, 0x2d
-;   addi a7, zero, 0x32
-;   addi s2, zero, 0x37
-;   addi s3, zero, 0x3c
+;   addi sp, sp, -0x80
+;   sd s1, 0x78(sp)
+;   sd s2, 0x70(sp)
+;   sd s3, 0x68(sp)
+;   sd s4, 0x60(sp)
+;   sd s5, 0x58(sp)
+;   sd s6, 0x50(sp)
+;   sd s7, 0x48(sp)
+;   sd s8, 0x40(sp)
+;   sd s9, 0x38(sp)
+;   sd s10, 0x30(sp)
+;   sd s11, 0x28(sp)
+; block1: ; offset 0x54
+;   addi a1, zero, 0xa
+;   sd a1, 0x10(sp)
+;   addi a1, zero, 0xf
+;   sd a1, 8(sp)
+;   addi a2, zero, 0x14
+;   sd a2, 0(sp)
+;   addi a3, zero, 0x19
+;   addi a4, zero, 0x1e
+;   addi a5, zero, 0x23
+;   addi a6, zero, 0x28
+;   addi a7, zero, 0x2d
+;   addi a2, zero, 0x32
+;   addi a1, zero, 0x37
+;   addi s5, zero, 0x3c
 ;   addi s4, zero, 0x41
-;   addi s5, zero, 0x46
-;   addi s6, zero, 0x4b
-;   addi s7, zero, 0x50
-;   addi s8, zero, 0x55
-;   addi s9, zero, 0x5a
-;   addi s10, zero, 0x5f
-;   addi s11, zero, 0x64
-;   addi t3, zero, 0x69
-;   addi t4, zero, 0x6e
-;   addi a1, zero, 0x73
-;   addi a0, zero, 0x78
-;   addi t2, zero, 0x7d
-;   addi t1, zero, 0x82
-;   addi t0, zero, 0x87
-;   bnez s1, 0x50
-; block2: ; offset 0xa0
-;   addi s1, zero, 0x8c
-;   sd a1, 0x30(sp)
-;   sd a0, 0x38(sp)
-;   sd t2, 0x40(sp)
-;   sd t1, 0x48(sp)
-;   sd t0, 0x50(sp)
-;   sd s1, 0x58(sp)
-;   auipc t1, 0
-;   ld t1, 0xc(t1)
+;   addi s3, zero, 0x46
+;   addi s2, zero, 0x4b
+;   addi s1, zero, 0x50
+;   addi t4, zero, 0x55
+;   addi t3, zero, 0x5a
+;   addi t2, zero, 0x5f
+;   addi t1, zero, 0x64
+;   addi t0, zero, 0x69
+;   addi s11, zero, 0x6e
+;   addi s10, zero, 0x73
+;   addi s9, zero, 0x78
+;   addi s8, zero, 0x7d
+;   addi s7, zero, 0x82
+;   addi s6, zero, 0x87
+;   bnez a0, 0xb0
+; block2: ; offset 0xcc
+;   addi a0, zero, 0x8c
+;   sd a2, 0x90(sp)
+;   sd a1, 0x98(sp)
+;   sd s5, 0xa0(sp)
+;   sd s4, 0xa8(sp)
+;   sd s3, 0xb0(sp)
+;   sd s2, 0xb8(sp)
+;   sd s1, 0xc0(sp)
+;   sd t4, 0xc8(sp)
+;   sd t3, 0xd0(sp)
+;   sd t2, 0xd8(sp)
+;   sd t1, 0xe0(sp)
+;   sd t0, 0xe8(sp)
+;   sd s11, 0xf0(sp)
+;   sd s10, 0xf8(sp)
+;   sd s9, 0x100(sp)
+;   sd s8, 0x108(sp)
+;   sd s7, 0x110(sp)
+;   sd s6, 0x118(sp)
+;   sd a0, 0x120(sp)
+;   auipc t0, 0
+;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %different_callee2 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   ld s1, 0x10(sp)
-;   ld a0, 8(sp)
-;   ld a1, 0(sp)
-;   ld ra, 0x28(sp)
-;   ld s0, 0x20(sp)
-;   addi sp, sp, 0x30
-;   jr t1
-; block3: ; offset 0xec
-;   ld s1, 0x10(sp)
-;   sd a1, 0x30(sp)
-;   sd a0, 0x38(sp)
-;   sd t2, 0x40(sp)
-;   sd t1, 0x48(sp)
-;   sd t0, 0x50(sp)
+;   ld a0, 0x10(sp)
+;   ld a1, 8(sp)
+;   ld a2, 0(sp)
+;   ld s1, 0x78(sp)
+;   ld s2, 0x70(sp)
+;   ld s3, 0x68(sp)
+;   ld s4, 0x60(sp)
+;   ld s5, 0x58(sp)
+;   ld s6, 0x50(sp)
+;   ld s7, 0x48(sp)
+;   ld s8, 0x40(sp)
+;   ld s9, 0x38(sp)
+;   ld s10, 0x30(sp)
+;   ld s11, 0x28(sp)
+;   ld ra, 0x88(sp)
+;   ld s0, 0x80(sp)
+;   addi sp, sp, 0x90
+;   jr t0
+; block3: ; offset 0x178
+;   ld a0, 0x10(sp)
+;   sd a2, 0xa0(sp)
+;   sd a1, 0xa8(sp)
+;   sd s5, 0xb0(sp)
+;   sd s4, 0xb8(sp)
+;   sd s3, 0xc0(sp)
+;   sd s2, 0xc8(sp)
+;   sd s1, 0xd0(sp)
+;   sd t4, 0xd8(sp)
+;   sd t3, 0xe0(sp)
+;   sd t2, 0xe8(sp)
+;   sd t1, 0xf0(sp)
+;   sd t0, 0xf8(sp)
+;   sd s11, 0x100(sp)
+;   sd s10, 0x108(sp)
+;   sd s9, 0x110(sp)
+;   sd s8, 0x118(sp)
+;   sd s7, 0x120(sp)
+;   sd s6, 0x128(sp)
 ;   auipc t0, 0
 ;   ld t0, 0xc(t0)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %different_callee1 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   ld a0, 8(sp)
-;   ld a1, 0(sp)
-;   ld ra, 0x28(sp)
-;   ld s0, 0x20(sp)
-;   addi sp, sp, 0x30
+;   ld a1, 8(sp)
+;   ld a2, 0(sp)
+;   ld s1, 0x78(sp)
+;   ld s2, 0x70(sp)
+;   ld s3, 0x68(sp)
+;   ld s4, 0x60(sp)
+;   ld s5, 0x58(sp)
+;   ld s6, 0x50(sp)
+;   ld s7, 0x48(sp)
+;   ld s8, 0x40(sp)
+;   ld s9, 0x38(sp)
+;   ld s10, 0x30(sp)
+;   ld s11, 0x28(sp)
+;   ld ra, 0x88(sp)
+;   ld s0, 0x80(sp)
+;   addi sp, sp, 0xa0
 ;   jr t0
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/tail-call-conv.clif b/cranelift/filetests/filetests/isa/riscv64/tail-call-conv.clif
index 80172904f..df67e9e73 100644
--- a/cranelift/filetests/filetests/isa/riscv64/tail-call-conv.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/tail-call-conv.clif
@@ -14,15 +14,28 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   ld a4,-48(incoming_arg)
-;   ld a0,-40(incoming_arg)
-;   ld a2,-32(incoming_arg)
-;   ld a4,-24(incoming_arg)
-;   ld s1,-16(incoming_arg)
+;   ld a3,-144(incoming_arg)
+;   ld a5,-136(incoming_arg)
+;   ld a1,-128(incoming_arg)
+;   ld a3,-120(incoming_arg)
+;   ld a5,-112(incoming_arg)
+;   ld a1,-104(incoming_arg)
+;   ld a3,-96(incoming_arg)
+;   ld a5,-88(incoming_arg)
+;   ld a1,-80(incoming_arg)
+;   ld a3,-72(incoming_arg)
+;   ld a5,-64(incoming_arg)
+;   ld a1,-56(incoming_arg)
+;   ld a3,-48(incoming_arg)
+;   ld a5,-40(incoming_arg)
+;   ld a1,-32(incoming_arg)
+;   ld a3,-24(incoming_arg)
+;   ld a5,-16(incoming_arg)
+;   ld a0,-8(incoming_arg)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
-;   addi sp,sp,48
+;   addi sp,sp,144
 ;   ret
 ;
 ; Disassembled:
@@ -32,15 +45,28 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ; block1: ; offset 0x10
-;   ld a4, 0x10(sp)
-;   ld a0, 0x18(sp)
-;   ld a2, 0x20(sp)
-;   ld a4, 0x28(sp)
-;   ld s1, 0x30(sp)
+;   ld a3, 0x10(sp)
+;   ld a5, 0x18(sp)
+;   ld a1, 0x20(sp)
+;   ld a3, 0x28(sp)
+;   ld a5, 0x30(sp)
+;   ld a1, 0x38(sp)
+;   ld a3, 0x40(sp)
+;   ld a5, 0x48(sp)
+;   ld a1, 0x50(sp)
+;   ld a3, 0x58(sp)
+;   ld a5, 0x60(sp)
+;   ld a1, 0x68(sp)
+;   ld a3, 0x70(sp)
+;   ld a5, 0x78(sp)
+;   ld a1, 0x80(sp)
+;   ld a3, 0x88(sp)
+;   ld a5, 0x90(sp)
+;   ld a0, 0x98(sp)
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   addi sp, sp, 0x30
+;   addi sp, sp, 0x90
 ;   ret
 
 function %tail_caller_stack_args() -> i64 tail {
@@ -82,49 +108,84 @@ block0:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-64
-;   virtual_sp_offset_adj +48
+;   addi sp,sp,-256
+;   virtual_sp_offset_adj +144
+;   sd s1,248(sp)
+;   sd s2,240(sp)
+;   sd s3,232(sp)
+;   sd s4,224(sp)
+;   sd s5,216(sp)
+;   sd s6,208(sp)
+;   sd s7,200(sp)
+;   sd s8,192(sp)
+;   sd s9,184(sp)
+;   sd s10,176(sp)
+;   sd s11,168(sp)
 ; block0:
-;   li s1,10
-;   sd s1,8(nominal_sp)
-;   li a0,15
-;   sd a0,0(nominal_sp)
-;   li a1,20
-;   li a2,25
-;   li a3,30
-;   li a4,35
-;   li a5,40
-;   li a6,45
-;   li a7,50
-;   li s2,55
-;   li s3,60
-;   li s4,65
-;   li s5,70
-;   li s6,75
-;   li s7,80
-;   li s8,85
-;   li s9,90
-;   li s10,95
-;   li s11,100
-;   li t3,105
-;   li t4,110
-;   li t0,115
-;   li t1,120
-;   li t2,125
-;   li s1,130
-;   li a0,135
-;   sd t0,0(sp)
-;   sd t1,8(sp)
-;   sd t2,16(sp)
-;   sd s1,24(sp)
-;   sd a0,32(sp)
-;   load_sym t0,%tail_callee_stack_args+0
-;   ld s1,8(nominal_sp)
-;   ld a0,0(nominal_sp)
-;   callind t0
-;   addi sp,sp,-48
-;   virtual_sp_offset_adj +48
-;   addi sp,sp,64
+;   li a0,10
+;   sd a0,8(nominal_sp)
+;   li a1,15
+;   sd a1,0(nominal_sp)
+;   li a2,20
+;   li a3,25
+;   li a4,30
+;   li a5,35
+;   li a6,40
+;   li a7,45
+;   li s3,50
+;   li s4,55
+;   li s5,60
+;   li s6,65
+;   li s7,70
+;   li s8,75
+;   li s9,80
+;   li s10,85
+;   li s11,90
+;   li t0,95
+;   li t1,100
+;   li t2,105
+;   li t3,110
+;   li t4,115
+;   li s1,120
+;   li s2,125
+;   li a0,130
+;   li a1,135
+;   sd s3,0(sp)
+;   sd s4,8(sp)
+;   sd s5,16(sp)
+;   sd s6,24(sp)
+;   sd s7,32(sp)
+;   sd s8,40(sp)
+;   sd s9,48(sp)
+;   sd s10,56(sp)
+;   sd s11,64(sp)
+;   sd t0,72(sp)
+;   sd t1,80(sp)
+;   sd t2,88(sp)
+;   sd t3,96(sp)
+;   sd t4,104(sp)
+;   sd s1,112(sp)
+;   sd s2,120(sp)
+;   sd a0,128(sp)
+;   sd a1,136(sp)
+;   load_sym s3,%tail_callee_stack_args+0
+;   ld a0,8(nominal_sp)
+;   ld a1,0(nominal_sp)
+;   callind s3
+;   addi sp,sp,-144
+;   virtual_sp_offset_adj +144
+;   ld s1,248(sp)
+;   ld s2,240(sp)
+;   ld s3,232(sp)
+;   ld s4,224(sp)
+;   ld s5,216(sp)
+;   ld s6,208(sp)
+;   ld s7,200(sp)
+;   ld s8,192(sp)
+;   ld s9,184(sp)
+;   ld s10,176(sp)
+;   ld s11,168(sp)
+;   addi sp,sp,256
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
@@ -136,51 +197,86 @@ block0:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x40
-; block1: ; offset 0x14
-;   addi s1, zero, 0xa
-;   sd s1, 0x38(sp)
-;   addi a0, zero, 0xf
-;   sd a0, 0x30(sp)
-;   addi a1, zero, 0x14
-;   addi a2, zero, 0x19
-;   addi a3, zero, 0x1e
-;   addi a4, zero, 0x23
-;   addi a5, zero, 0x28
-;   addi a6, zero, 0x2d
-;   addi a7, zero, 0x32
-;   addi s2, zero, 0x37
-;   addi s3, zero, 0x3c
-;   addi s4, zero, 0x41
-;   addi s5, zero, 0x46
-;   addi s6, zero, 0x4b
-;   addi s7, zero, 0x50
-;   addi s8, zero, 0x55
-;   addi s9, zero, 0x5a
-;   addi s10, zero, 0x5f
-;   addi s11, zero, 0x64
-;   addi t3, zero, 0x69
-;   addi t4, zero, 0x6e
-;   addi t0, zero, 0x73
-;   addi t1, zero, 0x78
-;   addi t2, zero, 0x7d
-;   addi s1, zero, 0x82
-;   addi a0, zero, 0x87
-;   sd t0, 0(sp)
-;   sd t1, 8(sp)
-;   sd t2, 0x10(sp)
-;   sd s1, 0x18(sp)
-;   sd a0, 0x20(sp)
-;   auipc t0, 0
-;   ld t0, 0xc(t0)
+;   addi sp, sp, -0x100
+;   sd s1, 0xf8(sp)
+;   sd s2, 0xf0(sp)
+;   sd s3, 0xe8(sp)
+;   sd s4, 0xe0(sp)
+;   sd s5, 0xd8(sp)
+;   sd s6, 0xd0(sp)
+;   sd s7, 0xc8(sp)
+;   sd s8, 0xc0(sp)
+;   sd s9, 0xb8(sp)
+;   sd s10, 0xb0(sp)
+;   sd s11, 0xa8(sp)
+; block1: ; offset 0x40
+;   addi a0, zero, 0xa
+;   sd a0, 0x98(sp)
+;   addi a1, zero, 0xf
+;   sd a1, 0x90(sp)
+;   addi a2, zero, 0x14
+;   addi a3, zero, 0x19
+;   addi a4, zero, 0x1e
+;   addi a5, zero, 0x23
+;   addi a6, zero, 0x28
+;   addi a7, zero, 0x2d
+;   addi s3, zero, 0x32
+;   addi s4, zero, 0x37
+;   addi s5, zero, 0x3c
+;   addi s6, zero, 0x41
+;   addi s7, zero, 0x46
+;   addi s8, zero, 0x4b
+;   addi s9, zero, 0x50
+;   addi s10, zero, 0x55
+;   addi s11, zero, 0x5a
+;   addi t0, zero, 0x5f
+;   addi t1, zero, 0x64
+;   addi t2, zero, 0x69
+;   addi t3, zero, 0x6e
+;   addi t4, zero, 0x73
+;   addi s1, zero, 0x78
+;   addi s2, zero, 0x7d
+;   addi a0, zero, 0x82
+;   addi a1, zero, 0x87
+;   sd s3, 0(sp)
+;   sd s4, 8(sp)
+;   sd s5, 0x10(sp)
+;   sd s6, 0x18(sp)
+;   sd s7, 0x20(sp)
+;   sd s8, 0x28(sp)
+;   sd s9, 0x30(sp)
+;   sd s10, 0x38(sp)
+;   sd s11, 0x40(sp)
+;   sd t0, 0x48(sp)
+;   sd t1, 0x50(sp)
+;   sd t2, 0x58(sp)
+;   sd t3, 0x60(sp)
+;   sd t4, 0x68(sp)
+;   sd s1, 0x70(sp)
+;   sd s2, 0x78(sp)
+;   sd a0, 0x80(sp)
+;   sd a1, 0x88(sp)
+;   auipc s3, 0
+;   ld s3, 0xc(s3)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_args 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   ld s1, 0x38(sp)
-;   ld a0, 0x30(sp)
-;   jalr t0
-;   addi sp, sp, -0x30
-;   addi sp, sp, 0x40
+;   ld a0, 0x98(sp)
+;   ld a1, 0x90(sp)
+;   jalr s3
+;   addi sp, sp, -0x90
+;   ld s1, 0xf8(sp)
+;   ld s2, 0xf0(sp)
+;   ld s3, 0xe8(sp)
+;   ld s4, 0xe0(sp)
+;   ld s5, 0xd8(sp)
+;   ld s6, 0xd0(sp)
+;   ld s7, 0xc8(sp)
+;   ld s8, 0xc0(sp)
+;   ld s9, 0xb8(sp)
+;   ld s10, 0xb0(sp)
+;   ld s11, 0xa8(sp)
+;   addi sp, sp, 0x100
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -224,46 +320,89 @@ block0:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-32
+;   addi sp,sp,-128
+;   sd s1,120(sp)
+;   sd s2,112(sp)
+;   sd s3,104(sp)
+;   sd s4,96(sp)
+;   sd s5,88(sp)
+;   sd s6,80(sp)
+;   sd s7,72(sp)
+;   sd s8,64(sp)
+;   sd s9,56(sp)
+;   sd s10,48(sp)
+;   sd s11,40(sp)
 ; block0:
 ;   li a3,10
-;   sd a3,16(nominal_sp)
-;   li a0,15
-;   sd a0,8(nominal_sp)
-;   li a1,20
-;   sd a1,0(nominal_sp)
-;   li a2,25
-;   li a3,30
-;   li a4,35
-;   li a5,40
-;   li a6,45
-;   li a7,50
-;   li s2,55
-;   li s3,60
-;   li s4,65
-;   li s5,70
-;   li s6,75
-;   li s7,80
-;   li s8,85
-;   li s9,90
-;   li s10,95
-;   li s11,100
-;   li t3,105
-;   li t4,110
-;   li t0,115
-;   li t1,120
-;   li t2,125
-;   li a0,130
-;   li a1,135
-;   sd t0,0(s1)
-;   sd t1,8(s1)
-;   sd t2,16(s1)
-;   sd a0,24(s1)
-;   sd a1,32(s1)
-;   ld s1,16(nominal_sp)
-;   ld a0,8(nominal_sp)
-;   ld a1,0(nominal_sp)
-;   addi sp,sp,32
+;   sd a3,24(nominal_sp)
+;   li a1,15
+;   sd a1,16(nominal_sp)
+;   li a4,20
+;   sd a4,8(nominal_sp)
+;   li a4,25
+;   li a5,30
+;   li a2,35
+;   li s3,40
+;   li s4,45
+;   li s5,50
+;   li s6,55
+;   li s7,60
+;   li s8,65
+;   li s9,70
+;   li s10,75
+;   li s11,80
+;   li t0,85
+;   li t1,90
+;   li t2,95
+;   li a6,100
+;   li a7,105
+;   li t3,110
+;   li t4,115
+;   li s1,120
+;   li s2,125
+;   li a1,130
+;   li a3,135
+;   sd a3,0(nominal_sp)
+;   ld a3,8(nominal_sp)
+;   sd a3,0(a0)
+;   sd a4,8(a0)
+;   sd a5,16(a0)
+;   sd a2,24(a0)
+;   sd s3,32(a0)
+;   sd s4,40(a0)
+;   sd s5,48(a0)
+;   sd s6,56(a0)
+;   sd s7,64(a0)
+;   sd s8,72(a0)
+;   sd s9,80(a0)
+;   sd s10,88(a0)
+;   sd s11,96(a0)
+;   sd t0,104(a0)
+;   sd t1,112(a0)
+;   sd t2,120(a0)
+;   sd a6,128(a0)
+;   sd a7,136(a0)
+;   sd t3,144(a0)
+;   sd t4,152(a0)
+;   sd s1,160(a0)
+;   sd s2,168(a0)
+;   sd a1,176(a0)
+;   ld a3,0(nominal_sp)
+;   sd a3,184(a0)
+;   ld a0,24(nominal_sp)
+;   ld a1,16(nominal_sp)
+;   ld s1,120(sp)
+;   ld s2,112(sp)
+;   ld s3,104(sp)
+;   ld s4,96(sp)
+;   ld s5,88(sp)
+;   ld s6,80(sp)
+;   ld s7,72(sp)
+;   ld s8,64(sp)
+;   ld s9,56(sp)
+;   ld s10,48(sp)
+;   ld s11,40(sp)
+;   addi sp,sp,128
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
@@ -275,46 +414,89 @@ block0:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x20
-; block1: ; offset 0x14
+;   addi sp, sp, -0x80
+;   sd s1, 0x78(sp)
+;   sd s2, 0x70(sp)
+;   sd s3, 0x68(sp)
+;   sd s4, 0x60(sp)
+;   sd s5, 0x58(sp)
+;   sd s6, 0x50(sp)
+;   sd s7, 0x48(sp)
+;   sd s8, 0x40(sp)
+;   sd s9, 0x38(sp)
+;   sd s10, 0x30(sp)
+;   sd s11, 0x28(sp)
+; block1: ; offset 0x40
 ;   addi a3, zero, 0xa
-;   sd a3, 0x10(sp)
-;   addi a0, zero, 0xf
-;   sd a0, 8(sp)
-;   addi a1, zero, 0x14
-;   sd a1, 0(sp)
-;   addi a2, zero, 0x19
-;   addi a3, zero, 0x1e
-;   addi a4, zero, 0x23
-;   addi a5, zero, 0x28
-;   addi a6, zero, 0x2d
-;   addi a7, zero, 0x32
-;   addi s2, zero, 0x37
-;   addi s3, zero, 0x3c
-;   addi s4, zero, 0x41
-;   addi s5, zero, 0x46
-;   addi s6, zero, 0x4b
-;   addi s7, zero, 0x50
-;   addi s8, zero, 0x55
-;   addi s9, zero, 0x5a
-;   addi s10, zero, 0x5f
-;   addi s11, zero, 0x64
-;   addi t3, zero, 0x69
-;   addi t4, zero, 0x6e
-;   addi t0, zero, 0x73
-;   addi t1, zero, 0x78
-;   addi t2, zero, 0x7d
-;   addi a0, zero, 0x82
-;   addi a1, zero, 0x87
-;   sd t0, 0(s1)
-;   sd t1, 8(s1)
-;   sd t2, 0x10(s1)
-;   sd a0, 0x18(s1)
-;   sd a1, 0x20(s1)
-;   ld s1, 0x10(sp)
-;   ld a0, 8(sp)
-;   ld a1, 0(sp)
-;   addi sp, sp, 0x20
+;   sd a3, 0x18(sp)
+;   addi a1, zero, 0xf
+;   sd a1, 0x10(sp)
+;   addi a4, zero, 0x14
+;   sd a4, 8(sp)
+;   addi a4, zero, 0x19
+;   addi a5, zero, 0x1e
+;   addi a2, zero, 0x23
+;   addi s3, zero, 0x28
+;   addi s4, zero, 0x2d
+;   addi s5, zero, 0x32
+;   addi s6, zero, 0x37
+;   addi s7, zero, 0x3c
+;   addi s8, zero, 0x41
+;   addi s9, zero, 0x46
+;   addi s10, zero, 0x4b
+;   addi s11, zero, 0x50
+;   addi t0, zero, 0x55
+;   addi t1, zero, 0x5a
+;   addi t2, zero, 0x5f
+;   addi a6, zero, 0x64
+;   addi a7, zero, 0x69
+;   addi t3, zero, 0x6e
+;   addi t4, zero, 0x73
+;   addi s1, zero, 0x78
+;   addi s2, zero, 0x7d
+;   addi a1, zero, 0x82
+;   addi a3, zero, 0x87
+;   sd a3, 0(sp)
+;   ld a3, 8(sp)
+;   sd a3, 0(a0)
+;   sd a4, 8(a0)
+;   sd a5, 0x10(a0)
+;   sd a2, 0x18(a0)
+;   sd s3, 0x20(a0)
+;   sd s4, 0x28(a0)
+;   sd s5, 0x30(a0)
+;   sd s6, 0x38(a0)
+;   sd s7, 0x40(a0)
+;   sd s8, 0x48(a0)
+;   sd s9, 0x50(a0)
+;   sd s10, 0x58(a0)
+;   sd s11, 0x60(a0)
+;   sd t0, 0x68(a0)
+;   sd t1, 0x70(a0)
+;   sd t2, 0x78(a0)
+;   sd a6, 0x80(a0)
+;   sd a7, 0x88(a0)
+;   sd t3, 0x90(a0)
+;   sd t4, 0x98(a0)
+;   sd s1, 0xa0(a0)
+;   sd s2, 0xa8(a0)
+;   sd a1, 0xb0(a0)
+;   ld a3, 0(sp)
+;   sd a3, 0xb8(a0)
+;   ld a0, 0x18(sp)
+;   ld a1, 0x10(sp)
+;   ld s1, 0x78(sp)
+;   ld s2, 0x70(sp)
+;   ld s3, 0x68(sp)
+;   ld s4, 0x60(sp)
+;   ld s5, 0x58(sp)
+;   ld s6, 0x50(sp)
+;   ld s7, 0x48(sp)
+;   ld s8, 0x40(sp)
+;   ld s9, 0x38(sp)
+;   ld s10, 0x30(sp)
+;   ld s11, 0x28(sp)
+;   addi sp, sp, 0x80
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -333,18 +515,37 @@ block0:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-48
-;   virtual_sp_offset_adj +48
+;   addi sp,sp,-192
+;   virtual_sp_offset_adj +192
 ; block0:
-;   load_addr s1,0(sp)
-;   load_sym t0,%tail_callee_stack_rets+0
-;   callind t0
-;   ld a0,0(sp)
-;   ld a2,8(sp)
-;   ld a4,16(sp)
-;   ld a0,24(sp)
-;   ld s1,32(sp)
-;   addi sp,sp,48
+;   load_addr a0,0(sp)
+;   load_sym a4,%tail_callee_stack_rets+0
+;   callind a4
+;   ld a5,0(sp)
+;   ld a1,8(sp)
+;   ld a3,16(sp)
+;   ld a5,24(sp)
+;   ld a1,32(sp)
+;   ld a3,40(sp)
+;   ld a5,48(sp)
+;   ld a1,56(sp)
+;   ld a3,64(sp)
+;   ld a5,72(sp)
+;   ld a1,80(sp)
+;   ld a3,88(sp)
+;   ld a5,96(sp)
+;   ld a1,104(sp)
+;   ld a3,112(sp)
+;   ld a5,120(sp)
+;   ld a1,128(sp)
+;   ld a3,136(sp)
+;   ld a5,144(sp)
+;   ld a1,152(sp)
+;   ld a3,160(sp)
+;   ld a5,168(sp)
+;   ld a1,176(sp)
+;   ld a0,184(sp)
+;   addi sp,sp,192
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
@@ -356,21 +557,40 @@ block0:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x30
+;   addi sp, sp, -0xc0
 ; block1: ; offset 0x14
-;   mv s1, sp
-;   auipc t0, 0
-;   ld t0, 0xc(t0)
+;   mv a0, sp
+;   auipc a4, 0
+;   ld a4, 0xc(a4)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_rets 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   jalr t0
-;   ld a0, 0(sp)
-;   ld a2, 8(sp)
-;   ld a4, 0x10(sp)
-;   ld a0, 0x18(sp)
-;   ld s1, 0x20(sp)
-;   addi sp, sp, 0x30
+;   jalr a4
+;   ld a5, 0(sp)
+;   ld a1, 8(sp)
+;   ld a3, 0x10(sp)
+;   ld a5, 0x18(sp)
+;   ld a1, 0x20(sp)
+;   ld a3, 0x28(sp)
+;   ld a5, 0x30(sp)
+;   ld a1, 0x38(sp)
+;   ld a3, 0x40(sp)
+;   ld a5, 0x48(sp)
+;   ld a1, 0x50(sp)
+;   ld a3, 0x58(sp)
+;   ld a5, 0x60(sp)
+;   ld a1, 0x68(sp)
+;   ld a3, 0x70(sp)
+;   ld a5, 0x78(sp)
+;   ld a1, 0x80(sp)
+;   ld a3, 0x88(sp)
+;   ld a5, 0x90(sp)
+;   ld a1, 0x98(sp)
+;   ld a3, 0xa0(sp)
+;   ld a5, 0xa8(sp)
+;   ld a1, 0xb0(sp)
+;   ld a0, 0xb8(sp)
+;   addi sp, sp, 0xc0
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -389,30 +609,84 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-32
+;   addi sp,sp,-128
+;   sd s1,120(sp)
+;   sd s2,112(sp)
+;   sd s3,104(sp)
+;   sd s4,96(sp)
+;   sd s5,88(sp)
+;   sd s6,80(sp)
+;   sd s7,72(sp)
+;   sd s8,64(sp)
+;   sd s9,56(sp)
+;   sd s10,48(sp)
+;   sd s11,40(sp)
 ; block0:
 ;   sd a0,0(nominal_sp)
-;   sd a2,8(nominal_sp)
-;   sd a4,16(nominal_sp)
-;   ld a4,-48(incoming_arg)
+;   sd a1,8(nominal_sp)
+;   ld s4,-160(incoming_arg)
+;   ld s6,-152(incoming_arg)
+;   ld s8,-144(incoming_arg)
+;   ld s10,-136(incoming_arg)
+;   ld t0,-128(incoming_arg)
+;   ld t1,-120(incoming_arg)
+;   ld t4,-112(incoming_arg)
+;   ld t3,-104(incoming_arg)
+;   ld s1,-96(incoming_arg)
+;   ld s3,-88(incoming_arg)
+;   ld s5,-80(incoming_arg)
+;   ld s7,-72(incoming_arg)
+;   ld s9,-64(incoming_arg)
+;   ld s11,-56(incoming_arg)
+;   ld a1,-48(incoming_arg)
 ;   ld a0,-40(incoming_arg)
-;   ld t2,-32(incoming_arg)
-;   ld t1,-24(incoming_arg)
-;   ld t0,-16(incoming_arg)
-;   ld a2,-8(incoming_arg)
-;   sd a4,0(a2)
-;   sd a0,8(a2)
-;   sd t2,16(a2)
-;   sd t1,24(a2)
-;   sd t0,32(a2)
+;   ld s2,-32(incoming_arg)
+;   ld t2,-24(incoming_arg)
+;   sd t2,16(nominal_sp)
+;   ld t2,-16(incoming_arg)
+;   sd a2,0(t2)
+;   sd a3,8(t2)
+;   sd a4,16(t2)
+;   sd a5,24(t2)
+;   sd a6,32(t2)
+;   sd a7,40(t2)
+;   sd s4,48(t2)
+;   sd s6,56(t2)
+;   sd s8,64(t2)
+;   sd s10,72(t2)
+;   sd t0,80(t2)
+;   sd t1,88(t2)
+;   sd t4,96(t2)
+;   sd t3,104(t2)
+;   sd s1,112(t2)
+;   sd s3,120(t2)
+;   sd s5,128(t2)
+;   sd s7,136(t2)
+;   sd s9,144(t2)
+;   sd s11,152(t2)
+;   sd a1,160(t2)
+;   sd a0,168(t2)
+;   sd s2,176(t2)
+;   ld a1,16(nominal_sp)
+;   sd a1,184(t2)
 ;   ld a0,0(nominal_sp)
-;   ld a2,8(nominal_sp)
-;   ld a4,16(nominal_sp)
-;   addi sp,sp,32
+;   ld a1,8(nominal_sp)
+;   ld s1,120(sp)
+;   ld s2,112(sp)
+;   ld s3,104(sp)
+;   ld s4,96(sp)
+;   ld s5,88(sp)
+;   ld s6,80(sp)
+;   ld s7,72(sp)
+;   ld s8,64(sp)
+;   ld s9,56(sp)
+;   ld s10,48(sp)
+;   ld s11,40(sp)
+;   addi sp,sp,128
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
-;   addi sp,sp,48
+;   addi sp,sp,160
 ;   ret
 ;
 ; Disassembled:
@@ -421,30 +695,84 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x20
-; block1: ; offset 0x14
+;   addi sp, sp, -0x80
+;   sd s1, 0x78(sp)
+;   sd s2, 0x70(sp)
+;   sd s3, 0x68(sp)
+;   sd s4, 0x60(sp)
+;   sd s5, 0x58(sp)
+;   sd s6, 0x50(sp)
+;   sd s7, 0x48(sp)
+;   sd s8, 0x40(sp)
+;   sd s9, 0x38(sp)
+;   sd s10, 0x30(sp)
+;   sd s11, 0x28(sp)
+; block1: ; offset 0x40
 ;   sd a0, 0(sp)
-;   sd a2, 8(sp)
-;   sd a4, 0x10(sp)
-;   ld a4, 0x30(sp)
-;   ld a0, 0x38(sp)
-;   ld t2, 0x40(sp)
-;   ld t1, 0x48(sp)
-;   ld t0, 0x50(sp)
-;   ld a2, 0x58(sp)
-;   sd a4, 0(a2)
-;   sd a0, 8(a2)
-;   sd t2, 0x10(a2)
-;   sd t1, 0x18(a2)
-;   sd t0, 0x20(a2)
+;   sd a1, 8(sp)
+;   ld s4, 0x90(sp)
+;   ld s6, 0x98(sp)
+;   ld s8, 0xa0(sp)
+;   ld s10, 0xa8(sp)
+;   ld t0, 0xb0(sp)
+;   ld t1, 0xb8(sp)
+;   ld t4, 0xc0(sp)
+;   ld t3, 0xc8(sp)
+;   ld s1, 0xd0(sp)
+;   ld s3, 0xd8(sp)
+;   ld s5, 0xe0(sp)
+;   ld s7, 0xe8(sp)
+;   ld s9, 0xf0(sp)
+;   ld s11, 0xf8(sp)
+;   ld a1, 0x100(sp)
+;   ld a0, 0x108(sp)
+;   ld s2, 0x110(sp)
+;   ld t2, 0x118(sp)
+;   sd t2, 0x10(sp)
+;   ld t2, 0x120(sp)
+;   sd a2, 0(t2)
+;   sd a3, 8(t2)
+;   sd a4, 0x10(t2)
+;   sd a5, 0x18(t2)
+;   sd a6, 0x20(t2)
+;   sd a7, 0x28(t2)
+;   sd s4, 0x30(t2)
+;   sd s6, 0x38(t2)
+;   sd s8, 0x40(t2)
+;   sd s10, 0x48(t2)
+;   sd t0, 0x50(t2)
+;   sd t1, 0x58(t2)
+;   sd t4, 0x60(t2)
+;   sd t3, 0x68(t2)
+;   sd s1, 0x70(t2)
+;   sd s3, 0x78(t2)
+;   sd s5, 0x80(t2)
+;   sd s7, 0x88(t2)
+;   sd s9, 0x90(t2)
+;   sd s11, 0x98(t2)
+;   sd a1, 0xa0(t2)
+;   sd a0, 0xa8(t2)
+;   sd s2, 0xb0(t2)
+;   ld a1, 0x10(sp)
+;   sd a1, 0xb8(t2)
 ;   ld a0, 0(sp)
-;   ld a2, 8(sp)
-;   ld a4, 0x10(sp)
-;   addi sp, sp, 0x20
+;   ld a1, 8(sp)
+;   ld s1, 0x78(sp)
+;   ld s2, 0x70(sp)
+;   ld s3, 0x68(sp)
+;   ld s4, 0x60(sp)
+;   ld s5, 0x58(sp)
+;   ld s6, 0x50(sp)
+;   ld s7, 0x48(sp)
+;   ld s8, 0x40(sp)
+;   ld s9, 0x38(sp)
+;   ld s10, 0x30(sp)
+;   ld s11, 0x28(sp)
+;   addi sp, sp, 0x80
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
-;   addi sp, sp, 0x30
+;   addi sp, sp, 0xa0
 ;   ret
 
 function %tail_caller_stack_args_and_rets() -> i64 tail {
@@ -486,56 +814,110 @@ block0:
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-112
-;   virtual_sp_offset_adj +96
+;   addi sp,sp,-464
+;   virtual_sp_offset_adj +352
+;   sd s1,456(sp)
+;   sd s2,448(sp)
+;   sd s3,440(sp)
+;   sd s4,432(sp)
+;   sd s5,424(sp)
+;   sd s6,416(sp)
+;   sd s7,408(sp)
+;   sd s8,400(sp)
+;   sd s9,392(sp)
+;   sd s10,384(sp)
+;   sd s11,376(sp)
 ; block0:
-;   li s1,10
-;   sd s1,8(nominal_sp)
-;   li a0,15
-;   sd a0,0(nominal_sp)
-;   li a1,20
-;   li a2,25
-;   li a3,30
-;   li a4,35
-;   li a5,40
-;   li a6,45
-;   li a7,50
-;   li s2,55
-;   li s3,60
-;   li s4,65
-;   li s5,70
-;   li s6,75
-;   li s7,80
-;   li s8,85
-;   li s9,90
-;   li s10,95
-;   li s11,100
-;   li t3,105
-;   li t4,110
-;   li t0,115
-;   li t1,120
-;   li t2,125
-;   li s1,130
-;   li a0,135
-;   sd t0,0(sp)
-;   sd t1,8(sp)
-;   sd t2,16(sp)
-;   sd s1,24(sp)
-;   sd a0,32(sp)
-;   load_addr a0,48(sp)
-;   sd a0,40(sp)
-;   load_sym t0,%tail_callee_stack_args_and_rets+0
-;   ld s1,8(nominal_sp)
-;   ld a0,0(nominal_sp)
-;   callind t0
-;   addi sp,sp,-48
-;   virtual_sp_offset_adj +48
-;   ld a4,48(sp)
-;   ld a0,56(sp)
-;   ld a2,64(sp)
-;   ld a4,72(sp)
-;   ld s1,80(sp)
-;   addi sp,sp,112
+;   li a0,10
+;   sd a0,8(nominal_sp)
+;   li a1,15
+;   sd a1,0(nominal_sp)
+;   li a2,20
+;   li a3,25
+;   li a4,30
+;   li a5,35
+;   li a6,40
+;   li a7,45
+;   li s11,50
+;   li t0,55
+;   li t1,60
+;   li t2,65
+;   li t3,70
+;   li t4,75
+;   li s1,80
+;   li s2,85
+;   li s3,90
+;   li s4,95
+;   li s5,100
+;   li s6,105
+;   li s7,110
+;   li s8,115
+;   li s9,120
+;   li s10,125
+;   li a0,130
+;   li a1,135
+;   sd s11,0(sp)
+;   sd t0,8(sp)
+;   sd t1,16(sp)
+;   sd t2,24(sp)
+;   sd t3,32(sp)
+;   sd t4,40(sp)
+;   sd s1,48(sp)
+;   sd s2,56(sp)
+;   sd s3,64(sp)
+;   sd s4,72(sp)
+;   sd s5,80(sp)
+;   sd s6,88(sp)
+;   sd s7,96(sp)
+;   sd s8,104(sp)
+;   sd s9,112(sp)
+;   sd s10,120(sp)
+;   sd a0,128(sp)
+;   sd a1,136(sp)
+;   load_addr a0,160(sp)
+;   sd a0,144(sp)
+;   load_sym t1,%tail_callee_stack_args_and_rets+0
+;   ld a0,8(nominal_sp)
+;   ld a1,0(nominal_sp)
+;   callind t1
+;   addi sp,sp,-160
+;   virtual_sp_offset_adj +160
+;   ld a4,160(sp)
+;   ld a0,168(sp)
+;   ld a2,176(sp)
+;   ld a4,184(sp)
+;   ld a0,192(sp)
+;   ld a2,200(sp)
+;   ld a4,208(sp)
+;   ld a0,216(sp)
+;   ld a2,224(sp)
+;   ld a4,232(sp)
+;   ld a0,240(sp)
+;   ld a2,248(sp)
+;   ld a4,256(sp)
+;   ld a0,264(sp)
+;   ld a2,272(sp)
+;   ld a4,280(sp)
+;   ld a0,288(sp)
+;   ld a2,296(sp)
+;   ld a4,304(sp)
+;   ld a0,312(sp)
+;   ld a2,320(sp)
+;   ld a4,328(sp)
+;   ld a0,336(sp)
+;   ld a0,344(sp)
+;   ld s1,456(sp)
+;   ld s2,448(sp)
+;   ld s3,440(sp)
+;   ld s4,432(sp)
+;   ld s5,424(sp)
+;   ld s6,416(sp)
+;   ld s7,408(sp)
+;   ld s8,400(sp)
+;   ld s9,392(sp)
+;   ld s10,384(sp)
+;   ld s11,376(sp)
+;   addi sp,sp,464
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
@@ -547,58 +929,112 @@ block0:
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x70
-; block1: ; offset 0x14
-;   addi s1, zero, 0xa
-;   sd s1, 0x68(sp)
-;   addi a0, zero, 0xf
-;   sd a0, 0x60(sp)
-;   addi a1, zero, 0x14
-;   addi a2, zero, 0x19
-;   addi a3, zero, 0x1e
-;   addi a4, zero, 0x23
-;   addi a5, zero, 0x28
-;   addi a6, zero, 0x2d
-;   addi a7, zero, 0x32
-;   addi s2, zero, 0x37
-;   addi s3, zero, 0x3c
-;   addi s4, zero, 0x41
-;   addi s5, zero, 0x46
-;   addi s6, zero, 0x4b
-;   addi s7, zero, 0x50
-;   addi s8, zero, 0x55
-;   addi s9, zero, 0x5a
-;   addi s10, zero, 0x5f
-;   addi s11, zero, 0x64
-;   addi t3, zero, 0x69
-;   addi t4, zero, 0x6e
-;   addi t0, zero, 0x73
-;   addi t1, zero, 0x78
-;   addi t2, zero, 0x7d
-;   addi s1, zero, 0x82
-;   addi a0, zero, 0x87
-;   sd t0, 0(sp)
-;   sd t1, 8(sp)
-;   sd t2, 0x10(sp)
-;   sd s1, 0x18(sp)
-;   sd a0, 0x20(sp)
-;   addi a0, sp, 0x30
-;   sd a0, 0x28(sp)
-;   auipc t0, 0
-;   ld t0, 0xc(t0)
+;   addi sp, sp, -0x1d0
+;   sd s1, 0x1c8(sp)
+;   sd s2, 0x1c0(sp)
+;   sd s3, 0x1b8(sp)
+;   sd s4, 0x1b0(sp)
+;   sd s5, 0x1a8(sp)
+;   sd s6, 0x1a0(sp)
+;   sd s7, 0x198(sp)
+;   sd s8, 0x190(sp)
+;   sd s9, 0x188(sp)
+;   sd s10, 0x180(sp)
+;   sd s11, 0x178(sp)
+; block1: ; offset 0x40
+;   addi a0, zero, 0xa
+;   sd a0, 0x168(sp)
+;   addi a1, zero, 0xf
+;   sd a1, 0x160(sp)
+;   addi a2, zero, 0x14
+;   addi a3, zero, 0x19
+;   addi a4, zero, 0x1e
+;   addi a5, zero, 0x23
+;   addi a6, zero, 0x28
+;   addi a7, zero, 0x2d
+;   addi s11, zero, 0x32
+;   addi t0, zero, 0x37
+;   addi t1, zero, 0x3c
+;   addi t2, zero, 0x41
+;   addi t3, zero, 0x46
+;   addi t4, zero, 0x4b
+;   addi s1, zero, 0x50
+;   addi s2, zero, 0x55
+;   addi s3, zero, 0x5a
+;   addi s4, zero, 0x5f
+;   addi s5, zero, 0x64
+;   addi s6, zero, 0x69
+;   addi s7, zero, 0x6e
+;   addi s8, zero, 0x73
+;   addi s9, zero, 0x78
+;   addi s10, zero, 0x7d
+;   addi a0, zero, 0x82
+;   addi a1, zero, 0x87
+;   sd s11, 0(sp)
+;   sd t0, 8(sp)
+;   sd t1, 0x10(sp)
+;   sd t2, 0x18(sp)
+;   sd t3, 0x20(sp)
+;   sd t4, 0x28(sp)
+;   sd s1, 0x30(sp)
+;   sd s2, 0x38(sp)
+;   sd s3, 0x40(sp)
+;   sd s4, 0x48(sp)
+;   sd s5, 0x50(sp)
+;   sd s6, 0x58(sp)
+;   sd s7, 0x60(sp)
+;   sd s8, 0x68(sp)
+;   sd s9, 0x70(sp)
+;   sd s10, 0x78(sp)
+;   sd a0, 0x80(sp)
+;   sd a1, 0x88(sp)
+;   addi a0, sp, 0xa0
+;   sd a0, 0x90(sp)
+;   auipc t1, 0
+;   ld t1, 0xc(t1)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %tail_callee_stack_args_and_rets 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   ld s1, 0x68(sp)
-;   ld a0, 0x60(sp)
-;   jalr t0
-;   addi sp, sp, -0x30
-;   ld a4, 0x30(sp)
-;   ld a0, 0x38(sp)
-;   ld a2, 0x40(sp)
-;   ld a4, 0x48(sp)
-;   ld s1, 0x50(sp)
-;   addi sp, sp, 0x70
+;   ld a0, 0x168(sp)
+;   ld a1, 0x160(sp)
+;   jalr t1
+;   addi sp, sp, -0xa0
+;   ld a4, 0xa0(sp)
+;   ld a0, 0xa8(sp)
+;   ld a2, 0xb0(sp)
+;   ld a4, 0xb8(sp)
+;   ld a0, 0xc0(sp)
+;   ld a2, 0xc8(sp)
+;   ld a4, 0xd0(sp)
+;   ld a0, 0xd8(sp)
+;   ld a2, 0xe0(sp)
+;   ld a4, 0xe8(sp)
+;   ld a0, 0xf0(sp)
+;   ld a2, 0xf8(sp)
+;   ld a4, 0x100(sp)
+;   ld a0, 0x108(sp)
+;   ld a2, 0x110(sp)
+;   ld a4, 0x118(sp)
+;   ld a0, 0x120(sp)
+;   ld a2, 0x128(sp)
+;   ld a4, 0x130(sp)
+;   ld a0, 0x138(sp)
+;   ld a2, 0x140(sp)
+;   ld a4, 0x148(sp)
+;   ld a0, 0x150(sp)
+;   ld a0, 0x158(sp)
+;   ld s1, 0x1c8(sp)
+;   ld s2, 0x1c0(sp)
+;   ld s3, 0x1b8(sp)
+;   ld s4, 0x1b0(sp)
+;   ld s5, 0x1a8(sp)
+;   ld s6, 0x1a0(sp)
+;   ld s7, 0x198(sp)
+;   ld s8, 0x190(sp)
+;   ld s9, 0x188(sp)
+;   ld s10, 0x180(sp)
+;   ld s11, 0x178(sp)
+;   addi sp, sp, 0x1d0
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
diff --git a/cranelift/filetests/filetests/isa/riscv64/zca.clif b/cranelift/filetests/filetests/isa/riscv64/zca.clif
index 5bb7d11a6..0fe4c8f71 100644
--- a/cranelift/filetests/filetests/isa/riscv64/zca.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/zca.clif
@@ -183,8 +183,8 @@ block0(v0: i8):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   load_sym a2,%callee_i8+0
-;   return_call_ind a2 new_stack_arg_size:0 s1=s1
+;   load_sym t0,%callee_i8+0
+;   return_call_ind t0 new_stack_arg_size:0 a0=a0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -193,8 +193,8 @@ block0(v0: i8):
 ;   c.sdsp s0, 0(sp)
 ;   c.mv s0, sp
 ; block1: ; offset 0x8
-;   auipc a2, 0
-;   ld a2, 0xa(a2)
+;   auipc t0, 0
+;   ld t0, 0xa(t0)
 ;   c.j 0xa
 ;   c.unimp ; reloc_external Abs8 %callee_i8 0
 ;   c.unimp
@@ -203,7 +203,7 @@ block0(v0: i8):
 ;   c.ldsp ra, 8(sp)
 ;   c.ldsp s0, 0(sp)
 ;   c.addi16sp sp, 0x10
-;   c.jr a2
+;   c.jr t0
 
 function %c_ret(i32) -> i32 {
 block0(v0: i32):
diff --git a/cranelift/filetests/filetests/isa/x64/branches.clif b/cranelift/filetests/filetests/isa/x64/branches.clif
index 57ab4de3f..fbbd876b8 100644
--- a/cranelift/filetests/filetests/isa/x64/branches.clif
+++ b/cranelift/filetests/filetests/isa/x64/branches.clif
@@ -630,15 +630,13 @@ block202:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movl    $1112539136, %eax
-;   movd    %eax, %xmm4
-;   ucomiss %xmm4, %xmm0
+;   ucomiss const(1), %xmm0
 ;   jp      label2
 ;   jnz     label2; j label1
 ; block1:
 ;   jmp     label5
 ; block2:
-;   ucomiss %xmm4, %xmm0
+;   ucomiss const(0), %xmm0
 ;   jnp     label4; j label3
 ; block3:
 ;   jmp     label5
@@ -654,20 +652,36 @@ block202:
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movl $0x42500000, %eax
-;   movd %eax, %xmm4
-;   ucomiss %xmm4, %xmm0
-;   jp 0x1c
-;   je 0x27
-; block2: ; offset 0x1c
-;   ucomiss %xmm4, %xmm0
-;   jp 0x27
-; block3: ; offset 0x25
+;   ucomiss 0x25(%rip), %xmm0
+;   jp 0x17
+;   je 0x26
+; block2: ; offset 0x17
+;   ucomiss 0x22(%rip), %xmm0
+;   jp 0x26
+; block3: ; offset 0x24
 ;   ud2 ; trap: heap_oob
-; block4: ; offset 0x27
+; block4: ; offset 0x26
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %dl, 0x42(%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   pushq %rax
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
 
 function %br_i8_icmp(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
diff --git a/cranelift/filetests/filetests/isa/x64/f64-branches-avx.clif b/cranelift/filetests/filetests/isa/x64/f64-branches-avx.clif
new file mode 100644
index 000000000..f40100bbf
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/f64-branches-avx.clif
@@ -0,0 +1,105 @@
+test compile precise-output
+target x86_64 has_avx
+
+function %f3(f32, f32) -> i32 {
+block0(v0: f32, v1: f32):
+  v2 = fcmp eq v0, v1
+  brif v2, block1, block2
+
+block1:
+  v3 = iconst.i32 1
+  return v3
+
+block2:
+  v4 = iconst.i32 2
+  return v4
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vucomiss %xmm1, %xmm0
+;   jp      label1
+;   jnz     label1; j label2
+; block1:
+;   movl    $2, %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; block2:
+;   movl    $1, %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vucomiss %xmm1, %xmm0
+;   jp 0x14
+;   je 0x1e
+; block2: ; offset 0x14
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block3: ; offset 0x1e
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %f3(f64, f64) -> i32 {
+block0(v0: f64, v1: f64):
+  v2 = fcmp eq v0, v1
+  brif v2, block1, block2
+
+block1:
+  v3 = iconst.i32 1
+  return v3
+
+block2:
+  v4 = iconst.i32 2
+  return v4
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vucomisd %xmm1, %xmm0
+;   jp      label1
+;   jnz     label1; j label2
+; block1:
+;   movl    $2, %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; block2:
+;   movl    $1, %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vucomisd %xmm1, %xmm0
+;   jp 0x14
+;   je 0x1e
+; block2: ; offset 0x14
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block3: ; offset 0x1e
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/return-call-indirect.clif b/cranelift/filetests/filetests/isa/x64/return-call-indirect.clif
index ba16a98c9..22ba0bb94 100644
--- a/cranelift/filetests/filetests/isa/x64/return-call-indirect.clif
+++ b/cranelift/filetests/filetests/isa/x64/return-call-indirect.clif
@@ -42,18 +42,18 @@ block0(v0: i64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   load_ext_name %callee_i64+0, %rcx
-;   return_call_unknown %rcx (0) tmp=%rdx %rdi=%rdi
+;   load_ext_name %callee_i64+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11 %rdi=%rdi
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movabsq $0, %rcx ; reloc_external Abs8 %callee_i64 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %callee_i64 0
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rcx
+;   jmpq *%r10
 
 ;;;; Test colocated tail calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -70,18 +70,18 @@ block0(v0: i64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   load_ext_name %callee_i64+0, %rcx
-;   return_call_unknown %rcx (0) tmp=%rdx %rdi=%rdi
+;   load_ext_name %callee_i64+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11 %rdi=%rdi
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   leaq (%rip), %rcx ; reloc_external CallPCRel4 %callee_i64 -4
+;   leaq (%rip), %r10 ; reloc_external CallPCRel4 %callee_i64 -4
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rcx
+;   jmpq *%r10
 
 ;;;; Test passing `f64`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -139,18 +139,18 @@ block0(v0: f64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   load_ext_name %callee_f64+0, %rcx
-;   return_call_unknown %rcx (0) tmp=%rdx %xmm0=%xmm0
+;   load_ext_name %callee_f64+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11 %xmm0=%xmm0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movabsq $0, %rcx ; reloc_external Abs8 %callee_f64 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %callee_f64 0
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rcx
+;   jmpq *%r10
 
 ;;;; Test passing `i8`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -195,18 +195,18 @@ block0(v0: i8):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   load_ext_name %callee_i8+0, %rcx
-;   return_call_unknown %rcx (0) tmp=%rdx %rdi=%rdi
+;   load_ext_name %callee_i8+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11 %rdi=%rdi
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movabsq $0, %rcx ; reloc_external Abs8 %callee_i8 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %callee_i8 0
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rcx
+;   jmpq *%r10
 
 ;;;; Test passing many arguments on stack ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -335,7 +335,7 @@ block0:
 ;   movq    rsp(72 + virtual offset), %r8
 ;   movq    rsp(64 + virtual offset), %r9
 ;   movq    rsp(0 + virtual offset), %r10
-;   return_call_unknown %r10 (160) tmp=%rax %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
+;   return_call_unknown %r10 (160) tmp=%r11 %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
diff --git a/cranelift/filetests/filetests/isa/x64/return-call.clif b/cranelift/filetests/filetests/isa/x64/return-call.clif
index 8ffb1c2fd..113d495bc 100644
--- a/cranelift/filetests/filetests/isa/x64/return-call.clif
+++ b/cranelift/filetests/filetests/isa/x64/return-call.clif
@@ -40,18 +40,18 @@ block0(v0: i64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   load_ext_name %callee_i64+0, %rcx
-;   return_call_unknown %rcx (0) tmp=%rdx %rdi=%rdi
+;   load_ext_name %callee_i64+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11 %rdi=%rdi
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movabsq $0, %rcx ; reloc_external Abs8 %callee_i64 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %callee_i64 0
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rcx
+;   jmpq *%r10
 
 ;;;; Test colocated tail calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -66,7 +66,7 @@ block0(v0: i64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   return_call_known TestCase(%callee_i64) (0) tmp=%rax %rdi=%rdi
+;   return_call_known TestCase(%callee_i64) (0) tmp=%r11 %rdi=%rdi
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -131,18 +131,18 @@ block0(v0: f64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   load_ext_name %callee_f64+0, %rcx
-;   return_call_unknown %rcx (0) tmp=%rdx %xmm0=%xmm0
+;   load_ext_name %callee_f64+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11 %xmm0=%xmm0
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movabsq $0, %rcx ; reloc_external Abs8 %callee_f64 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %callee_f64 0
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rcx
+;   jmpq *%r10
 
 ;;;; Test passing `i8`s ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -185,18 +185,18 @@ block0(v0: i8):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   load_ext_name %callee_i8+0, %rcx
-;   return_call_unknown %rcx (0) tmp=%rdx %rdi=%rdi
+;   load_ext_name %callee_i8+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11 %rdi=%rdi
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   pushq %rbp
 ;   movq %rsp, %rbp
 ; block1: ; offset 0x4
-;   movabsq $0, %rcx ; reloc_external Abs8 %callee_i8 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %callee_i8 0
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rcx
+;   jmpq *%r10
 
 ;;;; Test passing fewer arguments on the stack ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -243,7 +243,7 @@ block0(v0: i32, v1: i32, v2: i32, v3: i32, v4: i32, v5: i32, v6: i32, v7: i32, v
 ;   movq    rbp(stack args max - 24), %r9
 ;   movq    rbp(stack args max - 16), %rax
 ;   movl    %eax, rbp(stack args max - 16)
-;   return_call_known TestCase(%one_stack_arg) (16) tmp=%r10 %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
+;   return_call_known TestCase(%one_stack_arg) (16) tmp=%r11 %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -260,8 +260,8 @@ block0(v0: i32, v1: i32, v2: i32, v3: i32, v4: i32, v5: i32, v6: i32, v7: i32, v
 ;   movl %eax, 0x20(%rbp)
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   movq (%rsp), %r10
-;   movq %r10, 0x10(%rsp)
+;   movq (%rsp), %r11
+;   movq %r11, 0x10(%rsp)
 ;   addq $0x10, %rsp
 ;   jmp 0x35 ; reloc_external CallPCRel4 %one_stack_arg -4
 
@@ -279,7 +279,7 @@ block0(v0: i32, v1: i32, v2: i32, v3: i32, v4: i32, v5: i32, v6: i32, v7: i32, v
 ;   movq    rbp(stack args max - 32), %r10
 ;   movq    rbp(stack args max - 24), %rsi
 ;   movq    rbp(stack args max - 16), %rdi
-;   return_call_known TestCase(%callee_i8) (0) tmp=%rdx %rdi=%rdi
+;   return_call_known TestCase(%callee_i8) (0) tmp=%r11 %rdi=%rdi
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -291,8 +291,8 @@ block0(v0: i32, v1: i32, v2: i32, v3: i32, v4: i32, v5: i32, v6: i32, v7: i32, v
 ;   movq 0x20(%rbp), %rdi
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   movq (%rsp), %rdx
-;   movq %rdx, 0x20(%rsp)
+;   movq (%rsp), %r11
+;   movq %r11, 0x20(%rsp)
 ;   addq $0x20, %rsp
 ;   jmp 0x26 ; reloc_external CallPCRel4 %callee_i8 -4
 
@@ -325,7 +325,7 @@ block0(v0: i32, v1: i32, v2: i32, v3: i32, v4: i32, v5: i32, v6: i32):
 ;   movl    %esi, rbp(stack args max - 16)
 ;   movq    %rsi, %rdi
 ;   movq    %r10, %rsi
-;   return_call_known TestCase(%call_one_stack_arg) (32) tmp=%r10 %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
+;   return_call_known TestCase(%call_one_stack_arg) (32) tmp=%r11 %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -531,14 +531,14 @@ block0:
 ;   movq    %rsi, rbp(stack args max - 16)
 ;   movq    rsp(0 + virtual offset), %rsi
 ;   movq    %rsi, rbp(stack args max - 8)
-;   load_ext_name %tail_callee_stack_args+0, %rax
+;   load_ext_name %tail_callee_stack_args+0, %r10
 ;   movq    rsp(72 + virtual offset), %rcx
 ;   movq    rsp(80 + virtual offset), %rdx
 ;   movq    rsp(88 + virtual offset), %rsi
 ;   movq    rsp(96 + virtual offset), %rdi
 ;   movq    rsp(64 + virtual offset), %r8
 ;   movq    rsp(56 + virtual offset), %r9
-;   return_call_unknown %rax (160) tmp=%r10 %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
+;   return_call_unknown %r10 (160) tmp=%r11 %rdi=%rdi %rsi=%rsi %rdx=%rdx %rcx=%rcx %r8=%r8 %r9=%r9
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -623,7 +623,7 @@ block0:
 ;   movq %rsi, 0xa0(%rbp)
 ;   movq (%rsp), %rsi
 ;   movq %rsi, 0xa8(%rbp)
-;   movabsq $0, %rax ; reloc_external Abs8 %tail_callee_stack_args 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %tail_callee_stack_args 0
 ;   movq 0x48(%rsp), %rcx
 ;   movq 0x50(%rsp), %rdx
 ;   movq 0x58(%rsp), %rsi
@@ -638,5 +638,5 @@ block0:
 ;   addq $0xa0, %rsp
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   jmpq *%rax
+;   jmpq *%r10
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-logical-compile-avx.clif b/cranelift/filetests/filetests/isa/x64/simd-logical-compile-avx.clif
new file mode 100644
index 000000000..f30b20acc
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/simd-logical-compile-avx.clif
@@ -0,0 +1,62 @@
+test compile precise-output
+target x86_64 sse42 has_avx
+
+function %vany_true_i32x4(i32x4) -> i8 {
+block0(v0: i32x4):
+    v1 = vany_true v0
+    return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   vptest  %xmm0, %xmm0
+;   setnz   %al
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vptest %xmm0, %xmm0
+;   setne %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %vall_true_i64x2(i64x2) -> i8 {
+block0(v0: i64x2):
+    v1 = vall_true v0
+    return v1
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   uninit  %xmm2
+;   vpxor   %xmm2, %xmm2, %xmm4
+;   vpcmpeqq %xmm0, %xmm4, %xmm6
+;   vptest  %xmm6, %xmm6
+;   setz    %al
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   vpxor %xmm2, %xmm2, %xmm4
+;   vpcmpeqq %xmm4, %xmm0, %xmm6
+;   vptest %xmm6, %xmm6
+;   sete %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/tail-call-conv.clif b/cranelift/filetests/filetests/isa/x64/tail-call-conv.clif
index 93ccab77f..7a2243a0f 100644
--- a/cranelift/filetests/filetests/isa/x64/tail-call-conv.clif
+++ b/cranelift/filetests/filetests/isa/x64/tail-call-conv.clif
@@ -895,7 +895,6 @@ block0:
 ;   popq %rbp
 ;   retq
 
-
 ;; Test that tail calls that shrink the argument area don't clobber the location
 ;; of an indirect jump
 
@@ -916,8 +915,8 @@ block0(v0: f64, v1: f64, v2: i8, v3: i32, v4: i128, v5: i32, v6: i128, v7: i32,
 ;   movq    rbp(stack args max - 24), %rax
 ;   movq    rbp(stack args max - 16), %rdx
 ;   movq    rbp(stack args max - 8), %r9
-;   load_ext_name %callee_simple+0, %rsi
-;   return_call_unknown %rsi (0) tmp=%rdi
+;   load_ext_name %callee_simple+0, %r10
+;   return_call_unknown %r10 (0) tmp=%r11
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
@@ -928,11 +927,11 @@ block0(v0: f64, v1: f64, v2: i8, v3: i32, v4: i128, v5: i32, v6: i128, v7: i32,
 ;   movq 0x18(%rbp), %rax
 ;   movq 0x20(%rbp), %rdx
 ;   movq 0x28(%rbp), %r9
-;   movabsq $0, %rsi ; reloc_external Abs8 %callee_simple 0
+;   movabsq $0, %r10 ; reloc_external Abs8 %callee_simple 0
 ;   movq %rbp, %rsp
 ;   popq %rbp
-;   movq (%rsp), %rdi
-;   movq %rdi, 0x20(%rsp)
+;   movq (%rsp), %r11
+;   movq %r11, 0x20(%rsp)
 ;   addq $0x20, %rsp
-;   jmpq *%rsi
+;   jmpq *%r10
 
diff --git a/cranelift/filetests/filetests/isa/x64/very-carefully-sink-loads-in-float-compares.clif b/cranelift/filetests/filetests/isa/x64/very-carefully-sink-loads-in-float-compares.clif
new file mode 100644
index 000000000..01c9d4db2
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/very-carefully-sink-loads-in-float-compares.clif
@@ -0,0 +1,499 @@
+test compile precise-output
+target x86_64
+
+;; This test ensures that Cranelift does not attempt to too eagerly sink loads
+;; into float comparison operations. When a single `fcmp` is used multiple times
+;; it'll regenerate `ucomiss` instructions, for example, but if this duplication
+;; happens then it shouldn't have a load sunk into it because that would load
+;; at two different points in the program, possibly seeing two different
+;; results.
+;;
+;; Exactly how this guarantee is provided has changed a bit over time with
+;; Cranelift. Originally in #3934 this was done explicitly in ISLE by avoiding
+;; the use of `put_in_xmm_mem`. Later in #4061 that ended up removing the need
+;; for the safeguards in #3934. Today there are no guards in ISLE for this any
+;; more and this test is intended to serve as a reference-test for notifying
+;; reviewers if anything changes.
+
+function %select_cond_rhs(f32, i64, i32, i32) -> i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v0, v4
+  v6 = select v5, v2, v3
+  return v6
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   ucomiss 0(%rdi), %xmm0
+;   cmovpl  %edx, %esi, %esi
+;   movq    %rsi, %rax
+;   cmovnzl %edx, %eax, %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   ucomiss (%rdi), %xmm0
+;   cmovpl %edx, %esi
+;   movq %rsi, %rax
+;   cmovnel %edx, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+
+function %select_cond_lhs(f32, i64, i32, i32) -> i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v4, v0
+  v6 = select v5, v2, v3
+  return v6
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm7
+;   ucomiss %xmm0, %xmm7
+;   cmovpl  %edx, %esi, %esi
+;   movq    %rsi, %rax
+;   cmovnzl %edx, %eax, %eax
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm7
+;   ucomiss %xmm0, %xmm7
+;   cmovpl %edx, %esi
+;   movq %rsi, %rax
+;   cmovnel %edx, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %select_cond_used_twice_rhs(f32, i64, i32, i32) -> i32, i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  ;; this load should NOT sink into either `select` below
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v0, v4
+  v6 = select v5, v2, v3
+  v7 = select v5, v3, v2
+  return v6, v7
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm1
+;   ucomiss %xmm1, %xmm0
+;   movq    %rsi, %rax
+;   cmovpl  %edx, %eax, %eax
+;   cmovnzl %edx, %eax, %eax
+;   ucomiss %xmm1, %xmm0
+;   cmovpl  %esi, %edx, %edx
+;   cmovnzl %esi, %edx, %edx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm1
+;   ucomiss %xmm1, %xmm0
+;   movq %rsi, %rax
+;   cmovpl %edx, %eax
+;   cmovnel %edx, %eax
+;   ucomiss %xmm1, %xmm0
+;   cmovpl %esi, %edx
+;   cmovnel %esi, %edx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+
+function %select_cond_used_twice_lhs(f32, i64, i32, i32) -> i32, i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  ;; this load should NOT sink into either `select` below
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v4, v0
+  v6 = select v5, v2, v3
+  v7 = select v5, v3, v2
+  return v6, v7
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm1
+;   ucomiss %xmm0, %xmm1
+;   movq    %rsi, %rax
+;   cmovpl  %edx, %eax, %eax
+;   cmovnzl %edx, %eax, %eax
+;   ucomiss %xmm0, %xmm1
+;   cmovpl  %esi, %edx, %edx
+;   cmovnzl %esi, %edx, %edx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm1
+;   ucomiss %xmm0, %xmm1
+;   movq %rsi, %rax
+;   cmovpl %edx, %eax
+;   cmovnel %edx, %eax
+;   ucomiss %xmm0, %xmm1
+;   cmovpl %esi, %edx
+;   cmovnel %esi, %edx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %brif_cond_rhs(f32, i64, i32, i32) -> i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v0, v4
+  brif v5, block1(v2), block1(v3)
+block1(v8: i32):
+  return v8
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm1
+;   ucomiss %xmm1, %xmm0
+;   jp      label2
+;   jnz     label2; j label1
+; block1:
+;   movq    %rsi, %rax
+;   jmp     label3
+; block2:
+;   movq    %rdx, %rax
+;   jmp     label3
+; block3:
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm1
+;   ucomiss %xmm1, %xmm0
+;   jp 0x1f
+;   jne 0x1f
+; block2: ; offset 0x17
+;   movq %rsi, %rax
+;   jmp 0x22
+; block3: ; offset 0x1f
+;   movq %rdx, %rax
+; block4: ; offset 0x22
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %brif_cond_lhs(f32, i64, i32, i32) -> i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v4, v0
+  brif v5, block1(v2), block1(v3)
+block1(v8: i32):
+  return v8
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm1
+;   ucomiss %xmm0, %xmm1
+;   jp      label2
+;   jnz     label2; j label1
+; block1:
+;   movq    %rsi, %rax
+;   jmp     label3
+; block2:
+;   movq    %rdx, %rax
+;   jmp     label3
+; block3:
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm1
+;   ucomiss %xmm0, %xmm1
+;   jp 0x1f
+;   jne 0x1f
+; block2: ; offset 0x17
+;   movq %rsi, %rax
+;   jmp 0x22
+; block3: ; offset 0x1f
+;   movq %rdx, %rax
+; block4: ; offset 0x22
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %brif_cond_used_twice_rhs(f32, i64, i32, i32) -> i32, i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v0, v4
+  brif v5, block1(v2), block1(v3)
+block1(v6: i32):
+  brif v5, block2(v3), block2(v2)
+block2(v7: i32):
+  return v6, v7
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jp      label2
+;   jnz     label2; j label1
+; block1:
+;   movq    %rsi, %rax
+;   jmp     label3
+; block2:
+;   movq    %rdx, %rax
+;   jmp     label3
+; block3:
+;   ucomiss %xmm3, %xmm0
+;   jp      label5
+;   jnz     label5; j label4
+; block4:
+;   jmp     label6
+; block5:
+;   movq    %rsi, %rdx
+;   jmp     label6
+; block6:
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jp 0x1f
+;   jne 0x1f
+; block2: ; offset 0x17
+;   movq %rsi, %rax
+;   jmp 0x22
+; block3: ; offset 0x1f
+;   movq %rdx, %rax
+; block4: ; offset 0x22
+;   ucomiss %xmm3, %xmm0
+;   jp 0x31
+;   je 0x34
+; block5: ; offset 0x31
+;   movq %rsi, %rdx
+; block6: ; offset 0x34
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %brif_cond_used_twice_lhs(f32, i64, i32, i32) -> i32, i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v4, v0
+  brif v5, block1(v2), block1(v3)
+block1(v6: i32):
+  brif v5, block2(v3), block2(v2)
+block2(v7: i32):
+  return v6, v7
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm3
+;   ucomiss %xmm0, %xmm3
+;   jp      label2
+;   jnz     label2; j label1
+; block1:
+;   movq    %rsi, %rax
+;   jmp     label3
+; block2:
+;   movq    %rdx, %rax
+;   jmp     label3
+; block3:
+;   ucomiss %xmm0, %xmm3
+;   jp      label5
+;   jnz     label5; j label4
+; block4:
+;   jmp     label6
+; block5:
+;   movq    %rsi, %rdx
+;   jmp     label6
+; block6:
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm3
+;   ucomiss %xmm0, %xmm3
+;   jp 0x1f
+;   jne 0x1f
+; block2: ; offset 0x17
+;   movq %rsi, %rax
+;   jmp 0x22
+; block3: ; offset 0x1f
+;   movq %rdx, %rax
+; block4: ; offset 0x22
+;   ucomiss %xmm0, %xmm3
+;   jp 0x31
+;   je 0x34
+; block5: ; offset 0x31
+;   movq %rsi, %rdx
+; block6: ; offset 0x34
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %mix_select_and_brif_rhs(f32, i64, i32, i32) -> i32, i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v0, v4
+  v6 = select v5, v2, v3
+  brif v5, block1(v3), block1(v2)
+block1(v7: i32):
+  return v6, v7
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm2
+;   ucomiss %xmm2, %xmm0
+;   movq    %rsi, %rax
+;   cmovpl  %edx, %eax, %eax
+;   cmovnzl %edx, %eax, %eax
+;   ucomiss %xmm2, %xmm0
+;   jp      label2
+;   jnz     label2; j label1
+; block1:
+;   jmp     label3
+; block2:
+;   movq    %rsi, %rdx
+;   jmp     label3
+; block3:
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm2
+;   ucomiss %xmm2, %xmm0
+;   movq %rsi, %rax
+;   cmovpl %edx, %eax
+;   cmovnel %edx, %eax
+;   ucomiss %xmm2, %xmm0
+;   jp 0x23
+;   je 0x26
+; block2: ; offset 0x23
+;   movq %rsi, %rdx
+; block3: ; offset 0x26
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %mix_select_and_brif_lhs(f32, i64, i32, i32) -> i32, i32 {
+block0(v0: f32, v1: i64, v2: i32, v3: i32):
+  v4 = load.f32 notrap aligned v1
+  v5 = fcmp eq v4, v0
+  v6 = select v5, v2, v3
+  brif v5, block1(v3), block1(v2)
+block1(v7: i32):
+  return v6, v7
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movss   0(%rdi), %xmm2
+;   ucomiss %xmm0, %xmm2
+;   movq    %rsi, %rax
+;   cmovpl  %edx, %eax, %eax
+;   cmovnzl %edx, %eax, %eax
+;   ucomiss %xmm0, %xmm2
+;   jp      label2
+;   jnz     label2; j label1
+; block1:
+;   jmp     label3
+; block2:
+;   movq    %rsi, %rdx
+;   jmp     label3
+; block3:
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movss (%rdi), %xmm2
+;   ucomiss %xmm0, %xmm2
+;   movq %rsi, %rax
+;   cmovpl %edx, %eax
+;   cmovnel %edx, %eax
+;   ucomiss %xmm0, %xmm2
+;   jp 0x23
+;   je 0x26
+; block2: ; offset 0x23
+;   movq %rsi, %rdx
+; block3: ; offset 0x26
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/winch.clif b/cranelift/filetests/filetests/isa/x64/winch.clif
index 808b73d57..8832531b7 100644
--- a/cranelift/filetests/filetests/isa/x64/winch.clif
+++ b/cranelift/filetests/filetests/isa/x64/winch.clif
@@ -38,8 +38,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   subq    %rsp, $16, %rsp
 ; block0:
 ;   movq    %rdi, rsp(0 + virtual offset)
-;   load_ext_name %g+0, %r15
-;   call    *%r15
+;   load_ext_name %g+0, %r10
+;   call    *%r10
 ;   movq    rsp(0 + virtual offset), %rax
 ;   addq    %rsp, $16, %rsp
 ;   movq    %rbp, %rsp
@@ -53,8 +53,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   subq $0x10, %rsp
 ; block1: ; offset 0x8
 ;   movq %rdi, (%rsp)
-;   movabsq $0, %r15 ; reloc_external Abs8 %g 0
-;   callq *%r15
+;   movabsq $0, %r10 ; reloc_external Abs8 %g 0
+;   callq *%r10
 ;   movq (%rsp), %rax
 ;   addq $0x10, %rsp
 ;   movq %rbp, %rsp
@@ -81,8 +81,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   movq    %r15, 48(%rsp)
 ; block0:
 ;   movq    %rdi, rsp(0 + virtual offset)
-;   load_ext_name %g+0, %r15
-;   call    *%r15
+;   load_ext_name %g+0, %r10
+;   call    *%r10
 ;   movq    rsp(0 + virtual offset), %rax
 ;   movq    16(%rsp), %rbx
 ;   movq    24(%rsp), %r12
@@ -106,8 +106,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   movq %r15, 0x30(%rsp)
 ; block1: ; offset 0x21
 ;   movq %rdi, (%rsp)
-;   movabsq $0, %r15 ; reloc_external Abs8 %g 0
-;   callq *%r15
+;   movabsq $0, %r10 ; reloc_external Abs8 %g 0
+;   callq *%r10
 ;   movq (%rsp), %rax
 ;   movq 0x10(%rsp), %rbx
 ;   movq 0x18(%rsp), %r12
@@ -135,8 +135,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   movq    %rdi, %rax
 ;   movq    %r9, %rdi
 ;   movq    %rax, %r9
-;   load_ext_name %g+0, %r15
-;   call    *%r15
+;   load_ext_name %g+0, %r10
+;   call    *%r10
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -149,8 +149,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   movq %rdi, %rax
 ;   movq %r9, %rdi
 ;   movq %rax, %r9
-;   movabsq $0, %r15 ; reloc_external Abs8 %g 0
-;   callq *%r15
+;   movabsq $0, %r10 ; reloc_external Abs8 %g 0
+;   callq *%r10
 ;   movq %rbp, %rsp
 ;   popq %rbp
 ;   retq
@@ -177,8 +177,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   movq    %rdi, %rax
 ;   movq    %r9, %rdi
 ;   movq    %rax, %r9
-;   load_ext_name %g+0, %r15
-;   call    *%r15
+;   load_ext_name %g+0, %r10
+;   call    *%r10
 ;   movq    0(%rsp), %rbx
 ;   movq    8(%rsp), %r12
 ;   movq    16(%rsp), %r13
@@ -203,8 +203,8 @@ block0(v0:i64, v1:i64, v2:i64, v3:i64, v4:i64, v5:i64):
 ;   movq %rdi, %rax
 ;   movq %r9, %rdi
 ;   movq %rax, %r9
-;   movabsq $0, %r15 ; reloc_external Abs8 %g 0
-;   callq *%r15
+;   movabsq $0, %r10 ; reloc_external Abs8 %g 0
+;   callq *%r10
 ;   movq (%rsp), %rbx
 ;   movq 8(%rsp), %r12
 ;   movq 0x10(%rsp), %r13
@@ -236,12 +236,12 @@ block0:
 ;   movq    %r14, 40(%rsp)
 ;   movq    %r15, 48(%rsp)
 ; block0:
-;   load_ext_name userextname0+0, %r15
-;   movq    %r15, rsp(0 + virtual offset)
-;   movq    rsp(0 + virtual offset), %r15
-;   call    *%r15
-;   movq    rsp(0 + virtual offset), %r15
-;   call    *%r15
+;   load_ext_name userextname0+0, %r10
+;   movq    %r10, rsp(0 + virtual offset)
+;   movq    rsp(0 + virtual offset), %r10
+;   call    *%r10
+;   movq    rsp(0 + virtual offset), %r10
+;   call    *%r10
 ;   movq    16(%rsp), %rbx
 ;   movq    24(%rsp), %r12
 ;   movq    32(%rsp), %r13
@@ -263,12 +263,12 @@ block0:
 ;   movq %r14, 0x28(%rsp)
 ;   movq %r15, 0x30(%rsp)
 ; block1: ; offset 0x21
-;   movabsq $0, %r15 ; reloc_external Abs8 u2:0 0
-;   movq %r15, (%rsp)
-;   movq (%rsp), %r15
-;   callq *%r15
-;   movq (%rsp), %r15
-;   callq *%r15
+;   movabsq $0, %r10 ; reloc_external Abs8 u2:0 0
+;   movq %r10, (%rsp)
+;   movq (%rsp), %r10
+;   callq *%r10
+;   movq (%rsp), %r10
+;   callq *%r10
 ;   movq 0x10(%rsp), %rbx
 ;   movq 0x18(%rsp), %r12
 ;   movq 0x20(%rsp), %r13
@@ -301,8 +301,8 @@ block0(v0:i64):
 ;   movq    %r15, 48(%rsp)
 ; block0:
 ;   lea     0(%rsp), %rdi
-;   load_ext_name %g+0, %r15
-;   call    *%r15
+;   load_ext_name %g+0, %r10
+;   call    *%r10
 ;   movq    4(%rsp), %rax
 ;   movq    0(%rsp), %r11
 ;   andl    %eax, %r11d, %eax
@@ -328,8 +328,8 @@ block0(v0:i64):
 ;   movq %r15, 0x30(%rsp)
 ; block1: ; offset 0x21
 ;   leaq (%rsp), %rdi
-;   movabsq $0, %r15 ; reloc_external Abs8 %g 0
-;   callq *%r15
+;   movabsq $0, %r10 ; reloc_external Abs8 %g 0
+;   callq *%r10
 ;   movq 4(%rsp), %rax
 ;   movq (%rsp), %r11
 ;   andl %r11d, %eax