**File:** modules/core/include/opencv2/core/hal/intrin.hpp
**Change Type:** modified
**Context:** PR #22179: [GSoC] New universal intrinsic backend for RVV

**Code Changes:**
```diff
@@ -200,7 +200,7 @@ using namespace CV_CPU_OPTIMIZATION_HAL_NAMESPACE;
 #   undef CV_RVV
 #endif
 
-#if (CV_SSE2 || CV_NEON || CV_VSX || CV_MSA || CV_WASM_SIMD || CV_RVV071 || CV_RVV) && !defined(CV_FORCE_SIMD128_CPP)
+#if (CV_SSE2 || CV_NEON || CV_VSX || CV_MSA || CV_WASM_SIMD || CV_RVV071) && !defined(CV_FORCE_SIMD128_CPP)
 #define CV__SIMD_FORWARD 128
 #include "opencv2/core/hal/intrin_forward.hpp"
 #endif
@@ -229,9 +229,10 @@ using namespace CV_CPU_OPTIMIZATION_HAL_NAMESPACE;
```

Review comment:
There is a problem when we use `enum { nlanes = 16, max_nlanes = nlanes };` instead of static menber. at least we need different full specializations in different SIMD widths, by using conditional compilation like: ```cpp #if CV_SIMD template <class T> struct VTraits; #if CV_SIMD512 template <> struct VTraits<v_uint8> { static inline int vlanes() { return v_uint8::nlanes; } enum { nlanes = 64, max_nlanes = nlanes }; using lane_type = uchar; }; #elif CV_SIMD256 template <> struct VTraits<v_uint8> { static inline int vlanes() { return v_uint8::nlanes; } enum { nlanes = 32, max_nlanes = nlanes }; using lane_type = uchar; }; #elif CV_SIMD128 template <> struct VTraits<v_uint8> { static inline int vlanes() { return v_uint8::nlanes; } enum { nlanes = 16, max_nlanes = nlanes }; using lane_type = uchar; }; #endif #endif ``` However, the compile still fails when we using this method on SSE or AVX. Error caused by the unit test initializer which request max_nlanes for different vector types: ```cpp operator R () { return initializer<VTraits<R>::max_nlanes>().init(*this); } ``` and taking AVX2 for example ``` -- CPU/HW features: -- Baseline: SSE SSE2 SSE3 SSSE3 SSE4_1 POPCNT SSE4_2 FP16 FMA3 AVX AVX2 -- requested: SSE3 -- required: AVX2 -- Dispatched code generation: AVX512_SKX -- requested: SSE4_1 SSE4_2 AVX FP16 AVX2 AVX512_SKX -- AVX512_SKX (8 files): + AVX_512F AVX512_COMMON AVX512_SKX ``` then `CV_SIMD256` is enabled and `VTraits<v_uint8>::max_nlanes` is `32` and `v_uint8` is a typedef as `v_uint8x32`. This looks good, but I got a compile error which seems like SSE3 is included and required max_nlanes is 16 but not 32: ``` In file included from /root/opencv_upstream/modules/core/test/test_intrin128.simd.hpp:19, from /root/opencv_upstream/.avx/modules/core/test/test_intrin128.sse3.cpp:3: /root/opencv_upstream/modules/core/test/test_intrin_utils.hpp: In instantiation of 'static R opencv_test::hal::intrin128::opt_SSE3::initializer<32>::init(const opencv_test::hal::intrin128::opt_SSE3::Data<R>&) [with R = cv::hal_SSE3::v_uint8x16]': /root/opencv_upstream/modules/core/test/test_intrin_utils.hpp:172:64: required from 'opencv_test::hal::intrin128::opt_SSE3::Data<R>::operator R() [with R = cv::hal_SSE3::v_uint8x16]' /root/opencv_upstream/modules/core/test/test_intrin_utils.hpp:339:11: required from 'opencv_test::hal::intrin128::opt_SSE3::TheTest<R>& opencv_test::hal::intrin128::opt_SSE3::TheTest<R>::test_loadstore() [with R = cv::hal_SSE3::v_uint8x16]' /root/opencv_upstream/modules/core/test/test_intrin_utils.hpp:1739:25: required from here /root/opencv_upstream/modules/core/test/test_intrin_utils.hpp:44:16: error: no matching function for call to 'cv::hal_SSE3::v_uint8x16::v_uint8x16(const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&, const LaneType&)' 44 | return R(d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15], | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 45 | d[16], d[17], d[18], d[19], d[20], d[21], d[22], d[23], d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31]); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ```