mwirth-epo/epo-nmt-datasets huggingface dataset:
以图5中的移位寄存器SR(7)和移位寄存器SR(9)的节点X(7)和节点X(9)为例(可一并参考图3及图4)，当节点X(5)的电势在时间点t6由第一电势VL1转变成第二电势VL2且移位寄存器SR(5)开始输出扫描信号OUT(5)时，节点X(7)的电势亦依据扫描信号OUT(5)(即第一输入信号IN1)从基准电势VL0转变成第一电势VL1。
Taking the node X( 7) of the seventh-level shift register SR( 7) and the node X( 9) of the ninth-level shift register SR( 9) in FIG. 5 as an example (referring to FIG. 3 and FIG. 4 together), when the voltage level of the node X( 5) changes from the first voltage level VL 1 to the second voltage level VL 2 at a time t 6 and the fifth-level shift register SR( 5) starts outputting the fifth-level scan signal OUT( 5), the voltage level of the node X( 7) also changes from the reference voltage level VL 0 to the first voltage level VL 1 according to the fifth-level scan signal OUT( 5) (i.e., the first input signal IN 1).
在时间点t8时，时钟信号CS3由低电势升至高电势，且节点X(7)的电势依据时钟信号CS3从第一电势VL1转变成第二电势VL2。
At a time t 8, the clock signal CS 3 rises from the low voltage level to the high voltage level, and the voltage level of the node X( 7) changes from the first voltage level VL 1 to the second voltage level VL 2 according to the clock signal CS 3.
此时，移位寄存器SR(7)依据节点X(7)的电势和时钟信号CS3输出扫描信号OUT(7)至对应的扫描线SL，且节点X(9)因扫描信号OUT(7)由基准电势VL0升至第一电势VL1。
At this time, the seventh-level shift register SR( 7) outputs the seventh-level scan signal OUT( 7) to the corresponding scan line SL according to the voltage level of the node X( 7) and the clock signal CS 3, and the voltage level of the node X( 9) rises from the reference voltage level VL 0 to the first voltage level VL 1 according to the seventh-level scan signal OUT( 7).
在时间点t10时，时钟信号CS3由高电势降至低电势，且节点X(7)的电势随着从第二电势VL2转变成第一电势VL1，并使得移位寄存器SR(7)停止输出扫描信号OUT(7)至对应的扫描线SL。
At a time point t 10, the clock signal CS 3 drops from high voltage level to low voltage level, and the voltage level of the node X( 7) changes from the second voltage level VL 2 to the first voltage level VL 1, and the seventh-level shift register SR( 7) stops outputting the seventh-level scan signal OUT( 7) to the corresponding scan line SL.
随后，在时间点t12时，第二时段PD2(显示时段)结束并进入第一时段PD1(触控时段)。
Subsequently, at a time point t 12, the second period PD 2 (display period) is ended and the first period PD 1 (touch period) is started.
由于第一时段PD1穿插进两第二时段PD2之间，因此节点X(7)和节点X(9)相较于节点X(1)和节点X(3)需长时间(如数百微秒)维持在高电势。
Since the first period PD 1 is inserted between two second periods PD 2, the node X( 7) and the node X( 9) are held at high voltage level for a long time (e.g., hundreds of microseconds) compared to the node X( 1) and the node X( 3).
请参考图4及图5，在第一时段PD1开始后，顺向输入信号FW和反向输入信号BW具有同相位。
Referring to FIG. 4 and FIG. 5, the forward input signal FW and the reverse input signal BW are in phase after the first period PD 1 is started.
反向输入信号BW可例如被提高至和顺向输入信号FW相同，并因反向输入信号BW与顺向输入信号FW具有相同电势可减少薄膜晶体管M3的漏电流，使得节点X(7)和节点X(9)的电势在第一时段PD1内不受薄膜晶体管M3的漏电流的影响，并能够长时间维持在第一电势VL1。
The backward input signal BW may for example be raised to be identical to the forward input signal FW, and the leakage current of the thin film transistor M 3 may be reduced because the backward input signal BW and the forward input signal FW have the same voltage level, so that the voltage levels of the node X( 7) and the node X( 9) are not affected by the leakage current of the thin film transistor M 3 in the first period PD 1, and the voltage levels of the node X( 7) and the node X( 9) can be held at the first potential VL 1 for a long time.
接着，在第一时段PD1中的时间点t14时，时钟信号CS1由低电势升至高电势。
Next, at a time t 14 in the first period PD 1, the clock signal CS 1 rises from low voltage level to high voltage level.
此时，节点X(9)依据时钟信号CS1从第一电势VL1升至第二电势VL2，使移位寄存器SR(9)输出扫描信号OUT(9)至移位寄存器SR(7)，以开启移位寄存器SR(7)的薄膜晶体管M3。
At this time, the voltage level of the node X( 9) rises from the first voltage level VL 1 to the second voltage level VL 2 according to the clock signal CS 1, causing the ninth-level shift register SR( 9) to output the ninth-level scan signal OUT( 9) to the seventh-level shift register SR( 7) to turn on the thin film transistor M 3 of the seventh-level shift register SR( 7).
尽管移位寄存器SR(7)的薄膜晶体管M3被开启，但由于顺向输入信号FW和反向输入信号BW具有同相位，且反向输入信号BW可具有高电势，使得节点X(7)的电势仍然被维持在第一电势VL1。
Although the thin film transistor M 3 of the seventh-level shift register SR( 7) is turned on, since the forward input signal FW and the backward input signal BW are in phase and the backward input signal BW may have high voltage level, the voltage level of the node X( 7) can still be held at the first voltage level VL 1.
在时间点t16时，第二时段PD2(显示时段)结束并进入第一时段PD1(触控时段)，且反向输入信号BW从第一参考电势VR1转变成第二参考电势VR2，即顺向输入信号FW和反向输入信号BW从同相位转换成反相位。
At a time t 16, the second period PD 2 (display period) is ended and the first period PD 1 (touch period) is started, and the backward input signal BW is changed from the first reference voltage level VR 1 to the second reference voltage level VR 2, that is, the forward input signal FW and the backward input signal BW are changed from being in phase to having reverse phases.
因此，节点X(7)的电荷可通过移位寄存器SR(7)的薄膜晶体管M3流出，使得节点X(7)的电势从第一电势VL1转变成基准电势VL0。
Therefore, electric charges of the node X( 7) can flow out through the thin film transistor M 3 of the seventh-level shift register SR( 7), so that the voltage level of the node X( 7) can be changed from the first voltage level VL 1 to the reference voltage level VL 0.
在本实施例中，在时间点t14至时间点t16之间的一时间点，节点X(7)具有第一电势VL1，且移位寄存器SR(9)的节点X(9)具有第二电势VL2。
In this embodiment, at a time between the time t 14 and the time t 16, the node X( 7) has the first voltage level VL 1, and the node X( 9) of the ninth-level shift register SR( 9) has the second potential VL 2.
此外，在某些实施例中，尽管节点X(9)已从第一电势VL1升至第二电势VL2，但在第一时段PD1(触控时段)内可通过集成电路阻挡扫描信号OUT(9)输出至对应的扫描线SL，并且在第二时段PD2(显示时段)开始之后再将扫描信号OUT(9)输出至对应的扫描线SL，避免在第一时段PD1内触控感测受到显示信号的干扰，但不以此为限。
Additionally, in some embodiments, although the node X( 9) has risen from the first voltage level VL 1 to the second voltage level VL 2, the ninth-level scan signal OUT( 9) can be blocked by the IC from outputting to the corresponding scan line SL in the first period PD 1 (touch period), the ninth-level scan signal OUT( 9) can be output to the corresponding scan line SL after the second period PD 2 (display period) is started, and the touch sensing can be avoided from being interfered by the display signals in the first period PD 1, but not limited thereto.
以上移位寄存器的操作方法可应用在图5中的移位寄存器SR(7)-SR(10)、SR(15)-SR(18)，亦即在第一时段PD1内节点X(i)具有第二电势VL2的移位寄存器以及这些移位寄存器的前两级移位寄存器，但不以此为限。
The above operation method of the shift registers can be applied to the shift registers SR( 7)-SR( 10) and SR( 15)-SR( 18) in FIG. 5, that is, the shift registers in which the nodes X(i) have the second voltage level VL 2 in the first period PD 1 and the shift registers that are two levels less than these shift registers, but not limited thereto.
对于现有的栅极驱动电路108，在第一时段PD1开始之后，节点X(9)会受到薄膜晶体管M3的漏电流影响。
For the conventional gate driver circuit 108, the node X( 9) is affected by the leakage current of the thin film transistor M 3 after the first period PD 1 is started.
由于在第一时段PD1内薄膜晶体管M3长时间(可能是数百微秒)受漏电的影响，节点X(9)的电势随时间下降的程度因此变得明显。
Since the thin film transistor M 3 is affected by the leakage current for a long time (possibly hundreds of microseconds) in the first period PD 1, the decrease of the voltage level of the node X( 9) with time becomes obvious.
再者，和扫描信号OUT(9)相关的节点X(9)的第二电势VL2也同样受到影响，进而使得扫描信号OUT(9)失真，并造成显示图像具有横纹的现象。
Moreover, the second voltage level VL 2 of the node X( 9) related to the ninth-level scan signal OUT( 9) is also affected, thereby distorting the ninth-level scan signal OUT( 9) and causing the display image to have horizontal stripes.
然而，本实施例借由在第一时段PD1内提高反向输入信号BW的电势，使顺向输入信号FW和反向输入信号BW在第一时段PD1内具有同相位，减少薄膜晶体管M3的漏电流并维持节点X(9)的电势，以避免扫描信号OUT(9)失真以及显示图像具有横纹的现象。
However, in this embodiment, the forward input signal FW and the backward input signal BW can be in phase in the first period PD 1 by raising the voltage level of the backward input signal BW in the first period PD 1, the leakage current of the thin film transistor M 3 can be reduced and the voltage level of the node X( 9) can be maintained, and the distortion of the scan signal OUT( 9) and the phenomenon of horizontal stripes in the display image can be avoided.
此外，图5中的移位寄存器SR(10)、SR(17)及SR(18)，亦即在第一时段PD1内节点X(i)具有第二电势VL2的移位寄存器皆具有上述功效。
In addition, the shift registers SR( 10), SR( 17), and SR( 18) in FIG. 5 (i.e., the shift registers with the nodes X(i) having the second voltage level VL 2 in the first period PD 1) can also have the above effects.
再者，图1或图2中显示区DR左右两侧的栅极驱动电路108皆可具有上述特征和功效，但不以此为限。
Furthermore, the gate driver circuits 108 on the left and right sides of the display region DR in FIG. 1 or FIG. 2 can have the above-mentioned features and effects, but not limited thereto.
依据以上的说明，本实施例可提供一种触控显示面板10的驱动方法，其包括：提供一栅极驱动电路108，包括多个移位寄存器SR(i)，各个移位寄存器SR(i)接收一顺向输入信号FW一反向输入信号BW，且各个移位寄存器SR(i)依据顺向输入信号FW和反向输入信号BW依序输出一扫描信号OUT(i)至触控显示面板10，其中在一图帧时间FR内，将输入移位寄存器SR(i)的顺向输入信号FW和反向输入信号BW设定成至少有两次同相位。
According to the above description, a driving method of a touch display panel 10 is provided in this embodiment, the driving method includes: providing a gate driver circuit 108 including a plurality of shift registers SR(i), wherein each of the shift registers SR(i) receives a forward input signal FW and a backward input signal BW, and the shift registers SR(i) sequentially output a plurality of scan signals OUT(i) to the touch display panel 10 according to the forward input signal FW and the backward input signal BW, wherein the forward input signal FW and the backward input signal BW provided to the shift registers SR(i) are set to be in phase at least twice in a frame time FR.
藉由此驱动方法，可达到以上说明中的功效。
The effects described in the above description can be achieved by this driving method.
请参考图6，其为本发明第一实施例的共同电极接收的信号的示意图。
Referring to FIG. 6, it is a schematic diagram of signals received by a common electrode according to the first embodiment of the present invention.
本实施例的第一时段PD1(触控时段)的开始或结束可例如通过共同电极接收的信号判断。
The start or end of the first period PD 1 (touch period) of this embodiment can be determined, for example, by signals received by a common electrode.
举例而言，共同电极在各个第一时段PD1内可接收多个感测信号TS以感测物体触碰，并且在各个第二时段PD2内可接收显示信号DS以显示图像。
For example, the common electrode may receive a plurality of sensing signals TS to sense the touch of object in each of the first periods PD 1, and the common electrode may receive a display signal DS to display images in each of the second periods PD 2.
感测信号TS的电势和显示信号DS的电势不同，例如，感测信号TS可具有一感测电势Vt，显示信号DS可具有一显示基准电势Vd，且感测电势Vt可大于显示基准电势Vd，但不以此为限。
For example, the sensing signal TS may have a sensing voltage level Vt, the display signal DS may have a display reference voltage level Vd, and the sensing voltage level Vt may be greater than the display reference voltage level Vd, but not limited thereto.
借此，在一图帧时间FR内可依据共同电极接收的信号或电势变化来区分第一时段PD1以及第二时段PD2。
Therefore, the first period PD 1 and the second period PD 2 can be distinguished according to the change in signals or voltage levels received by the common electrode within a frame time FR.
然而，区分第一时段PD1以及第二时段PD2并不以上述为限，在某些实施例中，可依据触控电极信号线SSL输出及/或接收的信号电势变化来区分第一时段PD1以及第二时段PD2。
In some embodiments, the first period PD 1 and the second period PD 2 may be distinguished according to the change in the voltage level of the signal output and/or received by the touch electrode signal line SSL.
在某些实施例中，可依据扫描线SL或数据线DL输出及/或接收的信号电势变化来区分第一时段PD1以及第二时段PD2。
In some embodiments, the first period PD 1 and the second period PD 2 may be distinguished according to the change in the voltage level of the signal output and/or received by the scan line SL or the data line DL.
此外，在某些实施例中还可利用时钟信号CS1-CS4来判断第一时段PD1开始的时间点。
In addition, in some embodiments, the clock signals CS 1-CS 4 may also be used for determining the time at which the first period PD 1 is started.
举例而言，如图5所示，时钟信号CS1-CS4在第二时段PD2内依序地并周期性地由低电势升高至高电势再由高电势降低至低电势。
For example, as shown in FIG. 5, the clock signals CS 1-CS 4 are sequentially and periodically raised from low voltage level to high voltage level and then lowered from high voltage level to low voltage level in the second period PD 2.
然而在第一时段PD1开始之后，时钟信号CS1-CS4皆维持在低电势，直至第一时段PD1的末段部分或下一个第二时段PD2开始之后，时钟信号CS1-CS4才又依序地并周期性地变化。
The clock signals CS 1-CS 4 are all held at low voltage level after the first period PD 1 is started, and the clock signals CS 1-CS 4 start to change sequentially and periodically again in the end of the first period PD 1 or after the start of the next second period PD 2.
换言之，通过观察时钟信号CS1-CS4停止依序地并周期性地变化的时间点，可以判断第一时段PD1开始的时间点。
Therefore, the time at which the first period PD 1 starts can be determined by observing the time at which the clock signals CS 1-CS 4 stop changing sequentially and periodically.
且离子注入方向与所述基底法线的夹角为0度，使得更多的掺杂离子注入到源漏掺杂区103中，有利于提高第一掺杂区109的掺杂浓度。
Moreover, the included angle between the ion implantation direction and the normal of the base is 0 degree, which makes more doping ions be implanted into the source-drain doped region 103 and is beneficial to improving the doping concentration of the first doped region 109.
其他实施例中，所述半导体结构为NMOS，形成所述第一掺杂区的工艺参数包括：掺杂离子包括：磷、砷和锑中的一种或多种；注入能量为1Kev至5Kev；掺杂离子的注入剂量为1E15原子每平方厘米至3E15原子每平方厘米；注入方向与所述基底法线的夹角为0度。
In other implementations, the semiconductor structure is an NMOS, and the process parameters for forming the first doped region include doping ions which includes one or more of phosphorus, arsenic and antimony; implantation energy which is 1 Kev to 5 Kev; implantation dose of doping ions which is 1E15 atoms per square centimeter to 3E15 atoms per square centimeter; and implantation direction, wherein the included angle between the implantation direction and the normal of the base is 0 degree.
需要说明的是，形成第一掺杂区109后，对第一掺杂区109进行退火处理，退火处理为尖峰退火工艺或激光退火工艺。
It should be noted that, after forming the first doped region 109, annealing treatment is performed on the first doped region 109, and the annealing treatment is either peak annealing process or laser annealing process.
尖峰退火工艺和激光退火工艺为半导体领域中常用的退火工艺，有利于提高工艺兼容性。
Peak annealing process and laser annealing process are commonly used annealing processes in the field of semiconductors, and are beneficial to improving process compatibility.
退火处理能够激活第一掺杂区109中的掺杂离子，修复晶格缺陷，且因为退火处理的时间短，第一掺杂区109中的离子不易扩散至栅极结构106下方的沟道区中，使得后续半导体工作时栅极结构106下方的电场强度不易过强，栅极结构106不易被破坏。
Because the time of annealing treatment is short, the ions in the first doped region 109 are not easy to diffuse into the channel area below the gate structure 106, which makes the intensity of the electric field under the gate structure 106 not too strong and the gate structure 10 not easily destroyed when the semiconductor works subsequently.
如图8所示，形成所述第一掺杂区109后，对所述开口108露出的源漏掺杂区103进行离子掺杂，在所述第一掺杂区109上形成第二掺杂区110，所述第二掺杂区110与源漏掺杂区103的掺杂离子类型相同，所述第二掺杂区110的掺杂离子浓度大于所述源漏掺杂区103的掺杂离子浓度，且第二掺杂区110在基底上的投影覆盖所述第一掺杂区109在所述基底上的投影。
The doping ion type of the second doped region 110 is the same as the doping ion type of the source-drain doped region 103, the ion doping concentration of the second doped region 110 is higher than the ion doping concentration of the source-drain doped region 103, and the projection of the second doped region 110 on the base covers the projection of the first doped region 109 on the base.
所述开口108呈倒梯形，后续刻蚀第一掺杂区109和第二掺杂区110形成沟槽的过程中，刻蚀轨迹易沿开口108的侧壁向下，因此形成的沟槽也呈倒梯形。
In the process of subsequently etching the first doped region 109 and the second doped region 110 to form the groove, the etching trajectory is easily downward along the sidewall of the opening 108, so the formed groove is also in the shape of an inverted trapezoid.
第二掺杂区110位于所述第一掺杂区109上，且第二掺杂区110在基底上的投影覆盖第一掺杂区109在基底上的投影，使得后续形成的沟槽的顶部位于第二掺杂区110中，后续在沟槽中形成的接触孔插塞位于所述第一掺杂区109和第二掺杂区110中，使得后续接触孔插塞的侧壁不易直接与源漏掺杂区103接触，进而降低了接触孔插塞与源漏掺杂区103的接触电阻。
The second doped region 110 is located over the first doped region 109, and the projection of the second doped region 110 on the base covers the projection of the first doped region 109 on the base, such that the top of the subsequently formed groove is located in the second doped region 110, and the contact hole plug subsequently formed in the groove is located in the first doped region 109 and the second doped region 109.
第二掺杂区110不宜过厚也不宜过薄。
The second doped region 110 should not be too thick or too thin.
若第二掺杂区110过厚，也就是说第二掺杂区110的区域较大，因为第二掺杂区110中的掺杂离子浓度高于源漏掺杂区103中的掺杂离子浓度，第二掺杂区110中的掺杂离子易扩散至鳍部101中的沟道区中，在半导体结构工作时，源漏掺杂区103源极和漏极的耗尽层扩展，导致短沟道效应较严重。
If the second doped region 110 is too thick, that is to say, the area of the second doped region 110 is large, because the ion doping concentration in the second doped region 110 is higher than the ion doping concentration of the source-drain doped region 103, the doping ions in the second doped region 110 can easily diffuse into the channel region in the fin 101, and when the semiconductor structure works, the source and drain depletion layers of the source-drain doped region 103 are expanded, resulting in serious short-channel effects.
若第二掺杂区110过薄，后续形成在沟槽112中的接触孔插塞顶部侧壁易直接与源漏掺杂区103接触，导致接触孔插塞与源漏掺杂区103的接触电阻较大。
If the second doped region 110 is too thin, the top sidewall of the contact hole plug formed in the groove 112 is easily in direct contact with the source-drain doped region 103, resulting in that the contact resistance between the contact hole plug and the source-drain doped region 103 is large.
本实施例中，第二掺杂区110的厚度为2纳米至5纳米。
In some implementations, the thickness of the second doped region 110 is 2 nanometers to 5 nanometers.
本实施例中，采用离子注入的方式形成第二掺杂区110。
In some implementations, the second doped region 110 is formed by adopting ion implantation.
本实施例中，所述半导体结构为PMOS，形成第二掺杂区110的工艺参数包括：掺杂离子包括：硼、镓和铟中的一种或多种。
In some implementations, the semiconductor structure is a PMOS, and the process parameters for forming the second doped region 110 include doping ions which include one or more of boron, gallium and indium.
具体表述参照形成第一掺杂区109，在此不再赘述。
For specific description, refer to the formation of the first doped region 109, which will not be repetitively described here.
本实施例中，注入能量为1Kev至5Kev。
In some implementations, the implantation energy is 1 Kev to 5 Key.
掺杂离子的注入剂量为1E15原子每平方厘米至3E15原子每平方厘米。
The implantation dose of doping ions is 1E15 atoms per square centimeter to 3E15 atoms per square centimeter.
离子注入方向与所述基底法线的夹角不宜太大，也不宜太小。
The included angle between the ion implantation direction and the normal of the base should not be too large or too small.
若所述夹角太大，根据离子注入的遮蔽效应，易导致形成第二掺杂区110的过程中，掺杂入源漏掺杂区103的离子较少，导致第二掺杂区110的形成质量较差。
If the included angle is too large, according to the shielding effect of ion implantation, in the process of forming the second doped region 110, the ions doped into the source-drain doped region is easily caused to be fewer, resulting in poor formation quality of the second doped region 110.
若所述夹角太小，在垂直于栅极结构106的延伸方向上，所述掺杂离子扩散距离较小，导致形成的第二掺杂区110的宽度较小，后续形成的接触孔插塞顶部易直接与源漏掺杂区103接触，导致接触孔插塞与源漏掺杂区103的接触电阻较大。
If the included angle is too small, in the extension direction perpendicular to the gate structure 106, the diffusion distance of the doping ions is small, resulting in that the width of the formed second doped region 110 is small, and the top of the subsequently formed contact hole plug is easily in direct contact with the source-drain doped region 103, resulting in that the contact resistance between the contact hole plug and the source-drain doped region 103 is large.
本实施例中，注入方向与所述基底法线的夹角为4度至15度。
In some implementations, the included angle between the implantation direction and the normal of the base is 4 degrees to 15 degrees.
其他实施例中，所述半导体结构为NMOS，所述第二离子掺杂的工艺参数包括：掺杂离子包括：磷、砷和锑中的一种或多种；注入能量为1Kev至5Kev；掺杂离子的注入剂量为1E15原子每平方厘米至3E15原子每平方厘米；注入方向与所述基底法线的夹角为4度至15度。
In other implementations, the semiconductor structure is an NMOS, and the process parameters for the second ion doping include doping ions which include one or more of phosphorus, arsenic and antimony; implantation energy which is 1 Kev to 5 Kev; implantation dose of doping ions which is 1E15 atoms per square centimeter to 3E15 atoms per square centimeter; implantation direction, wherein the included angle between the implantation direction and the normal of the base is 4 degrees to 15 degrees.
所述半导体结构的形成方法还包括：在形成第一掺杂区109后，进行第二离子掺杂前，去除所述开口108露出的所述抗刻蚀层105。
The method for forming the semiconductor structure further includes, after forming the first doped region 109 and before performing second ion doping, removing the anti-etching layer 105 exposed by the opening 108.
去除所述抗刻蚀层105使得掺杂离子形成第二掺杂区的过程中，掺杂离子的能量在注入的过程中不易消耗，使得在垂直于栅极结构106的延伸方向上，所述第二掺杂区110的宽度较大，从而后续形成的接触孔插塞顶部不易与源漏掺杂区103接触，有利于减小接触孔插塞与源漏掺杂区103的接触电阻。
In the process of removing the anti-etching layer 105 to make the doping ions to form the second doped region, the energy of the doping ions is not easily consumed in the process of implantation, such that the width of the second doped region 110 is larger in the extension direction perpendicular to the gate structure 106, the top of the subsequently formed contact hole plug is not easily in contact with the source-drain doped region 103 and it is beneficial to reducing the contact resistance between the contact hole plug and the source-drain doped region 103.
本实施例中，因为所述源漏掺杂区103的浓度小于所述第一掺杂区109和第二掺杂区110的掺杂浓度，因此，从开口108指向沟道区的方向上离子掺杂浓度递减，从而第一掺杂区109和第二掺杂区110中的掺杂离子不易穿过源漏掺杂区103进入沟道区，降低后续半导体工作时源漏掺杂区103源极和漏极的耗尽层扩展的概率，进而改善短沟道效应。
In some implementations, because the concentration of the source-drain doped region 103 is lower than the doping concentration of the first doped region 109 and the second doped region 110, the ion doping concentration gradually decreases in the direction from the opening 108 to the channel region, such that the doping ions in the first doped region 109 and the second doped region 110 are not easy to pass through the source-drain doped region 103 and enter the channel region, the probability of the expansion of the source and drain depletion layers of the source-drain doped region 103 when the semiconductor works is reduced, and the short-channel effects are improved.
需要说明的是，形成第二掺杂区110后，对第二掺杂区110进行退火处理。
It should be noted that, after forming the second doped region 110, annealing treatment is performed on the second doped region 110.
有关退火工艺的相关描述参照形成第一掺杂区109后的相关描述，在此不再赘述。
For the description related to the annealing process, refer to the related description after the formation of the first doped region 109, which will not be repetitively described here.
参考图9，形成所述第二掺杂区110后，刻蚀所述开口108底部的第一掺杂区109和第二掺杂区110，形成由第一掺杂区109和第二掺杂区110围成的沟槽112。
Referring to FIG. 9, after forming the second doped region 110, the first doped region 109 and the second doped region 110 at the bottom of the opening 108 are etched to form a groove 112 surrounded by the first doped region 109 and the second doped region 110.
所述沟槽112为后续形成接触孔插塞提供空间，且所述沟槽112位于所述源漏掺杂区103中，有利于增大接触孔插塞和源漏掺杂区103的接触面积，进而减小接触孔插塞和源漏掺杂区103的接触电阻。
The groove 112 provides a space for the subsequent formation of the contact hole plug, and the groove 112 is located in the source-drain doped region 103, which is beneficial to increasing the contact area between the contact hole plug and the source-drain doped region 103, thereby reducing the contact resistance between the contact hole plug and the source-drain doped region 103.
所述沟槽112由第一掺杂区109和第二掺杂区110围成，所述第一掺杂区109和第二掺杂区110的掺杂浓度高于所述源漏掺杂区103的掺杂浓度，有利于减小接触孔插塞和源漏掺杂区103的接触电阻。
The groove 112 is surrounded by the first doped region 109 and the second doped region 110, and the doping concentration of the first doped region 109 and the second doped region 110 is higher than the doping concentration of the source-drain doped region 103, which is beneficial to reducing the contact resistance between the contact hole plug and the source-drain doped region 103.
本实施例中，采用干法刻蚀工艺刻蚀所述第一掺杂区109和第二掺杂区110，形成沟槽112。
In some implementations, a dry etching process is adopted to etch the first doped region 109 and the second doped region 110 to form the groove 112.
干法刻蚀工艺为各向异性刻蚀工艺，具有较好的刻蚀剖面控制性，降低对其他膜层结构的损伤，有利于使沟槽112的形貌满足工艺需求，提高沟槽112的形成效率。
Dry etching process is an anisotropic etching process, which has better controllability of etching profile, reduces the damage to other film structures, is beneficial to making the morphology of the groove 112 meet the technological requirements and improves the formation efficiency of the groove 112.
需要说明的是，所述沟槽112的底面和开口108的底面距离D不宜太大。
It should be noted that a distance D between a bottom surface of the groove 112 and a bottom surface of the opening 108 should not be too great.