mwirth-epo/epo-nmt-datasets huggingface dataset:
另外，当时段TP1和时段TP2的比小于3：5时，例如时段TP1小于三个时间单位时，移位寄存器SR(i)中的薄膜晶体管的充电效能会受到影响。
In addition, when the ratio of the time period TP 1 to the time period TP 2 is less than 3:5 (e.g., when the time period TP 1 is less than three units of time), the charging efficiency of the thin film transistor in the shift register SR(i) may be affected.
在习知的触控显示面板中，时钟信号位在高电势和位在低电势的时段通常是相同的，例如时段TP1和时段TP2皆是四个时间单位。
In the conventional touch display panel, the time durations of the clock signal having high voltage level and low voltage level are usually identical, for example, the time period TP 1 and the time period TP 2 may both include four units of time.
然而在本实施例中，在周期同为八个时间单位的情况下，将时段TP1缩短为三个时间单位，并将时段TP2延长为五个时间单位，其中缩短时段TP1即代表缩短扫描信号OUT(i)的输出时间。
However, the time period TP 1 is shortened to include three units of time and the time period TP 2 is extended to include five units of time when each period (the sum of the time period TP 1 and the time period TP 2) includes eight units of time in this embodiment, and the output time of the scan signal OUT(i) is shortened as the time period TP 1 is shortened.
由于扫描信号OUT(i)会对其他图像显示信号FS产生纹波(ripple)，并使显示图像具有横纹的现象并降低图像的显示品质，因此，本实施例通过缩短时段TP1以缩短扫描信号OUT(i)的输出时间，可减少图像显示信号FS因扫描信号OUT(i)产生纹波的现象，以提升图像的显示品质。
Since the scan signal OUT(i) will cause other image display signals FS to have ripples and cause the display image to have horizontal stripes and reduce the display quality of the image, the ripples in the image display signal FS caused by the scan signal OUT(i) can be reduced by shortening the time period TP 1 and shortening the output time of the scan signal OUT(i) in this embodiment, and the display quality of the image can be improved.
在本实施例中，图像显示信号FS可例如是共同电极接收的信号、数据线DL接收的信号或是其他和显示相关的信号，但不以此为限。
In this embodiment, the image display signal FS may be, for example, a signal received by the common electrode, a signal received by the data line DL, or other display-related signals. but not limited thereto.
详细而言，对应图帧时间FR的开始阶段输出的扫描信号OUT(i)会对触控显示面板10中的其他图像显示信号FS产生纹波，例如图8中的扫描信号OUT(1)、OUT(2)。
Specifically, the scan signal OUT(i) output in the beginning of the frame time FR will cause the other image display signals FS in the touch display panel 10 to have ripples, such as the scan signals OUT( 1) and OUT( 2) in FIG. 8.
虽然图8未绘示，但和图帧时间FR的开始阶段相似的是，对应图帧时间FR的结束阶段输出的扫描信号OUT(i)也会对触控显示面板10中的其他图像显示信号FS产生纹波。
Similar to the beginning of the frame time FR, the scan signal OUT(i) output in the end of the frame time FR (not shown in FIG. 8 ) also causes the other image display signals FS in the touch display panel 10 to have ripples.
此外，对应触控时段(即第一时段PD1)的开始阶段及结束阶段输出的扫描信号OUT(i)也会对触控显示面板10中的其他图像显示信号FS产生纹波，例如图8中对应第一时段PD1的开始阶段的扫描信号OUT(7)、OUT(8)，以及对应第一时段PD1的结束阶段的扫描信号OUT(9)、OUT(10)。
In addition, the scan signals OUT(i) output in the beginning and the end of the touch period (i.e., the first period PD 1) also cause the other image display signals FS in the touch display panel 10 to have ripples, such as the scan signals OUT( 7) and OUT( 8) corresponding to the beginning of the first period PD 1, and the scan signals OUT( 9) and OUT( 10) corresponding to the end of the first period PD 1 in FIG. 8.
本实施例通过缩短时段TP1以缩短扫描信号OUT(i)的输出时间的作法可改善上述不同时间区段内纹波的现象。
In this embodiment, the ripples of signals in different periods of time can be reduced by shortening the time period TP 1 and shortening the output time of the scan signal OUT(i).
另一方面，如图8所示，本实施例的其中一个栅极驱动电路108是顺向扫描驱动，因此在图帧时间FR中，顺向输入信号FW的电势皆保持高于反向输入信号BW的电势。
As shown in FIG. 8, one of the gate driver circuits 108 in this embodiment may be in the forward scanning mode, and the voltage level of the forward input signal FW may be greater than the voltage level of the backward input signal BW throughout the frame time FR.
例如，顺向输入信号FW是VGH而反向输入信号BW是VGL。
For example, the voltage level of the forward input signal FW may be VGH, and the voltage level of the backward input signal BW may be VGL, but not limited thereto.
此外，本实施例的另一个栅极驱动电路108可以是反向扫描驱动，其中在图帧时间FR中，顺向输入信号FW的电势皆保持低于反向输入信号BW的电势。
In addition, the other gate driver circuit 108 in this embodiment may be in the backward scanning mode, and the voltage level of the forward input signal FW may be less than the voltage level of the backward input signal BW throughout the frame time FR.
例如，顺向输入信号FW是VGL而反向输入信号BW是VGH。
For example, the voltage level of the forward input signal FW may be VGL, and the voltage level of the backward input signal BW may be VGH.
然而栅极驱动电路108的驱动方式不以上述为限。
However, the driving method of the gate driver circuits 108 is not limited to the above description.
综上所述，在本发明的栅极驱动电路及触控显示面板的驱动方法中，在触控时段(即第一时段)内将顺向输入信号和反向输入信号设定成具有同相位，例如将顺向输入信号和反向输入信号设定成具有相同的电势，可减少移位寄存器中的薄膜晶体管的漏电流，以避免移位寄存器输出的扫描信号失真以及显示图像具有横纹的现象，进而提升图像显示品质。
Therefore, the leakage current of the thin film transistor in the shift register can be reduced to avoid the distortion of the scan signal output by the shift register and the phenomenon that the display image has horizontal stripes, thereby improving the image display quality.
此外，另可通过缩短时钟信号具有高电势的时间以缩短扫描信号的输出时间，进而改善扫描信号对触控显示面板中的其他图像显示信号产生纹波的现象。
In addition, the output time of the scan signal can be shortened by shortening the time duration of the clock signal having high voltage level, thereby reducing the phenomenon that the scan signal causes other image display signals to have ripples in the touch display panel.
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
本实施例中，注入能量为0.5Kev至2.5Kev。
In some implementations, the implantation energy is 0.5 Kev to 2.5 Kev.
若离子的注入剂量太大，易导致第三掺杂区114中的离子掺杂浓度过大，掺杂离子易扩散至鳍部101中的沟道区中，在半导体结构工作时，源漏掺杂区103源极和漏极的耗尽层扩展，导致短沟道效应较严重。
If the ion implantation dose is too large, the ion doping concentration of the third doped region 114 will be too high, the doping ions will easily diffuse into the channel region in the fin 101, and when the semiconductor structure works, the source and drain depletion layers of the source-drain doped region 103 will be expanded, resulting in serious short-channel effects.
若离子的注入剂量太小，第三掺杂区114中的掺杂浓度较小，当沟槽112(如图10所示)过深时，接触孔插塞与第三掺杂区114接触，第三掺杂区114难以起到减小接触孔插塞与源漏掺杂区103接触电阻的目的。
When the groove 112 (as illustrated in FIG. 10 ) is too deep, the contact hole plug is in contact with the third doped region 114.
本实施例中，离子注入剂量为5E14原子每平方厘米至15E14原子每平方厘米。
In this example, the ion implantation dose is 5E14 atoms per square centimeter to 15E14 atoms per square centimeter.
需要说明的是，注入方向与基底法线的夹角不宜太大，也不宜太小。
It should be noted that the included angle between the implantation direction and the normal of the base should not be too large or too small.
若所述夹角太大，第三掺杂区114中的掺杂离子易扩散至鳍部101中的沟道区中，在半导体结构工作时，源漏掺杂区103源极和漏极的耗尽层扩展，导致短沟道效应较严重。
If the included angle is too large, the doping ions in the third doped region 114 can easily diffuse into the channel region in the fin 101, and when the semiconductor structure works, the source and drain depletion layers of the source- and drain doped region 103 will be expanded, resulting in serious short-channel effects.
若所述夹角太小，在垂直于栅极结构106侧壁的方向上，所述掺杂离子扩散距离较小，导致形成的第三掺杂区114的宽度较小，所述接触孔插塞侧壁易直接与源漏掺杂区103接触，不易减小接触孔插塞侧壁与源漏掺杂区103的接触电阻。
If the included angle is too small, in the direction perpendicular to the sidewall of the gate structure 106, the diffusion distance of the doping ions is short, resulting in that the width of the formed third doped region 114 is small, the sidewall of the contact hole plug is easily in direct contact with the source-drain doped region 103, and it is not easy to reduce the contact resistance between the sidewall of the contact hole plug and the source-drain doped region 103.
本实施例中，注入方向与基底法线的夹角为0度至9度。
In some implementations, the included angle between the implantation direction and the normal of the base is 0 degree to 9 degrees.
其他实施例中，所述半导体结构为NMOS，所述离子掺杂的工艺参数包括：掺杂离子包括：磷、砷和锑中的一种或多种；注入能量为0.5Kev至2.5Kev；掺杂离子的注入剂量为5E14原子每平方厘米至15E14原子每平方厘米，注入方向与所述基底法线的夹角为0度至9度。
In other implementations, the semiconductor structure is an NMOS, and the process parameters for ion doping include doping ions which include one or more of phosphorus, arsenic and antimony; implantation energy which is 0.5 Kev to 2.5 Kev; implantation dose of doping ions which is 5E14 atoms per square centimeter to 15E14 atoms per square centimeter; and implantation direction, wherein the included angle between the implantation direction and the normal of the base is 0 degree to 9 degrees.
本实施例中，因为所述源漏掺杂区103的浓度小于所述第一掺杂区109、第二掺杂区110和第三掺杂区114的掺杂浓度，因此，从接触孔插塞指向沟道区的方向上离子掺杂浓度递减，从而第一掺杂区109、第二掺杂区110和第三掺杂区114中的掺杂离子不易穿过源漏掺杂区103进入沟道区，使得半导体工作时源漏掺杂区103源极和漏极的耗尽层不易扩展，减缓短沟道效应。
In some implementations, because the concentration of the source-drain doped region 103 is lower than the doping concentration of the first doped region 109, the second doped region 110 and the third doped region 114, the ion doping concentration gradually decreases in the direction from the contact hole plug to the channel region in the substrate 100, such that the doping ions in the first doped region 109, the second doped region 110 and the third doped region 114 are not easy to pass through the source-drain doped region 103 and enter the channel region, the source and drain depletion layers of the source-drain doped region 103 are not easily expanded when the semiconductor works, and the short-channel effects are relieved.
需要说明的是，在形成第三掺杂区114后，形成接触孔插塞113前，还包括：在所述沟槽112中形成所述金属硅化物层。
It should be noted that, after forming the third doped region 114 and before forming the contact hole plug 113, the metal silicide layer is formed in the groove 112.
需要说明的是，形成第三掺杂区114后，还包括：对第三掺杂区114进行退火处理。
It should be noted that, after forming the third doped region 114, the method further includes performing annealing treatment on the third doped region 114.
有关退火工艺的相关描述参照形成第三掺杂区114后的相关描述，在此不再赘述。
For the description related to the annealing process, refer to the description after the formation of the third doped region 114, which will not be repetitively described here.
相应的，本发明实施例还提供一种半导体结构。
In another form, the present disclosure further provides a semiconductor structure.
参考图11，示出了本发明半导体结构第一实施例的结构示意图。
FIG. 11 illustrates a structural schematic diagram of one form of a semiconductor structure according to the present disclosure.
半导体结构包括：基底，所述基底包括衬底100、位于所述衬底100上的栅极结构106、位于所述栅极结构106两侧所述衬底100中的源漏掺杂区103以及位于所述源漏掺杂区103上的层间介质层104；接触孔插塞113，位于所述源漏掺杂区103中，且所述源漏掺杂区103覆盖所述接触孔插塞113的部分侧壁；第一掺杂区109，位于所述源漏掺杂区103中，且位于所述接触孔插塞113的底部与源漏掺杂区103之间，所述第一掺杂区109的掺杂离子类型与源漏掺杂区103的掺杂离子类型相同，且第一掺杂区109的离子掺杂浓度高于所述源漏掺杂区103的离子掺杂浓度；第二掺杂区110，位于所述源漏掺杂区103中，且位于所述第一掺杂区109上，所述第二掺杂区110的掺杂离子类型与源漏掺杂区103的掺杂离子类型相同，第二掺杂区110的离子掺杂浓度高于所述源漏掺杂区103的离子掺杂浓度，所述第二掺杂区110覆盖所述接触孔插塞113的部分侧壁，且所述第二掺杂区110在基底上的投影覆盖所述第一掺杂区109在所述基底上的投影。
The semiconductor structure includes: a base, the base including a substrate 100, a gate structure 106 over the substrate 100, a source-drain doped region 103 in the substrate 100 on two sides of the gate structure 106, and an interlayer dielectric layer 104 over the source-drain doped region 103; a contact hole plug 113 in the source-drain doped region 103, the source-drain doped region 103 covering part of the sidewall of the contact hole plug 113; a first doped region 109 in the source-drain doped region 103 and between the bottom of the contact hole plug 113 and the source-drain doped region 103, the doping ion type of the first doped region 109 being the same as the doping ion type of the source-drain doped region 103, and the ion doping concentration of the first doped region 109 being higher than the ion doping concentration of the source-drain doped region 103; and a second doped region 110 in the source-drain doped region 103 and over the first doped region 109, the doping ion type of the second doped region 110 being the same as the doping ion type of the source-drain doped region 103, the ion doping concentration of the second doped region 110 being higher than the ion doping concentration of the source-drain doped region 103, the second doped region 110 covering part of the sidewall of the source-drain doped region 113, and the projection of the second doped region 110 on the base covering the projection of the first doped region 109 on the base.
本实施例中所述第一掺杂区109与所述接触孔插塞113的底部和侧壁接触，所述第二掺杂区110与接触孔插塞的侧壁接触，所述第一掺杂区109和第二掺杂区110包围位于所述源漏掺杂区103中的所述接触孔插塞113，使得接触孔插塞113不易直接与源漏掺杂区103接触，降低了接触孔插塞113与源漏掺杂区103的接触电阻，改善了半导体结构的电学性能。
In some implementations, the first doped region 109 is in contact with the bottom and sidewall of the contact hole plug 113, the second doped region 110 is in contact with the sidewall of the contact hole plug, and the first doped region 109 and the second doped region 110 surround the contact hole plug 113 in the source-drain doped region 103, such that the contact hole plug 113 is not easily in direct contact with the source-drain doped region 103, the contact resistance between the contact hole plug 113 and the source-drain doped region 103 is reduced, and the electrical performance of the semiconductor structure is improved.
此外，因为所述源漏掺杂区103的浓度小于所述第一掺杂区109和第二掺杂区110的掺杂浓度，因此，从接触孔插塞113指向衬底100中沟道区的方向上离子掺杂浓度递减，从而第一掺杂区109和第二掺杂区110中的掺杂离子不易穿过源漏掺杂区103进入沟道区，使得半导体工作时源漏掺杂区103源极和漏极的耗尽层不易扩展，减缓短沟道效应。
In addition, because the concentration of the source-drain doped region 103 is lower than the doping concentration of the first doped region 109 and the second doped region 110, the ion doping concentration gradually decreases in the direction from the contact hole plug 113 to the channel region in the substrate 100, such that the doping ions in the first doped region 109 and the second doped region 110 are not easy to pass through the source-drain doped region 103 and enter the channel region, the source and drain depletion layers of the source-drain doped region 103 are not easily expanded when the semiconductor works, and the short-channel effects are relieved.
本实施例以半导体结构为鳍式场效应晶体管(FinFET)为例，衬底100为具有鳍部101的衬底100。
In some implementations, the semiconductor structure is a fin field effect transistor (FinFET), and the substrate 100 is a substrate 100 with a fin 101.
鳍部101用于在半导体结构工作时，提供鳍式场效应晶体管的沟道。
The fin 101 is used for providing the channel of the fin field effect transistor when the semiconductor structure works.
本实施例中，鳍部101与衬底100为一体结构。
In some implementations, the fin 101 and the substrate 100 are in an integral structure.
鳍部101与衬底100的材料相同。
The material of the fin 101 is the same as the material of the substrate 100.
所述栅极结构106横跨鳍部101，且覆盖鳍部101的部分顶壁和部分侧壁。
The gate structure 106 spans the fin 101 and covers part of the top wall and part of the sidewall of the fin 101.
本实施例中，栅极结构106包括保形覆盖鳍部101的部分顶面和部分侧壁的栅介质层1061和位于栅介质层1061上的金属栅极层1062。
In some implementations, the gate structure 106 includes a gate dielectric layer 1061 covering part of the top surface and sidewall of the fin 101 conformally and a metal gate layer 1062 over the gate dielectric layer 1061.
栅介质层1061的材料为高k介质层。
The material of the gate dielectric layer 1061 is a high-k dielectric layer.
本实施例中，栅介质层1061的材料为HfO2。
In some implementations, the material of the gate dielectric layer 1061 is HfO2.
源漏掺杂区103，位于栅极结构106两侧的鳍部101中。
The source-drain doped region 103 is located in the fin 101 on two sides of the gate structure 106.
在半导体结构工作时，源漏掺杂区103为栅极结构106下方的沟道提供应力，提高载流子的迁移率。
When the semiconductor structure works, the source-drain doped region 103 provides stress for the channel below the gate structure 106 and improves the carrier mobility.
本实施例中，所述半导体结构用于形成PMOS晶体管，即所述源漏掺杂区103的材料为掺杂P型离子的锗化硅。
In some implementations, the semiconductor structure is used to form a PMOS transistor, that is, the material of the source-drain doped region 103 is silicon germanide doped with P-type ions.
本实施例通过在锗化硅中掺杂P型离子，使P型离子取代晶格中硅原子的位置，掺入的P型离子越多，多子的浓度就越高，导电性能也就越强。
In some implementations, by doping P-type ions in silicon germanide, P-type ions replace the positions of silicon atoms in the lattice, the more P-type ions are doped, the higher the concentration of free electrons is, and the stronger the conductivity is.
其他实施例中，所述半导体结构用于形成NMOS晶体管，即所述源漏掺杂区的材料相应为掺杂N型离子的碳化硅或磷化硅。
In other implementations, the semiconductor structure is used for forming an NMOS transistor, that is, the material of the source-drain doped region is correspondingly silicon carbide or silicon phosphide doped with N-type ions.
通过在碳化硅或磷化硅中掺杂N型离子，使N型离子取代晶格中硅原子的位置，掺入的N型离子越多，多子的浓度就越高，导电性能也就越强。
By doping N-type ions in silicon carbide or silicon phosphide, N-type ions replace the positions of the silicon atoms in the lattice, the more N-type ions are doped, the higher the concentration of free electrons is, and the stronger the conductivity is.
层间介质层104用于实现相邻半导体结构之间的电隔离。
The interlayer dielectric layer 104 is used for realizing electrical isolation between adjacent semiconductor structures.
因此，层间介质层104的材料为绝缘材料。
Therefore, the material of the interlayer dielectric layer 104 is an insulating material.
具体的，层间介质层104的材料为氧化硅。
Specifically, the material of the interlayer dielectric layer 104 is silicon oxide.
所述半导体结构还包括：抗刻蚀层105，位于所述层间介质层104与源漏掺杂区103之间，以及所述层间介质层104和栅极结构106之间。
The semiconductor structure further includes an anti-etching layer 105, which is located between the interlayer dielectric layer 104 and the source-drain doped region 103, and between the interlayer dielectric layer 104 and the gate structure 106.
在形成半导体结构的过程中，抗刻蚀层105原先覆盖源漏掺杂区103，对抗刻蚀层105进行离子掺杂，掺杂离子穿过抗刻蚀层105在源漏掺杂区103中形成第一掺杂区109。
In the process of forming the semiconductor structure, the anti-etching layer 105 originally covers the source-drain doped region 103, ion doping is performed on the anti-etching layer 105, and the doping ions pass through the anti-etching layer 105 to form the first doped region 109 in the source-drain doped region 103.
形成第一掺杂区109的过程中，抗刻蚀层105能够削弱掺杂离子的能量，避免掺杂离子的注入能量过大对源漏掺杂区103的晶格造成过大损伤，使得掺杂离子不易在晶格缺陷中快速扩散至鳍部101中的沟道区中，在半导体结构工作时，源漏掺杂区103的源极和漏极的耗尽层不易扩展，减缓了短沟道效应。
In the process of forming the first doped region 109, the anti-etching layer 105 can weaken the energy of doping ions and avoid the excessive damage to the lattice of the source-drain doped region 103 caused by the excessive implantation energy of doping ions, which makes the doping ions not easy to diffuse rapidly into the channel region in the fin 101 in the lattice defects, when the semiconductor structure works, the source and drain depletion layers of the source-drain doped region 103 are not easily expanded and the short-channel effects are relieved.
另外，抗刻蚀层105在刻蚀层间介质层104形成开口108(如图8所示)的过程中，定义刻蚀工艺刻蚀停止的位置，从而保障刻蚀形成开口108的同时，降低刻蚀工艺对源漏掺杂区103造成过刻蚀的概率。
In addition, in the process of etching the interlayer dielectric layer 104 to form an opening 108 (as illustrated in FIG. 8 ), the anti-etching layer 105 defines the etch stop position of the etching process, such that the formation of the opening 108 by etching is guaranteed and the probability of over-etching of the source-drain doped region 103 caused by the etching process is reduced at the same time.
所述抗刻蚀层105的材料采用低K介电常数的材料，因此，抗刻蚀层105的材料还能够起到减小源漏掺杂区103和栅极结构106电容耦合效应的作用。
Because the material of the anti-etching layer 105 is a material with a low-K dielectric constant, the material of the anti-etching layer 105 can also play a role of reducing the capacitive coupling effect of the source-drain doped region 103 and the subsequent gate structure 106.
需要说明的是，所述抗刻蚀层105不宜过厚也不宜过薄。
It should be noted that the anti-etching layer 105 should not be too thick or too thin.
若所述抗刻蚀层105过厚，在形成第一掺杂区109的过程中，离子不易穿过抗刻蚀层105，导致第一掺杂区109的掺杂浓度过低且形成区域过小，不利于减小接触孔插塞与源漏掺杂区103的接触电阻。
If the anti-etching layer 105 is too thick, it is not easy for ions to pass through the anti-etching layer 105 in the process of forming the first doped region 109, resulting in that the doping concentration of the first doped region 109 is too low and the region is too small, which is not beneficial to reducing the contact resistance between the contact hole plug and the source-drain doped region 103.
1.一种菌处理机构，其特征在于包括：
1.
去污处理流体供给部，在所述供气管道的初期去污时，将去污处理流体供给至所述供气管道；以及
A bacteria treatment mechanism comprising: a bacteria treatment unit having a space for performing bacteria treatment; a radiation irradiation unit that irradiates the bacteria treatment unit with radiation for performing the bacteria treatment; an air supply duct that supplies air to the bacteria treatment unit; a decontamination treatment fluid supply unit that supplies a decontamination treatment fluid to the air supply duct during initial decontamination of the air supply duct; and an exhaust duct that exhausts molecules in the bacteria treatment unit.
2.根据权利要求1所述的菌处理机构，其特征在于，
2.
所述去污处理流体为具有去污功能的气体或雾。
The bacteria treatment mechanism according to claim 1, wherein the decontamination treatment fluid is a gas or mist having a decontamination function.
3.根据权利要求2所述的菌处理机构，其特征在于，
3.
所述去污处理流体中包含过氧化氢。
The bacteria treatment mechanism according to claim 2, wherein the decontamination treatment fluid contains hydrogen peroxide.
4.根据权利要求4所述的菌处理机构，其特征在于，
4.
在所述菌处理部中，利用从所述放射线照射部所照射的所述放射线进行对象物的灭菌。
The bacteria treatment mechanism according to claim 1, wherein in the bacteria treatment unit, an object is sterilized by the radiation emitted from the radiation irradiation unit.
5.根据权利要求4所述的菌处理机构，其特征在于，
5.
所述对象物为在其内部收容被收容物并且由遮蔽材料所形成的框体，所述遮蔽材料将所述放射线及穿透性高于所述放射线且由所述放射线副产生的副放射线遮蔽，
The bacteria treatment mechanism according to claim 4, wherein the object is a housing that accommodates an accommodated object therein and is formed of a shielding material that shields the radiation and secondary radiation that has a higher transparency than the radiation and is secondarily generated by the radiation, an exterior of the housing is sterilized by the radiation, and the radiation and the secondary radiation do not penetrate through the accommodated object.
6.根据权利要求4所述的菌处理机构，其特征在于，
6.
所述对象物是利用将内侧保持于无菌状态的无菌保持材料将经遮蔽材料包覆的被收容物包裹而构成，所述遮蔽材料将所述放射线及穿透性高于所述放射线且由所述放射线副产生的副放射线遮蔽，
The bacteria treatment mechanism according to claim 4, wherein the object is configured to wrap an accommodated object covered with a shielding material that shields the radiation and secondary radiation that has a higher transparency than the radiation and is secondarily generated by the radiation, with a sterile maintaining material that maintains the inside in a sterile state, an exterior of the sterile maintaining material is sterilized by the radiation, and the radiation and the secondary radiation do not penetrate through the accommodated object.
7.根据权利要求4所述的菌处理机构，其特征在于，
7.
所述对象物为在其内部收容被收容物且在结构体内部设置包含遮蔽材料的层而形成的容器，所述遮蔽材料将所述放射线及穿透性高于所述放射线且由所述放射线副产生的副放射线遮蔽，
The bacteria treatment mechanism according to claim 4, wherein the object is a container that accommodates an accommodated object therein and is formed by providing a layer made of a shielding material that shields the radiation and secondary radiation that has a higher transparency than the radiation and is secondarily generated by the radiation inside a structure, an exterior of the container is sterilized by the radiation, and the radiation and the secondary radiation do not penetrate through the accommodated object.
8.根据权利要求5至7中任一项所述的菌处理机构，其特征在于，
8.
所述放射线为电子束，所述副放射线为X射线。
The bacteria treatment mechanism according to claim 5, wherein the radiation is an electron beam and the secondary radiation is an X-ray.
9.根据权利要求1至8中任一项所述的菌处理机构，其特征在于包括：
9.
催化剂，将从所述排气管道排气的分子分解。
The bacteria treatment mechanism according to claim 1, wherein a catalyst that decomposes molecules exhausted from the exhaust duct is provided.
10.根据权利要求9所述的菌处理机构，其特征在于，
10.
所述催化剂包括进行过氧化氢的分解的第一催化剂、进行臭氧的分解的第二催化剂中的任一者。
The bacteria treatment mechanism according to claim 9, wherein the catalyst includes one of a first catalyst that decomposes hydrogen peroxide and a second catalyst that decomposes ozone.
11.根据权利要求10所述的菌处理机构，其特征在于包括：
11.
排气切换机构，将已排气至所述排气管道的分子引导至所述第一催化剂或所述第二催化剂中的任一者。
The bacteria treatment mechanism according to claim 10, wherein an exhaust switching mechanism that guides the molecules exhausted to the exhaust duct to either the first catalyst or the second catalyst is provided.
12.根据权利要求9所述的菌处理机构，其特征在于，
12.
所述催化剂进行过氧化氢与臭氧两者的分解。
The bacteria treatment mechanism according to claim 9, wherein the catalyst decomposes both hydrogen peroxide and ozone.
13.根据权利要求1至12中任一项所述的菌处理机构，其特征在于，
13.
所述菌处理部为传递箱。
The bacteria treatment mechanism according to claim 1, wherein the bacteria treatment unit is a pass box.
14.一种菌处理方法，其特征在于包括：
14.