mwirth-epo/epo-nmt-datasets huggingface dataset:
另一方面，触控显示面板10在周边区PR内还包括至少一栅极驱动电路(gate driver circuit)108设置在基板100上，栅极驱动电路108可电连接至集成电路104，并可用以驱动触控显示面板10。
In this embodiment, the gate driver circuit 108 is a two-way scanning driver circuit, and in the shift registers SR( 1)-SR(N), a control end of the thin film transistor M 2 receives the first input signal IN 1, a first end of the thin film transistor M 2 receives the forward input signal FW, and a second end of the thin film transistor M 2 is coupled to the node X(i).
例如，本实施例的触控显示面板10包括两个栅极驱动电路108，其中栅极驱动电路108分别设置在显示区DR在第一方向D1上的两侧，而集成电路104设置在显示区DR在第二方向D2上的一侧，但栅极驱动电路108与控制集成电路104的数量与设置位置都不以上述为限。
A control end of the thin film transistor M 3 receives the second input signal IN 2, a first end of the thin film transistor M 3 receives the backward input signal BW, and a second end of the thin film transistor M 3 is coupled to a second end of the second thin film transistor M 2.
在本实施例中，各条扫描线SL可电连接至一个栅极驱动电路108。
The forward input signal FW and the backward input signal BW have reverse phases in the display period of the touch display panel, that is, when one of the forward input signal FW and the backward input signal BW has a high voltage level, then another one would have a low voltage level.
如图2所示，在相邻的两条扫描线SL中，一条可和位在显示区DR左侧的栅极驱动电路108电连接，而另一条可和位在显示区DR右侧的栅极驱动电路108电连接，但不以此为限。
The term “reverse phases” in the present invention can mean that one of signals has a voltage level greater than a specific voltage level, and the other one of signals has a voltage level less than the specific voltage level.
集成电路104可输出数据信号至数据线DL，并可输出控制信号至栅极驱动电路108，但不以此为限。
In addition, in the embodiment that the gate driver circuit 108 is a one-way scanning driver circuit, the first end of the thin film transistor M 2 receives a high voltage level, and the first end of the thin film transistor M 3 receives a low voltage level.
在某些实施例中，栅极驱动电路108的控制信号也可由其它的控制芯片提供。
In the gate driver circuit shown in FIG. 3, the forward input signal line FWL and the backward input signal line BWL may respectively be replaced by a high voltage level line and a low voltage level line, and the remaining portion is similar to the above description.
此外，在本实施例中，栅极驱动电路108为阵列基板行驱动(Gate driver on Array，GOA)电路结构，但不以此为限。
For example, the “high voltage level” may be a gate high voltage (VGH), and the “low voltage level” may be a gate low voltage (VGL).
在某些实施例中，栅极驱动电路108可制作为芯片后再设置在基板100上，或设置在可挠式或硬式电路板后再电连接至基板100上的连接垫，且所述连接垫电连接扫描线SL。
In the present invention, the “control end”, “first end”, and “second end” of the thin film transistor may respectively represent the gate electrode, the source electrode, and the drain electrode of a thin film transistor, or may respectively represent the gate electrode, the drain electrode, and the source electrode of a thin film transistor.
举例来说，栅极驱动电路108可包括多条控制信号线(例如时钟信号线、起始信号线与结束信号线)，所述控制信号线可通过走线112电连接至集成电路104，以使集成电路104可传送控制信号(例如时钟信号、起始信号与结束信号)至栅极驱动电路108。
If the shift register SR(i) is a first-level shift register or a second-level shift register (that is, i is 1 or 2), then the first input signal IN 1 is the initial signal IS, and the second input signal IN 2 is a (i+2)th-level scan signal OUT(i+2) output by the (i+2)th-level shift register SR(i+2) (that is, the third-level scan signal OUT( 3) or the fourth-level scan signal OUT( 4)).
请参考图3，其为本发明第一实施例的栅极驱动电路的示意图。
If the shift register SR(i) is any one of the shift registers from the third-level shift register to the (N−2)th-level shift register (that is, i is any one of integers from 3 to (N−2)), then the first input signal IN 1 is the (i−2)th-level scan signal OUT(i−2) output by the (i−2)th-level shift register SR(i−2), and the second input signal IN 2 is the (i+2)th-level scan signal OUT(i+2) output by the (i+2)th-level shift register SR(i+2).
以图1或图2中的其中一个栅极驱动电路108为例，栅极驱动电路108包含时钟信号线CL1-CL4、起始信号线IL、结束信号线EL、顺向输入信号线FWL、反向输入信号线BWL和第1级至第N级移位寄存器SR(1)-SR(N)，其中N为大于或等于5的正整数，但不以此为限。
If the shift register SR(i) is a (N−1)th-level shift register or a (N)th-level shift register (that is, i is (N−1) or N), then the first input signal IN 1 is the (i−2)th-level scan signal OUT(i−2) output by the (i−2)th-level shift register SR(i−2) (that is, the (N−3)th-level scan signal OUT(N−3) or the (N−2)th-level scan signal (N−2)), and the second input signal IN 2 is the ending signal ES.
本实施例的第1级至第N级移位寄存器SR(1)-SR(N)可为GOA电路结构，但不以此为限。
It should be noted that, each shift register SR(i) outputs a scan signal OUT(i) to the touch display panel 10 according to the forward input signal FW and the backward input signal BW.
时钟信号线CL1-CL4提供时钟信号CS1-CS4至对应的移位寄存器SR(1)-SR(N)。
When the gate driver circuit 108 is in a forward scanning mode, the forward input signal FW has high voltage level and the backward input signal BW has low voltage level; when the gate driver circuit 108 is in a backward scanning mode, the forward input signal FW has low voltage level and the backward input signal BW has high voltage level.
此外，N可为4的多倍数，而时钟信号线CL1提供时钟信号CS1至第1级移位寄存器SR(1)、第5级移位寄存器SR(5)、…和第(N-3)级移位寄存器SR(N-3)，时钟信号线CL2提供时钟信号CS2至第2级移位寄存器SR(2)、第6级移位寄存器SR(6)、…和第(N-2)级移位寄存器SR(N-2)，时钟信号线CL3提供时钟信号CS3至第3级移位寄存器SR(3)、第7级移位寄存器SR(7)、…和第(N-1)级移位寄存器SR(N-1)，且时钟信号线CL4提供时钟信号CS4至第4级移位寄存器SR(4)、第8级移位寄存器SR(8)、…和第N级移位寄存器SR(N)。
The pull-up unit 116 is coupled to the precharge unit 114 at the node X(i), the pull-up unit 116 receives a clock signal CSN, and the scan signal OUT(i) is output according to the voltage level of the node X(i) and the clock signal CSN, and the clock signal CSN can be any one of the clock signals CS 1-CS 4.
本发明的时钟信号线的数量不限为4条。
In the embodiment where N is a multiple of 4, if i is 1, 5...
此外，各个移位寄存器接收一顺向输入信号FW和一反向输入信号BW。
(N−3), then the clock signal CSN is the clock signal CS 1; if i is 2, 6...
例如，顺向输入信号线FWL与反向输入信号线BWL分别提供顺向输入信号FW与反向输入信号BW至第1级至第N级移位寄存器SR(1)-SR(N)，起始信号线IL提供起始信号IS至第1级和第2级移位寄存器SR(1)、SR(2)，且结束信号线EL提供结束信号ES至第(N-1)级和第N级移位寄存器SR(N-1)、SR(N)。
(N−2), then the clock signal CSN is the clock signal CS 2; if i is 3, 7...
时钟信号线CL1-CL4、起始信号线IL、结束信号线EL、顺向输入信号线FWL和反向输入信号线BWL可耦接一个或多个芯片，也就是时钟信号CS1-CS4、起始信号IS、结束信号ES、顺向输入信号线FWL和反向输入信号线BWL可由此一个或多个芯片提供，例如驱动芯片和/或时序控制芯片等，但不限于此。
(N−1), then the clock signal CSN is the clock signal CS 3; if i is 4, 8...
此外，第1级至第N级移位寄存器SR(1)-SR(N)分别产生第1级至第N级扫描信号OUT(1)-OUT(N)，且扫描信号OUT(1)-OUT(N)可分别输出至与其对应的扫描线SL，并通过扫描线SL驱动与其电连接的像素PX。
The pull-up unit 116 includes a thin film transistor M 1 and a capacitance Cx.
其中，第1级和第2级扫描信号OUT(1)、OUT(2)分别输入至第3级和第4级移位寄存器SR(3)、SR(4)，第(N-1)级和第N级扫描信号OUT(N-1)、OUT(N)分别输入至第(N-3)级和第(N-2)级移位寄存器SR(N-3)、SR(N-2)，而第3级至第(N-2)级扫描信号OUT(3)-OUT(N-2)中的每一扫描信号输入至其上下二级的移位寄存器。
A control end of the thin film transistor M 1 receives a precharge signal, a first end of the thin film transistor M 1 receives the clock signal CSN, and a second end of the thin film transistor M 1 outputs the scan signal OUT(i).
例如，第3级扫描信号OUT(3)输入至第1级和第5级移位寄存器SR(1)、SR(5)。
A first end of the capacitance Cx is coupled to the control end of the thin film transistor M 1, and a second end of the capacitance Cx is coupled to the second end of the thin film transistor M 1.
请参考图4，其为图3的栅极驱动电路中第i级移位寄存器的等效电路图。
FIG. 5 is a timing diagram of the gate driver circuit of FIG. 3 in a forward scanning mode.
如图4所示，第i级(其中i为1至N的正整数)移位寄存器SR(i)包括预充电单元114和上拉单元116，其中预充电单元114和上拉单元116的一端耦接于节点X(i)，而上拉单元116的另外一端可输出第i级扫描信号OUT(i)至对应的扫描线SL。
In order to make the drawing more simplified and easy to understand, FIG. 5 shows a portion of the operation of signals in one frame time FR, and FIG. 5 shows the operation of a portion of signals related to the first-level shift register SR( 1) to the eighteenth-level shift register SR( 18).
预充电单元114用以接收第一输入信号IN1和第二输入信号IN2，且依据第一输入信号IN1和第二输入信号IN2控制节点X(i)的电势。
As shown in FIG. 5, at least one first period PD 1 and at least one second period PD 2 are included in one frame time FR, the touch display panel 10 performs touch sensing in the first period PD 1, and the touch display panel 10 is driven to display in the second period PD 2.
预充电单元114包含薄膜晶体管M2、M3。
For example, the frame time FR may include a plurality of first periods PD 1 and a plurality of second periods PD 2 arranged alternately, but not limited thereto.
在本实施例中，栅极驱动电路108为双向扫描的驱动电路，而在这些移位寄存器SR(1)-SR(N)中，薄膜晶体管M2的控制端接收第一输入信号IN1，薄膜晶体管M2的第一端接收顺向输入信号FW，且薄膜晶体管M2的第二端耦接节点X(i)。
In addition, the gate driver circuit 108 of this embodiment can be operated in the forward scanning mode, for example, the forward input signal FW can have high voltage level (such as VGH) and the backward input signal BW can have low voltage level (such as VGL) in the second period PD 2.
薄膜晶体管M3的控制端接收第二输入信号IN2，薄膜晶体管M3的第一端接收反向输入信号BW，薄膜晶体管M3的第二端耦接薄膜晶体管M2的第二端，其中顺向输入信号FW与反向输入信号BW在触控显示面板的显示期间互为反相位，也就是当顺向输入信号FW与反向输入信号BW中的一者为高电势(high voltage level)时，另一者则为低电势(low voltage level)。
That is, the forward input signal FW and the backward input signal BW provided to the shift register SR(i) have reverse phases (e.g., VGL and VGH) in the second period PD 2, but not limited thereto.
此外，在栅极驱动电路108为单向扫描的驱动电路实施例中，薄膜晶体管M2的第一端接收一高电势，且薄膜晶体管M3的第一端接收一低电势，并且在图3的栅极驱动电路示意图中，顺向输入信号线FWL和反向输入信号线BWL可分别置换为高电势线与低电势线。
Taking the node X( 1) of the first-level shift register SR( 1) and the node X( 3) of the third-level shift register SR( 3) in FIG. 5 as an example (referring to FIG. 3 and FIG. 4 together), when the initial signal IS rises from low voltage level to high voltage level at a time t 0, the voltage level of the node X( 1) changes from a reference voltage level VL 0 to a first voltage level VL 1 according to the initial signal IS (the first input signal IN 1).
举例来说，所述高电势可为栅极高电势(Gate High Voltage，VGH)，而所述低电势可为栅极低电势(Gate Low Voltage，VGL)。
At a time t 2, the clock signal CS 1 rises from low voltage level to high voltage level, and the voltage level of the node X( 1) changes from the first voltage level VL 1 to a second voltage level VL 2 according to the clock signal CS 1.
在本文中，薄膜晶体管的“控制端”、“第一端”和“第二端”分别是指薄膜晶体管的栅极、源极和漏极，或者分别是指薄膜晶体管的栅极、漏极和源极。
At this time, the first-level shift register SR( 1) outputs the first-level scan signal OUT( 1) to the corresponding scan line SL according to the voltage level of the node X( 1) and the clock signal CS 1, and the voltage level of the node X( 3) rises from the reference voltage level VL 0 to the first voltage level VL 1 according to the first-level scan signal OUT( 1).
若移位寄存器SR(i)为第1级或第2级移位寄存器(即i为1或2)，则第一输入信号IN1为起始信号IS，且第二输入信号IN2为第(i+2)级移位寄存器SR(i+2)输出的扫描信号OUT(i+2)(即第3级扫描信号OUT(3)或第4级扫描信号OUT(4))。
At a time t 4, the clock signal CS 1 drops from high voltage level to low voltage level, and the clock signal CS 3 rises from low voltage level to high voltage level.
若移位寄存器SR(i)为第3级至第(N-2)级移位寄存器中的任一移位寄存器(即i为3至(N-2)中的任一正整数)，则第一输入信号IN1为第(i-2)级移位寄存器SR(i-2)输出的第(i-2)级扫描信号OUT(i-2)，且第二输入信号IN2为第(i+2)级移位寄存器SR(i+2)输出的第(i+2)级扫描信号OUT(i+2)。
At this time, the voltage level of the node X( 3) rises from the first voltage level VL 1 to the second voltage level VL 2 according to the clock signal CS 3, causing the third-level shift register SR( 3) to output the third-level scan signal OUT( 3) to the corresponding scan line SL.
若移位寄存器SR(i)为第(N-1)级或第N级移位寄存器(即i为(N-1)或N)，则第一输入信号IN1为第(i-2)级移位寄存器SR(i-2)输出的扫描信号OUT(i-2)(即第(N-3)级扫描信号OUT(N-3)或第(N-2)级扫描信号OUT(N-2))，且第二输入信号IN2为结束信号ES。
Meanwhile, the initial signal IS serving as the first input signal IN 1 of the first-level shift register SR( 1) has dropped back to low voltage level, and the third-level scan signal OUT( 3) serving as the second input signal IN 2 is input to the first-level shift register SR( 1), so that the voltage level of the node X( 1) is changed from the second voltage level VL 2 to the reference voltage level VL 0, and the first-level shift register SR( 1) stops outputting the first-level scan signal OUT( 1) to the corresponding scan line SL.
需说明的是，各个移位寄存器SR(i)依据顺向输入信号FW和反向输入信号BW依序输出一扫描信号OUT(i)至触控显示面板10。
The period between the time t 0 and the time t 4 can be regarded as the time when the first-level shift register SR( 1) outputs the first-level scan signal OUT( 1) to drive the corresponding scan line SL.
当栅极驱动电路108为顺向扫描时，顺向输入信号FW为高电势且反向输入信号BW为低电势；而当栅极驱动电路108为反向扫描时，顺向输入信号FW为低电势且反向输入信号BW为高电势。
The second voltage level VL 2 may be greater than the first voltage level VL 1 and the reference voltage level VL 0, and the first voltage level VL 1 may be greater than the reference voltage level VL 0, but not limited thereto.
上拉单元116和预充电单元114耦接在节点X(i)，上拉单元116接收时钟信号CSN，并依据节点X(i)的电势和时钟信号CSN输出扫描信号OUT(i)，其中时钟信号CSN为时钟信号CS1-CS4中的任一个。
The above operation method of the shift registers can be applied to the shift registers SR( 1)-SR( 6) and SR( 11)-SR( 14) in FIG. 5.
在N为4的多倍数的实施例中，若i为1、5、…、(N-3)，则时钟信号CSN为时钟信号CS1；若i为2、6、…、(N-2)，则时钟信号CSN为时钟信号CS2；若i为3、7、…、(N-1)，则时钟信号CSN为时钟信号CS3；若i为4、8、…、N，则时钟信号CSN为时钟信号CS4。
The above mentioned shift registers (SR( 1)-SR( 6) and SR( 11)-SR( 14)) are not the shift registers which the nodes X(i) have the second voltage level VL 2 in the first period PD 1 (such as SR( 9), SR( 10), SR( 17), and SR( 18) in FIG. 5 ) and the shift registers that are two levels less than these shift registers (such as SR( 7), SR( 8), SR( 15), and SR( 16) in FIG. 5 ), but not limited thereto.
上拉单元116包括薄膜晶体管M1和电容Cx。
In another aspect, the forward input signal FW and the backward input signal BW provided to the shift register SR(i) are in phase in the first period PD 1.
薄膜晶体管M1的控制端接收预充电信号，薄膜晶体管M1的第一端接收时钟信号CSN，且薄膜晶体管M1的第二端输出扫描信号OUT(i)。
As shown in FIG. 5, the forward input signal FW and the backward input signal BW provided to the shift register SR(i) are in phase at least twice in one frame time FR in this embodiment, but not limited thereto.
电容Cx的第一端耦接薄膜晶体管M1的控制端，且电容Cx的第二端耦接薄膜晶体管M1的第二端。
In some embodiment, the forward input signal FW and the backward input signal BW may be in phase three times or more than three times in one frame time FR.
图5为图3的栅极驱动电路在顺向扫描时的时序图，为方便说明，图5只示出一个图帧时间FR内的一部分的时序变化，且图5示出和第1级至第18级移位寄存器SR(1)-SR(18)相关的部分信号的时序变化。
In some embodiments, the forward input signal FW and the backward input signal BW may be in phase once in a frame time FR.
如图5所示，在一图帧时间FR内具有至少一第一时段PD1和至少一第二时段PD2，在第一时段PD1内，触控显示面板10进行触控感测，且在第二时段PD2内，触控显示面板10进行显示驱动。
Specifically, the backward input signal BW has a first reference voltage level VR 1 in the first period PD 1 and a second reference voltage level VR 2 in the second period PD 2, and the first reference voltage level VR 1 is different from the second reference voltage level VR 2.
此外，本实施例的栅极驱动电路108可为顺向扫描，例如在第二时段PD2内，顺向输入信号FW为高电势(如VGH)且反向输入信号BW为低电势(如VGL)，换言之，在第二时段PD2内输入移位寄存器SR(i)的顺向输入信号FW和反向输入信号BW具有反相位，但不以此为限。
The first reference voltage level VR 1 may be greater than the second reference voltage level VR 2, for example, the first reference voltage level VR 1 may be VGH and the second reference voltage level VR 2 may be VGL, but not limited thereto.
也就是说，抗刻蚀层105位于层间介质层104与源漏掺杂区103之间、以及层间介质层104和伪栅结构102之间。
That is to say, the anti-etching layer 105 is located between the interlayer dielectric layer 104 and the source-drain doped region 103, and between the interlayer dielectric layer 104 and the pseudo-gate structure 102.
后续对抗刻蚀层105进行离子掺杂在源漏掺杂区103中形成第一掺杂区的过程中，抗刻蚀层105能够削弱掺杂离子的能量，避免掺杂离子的注入能量过大对源漏掺杂区103的晶格造成过大损伤，导致后续掺杂离子在晶格缺陷中快速扩散至鳍部101中的沟道区中，在半导体结构工作时，源漏掺杂区103的源极和漏极的耗尽层易扩展，导致短沟道效应较严重。
In the subsequent process of performing ion doping on the anti-etching layer 105 to form the first doped region in the source-drain doped region 103, the anti-etching layer 105 can weaken the energy of doping ions and prevent the lattice of the source-drain doped region 103 from being excessively damaged due to excessive implantation energy of doping ions, resulting in subsequent rapid diffusion of doping ions in lattice defects into the channel region in the fin 101, and when the semiconductor structure works, the source and drain depletion layers of the source-drain doped region 103 are easily expanded, resulting in serious short-channel effects.
另外，抗刻蚀层105在后续刻蚀层间介质层104形成开口的过程中，定义刻蚀工艺刻蚀停止的位置，从而保障降低刻蚀工艺对源漏掺杂区103造成过刻蚀的概率。
In addition, in the subsequent etching of the interlayer dielectric layer 104 to form an opening, the anti-etching layer 105 defines the etch stop position of the etching process, so as to reduce the probability of over-etching of the source-drain doped region 103 caused in the etching process.
所述抗刻蚀层105的材料采用低K介电常数的材料。
The material of the anti-etching layer 105 is a material with a low-K dielectric constant.
所述抗刻蚀层105的材料包括：SiON、SiBCN、SiCN、掺杂碳的SiN和掺杂氧的SiN中的一种或多种。
The material of the anti-etching layer 105 includes one or more of SiON, SiBCN, SiCN, carbon-doped SiN and oxygen-doped SiN.
本实施例中，所述抗刻蚀层105的材料为掺杂碳的SiN或掺杂氧的SiN。
In some implementations, the material of the anti-etching layer 105 is carbon-doped SiN or oxygen-doped SiN.
所述抗刻蚀层105的材料采用低K介电常数的材料，因此，所述抗刻蚀层105的材料除了有抗刻蚀的作用还能够起到减小源漏掺杂区103和后续形成的栅极结构电容耦合效应的作用。
Because the material of the anti-etching layer 105 is a material with a low-K dielectric constant, the material of the anti-etching layer 105 not only has the anti-etching effect, but also can reduce the capacitive coupling effect of the source-drain doped region 103 and the subsequent gate structure.
抗刻蚀层105不宜过厚也不宜过薄。
The anti-etching layer 105 should not be too thick or too thin.
若抗刻蚀层105过厚，在后续形成第一掺杂区的过程中，离子不易穿过抗刻蚀层105，导致形成的第一掺杂区的掺杂浓度过低且区域过小，不利于减小接触孔插塞与源漏掺杂区103的接触电阻。
If the anti-etching layer 105 is too thick, it is not easy for ions to pass through the anti-etching layer 105 during the subsequent formation of the first doped region, resulting in that the doping concentration of the first doped region is too low and the region is too small, which is not beneficial to reducing the contact resistance between the contact hole plug and the source-drain doped region 103.
若抗刻蚀层105过薄，后续形成第一掺杂区的过程中，易对源漏掺杂区103的晶格造成损伤，掺杂离子易在晶格缺陷中快速扩散至鳍部101中的沟道区中，在半导体结构工作时，源漏掺杂区103的源极和漏极的耗尽层易扩展，导致短沟道效应较严重。
If the anti-etching layer 105 is too thin, it is easy to damage the lattice of the source-drain doped region 103 in the subsequent formation of the first doped region, doping ions are easy to diffuse rapidly into the channel region in the fin 101 in the lattice defects, and when the semiconductor structure works, the source and drain depletion layers of the source-drain doped region 103 are easily expanded, resulting in serious short-channel effects.
本实施例中，抗刻蚀层105的厚度为2纳米至6纳米。
In some implementations, the thickness of the anti-etching layer 105 is 2 nanometers to 6 nanometers.
如图5所示，去除所述伪栅结构102，在所述伪栅结构102处形成栅极结构材料层(图中未示出)；回刻蚀部分厚度的所述栅极结构材料层，形成栅极结构106和位于所述栅极结构106上的凹槽；在所述凹槽中形成掩膜层107。
As illustrated in FIG. 5, the pseudo-gate structure 102 is removed, and a gate structure material layer (not shown) is formed at the pseudo-gate structure 102; the gate structure material layer is back-etched for part of the thickness to form a gate structure 106 and a groove on the gate structure 106; and a mask layer 107 is formed in the groove.
所述栅极结构106用于在半导体结构工作时控制沟道的开启与断开。
The gate structure 106 is used for controlling the connection and disconnection of the channel when the semiconductor structure works.
本实施例中，栅极结构106包括保形覆盖鳍部101的部分顶面和部分侧壁的栅介质层1061和位于栅介质层1061上的金属栅极层1062。
In some implementations, the gate structure 106 includes a gate dielectric layer 1061 covering part of the top surface and part of a sidewall of the fin 101 conformally and a metal gate layer 1062 over the gate dielectric layer 1061.
栅介质层1061的材料为高k介质层，高k介质层的材料是指相对介电常数大于氧化硅相对介电常数的介质材料。
The material of high-k dielectric layer refers to the dielectric material with a relative dielectric constant greater than the relative dielectric constant of silicon oxide.
金属栅极层1062作为电极，用于实现与外部电路的电连接。
The metal gate layer 1062 is used as an electrode for realizing the electrical connection with an external circuit.
在本实施例中，金属栅极层1062的材料为镁钨合金。
In some implementations, the material of the metal gate layer 1062 is magnesium tungsten alloy.
所述掩膜层107用于在后续制程中保护栅极结构106。
The mask layer 107 is used for protecting the gate structure 106 in the subsequent manufacturing process.
具体的，掩膜层107的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。
Specifically, the material of the mask layer 107 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carboxynitride, silicon oxynitride, boron nitride and boron carbonitride.
本实施例中，掩膜层107的材料包括氮化硅。
In some implementations, the material of the mask layer 107 includes silicon nitride.
参考图6，刻蚀层间介质层104，形成露出所述源漏掺杂区103的开口108。
Referring to FIG. 6, the interlayer dielectric layer 104 is etched to form an opening 108 that exposes the source-drain doped region 103.
所述开口108定义后续第一掺杂区和第二掺杂区的掺杂区域。
The opening 108 defines the doped region of the subsequent first doped region and the second doped region.
另外，所述开口108为后续填充与源漏掺杂区103连接的接触孔插塞做准备。
In addition, the opening 108 is prepared for subsequent filling of the contact hole plug connected with the source-drain doped region 103.
本实施例中，所述开口108露出所述源漏掺杂区103是指，所述开口108露出抗刻蚀层105。
In some implementations, the opening 108 exposing the source-drain doped region 103 refers to that the opening 108 exposes the anti-etching layer 105.
形成露出所述源漏掺杂区103的开口108的步骤中，以所述抗刻蚀层105为刻蚀停止层刻蚀所述层间介质层104。
In the step of forming the opening 108 that exposes the source-drain doped region 103, the interlayer dielectric layer 104 is etched by taking the anti-etching layer 105 as an etch stop layer.
本实施例中，采用干法刻蚀工艺刻蚀所述层间介质层104，形成露出所述源漏掺杂区103的开口108。
In some implementations, the interlayer dielectric layer 104 is etched by adopting a dry etching process to form the opening 108 that exposes the source-drain doped region 103.
干法刻蚀工艺为各向异性刻蚀工艺，具有较好的刻蚀剖面控制性，降低对其他膜层结构的损伤，有利于使开口108的形貌满足工艺需求，提高开口108的形成效率，且干法刻蚀工艺在刻蚀过程中能够以抗刻蚀层105为刻蚀停止层，使得刻蚀停止位置易于控制。
Dry etching process is an anisotropic etching process, which has better controllability of etching profile, reduces damage to other film structures, is beneficial to making the morphology of the opening 108 meet the technological requirements and improves the formation efficiency of the opening 108.
所述半导体结构的形成方法还包括：在提供基底后，形成开口108前，形成覆盖所述栅极结构106和层间介质层104的介电层111。
The method for forming the semiconductor structure further includes: after providing the base and before forming the opening 108, forming a dielectric layer 111 covering the gate structure 106 and the interlayer dielectric layer 104.
所述介电层111用于实现相邻器件之间的电隔离，所述介电层111的材料为绝缘材料。
The dielectric layer 111 is used for realizing electrical isolation between adjacent devices, and the material of the dielectric layer 111 is an insulating material.
本实施例中，所述介电层111的材料为氧化硅。
In some implementations, the material of the dielectric layer 111 is silicon oxide.
需要说明的是，在刻蚀层间介质层104，形成开口108的过程中，刻蚀产生的聚合物杂质积累在开口108的底部，导致底部的层间介质层104不易被刻蚀，进而在垂直于栅极结构106的延伸方向上，所述开口108的顶部尺寸大于所述开口108底部的尺寸，也就是说，所述开口108呈倒梯形。
It should be noted that, in the process of etching the interlayer dielectric layer 104 to form the opening 108, the polymer impurities produced by etching accumulate at the bottom of the opening 108, which makes the interlayer dielectric layer 104 at the bottom not easy to be etched, and in the extension direction perpendicular to the gate structure 106, the size of the top of the opening 108 is larger than the size of the bottom of the opening 108, that is, the opening 108 is in the shape of an inverted trapezoid.
参考图7和图8，在所述开口108露出的所述源漏掺杂区103中形成第一掺杂区109和位于所述第一掺杂区109上的第二掺杂区110(如图8所示)，所述第二掺杂区110在基底上的投影覆盖所述第一掺杂区109在所述基底上的投影，且所述第一掺杂区109、第二掺杂区110以及源漏掺杂区103的掺杂离子类型相同，所述第一掺杂区109和第二掺杂区110的掺杂离子浓度大于所述源漏掺杂区103的掺杂离子浓度。
Referring to FIG. 7 and FIG. 8, a first doped region 109 and a second doped region 110 over the first doped region 109 are formed in the source-drain doped region 103 exposed by the opening 108 (as shown in FIG. 8 ), the projection of the second doped region 110 on the base covers the projection of the first doped region 109 on the base, the doping ion types of the first doped region 109, the second doped region 110 and the source-drain doped region 103 are the same, and the ion doping concentration of the first doped region 109 and the second doped region 110 is higher than the ion doping concentration of the source-drain doped region 103.
本实施例中第二掺杂区110位于第一掺杂区109上，且第二掺杂区110在基底上的投影覆盖第一掺杂区109在基底上的投影，第一掺杂区109和第二掺杂区110的掺杂离子类型与源漏掺杂区103的掺杂离子类型相同，且第一掺杂区109和第二掺杂区110的掺杂浓度均比源漏掺杂区103的掺杂浓度高。
In some implementations, the second doped region 110 is located over the first doped region 109, the projection of the second doped region 110 on the base covers the projection of the first doped region 109 on the base, the doping ion types of the first doped region 109 and the second doped region 110 are the same as the doping ion type of the source-drain doped region 103, and the doping concentration of the first doped region 110 and the second doped region is higher than the doping concentration of the source-drain doping 103.