40.2.2. Setting Events to Monitor Most processors contain counters , which are used by OProfile to monitor specific events. As shown in Table 40.2, "OProfile Processors and Counters" , the number of counters available depends on the processor. Table 40.2. OProfile Processors and Counters Processor cpu_type Number of Counters Pentium Pro i386/ppro 2 Pentium II i386/pii 2 Pentium III i386/piii 2 Pentium 4 (non-hyper-threaded) i386/p4 8 Pentium 4 (hyper-threaded) i386/p4-ht 4 Athlon i386/athlon 4 AMD64 x86-64/hammer 4 Itanium ia64/itanium 4 Itanium 2 ia64/itanium2 4 TIMER_INT timer 1 IBM eServer iSeries and pSeries timer 1 ppc64/power4 8 ppc64/power5 6 ppc64/970 8 IBM eServer S/390 and S/390x timer 1 IBM eServer zSeries timer 1 Use Table 40.2, "OProfile Processors and Counters" to verify that the correct processor type was detected and to determine the number of events that can be monitored simultaneously. timer is used as the processor type if the processor does not have supported performance monitoring hardware. If timer is used, events cannot be set for any processor because the hardware does not have support for hardware performance counters. Instead, the timer interrupt is used for profiling. If timer is not used as the processor type, the events monitored can be changed, and counter 0 for the processor is set to a time-based event by default. If more than one counter exists on the processor, the counters other than counter 0 are not set to an event by default. The default events monitored are shown in Table 40.3, "Default Events" . Table 40.3. Default Events Processor Default Event for Counter Description Pentium Pro, Pentium II, Pentium III, Athlon, AMD64 CPU_CLK_UNHALTED The processor's clock is not halted Pentium 4 (HT and non-HT) GLOBAL_POWER_EVENTS The time during which the processor is not stopped Itanium 2 CPU_CYCLES CPU Cycles TIMER_INT (none) Sample for each timer interrupt ppc64/power4 CYCLES Processor Cycles ppc64/power5 CYCLES Processor Cycles ppc64/970 CYCLES Processor Cycles The number of events that can be monitored at one time is determined by the number of counters for the processor. However, it is not a one-to-one correlation; on some processors, certain events must be mapped to specific counters. To determine the number of counters available, execute the following command: The events available vary depending on the processor type. To determine the events available for profiling, execute the following command as root (the list is specific to the system's processor type): The events for each counter can be configured via the command line or with a graphical interface. For more information on the graphical interface, refer to Section 40.8, "Graphical Interface" . If the counter cannot be set to a specific event, an error message is displayed. To set the event for each configurable counter via the command line, use opcontrol : Replace <event-name> with the exact name of the event from op_help , and replace <sample-rate> with the number of events between samples. 40.2.2.1. Sampling Rate By default, a time-based event set is selected. It creates a sample every 100,000 clock cycles per processor. If the timer interrupt is used, the timer is set to whatever the jiffy rate is and is not user-settable. If the cpu_type is not timer , each event can have a sampling rate set for it. The sampling rate is the number of events between each sample snapshot. When setting the event for the counter, a sample rate can also be specified: Replace <sample-rate> with the number of events to wait before sampling again. The smaller the count, the more frequent the samples. For events that do not happen frequently, a lower count may be needed to capture the event instances. Warning Be extremely careful when setting sampling rates. Sampling too frequently can overload the system, causing the system to appear as if it is frozen or causing the system to actually freeze.

Commands:
cat /dev/oprofile/cpu_type
op_help
opcontrol --event= <event-name> : <sample-rate>
opcontrol --event= <event-name> : <sample-rate>