The transceivers for Xilinx and Altera use slightly different gear boxes when they ingest 16 streams of data, turn them into 640 bits, and balance this with clock speed. Narrow is better, so 512 bits is an ideal number because it is a binary multiple, but in this case, the controller would have to process at almost 450 MHz, which runs the clock rate too fast. 650 bits, on the other hand, is as narrow as possible without running the clock rate too fast. 1024 bits, which OpenSilicon ran for a while, is too wide and too slow, causing more problems than it solves. Also, 512 bits sounds ideal, but it doesn’t work with the packet sizes. For example, the biggest packet, which is 128 bytes would be 8 flits, plus the header and tail, which is 9 flits, which does not divide into 512 bits cleanly.