The high frequency clock HFCLK is used for the encoding the audio signal in S/PDIF transmitter. So, the transmitter needs to be configured for an over-sampling ratio of 256 x FS. Hence, for a specific frame sync (FS) frequency, HFCLK should be 256 x FS, and the bit-clock should be 64 x FS.
For Example: Sampling frequency: 192KHz HFCLK    : 256 x FS = 256*192KHz = 49.152MHz Bit clock   : 64 x FS = 64*192KHz = 12.288 MHz
Accordingly, have to configure for different sampling frequency.
For more information, please refer application note(EE-266) which discusses briefly about SPDIF. The link is given below. https://www.analog.com/media/en/technical-documentation/application-notes/ee.266.rev.2.08.07.pdf