By programming CHx_SYNC_OFFSET registers, the signals of each channel can be delayed a certain number of modulator clocks.
The best way to approach the phase offset calibration is to find out which channel is the one with higher phase delay and set its register CHx_SYNC_OFFSET=0. Any other channel with lower phase mut be delayed until they are compensated.
At a given N (decimation rate), the maximum allowed phase delay that can be set is N-1. If a value greater that N-1 is set, it will be automatically changed to N-1.
The programmed delay is the value set in CHx_SYNC_OFFSET multiplied by a factor which depends on the decimation Rate.