For a state measurement the logic analyzer is clocked by a signal from the system under test. At every valid clock, the logic analyzer takes a snapshot of the system under test. This snapshot (sample) is clocked by the system so the measurements are synchronous with the system under test.
For a timing measurement, the logic analyzer samples data at regular intervals (500ps*-50ms) chosen in the clocking setup. This internal clock is not related to the system under test so the measurements are asynchronous to the system under test.
*See TLA module specifications for the minimum Deep Memory Timing