The ICM7240 generates timing delays based on the open-drain outputs of pins 1-8. Each open-drain output multiplies the reference period (i.e. TB I/O or RC) by a multiple of 2 and is driven with a 50% duty cycle. For example, Pin1 = T*2, Pin2 = T*4, Pin3 = T*8, etc., where T is the reference period. Open-drain outputs (Pins 1-8) are in parallel when external switches close, which results in an AND function between parallel switches. Figure 3 of the datasheet demonstrates an application circuit for a programmable frequency divider (datasheet attached), based on the configuration of pins 1-8. The configuration of pins 1-8 corresponds to a binary value, where pin 1 is the LSB. To configure a divide value of 3 (N=3), you would need to close switches 1 and 2. To configure a divide value of 5 (N=5), you would need to close switches 1 and 3. Switches that are left open have no effect on the output; thus, if all switches are left open, the output would remain high and will not oscillate.